1 //===-- AArch64MCTargetDesc.cpp - AArch64 Target Descriptions ---*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file provides AArch64 specific target descriptions.
11 //
12 //===----------------------------------------------------------------------===//
13
14 #include "AArch64MCTargetDesc.h"
15 #include "AArch64ELFStreamer.h"
16 #include "AArch64MCAsmInfo.h"
17 #include "AArch64WinCOFFStreamer.h"
18 #include "InstPrinter/AArch64InstPrinter.h"
19 #include "MCTargetDesc/AArch64AddressingModes.h"
20 #include "llvm/MC/MCAsmBackend.h"
21 #include "llvm/MC/MCCodeEmitter.h"
22 #include "llvm/MC/MCInstrAnalysis.h"
23 #include "llvm/MC/MCInstrInfo.h"
24 #include "llvm/MC/MCObjectWriter.h"
25 #include "llvm/MC/MCRegisterInfo.h"
26 #include "llvm/MC/MCStreamer.h"
27 #include "llvm/MC/MCSubtargetInfo.h"
28 #include "llvm/Support/Endian.h"
29 #include "llvm/Support/ErrorHandling.h"
30 #include "llvm/Support/TargetRegistry.h"
31
32 using namespace llvm;
33
34 #define GET_INSTRINFO_MC_DESC
35 #define GET_INSTRINFO_MC_HELPERS
36 #include "AArch64GenInstrInfo.inc"
37
38 #define GET_SUBTARGETINFO_MC_DESC
39 #include "AArch64GenSubtargetInfo.inc"
40
41 #define GET_REGINFO_MC_DESC
42 #include "AArch64GenRegisterInfo.inc"
43
createAArch64MCInstrInfo()44 static MCInstrInfo *createAArch64MCInstrInfo() {
45 MCInstrInfo *X = new MCInstrInfo();
46 InitAArch64MCInstrInfo(X);
47 return X;
48 }
49
50 static MCSubtargetInfo *
createAArch64MCSubtargetInfo(const Triple & TT,StringRef CPU,StringRef FS)51 createAArch64MCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
52 if (CPU.empty())
53 CPU = "generic";
54
55 return createAArch64MCSubtargetInfoImpl(TT, CPU, FS);
56 }
57
initLLVMToCVRegMapping(MCRegisterInfo * MRI)58 void AArch64_MC::initLLVMToCVRegMapping(MCRegisterInfo *MRI) {
59 for (unsigned Reg = AArch64::NoRegister + 1;
60 Reg < AArch64::NUM_TARGET_REGS; ++Reg) {
61 unsigned CV = MRI->getEncodingValue(Reg);
62 MRI->mapLLVMRegToCVReg(Reg, CV);
63 }
64 }
65
createAArch64MCRegisterInfo(const Triple & Triple)66 static MCRegisterInfo *createAArch64MCRegisterInfo(const Triple &Triple) {
67 MCRegisterInfo *X = new MCRegisterInfo();
68 InitAArch64MCRegisterInfo(X, AArch64::LR);
69 AArch64_MC::initLLVMToCVRegMapping(X);
70 return X;
71 }
72
createAArch64MCAsmInfo(const MCRegisterInfo & MRI,const Triple & TheTriple)73 static MCAsmInfo *createAArch64MCAsmInfo(const MCRegisterInfo &MRI,
74 const Triple &TheTriple) {
75 MCAsmInfo *MAI;
76 if (TheTriple.isOSBinFormatMachO())
77 MAI = new AArch64MCAsmInfoDarwin();
78 else if (TheTriple.isWindowsMSVCEnvironment())
79 MAI = new AArch64MCAsmInfoMicrosoftCOFF();
80 else if (TheTriple.isOSBinFormatCOFF())
81 MAI = new AArch64MCAsmInfoGNUCOFF();
82 else {
83 assert(TheTriple.isOSBinFormatELF() && "Invalid target");
84 MAI = new AArch64MCAsmInfoELF(TheTriple);
85 }
86
87 // Initial state of the frame pointer is SP.
88 unsigned Reg = MRI.getDwarfRegNum(AArch64::SP, true);
89 MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(nullptr, Reg, 0);
90 MAI->addInitialFrameState(Inst);
91
92 return MAI;
93 }
94
createAArch64MCInstPrinter(const Triple & T,unsigned SyntaxVariant,const MCAsmInfo & MAI,const MCInstrInfo & MII,const MCRegisterInfo & MRI)95 static MCInstPrinter *createAArch64MCInstPrinter(const Triple &T,
96 unsigned SyntaxVariant,
97 const MCAsmInfo &MAI,
98 const MCInstrInfo &MII,
99 const MCRegisterInfo &MRI) {
100 if (SyntaxVariant == 0)
101 return new AArch64InstPrinter(MAI, MII, MRI);
102 if (SyntaxVariant == 1)
103 return new AArch64AppleInstPrinter(MAI, MII, MRI);
104
105 return nullptr;
106 }
107
createELFStreamer(const Triple & T,MCContext & Ctx,std::unique_ptr<MCAsmBackend> && TAB,std::unique_ptr<MCObjectWriter> && OW,std::unique_ptr<MCCodeEmitter> && Emitter,bool RelaxAll)108 static MCStreamer *createELFStreamer(const Triple &T, MCContext &Ctx,
109 std::unique_ptr<MCAsmBackend> &&TAB,
110 std::unique_ptr<MCObjectWriter> &&OW,
111 std::unique_ptr<MCCodeEmitter> &&Emitter,
112 bool RelaxAll) {
113 return createAArch64ELFStreamer(Ctx, std::move(TAB), std::move(OW),
114 std::move(Emitter), RelaxAll);
115 }
116
createMachOStreamer(MCContext & Ctx,std::unique_ptr<MCAsmBackend> && TAB,std::unique_ptr<MCObjectWriter> && OW,std::unique_ptr<MCCodeEmitter> && Emitter,bool RelaxAll,bool DWARFMustBeAtTheEnd)117 static MCStreamer *createMachOStreamer(MCContext &Ctx,
118 std::unique_ptr<MCAsmBackend> &&TAB,
119 std::unique_ptr<MCObjectWriter> &&OW,
120 std::unique_ptr<MCCodeEmitter> &&Emitter,
121 bool RelaxAll,
122 bool DWARFMustBeAtTheEnd) {
123 return createMachOStreamer(Ctx, std::move(TAB), std::move(OW),
124 std::move(Emitter), RelaxAll, DWARFMustBeAtTheEnd,
125 /*LabelSections*/ true);
126 }
127
128 static MCStreamer *
createWinCOFFStreamer(MCContext & Ctx,std::unique_ptr<MCAsmBackend> && TAB,std::unique_ptr<MCObjectWriter> && OW,std::unique_ptr<MCCodeEmitter> && Emitter,bool RelaxAll,bool IncrementalLinkerCompatible)129 createWinCOFFStreamer(MCContext &Ctx, std::unique_ptr<MCAsmBackend> &&TAB,
130 std::unique_ptr<MCObjectWriter> &&OW,
131 std::unique_ptr<MCCodeEmitter> &&Emitter, bool RelaxAll,
132 bool IncrementalLinkerCompatible) {
133 return createAArch64WinCOFFStreamer(Ctx, std::move(TAB), std::move(OW),
134 std::move(Emitter), RelaxAll,
135 IncrementalLinkerCompatible);
136 }
137
138 namespace {
139
140 class AArch64MCInstrAnalysis : public MCInstrAnalysis {
141 public:
AArch64MCInstrAnalysis(const MCInstrInfo * Info)142 AArch64MCInstrAnalysis(const MCInstrInfo *Info) : MCInstrAnalysis(Info) {}
143
evaluateBranch(const MCInst & Inst,uint64_t Addr,uint64_t Size,uint64_t & Target) const144 bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size,
145 uint64_t &Target) const override {
146 // Search for a PC-relative argument.
147 // This will handle instructions like bcc (where the first argument is the
148 // condition code) and cbz (where it is a register).
149 const auto &Desc = Info->get(Inst.getOpcode());
150 for (unsigned i = 0, e = Inst.getNumOperands(); i != e; i++) {
151 if (Desc.OpInfo[i].OperandType == MCOI::OPERAND_PCREL) {
152 int64_t Imm = Inst.getOperand(i).getImm() * 4;
153 Target = Addr + Imm;
154 return true;
155 }
156 }
157 return false;
158 }
159
160 std::vector<std::pair<uint64_t, uint64_t>>
findPltEntries(uint64_t PltSectionVA,ArrayRef<uint8_t> PltContents,uint64_t GotPltSectionVA,const Triple & TargetTriple) const161 findPltEntries(uint64_t PltSectionVA, ArrayRef<uint8_t> PltContents,
162 uint64_t GotPltSectionVA,
163 const Triple &TargetTriple) const override {
164 // Do a lightweight parsing of PLT entries.
165 std::vector<std::pair<uint64_t, uint64_t>> Result;
166 for (uint64_t Byte = 0, End = PltContents.size(); Byte + 7 < End;
167 Byte += 4) {
168 uint32_t Insn = support::endian::read32le(PltContents.data() + Byte);
169 // Check for adrp.
170 if ((Insn & 0x9f000000) != 0x90000000)
171 continue;
172 uint64_t Imm = (((PltSectionVA + Byte) >> 12) << 12) +
173 (((Insn >> 29) & 3) << 12) + (((Insn >> 5) & 0x3ffff) << 14);
174 uint32_t Insn2 = support::endian::read32le(PltContents.data() + Byte + 4);
175 // Check for: ldr Xt, [Xn, #pimm].
176 if (Insn2 >> 22 == 0x3e5) {
177 Imm += ((Insn2 >> 10) & 0xfff) << 3;
178 Result.push_back(std::make_pair(PltSectionVA + Byte, Imm));
179 Byte += 4;
180 }
181 }
182 return Result;
183 }
184 };
185
186 } // end anonymous namespace
187
createAArch64InstrAnalysis(const MCInstrInfo * Info)188 static MCInstrAnalysis *createAArch64InstrAnalysis(const MCInstrInfo *Info) {
189 return new AArch64MCInstrAnalysis(Info);
190 }
191
192 // Force static initialization.
LLVMInitializeAArch64TargetMC()193 extern "C" void LLVMInitializeAArch64TargetMC() {
194 for (Target *T : {&getTheAArch64leTarget(), &getTheAArch64beTarget(),
195 &getTheARM64Target()}) {
196 // Register the MC asm info.
197 RegisterMCAsmInfoFn X(*T, createAArch64MCAsmInfo);
198
199 // Register the MC instruction info.
200 TargetRegistry::RegisterMCInstrInfo(*T, createAArch64MCInstrInfo);
201
202 // Register the MC register info.
203 TargetRegistry::RegisterMCRegInfo(*T, createAArch64MCRegisterInfo);
204
205 // Register the MC subtarget info.
206 TargetRegistry::RegisterMCSubtargetInfo(*T, createAArch64MCSubtargetInfo);
207
208 // Register the MC instruction analyzer.
209 TargetRegistry::RegisterMCInstrAnalysis(*T, createAArch64InstrAnalysis);
210
211 // Register the MC Code Emitter
212 TargetRegistry::RegisterMCCodeEmitter(*T, createAArch64MCCodeEmitter);
213
214 // Register the obj streamers.
215 TargetRegistry::RegisterELFStreamer(*T, createELFStreamer);
216 TargetRegistry::RegisterMachOStreamer(*T, createMachOStreamer);
217 TargetRegistry::RegisterCOFFStreamer(*T, createWinCOFFStreamer);
218
219 // Register the obj target streamer.
220 TargetRegistry::RegisterObjectTargetStreamer(
221 *T, createAArch64ObjectTargetStreamer);
222
223 // Register the asm streamer.
224 TargetRegistry::RegisterAsmTargetStreamer(*T,
225 createAArch64AsmTargetStreamer);
226 // Register the MCInstPrinter.
227 TargetRegistry::RegisterMCInstPrinter(*T, createAArch64MCInstPrinter);
228 }
229
230 // Register the asm backend.
231 for (Target *T : {&getTheAArch64leTarget(), &getTheARM64Target()})
232 TargetRegistry::RegisterMCAsmBackend(*T, createAArch64leAsmBackend);
233 TargetRegistry::RegisterMCAsmBackend(getTheAArch64beTarget(),
234 createAArch64beAsmBackend);
235 }
236