1//===----------------------------------------------------------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// Automatically generated file, please consult code owner before editing. 10//===----------------------------------------------------------------------===// 11 12def A2_abs : HInst< 13(outs IntRegs:$Rd32), 14(ins IntRegs:$Rs32), 15"$Rd32 = abs($Rs32)", 16tc_cf8126ae, TypeS_2op>, Enc_5e2823 { 17let Inst{13-5} = 0b000000100; 18let Inst{31-21} = 0b10001100100; 19let hasNewValue = 1; 20let opNewValue = 0; 21let prefersSlot3 = 1; 22} 23def A2_absp : HInst< 24(outs DoubleRegs:$Rdd32), 25(ins DoubleRegs:$Rss32), 26"$Rdd32 = abs($Rss32)", 27tc_cf8126ae, TypeS_2op>, Enc_b9c5fb { 28let Inst{13-5} = 0b000000110; 29let Inst{31-21} = 0b10000000100; 30let prefersSlot3 = 1; 31} 32def A2_abssat : HInst< 33(outs IntRegs:$Rd32), 34(ins IntRegs:$Rs32), 35"$Rd32 = abs($Rs32):sat", 36tc_cf8126ae, TypeS_2op>, Enc_5e2823 { 37let Inst{13-5} = 0b000000101; 38let Inst{31-21} = 0b10001100100; 39let hasNewValue = 1; 40let opNewValue = 0; 41let prefersSlot3 = 1; 42let Defs = [USR_OVF]; 43} 44def A2_add : HInst< 45(outs IntRegs:$Rd32), 46(ins IntRegs:$Rs32, IntRegs:$Rt32), 47"$Rd32 = add($Rs32,$Rt32)", 48tc_5a2711e5, TypeALU32_3op>, Enc_5ab2be, PredNewRel, ImmRegRel { 49let Inst{7-5} = 0b000; 50let Inst{13-13} = 0b0; 51let Inst{31-21} = 0b11110011000; 52let hasNewValue = 1; 53let opNewValue = 0; 54let CextOpcode = "A2_add"; 55let InputType = "reg"; 56let BaseOpcode = "A2_add"; 57let isCommutable = 1; 58let isPredicable = 1; 59} 60def A2_addh_h16_hh : HInst< 61(outs IntRegs:$Rd32), 62(ins IntRegs:$Rt32, IntRegs:$Rs32), 63"$Rd32 = add($Rt32.h,$Rs32.h):<<16", 64tc_679309b8, TypeALU64>, Enc_bd6011 { 65let Inst{7-5} = 0b011; 66let Inst{13-13} = 0b0; 67let Inst{31-21} = 0b11010101010; 68let hasNewValue = 1; 69let opNewValue = 0; 70let prefersSlot3 = 1; 71} 72def A2_addh_h16_hl : HInst< 73(outs IntRegs:$Rd32), 74(ins IntRegs:$Rt32, IntRegs:$Rs32), 75"$Rd32 = add($Rt32.h,$Rs32.l):<<16", 76tc_679309b8, TypeALU64>, Enc_bd6011 { 77let Inst{7-5} = 0b010; 78let Inst{13-13} = 0b0; 79let Inst{31-21} = 0b11010101010; 80let hasNewValue = 1; 81let opNewValue = 0; 82let prefersSlot3 = 1; 83} 84def A2_addh_h16_lh : HInst< 85(outs IntRegs:$Rd32), 86(ins IntRegs:$Rt32, IntRegs:$Rs32), 87"$Rd32 = add($Rt32.l,$Rs32.h):<<16", 88tc_679309b8, TypeALU64>, Enc_bd6011 { 89let Inst{7-5} = 0b001; 90let Inst{13-13} = 0b0; 91let Inst{31-21} = 0b11010101010; 92let hasNewValue = 1; 93let opNewValue = 0; 94let prefersSlot3 = 1; 95} 96def A2_addh_h16_ll : HInst< 97(outs IntRegs:$Rd32), 98(ins IntRegs:$Rt32, IntRegs:$Rs32), 99"$Rd32 = add($Rt32.l,$Rs32.l):<<16", 100tc_679309b8, TypeALU64>, Enc_bd6011 { 101let Inst{7-5} = 0b000; 102let Inst{13-13} = 0b0; 103let Inst{31-21} = 0b11010101010; 104let hasNewValue = 1; 105let opNewValue = 0; 106let prefersSlot3 = 1; 107} 108def A2_addh_h16_sat_hh : HInst< 109(outs IntRegs:$Rd32), 110(ins IntRegs:$Rt32, IntRegs:$Rs32), 111"$Rd32 = add($Rt32.h,$Rs32.h):sat:<<16", 112tc_779080bf, TypeALU64>, Enc_bd6011 { 113let Inst{7-5} = 0b111; 114let Inst{13-13} = 0b0; 115let Inst{31-21} = 0b11010101010; 116let hasNewValue = 1; 117let opNewValue = 0; 118let prefersSlot3 = 1; 119let Defs = [USR_OVF]; 120} 121def A2_addh_h16_sat_hl : HInst< 122(outs IntRegs:$Rd32), 123(ins IntRegs:$Rt32, IntRegs:$Rs32), 124"$Rd32 = add($Rt32.h,$Rs32.l):sat:<<16", 125tc_779080bf, TypeALU64>, Enc_bd6011 { 126let Inst{7-5} = 0b110; 127let Inst{13-13} = 0b0; 128let Inst{31-21} = 0b11010101010; 129let hasNewValue = 1; 130let opNewValue = 0; 131let prefersSlot3 = 1; 132let Defs = [USR_OVF]; 133} 134def A2_addh_h16_sat_lh : HInst< 135(outs IntRegs:$Rd32), 136(ins IntRegs:$Rt32, IntRegs:$Rs32), 137"$Rd32 = add($Rt32.l,$Rs32.h):sat:<<16", 138tc_779080bf, TypeALU64>, Enc_bd6011 { 139let Inst{7-5} = 0b101; 140let Inst{13-13} = 0b0; 141let Inst{31-21} = 0b11010101010; 142let hasNewValue = 1; 143let opNewValue = 0; 144let prefersSlot3 = 1; 145let Defs = [USR_OVF]; 146} 147def A2_addh_h16_sat_ll : HInst< 148(outs IntRegs:$Rd32), 149(ins IntRegs:$Rt32, IntRegs:$Rs32), 150"$Rd32 = add($Rt32.l,$Rs32.l):sat:<<16", 151tc_779080bf, TypeALU64>, Enc_bd6011 { 152let Inst{7-5} = 0b100; 153let Inst{13-13} = 0b0; 154let Inst{31-21} = 0b11010101010; 155let hasNewValue = 1; 156let opNewValue = 0; 157let prefersSlot3 = 1; 158let Defs = [USR_OVF]; 159} 160def A2_addh_l16_hl : HInst< 161(outs IntRegs:$Rd32), 162(ins IntRegs:$Rt32, IntRegs:$Rs32), 163"$Rd32 = add($Rt32.l,$Rs32.h)", 164tc_4414d8b1, TypeALU64>, Enc_bd6011 { 165let Inst{7-5} = 0b010; 166let Inst{13-13} = 0b0; 167let Inst{31-21} = 0b11010101000; 168let hasNewValue = 1; 169let opNewValue = 0; 170let prefersSlot3 = 1; 171} 172def A2_addh_l16_ll : HInst< 173(outs IntRegs:$Rd32), 174(ins IntRegs:$Rt32, IntRegs:$Rs32), 175"$Rd32 = add($Rt32.l,$Rs32.l)", 176tc_4414d8b1, TypeALU64>, Enc_bd6011 { 177let Inst{7-5} = 0b000; 178let Inst{13-13} = 0b0; 179let Inst{31-21} = 0b11010101000; 180let hasNewValue = 1; 181let opNewValue = 0; 182let prefersSlot3 = 1; 183} 184def A2_addh_l16_sat_hl : HInst< 185(outs IntRegs:$Rd32), 186(ins IntRegs:$Rt32, IntRegs:$Rs32), 187"$Rd32 = add($Rt32.l,$Rs32.h):sat", 188tc_779080bf, TypeALU64>, Enc_bd6011 { 189let Inst{7-5} = 0b110; 190let Inst{13-13} = 0b0; 191let Inst{31-21} = 0b11010101000; 192let hasNewValue = 1; 193let opNewValue = 0; 194let prefersSlot3 = 1; 195let Defs = [USR_OVF]; 196} 197def A2_addh_l16_sat_ll : HInst< 198(outs IntRegs:$Rd32), 199(ins IntRegs:$Rt32, IntRegs:$Rs32), 200"$Rd32 = add($Rt32.l,$Rs32.l):sat", 201tc_779080bf, TypeALU64>, Enc_bd6011 { 202let Inst{7-5} = 0b100; 203let Inst{13-13} = 0b0; 204let Inst{31-21} = 0b11010101000; 205let hasNewValue = 1; 206let opNewValue = 0; 207let prefersSlot3 = 1; 208let Defs = [USR_OVF]; 209} 210def A2_addi : HInst< 211(outs IntRegs:$Rd32), 212(ins IntRegs:$Rs32, s32_0Imm:$Ii), 213"$Rd32 = add($Rs32,#$Ii)", 214tc_5a2711e5, TypeALU32_ADDI>, Enc_cb9321, PredNewRel, ImmRegRel { 215let Inst{31-28} = 0b1011; 216let hasNewValue = 1; 217let opNewValue = 0; 218let CextOpcode = "A2_add"; 219let InputType = "imm"; 220let BaseOpcode = "A2_addi"; 221let isPredicable = 1; 222let isAdd = 1; 223let isExtendable = 1; 224let opExtendable = 2; 225let isExtentSigned = 1; 226let opExtentBits = 16; 227let opExtentAlign = 0; 228} 229def A2_addp : HInst< 230(outs DoubleRegs:$Rdd32), 231(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 232"$Rdd32 = add($Rss32,$Rtt32)", 233tc_946df596, TypeALU64>, Enc_a56825 { 234let Inst{7-5} = 0b111; 235let Inst{13-13} = 0b0; 236let Inst{31-21} = 0b11010011000; 237let isCommutable = 1; 238let isAdd = 1; 239} 240def A2_addpsat : HInst< 241(outs DoubleRegs:$Rdd32), 242(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 243"$Rdd32 = add($Rss32,$Rtt32):sat", 244tc_779080bf, TypeALU64>, Enc_a56825 { 245let Inst{7-5} = 0b101; 246let Inst{13-13} = 0b0; 247let Inst{31-21} = 0b11010011011; 248let prefersSlot3 = 1; 249let Defs = [USR_OVF]; 250let isCommutable = 1; 251} 252def A2_addsat : HInst< 253(outs IntRegs:$Rd32), 254(ins IntRegs:$Rs32, IntRegs:$Rt32), 255"$Rd32 = add($Rs32,$Rt32):sat", 256tc_61830035, TypeALU32_3op>, Enc_5ab2be { 257let Inst{7-5} = 0b000; 258let Inst{13-13} = 0b0; 259let Inst{31-21} = 0b11110110010; 260let hasNewValue = 1; 261let opNewValue = 0; 262let prefersSlot3 = 1; 263let Defs = [USR_OVF]; 264let InputType = "reg"; 265let isCommutable = 1; 266} 267def A2_addsp : HInst< 268(outs DoubleRegs:$Rdd32), 269(ins IntRegs:$Rs32, DoubleRegs:$Rtt32), 270"$Rdd32 = add($Rs32,$Rtt32)", 271tc_679309b8, TypeALU64> { 272let isPseudo = 1; 273} 274def A2_addsph : HInst< 275(outs DoubleRegs:$Rdd32), 276(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 277"$Rdd32 = add($Rss32,$Rtt32):raw:hi", 278tc_679309b8, TypeALU64>, Enc_a56825 { 279let Inst{7-5} = 0b111; 280let Inst{13-13} = 0b0; 281let Inst{31-21} = 0b11010011011; 282let prefersSlot3 = 1; 283} 284def A2_addspl : HInst< 285(outs DoubleRegs:$Rdd32), 286(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 287"$Rdd32 = add($Rss32,$Rtt32):raw:lo", 288tc_679309b8, TypeALU64>, Enc_a56825 { 289let Inst{7-5} = 0b110; 290let Inst{13-13} = 0b0; 291let Inst{31-21} = 0b11010011011; 292let prefersSlot3 = 1; 293} 294def A2_and : HInst< 295(outs IntRegs:$Rd32), 296(ins IntRegs:$Rs32, IntRegs:$Rt32), 297"$Rd32 = and($Rs32,$Rt32)", 298tc_5a2711e5, TypeALU32_3op>, Enc_5ab2be, PredNewRel, ImmRegRel { 299let Inst{7-5} = 0b000; 300let Inst{13-13} = 0b0; 301let Inst{31-21} = 0b11110001000; 302let hasNewValue = 1; 303let opNewValue = 0; 304let CextOpcode = "A2_and"; 305let InputType = "reg"; 306let BaseOpcode = "A2_and"; 307let isCommutable = 1; 308let isPredicable = 1; 309} 310def A2_andir : HInst< 311(outs IntRegs:$Rd32), 312(ins IntRegs:$Rs32, s32_0Imm:$Ii), 313"$Rd32 = and($Rs32,#$Ii)", 314tc_5a2711e5, TypeALU32_2op>, Enc_140c83, ImmRegRel { 315let Inst{31-22} = 0b0111011000; 316let hasNewValue = 1; 317let opNewValue = 0; 318let CextOpcode = "A2_and"; 319let InputType = "imm"; 320let isExtendable = 1; 321let opExtendable = 2; 322let isExtentSigned = 1; 323let opExtentBits = 10; 324let opExtentAlign = 0; 325} 326def A2_andp : HInst< 327(outs DoubleRegs:$Rdd32), 328(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 329"$Rdd32 = and($Rss32,$Rtt32)", 330tc_946df596, TypeALU64>, Enc_a56825 { 331let Inst{7-5} = 0b000; 332let Inst{13-13} = 0b0; 333let Inst{31-21} = 0b11010011111; 334let isCommutable = 1; 335} 336def A2_aslh : HInst< 337(outs IntRegs:$Rd32), 338(ins IntRegs:$Rs32), 339"$Rd32 = aslh($Rs32)", 340tc_57890846, TypeALU32_2op>, Enc_5e2823, PredNewRel { 341let Inst{13-5} = 0b000000000; 342let Inst{31-21} = 0b01110000000; 343let hasNewValue = 1; 344let opNewValue = 0; 345let BaseOpcode = "A2_aslh"; 346let isPredicable = 1; 347} 348def A2_asrh : HInst< 349(outs IntRegs:$Rd32), 350(ins IntRegs:$Rs32), 351"$Rd32 = asrh($Rs32)", 352tc_57890846, TypeALU32_2op>, Enc_5e2823, PredNewRel { 353let Inst{13-5} = 0b000000000; 354let Inst{31-21} = 0b01110000001; 355let hasNewValue = 1; 356let opNewValue = 0; 357let BaseOpcode = "A2_asrh"; 358let isPredicable = 1; 359} 360def A2_combine_hh : HInst< 361(outs IntRegs:$Rd32), 362(ins IntRegs:$Rt32, IntRegs:$Rs32), 363"$Rd32 = combine($Rt32.h,$Rs32.h)", 364tc_5a2711e5, TypeALU32_3op>, Enc_bd6011 { 365let Inst{7-5} = 0b000; 366let Inst{13-13} = 0b0; 367let Inst{31-21} = 0b11110011100; 368let hasNewValue = 1; 369let opNewValue = 0; 370let InputType = "reg"; 371} 372def A2_combine_hl : HInst< 373(outs IntRegs:$Rd32), 374(ins IntRegs:$Rt32, IntRegs:$Rs32), 375"$Rd32 = combine($Rt32.h,$Rs32.l)", 376tc_5a2711e5, TypeALU32_3op>, Enc_bd6011 { 377let Inst{7-5} = 0b000; 378let Inst{13-13} = 0b0; 379let Inst{31-21} = 0b11110011101; 380let hasNewValue = 1; 381let opNewValue = 0; 382let InputType = "reg"; 383} 384def A2_combine_lh : HInst< 385(outs IntRegs:$Rd32), 386(ins IntRegs:$Rt32, IntRegs:$Rs32), 387"$Rd32 = combine($Rt32.l,$Rs32.h)", 388tc_5a2711e5, TypeALU32_3op>, Enc_bd6011 { 389let Inst{7-5} = 0b000; 390let Inst{13-13} = 0b0; 391let Inst{31-21} = 0b11110011110; 392let hasNewValue = 1; 393let opNewValue = 0; 394let InputType = "reg"; 395} 396def A2_combine_ll : HInst< 397(outs IntRegs:$Rd32), 398(ins IntRegs:$Rt32, IntRegs:$Rs32), 399"$Rd32 = combine($Rt32.l,$Rs32.l)", 400tc_5a2711e5, TypeALU32_3op>, Enc_bd6011 { 401let Inst{7-5} = 0b000; 402let Inst{13-13} = 0b0; 403let Inst{31-21} = 0b11110011111; 404let hasNewValue = 1; 405let opNewValue = 0; 406let InputType = "reg"; 407} 408def A2_combineii : HInst< 409(outs DoubleRegs:$Rdd32), 410(ins s32_0Imm:$Ii, s8_0Imm:$II), 411"$Rdd32 = combine(#$Ii,#$II)", 412tc_5a2711e5, TypeALU32_2op>, Enc_18c338 { 413let Inst{31-23} = 0b011111000; 414let isReMaterializable = 1; 415let isAsCheapAsAMove = 1; 416let isMoveImm = 1; 417let isExtendable = 1; 418let opExtendable = 1; 419let isExtentSigned = 1; 420let opExtentBits = 8; 421let opExtentAlign = 0; 422} 423def A2_combinew : HInst< 424(outs DoubleRegs:$Rdd32), 425(ins IntRegs:$Rs32, IntRegs:$Rt32), 426"$Rdd32 = combine($Rs32,$Rt32)", 427tc_5a2711e5, TypeALU32_3op>, Enc_be32a5, PredNewRel { 428let Inst{7-5} = 0b000; 429let Inst{13-13} = 0b0; 430let Inst{31-21} = 0b11110101000; 431let InputType = "reg"; 432let BaseOpcode = "A2_combinew"; 433let isPredicable = 1; 434} 435def A2_max : HInst< 436(outs IntRegs:$Rd32), 437(ins IntRegs:$Rs32, IntRegs:$Rt32), 438"$Rd32 = max($Rs32,$Rt32)", 439tc_779080bf, TypeALU64>, Enc_5ab2be { 440let Inst{7-5} = 0b000; 441let Inst{13-13} = 0b0; 442let Inst{31-21} = 0b11010101110; 443let hasNewValue = 1; 444let opNewValue = 0; 445let prefersSlot3 = 1; 446} 447def A2_maxp : HInst< 448(outs DoubleRegs:$Rdd32), 449(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 450"$Rdd32 = max($Rss32,$Rtt32)", 451tc_779080bf, TypeALU64>, Enc_a56825 { 452let Inst{7-5} = 0b100; 453let Inst{13-13} = 0b0; 454let Inst{31-21} = 0b11010011110; 455let prefersSlot3 = 1; 456} 457def A2_maxu : HInst< 458(outs IntRegs:$Rd32), 459(ins IntRegs:$Rs32, IntRegs:$Rt32), 460"$Rd32 = maxu($Rs32,$Rt32)", 461tc_779080bf, TypeALU64>, Enc_5ab2be { 462let Inst{7-5} = 0b100; 463let Inst{13-13} = 0b0; 464let Inst{31-21} = 0b11010101110; 465let hasNewValue = 1; 466let opNewValue = 0; 467let prefersSlot3 = 1; 468} 469def A2_maxup : HInst< 470(outs DoubleRegs:$Rdd32), 471(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 472"$Rdd32 = maxu($Rss32,$Rtt32)", 473tc_779080bf, TypeALU64>, Enc_a56825 { 474let Inst{7-5} = 0b101; 475let Inst{13-13} = 0b0; 476let Inst{31-21} = 0b11010011110; 477let prefersSlot3 = 1; 478} 479def A2_min : HInst< 480(outs IntRegs:$Rd32), 481(ins IntRegs:$Rt32, IntRegs:$Rs32), 482"$Rd32 = min($Rt32,$Rs32)", 483tc_779080bf, TypeALU64>, Enc_bd6011 { 484let Inst{7-5} = 0b000; 485let Inst{13-13} = 0b0; 486let Inst{31-21} = 0b11010101101; 487let hasNewValue = 1; 488let opNewValue = 0; 489let prefersSlot3 = 1; 490} 491def A2_minp : HInst< 492(outs DoubleRegs:$Rdd32), 493(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), 494"$Rdd32 = min($Rtt32,$Rss32)", 495tc_779080bf, TypeALU64>, Enc_ea23e4 { 496let Inst{7-5} = 0b110; 497let Inst{13-13} = 0b0; 498let Inst{31-21} = 0b11010011101; 499let prefersSlot3 = 1; 500} 501def A2_minu : HInst< 502(outs IntRegs:$Rd32), 503(ins IntRegs:$Rt32, IntRegs:$Rs32), 504"$Rd32 = minu($Rt32,$Rs32)", 505tc_779080bf, TypeALU64>, Enc_bd6011 { 506let Inst{7-5} = 0b100; 507let Inst{13-13} = 0b0; 508let Inst{31-21} = 0b11010101101; 509let hasNewValue = 1; 510let opNewValue = 0; 511let prefersSlot3 = 1; 512} 513def A2_minup : HInst< 514(outs DoubleRegs:$Rdd32), 515(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), 516"$Rdd32 = minu($Rtt32,$Rss32)", 517tc_779080bf, TypeALU64>, Enc_ea23e4 { 518let Inst{7-5} = 0b111; 519let Inst{13-13} = 0b0; 520let Inst{31-21} = 0b11010011101; 521let prefersSlot3 = 1; 522} 523def A2_neg : HInst< 524(outs IntRegs:$Rd32), 525(ins IntRegs:$Rs32), 526"$Rd32 = neg($Rs32)", 527tc_57890846, TypeALU32_2op> { 528let hasNewValue = 1; 529let opNewValue = 0; 530let isPseudo = 1; 531let isCodeGenOnly = 1; 532} 533def A2_negp : HInst< 534(outs DoubleRegs:$Rdd32), 535(ins DoubleRegs:$Rss32), 536"$Rdd32 = neg($Rss32)", 537tc_0ae0825c, TypeS_2op>, Enc_b9c5fb { 538let Inst{13-5} = 0b000000101; 539let Inst{31-21} = 0b10000000100; 540} 541def A2_negsat : HInst< 542(outs IntRegs:$Rd32), 543(ins IntRegs:$Rs32), 544"$Rd32 = neg($Rs32):sat", 545tc_cf8126ae, TypeS_2op>, Enc_5e2823 { 546let Inst{13-5} = 0b000000110; 547let Inst{31-21} = 0b10001100100; 548let hasNewValue = 1; 549let opNewValue = 0; 550let prefersSlot3 = 1; 551let Defs = [USR_OVF]; 552} 553def A2_nop : HInst< 554(outs), 555(ins), 556"nop", 557tc_2eabeebe, TypeALU32_2op>, Enc_e3b0c4 { 558let Inst{13-0} = 0b00000000000000; 559let Inst{31-16} = 0b0111111100000000; 560} 561def A2_not : HInst< 562(outs IntRegs:$Rd32), 563(ins IntRegs:$Rs32), 564"$Rd32 = not($Rs32)", 565tc_57890846, TypeALU32_2op> { 566let hasNewValue = 1; 567let opNewValue = 0; 568let isPseudo = 1; 569let isCodeGenOnly = 1; 570} 571def A2_notp : HInst< 572(outs DoubleRegs:$Rdd32), 573(ins DoubleRegs:$Rss32), 574"$Rdd32 = not($Rss32)", 575tc_0ae0825c, TypeS_2op>, Enc_b9c5fb { 576let Inst{13-5} = 0b000000100; 577let Inst{31-21} = 0b10000000100; 578} 579def A2_or : HInst< 580(outs IntRegs:$Rd32), 581(ins IntRegs:$Rs32, IntRegs:$Rt32), 582"$Rd32 = or($Rs32,$Rt32)", 583tc_5a2711e5, TypeALU32_3op>, Enc_5ab2be, PredNewRel, ImmRegRel { 584let Inst{7-5} = 0b000; 585let Inst{13-13} = 0b0; 586let Inst{31-21} = 0b11110001001; 587let hasNewValue = 1; 588let opNewValue = 0; 589let CextOpcode = "A2_or"; 590let InputType = "reg"; 591let BaseOpcode = "A2_or"; 592let isCommutable = 1; 593let isPredicable = 1; 594} 595def A2_orir : HInst< 596(outs IntRegs:$Rd32), 597(ins IntRegs:$Rs32, s32_0Imm:$Ii), 598"$Rd32 = or($Rs32,#$Ii)", 599tc_5a2711e5, TypeALU32_2op>, Enc_140c83, ImmRegRel { 600let Inst{31-22} = 0b0111011010; 601let hasNewValue = 1; 602let opNewValue = 0; 603let CextOpcode = "A2_or"; 604let InputType = "imm"; 605let isExtendable = 1; 606let opExtendable = 2; 607let isExtentSigned = 1; 608let opExtentBits = 10; 609let opExtentAlign = 0; 610} 611def A2_orp : HInst< 612(outs DoubleRegs:$Rdd32), 613(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 614"$Rdd32 = or($Rss32,$Rtt32)", 615tc_946df596, TypeALU64>, Enc_a56825 { 616let Inst{7-5} = 0b010; 617let Inst{13-13} = 0b0; 618let Inst{31-21} = 0b11010011111; 619let isCommutable = 1; 620} 621def A2_paddf : HInst< 622(outs IntRegs:$Rd32), 623(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), 624"if (!$Pu4) $Rd32 = add($Rs32,$Rt32)", 625tc_4c5ba658, TypeALU32_3op>, Enc_ea4c54, PredNewRel, ImmRegRel { 626let Inst{7-7} = 0b1; 627let Inst{13-13} = 0b0; 628let Inst{31-21} = 0b11111011000; 629let isPredicated = 1; 630let isPredicatedFalse = 1; 631let hasNewValue = 1; 632let opNewValue = 0; 633let CextOpcode = "A2_add"; 634let InputType = "reg"; 635let BaseOpcode = "A2_add"; 636} 637def A2_paddfnew : HInst< 638(outs IntRegs:$Rd32), 639(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), 640"if (!$Pu4.new) $Rd32 = add($Rs32,$Rt32)", 641tc_05c070ec, TypeALU32_3op>, Enc_ea4c54, PredNewRel, ImmRegRel { 642let Inst{7-7} = 0b1; 643let Inst{13-13} = 0b1; 644let Inst{31-21} = 0b11111011000; 645let isPredicated = 1; 646let isPredicatedFalse = 1; 647let hasNewValue = 1; 648let opNewValue = 0; 649let isPredicatedNew = 1; 650let CextOpcode = "A2_add"; 651let InputType = "reg"; 652let BaseOpcode = "A2_add"; 653} 654def A2_paddif : HInst< 655(outs IntRegs:$Rd32), 656(ins PredRegs:$Pu4, IntRegs:$Rs32, s32_0Imm:$Ii), 657"if (!$Pu4) $Rd32 = add($Rs32,#$Ii)", 658tc_4c5ba658, TypeALU32_2op>, Enc_e38e1f, PredNewRel, ImmRegRel { 659let Inst{13-13} = 0b0; 660let Inst{31-23} = 0b011101001; 661let isPredicated = 1; 662let isPredicatedFalse = 1; 663let hasNewValue = 1; 664let opNewValue = 0; 665let CextOpcode = "A2_add"; 666let InputType = "imm"; 667let BaseOpcode = "A2_addi"; 668let isExtendable = 1; 669let opExtendable = 3; 670let isExtentSigned = 1; 671let opExtentBits = 8; 672let opExtentAlign = 0; 673} 674def A2_paddifnew : HInst< 675(outs IntRegs:$Rd32), 676(ins PredRegs:$Pu4, IntRegs:$Rs32, s32_0Imm:$Ii), 677"if (!$Pu4.new) $Rd32 = add($Rs32,#$Ii)", 678tc_05c070ec, TypeALU32_2op>, Enc_e38e1f, PredNewRel, ImmRegRel { 679let Inst{13-13} = 0b1; 680let Inst{31-23} = 0b011101001; 681let isPredicated = 1; 682let isPredicatedFalse = 1; 683let hasNewValue = 1; 684let opNewValue = 0; 685let isPredicatedNew = 1; 686let CextOpcode = "A2_add"; 687let InputType = "imm"; 688let BaseOpcode = "A2_addi"; 689let isExtendable = 1; 690let opExtendable = 3; 691let isExtentSigned = 1; 692let opExtentBits = 8; 693let opExtentAlign = 0; 694} 695def A2_paddit : HInst< 696(outs IntRegs:$Rd32), 697(ins PredRegs:$Pu4, IntRegs:$Rs32, s32_0Imm:$Ii), 698"if ($Pu4) $Rd32 = add($Rs32,#$Ii)", 699tc_4c5ba658, TypeALU32_2op>, Enc_e38e1f, PredNewRel, ImmRegRel { 700let Inst{13-13} = 0b0; 701let Inst{31-23} = 0b011101000; 702let isPredicated = 1; 703let hasNewValue = 1; 704let opNewValue = 0; 705let CextOpcode = "A2_add"; 706let InputType = "imm"; 707let BaseOpcode = "A2_addi"; 708let isExtendable = 1; 709let opExtendable = 3; 710let isExtentSigned = 1; 711let opExtentBits = 8; 712let opExtentAlign = 0; 713} 714def A2_padditnew : HInst< 715(outs IntRegs:$Rd32), 716(ins PredRegs:$Pu4, IntRegs:$Rs32, s32_0Imm:$Ii), 717"if ($Pu4.new) $Rd32 = add($Rs32,#$Ii)", 718tc_05c070ec, TypeALU32_2op>, Enc_e38e1f, PredNewRel, ImmRegRel { 719let Inst{13-13} = 0b1; 720let Inst{31-23} = 0b011101000; 721let isPredicated = 1; 722let hasNewValue = 1; 723let opNewValue = 0; 724let isPredicatedNew = 1; 725let CextOpcode = "A2_add"; 726let InputType = "imm"; 727let BaseOpcode = "A2_addi"; 728let isExtendable = 1; 729let opExtendable = 3; 730let isExtentSigned = 1; 731let opExtentBits = 8; 732let opExtentAlign = 0; 733} 734def A2_paddt : HInst< 735(outs IntRegs:$Rd32), 736(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), 737"if ($Pu4) $Rd32 = add($Rs32,$Rt32)", 738tc_4c5ba658, TypeALU32_3op>, Enc_ea4c54, PredNewRel, ImmRegRel { 739let Inst{7-7} = 0b0; 740let Inst{13-13} = 0b0; 741let Inst{31-21} = 0b11111011000; 742let isPredicated = 1; 743let hasNewValue = 1; 744let opNewValue = 0; 745let CextOpcode = "A2_add"; 746let InputType = "reg"; 747let BaseOpcode = "A2_add"; 748} 749def A2_paddtnew : HInst< 750(outs IntRegs:$Rd32), 751(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), 752"if ($Pu4.new) $Rd32 = add($Rs32,$Rt32)", 753tc_05c070ec, TypeALU32_3op>, Enc_ea4c54, PredNewRel, ImmRegRel { 754let Inst{7-7} = 0b0; 755let Inst{13-13} = 0b1; 756let Inst{31-21} = 0b11111011000; 757let isPredicated = 1; 758let hasNewValue = 1; 759let opNewValue = 0; 760let isPredicatedNew = 1; 761let CextOpcode = "A2_add"; 762let InputType = "reg"; 763let BaseOpcode = "A2_add"; 764} 765def A2_pandf : HInst< 766(outs IntRegs:$Rd32), 767(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), 768"if (!$Pu4) $Rd32 = and($Rs32,$Rt32)", 769tc_4c5ba658, TypeALU32_3op>, Enc_ea4c54, PredNewRel { 770let Inst{7-7} = 0b1; 771let Inst{13-13} = 0b0; 772let Inst{31-21} = 0b11111001000; 773let isPredicated = 1; 774let isPredicatedFalse = 1; 775let hasNewValue = 1; 776let opNewValue = 0; 777let BaseOpcode = "A2_and"; 778} 779def A2_pandfnew : HInst< 780(outs IntRegs:$Rd32), 781(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), 782"if (!$Pu4.new) $Rd32 = and($Rs32,$Rt32)", 783tc_05c070ec, TypeALU32_3op>, Enc_ea4c54, PredNewRel { 784let Inst{7-7} = 0b1; 785let Inst{13-13} = 0b1; 786let Inst{31-21} = 0b11111001000; 787let isPredicated = 1; 788let isPredicatedFalse = 1; 789let hasNewValue = 1; 790let opNewValue = 0; 791let isPredicatedNew = 1; 792let BaseOpcode = "A2_and"; 793} 794def A2_pandt : HInst< 795(outs IntRegs:$Rd32), 796(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), 797"if ($Pu4) $Rd32 = and($Rs32,$Rt32)", 798tc_4c5ba658, TypeALU32_3op>, Enc_ea4c54, PredNewRel { 799let Inst{7-7} = 0b0; 800let Inst{13-13} = 0b0; 801let Inst{31-21} = 0b11111001000; 802let isPredicated = 1; 803let hasNewValue = 1; 804let opNewValue = 0; 805let BaseOpcode = "A2_and"; 806} 807def A2_pandtnew : HInst< 808(outs IntRegs:$Rd32), 809(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), 810"if ($Pu4.new) $Rd32 = and($Rs32,$Rt32)", 811tc_05c070ec, TypeALU32_3op>, Enc_ea4c54, PredNewRel { 812let Inst{7-7} = 0b0; 813let Inst{13-13} = 0b1; 814let Inst{31-21} = 0b11111001000; 815let isPredicated = 1; 816let hasNewValue = 1; 817let opNewValue = 0; 818let isPredicatedNew = 1; 819let BaseOpcode = "A2_and"; 820} 821def A2_porf : HInst< 822(outs IntRegs:$Rd32), 823(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), 824"if (!$Pu4) $Rd32 = or($Rs32,$Rt32)", 825tc_4c5ba658, TypeALU32_3op>, Enc_ea4c54, PredNewRel { 826let Inst{7-7} = 0b1; 827let Inst{13-13} = 0b0; 828let Inst{31-21} = 0b11111001001; 829let isPredicated = 1; 830let isPredicatedFalse = 1; 831let hasNewValue = 1; 832let opNewValue = 0; 833let BaseOpcode = "A2_or"; 834} 835def A2_porfnew : HInst< 836(outs IntRegs:$Rd32), 837(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), 838"if (!$Pu4.new) $Rd32 = or($Rs32,$Rt32)", 839tc_05c070ec, TypeALU32_3op>, Enc_ea4c54, PredNewRel { 840let Inst{7-7} = 0b1; 841let Inst{13-13} = 0b1; 842let Inst{31-21} = 0b11111001001; 843let isPredicated = 1; 844let isPredicatedFalse = 1; 845let hasNewValue = 1; 846let opNewValue = 0; 847let isPredicatedNew = 1; 848let BaseOpcode = "A2_or"; 849} 850def A2_port : HInst< 851(outs IntRegs:$Rd32), 852(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), 853"if ($Pu4) $Rd32 = or($Rs32,$Rt32)", 854tc_4c5ba658, TypeALU32_3op>, Enc_ea4c54, PredNewRel { 855let Inst{7-7} = 0b0; 856let Inst{13-13} = 0b0; 857let Inst{31-21} = 0b11111001001; 858let isPredicated = 1; 859let hasNewValue = 1; 860let opNewValue = 0; 861let BaseOpcode = "A2_or"; 862} 863def A2_portnew : HInst< 864(outs IntRegs:$Rd32), 865(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), 866"if ($Pu4.new) $Rd32 = or($Rs32,$Rt32)", 867tc_05c070ec, TypeALU32_3op>, Enc_ea4c54, PredNewRel { 868let Inst{7-7} = 0b0; 869let Inst{13-13} = 0b1; 870let Inst{31-21} = 0b11111001001; 871let isPredicated = 1; 872let hasNewValue = 1; 873let opNewValue = 0; 874let isPredicatedNew = 1; 875let BaseOpcode = "A2_or"; 876} 877def A2_psubf : HInst< 878(outs IntRegs:$Rd32), 879(ins PredRegs:$Pu4, IntRegs:$Rt32, IntRegs:$Rs32), 880"if (!$Pu4) $Rd32 = sub($Rt32,$Rs32)", 881tc_4c5ba658, TypeALU32_3op>, Enc_9b0bc1, PredNewRel { 882let Inst{7-7} = 0b1; 883let Inst{13-13} = 0b0; 884let Inst{31-21} = 0b11111011001; 885let isPredicated = 1; 886let isPredicatedFalse = 1; 887let hasNewValue = 1; 888let opNewValue = 0; 889let BaseOpcode = "A2_sub"; 890} 891def A2_psubfnew : HInst< 892(outs IntRegs:$Rd32), 893(ins PredRegs:$Pu4, IntRegs:$Rt32, IntRegs:$Rs32), 894"if (!$Pu4.new) $Rd32 = sub($Rt32,$Rs32)", 895tc_05c070ec, TypeALU32_3op>, Enc_9b0bc1, PredNewRel { 896let Inst{7-7} = 0b1; 897let Inst{13-13} = 0b1; 898let Inst{31-21} = 0b11111011001; 899let isPredicated = 1; 900let isPredicatedFalse = 1; 901let hasNewValue = 1; 902let opNewValue = 0; 903let isPredicatedNew = 1; 904let BaseOpcode = "A2_sub"; 905} 906def A2_psubt : HInst< 907(outs IntRegs:$Rd32), 908(ins PredRegs:$Pu4, IntRegs:$Rt32, IntRegs:$Rs32), 909"if ($Pu4) $Rd32 = sub($Rt32,$Rs32)", 910tc_4c5ba658, TypeALU32_3op>, Enc_9b0bc1, PredNewRel { 911let Inst{7-7} = 0b0; 912let Inst{13-13} = 0b0; 913let Inst{31-21} = 0b11111011001; 914let isPredicated = 1; 915let hasNewValue = 1; 916let opNewValue = 0; 917let BaseOpcode = "A2_sub"; 918} 919def A2_psubtnew : HInst< 920(outs IntRegs:$Rd32), 921(ins PredRegs:$Pu4, IntRegs:$Rt32, IntRegs:$Rs32), 922"if ($Pu4.new) $Rd32 = sub($Rt32,$Rs32)", 923tc_05c070ec, TypeALU32_3op>, Enc_9b0bc1, PredNewRel { 924let Inst{7-7} = 0b0; 925let Inst{13-13} = 0b1; 926let Inst{31-21} = 0b11111011001; 927let isPredicated = 1; 928let hasNewValue = 1; 929let opNewValue = 0; 930let isPredicatedNew = 1; 931let BaseOpcode = "A2_sub"; 932} 933def A2_pxorf : HInst< 934(outs IntRegs:$Rd32), 935(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), 936"if (!$Pu4) $Rd32 = xor($Rs32,$Rt32)", 937tc_4c5ba658, TypeALU32_3op>, Enc_ea4c54, PredNewRel { 938let Inst{7-7} = 0b1; 939let Inst{13-13} = 0b0; 940let Inst{31-21} = 0b11111001011; 941let isPredicated = 1; 942let isPredicatedFalse = 1; 943let hasNewValue = 1; 944let opNewValue = 0; 945let BaseOpcode = "A2_xor"; 946} 947def A2_pxorfnew : HInst< 948(outs IntRegs:$Rd32), 949(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), 950"if (!$Pu4.new) $Rd32 = xor($Rs32,$Rt32)", 951tc_05c070ec, TypeALU32_3op>, Enc_ea4c54, PredNewRel { 952let Inst{7-7} = 0b1; 953let Inst{13-13} = 0b1; 954let Inst{31-21} = 0b11111001011; 955let isPredicated = 1; 956let isPredicatedFalse = 1; 957let hasNewValue = 1; 958let opNewValue = 0; 959let isPredicatedNew = 1; 960let BaseOpcode = "A2_xor"; 961} 962def A2_pxort : HInst< 963(outs IntRegs:$Rd32), 964(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), 965"if ($Pu4) $Rd32 = xor($Rs32,$Rt32)", 966tc_4c5ba658, TypeALU32_3op>, Enc_ea4c54, PredNewRel { 967let Inst{7-7} = 0b0; 968let Inst{13-13} = 0b0; 969let Inst{31-21} = 0b11111001011; 970let isPredicated = 1; 971let hasNewValue = 1; 972let opNewValue = 0; 973let BaseOpcode = "A2_xor"; 974} 975def A2_pxortnew : HInst< 976(outs IntRegs:$Rd32), 977(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), 978"if ($Pu4.new) $Rd32 = xor($Rs32,$Rt32)", 979tc_05c070ec, TypeALU32_3op>, Enc_ea4c54, PredNewRel { 980let Inst{7-7} = 0b0; 981let Inst{13-13} = 0b1; 982let Inst{31-21} = 0b11111001011; 983let isPredicated = 1; 984let hasNewValue = 1; 985let opNewValue = 0; 986let isPredicatedNew = 1; 987let BaseOpcode = "A2_xor"; 988} 989def A2_roundsat : HInst< 990(outs IntRegs:$Rd32), 991(ins DoubleRegs:$Rss32), 992"$Rd32 = round($Rss32):sat", 993tc_cf8126ae, TypeS_2op>, Enc_90cd8b { 994let Inst{13-5} = 0b000000001; 995let Inst{31-21} = 0b10001000110; 996let hasNewValue = 1; 997let opNewValue = 0; 998let prefersSlot3 = 1; 999let Defs = [USR_OVF]; 1000} 1001def A2_sat : HInst< 1002(outs IntRegs:$Rd32), 1003(ins DoubleRegs:$Rss32), 1004"$Rd32 = sat($Rss32)", 1005tc_0ae0825c, TypeS_2op>, Enc_90cd8b { 1006let Inst{13-5} = 0b000000000; 1007let Inst{31-21} = 0b10001000110; 1008let hasNewValue = 1; 1009let opNewValue = 0; 1010let Defs = [USR_OVF]; 1011} 1012def A2_satb : HInst< 1013(outs IntRegs:$Rd32), 1014(ins IntRegs:$Rs32), 1015"$Rd32 = satb($Rs32)", 1016tc_0ae0825c, TypeS_2op>, Enc_5e2823 { 1017let Inst{13-5} = 0b000000111; 1018let Inst{31-21} = 0b10001100110; 1019let hasNewValue = 1; 1020let opNewValue = 0; 1021let Defs = [USR_OVF]; 1022} 1023def A2_sath : HInst< 1024(outs IntRegs:$Rd32), 1025(ins IntRegs:$Rs32), 1026"$Rd32 = sath($Rs32)", 1027tc_0ae0825c, TypeS_2op>, Enc_5e2823 { 1028let Inst{13-5} = 0b000000100; 1029let Inst{31-21} = 0b10001100110; 1030let hasNewValue = 1; 1031let opNewValue = 0; 1032let Defs = [USR_OVF]; 1033} 1034def A2_satub : HInst< 1035(outs IntRegs:$Rd32), 1036(ins IntRegs:$Rs32), 1037"$Rd32 = satub($Rs32)", 1038tc_0ae0825c, TypeS_2op>, Enc_5e2823 { 1039let Inst{13-5} = 0b000000110; 1040let Inst{31-21} = 0b10001100110; 1041let hasNewValue = 1; 1042let opNewValue = 0; 1043let Defs = [USR_OVF]; 1044} 1045def A2_satuh : HInst< 1046(outs IntRegs:$Rd32), 1047(ins IntRegs:$Rs32), 1048"$Rd32 = satuh($Rs32)", 1049tc_0ae0825c, TypeS_2op>, Enc_5e2823 { 1050let Inst{13-5} = 0b000000101; 1051let Inst{31-21} = 0b10001100110; 1052let hasNewValue = 1; 1053let opNewValue = 0; 1054let Defs = [USR_OVF]; 1055} 1056def A2_sub : HInst< 1057(outs IntRegs:$Rd32), 1058(ins IntRegs:$Rt32, IntRegs:$Rs32), 1059"$Rd32 = sub($Rt32,$Rs32)", 1060tc_5a2711e5, TypeALU32_3op>, Enc_bd6011, PredNewRel, ImmRegRel { 1061let Inst{7-5} = 0b000; 1062let Inst{13-13} = 0b0; 1063let Inst{31-21} = 0b11110011001; 1064let hasNewValue = 1; 1065let opNewValue = 0; 1066let CextOpcode = "A2_sub"; 1067let InputType = "reg"; 1068let BaseOpcode = "A2_sub"; 1069let isPredicable = 1; 1070} 1071def A2_subh_h16_hh : HInst< 1072(outs IntRegs:$Rd32), 1073(ins IntRegs:$Rt32, IntRegs:$Rs32), 1074"$Rd32 = sub($Rt32.h,$Rs32.h):<<16", 1075tc_679309b8, TypeALU64>, Enc_bd6011 { 1076let Inst{7-5} = 0b011; 1077let Inst{13-13} = 0b0; 1078let Inst{31-21} = 0b11010101011; 1079let hasNewValue = 1; 1080let opNewValue = 0; 1081let prefersSlot3 = 1; 1082} 1083def A2_subh_h16_hl : HInst< 1084(outs IntRegs:$Rd32), 1085(ins IntRegs:$Rt32, IntRegs:$Rs32), 1086"$Rd32 = sub($Rt32.h,$Rs32.l):<<16", 1087tc_679309b8, TypeALU64>, Enc_bd6011 { 1088let Inst{7-5} = 0b010; 1089let Inst{13-13} = 0b0; 1090let Inst{31-21} = 0b11010101011; 1091let hasNewValue = 1; 1092let opNewValue = 0; 1093let prefersSlot3 = 1; 1094} 1095def A2_subh_h16_lh : HInst< 1096(outs IntRegs:$Rd32), 1097(ins IntRegs:$Rt32, IntRegs:$Rs32), 1098"$Rd32 = sub($Rt32.l,$Rs32.h):<<16", 1099tc_679309b8, TypeALU64>, Enc_bd6011 { 1100let Inst{7-5} = 0b001; 1101let Inst{13-13} = 0b0; 1102let Inst{31-21} = 0b11010101011; 1103let hasNewValue = 1; 1104let opNewValue = 0; 1105let prefersSlot3 = 1; 1106} 1107def A2_subh_h16_ll : HInst< 1108(outs IntRegs:$Rd32), 1109(ins IntRegs:$Rt32, IntRegs:$Rs32), 1110"$Rd32 = sub($Rt32.l,$Rs32.l):<<16", 1111tc_679309b8, TypeALU64>, Enc_bd6011 { 1112let Inst{7-5} = 0b000; 1113let Inst{13-13} = 0b0; 1114let Inst{31-21} = 0b11010101011; 1115let hasNewValue = 1; 1116let opNewValue = 0; 1117let prefersSlot3 = 1; 1118} 1119def A2_subh_h16_sat_hh : HInst< 1120(outs IntRegs:$Rd32), 1121(ins IntRegs:$Rt32, IntRegs:$Rs32), 1122"$Rd32 = sub($Rt32.h,$Rs32.h):sat:<<16", 1123tc_779080bf, TypeALU64>, Enc_bd6011 { 1124let Inst{7-5} = 0b111; 1125let Inst{13-13} = 0b0; 1126let Inst{31-21} = 0b11010101011; 1127let hasNewValue = 1; 1128let opNewValue = 0; 1129let prefersSlot3 = 1; 1130let Defs = [USR_OVF]; 1131} 1132def A2_subh_h16_sat_hl : HInst< 1133(outs IntRegs:$Rd32), 1134(ins IntRegs:$Rt32, IntRegs:$Rs32), 1135"$Rd32 = sub($Rt32.h,$Rs32.l):sat:<<16", 1136tc_779080bf, TypeALU64>, Enc_bd6011 { 1137let Inst{7-5} = 0b110; 1138let Inst{13-13} = 0b0; 1139let Inst{31-21} = 0b11010101011; 1140let hasNewValue = 1; 1141let opNewValue = 0; 1142let prefersSlot3 = 1; 1143let Defs = [USR_OVF]; 1144} 1145def A2_subh_h16_sat_lh : HInst< 1146(outs IntRegs:$Rd32), 1147(ins IntRegs:$Rt32, IntRegs:$Rs32), 1148"$Rd32 = sub($Rt32.l,$Rs32.h):sat:<<16", 1149tc_779080bf, TypeALU64>, Enc_bd6011 { 1150let Inst{7-5} = 0b101; 1151let Inst{13-13} = 0b0; 1152let Inst{31-21} = 0b11010101011; 1153let hasNewValue = 1; 1154let opNewValue = 0; 1155let prefersSlot3 = 1; 1156let Defs = [USR_OVF]; 1157} 1158def A2_subh_h16_sat_ll : HInst< 1159(outs IntRegs:$Rd32), 1160(ins IntRegs:$Rt32, IntRegs:$Rs32), 1161"$Rd32 = sub($Rt32.l,$Rs32.l):sat:<<16", 1162tc_779080bf, TypeALU64>, Enc_bd6011 { 1163let Inst{7-5} = 0b100; 1164let Inst{13-13} = 0b0; 1165let Inst{31-21} = 0b11010101011; 1166let hasNewValue = 1; 1167let opNewValue = 0; 1168let prefersSlot3 = 1; 1169let Defs = [USR_OVF]; 1170} 1171def A2_subh_l16_hl : HInst< 1172(outs IntRegs:$Rd32), 1173(ins IntRegs:$Rt32, IntRegs:$Rs32), 1174"$Rd32 = sub($Rt32.l,$Rs32.h)", 1175tc_4414d8b1, TypeALU64>, Enc_bd6011 { 1176let Inst{7-5} = 0b010; 1177let Inst{13-13} = 0b0; 1178let Inst{31-21} = 0b11010101001; 1179let hasNewValue = 1; 1180let opNewValue = 0; 1181let prefersSlot3 = 1; 1182} 1183def A2_subh_l16_ll : HInst< 1184(outs IntRegs:$Rd32), 1185(ins IntRegs:$Rt32, IntRegs:$Rs32), 1186"$Rd32 = sub($Rt32.l,$Rs32.l)", 1187tc_4414d8b1, TypeALU64>, Enc_bd6011 { 1188let Inst{7-5} = 0b000; 1189let Inst{13-13} = 0b0; 1190let Inst{31-21} = 0b11010101001; 1191let hasNewValue = 1; 1192let opNewValue = 0; 1193let prefersSlot3 = 1; 1194} 1195def A2_subh_l16_sat_hl : HInst< 1196(outs IntRegs:$Rd32), 1197(ins IntRegs:$Rt32, IntRegs:$Rs32), 1198"$Rd32 = sub($Rt32.l,$Rs32.h):sat", 1199tc_779080bf, TypeALU64>, Enc_bd6011 { 1200let Inst{7-5} = 0b110; 1201let Inst{13-13} = 0b0; 1202let Inst{31-21} = 0b11010101001; 1203let hasNewValue = 1; 1204let opNewValue = 0; 1205let prefersSlot3 = 1; 1206let Defs = [USR_OVF]; 1207} 1208def A2_subh_l16_sat_ll : HInst< 1209(outs IntRegs:$Rd32), 1210(ins IntRegs:$Rt32, IntRegs:$Rs32), 1211"$Rd32 = sub($Rt32.l,$Rs32.l):sat", 1212tc_779080bf, TypeALU64>, Enc_bd6011 { 1213let Inst{7-5} = 0b100; 1214let Inst{13-13} = 0b0; 1215let Inst{31-21} = 0b11010101001; 1216let hasNewValue = 1; 1217let opNewValue = 0; 1218let prefersSlot3 = 1; 1219let Defs = [USR_OVF]; 1220} 1221def A2_subp : HInst< 1222(outs DoubleRegs:$Rdd32), 1223(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), 1224"$Rdd32 = sub($Rtt32,$Rss32)", 1225tc_946df596, TypeALU64>, Enc_ea23e4 { 1226let Inst{7-5} = 0b111; 1227let Inst{13-13} = 0b0; 1228let Inst{31-21} = 0b11010011001; 1229} 1230def A2_subri : HInst< 1231(outs IntRegs:$Rd32), 1232(ins s32_0Imm:$Ii, IntRegs:$Rs32), 1233"$Rd32 = sub(#$Ii,$Rs32)", 1234tc_5a2711e5, TypeALU32_2op>, Enc_140c83, PredNewRel, ImmRegRel { 1235let Inst{31-22} = 0b0111011001; 1236let hasNewValue = 1; 1237let opNewValue = 0; 1238let CextOpcode = "A2_sub"; 1239let InputType = "imm"; 1240let isExtendable = 1; 1241let opExtendable = 1; 1242let isExtentSigned = 1; 1243let opExtentBits = 10; 1244let opExtentAlign = 0; 1245} 1246def A2_subsat : HInst< 1247(outs IntRegs:$Rd32), 1248(ins IntRegs:$Rt32, IntRegs:$Rs32), 1249"$Rd32 = sub($Rt32,$Rs32):sat", 1250tc_61830035, TypeALU32_3op>, Enc_bd6011 { 1251let Inst{7-5} = 0b000; 1252let Inst{13-13} = 0b0; 1253let Inst{31-21} = 0b11110110110; 1254let hasNewValue = 1; 1255let opNewValue = 0; 1256let prefersSlot3 = 1; 1257let Defs = [USR_OVF]; 1258let InputType = "reg"; 1259} 1260def A2_svaddh : HInst< 1261(outs IntRegs:$Rd32), 1262(ins IntRegs:$Rs32, IntRegs:$Rt32), 1263"$Rd32 = vaddh($Rs32,$Rt32)", 1264tc_5a2711e5, TypeALU32_3op>, Enc_5ab2be { 1265let Inst{7-5} = 0b000; 1266let Inst{13-13} = 0b0; 1267let Inst{31-21} = 0b11110110000; 1268let hasNewValue = 1; 1269let opNewValue = 0; 1270let InputType = "reg"; 1271let isCommutable = 1; 1272} 1273def A2_svaddhs : HInst< 1274(outs IntRegs:$Rd32), 1275(ins IntRegs:$Rs32, IntRegs:$Rt32), 1276"$Rd32 = vaddh($Rs32,$Rt32):sat", 1277tc_61830035, TypeALU32_3op>, Enc_5ab2be { 1278let Inst{7-5} = 0b000; 1279let Inst{13-13} = 0b0; 1280let Inst{31-21} = 0b11110110001; 1281let hasNewValue = 1; 1282let opNewValue = 0; 1283let prefersSlot3 = 1; 1284let Defs = [USR_OVF]; 1285let InputType = "reg"; 1286let isCommutable = 1; 1287} 1288def A2_svadduhs : HInst< 1289(outs IntRegs:$Rd32), 1290(ins IntRegs:$Rs32, IntRegs:$Rt32), 1291"$Rd32 = vadduh($Rs32,$Rt32):sat", 1292tc_61830035, TypeALU32_3op>, Enc_5ab2be { 1293let Inst{7-5} = 0b000; 1294let Inst{13-13} = 0b0; 1295let Inst{31-21} = 0b11110110011; 1296let hasNewValue = 1; 1297let opNewValue = 0; 1298let prefersSlot3 = 1; 1299let Defs = [USR_OVF]; 1300let InputType = "reg"; 1301let isCommutable = 1; 1302} 1303def A2_svavgh : HInst< 1304(outs IntRegs:$Rd32), 1305(ins IntRegs:$Rs32, IntRegs:$Rt32), 1306"$Rd32 = vavgh($Rs32,$Rt32)", 1307tc_1c80410a, TypeALU32_3op>, Enc_5ab2be { 1308let Inst{7-5} = 0b000; 1309let Inst{13-13} = 0b0; 1310let Inst{31-21} = 0b11110111000; 1311let hasNewValue = 1; 1312let opNewValue = 0; 1313let prefersSlot3 = 1; 1314let InputType = "reg"; 1315let isCommutable = 1; 1316} 1317def A2_svavghs : HInst< 1318(outs IntRegs:$Rd32), 1319(ins IntRegs:$Rs32, IntRegs:$Rt32), 1320"$Rd32 = vavgh($Rs32,$Rt32):rnd", 1321tc_d08ee0f4, TypeALU32_3op>, Enc_5ab2be { 1322let Inst{7-5} = 0b000; 1323let Inst{13-13} = 0b0; 1324let Inst{31-21} = 0b11110111001; 1325let hasNewValue = 1; 1326let opNewValue = 0; 1327let prefersSlot3 = 1; 1328let InputType = "reg"; 1329let isCommutable = 1; 1330} 1331def A2_svnavgh : HInst< 1332(outs IntRegs:$Rd32), 1333(ins IntRegs:$Rt32, IntRegs:$Rs32), 1334"$Rd32 = vnavgh($Rt32,$Rs32)", 1335tc_1c80410a, TypeALU32_3op>, Enc_bd6011 { 1336let Inst{7-5} = 0b000; 1337let Inst{13-13} = 0b0; 1338let Inst{31-21} = 0b11110111011; 1339let hasNewValue = 1; 1340let opNewValue = 0; 1341let prefersSlot3 = 1; 1342let InputType = "reg"; 1343} 1344def A2_svsubh : HInst< 1345(outs IntRegs:$Rd32), 1346(ins IntRegs:$Rt32, IntRegs:$Rs32), 1347"$Rd32 = vsubh($Rt32,$Rs32)", 1348tc_5a2711e5, TypeALU32_3op>, Enc_bd6011 { 1349let Inst{7-5} = 0b000; 1350let Inst{13-13} = 0b0; 1351let Inst{31-21} = 0b11110110100; 1352let hasNewValue = 1; 1353let opNewValue = 0; 1354let InputType = "reg"; 1355} 1356def A2_svsubhs : HInst< 1357(outs IntRegs:$Rd32), 1358(ins IntRegs:$Rt32, IntRegs:$Rs32), 1359"$Rd32 = vsubh($Rt32,$Rs32):sat", 1360tc_61830035, TypeALU32_3op>, Enc_bd6011 { 1361let Inst{7-5} = 0b000; 1362let Inst{13-13} = 0b0; 1363let Inst{31-21} = 0b11110110101; 1364let hasNewValue = 1; 1365let opNewValue = 0; 1366let prefersSlot3 = 1; 1367let Defs = [USR_OVF]; 1368let InputType = "reg"; 1369} 1370def A2_svsubuhs : HInst< 1371(outs IntRegs:$Rd32), 1372(ins IntRegs:$Rt32, IntRegs:$Rs32), 1373"$Rd32 = vsubuh($Rt32,$Rs32):sat", 1374tc_61830035, TypeALU32_3op>, Enc_bd6011 { 1375let Inst{7-5} = 0b000; 1376let Inst{13-13} = 0b0; 1377let Inst{31-21} = 0b11110110111; 1378let hasNewValue = 1; 1379let opNewValue = 0; 1380let prefersSlot3 = 1; 1381let Defs = [USR_OVF]; 1382let InputType = "reg"; 1383} 1384def A2_swiz : HInst< 1385(outs IntRegs:$Rd32), 1386(ins IntRegs:$Rs32), 1387"$Rd32 = swiz($Rs32)", 1388tc_0ae0825c, TypeS_2op>, Enc_5e2823 { 1389let Inst{13-5} = 0b000000111; 1390let Inst{31-21} = 0b10001100100; 1391let hasNewValue = 1; 1392let opNewValue = 0; 1393} 1394def A2_sxtb : HInst< 1395(outs IntRegs:$Rd32), 1396(ins IntRegs:$Rs32), 1397"$Rd32 = sxtb($Rs32)", 1398tc_57890846, TypeALU32_2op>, Enc_5e2823, PredNewRel { 1399let Inst{13-5} = 0b000000000; 1400let Inst{31-21} = 0b01110000101; 1401let hasNewValue = 1; 1402let opNewValue = 0; 1403let BaseOpcode = "A2_sxtb"; 1404let isPredicable = 1; 1405} 1406def A2_sxth : HInst< 1407(outs IntRegs:$Rd32), 1408(ins IntRegs:$Rs32), 1409"$Rd32 = sxth($Rs32)", 1410tc_57890846, TypeALU32_2op>, Enc_5e2823, PredNewRel { 1411let Inst{13-5} = 0b000000000; 1412let Inst{31-21} = 0b01110000111; 1413let hasNewValue = 1; 1414let opNewValue = 0; 1415let BaseOpcode = "A2_sxth"; 1416let isPredicable = 1; 1417} 1418def A2_sxtw : HInst< 1419(outs DoubleRegs:$Rdd32), 1420(ins IntRegs:$Rs32), 1421"$Rdd32 = sxtw($Rs32)", 1422tc_0ae0825c, TypeS_2op>, Enc_3a3d62 { 1423let Inst{13-5} = 0b000000000; 1424let Inst{31-21} = 0b10000100010; 1425} 1426def A2_tfr : HInst< 1427(outs IntRegs:$Rd32), 1428(ins IntRegs:$Rs32), 1429"$Rd32 = $Rs32", 1430tc_57890846, TypeALU32_2op>, Enc_5e2823, PredNewRel { 1431let Inst{13-5} = 0b000000000; 1432let Inst{31-21} = 0b01110000011; 1433let hasNewValue = 1; 1434let opNewValue = 0; 1435let InputType = "reg"; 1436let BaseOpcode = "A2_tfr"; 1437let isPredicable = 1; 1438} 1439def A2_tfrcrr : HInst< 1440(outs IntRegs:$Rd32), 1441(ins CtrRegs:$Cs32), 1442"$Rd32 = $Cs32", 1443tc_b9272d6c, TypeCR>, Enc_0cb018 { 1444let Inst{13-5} = 0b000000000; 1445let Inst{31-21} = 0b01101010000; 1446let hasNewValue = 1; 1447let opNewValue = 0; 1448} 1449def A2_tfrf : HInst< 1450(outs IntRegs:$Rd32), 1451(ins PredRegs:$Pu4, IntRegs:$Rs32), 1452"if (!$Pu4) $Rd32 = $Rs32", 1453tc_4c5ba658, TypeALU32_2op>, PredNewRel, ImmRegRel { 1454let isPredicated = 1; 1455let isPredicatedFalse = 1; 1456let hasNewValue = 1; 1457let opNewValue = 0; 1458let CextOpcode = "A2_tfr"; 1459let InputType = "reg"; 1460let BaseOpcode = "A2_tfr"; 1461let isPseudo = 1; 1462let isCodeGenOnly = 1; 1463} 1464def A2_tfrfnew : HInst< 1465(outs IntRegs:$Rd32), 1466(ins PredRegs:$Pu4, IntRegs:$Rs32), 1467"if (!$Pu4.new) $Rd32 = $Rs32", 1468tc_05c070ec, TypeALU32_2op>, PredNewRel, ImmRegRel { 1469let isPredicated = 1; 1470let isPredicatedFalse = 1; 1471let hasNewValue = 1; 1472let opNewValue = 0; 1473let isPredicatedNew = 1; 1474let CextOpcode = "A2_tfr"; 1475let InputType = "reg"; 1476let BaseOpcode = "A2_tfr"; 1477let isPseudo = 1; 1478let isCodeGenOnly = 1; 1479} 1480def A2_tfrih : HInst< 1481(outs IntRegs:$Rx32), 1482(ins IntRegs:$Rx32in, u16_0Imm:$Ii), 1483"$Rx32.h = #$Ii", 1484tc_5a2711e5, TypeALU32_2op>, Enc_51436c { 1485let Inst{21-21} = 0b1; 1486let Inst{31-24} = 0b01110010; 1487let hasNewValue = 1; 1488let opNewValue = 0; 1489let Constraints = "$Rx32 = $Rx32in"; 1490} 1491def A2_tfril : HInst< 1492(outs IntRegs:$Rx32), 1493(ins IntRegs:$Rx32in, u16_0Imm:$Ii), 1494"$Rx32.l = #$Ii", 1495tc_5a2711e5, TypeALU32_2op>, Enc_51436c { 1496let Inst{21-21} = 0b1; 1497let Inst{31-24} = 0b01110001; 1498let hasNewValue = 1; 1499let opNewValue = 0; 1500let Constraints = "$Rx32 = $Rx32in"; 1501} 1502def A2_tfrp : HInst< 1503(outs DoubleRegs:$Rdd32), 1504(ins DoubleRegs:$Rss32), 1505"$Rdd32 = $Rss32", 1506tc_5a2711e5, TypeALU32_2op>, PredNewRel { 1507let BaseOpcode = "A2_tfrp"; 1508let isPredicable = 1; 1509let isPseudo = 1; 1510} 1511def A2_tfrpf : HInst< 1512(outs DoubleRegs:$Rdd32), 1513(ins PredRegs:$Pu4, DoubleRegs:$Rss32), 1514"if (!$Pu4) $Rdd32 = $Rss32", 1515tc_5a2711e5, TypeALU32_2op>, PredNewRel { 1516let isPredicated = 1; 1517let isPredicatedFalse = 1; 1518let BaseOpcode = "A2_tfrp"; 1519let isPseudo = 1; 1520} 1521def A2_tfrpfnew : HInst< 1522(outs DoubleRegs:$Rdd32), 1523(ins PredRegs:$Pu4, DoubleRegs:$Rss32), 1524"if (!$Pu4.new) $Rdd32 = $Rss32", 1525tc_1ae57e39, TypeALU32_2op>, PredNewRel { 1526let isPredicated = 1; 1527let isPredicatedFalse = 1; 1528let isPredicatedNew = 1; 1529let BaseOpcode = "A2_tfrp"; 1530let isPseudo = 1; 1531} 1532def A2_tfrpi : HInst< 1533(outs DoubleRegs:$Rdd32), 1534(ins s8_0Imm:$Ii), 1535"$Rdd32 = #$Ii", 1536tc_5a2711e5, TypeALU64> { 1537let isReMaterializable = 1; 1538let isAsCheapAsAMove = 1; 1539let isMoveImm = 1; 1540let isPseudo = 1; 1541} 1542def A2_tfrpt : HInst< 1543(outs DoubleRegs:$Rdd32), 1544(ins PredRegs:$Pu4, DoubleRegs:$Rss32), 1545"if ($Pu4) $Rdd32 = $Rss32", 1546tc_5a2711e5, TypeALU32_2op>, PredNewRel { 1547let isPredicated = 1; 1548let BaseOpcode = "A2_tfrp"; 1549let isPseudo = 1; 1550} 1551def A2_tfrptnew : HInst< 1552(outs DoubleRegs:$Rdd32), 1553(ins PredRegs:$Pu4, DoubleRegs:$Rss32), 1554"if ($Pu4.new) $Rdd32 = $Rss32", 1555tc_1ae57e39, TypeALU32_2op>, PredNewRel { 1556let isPredicated = 1; 1557let isPredicatedNew = 1; 1558let BaseOpcode = "A2_tfrp"; 1559let isPseudo = 1; 1560} 1561def A2_tfrrcr : HInst< 1562(outs CtrRegs:$Cd32), 1563(ins IntRegs:$Rs32), 1564"$Cd32 = $Rs32", 1565tc_434c8e1e, TypeCR>, Enc_bd811a { 1566let Inst{13-5} = 0b000000000; 1567let Inst{31-21} = 0b01100010001; 1568let hasNewValue = 1; 1569let opNewValue = 0; 1570} 1571def A2_tfrsi : HInst< 1572(outs IntRegs:$Rd32), 1573(ins s32_0Imm:$Ii), 1574"$Rd32 = #$Ii", 1575tc_57890846, TypeALU32_2op>, Enc_5e87ce, PredNewRel, ImmRegRel { 1576let Inst{21-21} = 0b0; 1577let Inst{31-24} = 0b01111000; 1578let hasNewValue = 1; 1579let opNewValue = 0; 1580let CextOpcode = "A2_tfr"; 1581let InputType = "imm"; 1582let BaseOpcode = "A2_tfrsi"; 1583let isPredicable = 1; 1584let isReMaterializable = 1; 1585let isAsCheapAsAMove = 1; 1586let isMoveImm = 1; 1587let isExtendable = 1; 1588let opExtendable = 1; 1589let isExtentSigned = 1; 1590let opExtentBits = 16; 1591let opExtentAlign = 0; 1592} 1593def A2_tfrt : HInst< 1594(outs IntRegs:$Rd32), 1595(ins PredRegs:$Pu4, IntRegs:$Rs32), 1596"if ($Pu4) $Rd32 = $Rs32", 1597tc_4c5ba658, TypeALU32_2op>, PredNewRel, ImmRegRel { 1598let isPredicated = 1; 1599let hasNewValue = 1; 1600let opNewValue = 0; 1601let CextOpcode = "A2_tfr"; 1602let InputType = "reg"; 1603let BaseOpcode = "A2_tfr"; 1604let isPseudo = 1; 1605let isCodeGenOnly = 1; 1606} 1607def A2_tfrtnew : HInst< 1608(outs IntRegs:$Rd32), 1609(ins PredRegs:$Pu4, IntRegs:$Rs32), 1610"if ($Pu4.new) $Rd32 = $Rs32", 1611tc_05c070ec, TypeALU32_2op>, PredNewRel, ImmRegRel { 1612let isPredicated = 1; 1613let hasNewValue = 1; 1614let opNewValue = 0; 1615let isPredicatedNew = 1; 1616let CextOpcode = "A2_tfr"; 1617let InputType = "reg"; 1618let BaseOpcode = "A2_tfr"; 1619let isPseudo = 1; 1620let isCodeGenOnly = 1; 1621} 1622def A2_vabsh : HInst< 1623(outs DoubleRegs:$Rdd32), 1624(ins DoubleRegs:$Rss32), 1625"$Rdd32 = vabsh($Rss32)", 1626tc_cf8126ae, TypeS_2op>, Enc_b9c5fb { 1627let Inst{13-5} = 0b000000100; 1628let Inst{31-21} = 0b10000000010; 1629let prefersSlot3 = 1; 1630} 1631def A2_vabshsat : HInst< 1632(outs DoubleRegs:$Rdd32), 1633(ins DoubleRegs:$Rss32), 1634"$Rdd32 = vabsh($Rss32):sat", 1635tc_cf8126ae, TypeS_2op>, Enc_b9c5fb { 1636let Inst{13-5} = 0b000000101; 1637let Inst{31-21} = 0b10000000010; 1638let prefersSlot3 = 1; 1639let Defs = [USR_OVF]; 1640} 1641def A2_vabsw : HInst< 1642(outs DoubleRegs:$Rdd32), 1643(ins DoubleRegs:$Rss32), 1644"$Rdd32 = vabsw($Rss32)", 1645tc_cf8126ae, TypeS_2op>, Enc_b9c5fb { 1646let Inst{13-5} = 0b000000110; 1647let Inst{31-21} = 0b10000000010; 1648let prefersSlot3 = 1; 1649} 1650def A2_vabswsat : HInst< 1651(outs DoubleRegs:$Rdd32), 1652(ins DoubleRegs:$Rss32), 1653"$Rdd32 = vabsw($Rss32):sat", 1654tc_cf8126ae, TypeS_2op>, Enc_b9c5fb { 1655let Inst{13-5} = 0b000000111; 1656let Inst{31-21} = 0b10000000010; 1657let prefersSlot3 = 1; 1658let Defs = [USR_OVF]; 1659} 1660def A2_vaddb_map : HInst< 1661(outs DoubleRegs:$Rdd32), 1662(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 1663"$Rdd32 = vaddb($Rss32,$Rtt32)", 1664tc_946df596, TypeMAPPING> { 1665let isPseudo = 1; 1666let isCodeGenOnly = 1; 1667} 1668def A2_vaddh : HInst< 1669(outs DoubleRegs:$Rdd32), 1670(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 1671"$Rdd32 = vaddh($Rss32,$Rtt32)", 1672tc_946df596, TypeALU64>, Enc_a56825 { 1673let Inst{7-5} = 0b010; 1674let Inst{13-13} = 0b0; 1675let Inst{31-21} = 0b11010011000; 1676} 1677def A2_vaddhs : HInst< 1678(outs DoubleRegs:$Rdd32), 1679(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 1680"$Rdd32 = vaddh($Rss32,$Rtt32):sat", 1681tc_779080bf, TypeALU64>, Enc_a56825 { 1682let Inst{7-5} = 0b011; 1683let Inst{13-13} = 0b0; 1684let Inst{31-21} = 0b11010011000; 1685let prefersSlot3 = 1; 1686let Defs = [USR_OVF]; 1687} 1688def A2_vaddub : HInst< 1689(outs DoubleRegs:$Rdd32), 1690(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 1691"$Rdd32 = vaddub($Rss32,$Rtt32)", 1692tc_946df596, TypeALU64>, Enc_a56825 { 1693let Inst{7-5} = 0b000; 1694let Inst{13-13} = 0b0; 1695let Inst{31-21} = 0b11010011000; 1696} 1697def A2_vaddubs : HInst< 1698(outs DoubleRegs:$Rdd32), 1699(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 1700"$Rdd32 = vaddub($Rss32,$Rtt32):sat", 1701tc_779080bf, TypeALU64>, Enc_a56825 { 1702let Inst{7-5} = 0b001; 1703let Inst{13-13} = 0b0; 1704let Inst{31-21} = 0b11010011000; 1705let prefersSlot3 = 1; 1706let Defs = [USR_OVF]; 1707} 1708def A2_vadduhs : HInst< 1709(outs DoubleRegs:$Rdd32), 1710(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 1711"$Rdd32 = vadduh($Rss32,$Rtt32):sat", 1712tc_779080bf, TypeALU64>, Enc_a56825 { 1713let Inst{7-5} = 0b100; 1714let Inst{13-13} = 0b0; 1715let Inst{31-21} = 0b11010011000; 1716let prefersSlot3 = 1; 1717let Defs = [USR_OVF]; 1718} 1719def A2_vaddw : HInst< 1720(outs DoubleRegs:$Rdd32), 1721(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 1722"$Rdd32 = vaddw($Rss32,$Rtt32)", 1723tc_946df596, TypeALU64>, Enc_a56825 { 1724let Inst{7-5} = 0b101; 1725let Inst{13-13} = 0b0; 1726let Inst{31-21} = 0b11010011000; 1727} 1728def A2_vaddws : HInst< 1729(outs DoubleRegs:$Rdd32), 1730(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 1731"$Rdd32 = vaddw($Rss32,$Rtt32):sat", 1732tc_779080bf, TypeALU64>, Enc_a56825 { 1733let Inst{7-5} = 0b110; 1734let Inst{13-13} = 0b0; 1735let Inst{31-21} = 0b11010011000; 1736let prefersSlot3 = 1; 1737let Defs = [USR_OVF]; 1738} 1739def A2_vavgh : HInst< 1740(outs DoubleRegs:$Rdd32), 1741(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 1742"$Rdd32 = vavgh($Rss32,$Rtt32)", 1743tc_6132ba3d, TypeALU64>, Enc_a56825 { 1744let Inst{7-5} = 0b010; 1745let Inst{13-13} = 0b0; 1746let Inst{31-21} = 0b11010011010; 1747let prefersSlot3 = 1; 1748} 1749def A2_vavghcr : HInst< 1750(outs DoubleRegs:$Rdd32), 1751(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 1752"$Rdd32 = vavgh($Rss32,$Rtt32):crnd", 1753tc_002cb246, TypeALU64>, Enc_a56825 { 1754let Inst{7-5} = 0b100; 1755let Inst{13-13} = 0b0; 1756let Inst{31-21} = 0b11010011010; 1757let prefersSlot3 = 1; 1758} 1759def A2_vavghr : HInst< 1760(outs DoubleRegs:$Rdd32), 1761(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 1762"$Rdd32 = vavgh($Rss32,$Rtt32):rnd", 1763tc_e4a7f9f0, TypeALU64>, Enc_a56825 { 1764let Inst{7-5} = 0b011; 1765let Inst{13-13} = 0b0; 1766let Inst{31-21} = 0b11010011010; 1767let prefersSlot3 = 1; 1768} 1769def A2_vavgub : HInst< 1770(outs DoubleRegs:$Rdd32), 1771(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 1772"$Rdd32 = vavgub($Rss32,$Rtt32)", 1773tc_6132ba3d, TypeALU64>, Enc_a56825 { 1774let Inst{7-5} = 0b000; 1775let Inst{13-13} = 0b0; 1776let Inst{31-21} = 0b11010011010; 1777let prefersSlot3 = 1; 1778} 1779def A2_vavgubr : HInst< 1780(outs DoubleRegs:$Rdd32), 1781(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 1782"$Rdd32 = vavgub($Rss32,$Rtt32):rnd", 1783tc_e4a7f9f0, TypeALU64>, Enc_a56825 { 1784let Inst{7-5} = 0b001; 1785let Inst{13-13} = 0b0; 1786let Inst{31-21} = 0b11010011010; 1787let prefersSlot3 = 1; 1788} 1789def A2_vavguh : HInst< 1790(outs DoubleRegs:$Rdd32), 1791(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 1792"$Rdd32 = vavguh($Rss32,$Rtt32)", 1793tc_6132ba3d, TypeALU64>, Enc_a56825 { 1794let Inst{7-5} = 0b101; 1795let Inst{13-13} = 0b0; 1796let Inst{31-21} = 0b11010011010; 1797let prefersSlot3 = 1; 1798} 1799def A2_vavguhr : HInst< 1800(outs DoubleRegs:$Rdd32), 1801(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 1802"$Rdd32 = vavguh($Rss32,$Rtt32):rnd", 1803tc_e4a7f9f0, TypeALU64>, Enc_a56825 { 1804let Inst{7-5} = 0b110; 1805let Inst{13-13} = 0b0; 1806let Inst{31-21} = 0b11010011010; 1807let prefersSlot3 = 1; 1808} 1809def A2_vavguw : HInst< 1810(outs DoubleRegs:$Rdd32), 1811(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 1812"$Rdd32 = vavguw($Rss32,$Rtt32)", 1813tc_6132ba3d, TypeALU64>, Enc_a56825 { 1814let Inst{7-5} = 0b011; 1815let Inst{13-13} = 0b0; 1816let Inst{31-21} = 0b11010011011; 1817let prefersSlot3 = 1; 1818} 1819def A2_vavguwr : HInst< 1820(outs DoubleRegs:$Rdd32), 1821(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 1822"$Rdd32 = vavguw($Rss32,$Rtt32):rnd", 1823tc_e4a7f9f0, TypeALU64>, Enc_a56825 { 1824let Inst{7-5} = 0b100; 1825let Inst{13-13} = 0b0; 1826let Inst{31-21} = 0b11010011011; 1827let prefersSlot3 = 1; 1828} 1829def A2_vavgw : HInst< 1830(outs DoubleRegs:$Rdd32), 1831(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 1832"$Rdd32 = vavgw($Rss32,$Rtt32)", 1833tc_6132ba3d, TypeALU64>, Enc_a56825 { 1834let Inst{7-5} = 0b000; 1835let Inst{13-13} = 0b0; 1836let Inst{31-21} = 0b11010011011; 1837let prefersSlot3 = 1; 1838} 1839def A2_vavgwcr : HInst< 1840(outs DoubleRegs:$Rdd32), 1841(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 1842"$Rdd32 = vavgw($Rss32,$Rtt32):crnd", 1843tc_002cb246, TypeALU64>, Enc_a56825 { 1844let Inst{7-5} = 0b010; 1845let Inst{13-13} = 0b0; 1846let Inst{31-21} = 0b11010011011; 1847let prefersSlot3 = 1; 1848} 1849def A2_vavgwr : HInst< 1850(outs DoubleRegs:$Rdd32), 1851(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 1852"$Rdd32 = vavgw($Rss32,$Rtt32):rnd", 1853tc_e4a7f9f0, TypeALU64>, Enc_a56825 { 1854let Inst{7-5} = 0b001; 1855let Inst{13-13} = 0b0; 1856let Inst{31-21} = 0b11010011011; 1857let prefersSlot3 = 1; 1858} 1859def A2_vcmpbeq : HInst< 1860(outs PredRegs:$Pd4), 1861(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 1862"$Pd4 = vcmpb.eq($Rss32,$Rtt32)", 1863tc_85d5d03f, TypeALU64>, Enc_fcf7a7 { 1864let Inst{7-2} = 0b110000; 1865let Inst{13-13} = 0b0; 1866let Inst{31-21} = 0b11010010000; 1867} 1868def A2_vcmpbgtu : HInst< 1869(outs PredRegs:$Pd4), 1870(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 1871"$Pd4 = vcmpb.gtu($Rss32,$Rtt32)", 1872tc_85d5d03f, TypeALU64>, Enc_fcf7a7 { 1873let Inst{7-2} = 0b111000; 1874let Inst{13-13} = 0b0; 1875let Inst{31-21} = 0b11010010000; 1876} 1877def A2_vcmpheq : HInst< 1878(outs PredRegs:$Pd4), 1879(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 1880"$Pd4 = vcmph.eq($Rss32,$Rtt32)", 1881tc_85d5d03f, TypeALU64>, Enc_fcf7a7 { 1882let Inst{7-2} = 0b011000; 1883let Inst{13-13} = 0b0; 1884let Inst{31-21} = 0b11010010000; 1885} 1886def A2_vcmphgt : HInst< 1887(outs PredRegs:$Pd4), 1888(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 1889"$Pd4 = vcmph.gt($Rss32,$Rtt32)", 1890tc_85d5d03f, TypeALU64>, Enc_fcf7a7 { 1891let Inst{7-2} = 0b100000; 1892let Inst{13-13} = 0b0; 1893let Inst{31-21} = 0b11010010000; 1894} 1895def A2_vcmphgtu : HInst< 1896(outs PredRegs:$Pd4), 1897(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 1898"$Pd4 = vcmph.gtu($Rss32,$Rtt32)", 1899tc_85d5d03f, TypeALU64>, Enc_fcf7a7 { 1900let Inst{7-2} = 0b101000; 1901let Inst{13-13} = 0b0; 1902let Inst{31-21} = 0b11010010000; 1903} 1904def A2_vcmpweq : HInst< 1905(outs PredRegs:$Pd4), 1906(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 1907"$Pd4 = vcmpw.eq($Rss32,$Rtt32)", 1908tc_85d5d03f, TypeALU64>, Enc_fcf7a7 { 1909let Inst{7-2} = 0b000000; 1910let Inst{13-13} = 0b0; 1911let Inst{31-21} = 0b11010010000; 1912} 1913def A2_vcmpwgt : HInst< 1914(outs PredRegs:$Pd4), 1915(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 1916"$Pd4 = vcmpw.gt($Rss32,$Rtt32)", 1917tc_85d5d03f, TypeALU64>, Enc_fcf7a7 { 1918let Inst{7-2} = 0b001000; 1919let Inst{13-13} = 0b0; 1920let Inst{31-21} = 0b11010010000; 1921} 1922def A2_vcmpwgtu : HInst< 1923(outs PredRegs:$Pd4), 1924(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 1925"$Pd4 = vcmpw.gtu($Rss32,$Rtt32)", 1926tc_85d5d03f, TypeALU64>, Enc_fcf7a7 { 1927let Inst{7-2} = 0b010000; 1928let Inst{13-13} = 0b0; 1929let Inst{31-21} = 0b11010010000; 1930} 1931def A2_vconj : HInst< 1932(outs DoubleRegs:$Rdd32), 1933(ins DoubleRegs:$Rss32), 1934"$Rdd32 = vconj($Rss32):sat", 1935tc_cf8126ae, TypeS_2op>, Enc_b9c5fb { 1936let Inst{13-5} = 0b000000111; 1937let Inst{31-21} = 0b10000000100; 1938let prefersSlot3 = 1; 1939let Defs = [USR_OVF]; 1940} 1941def A2_vmaxb : HInst< 1942(outs DoubleRegs:$Rdd32), 1943(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), 1944"$Rdd32 = vmaxb($Rtt32,$Rss32)", 1945tc_779080bf, TypeALU64>, Enc_ea23e4 { 1946let Inst{7-5} = 0b110; 1947let Inst{13-13} = 0b0; 1948let Inst{31-21} = 0b11010011110; 1949let prefersSlot3 = 1; 1950} 1951def A2_vmaxh : HInst< 1952(outs DoubleRegs:$Rdd32), 1953(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), 1954"$Rdd32 = vmaxh($Rtt32,$Rss32)", 1955tc_779080bf, TypeALU64>, Enc_ea23e4 { 1956let Inst{7-5} = 0b001; 1957let Inst{13-13} = 0b0; 1958let Inst{31-21} = 0b11010011110; 1959let prefersSlot3 = 1; 1960} 1961def A2_vmaxub : HInst< 1962(outs DoubleRegs:$Rdd32), 1963(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), 1964"$Rdd32 = vmaxub($Rtt32,$Rss32)", 1965tc_779080bf, TypeALU64>, Enc_ea23e4 { 1966let Inst{7-5} = 0b000; 1967let Inst{13-13} = 0b0; 1968let Inst{31-21} = 0b11010011110; 1969let prefersSlot3 = 1; 1970} 1971def A2_vmaxuh : HInst< 1972(outs DoubleRegs:$Rdd32), 1973(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), 1974"$Rdd32 = vmaxuh($Rtt32,$Rss32)", 1975tc_779080bf, TypeALU64>, Enc_ea23e4 { 1976let Inst{7-5} = 0b010; 1977let Inst{13-13} = 0b0; 1978let Inst{31-21} = 0b11010011110; 1979let prefersSlot3 = 1; 1980} 1981def A2_vmaxuw : HInst< 1982(outs DoubleRegs:$Rdd32), 1983(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), 1984"$Rdd32 = vmaxuw($Rtt32,$Rss32)", 1985tc_779080bf, TypeALU64>, Enc_ea23e4 { 1986let Inst{7-5} = 0b101; 1987let Inst{13-13} = 0b0; 1988let Inst{31-21} = 0b11010011101; 1989let prefersSlot3 = 1; 1990} 1991def A2_vmaxw : HInst< 1992(outs DoubleRegs:$Rdd32), 1993(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), 1994"$Rdd32 = vmaxw($Rtt32,$Rss32)", 1995tc_779080bf, TypeALU64>, Enc_ea23e4 { 1996let Inst{7-5} = 0b011; 1997let Inst{13-13} = 0b0; 1998let Inst{31-21} = 0b11010011110; 1999let prefersSlot3 = 1; 2000} 2001def A2_vminb : HInst< 2002(outs DoubleRegs:$Rdd32), 2003(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), 2004"$Rdd32 = vminb($Rtt32,$Rss32)", 2005tc_779080bf, TypeALU64>, Enc_ea23e4 { 2006let Inst{7-5} = 0b111; 2007let Inst{13-13} = 0b0; 2008let Inst{31-21} = 0b11010011110; 2009let prefersSlot3 = 1; 2010} 2011def A2_vminh : HInst< 2012(outs DoubleRegs:$Rdd32), 2013(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), 2014"$Rdd32 = vminh($Rtt32,$Rss32)", 2015tc_779080bf, TypeALU64>, Enc_ea23e4 { 2016let Inst{7-5} = 0b001; 2017let Inst{13-13} = 0b0; 2018let Inst{31-21} = 0b11010011101; 2019let prefersSlot3 = 1; 2020} 2021def A2_vminub : HInst< 2022(outs DoubleRegs:$Rdd32), 2023(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), 2024"$Rdd32 = vminub($Rtt32,$Rss32)", 2025tc_779080bf, TypeALU64>, Enc_ea23e4 { 2026let Inst{7-5} = 0b000; 2027let Inst{13-13} = 0b0; 2028let Inst{31-21} = 0b11010011101; 2029let prefersSlot3 = 1; 2030} 2031def A2_vminuh : HInst< 2032(outs DoubleRegs:$Rdd32), 2033(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), 2034"$Rdd32 = vminuh($Rtt32,$Rss32)", 2035tc_779080bf, TypeALU64>, Enc_ea23e4 { 2036let Inst{7-5} = 0b010; 2037let Inst{13-13} = 0b0; 2038let Inst{31-21} = 0b11010011101; 2039let prefersSlot3 = 1; 2040} 2041def A2_vminuw : HInst< 2042(outs DoubleRegs:$Rdd32), 2043(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), 2044"$Rdd32 = vminuw($Rtt32,$Rss32)", 2045tc_779080bf, TypeALU64>, Enc_ea23e4 { 2046let Inst{7-5} = 0b100; 2047let Inst{13-13} = 0b0; 2048let Inst{31-21} = 0b11010011101; 2049let prefersSlot3 = 1; 2050} 2051def A2_vminw : HInst< 2052(outs DoubleRegs:$Rdd32), 2053(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), 2054"$Rdd32 = vminw($Rtt32,$Rss32)", 2055tc_779080bf, TypeALU64>, Enc_ea23e4 { 2056let Inst{7-5} = 0b011; 2057let Inst{13-13} = 0b0; 2058let Inst{31-21} = 0b11010011101; 2059let prefersSlot3 = 1; 2060} 2061def A2_vnavgh : HInst< 2062(outs DoubleRegs:$Rdd32), 2063(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), 2064"$Rdd32 = vnavgh($Rtt32,$Rss32)", 2065tc_6132ba3d, TypeALU64>, Enc_ea23e4 { 2066let Inst{7-5} = 0b000; 2067let Inst{13-13} = 0b0; 2068let Inst{31-21} = 0b11010011100; 2069let prefersSlot3 = 1; 2070} 2071def A2_vnavghcr : HInst< 2072(outs DoubleRegs:$Rdd32), 2073(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), 2074"$Rdd32 = vnavgh($Rtt32,$Rss32):crnd:sat", 2075tc_002cb246, TypeALU64>, Enc_ea23e4 { 2076let Inst{7-5} = 0b010; 2077let Inst{13-13} = 0b0; 2078let Inst{31-21} = 0b11010011100; 2079let prefersSlot3 = 1; 2080let Defs = [USR_OVF]; 2081} 2082def A2_vnavghr : HInst< 2083(outs DoubleRegs:$Rdd32), 2084(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), 2085"$Rdd32 = vnavgh($Rtt32,$Rss32):rnd:sat", 2086tc_002cb246, TypeALU64>, Enc_ea23e4 { 2087let Inst{7-5} = 0b001; 2088let Inst{13-13} = 0b0; 2089let Inst{31-21} = 0b11010011100; 2090let prefersSlot3 = 1; 2091let Defs = [USR_OVF]; 2092} 2093def A2_vnavgw : HInst< 2094(outs DoubleRegs:$Rdd32), 2095(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), 2096"$Rdd32 = vnavgw($Rtt32,$Rss32)", 2097tc_6132ba3d, TypeALU64>, Enc_ea23e4 { 2098let Inst{7-5} = 0b011; 2099let Inst{13-13} = 0b0; 2100let Inst{31-21} = 0b11010011100; 2101let prefersSlot3 = 1; 2102} 2103def A2_vnavgwcr : HInst< 2104(outs DoubleRegs:$Rdd32), 2105(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), 2106"$Rdd32 = vnavgw($Rtt32,$Rss32):crnd:sat", 2107tc_002cb246, TypeALU64>, Enc_ea23e4 { 2108let Inst{7-5} = 0b110; 2109let Inst{13-13} = 0b0; 2110let Inst{31-21} = 0b11010011100; 2111let prefersSlot3 = 1; 2112let Defs = [USR_OVF]; 2113} 2114def A2_vnavgwr : HInst< 2115(outs DoubleRegs:$Rdd32), 2116(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), 2117"$Rdd32 = vnavgw($Rtt32,$Rss32):rnd:sat", 2118tc_002cb246, TypeALU64>, Enc_ea23e4 { 2119let Inst{7-5} = 0b100; 2120let Inst{13-13} = 0b0; 2121let Inst{31-21} = 0b11010011100; 2122let prefersSlot3 = 1; 2123let Defs = [USR_OVF]; 2124} 2125def A2_vraddub : HInst< 2126(outs DoubleRegs:$Rdd32), 2127(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 2128"$Rdd32 = vraddub($Rss32,$Rtt32)", 2129tc_bafaade3, TypeM>, Enc_a56825 { 2130let Inst{7-5} = 0b001; 2131let Inst{13-13} = 0b0; 2132let Inst{31-21} = 0b11101000010; 2133let prefersSlot3 = 1; 2134} 2135def A2_vraddub_acc : HInst< 2136(outs DoubleRegs:$Rxx32), 2137(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 2138"$Rxx32 += vraddub($Rss32,$Rtt32)", 2139tc_d773585a, TypeM>, Enc_88c16c { 2140let Inst{7-5} = 0b001; 2141let Inst{13-13} = 0b0; 2142let Inst{31-21} = 0b11101010010; 2143let prefersSlot3 = 1; 2144let Constraints = "$Rxx32 = $Rxx32in"; 2145} 2146def A2_vrsadub : HInst< 2147(outs DoubleRegs:$Rdd32), 2148(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 2149"$Rdd32 = vrsadub($Rss32,$Rtt32)", 2150tc_bafaade3, TypeM>, Enc_a56825 { 2151let Inst{7-5} = 0b010; 2152let Inst{13-13} = 0b0; 2153let Inst{31-21} = 0b11101000010; 2154let prefersSlot3 = 1; 2155} 2156def A2_vrsadub_acc : HInst< 2157(outs DoubleRegs:$Rxx32), 2158(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 2159"$Rxx32 += vrsadub($Rss32,$Rtt32)", 2160tc_d773585a, TypeM>, Enc_88c16c { 2161let Inst{7-5} = 0b010; 2162let Inst{13-13} = 0b0; 2163let Inst{31-21} = 0b11101010010; 2164let prefersSlot3 = 1; 2165let Constraints = "$Rxx32 = $Rxx32in"; 2166} 2167def A2_vsubb_map : HInst< 2168(outs DoubleRegs:$Rdd32), 2169(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 2170"$Rdd32 = vsubb($Rss32,$Rtt32)", 2171tc_946df596, TypeMAPPING> { 2172let isPseudo = 1; 2173let isCodeGenOnly = 1; 2174} 2175def A2_vsubh : HInst< 2176(outs DoubleRegs:$Rdd32), 2177(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), 2178"$Rdd32 = vsubh($Rtt32,$Rss32)", 2179tc_946df596, TypeALU64>, Enc_ea23e4 { 2180let Inst{7-5} = 0b010; 2181let Inst{13-13} = 0b0; 2182let Inst{31-21} = 0b11010011001; 2183} 2184def A2_vsubhs : HInst< 2185(outs DoubleRegs:$Rdd32), 2186(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), 2187"$Rdd32 = vsubh($Rtt32,$Rss32):sat", 2188tc_779080bf, TypeALU64>, Enc_ea23e4 { 2189let Inst{7-5} = 0b011; 2190let Inst{13-13} = 0b0; 2191let Inst{31-21} = 0b11010011001; 2192let prefersSlot3 = 1; 2193let Defs = [USR_OVF]; 2194} 2195def A2_vsubub : HInst< 2196(outs DoubleRegs:$Rdd32), 2197(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), 2198"$Rdd32 = vsubub($Rtt32,$Rss32)", 2199tc_946df596, TypeALU64>, Enc_ea23e4 { 2200let Inst{7-5} = 0b000; 2201let Inst{13-13} = 0b0; 2202let Inst{31-21} = 0b11010011001; 2203} 2204def A2_vsububs : HInst< 2205(outs DoubleRegs:$Rdd32), 2206(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), 2207"$Rdd32 = vsubub($Rtt32,$Rss32):sat", 2208tc_779080bf, TypeALU64>, Enc_ea23e4 { 2209let Inst{7-5} = 0b001; 2210let Inst{13-13} = 0b0; 2211let Inst{31-21} = 0b11010011001; 2212let prefersSlot3 = 1; 2213let Defs = [USR_OVF]; 2214} 2215def A2_vsubuhs : HInst< 2216(outs DoubleRegs:$Rdd32), 2217(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), 2218"$Rdd32 = vsubuh($Rtt32,$Rss32):sat", 2219tc_779080bf, TypeALU64>, Enc_ea23e4 { 2220let Inst{7-5} = 0b100; 2221let Inst{13-13} = 0b0; 2222let Inst{31-21} = 0b11010011001; 2223let prefersSlot3 = 1; 2224let Defs = [USR_OVF]; 2225} 2226def A2_vsubw : HInst< 2227(outs DoubleRegs:$Rdd32), 2228(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), 2229"$Rdd32 = vsubw($Rtt32,$Rss32)", 2230tc_946df596, TypeALU64>, Enc_ea23e4 { 2231let Inst{7-5} = 0b101; 2232let Inst{13-13} = 0b0; 2233let Inst{31-21} = 0b11010011001; 2234} 2235def A2_vsubws : HInst< 2236(outs DoubleRegs:$Rdd32), 2237(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), 2238"$Rdd32 = vsubw($Rtt32,$Rss32):sat", 2239tc_779080bf, TypeALU64>, Enc_ea23e4 { 2240let Inst{7-5} = 0b110; 2241let Inst{13-13} = 0b0; 2242let Inst{31-21} = 0b11010011001; 2243let prefersSlot3 = 1; 2244let Defs = [USR_OVF]; 2245} 2246def A2_xor : HInst< 2247(outs IntRegs:$Rd32), 2248(ins IntRegs:$Rs32, IntRegs:$Rt32), 2249"$Rd32 = xor($Rs32,$Rt32)", 2250tc_5a2711e5, TypeALU32_3op>, Enc_5ab2be, PredNewRel { 2251let Inst{7-5} = 0b000; 2252let Inst{13-13} = 0b0; 2253let Inst{31-21} = 0b11110001011; 2254let hasNewValue = 1; 2255let opNewValue = 0; 2256let InputType = "reg"; 2257let BaseOpcode = "A2_xor"; 2258let isCommutable = 1; 2259let isPredicable = 1; 2260} 2261def A2_xorp : HInst< 2262(outs DoubleRegs:$Rdd32), 2263(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 2264"$Rdd32 = xor($Rss32,$Rtt32)", 2265tc_946df596, TypeALU64>, Enc_a56825 { 2266let Inst{7-5} = 0b100; 2267let Inst{13-13} = 0b0; 2268let Inst{31-21} = 0b11010011111; 2269let isCommutable = 1; 2270} 2271def A2_zxtb : HInst< 2272(outs IntRegs:$Rd32), 2273(ins IntRegs:$Rs32), 2274"$Rd32 = zxtb($Rs32)", 2275tc_5a2711e5, TypeALU32_2op>, PredNewRel { 2276let hasNewValue = 1; 2277let opNewValue = 0; 2278let BaseOpcode = "A2_zxtb"; 2279let isPredicable = 1; 2280let isPseudo = 1; 2281let isCodeGenOnly = 1; 2282} 2283def A2_zxth : HInst< 2284(outs IntRegs:$Rd32), 2285(ins IntRegs:$Rs32), 2286"$Rd32 = zxth($Rs32)", 2287tc_57890846, TypeALU32_2op>, Enc_5e2823, PredNewRel { 2288let Inst{13-5} = 0b000000000; 2289let Inst{31-21} = 0b01110000110; 2290let hasNewValue = 1; 2291let opNewValue = 0; 2292let BaseOpcode = "A2_zxth"; 2293let isPredicable = 1; 2294} 2295def A4_addp_c : HInst< 2296(outs DoubleRegs:$Rdd32, PredRegs:$Px4), 2297(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32, PredRegs:$Px4in), 2298"$Rdd32 = add($Rss32,$Rtt32,$Px4):carry", 2299tc_9c3ecd83, TypeS_3op>, Enc_2b3f60 { 2300let Inst{7-7} = 0b0; 2301let Inst{13-13} = 0b0; 2302let Inst{31-21} = 0b11000010110; 2303let isPredicateLate = 1; 2304let Constraints = "$Px4 = $Px4in"; 2305} 2306def A4_andn : HInst< 2307(outs IntRegs:$Rd32), 2308(ins IntRegs:$Rt32, IntRegs:$Rs32), 2309"$Rd32 = and($Rt32,~$Rs32)", 2310tc_5a2711e5, TypeALU32_3op>, Enc_bd6011 { 2311let Inst{7-5} = 0b000; 2312let Inst{13-13} = 0b0; 2313let Inst{31-21} = 0b11110001100; 2314let hasNewValue = 1; 2315let opNewValue = 0; 2316let InputType = "reg"; 2317} 2318def A4_andnp : HInst< 2319(outs DoubleRegs:$Rdd32), 2320(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), 2321"$Rdd32 = and($Rtt32,~$Rss32)", 2322tc_946df596, TypeALU64>, Enc_ea23e4 { 2323let Inst{7-5} = 0b001; 2324let Inst{13-13} = 0b0; 2325let Inst{31-21} = 0b11010011111; 2326} 2327def A4_bitsplit : HInst< 2328(outs DoubleRegs:$Rdd32), 2329(ins IntRegs:$Rs32, IntRegs:$Rt32), 2330"$Rdd32 = bitsplit($Rs32,$Rt32)", 2331tc_4414d8b1, TypeALU64>, Enc_be32a5 { 2332let Inst{7-5} = 0b000; 2333let Inst{13-13} = 0b0; 2334let Inst{31-21} = 0b11010100001; 2335let prefersSlot3 = 1; 2336} 2337def A4_bitspliti : HInst< 2338(outs DoubleRegs:$Rdd32), 2339(ins IntRegs:$Rs32, u5_0Imm:$Ii), 2340"$Rdd32 = bitsplit($Rs32,#$Ii)", 2341tc_4414d8b1, TypeS_2op>, Enc_311abd { 2342let Inst{7-5} = 0b100; 2343let Inst{13-13} = 0b0; 2344let Inst{31-21} = 0b10001000110; 2345let prefersSlot3 = 1; 2346} 2347def A4_boundscheck : HInst< 2348(outs PredRegs:$Pd4), 2349(ins IntRegs:$Rs32, DoubleRegs:$Rtt32), 2350"$Pd4 = boundscheck($Rs32,$Rtt32)", 2351tc_85d5d03f, TypeALU64> { 2352let isPseudo = 1; 2353} 2354def A4_boundscheck_hi : HInst< 2355(outs PredRegs:$Pd4), 2356(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 2357"$Pd4 = boundscheck($Rss32,$Rtt32):raw:hi", 2358tc_85d5d03f, TypeALU64>, Enc_fcf7a7 { 2359let Inst{7-2} = 0b101000; 2360let Inst{13-13} = 0b1; 2361let Inst{31-21} = 0b11010010000; 2362} 2363def A4_boundscheck_lo : HInst< 2364(outs PredRegs:$Pd4), 2365(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 2366"$Pd4 = boundscheck($Rss32,$Rtt32):raw:lo", 2367tc_85d5d03f, TypeALU64>, Enc_fcf7a7 { 2368let Inst{7-2} = 0b100000; 2369let Inst{13-13} = 0b1; 2370let Inst{31-21} = 0b11010010000; 2371} 2372def A4_cmpbeq : HInst< 2373(outs PredRegs:$Pd4), 2374(ins IntRegs:$Rs32, IntRegs:$Rt32), 2375"$Pd4 = cmpb.eq($Rs32,$Rt32)", 2376tc_85d5d03f, TypeS_3op>, Enc_c2b48e, ImmRegRel { 2377let Inst{7-2} = 0b110000; 2378let Inst{13-13} = 0b0; 2379let Inst{31-21} = 0b11000111110; 2380let CextOpcode = "A4_cmpbeq"; 2381let InputType = "reg"; 2382let isCommutable = 1; 2383let isCompare = 1; 2384} 2385def A4_cmpbeqi : HInst< 2386(outs PredRegs:$Pd4), 2387(ins IntRegs:$Rs32, u8_0Imm:$Ii), 2388"$Pd4 = cmpb.eq($Rs32,#$Ii)", 2389tc_643b4717, TypeALU64>, Enc_08d755, ImmRegRel { 2390let Inst{4-2} = 0b000; 2391let Inst{13-13} = 0b0; 2392let Inst{31-21} = 0b11011101000; 2393let CextOpcode = "A4_cmpbeq"; 2394let InputType = "imm"; 2395let isCommutable = 1; 2396let isCompare = 1; 2397} 2398def A4_cmpbgt : HInst< 2399(outs PredRegs:$Pd4), 2400(ins IntRegs:$Rs32, IntRegs:$Rt32), 2401"$Pd4 = cmpb.gt($Rs32,$Rt32)", 2402tc_85d5d03f, TypeS_3op>, Enc_c2b48e, ImmRegRel { 2403let Inst{7-2} = 0b010000; 2404let Inst{13-13} = 0b0; 2405let Inst{31-21} = 0b11000111110; 2406let CextOpcode = "A4_cmpbgt"; 2407let InputType = "reg"; 2408let isCompare = 1; 2409} 2410def A4_cmpbgti : HInst< 2411(outs PredRegs:$Pd4), 2412(ins IntRegs:$Rs32, s8_0Imm:$Ii), 2413"$Pd4 = cmpb.gt($Rs32,#$Ii)", 2414tc_643b4717, TypeALU64>, Enc_08d755, ImmRegRel { 2415let Inst{4-2} = 0b000; 2416let Inst{13-13} = 0b0; 2417let Inst{31-21} = 0b11011101001; 2418let CextOpcode = "A4_cmpbgt"; 2419let InputType = "imm"; 2420let isCompare = 1; 2421} 2422def A4_cmpbgtu : HInst< 2423(outs PredRegs:$Pd4), 2424(ins IntRegs:$Rs32, IntRegs:$Rt32), 2425"$Pd4 = cmpb.gtu($Rs32,$Rt32)", 2426tc_85d5d03f, TypeS_3op>, Enc_c2b48e, ImmRegRel { 2427let Inst{7-2} = 0b111000; 2428let Inst{13-13} = 0b0; 2429let Inst{31-21} = 0b11000111110; 2430let CextOpcode = "A4_cmpbgtu"; 2431let InputType = "reg"; 2432let isCompare = 1; 2433} 2434def A4_cmpbgtui : HInst< 2435(outs PredRegs:$Pd4), 2436(ins IntRegs:$Rs32, u32_0Imm:$Ii), 2437"$Pd4 = cmpb.gtu($Rs32,#$Ii)", 2438tc_643b4717, TypeALU64>, Enc_02553a, ImmRegRel { 2439let Inst{4-2} = 0b000; 2440let Inst{13-12} = 0b00; 2441let Inst{31-21} = 0b11011101010; 2442let CextOpcode = "A4_cmpbgtu"; 2443let InputType = "imm"; 2444let isCompare = 1; 2445let isExtendable = 1; 2446let opExtendable = 2; 2447let isExtentSigned = 0; 2448let opExtentBits = 7; 2449let opExtentAlign = 0; 2450} 2451def A4_cmpheq : HInst< 2452(outs PredRegs:$Pd4), 2453(ins IntRegs:$Rs32, IntRegs:$Rt32), 2454"$Pd4 = cmph.eq($Rs32,$Rt32)", 2455tc_85d5d03f, TypeS_3op>, Enc_c2b48e, ImmRegRel { 2456let Inst{7-2} = 0b011000; 2457let Inst{13-13} = 0b0; 2458let Inst{31-21} = 0b11000111110; 2459let CextOpcode = "A4_cmpheq"; 2460let InputType = "reg"; 2461let isCommutable = 1; 2462let isCompare = 1; 2463} 2464def A4_cmpheqi : HInst< 2465(outs PredRegs:$Pd4), 2466(ins IntRegs:$Rs32, s32_0Imm:$Ii), 2467"$Pd4 = cmph.eq($Rs32,#$Ii)", 2468tc_643b4717, TypeALU64>, Enc_08d755, ImmRegRel { 2469let Inst{4-2} = 0b010; 2470let Inst{13-13} = 0b0; 2471let Inst{31-21} = 0b11011101000; 2472let CextOpcode = "A4_cmpheq"; 2473let InputType = "imm"; 2474let isCommutable = 1; 2475let isCompare = 1; 2476let isExtendable = 1; 2477let opExtendable = 2; 2478let isExtentSigned = 1; 2479let opExtentBits = 8; 2480let opExtentAlign = 0; 2481} 2482def A4_cmphgt : HInst< 2483(outs PredRegs:$Pd4), 2484(ins IntRegs:$Rs32, IntRegs:$Rt32), 2485"$Pd4 = cmph.gt($Rs32,$Rt32)", 2486tc_85d5d03f, TypeS_3op>, Enc_c2b48e, ImmRegRel { 2487let Inst{7-2} = 0b100000; 2488let Inst{13-13} = 0b0; 2489let Inst{31-21} = 0b11000111110; 2490let CextOpcode = "A4_cmphgt"; 2491let InputType = "reg"; 2492let isCompare = 1; 2493} 2494def A4_cmphgti : HInst< 2495(outs PredRegs:$Pd4), 2496(ins IntRegs:$Rs32, s32_0Imm:$Ii), 2497"$Pd4 = cmph.gt($Rs32,#$Ii)", 2498tc_643b4717, TypeALU64>, Enc_08d755, ImmRegRel { 2499let Inst{4-2} = 0b010; 2500let Inst{13-13} = 0b0; 2501let Inst{31-21} = 0b11011101001; 2502let CextOpcode = "A4_cmphgt"; 2503let InputType = "imm"; 2504let isCompare = 1; 2505let isExtendable = 1; 2506let opExtendable = 2; 2507let isExtentSigned = 1; 2508let opExtentBits = 8; 2509let opExtentAlign = 0; 2510} 2511def A4_cmphgtu : HInst< 2512(outs PredRegs:$Pd4), 2513(ins IntRegs:$Rs32, IntRegs:$Rt32), 2514"$Pd4 = cmph.gtu($Rs32,$Rt32)", 2515tc_85d5d03f, TypeS_3op>, Enc_c2b48e, ImmRegRel { 2516let Inst{7-2} = 0b101000; 2517let Inst{13-13} = 0b0; 2518let Inst{31-21} = 0b11000111110; 2519let CextOpcode = "A4_cmphgtu"; 2520let InputType = "reg"; 2521let isCompare = 1; 2522} 2523def A4_cmphgtui : HInst< 2524(outs PredRegs:$Pd4), 2525(ins IntRegs:$Rs32, u32_0Imm:$Ii), 2526"$Pd4 = cmph.gtu($Rs32,#$Ii)", 2527tc_643b4717, TypeALU64>, Enc_02553a, ImmRegRel { 2528let Inst{4-2} = 0b010; 2529let Inst{13-12} = 0b00; 2530let Inst{31-21} = 0b11011101010; 2531let CextOpcode = "A4_cmphgtu"; 2532let InputType = "imm"; 2533let isCompare = 1; 2534let isExtendable = 1; 2535let opExtendable = 2; 2536let isExtentSigned = 0; 2537let opExtentBits = 7; 2538let opExtentAlign = 0; 2539} 2540def A4_combineii : HInst< 2541(outs DoubleRegs:$Rdd32), 2542(ins s8_0Imm:$Ii, u32_0Imm:$II), 2543"$Rdd32 = combine(#$Ii,#$II)", 2544tc_5a2711e5, TypeALU32_2op>, Enc_f0cca7 { 2545let Inst{31-21} = 0b01111100100; 2546let isExtendable = 1; 2547let opExtendable = 2; 2548let isExtentSigned = 0; 2549let opExtentBits = 6; 2550let opExtentAlign = 0; 2551} 2552def A4_combineir : HInst< 2553(outs DoubleRegs:$Rdd32), 2554(ins s32_0Imm:$Ii, IntRegs:$Rs32), 2555"$Rdd32 = combine(#$Ii,$Rs32)", 2556tc_5a2711e5, TypeALU32_2op>, Enc_9cdba7 { 2557let Inst{13-13} = 0b1; 2558let Inst{31-21} = 0b01110011001; 2559let isExtendable = 1; 2560let opExtendable = 1; 2561let isExtentSigned = 1; 2562let opExtentBits = 8; 2563let opExtentAlign = 0; 2564} 2565def A4_combineri : HInst< 2566(outs DoubleRegs:$Rdd32), 2567(ins IntRegs:$Rs32, s32_0Imm:$Ii), 2568"$Rdd32 = combine($Rs32,#$Ii)", 2569tc_5a2711e5, TypeALU32_2op>, Enc_9cdba7 { 2570let Inst{13-13} = 0b1; 2571let Inst{31-21} = 0b01110011000; 2572let isExtendable = 1; 2573let opExtendable = 2; 2574let isExtentSigned = 1; 2575let opExtentBits = 8; 2576let opExtentAlign = 0; 2577} 2578def A4_cround_ri : HInst< 2579(outs IntRegs:$Rd32), 2580(ins IntRegs:$Rs32, u5_0Imm:$Ii), 2581"$Rd32 = cround($Rs32,#$Ii)", 2582tc_002cb246, TypeS_2op>, Enc_a05677 { 2583let Inst{7-5} = 0b000; 2584let Inst{13-13} = 0b0; 2585let Inst{31-21} = 0b10001100111; 2586let hasNewValue = 1; 2587let opNewValue = 0; 2588let prefersSlot3 = 1; 2589} 2590def A4_cround_rr : HInst< 2591(outs IntRegs:$Rd32), 2592(ins IntRegs:$Rs32, IntRegs:$Rt32), 2593"$Rd32 = cround($Rs32,$Rt32)", 2594tc_002cb246, TypeS_3op>, Enc_5ab2be { 2595let Inst{7-5} = 0b000; 2596let Inst{13-13} = 0b0; 2597let Inst{31-21} = 0b11000110110; 2598let hasNewValue = 1; 2599let opNewValue = 0; 2600let prefersSlot3 = 1; 2601} 2602def A4_ext : HInst< 2603(outs), 2604(ins u26_6Imm:$Ii), 2605"immext(#$Ii)", 2606tc_862b3e70, TypeEXTENDER>, Enc_2b518f { 2607let Inst{31-28} = 0b0000; 2608} 2609def A4_modwrapu : HInst< 2610(outs IntRegs:$Rd32), 2611(ins IntRegs:$Rs32, IntRegs:$Rt32), 2612"$Rd32 = modwrap($Rs32,$Rt32)", 2613tc_779080bf, TypeALU64>, Enc_5ab2be { 2614let Inst{7-5} = 0b111; 2615let Inst{13-13} = 0b0; 2616let Inst{31-21} = 0b11010011111; 2617let hasNewValue = 1; 2618let opNewValue = 0; 2619let prefersSlot3 = 1; 2620} 2621def A4_orn : HInst< 2622(outs IntRegs:$Rd32), 2623(ins IntRegs:$Rt32, IntRegs:$Rs32), 2624"$Rd32 = or($Rt32,~$Rs32)", 2625tc_5a2711e5, TypeALU32_3op>, Enc_bd6011 { 2626let Inst{7-5} = 0b000; 2627let Inst{13-13} = 0b0; 2628let Inst{31-21} = 0b11110001101; 2629let hasNewValue = 1; 2630let opNewValue = 0; 2631let InputType = "reg"; 2632} 2633def A4_ornp : HInst< 2634(outs DoubleRegs:$Rdd32), 2635(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), 2636"$Rdd32 = or($Rtt32,~$Rss32)", 2637tc_946df596, TypeALU64>, Enc_ea23e4 { 2638let Inst{7-5} = 0b011; 2639let Inst{13-13} = 0b0; 2640let Inst{31-21} = 0b11010011111; 2641} 2642def A4_paslhf : HInst< 2643(outs IntRegs:$Rd32), 2644(ins PredRegs:$Pu4, IntRegs:$Rs32), 2645"if (!$Pu4) $Rd32 = aslh($Rs32)", 2646tc_5a2711e5, TypeALU32_2op>, Enc_fb6577, PredNewRel { 2647let Inst{7-5} = 0b000; 2648let Inst{13-10} = 0b1010; 2649let Inst{31-21} = 0b01110000000; 2650let isPredicated = 1; 2651let isPredicatedFalse = 1; 2652let hasNewValue = 1; 2653let opNewValue = 0; 2654let BaseOpcode = "A2_aslh"; 2655} 2656def A4_paslhfnew : HInst< 2657(outs IntRegs:$Rd32), 2658(ins PredRegs:$Pu4, IntRegs:$Rs32), 2659"if (!$Pu4.new) $Rd32 = aslh($Rs32)", 2660tc_1ae57e39, TypeALU32_2op>, Enc_fb6577, PredNewRel { 2661let Inst{7-5} = 0b000; 2662let Inst{13-10} = 0b1011; 2663let Inst{31-21} = 0b01110000000; 2664let isPredicated = 1; 2665let isPredicatedFalse = 1; 2666let hasNewValue = 1; 2667let opNewValue = 0; 2668let isPredicatedNew = 1; 2669let BaseOpcode = "A2_aslh"; 2670} 2671def A4_paslht : HInst< 2672(outs IntRegs:$Rd32), 2673(ins PredRegs:$Pu4, IntRegs:$Rs32), 2674"if ($Pu4) $Rd32 = aslh($Rs32)", 2675tc_5a2711e5, TypeALU32_2op>, Enc_fb6577, PredNewRel { 2676let Inst{7-5} = 0b000; 2677let Inst{13-10} = 0b1000; 2678let Inst{31-21} = 0b01110000000; 2679let isPredicated = 1; 2680let hasNewValue = 1; 2681let opNewValue = 0; 2682let BaseOpcode = "A2_aslh"; 2683} 2684def A4_paslhtnew : HInst< 2685(outs IntRegs:$Rd32), 2686(ins PredRegs:$Pu4, IntRegs:$Rs32), 2687"if ($Pu4.new) $Rd32 = aslh($Rs32)", 2688tc_1ae57e39, TypeALU32_2op>, Enc_fb6577, PredNewRel { 2689let Inst{7-5} = 0b000; 2690let Inst{13-10} = 0b1001; 2691let Inst{31-21} = 0b01110000000; 2692let isPredicated = 1; 2693let hasNewValue = 1; 2694let opNewValue = 0; 2695let isPredicatedNew = 1; 2696let BaseOpcode = "A2_aslh"; 2697} 2698def A4_pasrhf : HInst< 2699(outs IntRegs:$Rd32), 2700(ins PredRegs:$Pu4, IntRegs:$Rs32), 2701"if (!$Pu4) $Rd32 = asrh($Rs32)", 2702tc_5a2711e5, TypeALU32_2op>, Enc_fb6577, PredNewRel { 2703let Inst{7-5} = 0b000; 2704let Inst{13-10} = 0b1010; 2705let Inst{31-21} = 0b01110000001; 2706let isPredicated = 1; 2707let isPredicatedFalse = 1; 2708let hasNewValue = 1; 2709let opNewValue = 0; 2710let BaseOpcode = "A2_asrh"; 2711} 2712def A4_pasrhfnew : HInst< 2713(outs IntRegs:$Rd32), 2714(ins PredRegs:$Pu4, IntRegs:$Rs32), 2715"if (!$Pu4.new) $Rd32 = asrh($Rs32)", 2716tc_1ae57e39, TypeALU32_2op>, Enc_fb6577, PredNewRel { 2717let Inst{7-5} = 0b000; 2718let Inst{13-10} = 0b1011; 2719let Inst{31-21} = 0b01110000001; 2720let isPredicated = 1; 2721let isPredicatedFalse = 1; 2722let hasNewValue = 1; 2723let opNewValue = 0; 2724let isPredicatedNew = 1; 2725let BaseOpcode = "A2_asrh"; 2726} 2727def A4_pasrht : HInst< 2728(outs IntRegs:$Rd32), 2729(ins PredRegs:$Pu4, IntRegs:$Rs32), 2730"if ($Pu4) $Rd32 = asrh($Rs32)", 2731tc_5a2711e5, TypeALU32_2op>, Enc_fb6577, PredNewRel { 2732let Inst{7-5} = 0b000; 2733let Inst{13-10} = 0b1000; 2734let Inst{31-21} = 0b01110000001; 2735let isPredicated = 1; 2736let hasNewValue = 1; 2737let opNewValue = 0; 2738let BaseOpcode = "A2_asrh"; 2739} 2740def A4_pasrhtnew : HInst< 2741(outs IntRegs:$Rd32), 2742(ins PredRegs:$Pu4, IntRegs:$Rs32), 2743"if ($Pu4.new) $Rd32 = asrh($Rs32)", 2744tc_1ae57e39, TypeALU32_2op>, Enc_fb6577, PredNewRel { 2745let Inst{7-5} = 0b000; 2746let Inst{13-10} = 0b1001; 2747let Inst{31-21} = 0b01110000001; 2748let isPredicated = 1; 2749let hasNewValue = 1; 2750let opNewValue = 0; 2751let isPredicatedNew = 1; 2752let BaseOpcode = "A2_asrh"; 2753} 2754def A4_psxtbf : HInst< 2755(outs IntRegs:$Rd32), 2756(ins PredRegs:$Pu4, IntRegs:$Rs32), 2757"if (!$Pu4) $Rd32 = sxtb($Rs32)", 2758tc_5a2711e5, TypeALU32_2op>, Enc_fb6577, PredNewRel { 2759let Inst{7-5} = 0b000; 2760let Inst{13-10} = 0b1010; 2761let Inst{31-21} = 0b01110000101; 2762let isPredicated = 1; 2763let isPredicatedFalse = 1; 2764let hasNewValue = 1; 2765let opNewValue = 0; 2766let BaseOpcode = "A2_sxtb"; 2767} 2768def A4_psxtbfnew : HInst< 2769(outs IntRegs:$Rd32), 2770(ins PredRegs:$Pu4, IntRegs:$Rs32), 2771"if (!$Pu4.new) $Rd32 = sxtb($Rs32)", 2772tc_1ae57e39, TypeALU32_2op>, Enc_fb6577, PredNewRel { 2773let Inst{7-5} = 0b000; 2774let Inst{13-10} = 0b1011; 2775let Inst{31-21} = 0b01110000101; 2776let isPredicated = 1; 2777let isPredicatedFalse = 1; 2778let hasNewValue = 1; 2779let opNewValue = 0; 2780let isPredicatedNew = 1; 2781let BaseOpcode = "A2_sxtb"; 2782} 2783def A4_psxtbt : HInst< 2784(outs IntRegs:$Rd32), 2785(ins PredRegs:$Pu4, IntRegs:$Rs32), 2786"if ($Pu4) $Rd32 = sxtb($Rs32)", 2787tc_5a2711e5, TypeALU32_2op>, Enc_fb6577, PredNewRel { 2788let Inst{7-5} = 0b000; 2789let Inst{13-10} = 0b1000; 2790let Inst{31-21} = 0b01110000101; 2791let isPredicated = 1; 2792let hasNewValue = 1; 2793let opNewValue = 0; 2794let BaseOpcode = "A2_sxtb"; 2795} 2796def A4_psxtbtnew : HInst< 2797(outs IntRegs:$Rd32), 2798(ins PredRegs:$Pu4, IntRegs:$Rs32), 2799"if ($Pu4.new) $Rd32 = sxtb($Rs32)", 2800tc_1ae57e39, TypeALU32_2op>, Enc_fb6577, PredNewRel { 2801let Inst{7-5} = 0b000; 2802let Inst{13-10} = 0b1001; 2803let Inst{31-21} = 0b01110000101; 2804let isPredicated = 1; 2805let hasNewValue = 1; 2806let opNewValue = 0; 2807let isPredicatedNew = 1; 2808let BaseOpcode = "A2_sxtb"; 2809} 2810def A4_psxthf : HInst< 2811(outs IntRegs:$Rd32), 2812(ins PredRegs:$Pu4, IntRegs:$Rs32), 2813"if (!$Pu4) $Rd32 = sxth($Rs32)", 2814tc_5a2711e5, TypeALU32_2op>, Enc_fb6577, PredNewRel { 2815let Inst{7-5} = 0b000; 2816let Inst{13-10} = 0b1010; 2817let Inst{31-21} = 0b01110000111; 2818let isPredicated = 1; 2819let isPredicatedFalse = 1; 2820let hasNewValue = 1; 2821let opNewValue = 0; 2822let BaseOpcode = "A2_sxth"; 2823} 2824def A4_psxthfnew : HInst< 2825(outs IntRegs:$Rd32), 2826(ins PredRegs:$Pu4, IntRegs:$Rs32), 2827"if (!$Pu4.new) $Rd32 = sxth($Rs32)", 2828tc_1ae57e39, TypeALU32_2op>, Enc_fb6577, PredNewRel { 2829let Inst{7-5} = 0b000; 2830let Inst{13-10} = 0b1011; 2831let Inst{31-21} = 0b01110000111; 2832let isPredicated = 1; 2833let isPredicatedFalse = 1; 2834let hasNewValue = 1; 2835let opNewValue = 0; 2836let isPredicatedNew = 1; 2837let BaseOpcode = "A2_sxth"; 2838} 2839def A4_psxtht : HInst< 2840(outs IntRegs:$Rd32), 2841(ins PredRegs:$Pu4, IntRegs:$Rs32), 2842"if ($Pu4) $Rd32 = sxth($Rs32)", 2843tc_5a2711e5, TypeALU32_2op>, Enc_fb6577, PredNewRel { 2844let Inst{7-5} = 0b000; 2845let Inst{13-10} = 0b1000; 2846let Inst{31-21} = 0b01110000111; 2847let isPredicated = 1; 2848let hasNewValue = 1; 2849let opNewValue = 0; 2850let BaseOpcode = "A2_sxth"; 2851} 2852def A4_psxthtnew : HInst< 2853(outs IntRegs:$Rd32), 2854(ins PredRegs:$Pu4, IntRegs:$Rs32), 2855"if ($Pu4.new) $Rd32 = sxth($Rs32)", 2856tc_1ae57e39, TypeALU32_2op>, Enc_fb6577, PredNewRel { 2857let Inst{7-5} = 0b000; 2858let Inst{13-10} = 0b1001; 2859let Inst{31-21} = 0b01110000111; 2860let isPredicated = 1; 2861let hasNewValue = 1; 2862let opNewValue = 0; 2863let isPredicatedNew = 1; 2864let BaseOpcode = "A2_sxth"; 2865} 2866def A4_pzxtbf : HInst< 2867(outs IntRegs:$Rd32), 2868(ins PredRegs:$Pu4, IntRegs:$Rs32), 2869"if (!$Pu4) $Rd32 = zxtb($Rs32)", 2870tc_5a2711e5, TypeALU32_2op>, Enc_fb6577, PredNewRel { 2871let Inst{7-5} = 0b000; 2872let Inst{13-10} = 0b1010; 2873let Inst{31-21} = 0b01110000100; 2874let isPredicated = 1; 2875let isPredicatedFalse = 1; 2876let hasNewValue = 1; 2877let opNewValue = 0; 2878let BaseOpcode = "A2_zxtb"; 2879} 2880def A4_pzxtbfnew : HInst< 2881(outs IntRegs:$Rd32), 2882(ins PredRegs:$Pu4, IntRegs:$Rs32), 2883"if (!$Pu4.new) $Rd32 = zxtb($Rs32)", 2884tc_1ae57e39, TypeALU32_2op>, Enc_fb6577, PredNewRel { 2885let Inst{7-5} = 0b000; 2886let Inst{13-10} = 0b1011; 2887let Inst{31-21} = 0b01110000100; 2888let isPredicated = 1; 2889let isPredicatedFalse = 1; 2890let hasNewValue = 1; 2891let opNewValue = 0; 2892let isPredicatedNew = 1; 2893let BaseOpcode = "A2_zxtb"; 2894} 2895def A4_pzxtbt : HInst< 2896(outs IntRegs:$Rd32), 2897(ins PredRegs:$Pu4, IntRegs:$Rs32), 2898"if ($Pu4) $Rd32 = zxtb($Rs32)", 2899tc_5a2711e5, TypeALU32_2op>, Enc_fb6577, PredNewRel { 2900let Inst{7-5} = 0b000; 2901let Inst{13-10} = 0b1000; 2902let Inst{31-21} = 0b01110000100; 2903let isPredicated = 1; 2904let hasNewValue = 1; 2905let opNewValue = 0; 2906let BaseOpcode = "A2_zxtb"; 2907} 2908def A4_pzxtbtnew : HInst< 2909(outs IntRegs:$Rd32), 2910(ins PredRegs:$Pu4, IntRegs:$Rs32), 2911"if ($Pu4.new) $Rd32 = zxtb($Rs32)", 2912tc_1ae57e39, TypeALU32_2op>, Enc_fb6577, PredNewRel { 2913let Inst{7-5} = 0b000; 2914let Inst{13-10} = 0b1001; 2915let Inst{31-21} = 0b01110000100; 2916let isPredicated = 1; 2917let hasNewValue = 1; 2918let opNewValue = 0; 2919let isPredicatedNew = 1; 2920let BaseOpcode = "A2_zxtb"; 2921} 2922def A4_pzxthf : HInst< 2923(outs IntRegs:$Rd32), 2924(ins PredRegs:$Pu4, IntRegs:$Rs32), 2925"if (!$Pu4) $Rd32 = zxth($Rs32)", 2926tc_5a2711e5, TypeALU32_2op>, Enc_fb6577, PredNewRel { 2927let Inst{7-5} = 0b000; 2928let Inst{13-10} = 0b1010; 2929let Inst{31-21} = 0b01110000110; 2930let isPredicated = 1; 2931let isPredicatedFalse = 1; 2932let hasNewValue = 1; 2933let opNewValue = 0; 2934let BaseOpcode = "A2_zxth"; 2935} 2936def A4_pzxthfnew : HInst< 2937(outs IntRegs:$Rd32), 2938(ins PredRegs:$Pu4, IntRegs:$Rs32), 2939"if (!$Pu4.new) $Rd32 = zxth($Rs32)", 2940tc_1ae57e39, TypeALU32_2op>, Enc_fb6577, PredNewRel { 2941let Inst{7-5} = 0b000; 2942let Inst{13-10} = 0b1011; 2943let Inst{31-21} = 0b01110000110; 2944let isPredicated = 1; 2945let isPredicatedFalse = 1; 2946let hasNewValue = 1; 2947let opNewValue = 0; 2948let isPredicatedNew = 1; 2949let BaseOpcode = "A2_zxth"; 2950} 2951def A4_pzxtht : HInst< 2952(outs IntRegs:$Rd32), 2953(ins PredRegs:$Pu4, IntRegs:$Rs32), 2954"if ($Pu4) $Rd32 = zxth($Rs32)", 2955tc_5a2711e5, TypeALU32_2op>, Enc_fb6577, PredNewRel { 2956let Inst{7-5} = 0b000; 2957let Inst{13-10} = 0b1000; 2958let Inst{31-21} = 0b01110000110; 2959let isPredicated = 1; 2960let hasNewValue = 1; 2961let opNewValue = 0; 2962let BaseOpcode = "A2_zxth"; 2963} 2964def A4_pzxthtnew : HInst< 2965(outs IntRegs:$Rd32), 2966(ins PredRegs:$Pu4, IntRegs:$Rs32), 2967"if ($Pu4.new) $Rd32 = zxth($Rs32)", 2968tc_1ae57e39, TypeALU32_2op>, Enc_fb6577, PredNewRel { 2969let Inst{7-5} = 0b000; 2970let Inst{13-10} = 0b1001; 2971let Inst{31-21} = 0b01110000110; 2972let isPredicated = 1; 2973let hasNewValue = 1; 2974let opNewValue = 0; 2975let isPredicatedNew = 1; 2976let BaseOpcode = "A2_zxth"; 2977} 2978def A4_rcmpeq : HInst< 2979(outs IntRegs:$Rd32), 2980(ins IntRegs:$Rs32, IntRegs:$Rt32), 2981"$Rd32 = cmp.eq($Rs32,$Rt32)", 2982tc_5a2711e5, TypeALU32_3op>, Enc_5ab2be, ImmRegRel { 2983let Inst{7-5} = 0b000; 2984let Inst{13-13} = 0b0; 2985let Inst{31-21} = 0b11110011010; 2986let hasNewValue = 1; 2987let opNewValue = 0; 2988let CextOpcode = "A4_rcmpeq"; 2989let InputType = "reg"; 2990let isCommutable = 1; 2991} 2992def A4_rcmpeqi : HInst< 2993(outs IntRegs:$Rd32), 2994(ins IntRegs:$Rs32, s32_0Imm:$Ii), 2995"$Rd32 = cmp.eq($Rs32,#$Ii)", 2996tc_5a2711e5, TypeALU32_2op>, Enc_b8c967, ImmRegRel { 2997let Inst{13-13} = 0b1; 2998let Inst{31-21} = 0b01110011010; 2999let hasNewValue = 1; 3000let opNewValue = 0; 3001let CextOpcode = "A4_rcmpeqi"; 3002let InputType = "imm"; 3003let isExtendable = 1; 3004let opExtendable = 2; 3005let isExtentSigned = 1; 3006let opExtentBits = 8; 3007let opExtentAlign = 0; 3008} 3009def A4_rcmpneq : HInst< 3010(outs IntRegs:$Rd32), 3011(ins IntRegs:$Rs32, IntRegs:$Rt32), 3012"$Rd32 = !cmp.eq($Rs32,$Rt32)", 3013tc_5a2711e5, TypeALU32_3op>, Enc_5ab2be, ImmRegRel { 3014let Inst{7-5} = 0b000; 3015let Inst{13-13} = 0b0; 3016let Inst{31-21} = 0b11110011011; 3017let hasNewValue = 1; 3018let opNewValue = 0; 3019let CextOpcode = "A4_rcmpneq"; 3020let InputType = "reg"; 3021let isCommutable = 1; 3022} 3023def A4_rcmpneqi : HInst< 3024(outs IntRegs:$Rd32), 3025(ins IntRegs:$Rs32, s32_0Imm:$Ii), 3026"$Rd32 = !cmp.eq($Rs32,#$Ii)", 3027tc_5a2711e5, TypeALU32_2op>, Enc_b8c967, ImmRegRel { 3028let Inst{13-13} = 0b1; 3029let Inst{31-21} = 0b01110011011; 3030let hasNewValue = 1; 3031let opNewValue = 0; 3032let CextOpcode = "A4_rcmpeqi"; 3033let InputType = "imm"; 3034let isExtendable = 1; 3035let opExtendable = 2; 3036let isExtentSigned = 1; 3037let opExtentBits = 8; 3038let opExtentAlign = 0; 3039} 3040def A4_round_ri : HInst< 3041(outs IntRegs:$Rd32), 3042(ins IntRegs:$Rs32, u5_0Imm:$Ii), 3043"$Rd32 = round($Rs32,#$Ii)", 3044tc_002cb246, TypeS_2op>, Enc_a05677 { 3045let Inst{7-5} = 0b100; 3046let Inst{13-13} = 0b0; 3047let Inst{31-21} = 0b10001100111; 3048let hasNewValue = 1; 3049let opNewValue = 0; 3050let prefersSlot3 = 1; 3051} 3052def A4_round_ri_sat : HInst< 3053(outs IntRegs:$Rd32), 3054(ins IntRegs:$Rs32, u5_0Imm:$Ii), 3055"$Rd32 = round($Rs32,#$Ii):sat", 3056tc_002cb246, TypeS_2op>, Enc_a05677 { 3057let Inst{7-5} = 0b110; 3058let Inst{13-13} = 0b0; 3059let Inst{31-21} = 0b10001100111; 3060let hasNewValue = 1; 3061let opNewValue = 0; 3062let prefersSlot3 = 1; 3063let Defs = [USR_OVF]; 3064} 3065def A4_round_rr : HInst< 3066(outs IntRegs:$Rd32), 3067(ins IntRegs:$Rs32, IntRegs:$Rt32), 3068"$Rd32 = round($Rs32,$Rt32)", 3069tc_002cb246, TypeS_3op>, Enc_5ab2be { 3070let Inst{7-5} = 0b100; 3071let Inst{13-13} = 0b0; 3072let Inst{31-21} = 0b11000110110; 3073let hasNewValue = 1; 3074let opNewValue = 0; 3075let prefersSlot3 = 1; 3076} 3077def A4_round_rr_sat : HInst< 3078(outs IntRegs:$Rd32), 3079(ins IntRegs:$Rs32, IntRegs:$Rt32), 3080"$Rd32 = round($Rs32,$Rt32):sat", 3081tc_002cb246, TypeS_3op>, Enc_5ab2be { 3082let Inst{7-5} = 0b110; 3083let Inst{13-13} = 0b0; 3084let Inst{31-21} = 0b11000110110; 3085let hasNewValue = 1; 3086let opNewValue = 0; 3087let prefersSlot3 = 1; 3088let Defs = [USR_OVF]; 3089} 3090def A4_subp_c : HInst< 3091(outs DoubleRegs:$Rdd32, PredRegs:$Px4), 3092(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32, PredRegs:$Px4in), 3093"$Rdd32 = sub($Rss32,$Rtt32,$Px4):carry", 3094tc_9c3ecd83, TypeS_3op>, Enc_2b3f60 { 3095let Inst{7-7} = 0b0; 3096let Inst{13-13} = 0b0; 3097let Inst{31-21} = 0b11000010111; 3098let isPredicateLate = 1; 3099let Constraints = "$Px4 = $Px4in"; 3100} 3101def A4_tfrcpp : HInst< 3102(outs DoubleRegs:$Rdd32), 3103(ins CtrRegs64:$Css32), 3104"$Rdd32 = $Css32", 3105tc_b9272d6c, TypeCR>, Enc_667b39 { 3106let Inst{13-5} = 0b000000000; 3107let Inst{31-21} = 0b01101000000; 3108} 3109def A4_tfrpcp : HInst< 3110(outs CtrRegs64:$Cdd32), 3111(ins DoubleRegs:$Rss32), 3112"$Cdd32 = $Rss32", 3113tc_434c8e1e, TypeCR>, Enc_0ed752 { 3114let Inst{13-5} = 0b000000000; 3115let Inst{31-21} = 0b01100011001; 3116} 3117def A4_tlbmatch : HInst< 3118(outs PredRegs:$Pd4), 3119(ins DoubleRegs:$Rss32, IntRegs:$Rt32), 3120"$Pd4 = tlbmatch($Rss32,$Rt32)", 3121tc_4837eefb, TypeALU64>, Enc_03833b { 3122let Inst{7-2} = 0b011000; 3123let Inst{13-13} = 0b1; 3124let Inst{31-21} = 0b11010010000; 3125let isPredicateLate = 1; 3126} 3127def A4_vcmpbeq_any : HInst< 3128(outs PredRegs:$Pd4), 3129(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 3130"$Pd4 = any8(vcmpb.eq($Rss32,$Rtt32))", 3131tc_85d5d03f, TypeALU64>, Enc_fcf7a7 { 3132let Inst{7-2} = 0b000000; 3133let Inst{13-13} = 0b1; 3134let Inst{31-21} = 0b11010010000; 3135} 3136def A4_vcmpbeqi : HInst< 3137(outs PredRegs:$Pd4), 3138(ins DoubleRegs:$Rss32, u8_0Imm:$Ii), 3139"$Pd4 = vcmpb.eq($Rss32,#$Ii)", 3140tc_643b4717, TypeALU64>, Enc_0d8adb { 3141let Inst{4-2} = 0b000; 3142let Inst{13-13} = 0b0; 3143let Inst{31-21} = 0b11011100000; 3144} 3145def A4_vcmpbgt : HInst< 3146(outs PredRegs:$Pd4), 3147(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 3148"$Pd4 = vcmpb.gt($Rss32,$Rtt32)", 3149tc_85d5d03f, TypeALU64>, Enc_fcf7a7 { 3150let Inst{7-2} = 0b010000; 3151let Inst{13-13} = 0b1; 3152let Inst{31-21} = 0b11010010000; 3153} 3154def A4_vcmpbgti : HInst< 3155(outs PredRegs:$Pd4), 3156(ins DoubleRegs:$Rss32, s8_0Imm:$Ii), 3157"$Pd4 = vcmpb.gt($Rss32,#$Ii)", 3158tc_643b4717, TypeALU64>, Enc_0d8adb { 3159let Inst{4-2} = 0b000; 3160let Inst{13-13} = 0b0; 3161let Inst{31-21} = 0b11011100001; 3162} 3163def A4_vcmpbgtui : HInst< 3164(outs PredRegs:$Pd4), 3165(ins DoubleRegs:$Rss32, u7_0Imm:$Ii), 3166"$Pd4 = vcmpb.gtu($Rss32,#$Ii)", 3167tc_643b4717, TypeALU64>, Enc_3680c2 { 3168let Inst{4-2} = 0b000; 3169let Inst{13-12} = 0b00; 3170let Inst{31-21} = 0b11011100010; 3171} 3172def A4_vcmpheqi : HInst< 3173(outs PredRegs:$Pd4), 3174(ins DoubleRegs:$Rss32, s8_0Imm:$Ii), 3175"$Pd4 = vcmph.eq($Rss32,#$Ii)", 3176tc_643b4717, TypeALU64>, Enc_0d8adb { 3177let Inst{4-2} = 0b010; 3178let Inst{13-13} = 0b0; 3179let Inst{31-21} = 0b11011100000; 3180} 3181def A4_vcmphgti : HInst< 3182(outs PredRegs:$Pd4), 3183(ins DoubleRegs:$Rss32, s8_0Imm:$Ii), 3184"$Pd4 = vcmph.gt($Rss32,#$Ii)", 3185tc_643b4717, TypeALU64>, Enc_0d8adb { 3186let Inst{4-2} = 0b010; 3187let Inst{13-13} = 0b0; 3188let Inst{31-21} = 0b11011100001; 3189} 3190def A4_vcmphgtui : HInst< 3191(outs PredRegs:$Pd4), 3192(ins DoubleRegs:$Rss32, u7_0Imm:$Ii), 3193"$Pd4 = vcmph.gtu($Rss32,#$Ii)", 3194tc_643b4717, TypeALU64>, Enc_3680c2 { 3195let Inst{4-2} = 0b010; 3196let Inst{13-12} = 0b00; 3197let Inst{31-21} = 0b11011100010; 3198} 3199def A4_vcmpweqi : HInst< 3200(outs PredRegs:$Pd4), 3201(ins DoubleRegs:$Rss32, s8_0Imm:$Ii), 3202"$Pd4 = vcmpw.eq($Rss32,#$Ii)", 3203tc_643b4717, TypeALU64>, Enc_0d8adb { 3204let Inst{4-2} = 0b100; 3205let Inst{13-13} = 0b0; 3206let Inst{31-21} = 0b11011100000; 3207} 3208def A4_vcmpwgti : HInst< 3209(outs PredRegs:$Pd4), 3210(ins DoubleRegs:$Rss32, s8_0Imm:$Ii), 3211"$Pd4 = vcmpw.gt($Rss32,#$Ii)", 3212tc_643b4717, TypeALU64>, Enc_0d8adb { 3213let Inst{4-2} = 0b100; 3214let Inst{13-13} = 0b0; 3215let Inst{31-21} = 0b11011100001; 3216} 3217def A4_vcmpwgtui : HInst< 3218(outs PredRegs:$Pd4), 3219(ins DoubleRegs:$Rss32, u7_0Imm:$Ii), 3220"$Pd4 = vcmpw.gtu($Rss32,#$Ii)", 3221tc_643b4717, TypeALU64>, Enc_3680c2 { 3222let Inst{4-2} = 0b100; 3223let Inst{13-12} = 0b00; 3224let Inst{31-21} = 0b11011100010; 3225} 3226def A4_vrmaxh : HInst< 3227(outs DoubleRegs:$Rxx32), 3228(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Ru32), 3229"$Rxx32 = vrmaxh($Rss32,$Ru32)", 3230tc_5b54b33f, TypeS_3op>, Enc_412ff0 { 3231let Inst{7-5} = 0b001; 3232let Inst{13-13} = 0b0; 3233let Inst{31-21} = 0b11001011001; 3234let prefersSlot3 = 1; 3235let Constraints = "$Rxx32 = $Rxx32in"; 3236} 3237def A4_vrmaxuh : HInst< 3238(outs DoubleRegs:$Rxx32), 3239(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Ru32), 3240"$Rxx32 = vrmaxuh($Rss32,$Ru32)", 3241tc_5b54b33f, TypeS_3op>, Enc_412ff0 { 3242let Inst{7-5} = 0b001; 3243let Inst{13-13} = 0b1; 3244let Inst{31-21} = 0b11001011001; 3245let prefersSlot3 = 1; 3246let Constraints = "$Rxx32 = $Rxx32in"; 3247} 3248def A4_vrmaxuw : HInst< 3249(outs DoubleRegs:$Rxx32), 3250(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Ru32), 3251"$Rxx32 = vrmaxuw($Rss32,$Ru32)", 3252tc_5b54b33f, TypeS_3op>, Enc_412ff0 { 3253let Inst{7-5} = 0b010; 3254let Inst{13-13} = 0b1; 3255let Inst{31-21} = 0b11001011001; 3256let prefersSlot3 = 1; 3257let Constraints = "$Rxx32 = $Rxx32in"; 3258} 3259def A4_vrmaxw : HInst< 3260(outs DoubleRegs:$Rxx32), 3261(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Ru32), 3262"$Rxx32 = vrmaxw($Rss32,$Ru32)", 3263tc_5b54b33f, TypeS_3op>, Enc_412ff0 { 3264let Inst{7-5} = 0b010; 3265let Inst{13-13} = 0b0; 3266let Inst{31-21} = 0b11001011001; 3267let prefersSlot3 = 1; 3268let Constraints = "$Rxx32 = $Rxx32in"; 3269} 3270def A4_vrminh : HInst< 3271(outs DoubleRegs:$Rxx32), 3272(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Ru32), 3273"$Rxx32 = vrminh($Rss32,$Ru32)", 3274tc_5b54b33f, TypeS_3op>, Enc_412ff0 { 3275let Inst{7-5} = 0b101; 3276let Inst{13-13} = 0b0; 3277let Inst{31-21} = 0b11001011001; 3278let prefersSlot3 = 1; 3279let Constraints = "$Rxx32 = $Rxx32in"; 3280} 3281def A4_vrminuh : HInst< 3282(outs DoubleRegs:$Rxx32), 3283(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Ru32), 3284"$Rxx32 = vrminuh($Rss32,$Ru32)", 3285tc_5b54b33f, TypeS_3op>, Enc_412ff0 { 3286let Inst{7-5} = 0b101; 3287let Inst{13-13} = 0b1; 3288let Inst{31-21} = 0b11001011001; 3289let prefersSlot3 = 1; 3290let Constraints = "$Rxx32 = $Rxx32in"; 3291} 3292def A4_vrminuw : HInst< 3293(outs DoubleRegs:$Rxx32), 3294(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Ru32), 3295"$Rxx32 = vrminuw($Rss32,$Ru32)", 3296tc_5b54b33f, TypeS_3op>, Enc_412ff0 { 3297let Inst{7-5} = 0b110; 3298let Inst{13-13} = 0b1; 3299let Inst{31-21} = 0b11001011001; 3300let prefersSlot3 = 1; 3301let Constraints = "$Rxx32 = $Rxx32in"; 3302} 3303def A4_vrminw : HInst< 3304(outs DoubleRegs:$Rxx32), 3305(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Ru32), 3306"$Rxx32 = vrminw($Rss32,$Ru32)", 3307tc_5b54b33f, TypeS_3op>, Enc_412ff0 { 3308let Inst{7-5} = 0b110; 3309let Inst{13-13} = 0b0; 3310let Inst{31-21} = 0b11001011001; 3311let prefersSlot3 = 1; 3312let Constraints = "$Rxx32 = $Rxx32in"; 3313} 3314def A5_ACS : HInst< 3315(outs DoubleRegs:$Rxx32, PredRegs:$Pe4), 3316(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 3317"$Rxx32,$Pe4 = vacsh($Rss32,$Rtt32)", 3318tc_d1aa9eaa, TypeM>, Enc_831a7d, Requires<[HasV55]> { 3319let Inst{7-7} = 0b0; 3320let Inst{13-13} = 0b0; 3321let Inst{31-21} = 0b11101010101; 3322let isPredicateLate = 1; 3323let prefersSlot3 = 1; 3324let Defs = [USR_OVF]; 3325let Constraints = "$Rxx32 = $Rxx32in"; 3326} 3327def A5_vaddhubs : HInst< 3328(outs IntRegs:$Rd32), 3329(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 3330"$Rd32 = vaddhub($Rss32,$Rtt32):sat", 3331tc_002cb246, TypeS_3op>, Enc_d2216a { 3332let Inst{7-5} = 0b001; 3333let Inst{13-13} = 0b0; 3334let Inst{31-21} = 0b11000001010; 3335let hasNewValue = 1; 3336let opNewValue = 0; 3337let prefersSlot3 = 1; 3338let Defs = [USR_OVF]; 3339} 3340def A6_vcmpbeq_notany : HInst< 3341(outs PredRegs:$Pd4), 3342(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 3343"$Pd4 = !any8(vcmpb.eq($Rss32,$Rtt32))", 3344tc_1fc97744, TypeALU64>, Enc_fcf7a7, Requires<[HasV65]> { 3345let Inst{7-2} = 0b001000; 3346let Inst{13-13} = 0b1; 3347let Inst{31-21} = 0b11010010000; 3348} 3349def A6_vminub_RdP : HInst< 3350(outs DoubleRegs:$Rdd32, PredRegs:$Pe4), 3351(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), 3352"$Rdd32,$Pe4 = vminub($Rtt32,$Rss32)", 3353tc_f9058dd7, TypeM>, Enc_d2c7f1, Requires<[HasV62]> { 3354let Inst{7-7} = 0b0; 3355let Inst{13-13} = 0b0; 3356let Inst{31-21} = 0b11101010111; 3357let isPredicateLate = 1; 3358let prefersSlot3 = 1; 3359} 3360def C2_all8 : HInst< 3361(outs PredRegs:$Pd4), 3362(ins PredRegs:$Ps4), 3363"$Pd4 = all8($Ps4)", 3364tc_de554571, TypeCR>, Enc_65d691 { 3365let Inst{13-2} = 0b000000000000; 3366let Inst{31-18} = 0b01101011101000; 3367} 3368def C2_and : HInst< 3369(outs PredRegs:$Pd4), 3370(ins PredRegs:$Pt4, PredRegs:$Ps4), 3371"$Pd4 = and($Pt4,$Ps4)", 3372tc_640086b5, TypeCR>, Enc_454a26 { 3373let Inst{7-2} = 0b000000; 3374let Inst{13-10} = 0b0000; 3375let Inst{31-18} = 0b01101011000000; 3376} 3377def C2_andn : HInst< 3378(outs PredRegs:$Pd4), 3379(ins PredRegs:$Pt4, PredRegs:$Ps4), 3380"$Pd4 = and($Pt4,!$Ps4)", 3381tc_640086b5, TypeCR>, Enc_454a26 { 3382let Inst{7-2} = 0b000000; 3383let Inst{13-10} = 0b0000; 3384let Inst{31-18} = 0b01101011011000; 3385} 3386def C2_any8 : HInst< 3387(outs PredRegs:$Pd4), 3388(ins PredRegs:$Ps4), 3389"$Pd4 = any8($Ps4)", 3390tc_de554571, TypeCR>, Enc_65d691 { 3391let Inst{13-2} = 0b000000000000; 3392let Inst{31-18} = 0b01101011100000; 3393} 3394def C2_bitsclr : HInst< 3395(outs PredRegs:$Pd4), 3396(ins IntRegs:$Rs32, IntRegs:$Rt32), 3397"$Pd4 = bitsclr($Rs32,$Rt32)", 3398tc_85d5d03f, TypeS_3op>, Enc_c2b48e { 3399let Inst{7-2} = 0b000000; 3400let Inst{13-13} = 0b0; 3401let Inst{31-21} = 0b11000111100; 3402} 3403def C2_bitsclri : HInst< 3404(outs PredRegs:$Pd4), 3405(ins IntRegs:$Rs32, u6_0Imm:$Ii), 3406"$Pd4 = bitsclr($Rs32,#$Ii)", 3407tc_643b4717, TypeS_2op>, Enc_5d6c34 { 3408let Inst{7-2} = 0b000000; 3409let Inst{31-21} = 0b10000101100; 3410} 3411def C2_bitsset : HInst< 3412(outs PredRegs:$Pd4), 3413(ins IntRegs:$Rs32, IntRegs:$Rt32), 3414"$Pd4 = bitsset($Rs32,$Rt32)", 3415tc_85d5d03f, TypeS_3op>, Enc_c2b48e { 3416let Inst{7-2} = 0b000000; 3417let Inst{13-13} = 0b0; 3418let Inst{31-21} = 0b11000111010; 3419} 3420def C2_ccombinewf : HInst< 3421(outs DoubleRegs:$Rdd32), 3422(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), 3423"if (!$Pu4) $Rdd32 = combine($Rs32,$Rt32)", 3424tc_4c5ba658, TypeALU32_3op>, Enc_cb4b4e, PredNewRel { 3425let Inst{7-7} = 0b1; 3426let Inst{13-13} = 0b0; 3427let Inst{31-21} = 0b11111101000; 3428let isPredicated = 1; 3429let isPredicatedFalse = 1; 3430let BaseOpcode = "A2_combinew"; 3431} 3432def C2_ccombinewnewf : HInst< 3433(outs DoubleRegs:$Rdd32), 3434(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), 3435"if (!$Pu4.new) $Rdd32 = combine($Rs32,$Rt32)", 3436tc_05c070ec, TypeALU32_3op>, Enc_cb4b4e, PredNewRel { 3437let Inst{7-7} = 0b1; 3438let Inst{13-13} = 0b1; 3439let Inst{31-21} = 0b11111101000; 3440let isPredicated = 1; 3441let isPredicatedFalse = 1; 3442let isPredicatedNew = 1; 3443let BaseOpcode = "A2_combinew"; 3444} 3445def C2_ccombinewnewt : HInst< 3446(outs DoubleRegs:$Rdd32), 3447(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), 3448"if ($Pu4.new) $Rdd32 = combine($Rs32,$Rt32)", 3449tc_05c070ec, TypeALU32_3op>, Enc_cb4b4e, PredNewRel { 3450let Inst{7-7} = 0b0; 3451let Inst{13-13} = 0b1; 3452let Inst{31-21} = 0b11111101000; 3453let isPredicated = 1; 3454let isPredicatedNew = 1; 3455let BaseOpcode = "A2_combinew"; 3456} 3457def C2_ccombinewt : HInst< 3458(outs DoubleRegs:$Rdd32), 3459(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), 3460"if ($Pu4) $Rdd32 = combine($Rs32,$Rt32)", 3461tc_4c5ba658, TypeALU32_3op>, Enc_cb4b4e, PredNewRel { 3462let Inst{7-7} = 0b0; 3463let Inst{13-13} = 0b0; 3464let Inst{31-21} = 0b11111101000; 3465let isPredicated = 1; 3466let BaseOpcode = "A2_combinew"; 3467} 3468def C2_cmoveif : HInst< 3469(outs IntRegs:$Rd32), 3470(ins PredRegs:$Pu4, s32_0Imm:$Ii), 3471"if (!$Pu4) $Rd32 = #$Ii", 3472tc_5a2711e5, TypeALU32_2op>, Enc_cda00a, PredNewRel, ImmRegRel { 3473let Inst{13-13} = 0b0; 3474let Inst{20-20} = 0b0; 3475let Inst{31-23} = 0b011111101; 3476let isPredicated = 1; 3477let isPredicatedFalse = 1; 3478let hasNewValue = 1; 3479let opNewValue = 0; 3480let CextOpcode = "A2_tfr"; 3481let InputType = "imm"; 3482let BaseOpcode = "A2_tfrsi"; 3483let isMoveImm = 1; 3484let isExtendable = 1; 3485let opExtendable = 2; 3486let isExtentSigned = 1; 3487let opExtentBits = 12; 3488let opExtentAlign = 0; 3489} 3490def C2_cmoveit : HInst< 3491(outs IntRegs:$Rd32), 3492(ins PredRegs:$Pu4, s32_0Imm:$Ii), 3493"if ($Pu4) $Rd32 = #$Ii", 3494tc_5a2711e5, TypeALU32_2op>, Enc_cda00a, PredNewRel, ImmRegRel { 3495let Inst{13-13} = 0b0; 3496let Inst{20-20} = 0b0; 3497let Inst{31-23} = 0b011111100; 3498let isPredicated = 1; 3499let hasNewValue = 1; 3500let opNewValue = 0; 3501let CextOpcode = "A2_tfr"; 3502let InputType = "imm"; 3503let BaseOpcode = "A2_tfrsi"; 3504let isMoveImm = 1; 3505let isExtendable = 1; 3506let opExtendable = 2; 3507let isExtentSigned = 1; 3508let opExtentBits = 12; 3509let opExtentAlign = 0; 3510} 3511def C2_cmovenewif : HInst< 3512(outs IntRegs:$Rd32), 3513(ins PredRegs:$Pu4, s32_0Imm:$Ii), 3514"if (!$Pu4.new) $Rd32 = #$Ii", 3515tc_1ae57e39, TypeALU32_2op>, Enc_cda00a, PredNewRel, ImmRegRel { 3516let Inst{13-13} = 0b1; 3517let Inst{20-20} = 0b0; 3518let Inst{31-23} = 0b011111101; 3519let isPredicated = 1; 3520let isPredicatedFalse = 1; 3521let hasNewValue = 1; 3522let opNewValue = 0; 3523let isPredicatedNew = 1; 3524let CextOpcode = "A2_tfr"; 3525let InputType = "imm"; 3526let BaseOpcode = "A2_tfrsi"; 3527let isMoveImm = 1; 3528let isExtendable = 1; 3529let opExtendable = 2; 3530let isExtentSigned = 1; 3531let opExtentBits = 12; 3532let opExtentAlign = 0; 3533} 3534def C2_cmovenewit : HInst< 3535(outs IntRegs:$Rd32), 3536(ins PredRegs:$Pu4, s32_0Imm:$Ii), 3537"if ($Pu4.new) $Rd32 = #$Ii", 3538tc_1ae57e39, TypeALU32_2op>, Enc_cda00a, PredNewRel, ImmRegRel { 3539let Inst{13-13} = 0b1; 3540let Inst{20-20} = 0b0; 3541let Inst{31-23} = 0b011111100; 3542let isPredicated = 1; 3543let hasNewValue = 1; 3544let opNewValue = 0; 3545let isPredicatedNew = 1; 3546let CextOpcode = "A2_tfr"; 3547let InputType = "imm"; 3548let BaseOpcode = "A2_tfrsi"; 3549let isMoveImm = 1; 3550let isExtendable = 1; 3551let opExtendable = 2; 3552let isExtentSigned = 1; 3553let opExtentBits = 12; 3554let opExtentAlign = 0; 3555} 3556def C2_cmpeq : HInst< 3557(outs PredRegs:$Pd4), 3558(ins IntRegs:$Rs32, IntRegs:$Rt32), 3559"$Pd4 = cmp.eq($Rs32,$Rt32)", 3560tc_de4df740, TypeALU32_3op>, Enc_c2b48e, ImmRegRel { 3561let Inst{7-2} = 0b000000; 3562let Inst{13-13} = 0b0; 3563let Inst{31-21} = 0b11110010000; 3564let CextOpcode = "C2_cmpeq"; 3565let InputType = "reg"; 3566let isCommutable = 1; 3567let isCompare = 1; 3568} 3569def C2_cmpeqi : HInst< 3570(outs PredRegs:$Pd4), 3571(ins IntRegs:$Rs32, s32_0Imm:$Ii), 3572"$Pd4 = cmp.eq($Rs32,#$Ii)", 3573tc_56f114f4, TypeALU32_2op>, Enc_bd0b33, ImmRegRel { 3574let Inst{4-2} = 0b000; 3575let Inst{31-22} = 0b0111010100; 3576let CextOpcode = "C2_cmpeq"; 3577let InputType = "imm"; 3578let isCompare = 1; 3579let isExtendable = 1; 3580let opExtendable = 2; 3581let isExtentSigned = 1; 3582let opExtentBits = 10; 3583let opExtentAlign = 0; 3584} 3585def C2_cmpeqp : HInst< 3586(outs PredRegs:$Pd4), 3587(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 3588"$Pd4 = cmp.eq($Rss32,$Rtt32)", 3589tc_85d5d03f, TypeALU64>, Enc_fcf7a7 { 3590let Inst{7-2} = 0b000000; 3591let Inst{13-13} = 0b0; 3592let Inst{31-21} = 0b11010010100; 3593let isCommutable = 1; 3594let isCompare = 1; 3595} 3596def C2_cmpgei : HInst< 3597(outs PredRegs:$Pd4), 3598(ins IntRegs:$Rs32, s8_0Imm:$Ii), 3599"$Pd4 = cmp.ge($Rs32,#$Ii)", 3600tc_56f114f4, TypeALU32_2op> { 3601let isCompare = 1; 3602let isPseudo = 1; 3603} 3604def C2_cmpgeui : HInst< 3605(outs PredRegs:$Pd4), 3606(ins IntRegs:$Rs32, u8_0Imm:$Ii), 3607"$Pd4 = cmp.geu($Rs32,#$Ii)", 3608tc_56f114f4, TypeALU32_2op> { 3609let isCompare = 1; 3610let isPseudo = 1; 3611} 3612def C2_cmpgt : HInst< 3613(outs PredRegs:$Pd4), 3614(ins IntRegs:$Rs32, IntRegs:$Rt32), 3615"$Pd4 = cmp.gt($Rs32,$Rt32)", 3616tc_de4df740, TypeALU32_3op>, Enc_c2b48e, ImmRegRel { 3617let Inst{7-2} = 0b000000; 3618let Inst{13-13} = 0b0; 3619let Inst{31-21} = 0b11110010010; 3620let CextOpcode = "C2_cmpgt"; 3621let InputType = "reg"; 3622let isCompare = 1; 3623} 3624def C2_cmpgti : HInst< 3625(outs PredRegs:$Pd4), 3626(ins IntRegs:$Rs32, s32_0Imm:$Ii), 3627"$Pd4 = cmp.gt($Rs32,#$Ii)", 3628tc_56f114f4, TypeALU32_2op>, Enc_bd0b33, ImmRegRel { 3629let Inst{4-2} = 0b000; 3630let Inst{31-22} = 0b0111010101; 3631let CextOpcode = "C2_cmpgt"; 3632let InputType = "imm"; 3633let isCompare = 1; 3634let isExtendable = 1; 3635let opExtendable = 2; 3636let isExtentSigned = 1; 3637let opExtentBits = 10; 3638let opExtentAlign = 0; 3639} 3640def C2_cmpgtp : HInst< 3641(outs PredRegs:$Pd4), 3642(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 3643"$Pd4 = cmp.gt($Rss32,$Rtt32)", 3644tc_85d5d03f, TypeALU64>, Enc_fcf7a7 { 3645let Inst{7-2} = 0b010000; 3646let Inst{13-13} = 0b0; 3647let Inst{31-21} = 0b11010010100; 3648let isCompare = 1; 3649} 3650def C2_cmpgtu : HInst< 3651(outs PredRegs:$Pd4), 3652(ins IntRegs:$Rs32, IntRegs:$Rt32), 3653"$Pd4 = cmp.gtu($Rs32,$Rt32)", 3654tc_de4df740, TypeALU32_3op>, Enc_c2b48e, ImmRegRel { 3655let Inst{7-2} = 0b000000; 3656let Inst{13-13} = 0b0; 3657let Inst{31-21} = 0b11110010011; 3658let CextOpcode = "C2_cmpgtu"; 3659let InputType = "reg"; 3660let isCompare = 1; 3661} 3662def C2_cmpgtui : HInst< 3663(outs PredRegs:$Pd4), 3664(ins IntRegs:$Rs32, u32_0Imm:$Ii), 3665"$Pd4 = cmp.gtu($Rs32,#$Ii)", 3666tc_56f114f4, TypeALU32_2op>, Enc_c0cdde, ImmRegRel { 3667let Inst{4-2} = 0b000; 3668let Inst{31-21} = 0b01110101100; 3669let CextOpcode = "C2_cmpgtu"; 3670let InputType = "imm"; 3671let isCompare = 1; 3672let isExtendable = 1; 3673let opExtendable = 2; 3674let isExtentSigned = 0; 3675let opExtentBits = 9; 3676let opExtentAlign = 0; 3677} 3678def C2_cmpgtup : HInst< 3679(outs PredRegs:$Pd4), 3680(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 3681"$Pd4 = cmp.gtu($Rss32,$Rtt32)", 3682tc_85d5d03f, TypeALU64>, Enc_fcf7a7 { 3683let Inst{7-2} = 0b100000; 3684let Inst{13-13} = 0b0; 3685let Inst{31-21} = 0b11010010100; 3686let isCompare = 1; 3687} 3688def C2_cmplt : HInst< 3689(outs PredRegs:$Pd4), 3690(ins IntRegs:$Rs32, IntRegs:$Rt32), 3691"$Pd4 = cmp.lt($Rs32,$Rt32)", 3692tc_56f114f4, TypeALU32_3op> { 3693let isCompare = 1; 3694let isPseudo = 1; 3695let isCodeGenOnly = 1; 3696} 3697def C2_cmpltu : HInst< 3698(outs PredRegs:$Pd4), 3699(ins IntRegs:$Rs32, IntRegs:$Rt32), 3700"$Pd4 = cmp.ltu($Rs32,$Rt32)", 3701tc_56f114f4, TypeALU32_3op> { 3702let isCompare = 1; 3703let isPseudo = 1; 3704let isCodeGenOnly = 1; 3705} 3706def C2_mask : HInst< 3707(outs DoubleRegs:$Rdd32), 3708(ins PredRegs:$Pt4), 3709"$Rdd32 = mask($Pt4)", 3710tc_0ae0825c, TypeS_2op>, Enc_78e566 { 3711let Inst{7-5} = 0b000; 3712let Inst{13-10} = 0b0000; 3713let Inst{31-16} = 0b1000011000000000; 3714} 3715def C2_mux : HInst< 3716(outs IntRegs:$Rd32), 3717(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), 3718"$Rd32 = mux($Pu4,$Rs32,$Rt32)", 3719tc_4c5ba658, TypeALU32_3op>, Enc_ea4c54 { 3720let Inst{7-7} = 0b0; 3721let Inst{13-13} = 0b0; 3722let Inst{31-21} = 0b11110100000; 3723let hasNewValue = 1; 3724let opNewValue = 0; 3725let InputType = "reg"; 3726} 3727def C2_muxii : HInst< 3728(outs IntRegs:$Rd32), 3729(ins PredRegs:$Pu4, s32_0Imm:$Ii, s8_0Imm:$II), 3730"$Rd32 = mux($Pu4,#$Ii,#$II)", 3731tc_4c5ba658, TypeALU32_2op>, Enc_830e5d { 3732let Inst{31-25} = 0b0111101; 3733let hasNewValue = 1; 3734let opNewValue = 0; 3735let isExtendable = 1; 3736let opExtendable = 2; 3737let isExtentSigned = 1; 3738let opExtentBits = 8; 3739let opExtentAlign = 0; 3740} 3741def C2_muxir : HInst< 3742(outs IntRegs:$Rd32), 3743(ins PredRegs:$Pu4, IntRegs:$Rs32, s32_0Imm:$Ii), 3744"$Rd32 = mux($Pu4,$Rs32,#$Ii)", 3745tc_4c5ba658, TypeALU32_2op>, Enc_e38e1f { 3746let Inst{13-13} = 0b0; 3747let Inst{31-23} = 0b011100110; 3748let hasNewValue = 1; 3749let opNewValue = 0; 3750let InputType = "imm"; 3751let isExtendable = 1; 3752let opExtendable = 3; 3753let isExtentSigned = 1; 3754let opExtentBits = 8; 3755let opExtentAlign = 0; 3756} 3757def C2_muxri : HInst< 3758(outs IntRegs:$Rd32), 3759(ins PredRegs:$Pu4, s32_0Imm:$Ii, IntRegs:$Rs32), 3760"$Rd32 = mux($Pu4,#$Ii,$Rs32)", 3761tc_4c5ba658, TypeALU32_2op>, Enc_e38e1f { 3762let Inst{13-13} = 0b0; 3763let Inst{31-23} = 0b011100111; 3764let hasNewValue = 1; 3765let opNewValue = 0; 3766let InputType = "imm"; 3767let isExtendable = 1; 3768let opExtendable = 2; 3769let isExtentSigned = 1; 3770let opExtentBits = 8; 3771let opExtentAlign = 0; 3772} 3773def C2_not : HInst< 3774(outs PredRegs:$Pd4), 3775(ins PredRegs:$Ps4), 3776"$Pd4 = not($Ps4)", 3777tc_de554571, TypeCR>, Enc_65d691 { 3778let Inst{13-2} = 0b000000000000; 3779let Inst{31-18} = 0b01101011110000; 3780} 3781def C2_or : HInst< 3782(outs PredRegs:$Pd4), 3783(ins PredRegs:$Pt4, PredRegs:$Ps4), 3784"$Pd4 = or($Pt4,$Ps4)", 3785tc_640086b5, TypeCR>, Enc_454a26 { 3786let Inst{7-2} = 0b000000; 3787let Inst{13-10} = 0b0000; 3788let Inst{31-18} = 0b01101011001000; 3789} 3790def C2_orn : HInst< 3791(outs PredRegs:$Pd4), 3792(ins PredRegs:$Pt4, PredRegs:$Ps4), 3793"$Pd4 = or($Pt4,!$Ps4)", 3794tc_640086b5, TypeCR>, Enc_454a26 { 3795let Inst{7-2} = 0b000000; 3796let Inst{13-10} = 0b0000; 3797let Inst{31-18} = 0b01101011111000; 3798} 3799def C2_pxfer_map : HInst< 3800(outs PredRegs:$Pd4), 3801(ins PredRegs:$Ps4), 3802"$Pd4 = $Ps4", 3803tc_640086b5, TypeMAPPING> { 3804let isPseudo = 1; 3805let isCodeGenOnly = 1; 3806} 3807def C2_tfrpr : HInst< 3808(outs IntRegs:$Rd32), 3809(ins PredRegs:$Ps4), 3810"$Rd32 = $Ps4", 3811tc_0ae0825c, TypeS_2op>, Enc_f5e933 { 3812let Inst{13-5} = 0b000000000; 3813let Inst{31-18} = 0b10001001010000; 3814let hasNewValue = 1; 3815let opNewValue = 0; 3816} 3817def C2_tfrrp : HInst< 3818(outs PredRegs:$Pd4), 3819(ins IntRegs:$Rs32), 3820"$Pd4 = $Rs32", 3821tc_cfd8378a, TypeS_2op>, Enc_48b75f { 3822let Inst{13-2} = 0b000000000000; 3823let Inst{31-21} = 0b10000101010; 3824} 3825def C2_vitpack : HInst< 3826(outs IntRegs:$Rd32), 3827(ins PredRegs:$Ps4, PredRegs:$Pt4), 3828"$Rd32 = vitpack($Ps4,$Pt4)", 3829tc_4414d8b1, TypeS_2op>, Enc_527412 { 3830let Inst{7-5} = 0b000; 3831let Inst{13-10} = 0b0000; 3832let Inst{31-18} = 0b10001001000000; 3833let hasNewValue = 1; 3834let opNewValue = 0; 3835let prefersSlot3 = 1; 3836} 3837def C2_vmux : HInst< 3838(outs DoubleRegs:$Rdd32), 3839(ins PredRegs:$Pu4, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 3840"$Rdd32 = vmux($Pu4,$Rss32,$Rtt32)", 3841tc_b4b5c03a, TypeALU64>, Enc_329361 { 3842let Inst{7-7} = 0b0; 3843let Inst{13-13} = 0b0; 3844let Inst{31-21} = 0b11010001000; 3845} 3846def C2_xor : HInst< 3847(outs PredRegs:$Pd4), 3848(ins PredRegs:$Ps4, PredRegs:$Pt4), 3849"$Pd4 = xor($Ps4,$Pt4)", 3850tc_640086b5, TypeCR>, Enc_284ebb { 3851let Inst{7-2} = 0b000000; 3852let Inst{13-10} = 0b0000; 3853let Inst{31-18} = 0b01101011010000; 3854} 3855def C4_addipc : HInst< 3856(outs IntRegs:$Rd32), 3857(ins u32_0Imm:$Ii), 3858"$Rd32 = add(pc,#$Ii)", 3859tc_a813cf9a, TypeCR>, Enc_607661 { 3860let Inst{6-5} = 0b00; 3861let Inst{13-13} = 0b0; 3862let Inst{31-16} = 0b0110101001001001; 3863let hasNewValue = 1; 3864let opNewValue = 0; 3865let isExtendable = 1; 3866let opExtendable = 1; 3867let isExtentSigned = 0; 3868let opExtentBits = 6; 3869let opExtentAlign = 0; 3870} 3871def C4_and_and : HInst< 3872(outs PredRegs:$Pd4), 3873(ins PredRegs:$Ps4, PredRegs:$Pt4, PredRegs:$Pu4), 3874"$Pd4 = and($Ps4,and($Pt4,$Pu4))", 3875tc_b31c2e97, TypeCR>, Enc_9ac432 { 3876let Inst{5-2} = 0b0000; 3877let Inst{13-10} = 0b0000; 3878let Inst{31-18} = 0b01101011000100; 3879} 3880def C4_and_andn : HInst< 3881(outs PredRegs:$Pd4), 3882(ins PredRegs:$Ps4, PredRegs:$Pt4, PredRegs:$Pu4), 3883"$Pd4 = and($Ps4,and($Pt4,!$Pu4))", 3884tc_b31c2e97, TypeCR>, Enc_9ac432 { 3885let Inst{5-2} = 0b0000; 3886let Inst{13-10} = 0b0000; 3887let Inst{31-18} = 0b01101011100100; 3888} 3889def C4_and_or : HInst< 3890(outs PredRegs:$Pd4), 3891(ins PredRegs:$Ps4, PredRegs:$Pt4, PredRegs:$Pu4), 3892"$Pd4 = and($Ps4,or($Pt4,$Pu4))", 3893tc_b31c2e97, TypeCR>, Enc_9ac432 { 3894let Inst{5-2} = 0b0000; 3895let Inst{13-10} = 0b0000; 3896let Inst{31-18} = 0b01101011001100; 3897} 3898def C4_and_orn : HInst< 3899(outs PredRegs:$Pd4), 3900(ins PredRegs:$Ps4, PredRegs:$Pt4, PredRegs:$Pu4), 3901"$Pd4 = and($Ps4,or($Pt4,!$Pu4))", 3902tc_b31c2e97, TypeCR>, Enc_9ac432 { 3903let Inst{5-2} = 0b0000; 3904let Inst{13-10} = 0b0000; 3905let Inst{31-18} = 0b01101011101100; 3906} 3907def C4_cmplte : HInst< 3908(outs PredRegs:$Pd4), 3909(ins IntRegs:$Rs32, IntRegs:$Rt32), 3910"$Pd4 = !cmp.gt($Rs32,$Rt32)", 3911tc_de4df740, TypeALU32_3op>, Enc_c2b48e, ImmRegRel { 3912let Inst{7-2} = 0b000100; 3913let Inst{13-13} = 0b0; 3914let Inst{31-21} = 0b11110010010; 3915let CextOpcode = "C4_cmplte"; 3916let InputType = "reg"; 3917let isCompare = 1; 3918} 3919def C4_cmpltei : HInst< 3920(outs PredRegs:$Pd4), 3921(ins IntRegs:$Rs32, s32_0Imm:$Ii), 3922"$Pd4 = !cmp.gt($Rs32,#$Ii)", 3923tc_56f114f4, TypeALU32_2op>, Enc_bd0b33, ImmRegRel { 3924let Inst{4-2} = 0b100; 3925let Inst{31-22} = 0b0111010101; 3926let CextOpcode = "C4_cmplte"; 3927let InputType = "imm"; 3928let isCompare = 1; 3929let isExtendable = 1; 3930let opExtendable = 2; 3931let isExtentSigned = 1; 3932let opExtentBits = 10; 3933let opExtentAlign = 0; 3934} 3935def C4_cmplteu : HInst< 3936(outs PredRegs:$Pd4), 3937(ins IntRegs:$Rs32, IntRegs:$Rt32), 3938"$Pd4 = !cmp.gtu($Rs32,$Rt32)", 3939tc_de4df740, TypeALU32_3op>, Enc_c2b48e, ImmRegRel { 3940let Inst{7-2} = 0b000100; 3941let Inst{13-13} = 0b0; 3942let Inst{31-21} = 0b11110010011; 3943let CextOpcode = "C4_cmplteu"; 3944let InputType = "reg"; 3945let isCompare = 1; 3946} 3947def C4_cmplteui : HInst< 3948(outs PredRegs:$Pd4), 3949(ins IntRegs:$Rs32, u32_0Imm:$Ii), 3950"$Pd4 = !cmp.gtu($Rs32,#$Ii)", 3951tc_56f114f4, TypeALU32_2op>, Enc_c0cdde, ImmRegRel { 3952let Inst{4-2} = 0b100; 3953let Inst{31-21} = 0b01110101100; 3954let CextOpcode = "C4_cmplteu"; 3955let InputType = "imm"; 3956let isCompare = 1; 3957let isExtendable = 1; 3958let opExtendable = 2; 3959let isExtentSigned = 0; 3960let opExtentBits = 9; 3961let opExtentAlign = 0; 3962} 3963def C4_cmpneq : HInst< 3964(outs PredRegs:$Pd4), 3965(ins IntRegs:$Rs32, IntRegs:$Rt32), 3966"$Pd4 = !cmp.eq($Rs32,$Rt32)", 3967tc_de4df740, TypeALU32_3op>, Enc_c2b48e, ImmRegRel { 3968let Inst{7-2} = 0b000100; 3969let Inst{13-13} = 0b0; 3970let Inst{31-21} = 0b11110010000; 3971let CextOpcode = "C4_cmpneq"; 3972let InputType = "reg"; 3973let isCommutable = 1; 3974let isCompare = 1; 3975} 3976def C4_cmpneqi : HInst< 3977(outs PredRegs:$Pd4), 3978(ins IntRegs:$Rs32, s32_0Imm:$Ii), 3979"$Pd4 = !cmp.eq($Rs32,#$Ii)", 3980tc_56f114f4, TypeALU32_2op>, Enc_bd0b33, ImmRegRel { 3981let Inst{4-2} = 0b100; 3982let Inst{31-22} = 0b0111010100; 3983let CextOpcode = "C4_cmpneq"; 3984let InputType = "imm"; 3985let isCompare = 1; 3986let isExtendable = 1; 3987let opExtendable = 2; 3988let isExtentSigned = 1; 3989let opExtentBits = 10; 3990let opExtentAlign = 0; 3991} 3992def C4_fastcorner9 : HInst< 3993(outs PredRegs:$Pd4), 3994(ins PredRegs:$Ps4, PredRegs:$Pt4), 3995"$Pd4 = fastcorner9($Ps4,$Pt4)", 3996tc_640086b5, TypeCR>, Enc_284ebb { 3997let Inst{7-2} = 0b100100; 3998let Inst{13-10} = 0b1000; 3999let Inst{31-18} = 0b01101011000000; 4000} 4001def C4_fastcorner9_not : HInst< 4002(outs PredRegs:$Pd4), 4003(ins PredRegs:$Ps4, PredRegs:$Pt4), 4004"$Pd4 = !fastcorner9($Ps4,$Pt4)", 4005tc_640086b5, TypeCR>, Enc_284ebb { 4006let Inst{7-2} = 0b100100; 4007let Inst{13-10} = 0b1000; 4008let Inst{31-18} = 0b01101011000100; 4009} 4010def C4_nbitsclr : HInst< 4011(outs PredRegs:$Pd4), 4012(ins IntRegs:$Rs32, IntRegs:$Rt32), 4013"$Pd4 = !bitsclr($Rs32,$Rt32)", 4014tc_85d5d03f, TypeS_3op>, Enc_c2b48e { 4015let Inst{7-2} = 0b000000; 4016let Inst{13-13} = 0b0; 4017let Inst{31-21} = 0b11000111101; 4018} 4019def C4_nbitsclri : HInst< 4020(outs PredRegs:$Pd4), 4021(ins IntRegs:$Rs32, u6_0Imm:$Ii), 4022"$Pd4 = !bitsclr($Rs32,#$Ii)", 4023tc_643b4717, TypeS_2op>, Enc_5d6c34 { 4024let Inst{7-2} = 0b000000; 4025let Inst{31-21} = 0b10000101101; 4026} 4027def C4_nbitsset : HInst< 4028(outs PredRegs:$Pd4), 4029(ins IntRegs:$Rs32, IntRegs:$Rt32), 4030"$Pd4 = !bitsset($Rs32,$Rt32)", 4031tc_85d5d03f, TypeS_3op>, Enc_c2b48e { 4032let Inst{7-2} = 0b000000; 4033let Inst{13-13} = 0b0; 4034let Inst{31-21} = 0b11000111011; 4035} 4036def C4_or_and : HInst< 4037(outs PredRegs:$Pd4), 4038(ins PredRegs:$Ps4, PredRegs:$Pt4, PredRegs:$Pu4), 4039"$Pd4 = or($Ps4,and($Pt4,$Pu4))", 4040tc_b31c2e97, TypeCR>, Enc_9ac432 { 4041let Inst{5-2} = 0b0000; 4042let Inst{13-10} = 0b0000; 4043let Inst{31-18} = 0b01101011010100; 4044} 4045def C4_or_andn : HInst< 4046(outs PredRegs:$Pd4), 4047(ins PredRegs:$Ps4, PredRegs:$Pt4, PredRegs:$Pu4), 4048"$Pd4 = or($Ps4,and($Pt4,!$Pu4))", 4049tc_b31c2e97, TypeCR>, Enc_9ac432 { 4050let Inst{5-2} = 0b0000; 4051let Inst{13-10} = 0b0000; 4052let Inst{31-18} = 0b01101011110100; 4053} 4054def C4_or_or : HInst< 4055(outs PredRegs:$Pd4), 4056(ins PredRegs:$Ps4, PredRegs:$Pt4, PredRegs:$Pu4), 4057"$Pd4 = or($Ps4,or($Pt4,$Pu4))", 4058tc_b31c2e97, TypeCR>, Enc_9ac432 { 4059let Inst{5-2} = 0b0000; 4060let Inst{13-10} = 0b0000; 4061let Inst{31-18} = 0b01101011011100; 4062} 4063def C4_or_orn : HInst< 4064(outs PredRegs:$Pd4), 4065(ins PredRegs:$Ps4, PredRegs:$Pt4, PredRegs:$Pu4), 4066"$Pd4 = or($Ps4,or($Pt4,!$Pu4))", 4067tc_b31c2e97, TypeCR>, Enc_9ac432 { 4068let Inst{5-2} = 0b0000; 4069let Inst{13-10} = 0b0000; 4070let Inst{31-18} = 0b01101011111100; 4071} 4072def F2_conv_d2df : HInst< 4073(outs DoubleRegs:$Rdd32), 4074(ins DoubleRegs:$Rss32), 4075"$Rdd32 = convert_d2df($Rss32)", 4076tc_3a867367, TypeS_2op>, Enc_b9c5fb { 4077let Inst{13-5} = 0b000000011; 4078let Inst{31-21} = 0b10000000111; 4079let isFP = 1; 4080let Uses = [USR]; 4081} 4082def F2_conv_d2sf : HInst< 4083(outs IntRegs:$Rd32), 4084(ins DoubleRegs:$Rss32), 4085"$Rd32 = convert_d2sf($Rss32)", 4086tc_3a867367, TypeS_2op>, Enc_90cd8b { 4087let Inst{13-5} = 0b000000001; 4088let Inst{31-21} = 0b10001000010; 4089let hasNewValue = 1; 4090let opNewValue = 0; 4091let isFP = 1; 4092let Uses = [USR]; 4093} 4094def F2_conv_df2d : HInst< 4095(outs DoubleRegs:$Rdd32), 4096(ins DoubleRegs:$Rss32), 4097"$Rdd32 = convert_df2d($Rss32)", 4098tc_3a867367, TypeS_2op>, Enc_b9c5fb { 4099let Inst{13-5} = 0b000000000; 4100let Inst{31-21} = 0b10000000111; 4101let isFP = 1; 4102let Uses = [USR]; 4103} 4104def F2_conv_df2d_chop : HInst< 4105(outs DoubleRegs:$Rdd32), 4106(ins DoubleRegs:$Rss32), 4107"$Rdd32 = convert_df2d($Rss32):chop", 4108tc_3a867367, TypeS_2op>, Enc_b9c5fb { 4109let Inst{13-5} = 0b000000110; 4110let Inst{31-21} = 0b10000000111; 4111let isFP = 1; 4112let Uses = [USR]; 4113} 4114def F2_conv_df2sf : HInst< 4115(outs IntRegs:$Rd32), 4116(ins DoubleRegs:$Rss32), 4117"$Rd32 = convert_df2sf($Rss32)", 4118tc_3a867367, TypeS_2op>, Enc_90cd8b { 4119let Inst{13-5} = 0b000000001; 4120let Inst{31-21} = 0b10001000000; 4121let hasNewValue = 1; 4122let opNewValue = 0; 4123let isFP = 1; 4124let Uses = [USR]; 4125} 4126def F2_conv_df2ud : HInst< 4127(outs DoubleRegs:$Rdd32), 4128(ins DoubleRegs:$Rss32), 4129"$Rdd32 = convert_df2ud($Rss32)", 4130tc_3a867367, TypeS_2op>, Enc_b9c5fb { 4131let Inst{13-5} = 0b000000001; 4132let Inst{31-21} = 0b10000000111; 4133let isFP = 1; 4134let Uses = [USR]; 4135} 4136def F2_conv_df2ud_chop : HInst< 4137(outs DoubleRegs:$Rdd32), 4138(ins DoubleRegs:$Rss32), 4139"$Rdd32 = convert_df2ud($Rss32):chop", 4140tc_3a867367, TypeS_2op>, Enc_b9c5fb { 4141let Inst{13-5} = 0b000000111; 4142let Inst{31-21} = 0b10000000111; 4143let isFP = 1; 4144let Uses = [USR]; 4145} 4146def F2_conv_df2uw : HInst< 4147(outs IntRegs:$Rd32), 4148(ins DoubleRegs:$Rss32), 4149"$Rd32 = convert_df2uw($Rss32)", 4150tc_3a867367, TypeS_2op>, Enc_90cd8b { 4151let Inst{13-5} = 0b000000001; 4152let Inst{31-21} = 0b10001000011; 4153let hasNewValue = 1; 4154let opNewValue = 0; 4155let isFP = 1; 4156let Uses = [USR]; 4157} 4158def F2_conv_df2uw_chop : HInst< 4159(outs IntRegs:$Rd32), 4160(ins DoubleRegs:$Rss32), 4161"$Rd32 = convert_df2uw($Rss32):chop", 4162tc_3a867367, TypeS_2op>, Enc_90cd8b { 4163let Inst{13-5} = 0b000000001; 4164let Inst{31-21} = 0b10001000101; 4165let hasNewValue = 1; 4166let opNewValue = 0; 4167let isFP = 1; 4168let Uses = [USR]; 4169} 4170def F2_conv_df2w : HInst< 4171(outs IntRegs:$Rd32), 4172(ins DoubleRegs:$Rss32), 4173"$Rd32 = convert_df2w($Rss32)", 4174tc_3a867367, TypeS_2op>, Enc_90cd8b { 4175let Inst{13-5} = 0b000000001; 4176let Inst{31-21} = 0b10001000100; 4177let hasNewValue = 1; 4178let opNewValue = 0; 4179let isFP = 1; 4180let Uses = [USR]; 4181} 4182def F2_conv_df2w_chop : HInst< 4183(outs IntRegs:$Rd32), 4184(ins DoubleRegs:$Rss32), 4185"$Rd32 = convert_df2w($Rss32):chop", 4186tc_3a867367, TypeS_2op>, Enc_90cd8b { 4187let Inst{13-5} = 0b000000001; 4188let Inst{31-21} = 0b10001000111; 4189let hasNewValue = 1; 4190let opNewValue = 0; 4191let isFP = 1; 4192let Uses = [USR]; 4193} 4194def F2_conv_sf2d : HInst< 4195(outs DoubleRegs:$Rdd32), 4196(ins IntRegs:$Rs32), 4197"$Rdd32 = convert_sf2d($Rs32)", 4198tc_3a867367, TypeS_2op>, Enc_3a3d62 { 4199let Inst{13-5} = 0b000000100; 4200let Inst{31-21} = 0b10000100100; 4201let isFP = 1; 4202let Uses = [USR]; 4203} 4204def F2_conv_sf2d_chop : HInst< 4205(outs DoubleRegs:$Rdd32), 4206(ins IntRegs:$Rs32), 4207"$Rdd32 = convert_sf2d($Rs32):chop", 4208tc_3a867367, TypeS_2op>, Enc_3a3d62 { 4209let Inst{13-5} = 0b000000110; 4210let Inst{31-21} = 0b10000100100; 4211let isFP = 1; 4212let Uses = [USR]; 4213} 4214def F2_conv_sf2df : HInst< 4215(outs DoubleRegs:$Rdd32), 4216(ins IntRegs:$Rs32), 4217"$Rdd32 = convert_sf2df($Rs32)", 4218tc_3a867367, TypeS_2op>, Enc_3a3d62 { 4219let Inst{13-5} = 0b000000000; 4220let Inst{31-21} = 0b10000100100; 4221let isFP = 1; 4222let Uses = [USR]; 4223} 4224def F2_conv_sf2ud : HInst< 4225(outs DoubleRegs:$Rdd32), 4226(ins IntRegs:$Rs32), 4227"$Rdd32 = convert_sf2ud($Rs32)", 4228tc_3a867367, TypeS_2op>, Enc_3a3d62 { 4229let Inst{13-5} = 0b000000011; 4230let Inst{31-21} = 0b10000100100; 4231let isFP = 1; 4232let Uses = [USR]; 4233} 4234def F2_conv_sf2ud_chop : HInst< 4235(outs DoubleRegs:$Rdd32), 4236(ins IntRegs:$Rs32), 4237"$Rdd32 = convert_sf2ud($Rs32):chop", 4238tc_3a867367, TypeS_2op>, Enc_3a3d62 { 4239let Inst{13-5} = 0b000000101; 4240let Inst{31-21} = 0b10000100100; 4241let isFP = 1; 4242let Uses = [USR]; 4243} 4244def F2_conv_sf2uw : HInst< 4245(outs IntRegs:$Rd32), 4246(ins IntRegs:$Rs32), 4247"$Rd32 = convert_sf2uw($Rs32)", 4248tc_3a867367, TypeS_2op>, Enc_5e2823 { 4249let Inst{13-5} = 0b000000000; 4250let Inst{31-21} = 0b10001011011; 4251let hasNewValue = 1; 4252let opNewValue = 0; 4253let isFP = 1; 4254let Uses = [USR]; 4255} 4256def F2_conv_sf2uw_chop : HInst< 4257(outs IntRegs:$Rd32), 4258(ins IntRegs:$Rs32), 4259"$Rd32 = convert_sf2uw($Rs32):chop", 4260tc_3a867367, TypeS_2op>, Enc_5e2823 { 4261let Inst{13-5} = 0b000000001; 4262let Inst{31-21} = 0b10001011011; 4263let hasNewValue = 1; 4264let opNewValue = 0; 4265let isFP = 1; 4266let Uses = [USR]; 4267} 4268def F2_conv_sf2w : HInst< 4269(outs IntRegs:$Rd32), 4270(ins IntRegs:$Rs32), 4271"$Rd32 = convert_sf2w($Rs32)", 4272tc_3a867367, TypeS_2op>, Enc_5e2823 { 4273let Inst{13-5} = 0b000000000; 4274let Inst{31-21} = 0b10001011100; 4275let hasNewValue = 1; 4276let opNewValue = 0; 4277let isFP = 1; 4278let Uses = [USR]; 4279} 4280def F2_conv_sf2w_chop : HInst< 4281(outs IntRegs:$Rd32), 4282(ins IntRegs:$Rs32), 4283"$Rd32 = convert_sf2w($Rs32):chop", 4284tc_3a867367, TypeS_2op>, Enc_5e2823 { 4285let Inst{13-5} = 0b000000001; 4286let Inst{31-21} = 0b10001011100; 4287let hasNewValue = 1; 4288let opNewValue = 0; 4289let isFP = 1; 4290let Uses = [USR]; 4291} 4292def F2_conv_ud2df : HInst< 4293(outs DoubleRegs:$Rdd32), 4294(ins DoubleRegs:$Rss32), 4295"$Rdd32 = convert_ud2df($Rss32)", 4296tc_3a867367, TypeS_2op>, Enc_b9c5fb { 4297let Inst{13-5} = 0b000000010; 4298let Inst{31-21} = 0b10000000111; 4299let isFP = 1; 4300let Uses = [USR]; 4301} 4302def F2_conv_ud2sf : HInst< 4303(outs IntRegs:$Rd32), 4304(ins DoubleRegs:$Rss32), 4305"$Rd32 = convert_ud2sf($Rss32)", 4306tc_3a867367, TypeS_2op>, Enc_90cd8b { 4307let Inst{13-5} = 0b000000001; 4308let Inst{31-21} = 0b10001000001; 4309let hasNewValue = 1; 4310let opNewValue = 0; 4311let isFP = 1; 4312let Uses = [USR]; 4313} 4314def F2_conv_uw2df : HInst< 4315(outs DoubleRegs:$Rdd32), 4316(ins IntRegs:$Rs32), 4317"$Rdd32 = convert_uw2df($Rs32)", 4318tc_3a867367, TypeS_2op>, Enc_3a3d62 { 4319let Inst{13-5} = 0b000000001; 4320let Inst{31-21} = 0b10000100100; 4321let isFP = 1; 4322let Uses = [USR]; 4323} 4324def F2_conv_uw2sf : HInst< 4325(outs IntRegs:$Rd32), 4326(ins IntRegs:$Rs32), 4327"$Rd32 = convert_uw2sf($Rs32)", 4328tc_3a867367, TypeS_2op>, Enc_5e2823 { 4329let Inst{13-5} = 0b000000000; 4330let Inst{31-21} = 0b10001011001; 4331let hasNewValue = 1; 4332let opNewValue = 0; 4333let isFP = 1; 4334let Uses = [USR]; 4335} 4336def F2_conv_w2df : HInst< 4337(outs DoubleRegs:$Rdd32), 4338(ins IntRegs:$Rs32), 4339"$Rdd32 = convert_w2df($Rs32)", 4340tc_3a867367, TypeS_2op>, Enc_3a3d62 { 4341let Inst{13-5} = 0b000000010; 4342let Inst{31-21} = 0b10000100100; 4343let isFP = 1; 4344let Uses = [USR]; 4345} 4346def F2_conv_w2sf : HInst< 4347(outs IntRegs:$Rd32), 4348(ins IntRegs:$Rs32), 4349"$Rd32 = convert_w2sf($Rs32)", 4350tc_3a867367, TypeS_2op>, Enc_5e2823 { 4351let Inst{13-5} = 0b000000000; 4352let Inst{31-21} = 0b10001011010; 4353let hasNewValue = 1; 4354let opNewValue = 0; 4355let isFP = 1; 4356let Uses = [USR]; 4357} 4358def F2_dfadd : HInst< 4359(outs DoubleRegs:$Rdd32), 4360(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 4361"$Rdd32 = dfadd($Rss32,$Rtt32)", 4362tc_2f7c551d, TypeM>, Enc_a56825, Requires<[HasV66]> { 4363let Inst{7-5} = 0b011; 4364let Inst{13-13} = 0b0; 4365let Inst{31-21} = 0b11101000000; 4366let isFP = 1; 4367let Uses = [USR]; 4368} 4369def F2_dfclass : HInst< 4370(outs PredRegs:$Pd4), 4371(ins DoubleRegs:$Rss32, u5_0Imm:$Ii), 4372"$Pd4 = dfclass($Rss32,#$Ii)", 4373tc_643b4717, TypeALU64>, Enc_1f19b5 { 4374let Inst{4-2} = 0b100; 4375let Inst{13-10} = 0b0000; 4376let Inst{31-21} = 0b11011100100; 4377let isFP = 1; 4378let Uses = [USR]; 4379} 4380def F2_dfcmpeq : HInst< 4381(outs PredRegs:$Pd4), 4382(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 4383"$Pd4 = dfcmp.eq($Rss32,$Rtt32)", 4384tc_85d5d03f, TypeALU64>, Enc_fcf7a7 { 4385let Inst{7-2} = 0b000000; 4386let Inst{13-13} = 0b0; 4387let Inst{31-21} = 0b11010010111; 4388let isFP = 1; 4389let Uses = [USR]; 4390let isCompare = 1; 4391} 4392def F2_dfcmpge : HInst< 4393(outs PredRegs:$Pd4), 4394(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 4395"$Pd4 = dfcmp.ge($Rss32,$Rtt32)", 4396tc_85d5d03f, TypeALU64>, Enc_fcf7a7 { 4397let Inst{7-2} = 0b010000; 4398let Inst{13-13} = 0b0; 4399let Inst{31-21} = 0b11010010111; 4400let isFP = 1; 4401let Uses = [USR]; 4402let isCompare = 1; 4403} 4404def F2_dfcmpgt : HInst< 4405(outs PredRegs:$Pd4), 4406(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 4407"$Pd4 = dfcmp.gt($Rss32,$Rtt32)", 4408tc_85d5d03f, TypeALU64>, Enc_fcf7a7 { 4409let Inst{7-2} = 0b001000; 4410let Inst{13-13} = 0b0; 4411let Inst{31-21} = 0b11010010111; 4412let isFP = 1; 4413let Uses = [USR]; 4414let isCompare = 1; 4415} 4416def F2_dfcmpuo : HInst< 4417(outs PredRegs:$Pd4), 4418(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 4419"$Pd4 = dfcmp.uo($Rss32,$Rtt32)", 4420tc_85d5d03f, TypeALU64>, Enc_fcf7a7 { 4421let Inst{7-2} = 0b011000; 4422let Inst{13-13} = 0b0; 4423let Inst{31-21} = 0b11010010111; 4424let isFP = 1; 4425let Uses = [USR]; 4426let isCompare = 1; 4427} 4428def F2_dfimm_n : HInst< 4429(outs DoubleRegs:$Rdd32), 4430(ins u10_0Imm:$Ii), 4431"$Rdd32 = dfmake(#$Ii):neg", 4432tc_9e313203, TypeALU64>, Enc_e6c957 { 4433let Inst{20-16} = 0b00000; 4434let Inst{31-22} = 0b1101100101; 4435let prefersSlot3 = 1; 4436} 4437def F2_dfimm_p : HInst< 4438(outs DoubleRegs:$Rdd32), 4439(ins u10_0Imm:$Ii), 4440"$Rdd32 = dfmake(#$Ii):pos", 4441tc_9e313203, TypeALU64>, Enc_e6c957 { 4442let Inst{20-16} = 0b00000; 4443let Inst{31-22} = 0b1101100100; 4444let prefersSlot3 = 1; 4445} 4446def F2_dfsub : HInst< 4447(outs DoubleRegs:$Rdd32), 4448(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 4449"$Rdd32 = dfsub($Rss32,$Rtt32)", 4450tc_2f7c551d, TypeM>, Enc_a56825, Requires<[HasV66]> { 4451let Inst{7-5} = 0b011; 4452let Inst{13-13} = 0b0; 4453let Inst{31-21} = 0b11101000100; 4454let isFP = 1; 4455let Uses = [USR]; 4456} 4457def F2_sfadd : HInst< 4458(outs IntRegs:$Rd32), 4459(ins IntRegs:$Rs32, IntRegs:$Rt32), 4460"$Rd32 = sfadd($Rs32,$Rt32)", 4461tc_3b470976, TypeM>, Enc_5ab2be { 4462let Inst{7-5} = 0b000; 4463let Inst{13-13} = 0b0; 4464let Inst{31-21} = 0b11101011000; 4465let hasNewValue = 1; 4466let opNewValue = 0; 4467let isFP = 1; 4468let Uses = [USR]; 4469let isCommutable = 1; 4470} 4471def F2_sfclass : HInst< 4472(outs PredRegs:$Pd4), 4473(ins IntRegs:$Rs32, u5_0Imm:$Ii), 4474"$Pd4 = sfclass($Rs32,#$Ii)", 4475tc_643b4717, TypeS_2op>, Enc_83ee64 { 4476let Inst{7-2} = 0b000000; 4477let Inst{13-13} = 0b0; 4478let Inst{31-21} = 0b10000101111; 4479let isFP = 1; 4480let Uses = [USR]; 4481} 4482def F2_sfcmpeq : HInst< 4483(outs PredRegs:$Pd4), 4484(ins IntRegs:$Rs32, IntRegs:$Rt32), 4485"$Pd4 = sfcmp.eq($Rs32,$Rt32)", 4486tc_85d5d03f, TypeS_3op>, Enc_c2b48e { 4487let Inst{7-2} = 0b011000; 4488let Inst{13-13} = 0b0; 4489let Inst{31-21} = 0b11000111111; 4490let isFP = 1; 4491let Uses = [USR]; 4492let isCompare = 1; 4493} 4494def F2_sfcmpge : HInst< 4495(outs PredRegs:$Pd4), 4496(ins IntRegs:$Rs32, IntRegs:$Rt32), 4497"$Pd4 = sfcmp.ge($Rs32,$Rt32)", 4498tc_85d5d03f, TypeS_3op>, Enc_c2b48e { 4499let Inst{7-2} = 0b000000; 4500let Inst{13-13} = 0b0; 4501let Inst{31-21} = 0b11000111111; 4502let isFP = 1; 4503let Uses = [USR]; 4504let isCompare = 1; 4505} 4506def F2_sfcmpgt : HInst< 4507(outs PredRegs:$Pd4), 4508(ins IntRegs:$Rs32, IntRegs:$Rt32), 4509"$Pd4 = sfcmp.gt($Rs32,$Rt32)", 4510tc_85d5d03f, TypeS_3op>, Enc_c2b48e { 4511let Inst{7-2} = 0b100000; 4512let Inst{13-13} = 0b0; 4513let Inst{31-21} = 0b11000111111; 4514let isFP = 1; 4515let Uses = [USR]; 4516let isCompare = 1; 4517} 4518def F2_sfcmpuo : HInst< 4519(outs PredRegs:$Pd4), 4520(ins IntRegs:$Rs32, IntRegs:$Rt32), 4521"$Pd4 = sfcmp.uo($Rs32,$Rt32)", 4522tc_85d5d03f, TypeS_3op>, Enc_c2b48e { 4523let Inst{7-2} = 0b001000; 4524let Inst{13-13} = 0b0; 4525let Inst{31-21} = 0b11000111111; 4526let isFP = 1; 4527let Uses = [USR]; 4528let isCompare = 1; 4529} 4530def F2_sffixupd : HInst< 4531(outs IntRegs:$Rd32), 4532(ins IntRegs:$Rs32, IntRegs:$Rt32), 4533"$Rd32 = sffixupd($Rs32,$Rt32)", 4534tc_3b470976, TypeM>, Enc_5ab2be { 4535let Inst{7-5} = 0b001; 4536let Inst{13-13} = 0b0; 4537let Inst{31-21} = 0b11101011110; 4538let hasNewValue = 1; 4539let opNewValue = 0; 4540let isFP = 1; 4541} 4542def F2_sffixupn : HInst< 4543(outs IntRegs:$Rd32), 4544(ins IntRegs:$Rs32, IntRegs:$Rt32), 4545"$Rd32 = sffixupn($Rs32,$Rt32)", 4546tc_3b470976, TypeM>, Enc_5ab2be { 4547let Inst{7-5} = 0b000; 4548let Inst{13-13} = 0b0; 4549let Inst{31-21} = 0b11101011110; 4550let hasNewValue = 1; 4551let opNewValue = 0; 4552let isFP = 1; 4553} 4554def F2_sffixupr : HInst< 4555(outs IntRegs:$Rd32), 4556(ins IntRegs:$Rs32), 4557"$Rd32 = sffixupr($Rs32)", 4558tc_3a867367, TypeS_2op>, Enc_5e2823 { 4559let Inst{13-5} = 0b000000000; 4560let Inst{31-21} = 0b10001011101; 4561let hasNewValue = 1; 4562let opNewValue = 0; 4563let isFP = 1; 4564} 4565def F2_sffma : HInst< 4566(outs IntRegs:$Rx32), 4567(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), 4568"$Rx32 += sfmpy($Rs32,$Rt32)", 4569tc_a58fd5cc, TypeM>, Enc_2ae154 { 4570let Inst{7-5} = 0b100; 4571let Inst{13-13} = 0b0; 4572let Inst{31-21} = 0b11101111000; 4573let hasNewValue = 1; 4574let opNewValue = 0; 4575let isFP = 1; 4576let Uses = [USR]; 4577let Constraints = "$Rx32 = $Rx32in"; 4578} 4579def F2_sffma_lib : HInst< 4580(outs IntRegs:$Rx32), 4581(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), 4582"$Rx32 += sfmpy($Rs32,$Rt32):lib", 4583tc_a58fd5cc, TypeM>, Enc_2ae154 { 4584let Inst{7-5} = 0b110; 4585let Inst{13-13} = 0b0; 4586let Inst{31-21} = 0b11101111000; 4587let hasNewValue = 1; 4588let opNewValue = 0; 4589let isFP = 1; 4590let Uses = [USR]; 4591let Constraints = "$Rx32 = $Rx32in"; 4592} 4593def F2_sffma_sc : HInst< 4594(outs IntRegs:$Rx32), 4595(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32, PredRegs:$Pu4), 4596"$Rx32 += sfmpy($Rs32,$Rt32,$Pu4):scale", 4597tc_4560740b, TypeM>, Enc_437f33 { 4598let Inst{7-7} = 0b1; 4599let Inst{13-13} = 0b0; 4600let Inst{31-21} = 0b11101111011; 4601let hasNewValue = 1; 4602let opNewValue = 0; 4603let isFP = 1; 4604let Uses = [USR]; 4605let Constraints = "$Rx32 = $Rx32in"; 4606} 4607def F2_sffms : HInst< 4608(outs IntRegs:$Rx32), 4609(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), 4610"$Rx32 -= sfmpy($Rs32,$Rt32)", 4611tc_a58fd5cc, TypeM>, Enc_2ae154 { 4612let Inst{7-5} = 0b101; 4613let Inst{13-13} = 0b0; 4614let Inst{31-21} = 0b11101111000; 4615let hasNewValue = 1; 4616let opNewValue = 0; 4617let isFP = 1; 4618let Uses = [USR]; 4619let Constraints = "$Rx32 = $Rx32in"; 4620} 4621def F2_sffms_lib : HInst< 4622(outs IntRegs:$Rx32), 4623(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), 4624"$Rx32 -= sfmpy($Rs32,$Rt32):lib", 4625tc_a58fd5cc, TypeM>, Enc_2ae154 { 4626let Inst{7-5} = 0b111; 4627let Inst{13-13} = 0b0; 4628let Inst{31-21} = 0b11101111000; 4629let hasNewValue = 1; 4630let opNewValue = 0; 4631let isFP = 1; 4632let Uses = [USR]; 4633let Constraints = "$Rx32 = $Rx32in"; 4634} 4635def F2_sfimm_n : HInst< 4636(outs IntRegs:$Rd32), 4637(ins u10_0Imm:$Ii), 4638"$Rd32 = sfmake(#$Ii):neg", 4639tc_9e313203, TypeALU64>, Enc_6c9440 { 4640let Inst{20-16} = 0b00000; 4641let Inst{31-22} = 0b1101011001; 4642let hasNewValue = 1; 4643let opNewValue = 0; 4644let prefersSlot3 = 1; 4645} 4646def F2_sfimm_p : HInst< 4647(outs IntRegs:$Rd32), 4648(ins u10_0Imm:$Ii), 4649"$Rd32 = sfmake(#$Ii):pos", 4650tc_9e313203, TypeALU64>, Enc_6c9440 { 4651let Inst{20-16} = 0b00000; 4652let Inst{31-22} = 0b1101011000; 4653let hasNewValue = 1; 4654let opNewValue = 0; 4655let prefersSlot3 = 1; 4656} 4657def F2_sfinvsqrta : HInst< 4658(outs IntRegs:$Rd32, PredRegs:$Pe4), 4659(ins IntRegs:$Rs32), 4660"$Rd32,$Pe4 = sfinvsqrta($Rs32)", 4661tc_b8bffe55, TypeS_2op>, Enc_890909 { 4662let Inst{13-7} = 0b0000000; 4663let Inst{31-21} = 0b10001011111; 4664let hasNewValue = 1; 4665let opNewValue = 0; 4666let isFP = 1; 4667let isPredicateLate = 1; 4668} 4669def F2_sfmax : HInst< 4670(outs IntRegs:$Rd32), 4671(ins IntRegs:$Rs32, IntRegs:$Rt32), 4672"$Rd32 = sfmax($Rs32,$Rt32)", 4673tc_88b4f13d, TypeM>, Enc_5ab2be { 4674let Inst{7-5} = 0b000; 4675let Inst{13-13} = 0b0; 4676let Inst{31-21} = 0b11101011100; 4677let hasNewValue = 1; 4678let opNewValue = 0; 4679let isFP = 1; 4680let prefersSlot3 = 1; 4681let Uses = [USR]; 4682} 4683def F2_sfmin : HInst< 4684(outs IntRegs:$Rd32), 4685(ins IntRegs:$Rs32, IntRegs:$Rt32), 4686"$Rd32 = sfmin($Rs32,$Rt32)", 4687tc_88b4f13d, TypeM>, Enc_5ab2be { 4688let Inst{7-5} = 0b001; 4689let Inst{13-13} = 0b0; 4690let Inst{31-21} = 0b11101011100; 4691let hasNewValue = 1; 4692let opNewValue = 0; 4693let isFP = 1; 4694let prefersSlot3 = 1; 4695let Uses = [USR]; 4696} 4697def F2_sfmpy : HInst< 4698(outs IntRegs:$Rd32), 4699(ins IntRegs:$Rs32, IntRegs:$Rt32), 4700"$Rd32 = sfmpy($Rs32,$Rt32)", 4701tc_3b470976, TypeM>, Enc_5ab2be { 4702let Inst{7-5} = 0b000; 4703let Inst{13-13} = 0b0; 4704let Inst{31-21} = 0b11101011010; 4705let hasNewValue = 1; 4706let opNewValue = 0; 4707let isFP = 1; 4708let Uses = [USR]; 4709let isCommutable = 1; 4710} 4711def F2_sfrecipa : HInst< 4712(outs IntRegs:$Rd32, PredRegs:$Pe4), 4713(ins IntRegs:$Rs32, IntRegs:$Rt32), 4714"$Rd32,$Pe4 = sfrecipa($Rs32,$Rt32)", 4715tc_2ff964b4, TypeM>, Enc_a94f3b { 4716let Inst{7-7} = 0b1; 4717let Inst{13-13} = 0b0; 4718let Inst{31-21} = 0b11101011111; 4719let hasNewValue = 1; 4720let opNewValue = 0; 4721let isFP = 1; 4722let isPredicateLate = 1; 4723} 4724def F2_sfsub : HInst< 4725(outs IntRegs:$Rd32), 4726(ins IntRegs:$Rs32, IntRegs:$Rt32), 4727"$Rd32 = sfsub($Rs32,$Rt32)", 4728tc_3b470976, TypeM>, Enc_5ab2be { 4729let Inst{7-5} = 0b001; 4730let Inst{13-13} = 0b0; 4731let Inst{31-21} = 0b11101011000; 4732let hasNewValue = 1; 4733let opNewValue = 0; 4734let isFP = 1; 4735let Uses = [USR]; 4736} 4737def G4_tfrgcpp : HInst< 4738(outs DoubleRegs:$Rdd32), 4739(ins GuestRegs64:$Gss32), 4740"$Rdd32 = $Gss32", 4741tc_0d8f5752, TypeCR>, Enc_0aa344 { 4742let Inst{13-5} = 0b000000000; 4743let Inst{31-21} = 0b01101000001; 4744} 4745def G4_tfrgcrr : HInst< 4746(outs IntRegs:$Rd32), 4747(ins GuestRegs:$Gs32), 4748"$Rd32 = $Gs32", 4749tc_0d8f5752, TypeCR>, Enc_44271f { 4750let Inst{13-5} = 0b000000000; 4751let Inst{31-21} = 0b01101010001; 4752let hasNewValue = 1; 4753let opNewValue = 0; 4754} 4755def G4_tfrgpcp : HInst< 4756(outs GuestRegs64:$Gdd32), 4757(ins DoubleRegs:$Rss32), 4758"$Gdd32 = $Rss32", 4759tc_bcf98408, TypeCR>, Enc_ed5027 { 4760let Inst{13-5} = 0b000000000; 4761let Inst{31-21} = 0b01100011000; 4762let hasNewValue = 1; 4763let opNewValue = 0; 4764} 4765def G4_tfrgrcr : HInst< 4766(outs GuestRegs:$Gd32), 4767(ins IntRegs:$Rs32), 4768"$Gd32 = $Rs32", 4769tc_bcf98408, TypeCR>, Enc_621fba { 4770let Inst{13-5} = 0b000000000; 4771let Inst{31-21} = 0b01100010000; 4772let hasNewValue = 1; 4773let opNewValue = 0; 4774} 4775def J2_call : HInst< 4776(outs), 4777(ins a30_2Imm:$Ii), 4778"call $Ii", 4779tc_4ae7b58b, TypeJ>, Enc_81ac1d, PredRel { 4780let Inst{0-0} = 0b0; 4781let Inst{31-25} = 0b0101101; 4782let isCall = 1; 4783let prefersSlot3 = 1; 4784let cofRelax2 = 1; 4785let cofMax1 = 1; 4786let Uses = [R29]; 4787let Defs = [PC, R31]; 4788let BaseOpcode = "J2_call"; 4789let isPredicable = 1; 4790let hasSideEffects = 1; 4791let isExtendable = 1; 4792let opExtendable = 0; 4793let isExtentSigned = 1; 4794let opExtentBits = 24; 4795let opExtentAlign = 2; 4796} 4797def J2_callf : HInst< 4798(outs), 4799(ins PredRegs:$Pu4, a30_2Imm:$Ii), 4800"if (!$Pu4) call $Ii", 4801tc_1d81e60e, TypeJ>, Enc_daea09, PredRel { 4802let Inst{0-0} = 0b0; 4803let Inst{12-10} = 0b000; 4804let Inst{21-21} = 0b1; 4805let Inst{31-24} = 0b01011101; 4806let isPredicated = 1; 4807let isPredicatedFalse = 1; 4808let isCall = 1; 4809let prefersSlot3 = 1; 4810let cofRelax1 = 1; 4811let cofRelax2 = 1; 4812let cofMax1 = 1; 4813let Uses = [R29]; 4814let Defs = [PC, R31]; 4815let BaseOpcode = "J2_call"; 4816let hasSideEffects = 1; 4817let isTaken = Inst{12}; 4818let isExtendable = 1; 4819let opExtendable = 1; 4820let isExtentSigned = 1; 4821let opExtentBits = 17; 4822let opExtentAlign = 2; 4823} 4824def J2_callr : HInst< 4825(outs), 4826(ins IntRegs:$Rs32), 4827"callr $Rs32", 4828tc_3bd75825, TypeJ>, Enc_ecbcc8 { 4829let Inst{13-0} = 0b00000000000000; 4830let Inst{31-21} = 0b01010000101; 4831let isCall = 1; 4832let prefersSlot3 = 1; 4833let cofMax1 = 1; 4834let Uses = [R29]; 4835let Defs = [PC, R31]; 4836let hasSideEffects = 1; 4837} 4838def J2_callrf : HInst< 4839(outs), 4840(ins PredRegs:$Pu4, IntRegs:$Rs32), 4841"if (!$Pu4) callr $Rs32", 4842tc_1ad90acd, TypeJ>, Enc_88d4d9 { 4843let Inst{7-0} = 0b00000000; 4844let Inst{13-10} = 0b0000; 4845let Inst{31-21} = 0b01010001001; 4846let isPredicated = 1; 4847let isPredicatedFalse = 1; 4848let isCall = 1; 4849let prefersSlot3 = 1; 4850let cofMax1 = 1; 4851let Uses = [R29]; 4852let Defs = [PC, R31]; 4853let hasSideEffects = 1; 4854let isTaken = Inst{12}; 4855} 4856def J2_callrt : HInst< 4857(outs), 4858(ins PredRegs:$Pu4, IntRegs:$Rs32), 4859"if ($Pu4) callr $Rs32", 4860tc_1ad90acd, TypeJ>, Enc_88d4d9 { 4861let Inst{7-0} = 0b00000000; 4862let Inst{13-10} = 0b0000; 4863let Inst{31-21} = 0b01010001000; 4864let isPredicated = 1; 4865let isCall = 1; 4866let prefersSlot3 = 1; 4867let cofMax1 = 1; 4868let Uses = [R29]; 4869let Defs = [PC, R31]; 4870let hasSideEffects = 1; 4871let isTaken = Inst{12}; 4872} 4873def J2_callt : HInst< 4874(outs), 4875(ins PredRegs:$Pu4, a30_2Imm:$Ii), 4876"if ($Pu4) call $Ii", 4877tc_1d81e60e, TypeJ>, Enc_daea09, PredRel { 4878let Inst{0-0} = 0b0; 4879let Inst{12-10} = 0b000; 4880let Inst{21-21} = 0b0; 4881let Inst{31-24} = 0b01011101; 4882let isPredicated = 1; 4883let isCall = 1; 4884let prefersSlot3 = 1; 4885let cofRelax1 = 1; 4886let cofRelax2 = 1; 4887let cofMax1 = 1; 4888let Uses = [R29]; 4889let Defs = [PC, R31]; 4890let BaseOpcode = "J2_call"; 4891let hasSideEffects = 1; 4892let isTaken = Inst{12}; 4893let isExtendable = 1; 4894let opExtendable = 1; 4895let isExtentSigned = 1; 4896let opExtentBits = 17; 4897let opExtentAlign = 2; 4898} 4899def J2_endloop0 : HInst< 4900(outs), 4901(ins), 4902"endloop0", 4903tc_1b6f7cec, TypeJ> { 4904let Uses = [LC0, SA0]; 4905let Defs = [LC0, P3, PC, USR]; 4906let isBranch = 1; 4907let isTerminator = 1; 4908let isPseudo = 1; 4909} 4910def J2_endloop01 : HInst< 4911(outs), 4912(ins), 4913"endloop01", 4914tc_1b6f7cec, TypeJ> { 4915let Uses = [LC0, LC1, SA0, SA1]; 4916let Defs = [LC0, LC1, P3, PC, USR]; 4917let isPseudo = 1; 4918} 4919def J2_endloop1 : HInst< 4920(outs), 4921(ins), 4922"endloop1", 4923tc_1b6f7cec, TypeJ> { 4924let Uses = [LC1, SA1]; 4925let Defs = [LC1, PC]; 4926let isBranch = 1; 4927let isTerminator = 1; 4928let isPseudo = 1; 4929} 4930def J2_jump : HInst< 4931(outs), 4932(ins b30_2Imm:$Ii), 4933"jump $Ii", 4934tc_ae53734a, TypeJ>, Enc_81ac1d, PredNewRel { 4935let Inst{0-0} = 0b0; 4936let Inst{31-25} = 0b0101100; 4937let isTerminator = 1; 4938let isBranch = 1; 4939let cofRelax2 = 1; 4940let cofMax1 = 1; 4941let Defs = [PC]; 4942let InputType = "imm"; 4943let BaseOpcode = "J2_jump"; 4944let isBarrier = 1; 4945let isPredicable = 1; 4946let isExtendable = 1; 4947let opExtendable = 0; 4948let isExtentSigned = 1; 4949let opExtentBits = 24; 4950let opExtentAlign = 2; 4951} 4952def J2_jumpf : HInst< 4953(outs), 4954(ins PredRegs:$Pu4, b30_2Imm:$Ii), 4955"if (!$Pu4) jump:nt $Ii", 4956tc_db2bce9c, TypeJ>, Enc_daea09, PredNewRel { 4957let Inst{0-0} = 0b0; 4958let Inst{12-10} = 0b000; 4959let Inst{21-21} = 0b1; 4960let Inst{31-24} = 0b01011100; 4961let isPredicated = 1; 4962let isPredicatedFalse = 1; 4963let isTerminator = 1; 4964let isBranch = 1; 4965let cofRelax1 = 1; 4966let cofRelax2 = 1; 4967let cofMax1 = 1; 4968let Defs = [PC]; 4969let InputType = "imm"; 4970let BaseOpcode = "J2_jump"; 4971let isTaken = Inst{12}; 4972let isExtendable = 1; 4973let opExtendable = 1; 4974let isExtentSigned = 1; 4975let opExtentBits = 17; 4976let opExtentAlign = 2; 4977} 4978def J2_jumpf_nopred_map : HInst< 4979(outs), 4980(ins PredRegs:$Pu4, b15_2Imm:$Ii), 4981"if (!$Pu4) jump $Ii", 4982tc_db2bce9c, TypeMAPPING>, Requires<[HasV60]> { 4983let isPseudo = 1; 4984let isCodeGenOnly = 1; 4985} 4986def J2_jumpfnew : HInst< 4987(outs), 4988(ins PredRegs:$Pu4, b30_2Imm:$Ii), 4989"if (!$Pu4.new) jump:nt $Ii", 4990tc_20cdee80, TypeJ>, Enc_daea09, PredNewRel { 4991let Inst{0-0} = 0b0; 4992let Inst{12-10} = 0b010; 4993let Inst{21-21} = 0b1; 4994let Inst{31-24} = 0b01011100; 4995let isPredicated = 1; 4996let isPredicatedFalse = 1; 4997let isTerminator = 1; 4998let isBranch = 1; 4999let isPredicatedNew = 1; 5000let cofRelax1 = 1; 5001let cofRelax2 = 1; 5002let cofMax1 = 1; 5003let Defs = [PC]; 5004let InputType = "imm"; 5005let BaseOpcode = "J2_jump"; 5006let isTaken = Inst{12}; 5007let isExtendable = 1; 5008let opExtendable = 1; 5009let isExtentSigned = 1; 5010let opExtentBits = 17; 5011let opExtentAlign = 2; 5012} 5013def J2_jumpfnewpt : HInst< 5014(outs), 5015(ins PredRegs:$Pu4, b30_2Imm:$Ii), 5016"if (!$Pu4.new) jump:t $Ii", 5017tc_20cdee80, TypeJ>, Enc_daea09, PredNewRel { 5018let Inst{0-0} = 0b0; 5019let Inst{12-10} = 0b110; 5020let Inst{21-21} = 0b1; 5021let Inst{31-24} = 0b01011100; 5022let isPredicated = 1; 5023let isPredicatedFalse = 1; 5024let isTerminator = 1; 5025let isBranch = 1; 5026let isPredicatedNew = 1; 5027let cofRelax1 = 1; 5028let cofRelax2 = 1; 5029let cofMax1 = 1; 5030let Defs = [PC]; 5031let InputType = "imm"; 5032let BaseOpcode = "J2_jump"; 5033let isTaken = Inst{12}; 5034let isExtendable = 1; 5035let opExtendable = 1; 5036let isExtentSigned = 1; 5037let opExtentBits = 17; 5038let opExtentAlign = 2; 5039} 5040def J2_jumpfpt : HInst< 5041(outs), 5042(ins PredRegs:$Pu4, b30_2Imm:$Ii), 5043"if (!$Pu4) jump:t $Ii", 5044tc_cd374165, TypeJ>, Enc_daea09, Requires<[HasV60]>, PredNewRel { 5045let Inst{0-0} = 0b0; 5046let Inst{12-10} = 0b100; 5047let Inst{21-21} = 0b1; 5048let Inst{31-24} = 0b01011100; 5049let isPredicated = 1; 5050let isPredicatedFalse = 1; 5051let isTerminator = 1; 5052let isBranch = 1; 5053let cofRelax1 = 1; 5054let cofRelax2 = 1; 5055let cofMax1 = 1; 5056let Defs = [PC]; 5057let InputType = "imm"; 5058let BaseOpcode = "J2_jump"; 5059let isTaken = Inst{12}; 5060let isExtendable = 1; 5061let opExtendable = 1; 5062let isExtentSigned = 1; 5063let opExtentBits = 17; 5064let opExtentAlign = 2; 5065} 5066def J2_jumpr : HInst< 5067(outs), 5068(ins IntRegs:$Rs32), 5069"jumpr $Rs32", 5070tc_d5b7b0c1, TypeJ>, Enc_ecbcc8, PredNewRel { 5071let Inst{13-0} = 0b00000000000000; 5072let Inst{31-21} = 0b01010010100; 5073let isTerminator = 1; 5074let isIndirectBranch = 1; 5075let isBranch = 1; 5076let cofMax1 = 1; 5077let Defs = [PC]; 5078let InputType = "reg"; 5079let BaseOpcode = "J2_jumpr"; 5080let isBarrier = 1; 5081let isPredicable = 1; 5082} 5083def J2_jumprf : HInst< 5084(outs), 5085(ins PredRegs:$Pu4, IntRegs:$Rs32), 5086"if (!$Pu4) jumpr:nt $Rs32", 5087tc_85c9c08f, TypeJ>, Enc_88d4d9, PredNewRel { 5088let Inst{7-0} = 0b00000000; 5089let Inst{13-10} = 0b0000; 5090let Inst{31-21} = 0b01010011011; 5091let isPredicated = 1; 5092let isPredicatedFalse = 1; 5093let isTerminator = 1; 5094let isIndirectBranch = 1; 5095let isBranch = 1; 5096let cofMax1 = 1; 5097let Defs = [PC]; 5098let InputType = "reg"; 5099let BaseOpcode = "J2_jumpr"; 5100let isTaken = Inst{12}; 5101} 5102def J2_jumprf_nopred_map : HInst< 5103(outs), 5104(ins PredRegs:$Pu4, IntRegs:$Rs32), 5105"if (!$Pu4) jumpr $Rs32", 5106tc_85c9c08f, TypeMAPPING>, Requires<[HasV60]> { 5107let isPseudo = 1; 5108let isCodeGenOnly = 1; 5109} 5110def J2_jumprfnew : HInst< 5111(outs), 5112(ins PredRegs:$Pu4, IntRegs:$Rs32), 5113"if (!$Pu4.new) jumpr:nt $Rs32", 5114tc_b51dc29a, TypeJ>, Enc_88d4d9, PredNewRel { 5115let Inst{7-0} = 0b00000000; 5116let Inst{13-10} = 0b0010; 5117let Inst{31-21} = 0b01010011011; 5118let isPredicated = 1; 5119let isPredicatedFalse = 1; 5120let isTerminator = 1; 5121let isIndirectBranch = 1; 5122let isBranch = 1; 5123let isPredicatedNew = 1; 5124let cofMax1 = 1; 5125let Defs = [PC]; 5126let InputType = "reg"; 5127let BaseOpcode = "J2_jumpr"; 5128let isTaken = Inst{12}; 5129} 5130def J2_jumprfnewpt : HInst< 5131(outs), 5132(ins PredRegs:$Pu4, IntRegs:$Rs32), 5133"if (!$Pu4.new) jumpr:t $Rs32", 5134tc_b51dc29a, TypeJ>, Enc_88d4d9, PredNewRel { 5135let Inst{7-0} = 0b00000000; 5136let Inst{13-10} = 0b0110; 5137let Inst{31-21} = 0b01010011011; 5138let isPredicated = 1; 5139let isPredicatedFalse = 1; 5140let isTerminator = 1; 5141let isIndirectBranch = 1; 5142let isBranch = 1; 5143let isPredicatedNew = 1; 5144let cofMax1 = 1; 5145let Defs = [PC]; 5146let InputType = "reg"; 5147let BaseOpcode = "J2_jumpr"; 5148let isTaken = Inst{12}; 5149} 5150def J2_jumprfpt : HInst< 5151(outs), 5152(ins PredRegs:$Pu4, IntRegs:$Rs32), 5153"if (!$Pu4) jumpr:t $Rs32", 5154tc_e78647bd, TypeJ>, Enc_88d4d9, Requires<[HasV60]>, PredNewRel { 5155let Inst{7-0} = 0b00000000; 5156let Inst{13-10} = 0b0100; 5157let Inst{31-21} = 0b01010011011; 5158let isPredicated = 1; 5159let isPredicatedFalse = 1; 5160let isTerminator = 1; 5161let isIndirectBranch = 1; 5162let isBranch = 1; 5163let cofMax1 = 1; 5164let Defs = [PC]; 5165let InputType = "reg"; 5166let BaseOpcode = "J2_jumpr"; 5167let isTaken = Inst{12}; 5168} 5169def J2_jumprgtez : HInst< 5170(outs), 5171(ins IntRegs:$Rs32, b13_2Imm:$Ii), 5172"if ($Rs32>=#0) jump:nt $Ii", 5173tc_d9d43ecb, TypeCR>, Enc_0fa531 { 5174let Inst{0-0} = 0b0; 5175let Inst{12-12} = 0b0; 5176let Inst{31-22} = 0b0110000101; 5177let isPredicated = 1; 5178let isTerminator = 1; 5179let isBranch = 1; 5180let isPredicatedNew = 1; 5181let cofRelax1 = 1; 5182let cofRelax2 = 1; 5183let cofMax1 = 1; 5184let Defs = [PC]; 5185let isTaken = Inst{12}; 5186} 5187def J2_jumprgtezpt : HInst< 5188(outs), 5189(ins IntRegs:$Rs32, b13_2Imm:$Ii), 5190"if ($Rs32>=#0) jump:t $Ii", 5191tc_d9d43ecb, TypeCR>, Enc_0fa531 { 5192let Inst{0-0} = 0b0; 5193let Inst{12-12} = 0b1; 5194let Inst{31-22} = 0b0110000101; 5195let isPredicated = 1; 5196let isTerminator = 1; 5197let isBranch = 1; 5198let isPredicatedNew = 1; 5199let cofRelax1 = 1; 5200let cofRelax2 = 1; 5201let cofMax1 = 1; 5202let Defs = [PC]; 5203let isTaken = Inst{12}; 5204} 5205def J2_jumprltez : HInst< 5206(outs), 5207(ins IntRegs:$Rs32, b13_2Imm:$Ii), 5208"if ($Rs32<=#0) jump:nt $Ii", 5209tc_d9d43ecb, TypeCR>, Enc_0fa531 { 5210let Inst{0-0} = 0b0; 5211let Inst{12-12} = 0b0; 5212let Inst{31-22} = 0b0110000111; 5213let isPredicated = 1; 5214let isTerminator = 1; 5215let isBranch = 1; 5216let isPredicatedNew = 1; 5217let cofRelax1 = 1; 5218let cofRelax2 = 1; 5219let cofMax1 = 1; 5220let Defs = [PC]; 5221let isTaken = Inst{12}; 5222} 5223def J2_jumprltezpt : HInst< 5224(outs), 5225(ins IntRegs:$Rs32, b13_2Imm:$Ii), 5226"if ($Rs32<=#0) jump:t $Ii", 5227tc_d9d43ecb, TypeCR>, Enc_0fa531 { 5228let Inst{0-0} = 0b0; 5229let Inst{12-12} = 0b1; 5230let Inst{31-22} = 0b0110000111; 5231let isPredicated = 1; 5232let isTerminator = 1; 5233let isBranch = 1; 5234let isPredicatedNew = 1; 5235let cofRelax1 = 1; 5236let cofRelax2 = 1; 5237let cofMax1 = 1; 5238let Defs = [PC]; 5239let isTaken = Inst{12}; 5240} 5241def J2_jumprnz : HInst< 5242(outs), 5243(ins IntRegs:$Rs32, b13_2Imm:$Ii), 5244"if ($Rs32==#0) jump:nt $Ii", 5245tc_d9d43ecb, TypeCR>, Enc_0fa531 { 5246let Inst{0-0} = 0b0; 5247let Inst{12-12} = 0b0; 5248let Inst{31-22} = 0b0110000110; 5249let isPredicated = 1; 5250let isTerminator = 1; 5251let isBranch = 1; 5252let isPredicatedNew = 1; 5253let cofRelax1 = 1; 5254let cofRelax2 = 1; 5255let cofMax1 = 1; 5256let Defs = [PC]; 5257let isTaken = Inst{12}; 5258} 5259def J2_jumprnzpt : HInst< 5260(outs), 5261(ins IntRegs:$Rs32, b13_2Imm:$Ii), 5262"if ($Rs32==#0) jump:t $Ii", 5263tc_d9d43ecb, TypeCR>, Enc_0fa531 { 5264let Inst{0-0} = 0b0; 5265let Inst{12-12} = 0b1; 5266let Inst{31-22} = 0b0110000110; 5267let isPredicated = 1; 5268let isTerminator = 1; 5269let isBranch = 1; 5270let isPredicatedNew = 1; 5271let cofRelax1 = 1; 5272let cofRelax2 = 1; 5273let cofMax1 = 1; 5274let Defs = [PC]; 5275let isTaken = Inst{12}; 5276} 5277def J2_jumprt : HInst< 5278(outs), 5279(ins PredRegs:$Pu4, IntRegs:$Rs32), 5280"if ($Pu4) jumpr:nt $Rs32", 5281tc_85c9c08f, TypeJ>, Enc_88d4d9, PredNewRel { 5282let Inst{7-0} = 0b00000000; 5283let Inst{13-10} = 0b0000; 5284let Inst{31-21} = 0b01010011010; 5285let isPredicated = 1; 5286let isTerminator = 1; 5287let isIndirectBranch = 1; 5288let isBranch = 1; 5289let cofMax1 = 1; 5290let Defs = [PC]; 5291let InputType = "reg"; 5292let BaseOpcode = "J2_jumpr"; 5293let isTaken = Inst{12}; 5294} 5295def J2_jumprt_nopred_map : HInst< 5296(outs), 5297(ins PredRegs:$Pu4, IntRegs:$Rs32), 5298"if ($Pu4) jumpr $Rs32", 5299tc_85c9c08f, TypeMAPPING>, Requires<[HasV60]> { 5300let isPseudo = 1; 5301let isCodeGenOnly = 1; 5302} 5303def J2_jumprtnew : HInst< 5304(outs), 5305(ins PredRegs:$Pu4, IntRegs:$Rs32), 5306"if ($Pu4.new) jumpr:nt $Rs32", 5307tc_b51dc29a, TypeJ>, Enc_88d4d9, PredNewRel { 5308let Inst{7-0} = 0b00000000; 5309let Inst{13-10} = 0b0010; 5310let Inst{31-21} = 0b01010011010; 5311let isPredicated = 1; 5312let isTerminator = 1; 5313let isIndirectBranch = 1; 5314let isBranch = 1; 5315let isPredicatedNew = 1; 5316let cofMax1 = 1; 5317let Defs = [PC]; 5318let InputType = "reg"; 5319let BaseOpcode = "J2_jumpr"; 5320let isTaken = Inst{12}; 5321} 5322def J2_jumprtnewpt : HInst< 5323(outs), 5324(ins PredRegs:$Pu4, IntRegs:$Rs32), 5325"if ($Pu4.new) jumpr:t $Rs32", 5326tc_b51dc29a, TypeJ>, Enc_88d4d9, PredNewRel { 5327let Inst{7-0} = 0b00000000; 5328let Inst{13-10} = 0b0110; 5329let Inst{31-21} = 0b01010011010; 5330let isPredicated = 1; 5331let isTerminator = 1; 5332let isIndirectBranch = 1; 5333let isBranch = 1; 5334let isPredicatedNew = 1; 5335let cofMax1 = 1; 5336let Defs = [PC]; 5337let InputType = "reg"; 5338let BaseOpcode = "J2_jumpr"; 5339let isTaken = Inst{12}; 5340} 5341def J2_jumprtpt : HInst< 5342(outs), 5343(ins PredRegs:$Pu4, IntRegs:$Rs32), 5344"if ($Pu4) jumpr:t $Rs32", 5345tc_e78647bd, TypeJ>, Enc_88d4d9, Requires<[HasV60]>, PredNewRel { 5346let Inst{7-0} = 0b00000000; 5347let Inst{13-10} = 0b0100; 5348let Inst{31-21} = 0b01010011010; 5349let isPredicated = 1; 5350let isTerminator = 1; 5351let isIndirectBranch = 1; 5352let isBranch = 1; 5353let cofMax1 = 1; 5354let Defs = [PC]; 5355let InputType = "reg"; 5356let BaseOpcode = "J2_jumpr"; 5357let isTaken = Inst{12}; 5358} 5359def J2_jumprz : HInst< 5360(outs), 5361(ins IntRegs:$Rs32, b13_2Imm:$Ii), 5362"if ($Rs32!=#0) jump:nt $Ii", 5363tc_d9d43ecb, TypeCR>, Enc_0fa531 { 5364let Inst{0-0} = 0b0; 5365let Inst{12-12} = 0b0; 5366let Inst{31-22} = 0b0110000100; 5367let isPredicated = 1; 5368let isTerminator = 1; 5369let isBranch = 1; 5370let isPredicatedNew = 1; 5371let cofRelax1 = 1; 5372let cofRelax2 = 1; 5373let cofMax1 = 1; 5374let Defs = [PC]; 5375let isTaken = Inst{12}; 5376} 5377def J2_jumprzpt : HInst< 5378(outs), 5379(ins IntRegs:$Rs32, b13_2Imm:$Ii), 5380"if ($Rs32!=#0) jump:t $Ii", 5381tc_d9d43ecb, TypeCR>, Enc_0fa531 { 5382let Inst{0-0} = 0b0; 5383let Inst{12-12} = 0b1; 5384let Inst{31-22} = 0b0110000100; 5385let isPredicated = 1; 5386let isTerminator = 1; 5387let isBranch = 1; 5388let isPredicatedNew = 1; 5389let cofRelax1 = 1; 5390let cofRelax2 = 1; 5391let cofMax1 = 1; 5392let Defs = [PC]; 5393let isTaken = Inst{12}; 5394} 5395def J2_jumpt : HInst< 5396(outs), 5397(ins PredRegs:$Pu4, b30_2Imm:$Ii), 5398"if ($Pu4) jump:nt $Ii", 5399tc_db2bce9c, TypeJ>, Enc_daea09, PredNewRel { 5400let Inst{0-0} = 0b0; 5401let Inst{12-10} = 0b000; 5402let Inst{21-21} = 0b0; 5403let Inst{31-24} = 0b01011100; 5404let isPredicated = 1; 5405let isTerminator = 1; 5406let isBranch = 1; 5407let cofRelax1 = 1; 5408let cofRelax2 = 1; 5409let cofMax1 = 1; 5410let Defs = [PC]; 5411let InputType = "imm"; 5412let BaseOpcode = "J2_jump"; 5413let isTaken = Inst{12}; 5414let isExtendable = 1; 5415let opExtendable = 1; 5416let isExtentSigned = 1; 5417let opExtentBits = 17; 5418let opExtentAlign = 2; 5419} 5420def J2_jumpt_nopred_map : HInst< 5421(outs), 5422(ins PredRegs:$Pu4, b15_2Imm:$Ii), 5423"if ($Pu4) jump $Ii", 5424tc_db2bce9c, TypeMAPPING>, Requires<[HasV60]> { 5425let isPseudo = 1; 5426let isCodeGenOnly = 1; 5427} 5428def J2_jumptnew : HInst< 5429(outs), 5430(ins PredRegs:$Pu4, b30_2Imm:$Ii), 5431"if ($Pu4.new) jump:nt $Ii", 5432tc_20cdee80, TypeJ>, Enc_daea09, PredNewRel { 5433let Inst{0-0} = 0b0; 5434let Inst{12-10} = 0b010; 5435let Inst{21-21} = 0b0; 5436let Inst{31-24} = 0b01011100; 5437let isPredicated = 1; 5438let isTerminator = 1; 5439let isBranch = 1; 5440let isPredicatedNew = 1; 5441let cofRelax1 = 1; 5442let cofRelax2 = 1; 5443let cofMax1 = 1; 5444let Defs = [PC]; 5445let InputType = "imm"; 5446let BaseOpcode = "J2_jump"; 5447let isTaken = Inst{12}; 5448let isExtendable = 1; 5449let opExtendable = 1; 5450let isExtentSigned = 1; 5451let opExtentBits = 17; 5452let opExtentAlign = 2; 5453} 5454def J2_jumptnewpt : HInst< 5455(outs), 5456(ins PredRegs:$Pu4, b30_2Imm:$Ii), 5457"if ($Pu4.new) jump:t $Ii", 5458tc_20cdee80, TypeJ>, Enc_daea09, PredNewRel { 5459let Inst{0-0} = 0b0; 5460let Inst{12-10} = 0b110; 5461let Inst{21-21} = 0b0; 5462let Inst{31-24} = 0b01011100; 5463let isPredicated = 1; 5464let isTerminator = 1; 5465let isBranch = 1; 5466let isPredicatedNew = 1; 5467let cofRelax1 = 1; 5468let cofRelax2 = 1; 5469let cofMax1 = 1; 5470let Defs = [PC]; 5471let InputType = "imm"; 5472let BaseOpcode = "J2_jump"; 5473let isTaken = Inst{12}; 5474let isExtendable = 1; 5475let opExtendable = 1; 5476let isExtentSigned = 1; 5477let opExtentBits = 17; 5478let opExtentAlign = 2; 5479} 5480def J2_jumptpt : HInst< 5481(outs), 5482(ins PredRegs:$Pu4, b30_2Imm:$Ii), 5483"if ($Pu4) jump:t $Ii", 5484tc_cd374165, TypeJ>, Enc_daea09, Requires<[HasV60]>, PredNewRel { 5485let Inst{0-0} = 0b0; 5486let Inst{12-10} = 0b100; 5487let Inst{21-21} = 0b0; 5488let Inst{31-24} = 0b01011100; 5489let isPredicated = 1; 5490let isTerminator = 1; 5491let isBranch = 1; 5492let cofRelax1 = 1; 5493let cofRelax2 = 1; 5494let cofMax1 = 1; 5495let Defs = [PC]; 5496let InputType = "imm"; 5497let BaseOpcode = "J2_jump"; 5498let isTaken = Inst{12}; 5499let isExtendable = 1; 5500let opExtendable = 1; 5501let isExtentSigned = 1; 5502let opExtentBits = 17; 5503let opExtentAlign = 2; 5504} 5505def J2_loop0i : HInst< 5506(outs), 5507(ins b30_2Imm:$Ii, u10_0Imm:$II), 5508"loop0($Ii,#$II)", 5509tc_a9d88b22, TypeCR>, Enc_4dc228 { 5510let Inst{2-2} = 0b0; 5511let Inst{13-13} = 0b0; 5512let Inst{31-21} = 0b01101001000; 5513let cofRelax1 = 1; 5514let cofRelax2 = 1; 5515let Defs = [LC0, SA0, USR]; 5516let isExtendable = 1; 5517let opExtendable = 0; 5518let isExtentSigned = 1; 5519let opExtentBits = 9; 5520let opExtentAlign = 2; 5521} 5522def J2_loop0r : HInst< 5523(outs), 5524(ins b30_2Imm:$Ii, IntRegs:$Rs32), 5525"loop0($Ii,$Rs32)", 5526tc_df3319ed, TypeCR>, Enc_864a5a { 5527let Inst{2-0} = 0b000; 5528let Inst{7-5} = 0b000; 5529let Inst{13-13} = 0b0; 5530let Inst{31-21} = 0b01100000000; 5531let cofRelax1 = 1; 5532let cofRelax2 = 1; 5533let Defs = [LC0, SA0, USR]; 5534let isExtendable = 1; 5535let opExtendable = 0; 5536let isExtentSigned = 1; 5537let opExtentBits = 9; 5538let opExtentAlign = 2; 5539} 5540def J2_loop1i : HInst< 5541(outs), 5542(ins b30_2Imm:$Ii, u10_0Imm:$II), 5543"loop1($Ii,#$II)", 5544tc_a9d88b22, TypeCR>, Enc_4dc228 { 5545let Inst{2-2} = 0b0; 5546let Inst{13-13} = 0b0; 5547let Inst{31-21} = 0b01101001001; 5548let cofRelax1 = 1; 5549let cofRelax2 = 1; 5550let Defs = [LC1, SA1]; 5551let isExtendable = 1; 5552let opExtendable = 0; 5553let isExtentSigned = 1; 5554let opExtentBits = 9; 5555let opExtentAlign = 2; 5556} 5557def J2_loop1r : HInst< 5558(outs), 5559(ins b30_2Imm:$Ii, IntRegs:$Rs32), 5560"loop1($Ii,$Rs32)", 5561tc_df3319ed, TypeCR>, Enc_864a5a { 5562let Inst{2-0} = 0b000; 5563let Inst{7-5} = 0b000; 5564let Inst{13-13} = 0b0; 5565let Inst{31-21} = 0b01100000001; 5566let cofRelax1 = 1; 5567let cofRelax2 = 1; 5568let Defs = [LC1, SA1]; 5569let isExtendable = 1; 5570let opExtendable = 0; 5571let isExtentSigned = 1; 5572let opExtentBits = 9; 5573let opExtentAlign = 2; 5574} 5575def J2_pause : HInst< 5576(outs), 5577(ins u8_0Imm:$Ii), 5578"pause(#$Ii)", 5579tc_8d9d0154, TypeJ>, Enc_a51a9a { 5580let Inst{1-0} = 0b00; 5581let Inst{7-5} = 0b000; 5582let Inst{13-13} = 0b0; 5583let Inst{31-16} = 0b0101010001000000; 5584let isSolo = 1; 5585} 5586def J2_ploop1si : HInst< 5587(outs), 5588(ins b30_2Imm:$Ii, u10_0Imm:$II), 5589"p3 = sp1loop0($Ii,#$II)", 5590tc_1c4528a2, TypeCR>, Enc_4dc228 { 5591let Inst{2-2} = 0b0; 5592let Inst{13-13} = 0b0; 5593let Inst{31-21} = 0b01101001101; 5594let isPredicateLate = 1; 5595let cofRelax1 = 1; 5596let cofRelax2 = 1; 5597let Defs = [LC0, P3, SA0, USR]; 5598let isExtendable = 1; 5599let opExtendable = 0; 5600let isExtentSigned = 1; 5601let opExtentBits = 9; 5602let opExtentAlign = 2; 5603} 5604def J2_ploop1sr : HInst< 5605(outs), 5606(ins b30_2Imm:$Ii, IntRegs:$Rs32), 5607"p3 = sp1loop0($Ii,$Rs32)", 5608tc_32779c6f, TypeCR>, Enc_864a5a { 5609let Inst{2-0} = 0b000; 5610let Inst{7-5} = 0b000; 5611let Inst{13-13} = 0b0; 5612let Inst{31-21} = 0b01100000101; 5613let isPredicateLate = 1; 5614let cofRelax1 = 1; 5615let cofRelax2 = 1; 5616let Defs = [LC0, P3, SA0, USR]; 5617let isExtendable = 1; 5618let opExtendable = 0; 5619let isExtentSigned = 1; 5620let opExtentBits = 9; 5621let opExtentAlign = 2; 5622} 5623def J2_ploop2si : HInst< 5624(outs), 5625(ins b30_2Imm:$Ii, u10_0Imm:$II), 5626"p3 = sp2loop0($Ii,#$II)", 5627tc_1c4528a2, TypeCR>, Enc_4dc228 { 5628let Inst{2-2} = 0b0; 5629let Inst{13-13} = 0b0; 5630let Inst{31-21} = 0b01101001110; 5631let isPredicateLate = 1; 5632let cofRelax1 = 1; 5633let cofRelax2 = 1; 5634let Defs = [LC0, P3, SA0, USR]; 5635let isExtendable = 1; 5636let opExtendable = 0; 5637let isExtentSigned = 1; 5638let opExtentBits = 9; 5639let opExtentAlign = 2; 5640} 5641def J2_ploop2sr : HInst< 5642(outs), 5643(ins b30_2Imm:$Ii, IntRegs:$Rs32), 5644"p3 = sp2loop0($Ii,$Rs32)", 5645tc_32779c6f, TypeCR>, Enc_864a5a { 5646let Inst{2-0} = 0b000; 5647let Inst{7-5} = 0b000; 5648let Inst{13-13} = 0b0; 5649let Inst{31-21} = 0b01100000110; 5650let isPredicateLate = 1; 5651let cofRelax1 = 1; 5652let cofRelax2 = 1; 5653let Defs = [LC0, P3, SA0, USR]; 5654let isExtendable = 1; 5655let opExtendable = 0; 5656let isExtentSigned = 1; 5657let opExtentBits = 9; 5658let opExtentAlign = 2; 5659} 5660def J2_ploop3si : HInst< 5661(outs), 5662(ins b30_2Imm:$Ii, u10_0Imm:$II), 5663"p3 = sp3loop0($Ii,#$II)", 5664tc_1c4528a2, TypeCR>, Enc_4dc228 { 5665let Inst{2-2} = 0b0; 5666let Inst{13-13} = 0b0; 5667let Inst{31-21} = 0b01101001111; 5668let isPredicateLate = 1; 5669let cofRelax1 = 1; 5670let cofRelax2 = 1; 5671let Defs = [LC0, P3, SA0, USR]; 5672let isExtendable = 1; 5673let opExtendable = 0; 5674let isExtentSigned = 1; 5675let opExtentBits = 9; 5676let opExtentAlign = 2; 5677} 5678def J2_ploop3sr : HInst< 5679(outs), 5680(ins b30_2Imm:$Ii, IntRegs:$Rs32), 5681"p3 = sp3loop0($Ii,$Rs32)", 5682tc_32779c6f, TypeCR>, Enc_864a5a { 5683let Inst{2-0} = 0b000; 5684let Inst{7-5} = 0b000; 5685let Inst{13-13} = 0b0; 5686let Inst{31-21} = 0b01100000111; 5687let isPredicateLate = 1; 5688let cofRelax1 = 1; 5689let cofRelax2 = 1; 5690let Defs = [LC0, P3, SA0, USR]; 5691let isExtendable = 1; 5692let opExtendable = 0; 5693let isExtentSigned = 1; 5694let opExtentBits = 9; 5695let opExtentAlign = 2; 5696} 5697def J2_trap0 : HInst< 5698(outs), 5699(ins u8_0Imm:$Ii), 5700"trap0(#$Ii)", 5701tc_fc3999b4, TypeJ>, Enc_a51a9a { 5702let Inst{1-0} = 0b00; 5703let Inst{7-5} = 0b000; 5704let Inst{13-13} = 0b0; 5705let Inst{31-16} = 0b0101010000000000; 5706let isSolo = 1; 5707let hasSideEffects = 1; 5708} 5709def J2_trap1 : HInst< 5710(outs IntRegs:$Rx32), 5711(ins IntRegs:$Rx32in, u8_0Imm:$Ii), 5712"trap1($Rx32,#$Ii)", 5713tc_b9e09e03, TypeJ>, Enc_33f8ba { 5714let Inst{1-0} = 0b00; 5715let Inst{7-5} = 0b000; 5716let Inst{13-13} = 0b0; 5717let Inst{31-21} = 0b01010100100; 5718let hasNewValue = 1; 5719let opNewValue = 0; 5720let isSolo = 1; 5721let Uses = [GOSP]; 5722let Defs = [GOSP, PC]; 5723let hasSideEffects = 1; 5724let Constraints = "$Rx32 = $Rx32in"; 5725} 5726def J2_trap1_noregmap : HInst< 5727(outs), 5728(ins u8_0Imm:$Ii), 5729"trap1(#$Ii)", 5730tc_b9e09e03, TypeMAPPING> { 5731let hasSideEffects = 1; 5732let isPseudo = 1; 5733let isCodeGenOnly = 1; 5734} 5735def J4_cmpeq_f_jumpnv_nt : HInst< 5736(outs), 5737(ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii), 5738"if (!cmp.eq($Ns8.new,$Rt32)) jump:nt $Ii", 5739tc_9bfd761f, TypeNCJ>, Enc_c9a18e, PredRel { 5740let Inst{0-0} = 0b0; 5741let Inst{13-13} = 0b0; 5742let Inst{19-19} = 0b0; 5743let Inst{31-22} = 0b0010000001; 5744let isPredicated = 1; 5745let isPredicatedFalse = 1; 5746let isTerminator = 1; 5747let isBranch = 1; 5748let isNewValue = 1; 5749let cofMax1 = 1; 5750let isRestrictNoSlot1Store = 1; 5751let Defs = [PC]; 5752let BaseOpcode = "J4_cmpeqr"; 5753let isTaken = Inst{13}; 5754let isExtendable = 1; 5755let opExtendable = 2; 5756let isExtentSigned = 1; 5757let opExtentBits = 11; 5758let opExtentAlign = 2; 5759let opNewValue = 0; 5760} 5761def J4_cmpeq_f_jumpnv_t : HInst< 5762(outs), 5763(ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii), 5764"if (!cmp.eq($Ns8.new,$Rt32)) jump:t $Ii", 5765tc_9bfd761f, TypeNCJ>, Enc_c9a18e, PredRel { 5766let Inst{0-0} = 0b0; 5767let Inst{13-13} = 0b1; 5768let Inst{19-19} = 0b0; 5769let Inst{31-22} = 0b0010000001; 5770let isPredicated = 1; 5771let isPredicatedFalse = 1; 5772let isTerminator = 1; 5773let isBranch = 1; 5774let isNewValue = 1; 5775let cofMax1 = 1; 5776let isRestrictNoSlot1Store = 1; 5777let Defs = [PC]; 5778let BaseOpcode = "J4_cmpeqr"; 5779let isTaken = Inst{13}; 5780let isExtendable = 1; 5781let opExtendable = 2; 5782let isExtentSigned = 1; 5783let opExtentBits = 11; 5784let opExtentAlign = 2; 5785let opNewValue = 0; 5786} 5787def J4_cmpeq_fp0_jump_nt : HInst< 5788(outs), 5789(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), 5790"p0 = cmp.eq($Rs16,$Rt16); if (!p0.new) jump:nt $Ii", 5791tc_56336eb0, TypeCJ>, Enc_6a5972, PredRel { 5792let Inst{0-0} = 0b0; 5793let Inst{13-12} = 0b00; 5794let Inst{31-22} = 0b0001010001; 5795let isPredicated = 1; 5796let isPredicatedFalse = 1; 5797let isTerminator = 1; 5798let isBranch = 1; 5799let isPredicatedNew = 1; 5800let cofRelax1 = 1; 5801let cofRelax2 = 1; 5802let cofMax1 = 1; 5803let Uses = [P0]; 5804let Defs = [P0, PC]; 5805let BaseOpcode = "J4_cmpeqp0"; 5806let isTaken = Inst{13}; 5807let isExtendable = 1; 5808let opExtendable = 2; 5809let isExtentSigned = 1; 5810let opExtentBits = 11; 5811let opExtentAlign = 2; 5812} 5813def J4_cmpeq_fp0_jump_t : HInst< 5814(outs), 5815(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), 5816"p0 = cmp.eq($Rs16,$Rt16); if (!p0.new) jump:t $Ii", 5817tc_56336eb0, TypeCJ>, Enc_6a5972, PredRel { 5818let Inst{0-0} = 0b0; 5819let Inst{13-12} = 0b10; 5820let Inst{31-22} = 0b0001010001; 5821let isPredicated = 1; 5822let isPredicatedFalse = 1; 5823let isTerminator = 1; 5824let isBranch = 1; 5825let isPredicatedNew = 1; 5826let cofRelax1 = 1; 5827let cofRelax2 = 1; 5828let cofMax1 = 1; 5829let Uses = [P0]; 5830let Defs = [P0, PC]; 5831let BaseOpcode = "J4_cmpeqp0"; 5832let isTaken = Inst{13}; 5833let isExtendable = 1; 5834let opExtendable = 2; 5835let isExtentSigned = 1; 5836let opExtentBits = 11; 5837let opExtentAlign = 2; 5838} 5839def J4_cmpeq_fp1_jump_nt : HInst< 5840(outs), 5841(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), 5842"p1 = cmp.eq($Rs16,$Rt16); if (!p1.new) jump:nt $Ii", 5843tc_56336eb0, TypeCJ>, Enc_6a5972, PredRel { 5844let Inst{0-0} = 0b0; 5845let Inst{13-12} = 0b01; 5846let Inst{31-22} = 0b0001010001; 5847let isPredicated = 1; 5848let isPredicatedFalse = 1; 5849let isTerminator = 1; 5850let isBranch = 1; 5851let isPredicatedNew = 1; 5852let cofRelax1 = 1; 5853let cofRelax2 = 1; 5854let cofMax1 = 1; 5855let Uses = [P1]; 5856let Defs = [P1, PC]; 5857let BaseOpcode = "J4_cmpeqp1"; 5858let isTaken = Inst{13}; 5859let isExtendable = 1; 5860let opExtendable = 2; 5861let isExtentSigned = 1; 5862let opExtentBits = 11; 5863let opExtentAlign = 2; 5864} 5865def J4_cmpeq_fp1_jump_t : HInst< 5866(outs), 5867(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), 5868"p1 = cmp.eq($Rs16,$Rt16); if (!p1.new) jump:t $Ii", 5869tc_56336eb0, TypeCJ>, Enc_6a5972, PredRel { 5870let Inst{0-0} = 0b0; 5871let Inst{13-12} = 0b11; 5872let Inst{31-22} = 0b0001010001; 5873let isPredicated = 1; 5874let isPredicatedFalse = 1; 5875let isTerminator = 1; 5876let isBranch = 1; 5877let isPredicatedNew = 1; 5878let cofRelax1 = 1; 5879let cofRelax2 = 1; 5880let cofMax1 = 1; 5881let Uses = [P1]; 5882let Defs = [P1, PC]; 5883let BaseOpcode = "J4_cmpeqp1"; 5884let isTaken = Inst{13}; 5885let isExtendable = 1; 5886let opExtendable = 2; 5887let isExtentSigned = 1; 5888let opExtentBits = 11; 5889let opExtentAlign = 2; 5890} 5891def J4_cmpeq_t_jumpnv_nt : HInst< 5892(outs), 5893(ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii), 5894"if (cmp.eq($Ns8.new,$Rt32)) jump:nt $Ii", 5895tc_9bfd761f, TypeNCJ>, Enc_c9a18e, PredRel { 5896let Inst{0-0} = 0b0; 5897let Inst{13-13} = 0b0; 5898let Inst{19-19} = 0b0; 5899let Inst{31-22} = 0b0010000000; 5900let isPredicated = 1; 5901let isTerminator = 1; 5902let isBranch = 1; 5903let isNewValue = 1; 5904let cofMax1 = 1; 5905let isRestrictNoSlot1Store = 1; 5906let Defs = [PC]; 5907let BaseOpcode = "J4_cmpeqr"; 5908let isTaken = Inst{13}; 5909let isExtendable = 1; 5910let opExtendable = 2; 5911let isExtentSigned = 1; 5912let opExtentBits = 11; 5913let opExtentAlign = 2; 5914let opNewValue = 0; 5915} 5916def J4_cmpeq_t_jumpnv_t : HInst< 5917(outs), 5918(ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii), 5919"if (cmp.eq($Ns8.new,$Rt32)) jump:t $Ii", 5920tc_9bfd761f, TypeNCJ>, Enc_c9a18e, PredRel { 5921let Inst{0-0} = 0b0; 5922let Inst{13-13} = 0b1; 5923let Inst{19-19} = 0b0; 5924let Inst{31-22} = 0b0010000000; 5925let isPredicated = 1; 5926let isTerminator = 1; 5927let isBranch = 1; 5928let isNewValue = 1; 5929let cofMax1 = 1; 5930let isRestrictNoSlot1Store = 1; 5931let Defs = [PC]; 5932let BaseOpcode = "J4_cmpeqr"; 5933let isTaken = Inst{13}; 5934let isExtendable = 1; 5935let opExtendable = 2; 5936let isExtentSigned = 1; 5937let opExtentBits = 11; 5938let opExtentAlign = 2; 5939let opNewValue = 0; 5940} 5941def J4_cmpeq_tp0_jump_nt : HInst< 5942(outs), 5943(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), 5944"p0 = cmp.eq($Rs16,$Rt16); if (p0.new) jump:nt $Ii", 5945tc_56336eb0, TypeCJ>, Enc_6a5972, PredRel { 5946let Inst{0-0} = 0b0; 5947let Inst{13-12} = 0b00; 5948let Inst{31-22} = 0b0001010000; 5949let isPredicated = 1; 5950let isTerminator = 1; 5951let isBranch = 1; 5952let isPredicatedNew = 1; 5953let cofRelax1 = 1; 5954let cofRelax2 = 1; 5955let cofMax1 = 1; 5956let Uses = [P0]; 5957let Defs = [P0, PC]; 5958let BaseOpcode = "J4_cmpeqp0"; 5959let isTaken = Inst{13}; 5960let isExtendable = 1; 5961let opExtendable = 2; 5962let isExtentSigned = 1; 5963let opExtentBits = 11; 5964let opExtentAlign = 2; 5965} 5966def J4_cmpeq_tp0_jump_t : HInst< 5967(outs), 5968(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), 5969"p0 = cmp.eq($Rs16,$Rt16); if (p0.new) jump:t $Ii", 5970tc_56336eb0, TypeCJ>, Enc_6a5972, PredRel { 5971let Inst{0-0} = 0b0; 5972let Inst{13-12} = 0b10; 5973let Inst{31-22} = 0b0001010000; 5974let isPredicated = 1; 5975let isTerminator = 1; 5976let isBranch = 1; 5977let isPredicatedNew = 1; 5978let cofRelax1 = 1; 5979let cofRelax2 = 1; 5980let cofMax1 = 1; 5981let Uses = [P0]; 5982let Defs = [P0, PC]; 5983let BaseOpcode = "J4_cmpeqp0"; 5984let isTaken = Inst{13}; 5985let isExtendable = 1; 5986let opExtendable = 2; 5987let isExtentSigned = 1; 5988let opExtentBits = 11; 5989let opExtentAlign = 2; 5990} 5991def J4_cmpeq_tp1_jump_nt : HInst< 5992(outs), 5993(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), 5994"p1 = cmp.eq($Rs16,$Rt16); if (p1.new) jump:nt $Ii", 5995tc_56336eb0, TypeCJ>, Enc_6a5972, PredRel { 5996let Inst{0-0} = 0b0; 5997let Inst{13-12} = 0b01; 5998let Inst{31-22} = 0b0001010000; 5999let isPredicated = 1; 6000let isTerminator = 1; 6001let isBranch = 1; 6002let isPredicatedNew = 1; 6003let cofRelax1 = 1; 6004let cofRelax2 = 1; 6005let cofMax1 = 1; 6006let Uses = [P1]; 6007let Defs = [P1, PC]; 6008let BaseOpcode = "J4_cmpeqp1"; 6009let isTaken = Inst{13}; 6010let isExtendable = 1; 6011let opExtendable = 2; 6012let isExtentSigned = 1; 6013let opExtentBits = 11; 6014let opExtentAlign = 2; 6015} 6016def J4_cmpeq_tp1_jump_t : HInst< 6017(outs), 6018(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), 6019"p1 = cmp.eq($Rs16,$Rt16); if (p1.new) jump:t $Ii", 6020tc_56336eb0, TypeCJ>, Enc_6a5972, PredRel { 6021let Inst{0-0} = 0b0; 6022let Inst{13-12} = 0b11; 6023let Inst{31-22} = 0b0001010000; 6024let isPredicated = 1; 6025let isTerminator = 1; 6026let isBranch = 1; 6027let isPredicatedNew = 1; 6028let cofRelax1 = 1; 6029let cofRelax2 = 1; 6030let cofMax1 = 1; 6031let Uses = [P1]; 6032let Defs = [P1, PC]; 6033let BaseOpcode = "J4_cmpeqp1"; 6034let isTaken = Inst{13}; 6035let isExtendable = 1; 6036let opExtendable = 2; 6037let isExtentSigned = 1; 6038let opExtentBits = 11; 6039let opExtentAlign = 2; 6040} 6041def J4_cmpeqi_f_jumpnv_nt : HInst< 6042(outs), 6043(ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii), 6044"if (!cmp.eq($Ns8.new,#$II)) jump:nt $Ii", 6045tc_bd8382d1, TypeNCJ>, Enc_eafd18, PredRel { 6046let Inst{0-0} = 0b0; 6047let Inst{13-13} = 0b0; 6048let Inst{19-19} = 0b0; 6049let Inst{31-22} = 0b0010010001; 6050let isPredicated = 1; 6051let isPredicatedFalse = 1; 6052let isTerminator = 1; 6053let isBranch = 1; 6054let isNewValue = 1; 6055let cofMax1 = 1; 6056let isRestrictNoSlot1Store = 1; 6057let Defs = [PC]; 6058let BaseOpcode = "J4_cmpeqi"; 6059let isTaken = Inst{13}; 6060let isExtendable = 1; 6061let opExtendable = 2; 6062let isExtentSigned = 1; 6063let opExtentBits = 11; 6064let opExtentAlign = 2; 6065let opNewValue = 0; 6066} 6067def J4_cmpeqi_f_jumpnv_t : HInst< 6068(outs), 6069(ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii), 6070"if (!cmp.eq($Ns8.new,#$II)) jump:t $Ii", 6071tc_bd8382d1, TypeNCJ>, Enc_eafd18, PredRel { 6072let Inst{0-0} = 0b0; 6073let Inst{13-13} = 0b1; 6074let Inst{19-19} = 0b0; 6075let Inst{31-22} = 0b0010010001; 6076let isPredicated = 1; 6077let isPredicatedFalse = 1; 6078let isTerminator = 1; 6079let isBranch = 1; 6080let isNewValue = 1; 6081let cofMax1 = 1; 6082let isRestrictNoSlot1Store = 1; 6083let Defs = [PC]; 6084let BaseOpcode = "J4_cmpeqi"; 6085let isTaken = Inst{13}; 6086let isExtendable = 1; 6087let opExtendable = 2; 6088let isExtentSigned = 1; 6089let opExtentBits = 11; 6090let opExtentAlign = 2; 6091let opNewValue = 0; 6092} 6093def J4_cmpeqi_fp0_jump_nt : HInst< 6094(outs), 6095(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), 6096"p0 = cmp.eq($Rs16,#$II); if (!p0.new) jump:nt $Ii", 6097tc_3d495a39, TypeCJ>, Enc_14d27a, PredRel { 6098let Inst{0-0} = 0b0; 6099let Inst{13-13} = 0b0; 6100let Inst{31-22} = 0b0001000001; 6101let isPredicated = 1; 6102let isPredicatedFalse = 1; 6103let isTerminator = 1; 6104let isBranch = 1; 6105let isPredicatedNew = 1; 6106let cofRelax1 = 1; 6107let cofRelax2 = 1; 6108let cofMax1 = 1; 6109let Uses = [P0]; 6110let Defs = [P0, PC]; 6111let BaseOpcode = "J4_cmpeqip0"; 6112let isTaken = Inst{13}; 6113let isExtendable = 1; 6114let opExtendable = 2; 6115let isExtentSigned = 1; 6116let opExtentBits = 11; 6117let opExtentAlign = 2; 6118} 6119def J4_cmpeqi_fp0_jump_t : HInst< 6120(outs), 6121(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), 6122"p0 = cmp.eq($Rs16,#$II); if (!p0.new) jump:t $Ii", 6123tc_3d495a39, TypeCJ>, Enc_14d27a, PredRel { 6124let Inst{0-0} = 0b0; 6125let Inst{13-13} = 0b1; 6126let Inst{31-22} = 0b0001000001; 6127let isPredicated = 1; 6128let isPredicatedFalse = 1; 6129let isTerminator = 1; 6130let isBranch = 1; 6131let isPredicatedNew = 1; 6132let cofRelax1 = 1; 6133let cofRelax2 = 1; 6134let cofMax1 = 1; 6135let Uses = [P0]; 6136let Defs = [P0, PC]; 6137let BaseOpcode = "J4_cmpeqip0"; 6138let isTaken = Inst{13}; 6139let isExtendable = 1; 6140let opExtendable = 2; 6141let isExtentSigned = 1; 6142let opExtentBits = 11; 6143let opExtentAlign = 2; 6144} 6145def J4_cmpeqi_fp1_jump_nt : HInst< 6146(outs), 6147(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), 6148"p1 = cmp.eq($Rs16,#$II); if (!p1.new) jump:nt $Ii", 6149tc_3d495a39, TypeCJ>, Enc_14d27a, PredRel { 6150let Inst{0-0} = 0b0; 6151let Inst{13-13} = 0b0; 6152let Inst{31-22} = 0b0001001001; 6153let isPredicated = 1; 6154let isPredicatedFalse = 1; 6155let isTerminator = 1; 6156let isBranch = 1; 6157let isPredicatedNew = 1; 6158let cofRelax1 = 1; 6159let cofRelax2 = 1; 6160let cofMax1 = 1; 6161let Uses = [P1]; 6162let Defs = [P1, PC]; 6163let BaseOpcode = "J4_cmpeqip1"; 6164let isTaken = Inst{13}; 6165let isExtendable = 1; 6166let opExtendable = 2; 6167let isExtentSigned = 1; 6168let opExtentBits = 11; 6169let opExtentAlign = 2; 6170} 6171def J4_cmpeqi_fp1_jump_t : HInst< 6172(outs), 6173(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), 6174"p1 = cmp.eq($Rs16,#$II); if (!p1.new) jump:t $Ii", 6175tc_3d495a39, TypeCJ>, Enc_14d27a, PredRel { 6176let Inst{0-0} = 0b0; 6177let Inst{13-13} = 0b1; 6178let Inst{31-22} = 0b0001001001; 6179let isPredicated = 1; 6180let isPredicatedFalse = 1; 6181let isTerminator = 1; 6182let isBranch = 1; 6183let isPredicatedNew = 1; 6184let cofRelax1 = 1; 6185let cofRelax2 = 1; 6186let cofMax1 = 1; 6187let Uses = [P1]; 6188let Defs = [P1, PC]; 6189let BaseOpcode = "J4_cmpeqip1"; 6190let isTaken = Inst{13}; 6191let isExtendable = 1; 6192let opExtendable = 2; 6193let isExtentSigned = 1; 6194let opExtentBits = 11; 6195let opExtentAlign = 2; 6196} 6197def J4_cmpeqi_t_jumpnv_nt : HInst< 6198(outs), 6199(ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii), 6200"if (cmp.eq($Ns8.new,#$II)) jump:nt $Ii", 6201tc_bd8382d1, TypeNCJ>, Enc_eafd18, PredRel { 6202let Inst{0-0} = 0b0; 6203let Inst{13-13} = 0b0; 6204let Inst{19-19} = 0b0; 6205let Inst{31-22} = 0b0010010000; 6206let isPredicated = 1; 6207let isTerminator = 1; 6208let isBranch = 1; 6209let isNewValue = 1; 6210let cofMax1 = 1; 6211let isRestrictNoSlot1Store = 1; 6212let Defs = [PC]; 6213let BaseOpcode = "J4_cmpeqi"; 6214let isTaken = Inst{13}; 6215let isExtendable = 1; 6216let opExtendable = 2; 6217let isExtentSigned = 1; 6218let opExtentBits = 11; 6219let opExtentAlign = 2; 6220let opNewValue = 0; 6221} 6222def J4_cmpeqi_t_jumpnv_t : HInst< 6223(outs), 6224(ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii), 6225"if (cmp.eq($Ns8.new,#$II)) jump:t $Ii", 6226tc_bd8382d1, TypeNCJ>, Enc_eafd18, PredRel { 6227let Inst{0-0} = 0b0; 6228let Inst{13-13} = 0b1; 6229let Inst{19-19} = 0b0; 6230let Inst{31-22} = 0b0010010000; 6231let isPredicated = 1; 6232let isTerminator = 1; 6233let isBranch = 1; 6234let isNewValue = 1; 6235let cofMax1 = 1; 6236let isRestrictNoSlot1Store = 1; 6237let Defs = [PC]; 6238let BaseOpcode = "J4_cmpeqi"; 6239let isTaken = Inst{13}; 6240let isExtendable = 1; 6241let opExtendable = 2; 6242let isExtentSigned = 1; 6243let opExtentBits = 11; 6244let opExtentAlign = 2; 6245let opNewValue = 0; 6246} 6247def J4_cmpeqi_tp0_jump_nt : HInst< 6248(outs), 6249(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), 6250"p0 = cmp.eq($Rs16,#$II); if (p0.new) jump:nt $Ii", 6251tc_3d495a39, TypeCJ>, Enc_14d27a, PredRel { 6252let Inst{0-0} = 0b0; 6253let Inst{13-13} = 0b0; 6254let Inst{31-22} = 0b0001000000; 6255let isPredicated = 1; 6256let isTerminator = 1; 6257let isBranch = 1; 6258let isPredicatedNew = 1; 6259let cofRelax1 = 1; 6260let cofRelax2 = 1; 6261let cofMax1 = 1; 6262let Uses = [P0]; 6263let Defs = [P0, PC]; 6264let BaseOpcode = "J4_cmpeqip0"; 6265let isTaken = Inst{13}; 6266let isExtendable = 1; 6267let opExtendable = 2; 6268let isExtentSigned = 1; 6269let opExtentBits = 11; 6270let opExtentAlign = 2; 6271} 6272def J4_cmpeqi_tp0_jump_t : HInst< 6273(outs), 6274(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), 6275"p0 = cmp.eq($Rs16,#$II); if (p0.new) jump:t $Ii", 6276tc_3d495a39, TypeCJ>, Enc_14d27a, PredRel { 6277let Inst{0-0} = 0b0; 6278let Inst{13-13} = 0b1; 6279let Inst{31-22} = 0b0001000000; 6280let isPredicated = 1; 6281let isTerminator = 1; 6282let isBranch = 1; 6283let isPredicatedNew = 1; 6284let cofRelax1 = 1; 6285let cofRelax2 = 1; 6286let cofMax1 = 1; 6287let Uses = [P0]; 6288let Defs = [P0, PC]; 6289let BaseOpcode = "J4_cmpeqip0"; 6290let isTaken = Inst{13}; 6291let isExtendable = 1; 6292let opExtendable = 2; 6293let isExtentSigned = 1; 6294let opExtentBits = 11; 6295let opExtentAlign = 2; 6296} 6297def J4_cmpeqi_tp1_jump_nt : HInst< 6298(outs), 6299(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), 6300"p1 = cmp.eq($Rs16,#$II); if (p1.new) jump:nt $Ii", 6301tc_3d495a39, TypeCJ>, Enc_14d27a, PredRel { 6302let Inst{0-0} = 0b0; 6303let Inst{13-13} = 0b0; 6304let Inst{31-22} = 0b0001001000; 6305let isPredicated = 1; 6306let isTerminator = 1; 6307let isBranch = 1; 6308let isPredicatedNew = 1; 6309let cofRelax1 = 1; 6310let cofRelax2 = 1; 6311let cofMax1 = 1; 6312let Uses = [P1]; 6313let Defs = [P1, PC]; 6314let BaseOpcode = "J4_cmpeqip1"; 6315let isTaken = Inst{13}; 6316let isExtendable = 1; 6317let opExtendable = 2; 6318let isExtentSigned = 1; 6319let opExtentBits = 11; 6320let opExtentAlign = 2; 6321} 6322def J4_cmpeqi_tp1_jump_t : HInst< 6323(outs), 6324(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), 6325"p1 = cmp.eq($Rs16,#$II); if (p1.new) jump:t $Ii", 6326tc_3d495a39, TypeCJ>, Enc_14d27a, PredRel { 6327let Inst{0-0} = 0b0; 6328let Inst{13-13} = 0b1; 6329let Inst{31-22} = 0b0001001000; 6330let isPredicated = 1; 6331let isTerminator = 1; 6332let isBranch = 1; 6333let isPredicatedNew = 1; 6334let cofRelax1 = 1; 6335let cofRelax2 = 1; 6336let cofMax1 = 1; 6337let Uses = [P1]; 6338let Defs = [P1, PC]; 6339let BaseOpcode = "J4_cmpeqip1"; 6340let isTaken = Inst{13}; 6341let isExtendable = 1; 6342let opExtendable = 2; 6343let isExtentSigned = 1; 6344let opExtentBits = 11; 6345let opExtentAlign = 2; 6346} 6347def J4_cmpeqn1_f_jumpnv_nt : HInst< 6348(outs), 6349(ins IntRegs:$Ns8, n1Const:$n1, b30_2Imm:$Ii), 6350"if (!cmp.eq($Ns8.new,#$n1)) jump:nt $Ii", 6351tc_bd8382d1, TypeNCJ>, Enc_e90a15, PredRel { 6352let Inst{0-0} = 0b0; 6353let Inst{13-8} = 0b000000; 6354let Inst{19-19} = 0b0; 6355let Inst{31-22} = 0b0010011001; 6356let isPredicated = 1; 6357let isPredicatedFalse = 1; 6358let isTerminator = 1; 6359let isBranch = 1; 6360let isNewValue = 1; 6361let cofMax1 = 1; 6362let isRestrictNoSlot1Store = 1; 6363let Defs = [PC]; 6364let BaseOpcode = "J4_cmpeqn1r"; 6365let isTaken = Inst{13}; 6366let isExtendable = 1; 6367let opExtendable = 2; 6368let isExtentSigned = 1; 6369let opExtentBits = 11; 6370let opExtentAlign = 2; 6371let opNewValue = 0; 6372} 6373def J4_cmpeqn1_f_jumpnv_t : HInst< 6374(outs), 6375(ins IntRegs:$Ns8, n1Const:$n1, b30_2Imm:$Ii), 6376"if (!cmp.eq($Ns8.new,#$n1)) jump:t $Ii", 6377tc_bd8382d1, TypeNCJ>, Enc_5a18b3, PredRel { 6378let Inst{0-0} = 0b0; 6379let Inst{13-8} = 0b100000; 6380let Inst{19-19} = 0b0; 6381let Inst{31-22} = 0b0010011001; 6382let isPredicated = 1; 6383let isPredicatedFalse = 1; 6384let isTerminator = 1; 6385let isBranch = 1; 6386let isNewValue = 1; 6387let cofMax1 = 1; 6388let isRestrictNoSlot1Store = 1; 6389let Defs = [PC]; 6390let BaseOpcode = "J4_cmpeqn1r"; 6391let isTaken = Inst{13}; 6392let isExtendable = 1; 6393let opExtendable = 2; 6394let isExtentSigned = 1; 6395let opExtentBits = 11; 6396let opExtentAlign = 2; 6397let opNewValue = 0; 6398} 6399def J4_cmpeqn1_fp0_jump_nt : HInst< 6400(outs), 6401(ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii), 6402"p0 = cmp.eq($Rs16,#$n1); if (!p0.new) jump:nt $Ii", 6403tc_3d495a39, TypeCJ>, Enc_1de724, PredRel { 6404let Inst{0-0} = 0b0; 6405let Inst{13-8} = 0b000000; 6406let Inst{31-22} = 0b0001000111; 6407let isPredicated = 1; 6408let isPredicatedFalse = 1; 6409let isTerminator = 1; 6410let isBranch = 1; 6411let isPredicatedNew = 1; 6412let cofRelax1 = 1; 6413let cofRelax2 = 1; 6414let cofMax1 = 1; 6415let Uses = [P0]; 6416let Defs = [P0, PC]; 6417let BaseOpcode = "J4_cmpeqn1p0"; 6418let isTaken = Inst{13}; 6419let isExtendable = 1; 6420let opExtendable = 2; 6421let isExtentSigned = 1; 6422let opExtentBits = 11; 6423let opExtentAlign = 2; 6424} 6425def J4_cmpeqn1_fp0_jump_t : HInst< 6426(outs), 6427(ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii), 6428"p0 = cmp.eq($Rs16,#$n1); if (!p0.new) jump:t $Ii", 6429tc_3d495a39, TypeCJ>, Enc_14640c, PredRel { 6430let Inst{0-0} = 0b0; 6431let Inst{13-8} = 0b100000; 6432let Inst{31-22} = 0b0001000111; 6433let isPredicated = 1; 6434let isPredicatedFalse = 1; 6435let isTerminator = 1; 6436let isBranch = 1; 6437let isPredicatedNew = 1; 6438let cofRelax1 = 1; 6439let cofRelax2 = 1; 6440let cofMax1 = 1; 6441let Uses = [P0]; 6442let Defs = [P0, PC]; 6443let BaseOpcode = "J4_cmpeqn1p0"; 6444let isTaken = Inst{13}; 6445let isExtendable = 1; 6446let opExtendable = 2; 6447let isExtentSigned = 1; 6448let opExtentBits = 11; 6449let opExtentAlign = 2; 6450} 6451def J4_cmpeqn1_fp1_jump_nt : HInst< 6452(outs), 6453(ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii), 6454"p1 = cmp.eq($Rs16,#$n1); if (!p1.new) jump:nt $Ii", 6455tc_3d495a39, TypeCJ>, Enc_668704, PredRel { 6456let Inst{0-0} = 0b0; 6457let Inst{13-8} = 0b000000; 6458let Inst{31-22} = 0b0001001111; 6459let isPredicated = 1; 6460let isPredicatedFalse = 1; 6461let isTerminator = 1; 6462let isBranch = 1; 6463let isPredicatedNew = 1; 6464let cofRelax1 = 1; 6465let cofRelax2 = 1; 6466let cofMax1 = 1; 6467let Uses = [P1]; 6468let Defs = [P1, PC]; 6469let BaseOpcode = "J4_cmpeqn1p1"; 6470let isTaken = Inst{13}; 6471let isExtendable = 1; 6472let opExtendable = 2; 6473let isExtentSigned = 1; 6474let opExtentBits = 11; 6475let opExtentAlign = 2; 6476} 6477def J4_cmpeqn1_fp1_jump_t : HInst< 6478(outs), 6479(ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii), 6480"p1 = cmp.eq($Rs16,#$n1); if (!p1.new) jump:t $Ii", 6481tc_3d495a39, TypeCJ>, Enc_800e04, PredRel { 6482let Inst{0-0} = 0b0; 6483let Inst{13-8} = 0b100000; 6484let Inst{31-22} = 0b0001001111; 6485let isPredicated = 1; 6486let isPredicatedFalse = 1; 6487let isTerminator = 1; 6488let isBranch = 1; 6489let isPredicatedNew = 1; 6490let cofRelax1 = 1; 6491let cofRelax2 = 1; 6492let cofMax1 = 1; 6493let Uses = [P1]; 6494let Defs = [P1, PC]; 6495let BaseOpcode = "J4_cmpeqn1p1"; 6496let isTaken = Inst{13}; 6497let isExtendable = 1; 6498let opExtendable = 2; 6499let isExtentSigned = 1; 6500let opExtentBits = 11; 6501let opExtentAlign = 2; 6502} 6503def J4_cmpeqn1_t_jumpnv_nt : HInst< 6504(outs), 6505(ins IntRegs:$Ns8, n1Const:$n1, b30_2Imm:$Ii), 6506"if (cmp.eq($Ns8.new,#$n1)) jump:nt $Ii", 6507tc_bd8382d1, TypeNCJ>, Enc_4aca3a, PredRel { 6508let Inst{0-0} = 0b0; 6509let Inst{13-8} = 0b000000; 6510let Inst{19-19} = 0b0; 6511let Inst{31-22} = 0b0010011000; 6512let isPredicated = 1; 6513let isTerminator = 1; 6514let isBranch = 1; 6515let isNewValue = 1; 6516let cofMax1 = 1; 6517let isRestrictNoSlot1Store = 1; 6518let Defs = [PC]; 6519let BaseOpcode = "J4_cmpeqn1r"; 6520let isTaken = Inst{13}; 6521let isExtendable = 1; 6522let opExtendable = 2; 6523let isExtentSigned = 1; 6524let opExtentBits = 11; 6525let opExtentAlign = 2; 6526let opNewValue = 0; 6527} 6528def J4_cmpeqn1_t_jumpnv_t : HInst< 6529(outs), 6530(ins IntRegs:$Ns8, n1Const:$n1, b30_2Imm:$Ii), 6531"if (cmp.eq($Ns8.new,#$n1)) jump:t $Ii", 6532tc_bd8382d1, TypeNCJ>, Enc_f7ea77, PredRel { 6533let Inst{0-0} = 0b0; 6534let Inst{13-8} = 0b100000; 6535let Inst{19-19} = 0b0; 6536let Inst{31-22} = 0b0010011000; 6537let isPredicated = 1; 6538let isTerminator = 1; 6539let isBranch = 1; 6540let isNewValue = 1; 6541let cofMax1 = 1; 6542let isRestrictNoSlot1Store = 1; 6543let Defs = [PC]; 6544let BaseOpcode = "J4_cmpeqn1r"; 6545let isTaken = Inst{13}; 6546let isExtendable = 1; 6547let opExtendable = 2; 6548let isExtentSigned = 1; 6549let opExtentBits = 11; 6550let opExtentAlign = 2; 6551let opNewValue = 0; 6552} 6553def J4_cmpeqn1_tp0_jump_nt : HInst< 6554(outs), 6555(ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii), 6556"p0 = cmp.eq($Rs16,#$n1); if (p0.new) jump:nt $Ii", 6557tc_3d495a39, TypeCJ>, Enc_405228, PredRel { 6558let Inst{0-0} = 0b0; 6559let Inst{13-8} = 0b000000; 6560let Inst{31-22} = 0b0001000110; 6561let isPredicated = 1; 6562let isTerminator = 1; 6563let isBranch = 1; 6564let isPredicatedNew = 1; 6565let cofRelax1 = 1; 6566let cofRelax2 = 1; 6567let cofMax1 = 1; 6568let Uses = [P0]; 6569let Defs = [P0, PC]; 6570let BaseOpcode = "J4_cmpeqn1p0"; 6571let isTaken = Inst{13}; 6572let isExtendable = 1; 6573let opExtendable = 2; 6574let isExtentSigned = 1; 6575let opExtentBits = 11; 6576let opExtentAlign = 2; 6577} 6578def J4_cmpeqn1_tp0_jump_t : HInst< 6579(outs), 6580(ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii), 6581"p0 = cmp.eq($Rs16,#$n1); if (p0.new) jump:t $Ii", 6582tc_3d495a39, TypeCJ>, Enc_3a2484, PredRel { 6583let Inst{0-0} = 0b0; 6584let Inst{13-8} = 0b100000; 6585let Inst{31-22} = 0b0001000110; 6586let isPredicated = 1; 6587let isTerminator = 1; 6588let isBranch = 1; 6589let isPredicatedNew = 1; 6590let cofRelax1 = 1; 6591let cofRelax2 = 1; 6592let cofMax1 = 1; 6593let Uses = [P0]; 6594let Defs = [P0, PC]; 6595let BaseOpcode = "J4_cmpeqn1p0"; 6596let isTaken = Inst{13}; 6597let isExtendable = 1; 6598let opExtendable = 2; 6599let isExtentSigned = 1; 6600let opExtentBits = 11; 6601let opExtentAlign = 2; 6602} 6603def J4_cmpeqn1_tp1_jump_nt : HInst< 6604(outs), 6605(ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii), 6606"p1 = cmp.eq($Rs16,#$n1); if (p1.new) jump:nt $Ii", 6607tc_3d495a39, TypeCJ>, Enc_736575, PredRel { 6608let Inst{0-0} = 0b0; 6609let Inst{13-8} = 0b000000; 6610let Inst{31-22} = 0b0001001110; 6611let isPredicated = 1; 6612let isTerminator = 1; 6613let isBranch = 1; 6614let isPredicatedNew = 1; 6615let cofRelax1 = 1; 6616let cofRelax2 = 1; 6617let cofMax1 = 1; 6618let Uses = [P1]; 6619let Defs = [P1, PC]; 6620let BaseOpcode = "J4_cmpeqn1p1"; 6621let isTaken = Inst{13}; 6622let isExtendable = 1; 6623let opExtendable = 2; 6624let isExtentSigned = 1; 6625let opExtentBits = 11; 6626let opExtentAlign = 2; 6627} 6628def J4_cmpeqn1_tp1_jump_t : HInst< 6629(outs), 6630(ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii), 6631"p1 = cmp.eq($Rs16,#$n1); if (p1.new) jump:t $Ii", 6632tc_3d495a39, TypeCJ>, Enc_8e583a, PredRel { 6633let Inst{0-0} = 0b0; 6634let Inst{13-8} = 0b100000; 6635let Inst{31-22} = 0b0001001110; 6636let isPredicated = 1; 6637let isTerminator = 1; 6638let isBranch = 1; 6639let isPredicatedNew = 1; 6640let cofRelax1 = 1; 6641let cofRelax2 = 1; 6642let cofMax1 = 1; 6643let Uses = [P1]; 6644let Defs = [P1, PC]; 6645let BaseOpcode = "J4_cmpeqn1p1"; 6646let isTaken = Inst{13}; 6647let isExtendable = 1; 6648let opExtendable = 2; 6649let isExtentSigned = 1; 6650let opExtentBits = 11; 6651let opExtentAlign = 2; 6652} 6653def J4_cmpgt_f_jumpnv_nt : HInst< 6654(outs), 6655(ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii), 6656"if (!cmp.gt($Ns8.new,$Rt32)) jump:nt $Ii", 6657tc_9bfd761f, TypeNCJ>, Enc_c9a18e, PredRel { 6658let Inst{0-0} = 0b0; 6659let Inst{13-13} = 0b0; 6660let Inst{19-19} = 0b0; 6661let Inst{31-22} = 0b0010000011; 6662let isPredicated = 1; 6663let isPredicatedFalse = 1; 6664let isTerminator = 1; 6665let isBranch = 1; 6666let isNewValue = 1; 6667let cofMax1 = 1; 6668let isRestrictNoSlot1Store = 1; 6669let Defs = [PC]; 6670let BaseOpcode = "J4_cmpgtr"; 6671let isTaken = Inst{13}; 6672let isExtendable = 1; 6673let opExtendable = 2; 6674let isExtentSigned = 1; 6675let opExtentBits = 11; 6676let opExtentAlign = 2; 6677let opNewValue = 0; 6678} 6679def J4_cmpgt_f_jumpnv_t : HInst< 6680(outs), 6681(ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii), 6682"if (!cmp.gt($Ns8.new,$Rt32)) jump:t $Ii", 6683tc_9bfd761f, TypeNCJ>, Enc_c9a18e, PredRel { 6684let Inst{0-0} = 0b0; 6685let Inst{13-13} = 0b1; 6686let Inst{19-19} = 0b0; 6687let Inst{31-22} = 0b0010000011; 6688let isPredicated = 1; 6689let isPredicatedFalse = 1; 6690let isTerminator = 1; 6691let isBranch = 1; 6692let isNewValue = 1; 6693let cofMax1 = 1; 6694let isRestrictNoSlot1Store = 1; 6695let Defs = [PC]; 6696let BaseOpcode = "J4_cmpgtr"; 6697let isTaken = Inst{13}; 6698let isExtendable = 1; 6699let opExtendable = 2; 6700let isExtentSigned = 1; 6701let opExtentBits = 11; 6702let opExtentAlign = 2; 6703let opNewValue = 0; 6704} 6705def J4_cmpgt_fp0_jump_nt : HInst< 6706(outs), 6707(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), 6708"p0 = cmp.gt($Rs16,$Rt16); if (!p0.new) jump:nt $Ii", 6709tc_56336eb0, TypeCJ>, Enc_6a5972, PredRel { 6710let Inst{0-0} = 0b0; 6711let Inst{13-12} = 0b00; 6712let Inst{31-22} = 0b0001010011; 6713let isPredicated = 1; 6714let isPredicatedFalse = 1; 6715let isTerminator = 1; 6716let isBranch = 1; 6717let isPredicatedNew = 1; 6718let cofRelax1 = 1; 6719let cofRelax2 = 1; 6720let cofMax1 = 1; 6721let Uses = [P0]; 6722let Defs = [P0, PC]; 6723let BaseOpcode = "J4_cmpgtp0"; 6724let isTaken = Inst{13}; 6725let isExtendable = 1; 6726let opExtendable = 2; 6727let isExtentSigned = 1; 6728let opExtentBits = 11; 6729let opExtentAlign = 2; 6730} 6731def J4_cmpgt_fp0_jump_t : HInst< 6732(outs), 6733(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), 6734"p0 = cmp.gt($Rs16,$Rt16); if (!p0.new) jump:t $Ii", 6735tc_56336eb0, TypeCJ>, Enc_6a5972, PredRel { 6736let Inst{0-0} = 0b0; 6737let Inst{13-12} = 0b10; 6738let Inst{31-22} = 0b0001010011; 6739let isPredicated = 1; 6740let isPredicatedFalse = 1; 6741let isTerminator = 1; 6742let isBranch = 1; 6743let isPredicatedNew = 1; 6744let cofRelax1 = 1; 6745let cofRelax2 = 1; 6746let cofMax1 = 1; 6747let Uses = [P0]; 6748let Defs = [P0, PC]; 6749let BaseOpcode = "J4_cmpgtp0"; 6750let isTaken = Inst{13}; 6751let isExtendable = 1; 6752let opExtendable = 2; 6753let isExtentSigned = 1; 6754let opExtentBits = 11; 6755let opExtentAlign = 2; 6756} 6757def J4_cmpgt_fp1_jump_nt : HInst< 6758(outs), 6759(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), 6760"p1 = cmp.gt($Rs16,$Rt16); if (!p1.new) jump:nt $Ii", 6761tc_56336eb0, TypeCJ>, Enc_6a5972, PredRel { 6762let Inst{0-0} = 0b0; 6763let Inst{13-12} = 0b01; 6764let Inst{31-22} = 0b0001010011; 6765let isPredicated = 1; 6766let isPredicatedFalse = 1; 6767let isTerminator = 1; 6768let isBranch = 1; 6769let isPredicatedNew = 1; 6770let cofRelax1 = 1; 6771let cofRelax2 = 1; 6772let cofMax1 = 1; 6773let Uses = [P1]; 6774let Defs = [P1, PC]; 6775let BaseOpcode = "J4_cmpgtp1"; 6776let isTaken = Inst{13}; 6777let isExtendable = 1; 6778let opExtendable = 2; 6779let isExtentSigned = 1; 6780let opExtentBits = 11; 6781let opExtentAlign = 2; 6782} 6783def J4_cmpgt_fp1_jump_t : HInst< 6784(outs), 6785(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), 6786"p1 = cmp.gt($Rs16,$Rt16); if (!p1.new) jump:t $Ii", 6787tc_56336eb0, TypeCJ>, Enc_6a5972, PredRel { 6788let Inst{0-0} = 0b0; 6789let Inst{13-12} = 0b11; 6790let Inst{31-22} = 0b0001010011; 6791let isPredicated = 1; 6792let isPredicatedFalse = 1; 6793let isTerminator = 1; 6794let isBranch = 1; 6795let isPredicatedNew = 1; 6796let cofRelax1 = 1; 6797let cofRelax2 = 1; 6798let cofMax1 = 1; 6799let Uses = [P1]; 6800let Defs = [P1, PC]; 6801let BaseOpcode = "J4_cmpgtp1"; 6802let isTaken = Inst{13}; 6803let isExtendable = 1; 6804let opExtendable = 2; 6805let isExtentSigned = 1; 6806let opExtentBits = 11; 6807let opExtentAlign = 2; 6808} 6809def J4_cmpgt_t_jumpnv_nt : HInst< 6810(outs), 6811(ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii), 6812"if (cmp.gt($Ns8.new,$Rt32)) jump:nt $Ii", 6813tc_9bfd761f, TypeNCJ>, Enc_c9a18e, PredRel { 6814let Inst{0-0} = 0b0; 6815let Inst{13-13} = 0b0; 6816let Inst{19-19} = 0b0; 6817let Inst{31-22} = 0b0010000010; 6818let isPredicated = 1; 6819let isTerminator = 1; 6820let isBranch = 1; 6821let isNewValue = 1; 6822let cofMax1 = 1; 6823let isRestrictNoSlot1Store = 1; 6824let Defs = [PC]; 6825let BaseOpcode = "J4_cmpgtr"; 6826let isTaken = Inst{13}; 6827let isExtendable = 1; 6828let opExtendable = 2; 6829let isExtentSigned = 1; 6830let opExtentBits = 11; 6831let opExtentAlign = 2; 6832let opNewValue = 0; 6833} 6834def J4_cmpgt_t_jumpnv_t : HInst< 6835(outs), 6836(ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii), 6837"if (cmp.gt($Ns8.new,$Rt32)) jump:t $Ii", 6838tc_9bfd761f, TypeNCJ>, Enc_c9a18e, PredRel { 6839let Inst{0-0} = 0b0; 6840let Inst{13-13} = 0b1; 6841let Inst{19-19} = 0b0; 6842let Inst{31-22} = 0b0010000010; 6843let isPredicated = 1; 6844let isTerminator = 1; 6845let isBranch = 1; 6846let isNewValue = 1; 6847let cofMax1 = 1; 6848let isRestrictNoSlot1Store = 1; 6849let Defs = [PC]; 6850let BaseOpcode = "J4_cmpgtr"; 6851let isTaken = Inst{13}; 6852let isExtendable = 1; 6853let opExtendable = 2; 6854let isExtentSigned = 1; 6855let opExtentBits = 11; 6856let opExtentAlign = 2; 6857let opNewValue = 0; 6858} 6859def J4_cmpgt_tp0_jump_nt : HInst< 6860(outs), 6861(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), 6862"p0 = cmp.gt($Rs16,$Rt16); if (p0.new) jump:nt $Ii", 6863tc_56336eb0, TypeCJ>, Enc_6a5972, PredRel { 6864let Inst{0-0} = 0b0; 6865let Inst{13-12} = 0b00; 6866let Inst{31-22} = 0b0001010010; 6867let isPredicated = 1; 6868let isTerminator = 1; 6869let isBranch = 1; 6870let isPredicatedNew = 1; 6871let cofRelax1 = 1; 6872let cofRelax2 = 1; 6873let cofMax1 = 1; 6874let Uses = [P0]; 6875let Defs = [P0, PC]; 6876let BaseOpcode = "J4_cmpgtp0"; 6877let isTaken = Inst{13}; 6878let isExtendable = 1; 6879let opExtendable = 2; 6880let isExtentSigned = 1; 6881let opExtentBits = 11; 6882let opExtentAlign = 2; 6883} 6884def J4_cmpgt_tp0_jump_t : HInst< 6885(outs), 6886(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), 6887"p0 = cmp.gt($Rs16,$Rt16); if (p0.new) jump:t $Ii", 6888tc_56336eb0, TypeCJ>, Enc_6a5972, PredRel { 6889let Inst{0-0} = 0b0; 6890let Inst{13-12} = 0b10; 6891let Inst{31-22} = 0b0001010010; 6892let isPredicated = 1; 6893let isTerminator = 1; 6894let isBranch = 1; 6895let isPredicatedNew = 1; 6896let cofRelax1 = 1; 6897let cofRelax2 = 1; 6898let cofMax1 = 1; 6899let Uses = [P0]; 6900let Defs = [P0, PC]; 6901let BaseOpcode = "J4_cmpgtp0"; 6902let isTaken = Inst{13}; 6903let isExtendable = 1; 6904let opExtendable = 2; 6905let isExtentSigned = 1; 6906let opExtentBits = 11; 6907let opExtentAlign = 2; 6908} 6909def J4_cmpgt_tp1_jump_nt : HInst< 6910(outs), 6911(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), 6912"p1 = cmp.gt($Rs16,$Rt16); if (p1.new) jump:nt $Ii", 6913tc_56336eb0, TypeCJ>, Enc_6a5972, PredRel { 6914let Inst{0-0} = 0b0; 6915let Inst{13-12} = 0b01; 6916let Inst{31-22} = 0b0001010010; 6917let isPredicated = 1; 6918let isTerminator = 1; 6919let isBranch = 1; 6920let isPredicatedNew = 1; 6921let cofRelax1 = 1; 6922let cofRelax2 = 1; 6923let cofMax1 = 1; 6924let Uses = [P1]; 6925let Defs = [P1, PC]; 6926let BaseOpcode = "J4_cmpgtp1"; 6927let isTaken = Inst{13}; 6928let isExtendable = 1; 6929let opExtendable = 2; 6930let isExtentSigned = 1; 6931let opExtentBits = 11; 6932let opExtentAlign = 2; 6933} 6934def J4_cmpgt_tp1_jump_t : HInst< 6935(outs), 6936(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), 6937"p1 = cmp.gt($Rs16,$Rt16); if (p1.new) jump:t $Ii", 6938tc_56336eb0, TypeCJ>, Enc_6a5972, PredRel { 6939let Inst{0-0} = 0b0; 6940let Inst{13-12} = 0b11; 6941let Inst{31-22} = 0b0001010010; 6942let isPredicated = 1; 6943let isTerminator = 1; 6944let isBranch = 1; 6945let isPredicatedNew = 1; 6946let cofRelax1 = 1; 6947let cofRelax2 = 1; 6948let cofMax1 = 1; 6949let Uses = [P1]; 6950let Defs = [P1, PC]; 6951let BaseOpcode = "J4_cmpgtp1"; 6952let isTaken = Inst{13}; 6953let isExtendable = 1; 6954let opExtendable = 2; 6955let isExtentSigned = 1; 6956let opExtentBits = 11; 6957let opExtentAlign = 2; 6958} 6959def J4_cmpgti_f_jumpnv_nt : HInst< 6960(outs), 6961(ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii), 6962"if (!cmp.gt($Ns8.new,#$II)) jump:nt $Ii", 6963tc_bd8382d1, TypeNCJ>, Enc_eafd18, PredRel { 6964let Inst{0-0} = 0b0; 6965let Inst{13-13} = 0b0; 6966let Inst{19-19} = 0b0; 6967let Inst{31-22} = 0b0010010011; 6968let isPredicated = 1; 6969let isPredicatedFalse = 1; 6970let isTerminator = 1; 6971let isBranch = 1; 6972let isNewValue = 1; 6973let cofMax1 = 1; 6974let isRestrictNoSlot1Store = 1; 6975let Defs = [PC]; 6976let BaseOpcode = "J4_cmpgtir"; 6977let isTaken = Inst{13}; 6978let isExtendable = 1; 6979let opExtendable = 2; 6980let isExtentSigned = 1; 6981let opExtentBits = 11; 6982let opExtentAlign = 2; 6983let opNewValue = 0; 6984} 6985def J4_cmpgti_f_jumpnv_t : HInst< 6986(outs), 6987(ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii), 6988"if (!cmp.gt($Ns8.new,#$II)) jump:t $Ii", 6989tc_bd8382d1, TypeNCJ>, Enc_eafd18, PredRel { 6990let Inst{0-0} = 0b0; 6991let Inst{13-13} = 0b1; 6992let Inst{19-19} = 0b0; 6993let Inst{31-22} = 0b0010010011; 6994let isPredicated = 1; 6995let isPredicatedFalse = 1; 6996let isTerminator = 1; 6997let isBranch = 1; 6998let isNewValue = 1; 6999let cofMax1 = 1; 7000let isRestrictNoSlot1Store = 1; 7001let Defs = [PC]; 7002let BaseOpcode = "J4_cmpgtir"; 7003let isTaken = Inst{13}; 7004let isExtendable = 1; 7005let opExtendable = 2; 7006let isExtentSigned = 1; 7007let opExtentBits = 11; 7008let opExtentAlign = 2; 7009let opNewValue = 0; 7010} 7011def J4_cmpgti_fp0_jump_nt : HInst< 7012(outs), 7013(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), 7014"p0 = cmp.gt($Rs16,#$II); if (!p0.new) jump:nt $Ii", 7015tc_3d495a39, TypeCJ>, Enc_14d27a, PredRel { 7016let Inst{0-0} = 0b0; 7017let Inst{13-13} = 0b0; 7018let Inst{31-22} = 0b0001000011; 7019let isPredicated = 1; 7020let isPredicatedFalse = 1; 7021let isTerminator = 1; 7022let isBranch = 1; 7023let isPredicatedNew = 1; 7024let cofRelax1 = 1; 7025let cofRelax2 = 1; 7026let cofMax1 = 1; 7027let Uses = [P0]; 7028let Defs = [P0, PC]; 7029let BaseOpcode = "J4_cmpgtip0"; 7030let isTaken = Inst{13}; 7031let isExtendable = 1; 7032let opExtendable = 2; 7033let isExtentSigned = 1; 7034let opExtentBits = 11; 7035let opExtentAlign = 2; 7036} 7037def J4_cmpgti_fp0_jump_t : HInst< 7038(outs), 7039(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), 7040"p0 = cmp.gt($Rs16,#$II); if (!p0.new) jump:t $Ii", 7041tc_3d495a39, TypeCJ>, Enc_14d27a, PredRel { 7042let Inst{0-0} = 0b0; 7043let Inst{13-13} = 0b1; 7044let Inst{31-22} = 0b0001000011; 7045let isPredicated = 1; 7046let isPredicatedFalse = 1; 7047let isTerminator = 1; 7048let isBranch = 1; 7049let isPredicatedNew = 1; 7050let cofRelax1 = 1; 7051let cofRelax2 = 1; 7052let cofMax1 = 1; 7053let Uses = [P0]; 7054let Defs = [P0, PC]; 7055let BaseOpcode = "J4_cmpgtip0"; 7056let isTaken = Inst{13}; 7057let isExtendable = 1; 7058let opExtendable = 2; 7059let isExtentSigned = 1; 7060let opExtentBits = 11; 7061let opExtentAlign = 2; 7062} 7063def J4_cmpgti_fp1_jump_nt : HInst< 7064(outs), 7065(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), 7066"p1 = cmp.gt($Rs16,#$II); if (!p1.new) jump:nt $Ii", 7067tc_3d495a39, TypeCJ>, Enc_14d27a, PredRel { 7068let Inst{0-0} = 0b0; 7069let Inst{13-13} = 0b0; 7070let Inst{31-22} = 0b0001001011; 7071let isPredicated = 1; 7072let isPredicatedFalse = 1; 7073let isTerminator = 1; 7074let isBranch = 1; 7075let isPredicatedNew = 1; 7076let cofRelax1 = 1; 7077let cofRelax2 = 1; 7078let cofMax1 = 1; 7079let Uses = [P1]; 7080let Defs = [P1, PC]; 7081let BaseOpcode = "J4_cmpgtip1"; 7082let isTaken = Inst{13}; 7083let isExtendable = 1; 7084let opExtendable = 2; 7085let isExtentSigned = 1; 7086let opExtentBits = 11; 7087let opExtentAlign = 2; 7088} 7089def J4_cmpgti_fp1_jump_t : HInst< 7090(outs), 7091(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), 7092"p1 = cmp.gt($Rs16,#$II); if (!p1.new) jump:t $Ii", 7093tc_3d495a39, TypeCJ>, Enc_14d27a, PredRel { 7094let Inst{0-0} = 0b0; 7095let Inst{13-13} = 0b1; 7096let Inst{31-22} = 0b0001001011; 7097let isPredicated = 1; 7098let isPredicatedFalse = 1; 7099let isTerminator = 1; 7100let isBranch = 1; 7101let isPredicatedNew = 1; 7102let cofRelax1 = 1; 7103let cofRelax2 = 1; 7104let cofMax1 = 1; 7105let Uses = [P1]; 7106let Defs = [P1, PC]; 7107let BaseOpcode = "J4_cmpgtip1"; 7108let isTaken = Inst{13}; 7109let isExtendable = 1; 7110let opExtendable = 2; 7111let isExtentSigned = 1; 7112let opExtentBits = 11; 7113let opExtentAlign = 2; 7114} 7115def J4_cmpgti_t_jumpnv_nt : HInst< 7116(outs), 7117(ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii), 7118"if (cmp.gt($Ns8.new,#$II)) jump:nt $Ii", 7119tc_bd8382d1, TypeNCJ>, Enc_eafd18, PredRel { 7120let Inst{0-0} = 0b0; 7121let Inst{13-13} = 0b0; 7122let Inst{19-19} = 0b0; 7123let Inst{31-22} = 0b0010010010; 7124let isPredicated = 1; 7125let isTerminator = 1; 7126let isBranch = 1; 7127let isNewValue = 1; 7128let cofMax1 = 1; 7129let isRestrictNoSlot1Store = 1; 7130let Defs = [PC]; 7131let BaseOpcode = "J4_cmpgtir"; 7132let isTaken = Inst{13}; 7133let isExtendable = 1; 7134let opExtendable = 2; 7135let isExtentSigned = 1; 7136let opExtentBits = 11; 7137let opExtentAlign = 2; 7138let opNewValue = 0; 7139} 7140def J4_cmpgti_t_jumpnv_t : HInst< 7141(outs), 7142(ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii), 7143"if (cmp.gt($Ns8.new,#$II)) jump:t $Ii", 7144tc_bd8382d1, TypeNCJ>, Enc_eafd18, PredRel { 7145let Inst{0-0} = 0b0; 7146let Inst{13-13} = 0b1; 7147let Inst{19-19} = 0b0; 7148let Inst{31-22} = 0b0010010010; 7149let isPredicated = 1; 7150let isTerminator = 1; 7151let isBranch = 1; 7152let isNewValue = 1; 7153let cofMax1 = 1; 7154let isRestrictNoSlot1Store = 1; 7155let Defs = [PC]; 7156let BaseOpcode = "J4_cmpgtir"; 7157let isTaken = Inst{13}; 7158let isExtendable = 1; 7159let opExtendable = 2; 7160let isExtentSigned = 1; 7161let opExtentBits = 11; 7162let opExtentAlign = 2; 7163let opNewValue = 0; 7164} 7165def J4_cmpgti_tp0_jump_nt : HInst< 7166(outs), 7167(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), 7168"p0 = cmp.gt($Rs16,#$II); if (p0.new) jump:nt $Ii", 7169tc_3d495a39, TypeCJ>, Enc_14d27a, PredRel { 7170let Inst{0-0} = 0b0; 7171let Inst{13-13} = 0b0; 7172let Inst{31-22} = 0b0001000010; 7173let isPredicated = 1; 7174let isTerminator = 1; 7175let isBranch = 1; 7176let isPredicatedNew = 1; 7177let cofRelax1 = 1; 7178let cofRelax2 = 1; 7179let cofMax1 = 1; 7180let Uses = [P0]; 7181let Defs = [P0, PC]; 7182let BaseOpcode = "J4_cmpgtip0"; 7183let isTaken = Inst{13}; 7184let isExtendable = 1; 7185let opExtendable = 2; 7186let isExtentSigned = 1; 7187let opExtentBits = 11; 7188let opExtentAlign = 2; 7189} 7190def J4_cmpgti_tp0_jump_t : HInst< 7191(outs), 7192(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), 7193"p0 = cmp.gt($Rs16,#$II); if (p0.new) jump:t $Ii", 7194tc_3d495a39, TypeCJ>, Enc_14d27a, PredRel { 7195let Inst{0-0} = 0b0; 7196let Inst{13-13} = 0b1; 7197let Inst{31-22} = 0b0001000010; 7198let isPredicated = 1; 7199let isTerminator = 1; 7200let isBranch = 1; 7201let isPredicatedNew = 1; 7202let cofRelax1 = 1; 7203let cofRelax2 = 1; 7204let cofMax1 = 1; 7205let Uses = [P0]; 7206let Defs = [P0, PC]; 7207let BaseOpcode = "J4_cmpgtip0"; 7208let isTaken = Inst{13}; 7209let isExtendable = 1; 7210let opExtendable = 2; 7211let isExtentSigned = 1; 7212let opExtentBits = 11; 7213let opExtentAlign = 2; 7214} 7215def J4_cmpgti_tp1_jump_nt : HInst< 7216(outs), 7217(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), 7218"p1 = cmp.gt($Rs16,#$II); if (p1.new) jump:nt $Ii", 7219tc_3d495a39, TypeCJ>, Enc_14d27a, PredRel { 7220let Inst{0-0} = 0b0; 7221let Inst{13-13} = 0b0; 7222let Inst{31-22} = 0b0001001010; 7223let isPredicated = 1; 7224let isTerminator = 1; 7225let isBranch = 1; 7226let isPredicatedNew = 1; 7227let cofRelax1 = 1; 7228let cofRelax2 = 1; 7229let cofMax1 = 1; 7230let Uses = [P1]; 7231let Defs = [P1, PC]; 7232let BaseOpcode = "J4_cmpgtip1"; 7233let isTaken = Inst{13}; 7234let isExtendable = 1; 7235let opExtendable = 2; 7236let isExtentSigned = 1; 7237let opExtentBits = 11; 7238let opExtentAlign = 2; 7239} 7240def J4_cmpgti_tp1_jump_t : HInst< 7241(outs), 7242(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), 7243"p1 = cmp.gt($Rs16,#$II); if (p1.new) jump:t $Ii", 7244tc_3d495a39, TypeCJ>, Enc_14d27a, PredRel { 7245let Inst{0-0} = 0b0; 7246let Inst{13-13} = 0b1; 7247let Inst{31-22} = 0b0001001010; 7248let isPredicated = 1; 7249let isTerminator = 1; 7250let isBranch = 1; 7251let isPredicatedNew = 1; 7252let cofRelax1 = 1; 7253let cofRelax2 = 1; 7254let cofMax1 = 1; 7255let Uses = [P1]; 7256let Defs = [P1, PC]; 7257let BaseOpcode = "J4_cmpgtip1"; 7258let isTaken = Inst{13}; 7259let isExtendable = 1; 7260let opExtendable = 2; 7261let isExtentSigned = 1; 7262let opExtentBits = 11; 7263let opExtentAlign = 2; 7264} 7265def J4_cmpgtn1_f_jumpnv_nt : HInst< 7266(outs), 7267(ins IntRegs:$Ns8, n1Const:$n1, b30_2Imm:$Ii), 7268"if (!cmp.gt($Ns8.new,#$n1)) jump:nt $Ii", 7269tc_bd8382d1, TypeNCJ>, Enc_3694bd, PredRel { 7270let Inst{0-0} = 0b0; 7271let Inst{13-8} = 0b000000; 7272let Inst{19-19} = 0b0; 7273let Inst{31-22} = 0b0010011011; 7274let isPredicated = 1; 7275let isPredicatedFalse = 1; 7276let isTerminator = 1; 7277let isBranch = 1; 7278let isNewValue = 1; 7279let cofMax1 = 1; 7280let isRestrictNoSlot1Store = 1; 7281let Defs = [PC]; 7282let BaseOpcode = "J4_cmpgtn1r"; 7283let isTaken = Inst{13}; 7284let isExtendable = 1; 7285let opExtendable = 2; 7286let isExtentSigned = 1; 7287let opExtentBits = 11; 7288let opExtentAlign = 2; 7289let opNewValue = 0; 7290} 7291def J4_cmpgtn1_f_jumpnv_t : HInst< 7292(outs), 7293(ins IntRegs:$Ns8, n1Const:$n1, b30_2Imm:$Ii), 7294"if (!cmp.gt($Ns8.new,#$n1)) jump:t $Ii", 7295tc_bd8382d1, TypeNCJ>, Enc_a6853f, PredRel { 7296let Inst{0-0} = 0b0; 7297let Inst{13-8} = 0b100000; 7298let Inst{19-19} = 0b0; 7299let Inst{31-22} = 0b0010011011; 7300let isPredicated = 1; 7301let isPredicatedFalse = 1; 7302let isTerminator = 1; 7303let isBranch = 1; 7304let isNewValue = 1; 7305let cofMax1 = 1; 7306let isRestrictNoSlot1Store = 1; 7307let Defs = [PC]; 7308let BaseOpcode = "J4_cmpgtn1r"; 7309let isTaken = Inst{13}; 7310let isExtendable = 1; 7311let opExtendable = 2; 7312let isExtentSigned = 1; 7313let opExtentBits = 11; 7314let opExtentAlign = 2; 7315let opNewValue = 0; 7316} 7317def J4_cmpgtn1_fp0_jump_nt : HInst< 7318(outs), 7319(ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii), 7320"p0 = cmp.gt($Rs16,#$n1); if (!p0.new) jump:nt $Ii", 7321tc_3d495a39, TypeCJ>, Enc_a42857, PredRel { 7322let Inst{0-0} = 0b0; 7323let Inst{13-8} = 0b000001; 7324let Inst{31-22} = 0b0001000111; 7325let isPredicated = 1; 7326let isPredicatedFalse = 1; 7327let isTerminator = 1; 7328let isBranch = 1; 7329let isPredicatedNew = 1; 7330let cofRelax1 = 1; 7331let cofRelax2 = 1; 7332let cofMax1 = 1; 7333let Uses = [P0]; 7334let Defs = [P0, PC]; 7335let BaseOpcode = "J4_cmpgtn1p0"; 7336let isTaken = Inst{13}; 7337let isExtendable = 1; 7338let opExtendable = 2; 7339let isExtentSigned = 1; 7340let opExtentBits = 11; 7341let opExtentAlign = 2; 7342} 7343def J4_cmpgtn1_fp0_jump_t : HInst< 7344(outs), 7345(ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii), 7346"p0 = cmp.gt($Rs16,#$n1); if (!p0.new) jump:t $Ii", 7347tc_3d495a39, TypeCJ>, Enc_f6fe0b, PredRel { 7348let Inst{0-0} = 0b0; 7349let Inst{13-8} = 0b100001; 7350let Inst{31-22} = 0b0001000111; 7351let isPredicated = 1; 7352let isPredicatedFalse = 1; 7353let isTerminator = 1; 7354let isBranch = 1; 7355let isPredicatedNew = 1; 7356let cofRelax1 = 1; 7357let cofRelax2 = 1; 7358let cofMax1 = 1; 7359let Uses = [P0]; 7360let Defs = [P0, PC]; 7361let BaseOpcode = "J4_cmpgtn1p0"; 7362let isTaken = Inst{13}; 7363let isExtendable = 1; 7364let opExtendable = 2; 7365let isExtentSigned = 1; 7366let opExtentBits = 11; 7367let opExtentAlign = 2; 7368} 7369def J4_cmpgtn1_fp1_jump_nt : HInst< 7370(outs), 7371(ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii), 7372"p1 = cmp.gt($Rs16,#$n1); if (!p1.new) jump:nt $Ii", 7373tc_3d495a39, TypeCJ>, Enc_3e3989, PredRel { 7374let Inst{0-0} = 0b0; 7375let Inst{13-8} = 0b000001; 7376let Inst{31-22} = 0b0001001111; 7377let isPredicated = 1; 7378let isPredicatedFalse = 1; 7379let isTerminator = 1; 7380let isBranch = 1; 7381let isPredicatedNew = 1; 7382let cofRelax1 = 1; 7383let cofRelax2 = 1; 7384let cofMax1 = 1; 7385let Uses = [P1]; 7386let Defs = [P1, PC]; 7387let BaseOpcode = "J4_cmpgtn1p1"; 7388let isTaken = Inst{13}; 7389let isExtendable = 1; 7390let opExtendable = 2; 7391let isExtentSigned = 1; 7392let opExtentBits = 11; 7393let opExtentAlign = 2; 7394} 7395def J4_cmpgtn1_fp1_jump_t : HInst< 7396(outs), 7397(ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii), 7398"p1 = cmp.gt($Rs16,#$n1); if (!p1.new) jump:t $Ii", 7399tc_3d495a39, TypeCJ>, Enc_b909d2, PredRel { 7400let Inst{0-0} = 0b0; 7401let Inst{13-8} = 0b100001; 7402let Inst{31-22} = 0b0001001111; 7403let isPredicated = 1; 7404let isPredicatedFalse = 1; 7405let isTerminator = 1; 7406let isBranch = 1; 7407let isPredicatedNew = 1; 7408let cofRelax1 = 1; 7409let cofRelax2 = 1; 7410let cofMax1 = 1; 7411let Uses = [P1]; 7412let Defs = [P1, PC]; 7413let BaseOpcode = "J4_cmpgtn1p1"; 7414let isTaken = Inst{13}; 7415let isExtendable = 1; 7416let opExtendable = 2; 7417let isExtentSigned = 1; 7418let opExtentBits = 11; 7419let opExtentAlign = 2; 7420} 7421def J4_cmpgtn1_t_jumpnv_nt : HInst< 7422(outs), 7423(ins IntRegs:$Ns8, n1Const:$n1, b30_2Imm:$Ii), 7424"if (cmp.gt($Ns8.new,#$n1)) jump:nt $Ii", 7425tc_bd8382d1, TypeNCJ>, Enc_f82302, PredRel { 7426let Inst{0-0} = 0b0; 7427let Inst{13-8} = 0b000000; 7428let Inst{19-19} = 0b0; 7429let Inst{31-22} = 0b0010011010; 7430let isPredicated = 1; 7431let isTerminator = 1; 7432let isBranch = 1; 7433let isNewValue = 1; 7434let cofMax1 = 1; 7435let isRestrictNoSlot1Store = 1; 7436let Defs = [PC]; 7437let BaseOpcode = "J4_cmpgtn1r"; 7438let isTaken = Inst{13}; 7439let isExtendable = 1; 7440let opExtendable = 2; 7441let isExtentSigned = 1; 7442let opExtentBits = 11; 7443let opExtentAlign = 2; 7444let opNewValue = 0; 7445} 7446def J4_cmpgtn1_t_jumpnv_t : HInst< 7447(outs), 7448(ins IntRegs:$Ns8, n1Const:$n1, b30_2Imm:$Ii), 7449"if (cmp.gt($Ns8.new,#$n1)) jump:t $Ii", 7450tc_bd8382d1, TypeNCJ>, Enc_6413b6, PredRel { 7451let Inst{0-0} = 0b0; 7452let Inst{13-8} = 0b100000; 7453let Inst{19-19} = 0b0; 7454let Inst{31-22} = 0b0010011010; 7455let isPredicated = 1; 7456let isTerminator = 1; 7457let isBranch = 1; 7458let isNewValue = 1; 7459let cofMax1 = 1; 7460let isRestrictNoSlot1Store = 1; 7461let Defs = [PC]; 7462let BaseOpcode = "J4_cmpgtn1r"; 7463let isTaken = Inst{13}; 7464let isExtendable = 1; 7465let opExtendable = 2; 7466let isExtentSigned = 1; 7467let opExtentBits = 11; 7468let opExtentAlign = 2; 7469let opNewValue = 0; 7470} 7471def J4_cmpgtn1_tp0_jump_nt : HInst< 7472(outs), 7473(ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii), 7474"p0 = cmp.gt($Rs16,#$n1); if (p0.new) jump:nt $Ii", 7475tc_3d495a39, TypeCJ>, Enc_b78edd, PredRel { 7476let Inst{0-0} = 0b0; 7477let Inst{13-8} = 0b000001; 7478let Inst{31-22} = 0b0001000110; 7479let isPredicated = 1; 7480let isTerminator = 1; 7481let isBranch = 1; 7482let isPredicatedNew = 1; 7483let cofRelax1 = 1; 7484let cofRelax2 = 1; 7485let cofMax1 = 1; 7486let Uses = [P0]; 7487let Defs = [P0, PC]; 7488let BaseOpcode = "J4_cmpgtn1p0"; 7489let isTaken = Inst{13}; 7490let isExtendable = 1; 7491let opExtendable = 2; 7492let isExtentSigned = 1; 7493let opExtentBits = 11; 7494let opExtentAlign = 2; 7495} 7496def J4_cmpgtn1_tp0_jump_t : HInst< 7497(outs), 7498(ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii), 7499"p0 = cmp.gt($Rs16,#$n1); if (p0.new) jump:t $Ii", 7500tc_3d495a39, TypeCJ>, Enc_041d7b, PredRel { 7501let Inst{0-0} = 0b0; 7502let Inst{13-8} = 0b100001; 7503let Inst{31-22} = 0b0001000110; 7504let isPredicated = 1; 7505let isTerminator = 1; 7506let isBranch = 1; 7507let isPredicatedNew = 1; 7508let cofRelax1 = 1; 7509let cofRelax2 = 1; 7510let cofMax1 = 1; 7511let Uses = [P0]; 7512let Defs = [P0, PC]; 7513let BaseOpcode = "J4_cmpgtn1p0"; 7514let isTaken = Inst{13}; 7515let isExtendable = 1; 7516let opExtendable = 2; 7517let isExtentSigned = 1; 7518let opExtentBits = 11; 7519let opExtentAlign = 2; 7520} 7521def J4_cmpgtn1_tp1_jump_nt : HInst< 7522(outs), 7523(ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii), 7524"p1 = cmp.gt($Rs16,#$n1); if (p1.new) jump:nt $Ii", 7525tc_3d495a39, TypeCJ>, Enc_b1e1fb, PredRel { 7526let Inst{0-0} = 0b0; 7527let Inst{13-8} = 0b000001; 7528let Inst{31-22} = 0b0001001110; 7529let isPredicated = 1; 7530let isTerminator = 1; 7531let isBranch = 1; 7532let isPredicatedNew = 1; 7533let cofRelax1 = 1; 7534let cofRelax2 = 1; 7535let cofMax1 = 1; 7536let Uses = [P1]; 7537let Defs = [P1, PC]; 7538let BaseOpcode = "J4_cmpgtn1p1"; 7539let isTaken = Inst{13}; 7540let isExtendable = 1; 7541let opExtendable = 2; 7542let isExtentSigned = 1; 7543let opExtentBits = 11; 7544let opExtentAlign = 2; 7545} 7546def J4_cmpgtn1_tp1_jump_t : HInst< 7547(outs), 7548(ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii), 7549"p1 = cmp.gt($Rs16,#$n1); if (p1.new) jump:t $Ii", 7550tc_3d495a39, TypeCJ>, Enc_178717, PredRel { 7551let Inst{0-0} = 0b0; 7552let Inst{13-8} = 0b100001; 7553let Inst{31-22} = 0b0001001110; 7554let isPredicated = 1; 7555let isTerminator = 1; 7556let isBranch = 1; 7557let isPredicatedNew = 1; 7558let cofRelax1 = 1; 7559let cofRelax2 = 1; 7560let cofMax1 = 1; 7561let Uses = [P1]; 7562let Defs = [P1, PC]; 7563let BaseOpcode = "J4_cmpgtn1p1"; 7564let isTaken = Inst{13}; 7565let isExtendable = 1; 7566let opExtendable = 2; 7567let isExtentSigned = 1; 7568let opExtentBits = 11; 7569let opExtentAlign = 2; 7570} 7571def J4_cmpgtu_f_jumpnv_nt : HInst< 7572(outs), 7573(ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii), 7574"if (!cmp.gtu($Ns8.new,$Rt32)) jump:nt $Ii", 7575tc_9bfd761f, TypeNCJ>, Enc_c9a18e, PredRel { 7576let Inst{0-0} = 0b0; 7577let Inst{13-13} = 0b0; 7578let Inst{19-19} = 0b0; 7579let Inst{31-22} = 0b0010000101; 7580let isPredicated = 1; 7581let isPredicatedFalse = 1; 7582let isTerminator = 1; 7583let isBranch = 1; 7584let isNewValue = 1; 7585let cofMax1 = 1; 7586let isRestrictNoSlot1Store = 1; 7587let Defs = [PC]; 7588let BaseOpcode = "J4_cmpgtur"; 7589let isTaken = Inst{13}; 7590let isExtendable = 1; 7591let opExtendable = 2; 7592let isExtentSigned = 1; 7593let opExtentBits = 11; 7594let opExtentAlign = 2; 7595let opNewValue = 0; 7596} 7597def J4_cmpgtu_f_jumpnv_t : HInst< 7598(outs), 7599(ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii), 7600"if (!cmp.gtu($Ns8.new,$Rt32)) jump:t $Ii", 7601tc_9bfd761f, TypeNCJ>, Enc_c9a18e, PredRel { 7602let Inst{0-0} = 0b0; 7603let Inst{13-13} = 0b1; 7604let Inst{19-19} = 0b0; 7605let Inst{31-22} = 0b0010000101; 7606let isPredicated = 1; 7607let isPredicatedFalse = 1; 7608let isTerminator = 1; 7609let isBranch = 1; 7610let isNewValue = 1; 7611let cofMax1 = 1; 7612let isRestrictNoSlot1Store = 1; 7613let Defs = [PC]; 7614let BaseOpcode = "J4_cmpgtur"; 7615let isTaken = Inst{13}; 7616let isExtendable = 1; 7617let opExtendable = 2; 7618let isExtentSigned = 1; 7619let opExtentBits = 11; 7620let opExtentAlign = 2; 7621let opNewValue = 0; 7622} 7623def J4_cmpgtu_fp0_jump_nt : HInst< 7624(outs), 7625(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), 7626"p0 = cmp.gtu($Rs16,$Rt16); if (!p0.new) jump:nt $Ii", 7627tc_56336eb0, TypeCJ>, Enc_6a5972, PredRel { 7628let Inst{0-0} = 0b0; 7629let Inst{13-12} = 0b00; 7630let Inst{31-22} = 0b0001010101; 7631let isPredicated = 1; 7632let isPredicatedFalse = 1; 7633let isTerminator = 1; 7634let isBranch = 1; 7635let isPredicatedNew = 1; 7636let cofRelax1 = 1; 7637let cofRelax2 = 1; 7638let cofMax1 = 1; 7639let Uses = [P0]; 7640let Defs = [P0, PC]; 7641let BaseOpcode = "J4_cmpgtup0"; 7642let isTaken = Inst{13}; 7643let isExtendable = 1; 7644let opExtendable = 2; 7645let isExtentSigned = 1; 7646let opExtentBits = 11; 7647let opExtentAlign = 2; 7648} 7649def J4_cmpgtu_fp0_jump_t : HInst< 7650(outs), 7651(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), 7652"p0 = cmp.gtu($Rs16,$Rt16); if (!p0.new) jump:t $Ii", 7653tc_56336eb0, TypeCJ>, Enc_6a5972, PredRel { 7654let Inst{0-0} = 0b0; 7655let Inst{13-12} = 0b10; 7656let Inst{31-22} = 0b0001010101; 7657let isPredicated = 1; 7658let isPredicatedFalse = 1; 7659let isTerminator = 1; 7660let isBranch = 1; 7661let isPredicatedNew = 1; 7662let cofRelax1 = 1; 7663let cofRelax2 = 1; 7664let cofMax1 = 1; 7665let Uses = [P0]; 7666let Defs = [P0, PC]; 7667let BaseOpcode = "J4_cmpgtup0"; 7668let isTaken = Inst{13}; 7669let isExtendable = 1; 7670let opExtendable = 2; 7671let isExtentSigned = 1; 7672let opExtentBits = 11; 7673let opExtentAlign = 2; 7674} 7675def J4_cmpgtu_fp1_jump_nt : HInst< 7676(outs), 7677(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), 7678"p1 = cmp.gtu($Rs16,$Rt16); if (!p1.new) jump:nt $Ii", 7679tc_56336eb0, TypeCJ>, Enc_6a5972, PredRel { 7680let Inst{0-0} = 0b0; 7681let Inst{13-12} = 0b01; 7682let Inst{31-22} = 0b0001010101; 7683let isPredicated = 1; 7684let isPredicatedFalse = 1; 7685let isTerminator = 1; 7686let isBranch = 1; 7687let isPredicatedNew = 1; 7688let cofRelax1 = 1; 7689let cofRelax2 = 1; 7690let cofMax1 = 1; 7691let Uses = [P1]; 7692let Defs = [P1, PC]; 7693let BaseOpcode = "J4_cmpgtup1"; 7694let isTaken = Inst{13}; 7695let isExtendable = 1; 7696let opExtendable = 2; 7697let isExtentSigned = 1; 7698let opExtentBits = 11; 7699let opExtentAlign = 2; 7700} 7701def J4_cmpgtu_fp1_jump_t : HInst< 7702(outs), 7703(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), 7704"p1 = cmp.gtu($Rs16,$Rt16); if (!p1.new) jump:t $Ii", 7705tc_56336eb0, TypeCJ>, Enc_6a5972, PredRel { 7706let Inst{0-0} = 0b0; 7707let Inst{13-12} = 0b11; 7708let Inst{31-22} = 0b0001010101; 7709let isPredicated = 1; 7710let isPredicatedFalse = 1; 7711let isTerminator = 1; 7712let isBranch = 1; 7713let isPredicatedNew = 1; 7714let cofRelax1 = 1; 7715let cofRelax2 = 1; 7716let cofMax1 = 1; 7717let Uses = [P1]; 7718let Defs = [P1, PC]; 7719let BaseOpcode = "J4_cmpgtup1"; 7720let isTaken = Inst{13}; 7721let isExtendable = 1; 7722let opExtendable = 2; 7723let isExtentSigned = 1; 7724let opExtentBits = 11; 7725let opExtentAlign = 2; 7726} 7727def J4_cmpgtu_t_jumpnv_nt : HInst< 7728(outs), 7729(ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii), 7730"if (cmp.gtu($Ns8.new,$Rt32)) jump:nt $Ii", 7731tc_9bfd761f, TypeNCJ>, Enc_c9a18e, PredRel { 7732let Inst{0-0} = 0b0; 7733let Inst{13-13} = 0b0; 7734let Inst{19-19} = 0b0; 7735let Inst{31-22} = 0b0010000100; 7736let isPredicated = 1; 7737let isTerminator = 1; 7738let isBranch = 1; 7739let isNewValue = 1; 7740let cofMax1 = 1; 7741let isRestrictNoSlot1Store = 1; 7742let Defs = [PC]; 7743let BaseOpcode = "J4_cmpgtur"; 7744let isTaken = Inst{13}; 7745let isExtendable = 1; 7746let opExtendable = 2; 7747let isExtentSigned = 1; 7748let opExtentBits = 11; 7749let opExtentAlign = 2; 7750let opNewValue = 0; 7751} 7752def J4_cmpgtu_t_jumpnv_t : HInst< 7753(outs), 7754(ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii), 7755"if (cmp.gtu($Ns8.new,$Rt32)) jump:t $Ii", 7756tc_9bfd761f, TypeNCJ>, Enc_c9a18e, PredRel { 7757let Inst{0-0} = 0b0; 7758let Inst{13-13} = 0b1; 7759let Inst{19-19} = 0b0; 7760let Inst{31-22} = 0b0010000100; 7761let isPredicated = 1; 7762let isTerminator = 1; 7763let isBranch = 1; 7764let isNewValue = 1; 7765let cofMax1 = 1; 7766let isRestrictNoSlot1Store = 1; 7767let Defs = [PC]; 7768let BaseOpcode = "J4_cmpgtur"; 7769let isTaken = Inst{13}; 7770let isExtendable = 1; 7771let opExtendable = 2; 7772let isExtentSigned = 1; 7773let opExtentBits = 11; 7774let opExtentAlign = 2; 7775let opNewValue = 0; 7776} 7777def J4_cmpgtu_tp0_jump_nt : HInst< 7778(outs), 7779(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), 7780"p0 = cmp.gtu($Rs16,$Rt16); if (p0.new) jump:nt $Ii", 7781tc_56336eb0, TypeCJ>, Enc_6a5972, PredRel { 7782let Inst{0-0} = 0b0; 7783let Inst{13-12} = 0b00; 7784let Inst{31-22} = 0b0001010100; 7785let isPredicated = 1; 7786let isTerminator = 1; 7787let isBranch = 1; 7788let isPredicatedNew = 1; 7789let cofRelax1 = 1; 7790let cofRelax2 = 1; 7791let cofMax1 = 1; 7792let Uses = [P0]; 7793let Defs = [P0, PC]; 7794let BaseOpcode = "J4_cmpgtup0"; 7795let isTaken = Inst{13}; 7796let isExtendable = 1; 7797let opExtendable = 2; 7798let isExtentSigned = 1; 7799let opExtentBits = 11; 7800let opExtentAlign = 2; 7801} 7802def J4_cmpgtu_tp0_jump_t : HInst< 7803(outs), 7804(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), 7805"p0 = cmp.gtu($Rs16,$Rt16); if (p0.new) jump:t $Ii", 7806tc_56336eb0, TypeCJ>, Enc_6a5972, PredRel { 7807let Inst{0-0} = 0b0; 7808let Inst{13-12} = 0b10; 7809let Inst{31-22} = 0b0001010100; 7810let isPredicated = 1; 7811let isTerminator = 1; 7812let isBranch = 1; 7813let isPredicatedNew = 1; 7814let cofRelax1 = 1; 7815let cofRelax2 = 1; 7816let cofMax1 = 1; 7817let Uses = [P0]; 7818let Defs = [P0, PC]; 7819let BaseOpcode = "J4_cmpgtup0"; 7820let isTaken = Inst{13}; 7821let isExtendable = 1; 7822let opExtendable = 2; 7823let isExtentSigned = 1; 7824let opExtentBits = 11; 7825let opExtentAlign = 2; 7826} 7827def J4_cmpgtu_tp1_jump_nt : HInst< 7828(outs), 7829(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), 7830"p1 = cmp.gtu($Rs16,$Rt16); if (p1.new) jump:nt $Ii", 7831tc_56336eb0, TypeCJ>, Enc_6a5972, PredRel { 7832let Inst{0-0} = 0b0; 7833let Inst{13-12} = 0b01; 7834let Inst{31-22} = 0b0001010100; 7835let isPredicated = 1; 7836let isTerminator = 1; 7837let isBranch = 1; 7838let isPredicatedNew = 1; 7839let cofRelax1 = 1; 7840let cofRelax2 = 1; 7841let cofMax1 = 1; 7842let Uses = [P1]; 7843let Defs = [P1, PC]; 7844let BaseOpcode = "J4_cmpgtup1"; 7845let isTaken = Inst{13}; 7846let isExtendable = 1; 7847let opExtendable = 2; 7848let isExtentSigned = 1; 7849let opExtentBits = 11; 7850let opExtentAlign = 2; 7851} 7852def J4_cmpgtu_tp1_jump_t : HInst< 7853(outs), 7854(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), 7855"p1 = cmp.gtu($Rs16,$Rt16); if (p1.new) jump:t $Ii", 7856tc_56336eb0, TypeCJ>, Enc_6a5972, PredRel { 7857let Inst{0-0} = 0b0; 7858let Inst{13-12} = 0b11; 7859let Inst{31-22} = 0b0001010100; 7860let isPredicated = 1; 7861let isTerminator = 1; 7862let isBranch = 1; 7863let isPredicatedNew = 1; 7864let cofRelax1 = 1; 7865let cofRelax2 = 1; 7866let cofMax1 = 1; 7867let Uses = [P1]; 7868let Defs = [P1, PC]; 7869let BaseOpcode = "J4_cmpgtup1"; 7870let isTaken = Inst{13}; 7871let isExtendable = 1; 7872let opExtendable = 2; 7873let isExtentSigned = 1; 7874let opExtentBits = 11; 7875let opExtentAlign = 2; 7876} 7877def J4_cmpgtui_f_jumpnv_nt : HInst< 7878(outs), 7879(ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii), 7880"if (!cmp.gtu($Ns8.new,#$II)) jump:nt $Ii", 7881tc_bd8382d1, TypeNCJ>, Enc_eafd18, PredRel { 7882let Inst{0-0} = 0b0; 7883let Inst{13-13} = 0b0; 7884let Inst{19-19} = 0b0; 7885let Inst{31-22} = 0b0010010101; 7886let isPredicated = 1; 7887let isPredicatedFalse = 1; 7888let isTerminator = 1; 7889let isBranch = 1; 7890let isNewValue = 1; 7891let cofMax1 = 1; 7892let isRestrictNoSlot1Store = 1; 7893let Defs = [PC]; 7894let BaseOpcode = "J4_cmpgtuir"; 7895let isTaken = Inst{13}; 7896let isExtendable = 1; 7897let opExtendable = 2; 7898let isExtentSigned = 1; 7899let opExtentBits = 11; 7900let opExtentAlign = 2; 7901let opNewValue = 0; 7902} 7903def J4_cmpgtui_f_jumpnv_t : HInst< 7904(outs), 7905(ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii), 7906"if (!cmp.gtu($Ns8.new,#$II)) jump:t $Ii", 7907tc_bd8382d1, TypeNCJ>, Enc_eafd18, PredRel { 7908let Inst{0-0} = 0b0; 7909let Inst{13-13} = 0b1; 7910let Inst{19-19} = 0b0; 7911let Inst{31-22} = 0b0010010101; 7912let isPredicated = 1; 7913let isPredicatedFalse = 1; 7914let isTerminator = 1; 7915let isBranch = 1; 7916let isNewValue = 1; 7917let cofMax1 = 1; 7918let isRestrictNoSlot1Store = 1; 7919let Defs = [PC]; 7920let BaseOpcode = "J4_cmpgtuir"; 7921let isTaken = Inst{13}; 7922let isExtendable = 1; 7923let opExtendable = 2; 7924let isExtentSigned = 1; 7925let opExtentBits = 11; 7926let opExtentAlign = 2; 7927let opNewValue = 0; 7928} 7929def J4_cmpgtui_fp0_jump_nt : HInst< 7930(outs), 7931(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), 7932"p0 = cmp.gtu($Rs16,#$II); if (!p0.new) jump:nt $Ii", 7933tc_3d495a39, TypeCJ>, Enc_14d27a, PredRel { 7934let Inst{0-0} = 0b0; 7935let Inst{13-13} = 0b0; 7936let Inst{31-22} = 0b0001000101; 7937let isPredicated = 1; 7938let isPredicatedFalse = 1; 7939let isTerminator = 1; 7940let isBranch = 1; 7941let isPredicatedNew = 1; 7942let cofRelax1 = 1; 7943let cofRelax2 = 1; 7944let cofMax1 = 1; 7945let Uses = [P0]; 7946let Defs = [P0, PC]; 7947let BaseOpcode = "J4_cmpgtuip0"; 7948let isTaken = Inst{13}; 7949let isExtendable = 1; 7950let opExtendable = 2; 7951let isExtentSigned = 1; 7952let opExtentBits = 11; 7953let opExtentAlign = 2; 7954} 7955def J4_cmpgtui_fp0_jump_t : HInst< 7956(outs), 7957(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), 7958"p0 = cmp.gtu($Rs16,#$II); if (!p0.new) jump:t $Ii", 7959tc_3d495a39, TypeCJ>, Enc_14d27a, PredRel { 7960let Inst{0-0} = 0b0; 7961let Inst{13-13} = 0b1; 7962let Inst{31-22} = 0b0001000101; 7963let isPredicated = 1; 7964let isPredicatedFalse = 1; 7965let isTerminator = 1; 7966let isBranch = 1; 7967let isPredicatedNew = 1; 7968let cofRelax1 = 1; 7969let cofRelax2 = 1; 7970let cofMax1 = 1; 7971let Uses = [P0]; 7972let Defs = [P0, PC]; 7973let BaseOpcode = "J4_cmpgtuip0"; 7974let isTaken = Inst{13}; 7975let isExtendable = 1; 7976let opExtendable = 2; 7977let isExtentSigned = 1; 7978let opExtentBits = 11; 7979let opExtentAlign = 2; 7980} 7981def J4_cmpgtui_fp1_jump_nt : HInst< 7982(outs), 7983(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), 7984"p1 = cmp.gtu($Rs16,#$II); if (!p1.new) jump:nt $Ii", 7985tc_3d495a39, TypeCJ>, Enc_14d27a, PredRel { 7986let Inst{0-0} = 0b0; 7987let Inst{13-13} = 0b0; 7988let Inst{31-22} = 0b0001001101; 7989let isPredicated = 1; 7990let isPredicatedFalse = 1; 7991let isTerminator = 1; 7992let isBranch = 1; 7993let isPredicatedNew = 1; 7994let cofRelax1 = 1; 7995let cofRelax2 = 1; 7996let cofMax1 = 1; 7997let Uses = [P1]; 7998let Defs = [P1, PC]; 7999let BaseOpcode = "J4_cmpgtuip1"; 8000let isTaken = Inst{13}; 8001let isExtendable = 1; 8002let opExtendable = 2; 8003let isExtentSigned = 1; 8004let opExtentBits = 11; 8005let opExtentAlign = 2; 8006} 8007def J4_cmpgtui_fp1_jump_t : HInst< 8008(outs), 8009(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), 8010"p1 = cmp.gtu($Rs16,#$II); if (!p1.new) jump:t $Ii", 8011tc_3d495a39, TypeCJ>, Enc_14d27a, PredRel { 8012let Inst{0-0} = 0b0; 8013let Inst{13-13} = 0b1; 8014let Inst{31-22} = 0b0001001101; 8015let isPredicated = 1; 8016let isPredicatedFalse = 1; 8017let isTerminator = 1; 8018let isBranch = 1; 8019let isPredicatedNew = 1; 8020let cofRelax1 = 1; 8021let cofRelax2 = 1; 8022let cofMax1 = 1; 8023let Uses = [P1]; 8024let Defs = [P1, PC]; 8025let BaseOpcode = "J4_cmpgtuip1"; 8026let isTaken = Inst{13}; 8027let isExtendable = 1; 8028let opExtendable = 2; 8029let isExtentSigned = 1; 8030let opExtentBits = 11; 8031let opExtentAlign = 2; 8032} 8033def J4_cmpgtui_t_jumpnv_nt : HInst< 8034(outs), 8035(ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii), 8036"if (cmp.gtu($Ns8.new,#$II)) jump:nt $Ii", 8037tc_bd8382d1, TypeNCJ>, Enc_eafd18, PredRel { 8038let Inst{0-0} = 0b0; 8039let Inst{13-13} = 0b0; 8040let Inst{19-19} = 0b0; 8041let Inst{31-22} = 0b0010010100; 8042let isPredicated = 1; 8043let isTerminator = 1; 8044let isBranch = 1; 8045let isNewValue = 1; 8046let cofMax1 = 1; 8047let isRestrictNoSlot1Store = 1; 8048let Defs = [PC]; 8049let BaseOpcode = "J4_cmpgtuir"; 8050let isTaken = Inst{13}; 8051let isExtendable = 1; 8052let opExtendable = 2; 8053let isExtentSigned = 1; 8054let opExtentBits = 11; 8055let opExtentAlign = 2; 8056let opNewValue = 0; 8057} 8058def J4_cmpgtui_t_jumpnv_t : HInst< 8059(outs), 8060(ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii), 8061"if (cmp.gtu($Ns8.new,#$II)) jump:t $Ii", 8062tc_bd8382d1, TypeNCJ>, Enc_eafd18, PredRel { 8063let Inst{0-0} = 0b0; 8064let Inst{13-13} = 0b1; 8065let Inst{19-19} = 0b0; 8066let Inst{31-22} = 0b0010010100; 8067let isPredicated = 1; 8068let isTerminator = 1; 8069let isBranch = 1; 8070let isNewValue = 1; 8071let cofMax1 = 1; 8072let isRestrictNoSlot1Store = 1; 8073let Defs = [PC]; 8074let BaseOpcode = "J4_cmpgtuir"; 8075let isTaken = Inst{13}; 8076let isExtendable = 1; 8077let opExtendable = 2; 8078let isExtentSigned = 1; 8079let opExtentBits = 11; 8080let opExtentAlign = 2; 8081let opNewValue = 0; 8082} 8083def J4_cmpgtui_tp0_jump_nt : HInst< 8084(outs), 8085(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), 8086"p0 = cmp.gtu($Rs16,#$II); if (p0.new) jump:nt $Ii", 8087tc_3d495a39, TypeCJ>, Enc_14d27a, PredRel { 8088let Inst{0-0} = 0b0; 8089let Inst{13-13} = 0b0; 8090let Inst{31-22} = 0b0001000100; 8091let isPredicated = 1; 8092let isTerminator = 1; 8093let isBranch = 1; 8094let isPredicatedNew = 1; 8095let cofRelax1 = 1; 8096let cofRelax2 = 1; 8097let cofMax1 = 1; 8098let Uses = [P0]; 8099let Defs = [P0, PC]; 8100let BaseOpcode = "J4_cmpgtuip0"; 8101let isTaken = Inst{13}; 8102let isExtendable = 1; 8103let opExtendable = 2; 8104let isExtentSigned = 1; 8105let opExtentBits = 11; 8106let opExtentAlign = 2; 8107} 8108def J4_cmpgtui_tp0_jump_t : HInst< 8109(outs), 8110(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), 8111"p0 = cmp.gtu($Rs16,#$II); if (p0.new) jump:t $Ii", 8112tc_3d495a39, TypeCJ>, Enc_14d27a, PredRel { 8113let Inst{0-0} = 0b0; 8114let Inst{13-13} = 0b1; 8115let Inst{31-22} = 0b0001000100; 8116let isPredicated = 1; 8117let isTerminator = 1; 8118let isBranch = 1; 8119let isPredicatedNew = 1; 8120let cofRelax1 = 1; 8121let cofRelax2 = 1; 8122let cofMax1 = 1; 8123let Uses = [P0]; 8124let Defs = [P0, PC]; 8125let BaseOpcode = "J4_cmpgtuip0"; 8126let isTaken = Inst{13}; 8127let isExtendable = 1; 8128let opExtendable = 2; 8129let isExtentSigned = 1; 8130let opExtentBits = 11; 8131let opExtentAlign = 2; 8132} 8133def J4_cmpgtui_tp1_jump_nt : HInst< 8134(outs), 8135(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), 8136"p1 = cmp.gtu($Rs16,#$II); if (p1.new) jump:nt $Ii", 8137tc_3d495a39, TypeCJ>, Enc_14d27a, PredRel { 8138let Inst{0-0} = 0b0; 8139let Inst{13-13} = 0b0; 8140let Inst{31-22} = 0b0001001100; 8141let isPredicated = 1; 8142let isTerminator = 1; 8143let isBranch = 1; 8144let isPredicatedNew = 1; 8145let cofRelax1 = 1; 8146let cofRelax2 = 1; 8147let cofMax1 = 1; 8148let Uses = [P1]; 8149let Defs = [P1, PC]; 8150let BaseOpcode = "J4_cmpgtuip1"; 8151let isTaken = Inst{13}; 8152let isExtendable = 1; 8153let opExtendable = 2; 8154let isExtentSigned = 1; 8155let opExtentBits = 11; 8156let opExtentAlign = 2; 8157} 8158def J4_cmpgtui_tp1_jump_t : HInst< 8159(outs), 8160(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), 8161"p1 = cmp.gtu($Rs16,#$II); if (p1.new) jump:t $Ii", 8162tc_3d495a39, TypeCJ>, Enc_14d27a, PredRel { 8163let Inst{0-0} = 0b0; 8164let Inst{13-13} = 0b1; 8165let Inst{31-22} = 0b0001001100; 8166let isPredicated = 1; 8167let isTerminator = 1; 8168let isBranch = 1; 8169let isPredicatedNew = 1; 8170let cofRelax1 = 1; 8171let cofRelax2 = 1; 8172let cofMax1 = 1; 8173let Uses = [P1]; 8174let Defs = [P1, PC]; 8175let BaseOpcode = "J4_cmpgtuip1"; 8176let isTaken = Inst{13}; 8177let isExtendable = 1; 8178let opExtendable = 2; 8179let isExtentSigned = 1; 8180let opExtentBits = 11; 8181let opExtentAlign = 2; 8182} 8183def J4_cmplt_f_jumpnv_nt : HInst< 8184(outs), 8185(ins IntRegs:$Rt32, IntRegs:$Ns8, b30_2Imm:$Ii), 8186"if (!cmp.gt($Rt32,$Ns8.new)) jump:nt $Ii", 8187tc_b343892a, TypeNCJ>, Enc_5de85f, PredRel { 8188let Inst{0-0} = 0b0; 8189let Inst{13-13} = 0b0; 8190let Inst{19-19} = 0b0; 8191let Inst{31-22} = 0b0010000111; 8192let isPredicated = 1; 8193let isPredicatedFalse = 1; 8194let isTerminator = 1; 8195let isBranch = 1; 8196let isNewValue = 1; 8197let cofMax1 = 1; 8198let isRestrictNoSlot1Store = 1; 8199let Defs = [PC]; 8200let BaseOpcode = "J4_cmpltr"; 8201let isTaken = Inst{13}; 8202let isExtendable = 1; 8203let opExtendable = 2; 8204let isExtentSigned = 1; 8205let opExtentBits = 11; 8206let opExtentAlign = 2; 8207let opNewValue = 1; 8208} 8209def J4_cmplt_f_jumpnv_t : HInst< 8210(outs), 8211(ins IntRegs:$Rt32, IntRegs:$Ns8, b30_2Imm:$Ii), 8212"if (!cmp.gt($Rt32,$Ns8.new)) jump:t $Ii", 8213tc_b343892a, TypeNCJ>, Enc_5de85f, PredRel { 8214let Inst{0-0} = 0b0; 8215let Inst{13-13} = 0b1; 8216let Inst{19-19} = 0b0; 8217let Inst{31-22} = 0b0010000111; 8218let isPredicated = 1; 8219let isPredicatedFalse = 1; 8220let isTerminator = 1; 8221let isBranch = 1; 8222let isNewValue = 1; 8223let cofMax1 = 1; 8224let isRestrictNoSlot1Store = 1; 8225let Defs = [PC]; 8226let BaseOpcode = "J4_cmpltr"; 8227let isTaken = Inst{13}; 8228let isExtendable = 1; 8229let opExtendable = 2; 8230let isExtentSigned = 1; 8231let opExtentBits = 11; 8232let opExtentAlign = 2; 8233let opNewValue = 1; 8234} 8235def J4_cmplt_t_jumpnv_nt : HInst< 8236(outs), 8237(ins IntRegs:$Rt32, IntRegs:$Ns8, b30_2Imm:$Ii), 8238"if (cmp.gt($Rt32,$Ns8.new)) jump:nt $Ii", 8239tc_b343892a, TypeNCJ>, Enc_5de85f, PredRel { 8240let Inst{0-0} = 0b0; 8241let Inst{13-13} = 0b0; 8242let Inst{19-19} = 0b0; 8243let Inst{31-22} = 0b0010000110; 8244let isPredicated = 1; 8245let isTerminator = 1; 8246let isBranch = 1; 8247let isNewValue = 1; 8248let cofMax1 = 1; 8249let isRestrictNoSlot1Store = 1; 8250let Defs = [PC]; 8251let BaseOpcode = "J4_cmpltr"; 8252let isTaken = Inst{13}; 8253let isExtendable = 1; 8254let opExtendable = 2; 8255let isExtentSigned = 1; 8256let opExtentBits = 11; 8257let opExtentAlign = 2; 8258let opNewValue = 1; 8259} 8260def J4_cmplt_t_jumpnv_t : HInst< 8261(outs), 8262(ins IntRegs:$Rt32, IntRegs:$Ns8, b30_2Imm:$Ii), 8263"if (cmp.gt($Rt32,$Ns8.new)) jump:t $Ii", 8264tc_b343892a, TypeNCJ>, Enc_5de85f, PredRel { 8265let Inst{0-0} = 0b0; 8266let Inst{13-13} = 0b1; 8267let Inst{19-19} = 0b0; 8268let Inst{31-22} = 0b0010000110; 8269let isPredicated = 1; 8270let isTerminator = 1; 8271let isBranch = 1; 8272let isNewValue = 1; 8273let cofMax1 = 1; 8274let isRestrictNoSlot1Store = 1; 8275let Defs = [PC]; 8276let BaseOpcode = "J4_cmpltr"; 8277let isTaken = Inst{13}; 8278let isExtendable = 1; 8279let opExtendable = 2; 8280let isExtentSigned = 1; 8281let opExtentBits = 11; 8282let opExtentAlign = 2; 8283let opNewValue = 1; 8284} 8285def J4_cmpltu_f_jumpnv_nt : HInst< 8286(outs), 8287(ins IntRegs:$Rt32, IntRegs:$Ns8, b30_2Imm:$Ii), 8288"if (!cmp.gtu($Rt32,$Ns8.new)) jump:nt $Ii", 8289tc_b343892a, TypeNCJ>, Enc_5de85f, PredRel { 8290let Inst{0-0} = 0b0; 8291let Inst{13-13} = 0b0; 8292let Inst{19-19} = 0b0; 8293let Inst{31-22} = 0b0010001001; 8294let isPredicated = 1; 8295let isPredicatedFalse = 1; 8296let isTerminator = 1; 8297let isBranch = 1; 8298let isNewValue = 1; 8299let cofMax1 = 1; 8300let isRestrictNoSlot1Store = 1; 8301let Defs = [PC]; 8302let BaseOpcode = "J4_cmpltur"; 8303let isTaken = Inst{13}; 8304let isExtendable = 1; 8305let opExtendable = 2; 8306let isExtentSigned = 1; 8307let opExtentBits = 11; 8308let opExtentAlign = 2; 8309let opNewValue = 1; 8310} 8311def J4_cmpltu_f_jumpnv_t : HInst< 8312(outs), 8313(ins IntRegs:$Rt32, IntRegs:$Ns8, b30_2Imm:$Ii), 8314"if (!cmp.gtu($Rt32,$Ns8.new)) jump:t $Ii", 8315tc_b343892a, TypeNCJ>, Enc_5de85f, PredRel { 8316let Inst{0-0} = 0b0; 8317let Inst{13-13} = 0b1; 8318let Inst{19-19} = 0b0; 8319let Inst{31-22} = 0b0010001001; 8320let isPredicated = 1; 8321let isPredicatedFalse = 1; 8322let isTerminator = 1; 8323let isBranch = 1; 8324let isNewValue = 1; 8325let cofMax1 = 1; 8326let isRestrictNoSlot1Store = 1; 8327let Defs = [PC]; 8328let BaseOpcode = "J4_cmpltur"; 8329let isTaken = Inst{13}; 8330let isExtendable = 1; 8331let opExtendable = 2; 8332let isExtentSigned = 1; 8333let opExtentBits = 11; 8334let opExtentAlign = 2; 8335let opNewValue = 1; 8336} 8337def J4_cmpltu_t_jumpnv_nt : HInst< 8338(outs), 8339(ins IntRegs:$Rt32, IntRegs:$Ns8, b30_2Imm:$Ii), 8340"if (cmp.gtu($Rt32,$Ns8.new)) jump:nt $Ii", 8341tc_b343892a, TypeNCJ>, Enc_5de85f, PredRel { 8342let Inst{0-0} = 0b0; 8343let Inst{13-13} = 0b0; 8344let Inst{19-19} = 0b0; 8345let Inst{31-22} = 0b0010001000; 8346let isPredicated = 1; 8347let isTerminator = 1; 8348let isBranch = 1; 8349let isNewValue = 1; 8350let cofMax1 = 1; 8351let isRestrictNoSlot1Store = 1; 8352let Defs = [PC]; 8353let BaseOpcode = "J4_cmpltur"; 8354let isTaken = Inst{13}; 8355let isExtendable = 1; 8356let opExtendable = 2; 8357let isExtentSigned = 1; 8358let opExtentBits = 11; 8359let opExtentAlign = 2; 8360let opNewValue = 1; 8361} 8362def J4_cmpltu_t_jumpnv_t : HInst< 8363(outs), 8364(ins IntRegs:$Rt32, IntRegs:$Ns8, b30_2Imm:$Ii), 8365"if (cmp.gtu($Rt32,$Ns8.new)) jump:t $Ii", 8366tc_b343892a, TypeNCJ>, Enc_5de85f, PredRel { 8367let Inst{0-0} = 0b0; 8368let Inst{13-13} = 0b1; 8369let Inst{19-19} = 0b0; 8370let Inst{31-22} = 0b0010001000; 8371let isPredicated = 1; 8372let isTerminator = 1; 8373let isBranch = 1; 8374let isNewValue = 1; 8375let cofMax1 = 1; 8376let isRestrictNoSlot1Store = 1; 8377let Defs = [PC]; 8378let BaseOpcode = "J4_cmpltur"; 8379let isTaken = Inst{13}; 8380let isExtendable = 1; 8381let opExtendable = 2; 8382let isExtentSigned = 1; 8383let opExtentBits = 11; 8384let opExtentAlign = 2; 8385let opNewValue = 1; 8386} 8387def J4_hintjumpr : HInst< 8388(outs), 8389(ins IntRegs:$Rs32), 8390"hintjr($Rs32)", 8391tc_d5b7b0c1, TypeJ>, Enc_ecbcc8 { 8392let Inst{13-0} = 0b00000000000000; 8393let Inst{31-21} = 0b01010010101; 8394let isTerminator = 1; 8395let isIndirectBranch = 1; 8396let isBranch = 1; 8397let cofMax1 = 1; 8398} 8399def J4_jumpseti : HInst< 8400(outs GeneralSubRegs:$Rd16), 8401(ins u6_0Imm:$II, b30_2Imm:$Ii), 8402"$Rd16 = #$II ; jump $Ii", 8403tc_0663f615, TypeCJ>, Enc_9e4c3f { 8404let Inst{0-0} = 0b0; 8405let Inst{31-22} = 0b0001011000; 8406let hasNewValue = 1; 8407let opNewValue = 0; 8408let isTerminator = 1; 8409let isBranch = 1; 8410let cofRelax2 = 1; 8411let cofMax1 = 1; 8412let Defs = [PC]; 8413let isExtendable = 1; 8414let opExtendable = 2; 8415let isExtentSigned = 1; 8416let opExtentBits = 11; 8417let opExtentAlign = 2; 8418} 8419def J4_jumpsetr : HInst< 8420(outs GeneralSubRegs:$Rd16), 8421(ins GeneralSubRegs:$Rs16, b30_2Imm:$Ii), 8422"$Rd16 = $Rs16 ; jump $Ii", 8423tc_0663f615, TypeCJ>, Enc_66bce1 { 8424let Inst{0-0} = 0b0; 8425let Inst{13-12} = 0b00; 8426let Inst{31-22} = 0b0001011100; 8427let hasNewValue = 1; 8428let opNewValue = 0; 8429let isTerminator = 1; 8430let isBranch = 1; 8431let cofRelax2 = 1; 8432let cofMax1 = 1; 8433let Defs = [PC]; 8434let isExtendable = 1; 8435let opExtendable = 2; 8436let isExtentSigned = 1; 8437let opExtentBits = 11; 8438let opExtentAlign = 2; 8439} 8440def J4_tstbit0_f_jumpnv_nt : HInst< 8441(outs), 8442(ins IntRegs:$Ns8, b30_2Imm:$Ii), 8443"if (!tstbit($Ns8.new,#0)) jump:nt $Ii", 8444tc_8c945be0, TypeNCJ>, Enc_69d63b { 8445let Inst{0-0} = 0b0; 8446let Inst{13-8} = 0b000000; 8447let Inst{19-19} = 0b0; 8448let Inst{31-22} = 0b0010010111; 8449let isPredicated = 1; 8450let isPredicatedFalse = 1; 8451let isTerminator = 1; 8452let isBranch = 1; 8453let isNewValue = 1; 8454let cofMax1 = 1; 8455let isRestrictNoSlot1Store = 1; 8456let Defs = [PC]; 8457let isTaken = Inst{13}; 8458let isExtendable = 1; 8459let opExtendable = 1; 8460let isExtentSigned = 1; 8461let opExtentBits = 11; 8462let opExtentAlign = 2; 8463let opNewValue = 0; 8464} 8465def J4_tstbit0_f_jumpnv_t : HInst< 8466(outs), 8467(ins IntRegs:$Ns8, b30_2Imm:$Ii), 8468"if (!tstbit($Ns8.new,#0)) jump:t $Ii", 8469tc_8c945be0, TypeNCJ>, Enc_69d63b { 8470let Inst{0-0} = 0b0; 8471let Inst{13-8} = 0b100000; 8472let Inst{19-19} = 0b0; 8473let Inst{31-22} = 0b0010010111; 8474let isPredicated = 1; 8475let isPredicatedFalse = 1; 8476let isTerminator = 1; 8477let isBranch = 1; 8478let isNewValue = 1; 8479let cofMax1 = 1; 8480let isRestrictNoSlot1Store = 1; 8481let Defs = [PC]; 8482let isTaken = Inst{13}; 8483let isExtendable = 1; 8484let opExtendable = 1; 8485let isExtentSigned = 1; 8486let opExtentBits = 11; 8487let opExtentAlign = 2; 8488let opNewValue = 0; 8489} 8490def J4_tstbit0_fp0_jump_nt : HInst< 8491(outs), 8492(ins GeneralSubRegs:$Rs16, b30_2Imm:$Ii), 8493"p0 = tstbit($Rs16,#0); if (!p0.new) jump:nt $Ii", 8494tc_2332b92e, TypeCJ>, Enc_ad1c74 { 8495let Inst{0-0} = 0b0; 8496let Inst{13-8} = 0b000011; 8497let Inst{31-22} = 0b0001000111; 8498let isPredicated = 1; 8499let isPredicatedFalse = 1; 8500let isTerminator = 1; 8501let isBranch = 1; 8502let isPredicatedNew = 1; 8503let cofRelax1 = 1; 8504let cofRelax2 = 1; 8505let cofMax1 = 1; 8506let Uses = [P0]; 8507let Defs = [P0, PC]; 8508let isTaken = Inst{13}; 8509let isExtendable = 1; 8510let opExtendable = 1; 8511let isExtentSigned = 1; 8512let opExtentBits = 11; 8513let opExtentAlign = 2; 8514} 8515def J4_tstbit0_fp0_jump_t : HInst< 8516(outs), 8517(ins GeneralSubRegs:$Rs16, b30_2Imm:$Ii), 8518"p0 = tstbit($Rs16,#0); if (!p0.new) jump:t $Ii", 8519tc_2332b92e, TypeCJ>, Enc_ad1c74 { 8520let Inst{0-0} = 0b0; 8521let Inst{13-8} = 0b100011; 8522let Inst{31-22} = 0b0001000111; 8523let isPredicated = 1; 8524let isPredicatedFalse = 1; 8525let isTerminator = 1; 8526let isBranch = 1; 8527let isPredicatedNew = 1; 8528let cofRelax1 = 1; 8529let cofRelax2 = 1; 8530let cofMax1 = 1; 8531let Uses = [P0]; 8532let Defs = [P0, PC]; 8533let isTaken = Inst{13}; 8534let isExtendable = 1; 8535let opExtendable = 1; 8536let isExtentSigned = 1; 8537let opExtentBits = 11; 8538let opExtentAlign = 2; 8539} 8540def J4_tstbit0_fp1_jump_nt : HInst< 8541(outs), 8542(ins GeneralSubRegs:$Rs16, b30_2Imm:$Ii), 8543"p1 = tstbit($Rs16,#0); if (!p1.new) jump:nt $Ii", 8544tc_2332b92e, TypeCJ>, Enc_ad1c74 { 8545let Inst{0-0} = 0b0; 8546let Inst{13-8} = 0b000011; 8547let Inst{31-22} = 0b0001001111; 8548let isPredicated = 1; 8549let isPredicatedFalse = 1; 8550let isTerminator = 1; 8551let isBranch = 1; 8552let isPredicatedNew = 1; 8553let cofRelax1 = 1; 8554let cofRelax2 = 1; 8555let cofMax1 = 1; 8556let Uses = [P1]; 8557let Defs = [P1, PC]; 8558let isTaken = Inst{13}; 8559let isExtendable = 1; 8560let opExtendable = 1; 8561let isExtentSigned = 1; 8562let opExtentBits = 11; 8563let opExtentAlign = 2; 8564} 8565def J4_tstbit0_fp1_jump_t : HInst< 8566(outs), 8567(ins GeneralSubRegs:$Rs16, b30_2Imm:$Ii), 8568"p1 = tstbit($Rs16,#0); if (!p1.new) jump:t $Ii", 8569tc_2332b92e, TypeCJ>, Enc_ad1c74 { 8570let Inst{0-0} = 0b0; 8571let Inst{13-8} = 0b100011; 8572let Inst{31-22} = 0b0001001111; 8573let isPredicated = 1; 8574let isPredicatedFalse = 1; 8575let isTerminator = 1; 8576let isBranch = 1; 8577let isPredicatedNew = 1; 8578let cofRelax1 = 1; 8579let cofRelax2 = 1; 8580let cofMax1 = 1; 8581let Uses = [P1]; 8582let Defs = [P1, PC]; 8583let isTaken = Inst{13}; 8584let isExtendable = 1; 8585let opExtendable = 1; 8586let isExtentSigned = 1; 8587let opExtentBits = 11; 8588let opExtentAlign = 2; 8589} 8590def J4_tstbit0_t_jumpnv_nt : HInst< 8591(outs), 8592(ins IntRegs:$Ns8, b30_2Imm:$Ii), 8593"if (tstbit($Ns8.new,#0)) jump:nt $Ii", 8594tc_8c945be0, TypeNCJ>, Enc_69d63b { 8595let Inst{0-0} = 0b0; 8596let Inst{13-8} = 0b000000; 8597let Inst{19-19} = 0b0; 8598let Inst{31-22} = 0b0010010110; 8599let isPredicated = 1; 8600let isTerminator = 1; 8601let isBranch = 1; 8602let isNewValue = 1; 8603let cofMax1 = 1; 8604let isRestrictNoSlot1Store = 1; 8605let Defs = [PC]; 8606let isTaken = Inst{13}; 8607let isExtendable = 1; 8608let opExtendable = 1; 8609let isExtentSigned = 1; 8610let opExtentBits = 11; 8611let opExtentAlign = 2; 8612let opNewValue = 0; 8613} 8614def J4_tstbit0_t_jumpnv_t : HInst< 8615(outs), 8616(ins IntRegs:$Ns8, b30_2Imm:$Ii), 8617"if (tstbit($Ns8.new,#0)) jump:t $Ii", 8618tc_8c945be0, TypeNCJ>, Enc_69d63b { 8619let Inst{0-0} = 0b0; 8620let Inst{13-8} = 0b100000; 8621let Inst{19-19} = 0b0; 8622let Inst{31-22} = 0b0010010110; 8623let isPredicated = 1; 8624let isTerminator = 1; 8625let isBranch = 1; 8626let isNewValue = 1; 8627let cofMax1 = 1; 8628let isRestrictNoSlot1Store = 1; 8629let Defs = [PC]; 8630let isTaken = Inst{13}; 8631let isExtendable = 1; 8632let opExtendable = 1; 8633let isExtentSigned = 1; 8634let opExtentBits = 11; 8635let opExtentAlign = 2; 8636let opNewValue = 0; 8637} 8638def J4_tstbit0_tp0_jump_nt : HInst< 8639(outs), 8640(ins GeneralSubRegs:$Rs16, b30_2Imm:$Ii), 8641"p0 = tstbit($Rs16,#0); if (p0.new) jump:nt $Ii", 8642tc_2332b92e, TypeCJ>, Enc_ad1c74 { 8643let Inst{0-0} = 0b0; 8644let Inst{13-8} = 0b000011; 8645let Inst{31-22} = 0b0001000110; 8646let isPredicated = 1; 8647let isTerminator = 1; 8648let isBranch = 1; 8649let isPredicatedNew = 1; 8650let cofRelax1 = 1; 8651let cofRelax2 = 1; 8652let cofMax1 = 1; 8653let Uses = [P0]; 8654let Defs = [P0, PC]; 8655let isTaken = Inst{13}; 8656let isExtendable = 1; 8657let opExtendable = 1; 8658let isExtentSigned = 1; 8659let opExtentBits = 11; 8660let opExtentAlign = 2; 8661} 8662def J4_tstbit0_tp0_jump_t : HInst< 8663(outs), 8664(ins GeneralSubRegs:$Rs16, b30_2Imm:$Ii), 8665"p0 = tstbit($Rs16,#0); if (p0.new) jump:t $Ii", 8666tc_2332b92e, TypeCJ>, Enc_ad1c74 { 8667let Inst{0-0} = 0b0; 8668let Inst{13-8} = 0b100011; 8669let Inst{31-22} = 0b0001000110; 8670let isPredicated = 1; 8671let isTerminator = 1; 8672let isBranch = 1; 8673let isPredicatedNew = 1; 8674let cofRelax1 = 1; 8675let cofRelax2 = 1; 8676let cofMax1 = 1; 8677let Uses = [P0]; 8678let Defs = [P0, PC]; 8679let isTaken = Inst{13}; 8680let isExtendable = 1; 8681let opExtendable = 1; 8682let isExtentSigned = 1; 8683let opExtentBits = 11; 8684let opExtentAlign = 2; 8685} 8686def J4_tstbit0_tp1_jump_nt : HInst< 8687(outs), 8688(ins GeneralSubRegs:$Rs16, b30_2Imm:$Ii), 8689"p1 = tstbit($Rs16,#0); if (p1.new) jump:nt $Ii", 8690tc_2332b92e, TypeCJ>, Enc_ad1c74 { 8691let Inst{0-0} = 0b0; 8692let Inst{13-8} = 0b000011; 8693let Inst{31-22} = 0b0001001110; 8694let isPredicated = 1; 8695let isTerminator = 1; 8696let isBranch = 1; 8697let isPredicatedNew = 1; 8698let cofRelax1 = 1; 8699let cofRelax2 = 1; 8700let cofMax1 = 1; 8701let Uses = [P1]; 8702let Defs = [P1, PC]; 8703let isTaken = Inst{13}; 8704let isExtendable = 1; 8705let opExtendable = 1; 8706let isExtentSigned = 1; 8707let opExtentBits = 11; 8708let opExtentAlign = 2; 8709} 8710def J4_tstbit0_tp1_jump_t : HInst< 8711(outs), 8712(ins GeneralSubRegs:$Rs16, b30_2Imm:$Ii), 8713"p1 = tstbit($Rs16,#0); if (p1.new) jump:t $Ii", 8714tc_2332b92e, TypeCJ>, Enc_ad1c74 { 8715let Inst{0-0} = 0b0; 8716let Inst{13-8} = 0b100011; 8717let Inst{31-22} = 0b0001001110; 8718let isPredicated = 1; 8719let isTerminator = 1; 8720let isBranch = 1; 8721let isPredicatedNew = 1; 8722let cofRelax1 = 1; 8723let cofRelax2 = 1; 8724let cofMax1 = 1; 8725let Uses = [P1]; 8726let Defs = [P1, PC]; 8727let isTaken = Inst{13}; 8728let isExtendable = 1; 8729let opExtendable = 1; 8730let isExtentSigned = 1; 8731let opExtentBits = 11; 8732let opExtentAlign = 2; 8733} 8734def L2_deallocframe : HInst< 8735(outs DoubleRegs:$Rdd32), 8736(ins IntRegs:$Rs32), 8737"$Rdd32 = deallocframe($Rs32):raw", 8738tc_15aa71c5, TypeLD>, Enc_3a3d62 { 8739let Inst{13-5} = 0b000000000; 8740let Inst{31-21} = 0b10010000000; 8741let accessSize = DoubleWordAccess; 8742let mayLoad = 1; 8743let Uses = [FRAMEKEY]; 8744let Defs = [R29]; 8745} 8746def L2_loadalignb_io : HInst< 8747(outs DoubleRegs:$Ryy32), 8748(ins DoubleRegs:$Ryy32in, IntRegs:$Rs32, s32_0Imm:$Ii), 8749"$Ryy32 = memb_fifo($Rs32+#$Ii)", 8750tc_5ef37dc4, TypeLD>, Enc_a27588 { 8751let Inst{24-21} = 0b0100; 8752let Inst{31-27} = 0b10010; 8753let addrMode = BaseImmOffset; 8754let accessSize = ByteAccess; 8755let mayLoad = 1; 8756let isExtendable = 1; 8757let opExtendable = 3; 8758let isExtentSigned = 1; 8759let opExtentBits = 11; 8760let opExtentAlign = 0; 8761let Constraints = "$Ryy32 = $Ryy32in"; 8762} 8763def L2_loadalignb_pbr : HInst< 8764(outs DoubleRegs:$Ryy32, IntRegs:$Rx32), 8765(ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, ModRegs:$Mu2), 8766"$Ryy32 = memb_fifo($Rx32++$Mu2:brev)", 8767tc_3c76b0ff, TypeLD>, Enc_1f5d8f { 8768let Inst{12-5} = 0b00000000; 8769let Inst{31-21} = 0b10011110100; 8770let addrMode = PostInc; 8771let accessSize = ByteAccess; 8772let mayLoad = 1; 8773let Constraints = "$Ryy32 = $Ryy32in, $Rx32 = $Rx32in"; 8774} 8775def L2_loadalignb_pci : HInst< 8776(outs DoubleRegs:$Ryy32, IntRegs:$Rx32), 8777(ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, s4_0Imm:$Ii, ModRegs:$Mu2), 8778"$Ryy32 = memb_fifo($Rx32++#$Ii:circ($Mu2))", 8779tc_785f65a7, TypeLD>, Enc_74aef2 { 8780let Inst{12-9} = 0b0000; 8781let Inst{31-21} = 0b10011000100; 8782let addrMode = PostInc; 8783let accessSize = ByteAccess; 8784let mayLoad = 1; 8785let Uses = [CS]; 8786let Constraints = "$Ryy32 = $Ryy32in, $Rx32 = $Rx32in"; 8787} 8788def L2_loadalignb_pcr : HInst< 8789(outs DoubleRegs:$Ryy32, IntRegs:$Rx32), 8790(ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, ModRegs:$Mu2), 8791"$Ryy32 = memb_fifo($Rx32++I:circ($Mu2))", 8792tc_3c76b0ff, TypeLD>, Enc_1f5d8f { 8793let Inst{12-5} = 0b00010000; 8794let Inst{31-21} = 0b10011000100; 8795let addrMode = PostInc; 8796let accessSize = ByteAccess; 8797let mayLoad = 1; 8798let Uses = [CS]; 8799let Constraints = "$Ryy32 = $Ryy32in, $Rx32 = $Rx32in"; 8800} 8801def L2_loadalignb_pi : HInst< 8802(outs DoubleRegs:$Ryy32, IntRegs:$Rx32), 8803(ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, s4_0Imm:$Ii), 8804"$Ryy32 = memb_fifo($Rx32++#$Ii)", 8805tc_3c76b0ff, TypeLD>, Enc_6b197f { 8806let Inst{13-9} = 0b00000; 8807let Inst{31-21} = 0b10011010100; 8808let addrMode = PostInc; 8809let accessSize = ByteAccess; 8810let mayLoad = 1; 8811let Constraints = "$Ryy32 = $Ryy32in, $Rx32 = $Rx32in"; 8812} 8813def L2_loadalignb_pr : HInst< 8814(outs DoubleRegs:$Ryy32, IntRegs:$Rx32), 8815(ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, ModRegs:$Mu2), 8816"$Ryy32 = memb_fifo($Rx32++$Mu2)", 8817tc_3c76b0ff, TypeLD>, Enc_1f5d8f { 8818let Inst{12-5} = 0b00000000; 8819let Inst{31-21} = 0b10011100100; 8820let addrMode = PostInc; 8821let accessSize = ByteAccess; 8822let mayLoad = 1; 8823let Constraints = "$Ryy32 = $Ryy32in, $Rx32 = $Rx32in"; 8824} 8825def L2_loadalignb_zomap : HInst< 8826(outs DoubleRegs:$Ryy32), 8827(ins DoubleRegs:$Ryy32in, IntRegs:$Rs32), 8828"$Ryy32 = memb_fifo($Rs32)", 8829tc_5ef37dc4, TypeMAPPING> { 8830let isPseudo = 1; 8831let isCodeGenOnly = 1; 8832let Constraints = "$Ryy32 = $Ryy32in"; 8833} 8834def L2_loadalignh_io : HInst< 8835(outs DoubleRegs:$Ryy32), 8836(ins DoubleRegs:$Ryy32in, IntRegs:$Rs32, s31_1Imm:$Ii), 8837"$Ryy32 = memh_fifo($Rs32+#$Ii)", 8838tc_5ef37dc4, TypeLD>, Enc_5cd7e9 { 8839let Inst{24-21} = 0b0010; 8840let Inst{31-27} = 0b10010; 8841let addrMode = BaseImmOffset; 8842let accessSize = HalfWordAccess; 8843let mayLoad = 1; 8844let isExtendable = 1; 8845let opExtendable = 3; 8846let isExtentSigned = 1; 8847let opExtentBits = 12; 8848let opExtentAlign = 1; 8849let Constraints = "$Ryy32 = $Ryy32in"; 8850} 8851def L2_loadalignh_pbr : HInst< 8852(outs DoubleRegs:$Ryy32, IntRegs:$Rx32), 8853(ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, ModRegs:$Mu2), 8854"$Ryy32 = memh_fifo($Rx32++$Mu2:brev)", 8855tc_3c76b0ff, TypeLD>, Enc_1f5d8f { 8856let Inst{12-5} = 0b00000000; 8857let Inst{31-21} = 0b10011110010; 8858let addrMode = PostInc; 8859let accessSize = HalfWordAccess; 8860let mayLoad = 1; 8861let Constraints = "$Ryy32 = $Ryy32in, $Rx32 = $Rx32in"; 8862} 8863def L2_loadalignh_pci : HInst< 8864(outs DoubleRegs:$Ryy32, IntRegs:$Rx32), 8865(ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, s4_1Imm:$Ii, ModRegs:$Mu2), 8866"$Ryy32 = memh_fifo($Rx32++#$Ii:circ($Mu2))", 8867tc_785f65a7, TypeLD>, Enc_9e2e1c { 8868let Inst{12-9} = 0b0000; 8869let Inst{31-21} = 0b10011000010; 8870let addrMode = PostInc; 8871let accessSize = HalfWordAccess; 8872let mayLoad = 1; 8873let Uses = [CS]; 8874let Constraints = "$Ryy32 = $Ryy32in, $Rx32 = $Rx32in"; 8875} 8876def L2_loadalignh_pcr : HInst< 8877(outs DoubleRegs:$Ryy32, IntRegs:$Rx32), 8878(ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, ModRegs:$Mu2), 8879"$Ryy32 = memh_fifo($Rx32++I:circ($Mu2))", 8880tc_3c76b0ff, TypeLD>, Enc_1f5d8f { 8881let Inst{12-5} = 0b00010000; 8882let Inst{31-21} = 0b10011000010; 8883let addrMode = PostInc; 8884let accessSize = HalfWordAccess; 8885let mayLoad = 1; 8886let Uses = [CS]; 8887let Constraints = "$Ryy32 = $Ryy32in, $Rx32 = $Rx32in"; 8888} 8889def L2_loadalignh_pi : HInst< 8890(outs DoubleRegs:$Ryy32, IntRegs:$Rx32), 8891(ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, s4_1Imm:$Ii), 8892"$Ryy32 = memh_fifo($Rx32++#$Ii)", 8893tc_3c76b0ff, TypeLD>, Enc_bd1cbc { 8894let Inst{13-9} = 0b00000; 8895let Inst{31-21} = 0b10011010010; 8896let addrMode = PostInc; 8897let accessSize = HalfWordAccess; 8898let mayLoad = 1; 8899let Constraints = "$Ryy32 = $Ryy32in, $Rx32 = $Rx32in"; 8900} 8901def L2_loadalignh_pr : HInst< 8902(outs DoubleRegs:$Ryy32, IntRegs:$Rx32), 8903(ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, ModRegs:$Mu2), 8904"$Ryy32 = memh_fifo($Rx32++$Mu2)", 8905tc_3c76b0ff, TypeLD>, Enc_1f5d8f { 8906let Inst{12-5} = 0b00000000; 8907let Inst{31-21} = 0b10011100010; 8908let addrMode = PostInc; 8909let accessSize = HalfWordAccess; 8910let mayLoad = 1; 8911let Constraints = "$Ryy32 = $Ryy32in, $Rx32 = $Rx32in"; 8912} 8913def L2_loadalignh_zomap : HInst< 8914(outs DoubleRegs:$Ryy32), 8915(ins DoubleRegs:$Ryy32in, IntRegs:$Rs32), 8916"$Ryy32 = memh_fifo($Rs32)", 8917tc_5ef37dc4, TypeMAPPING> { 8918let isPseudo = 1; 8919let isCodeGenOnly = 1; 8920let Constraints = "$Ryy32 = $Ryy32in"; 8921} 8922def L2_loadbsw2_io : HInst< 8923(outs IntRegs:$Rd32), 8924(ins IntRegs:$Rs32, s31_1Imm:$Ii), 8925"$Rd32 = membh($Rs32+#$Ii)", 8926tc_17e0d2cd, TypeLD>, Enc_de0214 { 8927let Inst{24-21} = 0b0001; 8928let Inst{31-27} = 0b10010; 8929let hasNewValue = 1; 8930let opNewValue = 0; 8931let addrMode = BaseImmOffset; 8932let accessSize = HalfWordAccess; 8933let mayLoad = 1; 8934let isExtendable = 1; 8935let opExtendable = 2; 8936let isExtentSigned = 1; 8937let opExtentBits = 12; 8938let opExtentAlign = 1; 8939} 8940def L2_loadbsw2_pbr : HInst< 8941(outs IntRegs:$Rd32, IntRegs:$Rx32), 8942(ins IntRegs:$Rx32in, ModRegs:$Mu2), 8943"$Rd32 = membh($Rx32++$Mu2:brev)", 8944tc_44d3da28, TypeLD>, Enc_74d4e5 { 8945let Inst{12-5} = 0b00000000; 8946let Inst{31-21} = 0b10011110001; 8947let hasNewValue = 1; 8948let opNewValue = 0; 8949let addrMode = PostInc; 8950let accessSize = HalfWordAccess; 8951let mayLoad = 1; 8952let Constraints = "$Rx32 = $Rx32in"; 8953} 8954def L2_loadbsw2_pci : HInst< 8955(outs IntRegs:$Rd32, IntRegs:$Rx32), 8956(ins IntRegs:$Rx32in, s4_1Imm:$Ii, ModRegs:$Mu2), 8957"$Rd32 = membh($Rx32++#$Ii:circ($Mu2))", 8958tc_e93a3d71, TypeLD>, Enc_e83554 { 8959let Inst{12-9} = 0b0000; 8960let Inst{31-21} = 0b10011000001; 8961let hasNewValue = 1; 8962let opNewValue = 0; 8963let addrMode = PostInc; 8964let accessSize = HalfWordAccess; 8965let mayLoad = 1; 8966let Uses = [CS]; 8967let Constraints = "$Rx32 = $Rx32in"; 8968} 8969def L2_loadbsw2_pcr : HInst< 8970(outs IntRegs:$Rd32, IntRegs:$Rx32), 8971(ins IntRegs:$Rx32in, ModRegs:$Mu2), 8972"$Rd32 = membh($Rx32++I:circ($Mu2))", 8973tc_44d3da28, TypeLD>, Enc_74d4e5 { 8974let Inst{12-5} = 0b00010000; 8975let Inst{31-21} = 0b10011000001; 8976let hasNewValue = 1; 8977let opNewValue = 0; 8978let addrMode = PostInc; 8979let accessSize = HalfWordAccess; 8980let mayLoad = 1; 8981let Uses = [CS]; 8982let Constraints = "$Rx32 = $Rx32in"; 8983} 8984def L2_loadbsw2_pi : HInst< 8985(outs IntRegs:$Rd32, IntRegs:$Rx32), 8986(ins IntRegs:$Rx32in, s4_1Imm:$Ii), 8987"$Rd32 = membh($Rx32++#$Ii)", 8988tc_44d3da28, TypeLD>, Enc_152467 { 8989let Inst{13-9} = 0b00000; 8990let Inst{31-21} = 0b10011010001; 8991let hasNewValue = 1; 8992let opNewValue = 0; 8993let addrMode = PostInc; 8994let accessSize = HalfWordAccess; 8995let mayLoad = 1; 8996let Constraints = "$Rx32 = $Rx32in"; 8997} 8998def L2_loadbsw2_pr : HInst< 8999(outs IntRegs:$Rd32, IntRegs:$Rx32), 9000(ins IntRegs:$Rx32in, ModRegs:$Mu2), 9001"$Rd32 = membh($Rx32++$Mu2)", 9002tc_44d3da28, TypeLD>, Enc_74d4e5 { 9003let Inst{12-5} = 0b00000000; 9004let Inst{31-21} = 0b10011100001; 9005let hasNewValue = 1; 9006let opNewValue = 0; 9007let addrMode = PostInc; 9008let accessSize = HalfWordAccess; 9009let mayLoad = 1; 9010let Constraints = "$Rx32 = $Rx32in"; 9011} 9012def L2_loadbsw2_zomap : HInst< 9013(outs IntRegs:$Rd32), 9014(ins IntRegs:$Rs32), 9015"$Rd32 = membh($Rs32)", 9016tc_17e0d2cd, TypeMAPPING> { 9017let hasNewValue = 1; 9018let opNewValue = 0; 9019let isPseudo = 1; 9020let isCodeGenOnly = 1; 9021} 9022def L2_loadbsw4_io : HInst< 9023(outs DoubleRegs:$Rdd32), 9024(ins IntRegs:$Rs32, s30_2Imm:$Ii), 9025"$Rdd32 = membh($Rs32+#$Ii)", 9026tc_17e0d2cd, TypeLD>, Enc_2d7491 { 9027let Inst{24-21} = 0b0111; 9028let Inst{31-27} = 0b10010; 9029let addrMode = BaseImmOffset; 9030let accessSize = WordAccess; 9031let mayLoad = 1; 9032let isExtendable = 1; 9033let opExtendable = 2; 9034let isExtentSigned = 1; 9035let opExtentBits = 13; 9036let opExtentAlign = 2; 9037} 9038def L2_loadbsw4_pbr : HInst< 9039(outs DoubleRegs:$Rdd32, IntRegs:$Rx32), 9040(ins IntRegs:$Rx32in, ModRegs:$Mu2), 9041"$Rdd32 = membh($Rx32++$Mu2:brev)", 9042tc_44d3da28, TypeLD>, Enc_7eee72 { 9043let Inst{12-5} = 0b00000000; 9044let Inst{31-21} = 0b10011110111; 9045let addrMode = PostInc; 9046let accessSize = WordAccess; 9047let mayLoad = 1; 9048let Constraints = "$Rx32 = $Rx32in"; 9049} 9050def L2_loadbsw4_pci : HInst< 9051(outs DoubleRegs:$Rdd32, IntRegs:$Rx32), 9052(ins IntRegs:$Rx32in, s4_2Imm:$Ii, ModRegs:$Mu2), 9053"$Rdd32 = membh($Rx32++#$Ii:circ($Mu2))", 9054tc_e93a3d71, TypeLD>, Enc_70b24b { 9055let Inst{12-9} = 0b0000; 9056let Inst{31-21} = 0b10011000111; 9057let addrMode = PostInc; 9058let accessSize = WordAccess; 9059let mayLoad = 1; 9060let Uses = [CS]; 9061let Constraints = "$Rx32 = $Rx32in"; 9062} 9063def L2_loadbsw4_pcr : HInst< 9064(outs DoubleRegs:$Rdd32, IntRegs:$Rx32), 9065(ins IntRegs:$Rx32in, ModRegs:$Mu2), 9066"$Rdd32 = membh($Rx32++I:circ($Mu2))", 9067tc_44d3da28, TypeLD>, Enc_7eee72 { 9068let Inst{12-5} = 0b00010000; 9069let Inst{31-21} = 0b10011000111; 9070let addrMode = PostInc; 9071let accessSize = WordAccess; 9072let mayLoad = 1; 9073let Uses = [CS]; 9074let Constraints = "$Rx32 = $Rx32in"; 9075} 9076def L2_loadbsw4_pi : HInst< 9077(outs DoubleRegs:$Rdd32, IntRegs:$Rx32), 9078(ins IntRegs:$Rx32in, s4_2Imm:$Ii), 9079"$Rdd32 = membh($Rx32++#$Ii)", 9080tc_44d3da28, TypeLD>, Enc_71f1b4 { 9081let Inst{13-9} = 0b00000; 9082let Inst{31-21} = 0b10011010111; 9083let addrMode = PostInc; 9084let accessSize = WordAccess; 9085let mayLoad = 1; 9086let Constraints = "$Rx32 = $Rx32in"; 9087} 9088def L2_loadbsw4_pr : HInst< 9089(outs DoubleRegs:$Rdd32, IntRegs:$Rx32), 9090(ins IntRegs:$Rx32in, ModRegs:$Mu2), 9091"$Rdd32 = membh($Rx32++$Mu2)", 9092tc_44d3da28, TypeLD>, Enc_7eee72 { 9093let Inst{12-5} = 0b00000000; 9094let Inst{31-21} = 0b10011100111; 9095let addrMode = PostInc; 9096let accessSize = WordAccess; 9097let mayLoad = 1; 9098let Constraints = "$Rx32 = $Rx32in"; 9099} 9100def L2_loadbsw4_zomap : HInst< 9101(outs DoubleRegs:$Rdd32), 9102(ins IntRegs:$Rs32), 9103"$Rdd32 = membh($Rs32)", 9104tc_17e0d2cd, TypeMAPPING> { 9105let isPseudo = 1; 9106let isCodeGenOnly = 1; 9107} 9108def L2_loadbzw2_io : HInst< 9109(outs IntRegs:$Rd32), 9110(ins IntRegs:$Rs32, s31_1Imm:$Ii), 9111"$Rd32 = memubh($Rs32+#$Ii)", 9112tc_17e0d2cd, TypeLD>, Enc_de0214 { 9113let Inst{24-21} = 0b0011; 9114let Inst{31-27} = 0b10010; 9115let hasNewValue = 1; 9116let opNewValue = 0; 9117let addrMode = BaseImmOffset; 9118let accessSize = HalfWordAccess; 9119let mayLoad = 1; 9120let isExtendable = 1; 9121let opExtendable = 2; 9122let isExtentSigned = 1; 9123let opExtentBits = 12; 9124let opExtentAlign = 1; 9125} 9126def L2_loadbzw2_pbr : HInst< 9127(outs IntRegs:$Rd32, IntRegs:$Rx32), 9128(ins IntRegs:$Rx32in, ModRegs:$Mu2), 9129"$Rd32 = memubh($Rx32++$Mu2:brev)", 9130tc_44d3da28, TypeLD>, Enc_74d4e5 { 9131let Inst{12-5} = 0b00000000; 9132let Inst{31-21} = 0b10011110011; 9133let hasNewValue = 1; 9134let opNewValue = 0; 9135let addrMode = PostInc; 9136let accessSize = HalfWordAccess; 9137let mayLoad = 1; 9138let Constraints = "$Rx32 = $Rx32in"; 9139} 9140def L2_loadbzw2_pci : HInst< 9141(outs IntRegs:$Rd32, IntRegs:$Rx32), 9142(ins IntRegs:$Rx32in, s4_1Imm:$Ii, ModRegs:$Mu2), 9143"$Rd32 = memubh($Rx32++#$Ii:circ($Mu2))", 9144tc_e93a3d71, TypeLD>, Enc_e83554 { 9145let Inst{12-9} = 0b0000; 9146let Inst{31-21} = 0b10011000011; 9147let hasNewValue = 1; 9148let opNewValue = 0; 9149let addrMode = PostInc; 9150let accessSize = HalfWordAccess; 9151let mayLoad = 1; 9152let Uses = [CS]; 9153let Constraints = "$Rx32 = $Rx32in"; 9154} 9155def L2_loadbzw2_pcr : HInst< 9156(outs IntRegs:$Rd32, IntRegs:$Rx32), 9157(ins IntRegs:$Rx32in, ModRegs:$Mu2), 9158"$Rd32 = memubh($Rx32++I:circ($Mu2))", 9159tc_44d3da28, TypeLD>, Enc_74d4e5 { 9160let Inst{12-5} = 0b00010000; 9161let Inst{31-21} = 0b10011000011; 9162let hasNewValue = 1; 9163let opNewValue = 0; 9164let addrMode = PostInc; 9165let accessSize = HalfWordAccess; 9166let mayLoad = 1; 9167let Uses = [CS]; 9168let Constraints = "$Rx32 = $Rx32in"; 9169} 9170def L2_loadbzw2_pi : HInst< 9171(outs IntRegs:$Rd32, IntRegs:$Rx32), 9172(ins IntRegs:$Rx32in, s4_1Imm:$Ii), 9173"$Rd32 = memubh($Rx32++#$Ii)", 9174tc_44d3da28, TypeLD>, Enc_152467 { 9175let Inst{13-9} = 0b00000; 9176let Inst{31-21} = 0b10011010011; 9177let hasNewValue = 1; 9178let opNewValue = 0; 9179let addrMode = PostInc; 9180let accessSize = HalfWordAccess; 9181let mayLoad = 1; 9182let Constraints = "$Rx32 = $Rx32in"; 9183} 9184def L2_loadbzw2_pr : HInst< 9185(outs IntRegs:$Rd32, IntRegs:$Rx32), 9186(ins IntRegs:$Rx32in, ModRegs:$Mu2), 9187"$Rd32 = memubh($Rx32++$Mu2)", 9188tc_44d3da28, TypeLD>, Enc_74d4e5 { 9189let Inst{12-5} = 0b00000000; 9190let Inst{31-21} = 0b10011100011; 9191let hasNewValue = 1; 9192let opNewValue = 0; 9193let addrMode = PostInc; 9194let accessSize = HalfWordAccess; 9195let mayLoad = 1; 9196let Constraints = "$Rx32 = $Rx32in"; 9197} 9198def L2_loadbzw2_zomap : HInst< 9199(outs IntRegs:$Rd32), 9200(ins IntRegs:$Rs32), 9201"$Rd32 = memubh($Rs32)", 9202tc_17e0d2cd, TypeMAPPING> { 9203let hasNewValue = 1; 9204let opNewValue = 0; 9205let isPseudo = 1; 9206let isCodeGenOnly = 1; 9207} 9208def L2_loadbzw4_io : HInst< 9209(outs DoubleRegs:$Rdd32), 9210(ins IntRegs:$Rs32, s30_2Imm:$Ii), 9211"$Rdd32 = memubh($Rs32+#$Ii)", 9212tc_17e0d2cd, TypeLD>, Enc_2d7491 { 9213let Inst{24-21} = 0b0101; 9214let Inst{31-27} = 0b10010; 9215let addrMode = BaseImmOffset; 9216let accessSize = WordAccess; 9217let mayLoad = 1; 9218let isExtendable = 1; 9219let opExtendable = 2; 9220let isExtentSigned = 1; 9221let opExtentBits = 13; 9222let opExtentAlign = 2; 9223} 9224def L2_loadbzw4_pbr : HInst< 9225(outs DoubleRegs:$Rdd32, IntRegs:$Rx32), 9226(ins IntRegs:$Rx32in, ModRegs:$Mu2), 9227"$Rdd32 = memubh($Rx32++$Mu2:brev)", 9228tc_44d3da28, TypeLD>, Enc_7eee72 { 9229let Inst{12-5} = 0b00000000; 9230let Inst{31-21} = 0b10011110101; 9231let addrMode = PostInc; 9232let accessSize = WordAccess; 9233let mayLoad = 1; 9234let Constraints = "$Rx32 = $Rx32in"; 9235} 9236def L2_loadbzw4_pci : HInst< 9237(outs DoubleRegs:$Rdd32, IntRegs:$Rx32), 9238(ins IntRegs:$Rx32in, s4_2Imm:$Ii, ModRegs:$Mu2), 9239"$Rdd32 = memubh($Rx32++#$Ii:circ($Mu2))", 9240tc_e93a3d71, TypeLD>, Enc_70b24b { 9241let Inst{12-9} = 0b0000; 9242let Inst{31-21} = 0b10011000101; 9243let addrMode = PostInc; 9244let accessSize = WordAccess; 9245let mayLoad = 1; 9246let Uses = [CS]; 9247let Constraints = "$Rx32 = $Rx32in"; 9248} 9249def L2_loadbzw4_pcr : HInst< 9250(outs DoubleRegs:$Rdd32, IntRegs:$Rx32), 9251(ins IntRegs:$Rx32in, ModRegs:$Mu2), 9252"$Rdd32 = memubh($Rx32++I:circ($Mu2))", 9253tc_44d3da28, TypeLD>, Enc_7eee72 { 9254let Inst{12-5} = 0b00010000; 9255let Inst{31-21} = 0b10011000101; 9256let addrMode = PostInc; 9257let accessSize = WordAccess; 9258let mayLoad = 1; 9259let Uses = [CS]; 9260let Constraints = "$Rx32 = $Rx32in"; 9261} 9262def L2_loadbzw4_pi : HInst< 9263(outs DoubleRegs:$Rdd32, IntRegs:$Rx32), 9264(ins IntRegs:$Rx32in, s4_2Imm:$Ii), 9265"$Rdd32 = memubh($Rx32++#$Ii)", 9266tc_44d3da28, TypeLD>, Enc_71f1b4 { 9267let Inst{13-9} = 0b00000; 9268let Inst{31-21} = 0b10011010101; 9269let addrMode = PostInc; 9270let accessSize = WordAccess; 9271let mayLoad = 1; 9272let Constraints = "$Rx32 = $Rx32in"; 9273} 9274def L2_loadbzw4_pr : HInst< 9275(outs DoubleRegs:$Rdd32, IntRegs:$Rx32), 9276(ins IntRegs:$Rx32in, ModRegs:$Mu2), 9277"$Rdd32 = memubh($Rx32++$Mu2)", 9278tc_44d3da28, TypeLD>, Enc_7eee72 { 9279let Inst{12-5} = 0b00000000; 9280let Inst{31-21} = 0b10011100101; 9281let addrMode = PostInc; 9282let accessSize = WordAccess; 9283let mayLoad = 1; 9284let Constraints = "$Rx32 = $Rx32in"; 9285} 9286def L2_loadbzw4_zomap : HInst< 9287(outs DoubleRegs:$Rdd32), 9288(ins IntRegs:$Rs32), 9289"$Rdd32 = memubh($Rs32)", 9290tc_17e0d2cd, TypeMAPPING> { 9291let isPseudo = 1; 9292let isCodeGenOnly = 1; 9293} 9294def L2_loadrb_io : HInst< 9295(outs IntRegs:$Rd32), 9296(ins IntRegs:$Rs32, s32_0Imm:$Ii), 9297"$Rd32 = memb($Rs32+#$Ii)", 9298tc_17e0d2cd, TypeLD>, Enc_211aaa, AddrModeRel, PostInc_BaseImm { 9299let Inst{24-21} = 0b1000; 9300let Inst{31-27} = 0b10010; 9301let hasNewValue = 1; 9302let opNewValue = 0; 9303let addrMode = BaseImmOffset; 9304let accessSize = ByteAccess; 9305let mayLoad = 1; 9306let CextOpcode = "L2_loadrb"; 9307let BaseOpcode = "L2_loadrb_io"; 9308let isPredicable = 1; 9309let isExtendable = 1; 9310let opExtendable = 2; 9311let isExtentSigned = 1; 9312let opExtentBits = 11; 9313let opExtentAlign = 0; 9314} 9315def L2_loadrb_pbr : HInst< 9316(outs IntRegs:$Rd32, IntRegs:$Rx32), 9317(ins IntRegs:$Rx32in, ModRegs:$Mu2), 9318"$Rd32 = memb($Rx32++$Mu2:brev)", 9319tc_44d3da28, TypeLD>, Enc_74d4e5 { 9320let Inst{12-5} = 0b00000000; 9321let Inst{31-21} = 0b10011111000; 9322let hasNewValue = 1; 9323let opNewValue = 0; 9324let addrMode = PostInc; 9325let accessSize = ByteAccess; 9326let mayLoad = 1; 9327let Constraints = "$Rx32 = $Rx32in"; 9328} 9329def L2_loadrb_pci : HInst< 9330(outs IntRegs:$Rd32, IntRegs:$Rx32), 9331(ins IntRegs:$Rx32in, s4_0Imm:$Ii, ModRegs:$Mu2), 9332"$Rd32 = memb($Rx32++#$Ii:circ($Mu2))", 9333tc_e93a3d71, TypeLD>, Enc_e0a47a { 9334let Inst{12-9} = 0b0000; 9335let Inst{31-21} = 0b10011001000; 9336let hasNewValue = 1; 9337let opNewValue = 0; 9338let addrMode = PostInc; 9339let accessSize = ByteAccess; 9340let mayLoad = 1; 9341let Uses = [CS]; 9342let Constraints = "$Rx32 = $Rx32in"; 9343} 9344def L2_loadrb_pcr : HInst< 9345(outs IntRegs:$Rd32, IntRegs:$Rx32), 9346(ins IntRegs:$Rx32in, ModRegs:$Mu2), 9347"$Rd32 = memb($Rx32++I:circ($Mu2))", 9348tc_44d3da28, TypeLD>, Enc_74d4e5 { 9349let Inst{12-5} = 0b00010000; 9350let Inst{31-21} = 0b10011001000; 9351let hasNewValue = 1; 9352let opNewValue = 0; 9353let addrMode = PostInc; 9354let accessSize = ByteAccess; 9355let mayLoad = 1; 9356let Uses = [CS]; 9357let Constraints = "$Rx32 = $Rx32in"; 9358} 9359def L2_loadrb_pi : HInst< 9360(outs IntRegs:$Rd32, IntRegs:$Rx32), 9361(ins IntRegs:$Rx32in, s4_0Imm:$Ii), 9362"$Rd32 = memb($Rx32++#$Ii)", 9363tc_44d3da28, TypeLD>, Enc_222336, PredNewRel, PostInc_BaseImm { 9364let Inst{13-9} = 0b00000; 9365let Inst{31-21} = 0b10011011000; 9366let hasNewValue = 1; 9367let opNewValue = 0; 9368let addrMode = PostInc; 9369let accessSize = ByteAccess; 9370let mayLoad = 1; 9371let CextOpcode = "L2_loadrb"; 9372let BaseOpcode = "L2_loadrb_pi"; 9373let isPredicable = 1; 9374let Constraints = "$Rx32 = $Rx32in"; 9375} 9376def L2_loadrb_pr : HInst< 9377(outs IntRegs:$Rd32, IntRegs:$Rx32), 9378(ins IntRegs:$Rx32in, ModRegs:$Mu2), 9379"$Rd32 = memb($Rx32++$Mu2)", 9380tc_44d3da28, TypeLD>, Enc_74d4e5 { 9381let Inst{12-5} = 0b00000000; 9382let Inst{31-21} = 0b10011101000; 9383let hasNewValue = 1; 9384let opNewValue = 0; 9385let addrMode = PostInc; 9386let accessSize = ByteAccess; 9387let mayLoad = 1; 9388let Constraints = "$Rx32 = $Rx32in"; 9389} 9390def L2_loadrb_zomap : HInst< 9391(outs IntRegs:$Rd32), 9392(ins IntRegs:$Rs32), 9393"$Rd32 = memb($Rs32)", 9394tc_17e0d2cd, TypeMAPPING> { 9395let hasNewValue = 1; 9396let opNewValue = 0; 9397let isPseudo = 1; 9398let isCodeGenOnly = 1; 9399} 9400def L2_loadrbgp : HInst< 9401(outs IntRegs:$Rd32), 9402(ins u32_0Imm:$Ii), 9403"$Rd32 = memb(gp+#$Ii)", 9404tc_c4db48cb, TypeV2LDST>, Enc_25bef0, AddrModeRel { 9405let Inst{24-21} = 0b1000; 9406let Inst{31-27} = 0b01001; 9407let hasNewValue = 1; 9408let opNewValue = 0; 9409let accessSize = ByteAccess; 9410let mayLoad = 1; 9411let Uses = [GP]; 9412let BaseOpcode = "L4_loadrb_abs"; 9413let isPredicable = 1; 9414let opExtendable = 1; 9415let isExtentSigned = 0; 9416let opExtentBits = 16; 9417let opExtentAlign = 0; 9418} 9419def L2_loadrd_io : HInst< 9420(outs DoubleRegs:$Rdd32), 9421(ins IntRegs:$Rs32, s29_3Imm:$Ii), 9422"$Rdd32 = memd($Rs32+#$Ii)", 9423tc_17e0d2cd, TypeLD>, Enc_fa3ba4, AddrModeRel, PostInc_BaseImm { 9424let Inst{24-21} = 0b1110; 9425let Inst{31-27} = 0b10010; 9426let addrMode = BaseImmOffset; 9427let accessSize = DoubleWordAccess; 9428let mayLoad = 1; 9429let CextOpcode = "L2_loadrd"; 9430let BaseOpcode = "L2_loadrd_io"; 9431let isPredicable = 1; 9432let isExtendable = 1; 9433let opExtendable = 2; 9434let isExtentSigned = 1; 9435let opExtentBits = 14; 9436let opExtentAlign = 3; 9437} 9438def L2_loadrd_pbr : HInst< 9439(outs DoubleRegs:$Rdd32, IntRegs:$Rx32), 9440(ins IntRegs:$Rx32in, ModRegs:$Mu2), 9441"$Rdd32 = memd($Rx32++$Mu2:brev)", 9442tc_44d3da28, TypeLD>, Enc_7eee72 { 9443let Inst{12-5} = 0b00000000; 9444let Inst{31-21} = 0b10011111110; 9445let addrMode = PostInc; 9446let accessSize = DoubleWordAccess; 9447let mayLoad = 1; 9448let Constraints = "$Rx32 = $Rx32in"; 9449} 9450def L2_loadrd_pci : HInst< 9451(outs DoubleRegs:$Rdd32, IntRegs:$Rx32), 9452(ins IntRegs:$Rx32in, s4_3Imm:$Ii, ModRegs:$Mu2), 9453"$Rdd32 = memd($Rx32++#$Ii:circ($Mu2))", 9454tc_e93a3d71, TypeLD>, Enc_b05839 { 9455let Inst{12-9} = 0b0000; 9456let Inst{31-21} = 0b10011001110; 9457let addrMode = PostInc; 9458let accessSize = DoubleWordAccess; 9459let mayLoad = 1; 9460let Uses = [CS]; 9461let Constraints = "$Rx32 = $Rx32in"; 9462} 9463def L2_loadrd_pcr : HInst< 9464(outs DoubleRegs:$Rdd32, IntRegs:$Rx32), 9465(ins IntRegs:$Rx32in, ModRegs:$Mu2), 9466"$Rdd32 = memd($Rx32++I:circ($Mu2))", 9467tc_44d3da28, TypeLD>, Enc_7eee72 { 9468let Inst{12-5} = 0b00010000; 9469let Inst{31-21} = 0b10011001110; 9470let addrMode = PostInc; 9471let accessSize = DoubleWordAccess; 9472let mayLoad = 1; 9473let Uses = [CS]; 9474let Constraints = "$Rx32 = $Rx32in"; 9475} 9476def L2_loadrd_pi : HInst< 9477(outs DoubleRegs:$Rdd32, IntRegs:$Rx32), 9478(ins IntRegs:$Rx32in, s4_3Imm:$Ii), 9479"$Rdd32 = memd($Rx32++#$Ii)", 9480tc_44d3da28, TypeLD>, Enc_5bdd42, PredNewRel, PostInc_BaseImm { 9481let Inst{13-9} = 0b00000; 9482let Inst{31-21} = 0b10011011110; 9483let addrMode = PostInc; 9484let accessSize = DoubleWordAccess; 9485let mayLoad = 1; 9486let CextOpcode = "L2_loadrd"; 9487let BaseOpcode = "L2_loadrd_pi"; 9488let isPredicable = 1; 9489let Constraints = "$Rx32 = $Rx32in"; 9490} 9491def L2_loadrd_pr : HInst< 9492(outs DoubleRegs:$Rdd32, IntRegs:$Rx32), 9493(ins IntRegs:$Rx32in, ModRegs:$Mu2), 9494"$Rdd32 = memd($Rx32++$Mu2)", 9495tc_44d3da28, TypeLD>, Enc_7eee72 { 9496let Inst{12-5} = 0b00000000; 9497let Inst{31-21} = 0b10011101110; 9498let addrMode = PostInc; 9499let accessSize = DoubleWordAccess; 9500let mayLoad = 1; 9501let Constraints = "$Rx32 = $Rx32in"; 9502} 9503def L2_loadrd_zomap : HInst< 9504(outs DoubleRegs:$Rdd32), 9505(ins IntRegs:$Rs32), 9506"$Rdd32 = memd($Rs32)", 9507tc_17e0d2cd, TypeMAPPING> { 9508let isPseudo = 1; 9509let isCodeGenOnly = 1; 9510} 9511def L2_loadrdgp : HInst< 9512(outs DoubleRegs:$Rdd32), 9513(ins u29_3Imm:$Ii), 9514"$Rdd32 = memd(gp+#$Ii)", 9515tc_c4db48cb, TypeV2LDST>, Enc_509701, AddrModeRel { 9516let Inst{24-21} = 0b1110; 9517let Inst{31-27} = 0b01001; 9518let accessSize = DoubleWordAccess; 9519let mayLoad = 1; 9520let Uses = [GP]; 9521let BaseOpcode = "L4_loadrd_abs"; 9522let isPredicable = 1; 9523let opExtendable = 1; 9524let isExtentSigned = 0; 9525let opExtentBits = 19; 9526let opExtentAlign = 3; 9527} 9528def L2_loadrh_io : HInst< 9529(outs IntRegs:$Rd32), 9530(ins IntRegs:$Rs32, s31_1Imm:$Ii), 9531"$Rd32 = memh($Rs32+#$Ii)", 9532tc_17e0d2cd, TypeLD>, Enc_de0214, AddrModeRel, PostInc_BaseImm { 9533let Inst{24-21} = 0b1010; 9534let Inst{31-27} = 0b10010; 9535let hasNewValue = 1; 9536let opNewValue = 0; 9537let addrMode = BaseImmOffset; 9538let accessSize = HalfWordAccess; 9539let mayLoad = 1; 9540let CextOpcode = "L2_loadrh"; 9541let BaseOpcode = "L2_loadrh_io"; 9542let isPredicable = 1; 9543let isExtendable = 1; 9544let opExtendable = 2; 9545let isExtentSigned = 1; 9546let opExtentBits = 12; 9547let opExtentAlign = 1; 9548} 9549def L2_loadrh_pbr : HInst< 9550(outs IntRegs:$Rd32, IntRegs:$Rx32), 9551(ins IntRegs:$Rx32in, ModRegs:$Mu2), 9552"$Rd32 = memh($Rx32++$Mu2:brev)", 9553tc_44d3da28, TypeLD>, Enc_74d4e5 { 9554let Inst{12-5} = 0b00000000; 9555let Inst{31-21} = 0b10011111010; 9556let hasNewValue = 1; 9557let opNewValue = 0; 9558let addrMode = PostInc; 9559let accessSize = HalfWordAccess; 9560let mayLoad = 1; 9561let Constraints = "$Rx32 = $Rx32in"; 9562} 9563def L2_loadrh_pci : HInst< 9564(outs IntRegs:$Rd32, IntRegs:$Rx32), 9565(ins IntRegs:$Rx32in, s4_1Imm:$Ii, ModRegs:$Mu2), 9566"$Rd32 = memh($Rx32++#$Ii:circ($Mu2))", 9567tc_e93a3d71, TypeLD>, Enc_e83554 { 9568let Inst{12-9} = 0b0000; 9569let Inst{31-21} = 0b10011001010; 9570let hasNewValue = 1; 9571let opNewValue = 0; 9572let addrMode = PostInc; 9573let accessSize = HalfWordAccess; 9574let mayLoad = 1; 9575let Uses = [CS]; 9576let Constraints = "$Rx32 = $Rx32in"; 9577} 9578def L2_loadrh_pcr : HInst< 9579(outs IntRegs:$Rd32, IntRegs:$Rx32), 9580(ins IntRegs:$Rx32in, ModRegs:$Mu2), 9581"$Rd32 = memh($Rx32++I:circ($Mu2))", 9582tc_44d3da28, TypeLD>, Enc_74d4e5 { 9583let Inst{12-5} = 0b00010000; 9584let Inst{31-21} = 0b10011001010; 9585let hasNewValue = 1; 9586let opNewValue = 0; 9587let addrMode = PostInc; 9588let accessSize = HalfWordAccess; 9589let mayLoad = 1; 9590let Uses = [CS]; 9591let Constraints = "$Rx32 = $Rx32in"; 9592} 9593def L2_loadrh_pi : HInst< 9594(outs IntRegs:$Rd32, IntRegs:$Rx32), 9595(ins IntRegs:$Rx32in, s4_1Imm:$Ii), 9596"$Rd32 = memh($Rx32++#$Ii)", 9597tc_44d3da28, TypeLD>, Enc_152467, PredNewRel, PostInc_BaseImm { 9598let Inst{13-9} = 0b00000; 9599let Inst{31-21} = 0b10011011010; 9600let hasNewValue = 1; 9601let opNewValue = 0; 9602let addrMode = PostInc; 9603let accessSize = HalfWordAccess; 9604let mayLoad = 1; 9605let CextOpcode = "L2_loadrh"; 9606let BaseOpcode = "L2_loadrh_pi"; 9607let isPredicable = 1; 9608let Constraints = "$Rx32 = $Rx32in"; 9609} 9610def L2_loadrh_pr : HInst< 9611(outs IntRegs:$Rd32, IntRegs:$Rx32), 9612(ins IntRegs:$Rx32in, ModRegs:$Mu2), 9613"$Rd32 = memh($Rx32++$Mu2)", 9614tc_44d3da28, TypeLD>, Enc_74d4e5 { 9615let Inst{12-5} = 0b00000000; 9616let Inst{31-21} = 0b10011101010; 9617let hasNewValue = 1; 9618let opNewValue = 0; 9619let addrMode = PostInc; 9620let accessSize = HalfWordAccess; 9621let mayLoad = 1; 9622let Constraints = "$Rx32 = $Rx32in"; 9623} 9624def L2_loadrh_zomap : HInst< 9625(outs IntRegs:$Rd32), 9626(ins IntRegs:$Rs32), 9627"$Rd32 = memh($Rs32)", 9628tc_17e0d2cd, TypeMAPPING> { 9629let hasNewValue = 1; 9630let opNewValue = 0; 9631let isPseudo = 1; 9632let isCodeGenOnly = 1; 9633} 9634def L2_loadrhgp : HInst< 9635(outs IntRegs:$Rd32), 9636(ins u31_1Imm:$Ii), 9637"$Rd32 = memh(gp+#$Ii)", 9638tc_c4db48cb, TypeV2LDST>, Enc_8df4be, AddrModeRel { 9639let Inst{24-21} = 0b1010; 9640let Inst{31-27} = 0b01001; 9641let hasNewValue = 1; 9642let opNewValue = 0; 9643let accessSize = HalfWordAccess; 9644let mayLoad = 1; 9645let Uses = [GP]; 9646let BaseOpcode = "L4_loadrh_abs"; 9647let isPredicable = 1; 9648let opExtendable = 1; 9649let isExtentSigned = 0; 9650let opExtentBits = 17; 9651let opExtentAlign = 1; 9652} 9653def L2_loadri_io : HInst< 9654(outs IntRegs:$Rd32), 9655(ins IntRegs:$Rs32, s30_2Imm:$Ii), 9656"$Rd32 = memw($Rs32+#$Ii)", 9657tc_17e0d2cd, TypeLD>, Enc_2a3787, AddrModeRel, PostInc_BaseImm { 9658let Inst{24-21} = 0b1100; 9659let Inst{31-27} = 0b10010; 9660let hasNewValue = 1; 9661let opNewValue = 0; 9662let addrMode = BaseImmOffset; 9663let accessSize = WordAccess; 9664let mayLoad = 1; 9665let CextOpcode = "L2_loadri"; 9666let BaseOpcode = "L2_loadri_io"; 9667let isPredicable = 1; 9668let isExtendable = 1; 9669let opExtendable = 2; 9670let isExtentSigned = 1; 9671let opExtentBits = 13; 9672let opExtentAlign = 2; 9673} 9674def L2_loadri_pbr : HInst< 9675(outs IntRegs:$Rd32, IntRegs:$Rx32), 9676(ins IntRegs:$Rx32in, ModRegs:$Mu2), 9677"$Rd32 = memw($Rx32++$Mu2:brev)", 9678tc_44d3da28, TypeLD>, Enc_74d4e5 { 9679let Inst{12-5} = 0b00000000; 9680let Inst{31-21} = 0b10011111100; 9681let hasNewValue = 1; 9682let opNewValue = 0; 9683let addrMode = PostInc; 9684let accessSize = WordAccess; 9685let mayLoad = 1; 9686let Constraints = "$Rx32 = $Rx32in"; 9687} 9688def L2_loadri_pci : HInst< 9689(outs IntRegs:$Rd32, IntRegs:$Rx32), 9690(ins IntRegs:$Rx32in, s4_2Imm:$Ii, ModRegs:$Mu2), 9691"$Rd32 = memw($Rx32++#$Ii:circ($Mu2))", 9692tc_e93a3d71, TypeLD>, Enc_27fd0e { 9693let Inst{12-9} = 0b0000; 9694let Inst{31-21} = 0b10011001100; 9695let hasNewValue = 1; 9696let opNewValue = 0; 9697let addrMode = PostInc; 9698let accessSize = WordAccess; 9699let mayLoad = 1; 9700let Uses = [CS]; 9701let Constraints = "$Rx32 = $Rx32in"; 9702} 9703def L2_loadri_pcr : HInst< 9704(outs IntRegs:$Rd32, IntRegs:$Rx32), 9705(ins IntRegs:$Rx32in, ModRegs:$Mu2), 9706"$Rd32 = memw($Rx32++I:circ($Mu2))", 9707tc_44d3da28, TypeLD>, Enc_74d4e5 { 9708let Inst{12-5} = 0b00010000; 9709let Inst{31-21} = 0b10011001100; 9710let hasNewValue = 1; 9711let opNewValue = 0; 9712let addrMode = PostInc; 9713let accessSize = WordAccess; 9714let mayLoad = 1; 9715let Uses = [CS]; 9716let Constraints = "$Rx32 = $Rx32in"; 9717} 9718def L2_loadri_pi : HInst< 9719(outs IntRegs:$Rd32, IntRegs:$Rx32), 9720(ins IntRegs:$Rx32in, s4_2Imm:$Ii), 9721"$Rd32 = memw($Rx32++#$Ii)", 9722tc_44d3da28, TypeLD>, Enc_3d920a, PredNewRel, PostInc_BaseImm { 9723let Inst{13-9} = 0b00000; 9724let Inst{31-21} = 0b10011011100; 9725let hasNewValue = 1; 9726let opNewValue = 0; 9727let addrMode = PostInc; 9728let accessSize = WordAccess; 9729let mayLoad = 1; 9730let CextOpcode = "L2_loadri"; 9731let BaseOpcode = "L2_loadri_pi"; 9732let isPredicable = 1; 9733let Constraints = "$Rx32 = $Rx32in"; 9734} 9735def L2_loadri_pr : HInst< 9736(outs IntRegs:$Rd32, IntRegs:$Rx32), 9737(ins IntRegs:$Rx32in, ModRegs:$Mu2), 9738"$Rd32 = memw($Rx32++$Mu2)", 9739tc_44d3da28, TypeLD>, Enc_74d4e5 { 9740let Inst{12-5} = 0b00000000; 9741let Inst{31-21} = 0b10011101100; 9742let hasNewValue = 1; 9743let opNewValue = 0; 9744let addrMode = PostInc; 9745let accessSize = WordAccess; 9746let mayLoad = 1; 9747let Constraints = "$Rx32 = $Rx32in"; 9748} 9749def L2_loadri_zomap : HInst< 9750(outs IntRegs:$Rd32), 9751(ins IntRegs:$Rs32), 9752"$Rd32 = memw($Rs32)", 9753tc_17e0d2cd, TypeMAPPING> { 9754let hasNewValue = 1; 9755let opNewValue = 0; 9756let isPseudo = 1; 9757let isCodeGenOnly = 1; 9758} 9759def L2_loadrigp : HInst< 9760(outs IntRegs:$Rd32), 9761(ins u30_2Imm:$Ii), 9762"$Rd32 = memw(gp+#$Ii)", 9763tc_c4db48cb, TypeV2LDST>, Enc_4f4ed7, AddrModeRel { 9764let Inst{24-21} = 0b1100; 9765let Inst{31-27} = 0b01001; 9766let hasNewValue = 1; 9767let opNewValue = 0; 9768let accessSize = WordAccess; 9769let mayLoad = 1; 9770let Uses = [GP]; 9771let BaseOpcode = "L4_loadri_abs"; 9772let isPredicable = 1; 9773let opExtendable = 1; 9774let isExtentSigned = 0; 9775let opExtentBits = 18; 9776let opExtentAlign = 2; 9777} 9778def L2_loadrub_io : HInst< 9779(outs IntRegs:$Rd32), 9780(ins IntRegs:$Rs32, s32_0Imm:$Ii), 9781"$Rd32 = memub($Rs32+#$Ii)", 9782tc_17e0d2cd, TypeLD>, Enc_211aaa, AddrModeRel, PostInc_BaseImm { 9783let Inst{24-21} = 0b1001; 9784let Inst{31-27} = 0b10010; 9785let hasNewValue = 1; 9786let opNewValue = 0; 9787let addrMode = BaseImmOffset; 9788let accessSize = ByteAccess; 9789let mayLoad = 1; 9790let CextOpcode = "L2_loadrub"; 9791let BaseOpcode = "L2_loadrub_io"; 9792let isPredicable = 1; 9793let isExtendable = 1; 9794let opExtendable = 2; 9795let isExtentSigned = 1; 9796let opExtentBits = 11; 9797let opExtentAlign = 0; 9798} 9799def L2_loadrub_pbr : HInst< 9800(outs IntRegs:$Rd32, IntRegs:$Rx32), 9801(ins IntRegs:$Rx32in, ModRegs:$Mu2), 9802"$Rd32 = memub($Rx32++$Mu2:brev)", 9803tc_44d3da28, TypeLD>, Enc_74d4e5 { 9804let Inst{12-5} = 0b00000000; 9805let Inst{31-21} = 0b10011111001; 9806let hasNewValue = 1; 9807let opNewValue = 0; 9808let addrMode = PostInc; 9809let accessSize = ByteAccess; 9810let mayLoad = 1; 9811let Constraints = "$Rx32 = $Rx32in"; 9812} 9813def L2_loadrub_pci : HInst< 9814(outs IntRegs:$Rd32, IntRegs:$Rx32), 9815(ins IntRegs:$Rx32in, s4_0Imm:$Ii, ModRegs:$Mu2), 9816"$Rd32 = memub($Rx32++#$Ii:circ($Mu2))", 9817tc_e93a3d71, TypeLD>, Enc_e0a47a { 9818let Inst{12-9} = 0b0000; 9819let Inst{31-21} = 0b10011001001; 9820let hasNewValue = 1; 9821let opNewValue = 0; 9822let addrMode = PostInc; 9823let accessSize = ByteAccess; 9824let mayLoad = 1; 9825let Uses = [CS]; 9826let Constraints = "$Rx32 = $Rx32in"; 9827} 9828def L2_loadrub_pcr : HInst< 9829(outs IntRegs:$Rd32, IntRegs:$Rx32), 9830(ins IntRegs:$Rx32in, ModRegs:$Mu2), 9831"$Rd32 = memub($Rx32++I:circ($Mu2))", 9832tc_44d3da28, TypeLD>, Enc_74d4e5 { 9833let Inst{12-5} = 0b00010000; 9834let Inst{31-21} = 0b10011001001; 9835let hasNewValue = 1; 9836let opNewValue = 0; 9837let addrMode = PostInc; 9838let accessSize = ByteAccess; 9839let mayLoad = 1; 9840let Uses = [CS]; 9841let Constraints = "$Rx32 = $Rx32in"; 9842} 9843def L2_loadrub_pi : HInst< 9844(outs IntRegs:$Rd32, IntRegs:$Rx32), 9845(ins IntRegs:$Rx32in, s4_0Imm:$Ii), 9846"$Rd32 = memub($Rx32++#$Ii)", 9847tc_44d3da28, TypeLD>, Enc_222336, PredNewRel, PostInc_BaseImm { 9848let Inst{13-9} = 0b00000; 9849let Inst{31-21} = 0b10011011001; 9850let hasNewValue = 1; 9851let opNewValue = 0; 9852let addrMode = PostInc; 9853let accessSize = ByteAccess; 9854let mayLoad = 1; 9855let CextOpcode = "L2_loadrub"; 9856let BaseOpcode = "L2_loadrub_pi"; 9857let isPredicable = 1; 9858let Constraints = "$Rx32 = $Rx32in"; 9859} 9860def L2_loadrub_pr : HInst< 9861(outs IntRegs:$Rd32, IntRegs:$Rx32), 9862(ins IntRegs:$Rx32in, ModRegs:$Mu2), 9863"$Rd32 = memub($Rx32++$Mu2)", 9864tc_44d3da28, TypeLD>, Enc_74d4e5 { 9865let Inst{12-5} = 0b00000000; 9866let Inst{31-21} = 0b10011101001; 9867let hasNewValue = 1; 9868let opNewValue = 0; 9869let addrMode = PostInc; 9870let accessSize = ByteAccess; 9871let mayLoad = 1; 9872let Constraints = "$Rx32 = $Rx32in"; 9873} 9874def L2_loadrub_zomap : HInst< 9875(outs IntRegs:$Rd32), 9876(ins IntRegs:$Rs32), 9877"$Rd32 = memub($Rs32)", 9878tc_17e0d2cd, TypeMAPPING> { 9879let hasNewValue = 1; 9880let opNewValue = 0; 9881let isPseudo = 1; 9882let isCodeGenOnly = 1; 9883} 9884def L2_loadrubgp : HInst< 9885(outs IntRegs:$Rd32), 9886(ins u32_0Imm:$Ii), 9887"$Rd32 = memub(gp+#$Ii)", 9888tc_c4db48cb, TypeV2LDST>, Enc_25bef0, AddrModeRel { 9889let Inst{24-21} = 0b1001; 9890let Inst{31-27} = 0b01001; 9891let hasNewValue = 1; 9892let opNewValue = 0; 9893let accessSize = ByteAccess; 9894let mayLoad = 1; 9895let Uses = [GP]; 9896let BaseOpcode = "L4_loadrub_abs"; 9897let isPredicable = 1; 9898let opExtendable = 1; 9899let isExtentSigned = 0; 9900let opExtentBits = 16; 9901let opExtentAlign = 0; 9902} 9903def L2_loadruh_io : HInst< 9904(outs IntRegs:$Rd32), 9905(ins IntRegs:$Rs32, s31_1Imm:$Ii), 9906"$Rd32 = memuh($Rs32+#$Ii)", 9907tc_17e0d2cd, TypeLD>, Enc_de0214, AddrModeRel, PostInc_BaseImm { 9908let Inst{24-21} = 0b1011; 9909let Inst{31-27} = 0b10010; 9910let hasNewValue = 1; 9911let opNewValue = 0; 9912let addrMode = BaseImmOffset; 9913let accessSize = HalfWordAccess; 9914let mayLoad = 1; 9915let CextOpcode = "L2_loadruh"; 9916let BaseOpcode = "L2_loadruh_io"; 9917let isPredicable = 1; 9918let isExtendable = 1; 9919let opExtendable = 2; 9920let isExtentSigned = 1; 9921let opExtentBits = 12; 9922let opExtentAlign = 1; 9923} 9924def L2_loadruh_pbr : HInst< 9925(outs IntRegs:$Rd32, IntRegs:$Rx32), 9926(ins IntRegs:$Rx32in, ModRegs:$Mu2), 9927"$Rd32 = memuh($Rx32++$Mu2:brev)", 9928tc_44d3da28, TypeLD>, Enc_74d4e5 { 9929let Inst{12-5} = 0b00000000; 9930let Inst{31-21} = 0b10011111011; 9931let hasNewValue = 1; 9932let opNewValue = 0; 9933let addrMode = PostInc; 9934let accessSize = HalfWordAccess; 9935let mayLoad = 1; 9936let Constraints = "$Rx32 = $Rx32in"; 9937} 9938def L2_loadruh_pci : HInst< 9939(outs IntRegs:$Rd32, IntRegs:$Rx32), 9940(ins IntRegs:$Rx32in, s4_1Imm:$Ii, ModRegs:$Mu2), 9941"$Rd32 = memuh($Rx32++#$Ii:circ($Mu2))", 9942tc_e93a3d71, TypeLD>, Enc_e83554 { 9943let Inst{12-9} = 0b0000; 9944let Inst{31-21} = 0b10011001011; 9945let hasNewValue = 1; 9946let opNewValue = 0; 9947let addrMode = PostInc; 9948let accessSize = HalfWordAccess; 9949let mayLoad = 1; 9950let Uses = [CS]; 9951let Constraints = "$Rx32 = $Rx32in"; 9952} 9953def L2_loadruh_pcr : HInst< 9954(outs IntRegs:$Rd32, IntRegs:$Rx32), 9955(ins IntRegs:$Rx32in, ModRegs:$Mu2), 9956"$Rd32 = memuh($Rx32++I:circ($Mu2))", 9957tc_44d3da28, TypeLD>, Enc_74d4e5 { 9958let Inst{12-5} = 0b00010000; 9959let Inst{31-21} = 0b10011001011; 9960let hasNewValue = 1; 9961let opNewValue = 0; 9962let addrMode = PostInc; 9963let accessSize = HalfWordAccess; 9964let mayLoad = 1; 9965let Uses = [CS]; 9966let Constraints = "$Rx32 = $Rx32in"; 9967} 9968def L2_loadruh_pi : HInst< 9969(outs IntRegs:$Rd32, IntRegs:$Rx32), 9970(ins IntRegs:$Rx32in, s4_1Imm:$Ii), 9971"$Rd32 = memuh($Rx32++#$Ii)", 9972tc_44d3da28, TypeLD>, Enc_152467, PredNewRel, PostInc_BaseImm { 9973let Inst{13-9} = 0b00000; 9974let Inst{31-21} = 0b10011011011; 9975let hasNewValue = 1; 9976let opNewValue = 0; 9977let addrMode = PostInc; 9978let accessSize = HalfWordAccess; 9979let mayLoad = 1; 9980let CextOpcode = "L2_loadruh"; 9981let BaseOpcode = "L2_loadruh_pi"; 9982let isPredicable = 1; 9983let Constraints = "$Rx32 = $Rx32in"; 9984} 9985def L2_loadruh_pr : HInst< 9986(outs IntRegs:$Rd32, IntRegs:$Rx32), 9987(ins IntRegs:$Rx32in, ModRegs:$Mu2), 9988"$Rd32 = memuh($Rx32++$Mu2)", 9989tc_44d3da28, TypeLD>, Enc_74d4e5 { 9990let Inst{12-5} = 0b00000000; 9991let Inst{31-21} = 0b10011101011; 9992let hasNewValue = 1; 9993let opNewValue = 0; 9994let addrMode = PostInc; 9995let accessSize = HalfWordAccess; 9996let mayLoad = 1; 9997let Constraints = "$Rx32 = $Rx32in"; 9998} 9999def L2_loadruh_zomap : HInst< 10000(outs IntRegs:$Rd32), 10001(ins IntRegs:$Rs32), 10002"$Rd32 = memuh($Rs32)", 10003tc_17e0d2cd, TypeMAPPING> { 10004let hasNewValue = 1; 10005let opNewValue = 0; 10006let isPseudo = 1; 10007let isCodeGenOnly = 1; 10008} 10009def L2_loadruhgp : HInst< 10010(outs IntRegs:$Rd32), 10011(ins u31_1Imm:$Ii), 10012"$Rd32 = memuh(gp+#$Ii)", 10013tc_c4db48cb, TypeV2LDST>, Enc_8df4be, AddrModeRel { 10014let Inst{24-21} = 0b1011; 10015let Inst{31-27} = 0b01001; 10016let hasNewValue = 1; 10017let opNewValue = 0; 10018let accessSize = HalfWordAccess; 10019let mayLoad = 1; 10020let Uses = [GP]; 10021let BaseOpcode = "L4_loadruh_abs"; 10022let isPredicable = 1; 10023let opExtendable = 1; 10024let isExtentSigned = 0; 10025let opExtentBits = 17; 10026let opExtentAlign = 1; 10027} 10028def L2_loadw_locked : HInst< 10029(outs IntRegs:$Rd32), 10030(ins IntRegs:$Rs32), 10031"$Rd32 = memw_locked($Rs32)", 10032tc_b43e7930, TypeLD>, Enc_5e2823 { 10033let Inst{13-5} = 0b000000000; 10034let Inst{31-21} = 0b10010010000; 10035let hasNewValue = 1; 10036let opNewValue = 0; 10037let accessSize = WordAccess; 10038let mayLoad = 1; 10039let isSoloAX = 1; 10040} 10041def L2_ploadrbf_io : HInst< 10042(outs IntRegs:$Rd32), 10043(ins PredRegs:$Pt4, IntRegs:$Rs32, u32_0Imm:$Ii), 10044"if (!$Pt4) $Rd32 = memb($Rs32+#$Ii)", 10045tc_5ef37dc4, TypeV2LDST>, Enc_a21d47, AddrModeRel { 10046let Inst{13-13} = 0b0; 10047let Inst{31-21} = 0b01000101000; 10048let isPredicated = 1; 10049let isPredicatedFalse = 1; 10050let hasNewValue = 1; 10051let opNewValue = 0; 10052let addrMode = BaseImmOffset; 10053let accessSize = ByteAccess; 10054let mayLoad = 1; 10055let CextOpcode = "L2_loadrb"; 10056let BaseOpcode = "L2_loadrb_io"; 10057let isExtendable = 1; 10058let opExtendable = 3; 10059let isExtentSigned = 0; 10060let opExtentBits = 6; 10061let opExtentAlign = 0; 10062} 10063def L2_ploadrbf_pi : HInst< 10064(outs IntRegs:$Rd32, IntRegs:$Rx32), 10065(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_0Imm:$Ii), 10066"if (!$Pt4) $Rd32 = memb($Rx32++#$Ii)", 10067tc_3c76b0ff, TypeLD>, Enc_f4413a, PredNewRel { 10068let Inst{13-11} = 0b101; 10069let Inst{31-21} = 0b10011011000; 10070let isPredicated = 1; 10071let isPredicatedFalse = 1; 10072let hasNewValue = 1; 10073let opNewValue = 0; 10074let addrMode = PostInc; 10075let accessSize = ByteAccess; 10076let mayLoad = 1; 10077let BaseOpcode = "L2_loadrb_pi"; 10078let Constraints = "$Rx32 = $Rx32in"; 10079} 10080def L2_ploadrbf_zomap : HInst< 10081(outs IntRegs:$Rd32), 10082(ins PredRegs:$Pt4, IntRegs:$Rs32), 10083"if (!$Pt4) $Rd32 = memb($Rs32)", 10084tc_5ef37dc4, TypeMAPPING> { 10085let hasNewValue = 1; 10086let opNewValue = 0; 10087let isPseudo = 1; 10088let isCodeGenOnly = 1; 10089} 10090def L2_ploadrbfnew_io : HInst< 10091(outs IntRegs:$Rd32), 10092(ins PredRegs:$Pt4, IntRegs:$Rs32, u32_0Imm:$Ii), 10093"if (!$Pt4.new) $Rd32 = memb($Rs32+#$Ii)", 10094tc_44d3da28, TypeV2LDST>, Enc_a21d47, AddrModeRel { 10095let Inst{13-13} = 0b0; 10096let Inst{31-21} = 0b01000111000; 10097let isPredicated = 1; 10098let isPredicatedFalse = 1; 10099let hasNewValue = 1; 10100let opNewValue = 0; 10101let addrMode = BaseImmOffset; 10102let accessSize = ByteAccess; 10103let isPredicatedNew = 1; 10104let mayLoad = 1; 10105let CextOpcode = "L2_loadrb"; 10106let BaseOpcode = "L2_loadrb_io"; 10107let isExtendable = 1; 10108let opExtendable = 3; 10109let isExtentSigned = 0; 10110let opExtentBits = 6; 10111let opExtentAlign = 0; 10112} 10113def L2_ploadrbfnew_pi : HInst< 10114(outs IntRegs:$Rd32, IntRegs:$Rx32), 10115(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_0Imm:$Ii), 10116"if (!$Pt4.new) $Rd32 = memb($Rx32++#$Ii)", 10117tc_e9f3243f, TypeLD>, Enc_f4413a, PredNewRel { 10118let Inst{13-11} = 0b111; 10119let Inst{31-21} = 0b10011011000; 10120let isPredicated = 1; 10121let isPredicatedFalse = 1; 10122let hasNewValue = 1; 10123let opNewValue = 0; 10124let addrMode = PostInc; 10125let accessSize = ByteAccess; 10126let isPredicatedNew = 1; 10127let mayLoad = 1; 10128let BaseOpcode = "L2_loadrb_pi"; 10129let Constraints = "$Rx32 = $Rx32in"; 10130} 10131def L2_ploadrbfnew_zomap : HInst< 10132(outs IntRegs:$Rd32), 10133(ins PredRegs:$Pt4, IntRegs:$Rs32), 10134"if (!$Pt4.new) $Rd32 = memb($Rs32)", 10135tc_44d3da28, TypeMAPPING> { 10136let hasNewValue = 1; 10137let opNewValue = 0; 10138let isPseudo = 1; 10139let isCodeGenOnly = 1; 10140} 10141def L2_ploadrbt_io : HInst< 10142(outs IntRegs:$Rd32), 10143(ins PredRegs:$Pt4, IntRegs:$Rs32, u32_0Imm:$Ii), 10144"if ($Pt4) $Rd32 = memb($Rs32+#$Ii)", 10145tc_5ef37dc4, TypeV2LDST>, Enc_a21d47, AddrModeRel { 10146let Inst{13-13} = 0b0; 10147let Inst{31-21} = 0b01000001000; 10148let isPredicated = 1; 10149let hasNewValue = 1; 10150let opNewValue = 0; 10151let addrMode = BaseImmOffset; 10152let accessSize = ByteAccess; 10153let mayLoad = 1; 10154let CextOpcode = "L2_loadrb"; 10155let BaseOpcode = "L2_loadrb_io"; 10156let isExtendable = 1; 10157let opExtendable = 3; 10158let isExtentSigned = 0; 10159let opExtentBits = 6; 10160let opExtentAlign = 0; 10161} 10162def L2_ploadrbt_pi : HInst< 10163(outs IntRegs:$Rd32, IntRegs:$Rx32), 10164(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_0Imm:$Ii), 10165"if ($Pt4) $Rd32 = memb($Rx32++#$Ii)", 10166tc_3c76b0ff, TypeLD>, Enc_f4413a, PredNewRel { 10167let Inst{13-11} = 0b100; 10168let Inst{31-21} = 0b10011011000; 10169let isPredicated = 1; 10170let hasNewValue = 1; 10171let opNewValue = 0; 10172let addrMode = PostInc; 10173let accessSize = ByteAccess; 10174let mayLoad = 1; 10175let BaseOpcode = "L2_loadrb_pi"; 10176let Constraints = "$Rx32 = $Rx32in"; 10177} 10178def L2_ploadrbt_zomap : HInst< 10179(outs IntRegs:$Rd32), 10180(ins PredRegs:$Pt4, IntRegs:$Rs32), 10181"if ($Pt4) $Rd32 = memb($Rs32)", 10182tc_5ef37dc4, TypeMAPPING> { 10183let hasNewValue = 1; 10184let opNewValue = 0; 10185let isPseudo = 1; 10186let isCodeGenOnly = 1; 10187} 10188def L2_ploadrbtnew_io : HInst< 10189(outs IntRegs:$Rd32), 10190(ins PredRegs:$Pt4, IntRegs:$Rs32, u32_0Imm:$Ii), 10191"if ($Pt4.new) $Rd32 = memb($Rs32+#$Ii)", 10192tc_44d3da28, TypeV2LDST>, Enc_a21d47, AddrModeRel { 10193let Inst{13-13} = 0b0; 10194let Inst{31-21} = 0b01000011000; 10195let isPredicated = 1; 10196let hasNewValue = 1; 10197let opNewValue = 0; 10198let addrMode = BaseImmOffset; 10199let accessSize = ByteAccess; 10200let isPredicatedNew = 1; 10201let mayLoad = 1; 10202let CextOpcode = "L2_loadrb"; 10203let BaseOpcode = "L2_loadrb_io"; 10204let isExtendable = 1; 10205let opExtendable = 3; 10206let isExtentSigned = 0; 10207let opExtentBits = 6; 10208let opExtentAlign = 0; 10209} 10210def L2_ploadrbtnew_pi : HInst< 10211(outs IntRegs:$Rd32, IntRegs:$Rx32), 10212(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_0Imm:$Ii), 10213"if ($Pt4.new) $Rd32 = memb($Rx32++#$Ii)", 10214tc_e9f3243f, TypeLD>, Enc_f4413a, PredNewRel { 10215let Inst{13-11} = 0b110; 10216let Inst{31-21} = 0b10011011000; 10217let isPredicated = 1; 10218let hasNewValue = 1; 10219let opNewValue = 0; 10220let addrMode = PostInc; 10221let accessSize = ByteAccess; 10222let isPredicatedNew = 1; 10223let mayLoad = 1; 10224let BaseOpcode = "L2_loadrb_pi"; 10225let Constraints = "$Rx32 = $Rx32in"; 10226} 10227def L2_ploadrbtnew_zomap : HInst< 10228(outs IntRegs:$Rd32), 10229(ins PredRegs:$Pt4, IntRegs:$Rs32), 10230"if ($Pt4.new) $Rd32 = memb($Rs32)", 10231tc_44d3da28, TypeMAPPING> { 10232let hasNewValue = 1; 10233let opNewValue = 0; 10234let isPseudo = 1; 10235let isCodeGenOnly = 1; 10236} 10237def L2_ploadrdf_io : HInst< 10238(outs DoubleRegs:$Rdd32), 10239(ins PredRegs:$Pt4, IntRegs:$Rs32, u29_3Imm:$Ii), 10240"if (!$Pt4) $Rdd32 = memd($Rs32+#$Ii)", 10241tc_5ef37dc4, TypeV2LDST>, Enc_acd6ed, AddrModeRel { 10242let Inst{13-13} = 0b0; 10243let Inst{31-21} = 0b01000101110; 10244let isPredicated = 1; 10245let isPredicatedFalse = 1; 10246let addrMode = BaseImmOffset; 10247let accessSize = DoubleWordAccess; 10248let mayLoad = 1; 10249let CextOpcode = "L2_loadrd"; 10250let BaseOpcode = "L2_loadrd_io"; 10251let isExtendable = 1; 10252let opExtendable = 3; 10253let isExtentSigned = 0; 10254let opExtentBits = 9; 10255let opExtentAlign = 3; 10256} 10257def L2_ploadrdf_pi : HInst< 10258(outs DoubleRegs:$Rdd32, IntRegs:$Rx32), 10259(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_3Imm:$Ii), 10260"if (!$Pt4) $Rdd32 = memd($Rx32++#$Ii)", 10261tc_3c76b0ff, TypeLD>, Enc_9d1247, PredNewRel { 10262let Inst{13-11} = 0b101; 10263let Inst{31-21} = 0b10011011110; 10264let isPredicated = 1; 10265let isPredicatedFalse = 1; 10266let addrMode = PostInc; 10267let accessSize = DoubleWordAccess; 10268let mayLoad = 1; 10269let BaseOpcode = "L2_loadrd_pi"; 10270let Constraints = "$Rx32 = $Rx32in"; 10271} 10272def L2_ploadrdf_zomap : HInst< 10273(outs DoubleRegs:$Rdd32), 10274(ins PredRegs:$Pt4, IntRegs:$Rs32), 10275"if (!$Pt4) $Rdd32 = memd($Rs32)", 10276tc_5ef37dc4, TypeMAPPING> { 10277let isPseudo = 1; 10278let isCodeGenOnly = 1; 10279} 10280def L2_ploadrdfnew_io : HInst< 10281(outs DoubleRegs:$Rdd32), 10282(ins PredRegs:$Pt4, IntRegs:$Rs32, u29_3Imm:$Ii), 10283"if (!$Pt4.new) $Rdd32 = memd($Rs32+#$Ii)", 10284tc_44d3da28, TypeV2LDST>, Enc_acd6ed, AddrModeRel { 10285let Inst{13-13} = 0b0; 10286let Inst{31-21} = 0b01000111110; 10287let isPredicated = 1; 10288let isPredicatedFalse = 1; 10289let addrMode = BaseImmOffset; 10290let accessSize = DoubleWordAccess; 10291let isPredicatedNew = 1; 10292let mayLoad = 1; 10293let CextOpcode = "L2_loadrd"; 10294let BaseOpcode = "L2_loadrd_io"; 10295let isExtendable = 1; 10296let opExtendable = 3; 10297let isExtentSigned = 0; 10298let opExtentBits = 9; 10299let opExtentAlign = 3; 10300} 10301def L2_ploadrdfnew_pi : HInst< 10302(outs DoubleRegs:$Rdd32, IntRegs:$Rx32), 10303(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_3Imm:$Ii), 10304"if (!$Pt4.new) $Rdd32 = memd($Rx32++#$Ii)", 10305tc_e9f3243f, TypeLD>, Enc_9d1247, PredNewRel { 10306let Inst{13-11} = 0b111; 10307let Inst{31-21} = 0b10011011110; 10308let isPredicated = 1; 10309let isPredicatedFalse = 1; 10310let addrMode = PostInc; 10311let accessSize = DoubleWordAccess; 10312let isPredicatedNew = 1; 10313let mayLoad = 1; 10314let BaseOpcode = "L2_loadrd_pi"; 10315let Constraints = "$Rx32 = $Rx32in"; 10316} 10317def L2_ploadrdfnew_zomap : HInst< 10318(outs DoubleRegs:$Rdd32), 10319(ins PredRegs:$Pt4, IntRegs:$Rs32), 10320"if (!$Pt4.new) $Rdd32 = memd($Rs32)", 10321tc_44d3da28, TypeMAPPING> { 10322let isPseudo = 1; 10323let isCodeGenOnly = 1; 10324} 10325def L2_ploadrdt_io : HInst< 10326(outs DoubleRegs:$Rdd32), 10327(ins PredRegs:$Pt4, IntRegs:$Rs32, u29_3Imm:$Ii), 10328"if ($Pt4) $Rdd32 = memd($Rs32+#$Ii)", 10329tc_5ef37dc4, TypeV2LDST>, Enc_acd6ed, AddrModeRel { 10330let Inst{13-13} = 0b0; 10331let Inst{31-21} = 0b01000001110; 10332let isPredicated = 1; 10333let addrMode = BaseImmOffset; 10334let accessSize = DoubleWordAccess; 10335let mayLoad = 1; 10336let CextOpcode = "L2_loadrd"; 10337let BaseOpcode = "L2_loadrd_io"; 10338let isExtendable = 1; 10339let opExtendable = 3; 10340let isExtentSigned = 0; 10341let opExtentBits = 9; 10342let opExtentAlign = 3; 10343} 10344def L2_ploadrdt_pi : HInst< 10345(outs DoubleRegs:$Rdd32, IntRegs:$Rx32), 10346(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_3Imm:$Ii), 10347"if ($Pt4) $Rdd32 = memd($Rx32++#$Ii)", 10348tc_3c76b0ff, TypeLD>, Enc_9d1247, PredNewRel { 10349let Inst{13-11} = 0b100; 10350let Inst{31-21} = 0b10011011110; 10351let isPredicated = 1; 10352let addrMode = PostInc; 10353let accessSize = DoubleWordAccess; 10354let mayLoad = 1; 10355let BaseOpcode = "L2_loadrd_pi"; 10356let Constraints = "$Rx32 = $Rx32in"; 10357} 10358def L2_ploadrdt_zomap : HInst< 10359(outs DoubleRegs:$Rdd32), 10360(ins PredRegs:$Pt4, IntRegs:$Rs32), 10361"if ($Pt4) $Rdd32 = memd($Rs32)", 10362tc_5ef37dc4, TypeMAPPING> { 10363let isPseudo = 1; 10364let isCodeGenOnly = 1; 10365} 10366def L2_ploadrdtnew_io : HInst< 10367(outs DoubleRegs:$Rdd32), 10368(ins PredRegs:$Pt4, IntRegs:$Rs32, u29_3Imm:$Ii), 10369"if ($Pt4.new) $Rdd32 = memd($Rs32+#$Ii)", 10370tc_44d3da28, TypeV2LDST>, Enc_acd6ed, AddrModeRel { 10371let Inst{13-13} = 0b0; 10372let Inst{31-21} = 0b01000011110; 10373let isPredicated = 1; 10374let addrMode = BaseImmOffset; 10375let accessSize = DoubleWordAccess; 10376let isPredicatedNew = 1; 10377let mayLoad = 1; 10378let CextOpcode = "L2_loadrd"; 10379let BaseOpcode = "L2_loadrd_io"; 10380let isExtendable = 1; 10381let opExtendable = 3; 10382let isExtentSigned = 0; 10383let opExtentBits = 9; 10384let opExtentAlign = 3; 10385} 10386def L2_ploadrdtnew_pi : HInst< 10387(outs DoubleRegs:$Rdd32, IntRegs:$Rx32), 10388(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_3Imm:$Ii), 10389"if ($Pt4.new) $Rdd32 = memd($Rx32++#$Ii)", 10390tc_e9f3243f, TypeLD>, Enc_9d1247, PredNewRel { 10391let Inst{13-11} = 0b110; 10392let Inst{31-21} = 0b10011011110; 10393let isPredicated = 1; 10394let addrMode = PostInc; 10395let accessSize = DoubleWordAccess; 10396let isPredicatedNew = 1; 10397let mayLoad = 1; 10398let BaseOpcode = "L2_loadrd_pi"; 10399let Constraints = "$Rx32 = $Rx32in"; 10400} 10401def L2_ploadrdtnew_zomap : HInst< 10402(outs DoubleRegs:$Rdd32), 10403(ins PredRegs:$Pt4, IntRegs:$Rs32), 10404"if ($Pt4.new) $Rdd32 = memd($Rs32)", 10405tc_44d3da28, TypeMAPPING> { 10406let isPseudo = 1; 10407let isCodeGenOnly = 1; 10408} 10409def L2_ploadrhf_io : HInst< 10410(outs IntRegs:$Rd32), 10411(ins PredRegs:$Pt4, IntRegs:$Rs32, u31_1Imm:$Ii), 10412"if (!$Pt4) $Rd32 = memh($Rs32+#$Ii)", 10413tc_5ef37dc4, TypeV2LDST>, Enc_a198f6, AddrModeRel { 10414let Inst{13-13} = 0b0; 10415let Inst{31-21} = 0b01000101010; 10416let isPredicated = 1; 10417let isPredicatedFalse = 1; 10418let hasNewValue = 1; 10419let opNewValue = 0; 10420let addrMode = BaseImmOffset; 10421let accessSize = HalfWordAccess; 10422let mayLoad = 1; 10423let CextOpcode = "L2_loadrh"; 10424let BaseOpcode = "L2_loadrh_io"; 10425let isExtendable = 1; 10426let opExtendable = 3; 10427let isExtentSigned = 0; 10428let opExtentBits = 7; 10429let opExtentAlign = 1; 10430} 10431def L2_ploadrhf_pi : HInst< 10432(outs IntRegs:$Rd32, IntRegs:$Rx32), 10433(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_1Imm:$Ii), 10434"if (!$Pt4) $Rd32 = memh($Rx32++#$Ii)", 10435tc_3c76b0ff, TypeLD>, Enc_733b27, PredNewRel { 10436let Inst{13-11} = 0b101; 10437let Inst{31-21} = 0b10011011010; 10438let isPredicated = 1; 10439let isPredicatedFalse = 1; 10440let hasNewValue = 1; 10441let opNewValue = 0; 10442let addrMode = PostInc; 10443let accessSize = HalfWordAccess; 10444let mayLoad = 1; 10445let BaseOpcode = "L2_loadrh_pi"; 10446let Constraints = "$Rx32 = $Rx32in"; 10447} 10448def L2_ploadrhf_zomap : HInst< 10449(outs IntRegs:$Rd32), 10450(ins PredRegs:$Pt4, IntRegs:$Rs32), 10451"if (!$Pt4) $Rd32 = memh($Rs32)", 10452tc_5ef37dc4, TypeMAPPING> { 10453let hasNewValue = 1; 10454let opNewValue = 0; 10455let isPseudo = 1; 10456let isCodeGenOnly = 1; 10457} 10458def L2_ploadrhfnew_io : HInst< 10459(outs IntRegs:$Rd32), 10460(ins PredRegs:$Pt4, IntRegs:$Rs32, u31_1Imm:$Ii), 10461"if (!$Pt4.new) $Rd32 = memh($Rs32+#$Ii)", 10462tc_44d3da28, TypeV2LDST>, Enc_a198f6, AddrModeRel { 10463let Inst{13-13} = 0b0; 10464let Inst{31-21} = 0b01000111010; 10465let isPredicated = 1; 10466let isPredicatedFalse = 1; 10467let hasNewValue = 1; 10468let opNewValue = 0; 10469let addrMode = BaseImmOffset; 10470let accessSize = HalfWordAccess; 10471let isPredicatedNew = 1; 10472let mayLoad = 1; 10473let CextOpcode = "L2_loadrh"; 10474let BaseOpcode = "L2_loadrh_io"; 10475let isExtendable = 1; 10476let opExtendable = 3; 10477let isExtentSigned = 0; 10478let opExtentBits = 7; 10479let opExtentAlign = 1; 10480} 10481def L2_ploadrhfnew_pi : HInst< 10482(outs IntRegs:$Rd32, IntRegs:$Rx32), 10483(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_1Imm:$Ii), 10484"if (!$Pt4.new) $Rd32 = memh($Rx32++#$Ii)", 10485tc_e9f3243f, TypeLD>, Enc_733b27, PredNewRel { 10486let Inst{13-11} = 0b111; 10487let Inst{31-21} = 0b10011011010; 10488let isPredicated = 1; 10489let isPredicatedFalse = 1; 10490let hasNewValue = 1; 10491let opNewValue = 0; 10492let addrMode = PostInc; 10493let accessSize = HalfWordAccess; 10494let isPredicatedNew = 1; 10495let mayLoad = 1; 10496let BaseOpcode = "L2_loadrh_pi"; 10497let Constraints = "$Rx32 = $Rx32in"; 10498} 10499def L2_ploadrhfnew_zomap : HInst< 10500(outs IntRegs:$Rd32), 10501(ins PredRegs:$Pt4, IntRegs:$Rs32), 10502"if (!$Pt4.new) $Rd32 = memh($Rs32)", 10503tc_44d3da28, TypeMAPPING> { 10504let hasNewValue = 1; 10505let opNewValue = 0; 10506let isPseudo = 1; 10507let isCodeGenOnly = 1; 10508} 10509def L2_ploadrht_io : HInst< 10510(outs IntRegs:$Rd32), 10511(ins PredRegs:$Pt4, IntRegs:$Rs32, u31_1Imm:$Ii), 10512"if ($Pt4) $Rd32 = memh($Rs32+#$Ii)", 10513tc_5ef37dc4, TypeV2LDST>, Enc_a198f6, AddrModeRel { 10514let Inst{13-13} = 0b0; 10515let Inst{31-21} = 0b01000001010; 10516let isPredicated = 1; 10517let hasNewValue = 1; 10518let opNewValue = 0; 10519let addrMode = BaseImmOffset; 10520let accessSize = HalfWordAccess; 10521let mayLoad = 1; 10522let CextOpcode = "L2_loadrh"; 10523let BaseOpcode = "L2_loadrh_io"; 10524let isExtendable = 1; 10525let opExtendable = 3; 10526let isExtentSigned = 0; 10527let opExtentBits = 7; 10528let opExtentAlign = 1; 10529} 10530def L2_ploadrht_pi : HInst< 10531(outs IntRegs:$Rd32, IntRegs:$Rx32), 10532(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_1Imm:$Ii), 10533"if ($Pt4) $Rd32 = memh($Rx32++#$Ii)", 10534tc_3c76b0ff, TypeLD>, Enc_733b27, PredNewRel { 10535let Inst{13-11} = 0b100; 10536let Inst{31-21} = 0b10011011010; 10537let isPredicated = 1; 10538let hasNewValue = 1; 10539let opNewValue = 0; 10540let addrMode = PostInc; 10541let accessSize = HalfWordAccess; 10542let mayLoad = 1; 10543let BaseOpcode = "L2_loadrh_pi"; 10544let Constraints = "$Rx32 = $Rx32in"; 10545} 10546def L2_ploadrht_zomap : HInst< 10547(outs IntRegs:$Rd32), 10548(ins PredRegs:$Pt4, IntRegs:$Rs32), 10549"if ($Pt4) $Rd32 = memh($Rs32)", 10550tc_5ef37dc4, TypeMAPPING> { 10551let hasNewValue = 1; 10552let opNewValue = 0; 10553let isPseudo = 1; 10554let isCodeGenOnly = 1; 10555} 10556def L2_ploadrhtnew_io : HInst< 10557(outs IntRegs:$Rd32), 10558(ins PredRegs:$Pt4, IntRegs:$Rs32, u31_1Imm:$Ii), 10559"if ($Pt4.new) $Rd32 = memh($Rs32+#$Ii)", 10560tc_44d3da28, TypeV2LDST>, Enc_a198f6, AddrModeRel { 10561let Inst{13-13} = 0b0; 10562let Inst{31-21} = 0b01000011010; 10563let isPredicated = 1; 10564let hasNewValue = 1; 10565let opNewValue = 0; 10566let addrMode = BaseImmOffset; 10567let accessSize = HalfWordAccess; 10568let isPredicatedNew = 1; 10569let mayLoad = 1; 10570let CextOpcode = "L2_loadrh"; 10571let BaseOpcode = "L2_loadrh_io"; 10572let isExtendable = 1; 10573let opExtendable = 3; 10574let isExtentSigned = 0; 10575let opExtentBits = 7; 10576let opExtentAlign = 1; 10577} 10578def L2_ploadrhtnew_pi : HInst< 10579(outs IntRegs:$Rd32, IntRegs:$Rx32), 10580(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_1Imm:$Ii), 10581"if ($Pt4.new) $Rd32 = memh($Rx32++#$Ii)", 10582tc_e9f3243f, TypeLD>, Enc_733b27, PredNewRel { 10583let Inst{13-11} = 0b110; 10584let Inst{31-21} = 0b10011011010; 10585let isPredicated = 1; 10586let hasNewValue = 1; 10587let opNewValue = 0; 10588let addrMode = PostInc; 10589let accessSize = HalfWordAccess; 10590let isPredicatedNew = 1; 10591let mayLoad = 1; 10592let BaseOpcode = "L2_loadrh_pi"; 10593let Constraints = "$Rx32 = $Rx32in"; 10594} 10595def L2_ploadrhtnew_zomap : HInst< 10596(outs IntRegs:$Rd32), 10597(ins PredRegs:$Pt4, IntRegs:$Rs32), 10598"if ($Pt4.new) $Rd32 = memh($Rs32)", 10599tc_44d3da28, TypeMAPPING> { 10600let hasNewValue = 1; 10601let opNewValue = 0; 10602let isPseudo = 1; 10603let isCodeGenOnly = 1; 10604} 10605def L2_ploadrif_io : HInst< 10606(outs IntRegs:$Rd32), 10607(ins PredRegs:$Pt4, IntRegs:$Rs32, u30_2Imm:$Ii), 10608"if (!$Pt4) $Rd32 = memw($Rs32+#$Ii)", 10609tc_5ef37dc4, TypeV2LDST>, Enc_f82eaf, AddrModeRel { 10610let Inst{13-13} = 0b0; 10611let Inst{31-21} = 0b01000101100; 10612let isPredicated = 1; 10613let isPredicatedFalse = 1; 10614let hasNewValue = 1; 10615let opNewValue = 0; 10616let addrMode = BaseImmOffset; 10617let accessSize = WordAccess; 10618let mayLoad = 1; 10619let CextOpcode = "L2_loadri"; 10620let BaseOpcode = "L2_loadri_io"; 10621let isExtendable = 1; 10622let opExtendable = 3; 10623let isExtentSigned = 0; 10624let opExtentBits = 8; 10625let opExtentAlign = 2; 10626} 10627def L2_ploadrif_pi : HInst< 10628(outs IntRegs:$Rd32, IntRegs:$Rx32), 10629(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_2Imm:$Ii), 10630"if (!$Pt4) $Rd32 = memw($Rx32++#$Ii)", 10631tc_3c76b0ff, TypeLD>, Enc_b97f71, PredNewRel { 10632let Inst{13-11} = 0b101; 10633let Inst{31-21} = 0b10011011100; 10634let isPredicated = 1; 10635let isPredicatedFalse = 1; 10636let hasNewValue = 1; 10637let opNewValue = 0; 10638let addrMode = PostInc; 10639let accessSize = WordAccess; 10640let mayLoad = 1; 10641let BaseOpcode = "L2_loadri_pi"; 10642let Constraints = "$Rx32 = $Rx32in"; 10643} 10644def L2_ploadrif_zomap : HInst< 10645(outs IntRegs:$Rd32), 10646(ins PredRegs:$Pt4, IntRegs:$Rs32), 10647"if (!$Pt4) $Rd32 = memw($Rs32)", 10648tc_5ef37dc4, TypeMAPPING> { 10649let hasNewValue = 1; 10650let opNewValue = 0; 10651let isPseudo = 1; 10652let isCodeGenOnly = 1; 10653} 10654def L2_ploadrifnew_io : HInst< 10655(outs IntRegs:$Rd32), 10656(ins PredRegs:$Pt4, IntRegs:$Rs32, u30_2Imm:$Ii), 10657"if (!$Pt4.new) $Rd32 = memw($Rs32+#$Ii)", 10658tc_44d3da28, TypeV2LDST>, Enc_f82eaf, AddrModeRel { 10659let Inst{13-13} = 0b0; 10660let Inst{31-21} = 0b01000111100; 10661let isPredicated = 1; 10662let isPredicatedFalse = 1; 10663let hasNewValue = 1; 10664let opNewValue = 0; 10665let addrMode = BaseImmOffset; 10666let accessSize = WordAccess; 10667let isPredicatedNew = 1; 10668let mayLoad = 1; 10669let CextOpcode = "L2_loadri"; 10670let BaseOpcode = "L2_loadri_io"; 10671let isExtendable = 1; 10672let opExtendable = 3; 10673let isExtentSigned = 0; 10674let opExtentBits = 8; 10675let opExtentAlign = 2; 10676} 10677def L2_ploadrifnew_pi : HInst< 10678(outs IntRegs:$Rd32, IntRegs:$Rx32), 10679(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_2Imm:$Ii), 10680"if (!$Pt4.new) $Rd32 = memw($Rx32++#$Ii)", 10681tc_e9f3243f, TypeLD>, Enc_b97f71, PredNewRel { 10682let Inst{13-11} = 0b111; 10683let Inst{31-21} = 0b10011011100; 10684let isPredicated = 1; 10685let isPredicatedFalse = 1; 10686let hasNewValue = 1; 10687let opNewValue = 0; 10688let addrMode = PostInc; 10689let accessSize = WordAccess; 10690let isPredicatedNew = 1; 10691let mayLoad = 1; 10692let BaseOpcode = "L2_loadri_pi"; 10693let Constraints = "$Rx32 = $Rx32in"; 10694} 10695def L2_ploadrifnew_zomap : HInst< 10696(outs IntRegs:$Rd32), 10697(ins PredRegs:$Pt4, IntRegs:$Rs32), 10698"if (!$Pt4.new) $Rd32 = memw($Rs32)", 10699tc_44d3da28, TypeMAPPING> { 10700let hasNewValue = 1; 10701let opNewValue = 0; 10702let isPseudo = 1; 10703let isCodeGenOnly = 1; 10704} 10705def L2_ploadrit_io : HInst< 10706(outs IntRegs:$Rd32), 10707(ins PredRegs:$Pt4, IntRegs:$Rs32, u30_2Imm:$Ii), 10708"if ($Pt4) $Rd32 = memw($Rs32+#$Ii)", 10709tc_5ef37dc4, TypeV2LDST>, Enc_f82eaf, AddrModeRel { 10710let Inst{13-13} = 0b0; 10711let Inst{31-21} = 0b01000001100; 10712let isPredicated = 1; 10713let hasNewValue = 1; 10714let opNewValue = 0; 10715let addrMode = BaseImmOffset; 10716let accessSize = WordAccess; 10717let mayLoad = 1; 10718let CextOpcode = "L2_loadri"; 10719let BaseOpcode = "L2_loadri_io"; 10720let isExtendable = 1; 10721let opExtendable = 3; 10722let isExtentSigned = 0; 10723let opExtentBits = 8; 10724let opExtentAlign = 2; 10725} 10726def L2_ploadrit_pi : HInst< 10727(outs IntRegs:$Rd32, IntRegs:$Rx32), 10728(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_2Imm:$Ii), 10729"if ($Pt4) $Rd32 = memw($Rx32++#$Ii)", 10730tc_3c76b0ff, TypeLD>, Enc_b97f71, PredNewRel { 10731let Inst{13-11} = 0b100; 10732let Inst{31-21} = 0b10011011100; 10733let isPredicated = 1; 10734let hasNewValue = 1; 10735let opNewValue = 0; 10736let addrMode = PostInc; 10737let accessSize = WordAccess; 10738let mayLoad = 1; 10739let BaseOpcode = "L2_loadri_pi"; 10740let Constraints = "$Rx32 = $Rx32in"; 10741} 10742def L2_ploadrit_zomap : HInst< 10743(outs IntRegs:$Rd32), 10744(ins PredRegs:$Pt4, IntRegs:$Rs32), 10745"if ($Pt4) $Rd32 = memw($Rs32)", 10746tc_5ef37dc4, TypeMAPPING> { 10747let hasNewValue = 1; 10748let opNewValue = 0; 10749let isPseudo = 1; 10750let isCodeGenOnly = 1; 10751} 10752def L2_ploadritnew_io : HInst< 10753(outs IntRegs:$Rd32), 10754(ins PredRegs:$Pt4, IntRegs:$Rs32, u30_2Imm:$Ii), 10755"if ($Pt4.new) $Rd32 = memw($Rs32+#$Ii)", 10756tc_44d3da28, TypeV2LDST>, Enc_f82eaf, AddrModeRel { 10757let Inst{13-13} = 0b0; 10758let Inst{31-21} = 0b01000011100; 10759let isPredicated = 1; 10760let hasNewValue = 1; 10761let opNewValue = 0; 10762let addrMode = BaseImmOffset; 10763let accessSize = WordAccess; 10764let isPredicatedNew = 1; 10765let mayLoad = 1; 10766let CextOpcode = "L2_loadri"; 10767let BaseOpcode = "L2_loadri_io"; 10768let isExtendable = 1; 10769let opExtendable = 3; 10770let isExtentSigned = 0; 10771let opExtentBits = 8; 10772let opExtentAlign = 2; 10773} 10774def L2_ploadritnew_pi : HInst< 10775(outs IntRegs:$Rd32, IntRegs:$Rx32), 10776(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_2Imm:$Ii), 10777"if ($Pt4.new) $Rd32 = memw($Rx32++#$Ii)", 10778tc_e9f3243f, TypeLD>, Enc_b97f71, PredNewRel { 10779let Inst{13-11} = 0b110; 10780let Inst{31-21} = 0b10011011100; 10781let isPredicated = 1; 10782let hasNewValue = 1; 10783let opNewValue = 0; 10784let addrMode = PostInc; 10785let accessSize = WordAccess; 10786let isPredicatedNew = 1; 10787let mayLoad = 1; 10788let BaseOpcode = "L2_loadri_pi"; 10789let Constraints = "$Rx32 = $Rx32in"; 10790} 10791def L2_ploadritnew_zomap : HInst< 10792(outs IntRegs:$Rd32), 10793(ins PredRegs:$Pt4, IntRegs:$Rs32), 10794"if ($Pt4.new) $Rd32 = memw($Rs32)", 10795tc_44d3da28, TypeMAPPING> { 10796let hasNewValue = 1; 10797let opNewValue = 0; 10798let isPseudo = 1; 10799let isCodeGenOnly = 1; 10800} 10801def L2_ploadrubf_io : HInst< 10802(outs IntRegs:$Rd32), 10803(ins PredRegs:$Pt4, IntRegs:$Rs32, u32_0Imm:$Ii), 10804"if (!$Pt4) $Rd32 = memub($Rs32+#$Ii)", 10805tc_5ef37dc4, TypeV2LDST>, Enc_a21d47, AddrModeRel { 10806let Inst{13-13} = 0b0; 10807let Inst{31-21} = 0b01000101001; 10808let isPredicated = 1; 10809let isPredicatedFalse = 1; 10810let hasNewValue = 1; 10811let opNewValue = 0; 10812let addrMode = BaseImmOffset; 10813let accessSize = ByteAccess; 10814let mayLoad = 1; 10815let CextOpcode = "L2_loadrub"; 10816let BaseOpcode = "L2_loadrub_io"; 10817let isExtendable = 1; 10818let opExtendable = 3; 10819let isExtentSigned = 0; 10820let opExtentBits = 6; 10821let opExtentAlign = 0; 10822} 10823def L2_ploadrubf_pi : HInst< 10824(outs IntRegs:$Rd32, IntRegs:$Rx32), 10825(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_0Imm:$Ii), 10826"if (!$Pt4) $Rd32 = memub($Rx32++#$Ii)", 10827tc_3c76b0ff, TypeLD>, Enc_f4413a, PredNewRel { 10828let Inst{13-11} = 0b101; 10829let Inst{31-21} = 0b10011011001; 10830let isPredicated = 1; 10831let isPredicatedFalse = 1; 10832let hasNewValue = 1; 10833let opNewValue = 0; 10834let addrMode = PostInc; 10835let accessSize = ByteAccess; 10836let mayLoad = 1; 10837let BaseOpcode = "L2_loadrub_pi"; 10838let Constraints = "$Rx32 = $Rx32in"; 10839} 10840def L2_ploadrubf_zomap : HInst< 10841(outs IntRegs:$Rd32), 10842(ins PredRegs:$Pt4, IntRegs:$Rs32), 10843"if (!$Pt4) $Rd32 = memub($Rs32)", 10844tc_5ef37dc4, TypeMAPPING> { 10845let hasNewValue = 1; 10846let opNewValue = 0; 10847let isPseudo = 1; 10848let isCodeGenOnly = 1; 10849} 10850def L2_ploadrubfnew_io : HInst< 10851(outs IntRegs:$Rd32), 10852(ins PredRegs:$Pt4, IntRegs:$Rs32, u32_0Imm:$Ii), 10853"if (!$Pt4.new) $Rd32 = memub($Rs32+#$Ii)", 10854tc_44d3da28, TypeV2LDST>, Enc_a21d47, AddrModeRel { 10855let Inst{13-13} = 0b0; 10856let Inst{31-21} = 0b01000111001; 10857let isPredicated = 1; 10858let isPredicatedFalse = 1; 10859let hasNewValue = 1; 10860let opNewValue = 0; 10861let addrMode = BaseImmOffset; 10862let accessSize = ByteAccess; 10863let isPredicatedNew = 1; 10864let mayLoad = 1; 10865let CextOpcode = "L2_loadrub"; 10866let BaseOpcode = "L2_loadrub_io"; 10867let isExtendable = 1; 10868let opExtendable = 3; 10869let isExtentSigned = 0; 10870let opExtentBits = 6; 10871let opExtentAlign = 0; 10872} 10873def L2_ploadrubfnew_pi : HInst< 10874(outs IntRegs:$Rd32, IntRegs:$Rx32), 10875(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_0Imm:$Ii), 10876"if (!$Pt4.new) $Rd32 = memub($Rx32++#$Ii)", 10877tc_e9f3243f, TypeLD>, Enc_f4413a, PredNewRel { 10878let Inst{13-11} = 0b111; 10879let Inst{31-21} = 0b10011011001; 10880let isPredicated = 1; 10881let isPredicatedFalse = 1; 10882let hasNewValue = 1; 10883let opNewValue = 0; 10884let addrMode = PostInc; 10885let accessSize = ByteAccess; 10886let isPredicatedNew = 1; 10887let mayLoad = 1; 10888let BaseOpcode = "L2_loadrub_pi"; 10889let Constraints = "$Rx32 = $Rx32in"; 10890} 10891def L2_ploadrubfnew_zomap : HInst< 10892(outs IntRegs:$Rd32), 10893(ins PredRegs:$Pt4, IntRegs:$Rs32), 10894"if (!$Pt4.new) $Rd32 = memub($Rs32)", 10895tc_44d3da28, TypeMAPPING> { 10896let hasNewValue = 1; 10897let opNewValue = 0; 10898let isPseudo = 1; 10899let isCodeGenOnly = 1; 10900} 10901def L2_ploadrubt_io : HInst< 10902(outs IntRegs:$Rd32), 10903(ins PredRegs:$Pt4, IntRegs:$Rs32, u32_0Imm:$Ii), 10904"if ($Pt4) $Rd32 = memub($Rs32+#$Ii)", 10905tc_5ef37dc4, TypeV2LDST>, Enc_a21d47, AddrModeRel { 10906let Inst{13-13} = 0b0; 10907let Inst{31-21} = 0b01000001001; 10908let isPredicated = 1; 10909let hasNewValue = 1; 10910let opNewValue = 0; 10911let addrMode = BaseImmOffset; 10912let accessSize = ByteAccess; 10913let mayLoad = 1; 10914let CextOpcode = "L2_loadrub"; 10915let BaseOpcode = "L2_loadrub_io"; 10916let isExtendable = 1; 10917let opExtendable = 3; 10918let isExtentSigned = 0; 10919let opExtentBits = 6; 10920let opExtentAlign = 0; 10921} 10922def L2_ploadrubt_pi : HInst< 10923(outs IntRegs:$Rd32, IntRegs:$Rx32), 10924(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_0Imm:$Ii), 10925"if ($Pt4) $Rd32 = memub($Rx32++#$Ii)", 10926tc_3c76b0ff, TypeLD>, Enc_f4413a, PredNewRel { 10927let Inst{13-11} = 0b100; 10928let Inst{31-21} = 0b10011011001; 10929let isPredicated = 1; 10930let hasNewValue = 1; 10931let opNewValue = 0; 10932let addrMode = PostInc; 10933let accessSize = ByteAccess; 10934let mayLoad = 1; 10935let BaseOpcode = "L2_loadrub_pi"; 10936let Constraints = "$Rx32 = $Rx32in"; 10937} 10938def L2_ploadrubt_zomap : HInst< 10939(outs IntRegs:$Rd32), 10940(ins PredRegs:$Pt4, IntRegs:$Rs32), 10941"if ($Pt4) $Rd32 = memub($Rs32)", 10942tc_5ef37dc4, TypeMAPPING> { 10943let hasNewValue = 1; 10944let opNewValue = 0; 10945let isPseudo = 1; 10946let isCodeGenOnly = 1; 10947} 10948def L2_ploadrubtnew_io : HInst< 10949(outs IntRegs:$Rd32), 10950(ins PredRegs:$Pt4, IntRegs:$Rs32, u32_0Imm:$Ii), 10951"if ($Pt4.new) $Rd32 = memub($Rs32+#$Ii)", 10952tc_44d3da28, TypeV2LDST>, Enc_a21d47, AddrModeRel { 10953let Inst{13-13} = 0b0; 10954let Inst{31-21} = 0b01000011001; 10955let isPredicated = 1; 10956let hasNewValue = 1; 10957let opNewValue = 0; 10958let addrMode = BaseImmOffset; 10959let accessSize = ByteAccess; 10960let isPredicatedNew = 1; 10961let mayLoad = 1; 10962let CextOpcode = "L2_loadrub"; 10963let BaseOpcode = "L2_loadrub_io"; 10964let isExtendable = 1; 10965let opExtendable = 3; 10966let isExtentSigned = 0; 10967let opExtentBits = 6; 10968let opExtentAlign = 0; 10969} 10970def L2_ploadrubtnew_pi : HInst< 10971(outs IntRegs:$Rd32, IntRegs:$Rx32), 10972(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_0Imm:$Ii), 10973"if ($Pt4.new) $Rd32 = memub($Rx32++#$Ii)", 10974tc_e9f3243f, TypeLD>, Enc_f4413a, PredNewRel { 10975let Inst{13-11} = 0b110; 10976let Inst{31-21} = 0b10011011001; 10977let isPredicated = 1; 10978let hasNewValue = 1; 10979let opNewValue = 0; 10980let addrMode = PostInc; 10981let accessSize = ByteAccess; 10982let isPredicatedNew = 1; 10983let mayLoad = 1; 10984let BaseOpcode = "L2_loadrub_pi"; 10985let Constraints = "$Rx32 = $Rx32in"; 10986} 10987def L2_ploadrubtnew_zomap : HInst< 10988(outs IntRegs:$Rd32), 10989(ins PredRegs:$Pt4, IntRegs:$Rs32), 10990"if ($Pt4.new) $Rd32 = memub($Rs32)", 10991tc_44d3da28, TypeMAPPING> { 10992let hasNewValue = 1; 10993let opNewValue = 0; 10994let isPseudo = 1; 10995let isCodeGenOnly = 1; 10996} 10997def L2_ploadruhf_io : HInst< 10998(outs IntRegs:$Rd32), 10999(ins PredRegs:$Pt4, IntRegs:$Rs32, u31_1Imm:$Ii), 11000"if (!$Pt4) $Rd32 = memuh($Rs32+#$Ii)", 11001tc_5ef37dc4, TypeV2LDST>, Enc_a198f6, AddrModeRel { 11002let Inst{13-13} = 0b0; 11003let Inst{31-21} = 0b01000101011; 11004let isPredicated = 1; 11005let isPredicatedFalse = 1; 11006let hasNewValue = 1; 11007let opNewValue = 0; 11008let addrMode = BaseImmOffset; 11009let accessSize = HalfWordAccess; 11010let mayLoad = 1; 11011let CextOpcode = "L2_loadruh"; 11012let BaseOpcode = "L2_loadruh_io"; 11013let isExtendable = 1; 11014let opExtendable = 3; 11015let isExtentSigned = 0; 11016let opExtentBits = 7; 11017let opExtentAlign = 1; 11018} 11019def L2_ploadruhf_pi : HInst< 11020(outs IntRegs:$Rd32, IntRegs:$Rx32), 11021(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_1Imm:$Ii), 11022"if (!$Pt4) $Rd32 = memuh($Rx32++#$Ii)", 11023tc_3c76b0ff, TypeLD>, Enc_733b27, PredNewRel { 11024let Inst{13-11} = 0b101; 11025let Inst{31-21} = 0b10011011011; 11026let isPredicated = 1; 11027let isPredicatedFalse = 1; 11028let hasNewValue = 1; 11029let opNewValue = 0; 11030let addrMode = PostInc; 11031let accessSize = HalfWordAccess; 11032let mayLoad = 1; 11033let BaseOpcode = "L2_loadruh_pi"; 11034let Constraints = "$Rx32 = $Rx32in"; 11035} 11036def L2_ploadruhf_zomap : HInst< 11037(outs IntRegs:$Rd32), 11038(ins PredRegs:$Pt4, IntRegs:$Rs32), 11039"if (!$Pt4) $Rd32 = memuh($Rs32)", 11040tc_5ef37dc4, TypeMAPPING> { 11041let hasNewValue = 1; 11042let opNewValue = 0; 11043let isPseudo = 1; 11044let isCodeGenOnly = 1; 11045} 11046def L2_ploadruhfnew_io : HInst< 11047(outs IntRegs:$Rd32), 11048(ins PredRegs:$Pt4, IntRegs:$Rs32, u31_1Imm:$Ii), 11049"if (!$Pt4.new) $Rd32 = memuh($Rs32+#$Ii)", 11050tc_44d3da28, TypeV2LDST>, Enc_a198f6, AddrModeRel { 11051let Inst{13-13} = 0b0; 11052let Inst{31-21} = 0b01000111011; 11053let isPredicated = 1; 11054let isPredicatedFalse = 1; 11055let hasNewValue = 1; 11056let opNewValue = 0; 11057let addrMode = BaseImmOffset; 11058let accessSize = HalfWordAccess; 11059let isPredicatedNew = 1; 11060let mayLoad = 1; 11061let CextOpcode = "L2_loadruh"; 11062let BaseOpcode = "L2_loadruh_io"; 11063let isExtendable = 1; 11064let opExtendable = 3; 11065let isExtentSigned = 0; 11066let opExtentBits = 7; 11067let opExtentAlign = 1; 11068} 11069def L2_ploadruhfnew_pi : HInst< 11070(outs IntRegs:$Rd32, IntRegs:$Rx32), 11071(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_1Imm:$Ii), 11072"if (!$Pt4.new) $Rd32 = memuh($Rx32++#$Ii)", 11073tc_e9f3243f, TypeLD>, Enc_733b27, PredNewRel { 11074let Inst{13-11} = 0b111; 11075let Inst{31-21} = 0b10011011011; 11076let isPredicated = 1; 11077let isPredicatedFalse = 1; 11078let hasNewValue = 1; 11079let opNewValue = 0; 11080let addrMode = PostInc; 11081let accessSize = HalfWordAccess; 11082let isPredicatedNew = 1; 11083let mayLoad = 1; 11084let BaseOpcode = "L2_loadruh_pi"; 11085let Constraints = "$Rx32 = $Rx32in"; 11086} 11087def L2_ploadruhfnew_zomap : HInst< 11088(outs IntRegs:$Rd32), 11089(ins PredRegs:$Pt4, IntRegs:$Rs32), 11090"if (!$Pt4.new) $Rd32 = memuh($Rs32)", 11091tc_44d3da28, TypeMAPPING> { 11092let hasNewValue = 1; 11093let opNewValue = 0; 11094let isPseudo = 1; 11095let isCodeGenOnly = 1; 11096} 11097def L2_ploadruht_io : HInst< 11098(outs IntRegs:$Rd32), 11099(ins PredRegs:$Pt4, IntRegs:$Rs32, u31_1Imm:$Ii), 11100"if ($Pt4) $Rd32 = memuh($Rs32+#$Ii)", 11101tc_5ef37dc4, TypeV2LDST>, Enc_a198f6, AddrModeRel { 11102let Inst{13-13} = 0b0; 11103let Inst{31-21} = 0b01000001011; 11104let isPredicated = 1; 11105let hasNewValue = 1; 11106let opNewValue = 0; 11107let addrMode = BaseImmOffset; 11108let accessSize = HalfWordAccess; 11109let mayLoad = 1; 11110let CextOpcode = "L2_loadruh"; 11111let BaseOpcode = "L2_loadruh_io"; 11112let isExtendable = 1; 11113let opExtendable = 3; 11114let isExtentSigned = 0; 11115let opExtentBits = 7; 11116let opExtentAlign = 1; 11117} 11118def L2_ploadruht_pi : HInst< 11119(outs IntRegs:$Rd32, IntRegs:$Rx32), 11120(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_1Imm:$Ii), 11121"if ($Pt4) $Rd32 = memuh($Rx32++#$Ii)", 11122tc_3c76b0ff, TypeLD>, Enc_733b27, PredNewRel { 11123let Inst{13-11} = 0b100; 11124let Inst{31-21} = 0b10011011011; 11125let isPredicated = 1; 11126let hasNewValue = 1; 11127let opNewValue = 0; 11128let addrMode = PostInc; 11129let accessSize = HalfWordAccess; 11130let mayLoad = 1; 11131let BaseOpcode = "L2_loadruh_pi"; 11132let Constraints = "$Rx32 = $Rx32in"; 11133} 11134def L2_ploadruht_zomap : HInst< 11135(outs IntRegs:$Rd32), 11136(ins PredRegs:$Pt4, IntRegs:$Rs32), 11137"if ($Pt4) $Rd32 = memuh($Rs32)", 11138tc_5ef37dc4, TypeMAPPING> { 11139let hasNewValue = 1; 11140let opNewValue = 0; 11141let isPseudo = 1; 11142let isCodeGenOnly = 1; 11143} 11144def L2_ploadruhtnew_io : HInst< 11145(outs IntRegs:$Rd32), 11146(ins PredRegs:$Pt4, IntRegs:$Rs32, u31_1Imm:$Ii), 11147"if ($Pt4.new) $Rd32 = memuh($Rs32+#$Ii)", 11148tc_44d3da28, TypeV2LDST>, Enc_a198f6, AddrModeRel { 11149let Inst{13-13} = 0b0; 11150let Inst{31-21} = 0b01000011011; 11151let isPredicated = 1; 11152let hasNewValue = 1; 11153let opNewValue = 0; 11154let addrMode = BaseImmOffset; 11155let accessSize = HalfWordAccess; 11156let isPredicatedNew = 1; 11157let mayLoad = 1; 11158let CextOpcode = "L2_loadruh"; 11159let BaseOpcode = "L2_loadruh_io"; 11160let isExtendable = 1; 11161let opExtendable = 3; 11162let isExtentSigned = 0; 11163let opExtentBits = 7; 11164let opExtentAlign = 1; 11165} 11166def L2_ploadruhtnew_pi : HInst< 11167(outs IntRegs:$Rd32, IntRegs:$Rx32), 11168(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_1Imm:$Ii), 11169"if ($Pt4.new) $Rd32 = memuh($Rx32++#$Ii)", 11170tc_e9f3243f, TypeLD>, Enc_733b27, PredNewRel { 11171let Inst{13-11} = 0b110; 11172let Inst{31-21} = 0b10011011011; 11173let isPredicated = 1; 11174let hasNewValue = 1; 11175let opNewValue = 0; 11176let addrMode = PostInc; 11177let accessSize = HalfWordAccess; 11178let isPredicatedNew = 1; 11179let mayLoad = 1; 11180let BaseOpcode = "L2_loadruh_pi"; 11181let Constraints = "$Rx32 = $Rx32in"; 11182} 11183def L2_ploadruhtnew_zomap : HInst< 11184(outs IntRegs:$Rd32), 11185(ins PredRegs:$Pt4, IntRegs:$Rs32), 11186"if ($Pt4.new) $Rd32 = memuh($Rs32)", 11187tc_44d3da28, TypeMAPPING> { 11188let hasNewValue = 1; 11189let opNewValue = 0; 11190let isPseudo = 1; 11191let isCodeGenOnly = 1; 11192} 11193def L4_add_memopb_io : HInst< 11194(outs), 11195(ins IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Rt32), 11196"memb($Rs32+#$Ii) += $Rt32", 11197tc_7186d325, TypeV4LDST>, Enc_d44e31 { 11198let Inst{6-5} = 0b00; 11199let Inst{13-13} = 0b0; 11200let Inst{31-21} = 0b00111110000; 11201let addrMode = BaseImmOffset; 11202let accessSize = ByteAccess; 11203let mayLoad = 1; 11204let isRestrictNoSlot1Store = 1; 11205let mayStore = 1; 11206let isExtendable = 1; 11207let opExtendable = 1; 11208let isExtentSigned = 0; 11209let opExtentBits = 6; 11210let opExtentAlign = 0; 11211} 11212def L4_add_memopb_zomap : HInst< 11213(outs), 11214(ins IntRegs:$Rs32, IntRegs:$Rt32), 11215"memb($Rs32) += $Rt32", 11216tc_7186d325, TypeMAPPING> { 11217let isPseudo = 1; 11218let isCodeGenOnly = 1; 11219} 11220def L4_add_memoph_io : HInst< 11221(outs), 11222(ins IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32), 11223"memh($Rs32+#$Ii) += $Rt32", 11224tc_7186d325, TypeV4LDST>, Enc_163a3c { 11225let Inst{6-5} = 0b00; 11226let Inst{13-13} = 0b0; 11227let Inst{31-21} = 0b00111110001; 11228let addrMode = BaseImmOffset; 11229let accessSize = HalfWordAccess; 11230let mayLoad = 1; 11231let isRestrictNoSlot1Store = 1; 11232let mayStore = 1; 11233let isExtendable = 1; 11234let opExtendable = 1; 11235let isExtentSigned = 0; 11236let opExtentBits = 7; 11237let opExtentAlign = 1; 11238} 11239def L4_add_memoph_zomap : HInst< 11240(outs), 11241(ins IntRegs:$Rs32, IntRegs:$Rt32), 11242"memh($Rs32) += $Rt32", 11243tc_7186d325, TypeMAPPING> { 11244let isPseudo = 1; 11245let isCodeGenOnly = 1; 11246} 11247def L4_add_memopw_io : HInst< 11248(outs), 11249(ins IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Rt32), 11250"memw($Rs32+#$Ii) += $Rt32", 11251tc_7186d325, TypeV4LDST>, Enc_226535 { 11252let Inst{6-5} = 0b00; 11253let Inst{13-13} = 0b0; 11254let Inst{31-21} = 0b00111110010; 11255let addrMode = BaseImmOffset; 11256let accessSize = WordAccess; 11257let mayLoad = 1; 11258let isRestrictNoSlot1Store = 1; 11259let mayStore = 1; 11260let isExtendable = 1; 11261let opExtendable = 1; 11262let isExtentSigned = 0; 11263let opExtentBits = 8; 11264let opExtentAlign = 2; 11265} 11266def L4_add_memopw_zomap : HInst< 11267(outs), 11268(ins IntRegs:$Rs32, IntRegs:$Rt32), 11269"memw($Rs32) += $Rt32", 11270tc_7186d325, TypeMAPPING> { 11271let isPseudo = 1; 11272let isCodeGenOnly = 1; 11273} 11274def L4_and_memopb_io : HInst< 11275(outs), 11276(ins IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Rt32), 11277"memb($Rs32+#$Ii) &= $Rt32", 11278tc_7186d325, TypeV4LDST>, Enc_d44e31 { 11279let Inst{6-5} = 0b10; 11280let Inst{13-13} = 0b0; 11281let Inst{31-21} = 0b00111110000; 11282let addrMode = BaseImmOffset; 11283let accessSize = ByteAccess; 11284let mayLoad = 1; 11285let isRestrictNoSlot1Store = 1; 11286let mayStore = 1; 11287let isExtendable = 1; 11288let opExtendable = 1; 11289let isExtentSigned = 0; 11290let opExtentBits = 6; 11291let opExtentAlign = 0; 11292} 11293def L4_and_memopb_zomap : HInst< 11294(outs), 11295(ins IntRegs:$Rs32, IntRegs:$Rt32), 11296"memb($Rs32) &= $Rt32", 11297tc_7186d325, TypeMAPPING> { 11298let isPseudo = 1; 11299let isCodeGenOnly = 1; 11300} 11301def L4_and_memoph_io : HInst< 11302(outs), 11303(ins IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32), 11304"memh($Rs32+#$Ii) &= $Rt32", 11305tc_7186d325, TypeV4LDST>, Enc_163a3c { 11306let Inst{6-5} = 0b10; 11307let Inst{13-13} = 0b0; 11308let Inst{31-21} = 0b00111110001; 11309let addrMode = BaseImmOffset; 11310let accessSize = HalfWordAccess; 11311let mayLoad = 1; 11312let isRestrictNoSlot1Store = 1; 11313let mayStore = 1; 11314let isExtendable = 1; 11315let opExtendable = 1; 11316let isExtentSigned = 0; 11317let opExtentBits = 7; 11318let opExtentAlign = 1; 11319} 11320def L4_and_memoph_zomap : HInst< 11321(outs), 11322(ins IntRegs:$Rs32, IntRegs:$Rt32), 11323"memh($Rs32) &= $Rt32", 11324tc_7186d325, TypeMAPPING> { 11325let isPseudo = 1; 11326let isCodeGenOnly = 1; 11327} 11328def L4_and_memopw_io : HInst< 11329(outs), 11330(ins IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Rt32), 11331"memw($Rs32+#$Ii) &= $Rt32", 11332tc_7186d325, TypeV4LDST>, Enc_226535 { 11333let Inst{6-5} = 0b10; 11334let Inst{13-13} = 0b0; 11335let Inst{31-21} = 0b00111110010; 11336let addrMode = BaseImmOffset; 11337let accessSize = WordAccess; 11338let mayLoad = 1; 11339let isRestrictNoSlot1Store = 1; 11340let mayStore = 1; 11341let isExtendable = 1; 11342let opExtendable = 1; 11343let isExtentSigned = 0; 11344let opExtentBits = 8; 11345let opExtentAlign = 2; 11346} 11347def L4_and_memopw_zomap : HInst< 11348(outs), 11349(ins IntRegs:$Rs32, IntRegs:$Rt32), 11350"memw($Rs32) &= $Rt32", 11351tc_7186d325, TypeMAPPING> { 11352let isPseudo = 1; 11353let isCodeGenOnly = 1; 11354} 11355def L4_iadd_memopb_io : HInst< 11356(outs), 11357(ins IntRegs:$Rs32, u32_0Imm:$Ii, u5_0Imm:$II), 11358"memb($Rs32+#$Ii) += #$II", 11359tc_096199d3, TypeV4LDST>, Enc_46c951 { 11360let Inst{6-5} = 0b00; 11361let Inst{13-13} = 0b0; 11362let Inst{31-21} = 0b00111111000; 11363let addrMode = BaseImmOffset; 11364let accessSize = ByteAccess; 11365let mayLoad = 1; 11366let isRestrictNoSlot1Store = 1; 11367let mayStore = 1; 11368let isExtendable = 1; 11369let opExtendable = 1; 11370let isExtentSigned = 0; 11371let opExtentBits = 6; 11372let opExtentAlign = 0; 11373} 11374def L4_iadd_memopb_zomap : HInst< 11375(outs), 11376(ins IntRegs:$Rs32, u5_0Imm:$II), 11377"memb($Rs32) += #$II", 11378tc_096199d3, TypeMAPPING> { 11379let isPseudo = 1; 11380let isCodeGenOnly = 1; 11381} 11382def L4_iadd_memoph_io : HInst< 11383(outs), 11384(ins IntRegs:$Rs32, u31_1Imm:$Ii, u5_0Imm:$II), 11385"memh($Rs32+#$Ii) += #$II", 11386tc_096199d3, TypeV4LDST>, Enc_e66a97 { 11387let Inst{6-5} = 0b00; 11388let Inst{13-13} = 0b0; 11389let Inst{31-21} = 0b00111111001; 11390let addrMode = BaseImmOffset; 11391let accessSize = HalfWordAccess; 11392let mayLoad = 1; 11393let isRestrictNoSlot1Store = 1; 11394let mayStore = 1; 11395let isExtendable = 1; 11396let opExtendable = 1; 11397let isExtentSigned = 0; 11398let opExtentBits = 7; 11399let opExtentAlign = 1; 11400} 11401def L4_iadd_memoph_zomap : HInst< 11402(outs), 11403(ins IntRegs:$Rs32, u5_0Imm:$II), 11404"memh($Rs32) += #$II", 11405tc_096199d3, TypeMAPPING> { 11406let isPseudo = 1; 11407let isCodeGenOnly = 1; 11408} 11409def L4_iadd_memopw_io : HInst< 11410(outs), 11411(ins IntRegs:$Rs32, u30_2Imm:$Ii, u5_0Imm:$II), 11412"memw($Rs32+#$Ii) += #$II", 11413tc_096199d3, TypeV4LDST>, Enc_84b2cd { 11414let Inst{6-5} = 0b00; 11415let Inst{13-13} = 0b0; 11416let Inst{31-21} = 0b00111111010; 11417let addrMode = BaseImmOffset; 11418let accessSize = WordAccess; 11419let mayLoad = 1; 11420let isRestrictNoSlot1Store = 1; 11421let mayStore = 1; 11422let isExtendable = 1; 11423let opExtendable = 1; 11424let isExtentSigned = 0; 11425let opExtentBits = 8; 11426let opExtentAlign = 2; 11427} 11428def L4_iadd_memopw_zomap : HInst< 11429(outs), 11430(ins IntRegs:$Rs32, u5_0Imm:$II), 11431"memw($Rs32) += #$II", 11432tc_096199d3, TypeMAPPING> { 11433let isPseudo = 1; 11434let isCodeGenOnly = 1; 11435} 11436def L4_iand_memopb_io : HInst< 11437(outs), 11438(ins IntRegs:$Rs32, u32_0Imm:$Ii, u5_0Imm:$II), 11439"memb($Rs32+#$Ii) = clrbit(#$II)", 11440tc_096199d3, TypeV4LDST>, Enc_46c951 { 11441let Inst{6-5} = 0b10; 11442let Inst{13-13} = 0b0; 11443let Inst{31-21} = 0b00111111000; 11444let addrMode = BaseImmOffset; 11445let accessSize = ByteAccess; 11446let mayLoad = 1; 11447let isRestrictNoSlot1Store = 1; 11448let mayStore = 1; 11449let isExtendable = 1; 11450let opExtendable = 1; 11451let isExtentSigned = 0; 11452let opExtentBits = 6; 11453let opExtentAlign = 0; 11454} 11455def L4_iand_memopb_zomap : HInst< 11456(outs), 11457(ins IntRegs:$Rs32, u5_0Imm:$II), 11458"memb($Rs32) = clrbit(#$II)", 11459tc_096199d3, TypeMAPPING> { 11460let isPseudo = 1; 11461let isCodeGenOnly = 1; 11462} 11463def L4_iand_memoph_io : HInst< 11464(outs), 11465(ins IntRegs:$Rs32, u31_1Imm:$Ii, u5_0Imm:$II), 11466"memh($Rs32+#$Ii) = clrbit(#$II)", 11467tc_096199d3, TypeV4LDST>, Enc_e66a97 { 11468let Inst{6-5} = 0b10; 11469let Inst{13-13} = 0b0; 11470let Inst{31-21} = 0b00111111001; 11471let addrMode = BaseImmOffset; 11472let accessSize = HalfWordAccess; 11473let mayLoad = 1; 11474let isRestrictNoSlot1Store = 1; 11475let mayStore = 1; 11476let isExtendable = 1; 11477let opExtendable = 1; 11478let isExtentSigned = 0; 11479let opExtentBits = 7; 11480let opExtentAlign = 1; 11481} 11482def L4_iand_memoph_zomap : HInst< 11483(outs), 11484(ins IntRegs:$Rs32, u5_0Imm:$II), 11485"memh($Rs32) = clrbit(#$II)", 11486tc_096199d3, TypeMAPPING> { 11487let isPseudo = 1; 11488let isCodeGenOnly = 1; 11489} 11490def L4_iand_memopw_io : HInst< 11491(outs), 11492(ins IntRegs:$Rs32, u30_2Imm:$Ii, u5_0Imm:$II), 11493"memw($Rs32+#$Ii) = clrbit(#$II)", 11494tc_096199d3, TypeV4LDST>, Enc_84b2cd { 11495let Inst{6-5} = 0b10; 11496let Inst{13-13} = 0b0; 11497let Inst{31-21} = 0b00111111010; 11498let addrMode = BaseImmOffset; 11499let accessSize = WordAccess; 11500let mayLoad = 1; 11501let isRestrictNoSlot1Store = 1; 11502let mayStore = 1; 11503let isExtendable = 1; 11504let opExtendable = 1; 11505let isExtentSigned = 0; 11506let opExtentBits = 8; 11507let opExtentAlign = 2; 11508} 11509def L4_iand_memopw_zomap : HInst< 11510(outs), 11511(ins IntRegs:$Rs32, u5_0Imm:$II), 11512"memw($Rs32) = clrbit(#$II)", 11513tc_096199d3, TypeMAPPING> { 11514let isPseudo = 1; 11515let isCodeGenOnly = 1; 11516} 11517def L4_ior_memopb_io : HInst< 11518(outs), 11519(ins IntRegs:$Rs32, u32_0Imm:$Ii, u5_0Imm:$II), 11520"memb($Rs32+#$Ii) = setbit(#$II)", 11521tc_096199d3, TypeV4LDST>, Enc_46c951 { 11522let Inst{6-5} = 0b11; 11523let Inst{13-13} = 0b0; 11524let Inst{31-21} = 0b00111111000; 11525let addrMode = BaseImmOffset; 11526let accessSize = ByteAccess; 11527let mayLoad = 1; 11528let isRestrictNoSlot1Store = 1; 11529let mayStore = 1; 11530let isExtendable = 1; 11531let opExtendable = 1; 11532let isExtentSigned = 0; 11533let opExtentBits = 6; 11534let opExtentAlign = 0; 11535} 11536def L4_ior_memopb_zomap : HInst< 11537(outs), 11538(ins IntRegs:$Rs32, u5_0Imm:$II), 11539"memb($Rs32) = setbit(#$II)", 11540tc_096199d3, TypeMAPPING> { 11541let isPseudo = 1; 11542let isCodeGenOnly = 1; 11543} 11544def L4_ior_memoph_io : HInst< 11545(outs), 11546(ins IntRegs:$Rs32, u31_1Imm:$Ii, u5_0Imm:$II), 11547"memh($Rs32+#$Ii) = setbit(#$II)", 11548tc_096199d3, TypeV4LDST>, Enc_e66a97 { 11549let Inst{6-5} = 0b11; 11550let Inst{13-13} = 0b0; 11551let Inst{31-21} = 0b00111111001; 11552let addrMode = BaseImmOffset; 11553let accessSize = HalfWordAccess; 11554let mayLoad = 1; 11555let isRestrictNoSlot1Store = 1; 11556let mayStore = 1; 11557let isExtendable = 1; 11558let opExtendable = 1; 11559let isExtentSigned = 0; 11560let opExtentBits = 7; 11561let opExtentAlign = 1; 11562} 11563def L4_ior_memoph_zomap : HInst< 11564(outs), 11565(ins IntRegs:$Rs32, u5_0Imm:$II), 11566"memh($Rs32) = setbit(#$II)", 11567tc_096199d3, TypeMAPPING> { 11568let isPseudo = 1; 11569let isCodeGenOnly = 1; 11570} 11571def L4_ior_memopw_io : HInst< 11572(outs), 11573(ins IntRegs:$Rs32, u30_2Imm:$Ii, u5_0Imm:$II), 11574"memw($Rs32+#$Ii) = setbit(#$II)", 11575tc_096199d3, TypeV4LDST>, Enc_84b2cd { 11576let Inst{6-5} = 0b11; 11577let Inst{13-13} = 0b0; 11578let Inst{31-21} = 0b00111111010; 11579let addrMode = BaseImmOffset; 11580let accessSize = WordAccess; 11581let mayLoad = 1; 11582let isRestrictNoSlot1Store = 1; 11583let mayStore = 1; 11584let isExtendable = 1; 11585let opExtendable = 1; 11586let isExtentSigned = 0; 11587let opExtentBits = 8; 11588let opExtentAlign = 2; 11589} 11590def L4_ior_memopw_zomap : HInst< 11591(outs), 11592(ins IntRegs:$Rs32, u5_0Imm:$II), 11593"memw($Rs32) = setbit(#$II)", 11594tc_096199d3, TypeMAPPING> { 11595let isPseudo = 1; 11596let isCodeGenOnly = 1; 11597} 11598def L4_isub_memopb_io : HInst< 11599(outs), 11600(ins IntRegs:$Rs32, u32_0Imm:$Ii, u5_0Imm:$II), 11601"memb($Rs32+#$Ii) -= #$II", 11602tc_096199d3, TypeV4LDST>, Enc_46c951 { 11603let Inst{6-5} = 0b01; 11604let Inst{13-13} = 0b0; 11605let Inst{31-21} = 0b00111111000; 11606let addrMode = BaseImmOffset; 11607let accessSize = ByteAccess; 11608let mayLoad = 1; 11609let isRestrictNoSlot1Store = 1; 11610let mayStore = 1; 11611let isExtendable = 1; 11612let opExtendable = 1; 11613let isExtentSigned = 0; 11614let opExtentBits = 6; 11615let opExtentAlign = 0; 11616} 11617def L4_isub_memopb_zomap : HInst< 11618(outs), 11619(ins IntRegs:$Rs32, u5_0Imm:$II), 11620"memb($Rs32) -= #$II", 11621tc_096199d3, TypeMAPPING> { 11622let isPseudo = 1; 11623let isCodeGenOnly = 1; 11624} 11625def L4_isub_memoph_io : HInst< 11626(outs), 11627(ins IntRegs:$Rs32, u31_1Imm:$Ii, u5_0Imm:$II), 11628"memh($Rs32+#$Ii) -= #$II", 11629tc_096199d3, TypeV4LDST>, Enc_e66a97 { 11630let Inst{6-5} = 0b01; 11631let Inst{13-13} = 0b0; 11632let Inst{31-21} = 0b00111111001; 11633let addrMode = BaseImmOffset; 11634let accessSize = HalfWordAccess; 11635let mayLoad = 1; 11636let isRestrictNoSlot1Store = 1; 11637let mayStore = 1; 11638let isExtendable = 1; 11639let opExtendable = 1; 11640let isExtentSigned = 0; 11641let opExtentBits = 7; 11642let opExtentAlign = 1; 11643} 11644def L4_isub_memoph_zomap : HInst< 11645(outs), 11646(ins IntRegs:$Rs32, u5_0Imm:$II), 11647"memh($Rs32) -= #$II", 11648tc_096199d3, TypeMAPPING> { 11649let isPseudo = 1; 11650let isCodeGenOnly = 1; 11651} 11652def L4_isub_memopw_io : HInst< 11653(outs), 11654(ins IntRegs:$Rs32, u30_2Imm:$Ii, u5_0Imm:$II), 11655"memw($Rs32+#$Ii) -= #$II", 11656tc_096199d3, TypeV4LDST>, Enc_84b2cd { 11657let Inst{6-5} = 0b01; 11658let Inst{13-13} = 0b0; 11659let Inst{31-21} = 0b00111111010; 11660let addrMode = BaseImmOffset; 11661let accessSize = WordAccess; 11662let mayLoad = 1; 11663let isRestrictNoSlot1Store = 1; 11664let mayStore = 1; 11665let isExtendable = 1; 11666let opExtendable = 1; 11667let isExtentSigned = 0; 11668let opExtentBits = 8; 11669let opExtentAlign = 2; 11670} 11671def L4_isub_memopw_zomap : HInst< 11672(outs), 11673(ins IntRegs:$Rs32, u5_0Imm:$II), 11674"memw($Rs32) -= #$II", 11675tc_096199d3, TypeMAPPING> { 11676let isPseudo = 1; 11677let isCodeGenOnly = 1; 11678} 11679def L4_loadalignb_ap : HInst< 11680(outs DoubleRegs:$Ryy32, IntRegs:$Re32), 11681(ins DoubleRegs:$Ryy32in, u32_0Imm:$II), 11682"$Ryy32 = memb_fifo($Re32=#$II)", 11683tc_7a91e76a, TypeLD>, Enc_f394d3 { 11684let Inst{7-7} = 0b0; 11685let Inst{13-12} = 0b01; 11686let Inst{31-21} = 0b10011010100; 11687let addrMode = AbsoluteSet; 11688let accessSize = ByteAccess; 11689let mayLoad = 1; 11690let isExtended = 1; 11691let DecoderNamespace = "MustExtend"; 11692let isExtendable = 1; 11693let opExtendable = 3; 11694let isExtentSigned = 0; 11695let opExtentBits = 6; 11696let opExtentAlign = 0; 11697let Constraints = "$Ryy32 = $Ryy32in"; 11698} 11699def L4_loadalignb_ur : HInst< 11700(outs DoubleRegs:$Ryy32), 11701(ins DoubleRegs:$Ryy32in, IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II), 11702"$Ryy32 = memb_fifo($Rt32<<#$Ii+#$II)", 11703tc_a5d4aeec, TypeLD>, Enc_04c959 { 11704let Inst{12-12} = 0b1; 11705let Inst{31-21} = 0b10011100100; 11706let addrMode = BaseLongOffset; 11707let accessSize = ByteAccess; 11708let mayLoad = 1; 11709let isExtended = 1; 11710let InputType = "imm"; 11711let DecoderNamespace = "MustExtend"; 11712let isExtendable = 1; 11713let opExtendable = 4; 11714let isExtentSigned = 0; 11715let opExtentBits = 6; 11716let opExtentAlign = 0; 11717let Constraints = "$Ryy32 = $Ryy32in"; 11718} 11719def L4_loadalignh_ap : HInst< 11720(outs DoubleRegs:$Ryy32, IntRegs:$Re32), 11721(ins DoubleRegs:$Ryy32in, u32_0Imm:$II), 11722"$Ryy32 = memh_fifo($Re32=#$II)", 11723tc_7a91e76a, TypeLD>, Enc_f394d3 { 11724let Inst{7-7} = 0b0; 11725let Inst{13-12} = 0b01; 11726let Inst{31-21} = 0b10011010010; 11727let addrMode = AbsoluteSet; 11728let accessSize = HalfWordAccess; 11729let mayLoad = 1; 11730let isExtended = 1; 11731let DecoderNamespace = "MustExtend"; 11732let isExtendable = 1; 11733let opExtendable = 3; 11734let isExtentSigned = 0; 11735let opExtentBits = 6; 11736let opExtentAlign = 0; 11737let Constraints = "$Ryy32 = $Ryy32in"; 11738} 11739def L4_loadalignh_ur : HInst< 11740(outs DoubleRegs:$Ryy32), 11741(ins DoubleRegs:$Ryy32in, IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II), 11742"$Ryy32 = memh_fifo($Rt32<<#$Ii+#$II)", 11743tc_a5d4aeec, TypeLD>, Enc_04c959 { 11744let Inst{12-12} = 0b1; 11745let Inst{31-21} = 0b10011100010; 11746let addrMode = BaseLongOffset; 11747let accessSize = HalfWordAccess; 11748let mayLoad = 1; 11749let isExtended = 1; 11750let InputType = "imm"; 11751let DecoderNamespace = "MustExtend"; 11752let isExtendable = 1; 11753let opExtendable = 4; 11754let isExtentSigned = 0; 11755let opExtentBits = 6; 11756let opExtentAlign = 0; 11757let Constraints = "$Ryy32 = $Ryy32in"; 11758} 11759def L4_loadbsw2_ap : HInst< 11760(outs IntRegs:$Rd32, IntRegs:$Re32), 11761(ins u32_0Imm:$II), 11762"$Rd32 = membh($Re32=#$II)", 11763tc_3b5b7ef9, TypeLD>, Enc_323f2d { 11764let Inst{7-7} = 0b0; 11765let Inst{13-12} = 0b01; 11766let Inst{31-21} = 0b10011010001; 11767let hasNewValue = 1; 11768let opNewValue = 0; 11769let addrMode = AbsoluteSet; 11770let accessSize = HalfWordAccess; 11771let mayLoad = 1; 11772let isExtended = 1; 11773let DecoderNamespace = "MustExtend"; 11774let isExtendable = 1; 11775let opExtendable = 2; 11776let isExtentSigned = 0; 11777let opExtentBits = 6; 11778let opExtentAlign = 0; 11779} 11780def L4_loadbsw2_ur : HInst< 11781(outs IntRegs:$Rd32), 11782(ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II), 11783"$Rd32 = membh($Rt32<<#$Ii+#$II)", 11784tc_bab0eed9, TypeLD>, Enc_4f677b { 11785let Inst{12-12} = 0b1; 11786let Inst{31-21} = 0b10011100001; 11787let hasNewValue = 1; 11788let opNewValue = 0; 11789let addrMode = BaseLongOffset; 11790let accessSize = HalfWordAccess; 11791let mayLoad = 1; 11792let isExtended = 1; 11793let InputType = "imm"; 11794let DecoderNamespace = "MustExtend"; 11795let isExtendable = 1; 11796let opExtendable = 3; 11797let isExtentSigned = 0; 11798let opExtentBits = 6; 11799let opExtentAlign = 0; 11800} 11801def L4_loadbsw4_ap : HInst< 11802(outs DoubleRegs:$Rdd32, IntRegs:$Re32), 11803(ins u32_0Imm:$II), 11804"$Rdd32 = membh($Re32=#$II)", 11805tc_3b5b7ef9, TypeLD>, Enc_7fa7f6 { 11806let Inst{7-7} = 0b0; 11807let Inst{13-12} = 0b01; 11808let Inst{31-21} = 0b10011010111; 11809let addrMode = AbsoluteSet; 11810let accessSize = WordAccess; 11811let mayLoad = 1; 11812let isExtended = 1; 11813let DecoderNamespace = "MustExtend"; 11814let isExtendable = 1; 11815let opExtendable = 2; 11816let isExtentSigned = 0; 11817let opExtentBits = 6; 11818let opExtentAlign = 0; 11819} 11820def L4_loadbsw4_ur : HInst< 11821(outs DoubleRegs:$Rdd32), 11822(ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II), 11823"$Rdd32 = membh($Rt32<<#$Ii+#$II)", 11824tc_bab0eed9, TypeLD>, Enc_6185fe { 11825let Inst{12-12} = 0b1; 11826let Inst{31-21} = 0b10011100111; 11827let addrMode = BaseLongOffset; 11828let accessSize = WordAccess; 11829let mayLoad = 1; 11830let isExtended = 1; 11831let InputType = "imm"; 11832let DecoderNamespace = "MustExtend"; 11833let isExtendable = 1; 11834let opExtendable = 3; 11835let isExtentSigned = 0; 11836let opExtentBits = 6; 11837let opExtentAlign = 0; 11838} 11839def L4_loadbzw2_ap : HInst< 11840(outs IntRegs:$Rd32, IntRegs:$Re32), 11841(ins u32_0Imm:$II), 11842"$Rd32 = memubh($Re32=#$II)", 11843tc_3b5b7ef9, TypeLD>, Enc_323f2d { 11844let Inst{7-7} = 0b0; 11845let Inst{13-12} = 0b01; 11846let Inst{31-21} = 0b10011010011; 11847let hasNewValue = 1; 11848let opNewValue = 0; 11849let addrMode = AbsoluteSet; 11850let accessSize = HalfWordAccess; 11851let mayLoad = 1; 11852let isExtended = 1; 11853let DecoderNamespace = "MustExtend"; 11854let isExtendable = 1; 11855let opExtendable = 2; 11856let isExtentSigned = 0; 11857let opExtentBits = 6; 11858let opExtentAlign = 0; 11859} 11860def L4_loadbzw2_ur : HInst< 11861(outs IntRegs:$Rd32), 11862(ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II), 11863"$Rd32 = memubh($Rt32<<#$Ii+#$II)", 11864tc_bab0eed9, TypeLD>, Enc_4f677b { 11865let Inst{12-12} = 0b1; 11866let Inst{31-21} = 0b10011100011; 11867let hasNewValue = 1; 11868let opNewValue = 0; 11869let addrMode = BaseLongOffset; 11870let accessSize = HalfWordAccess; 11871let mayLoad = 1; 11872let isExtended = 1; 11873let InputType = "imm"; 11874let DecoderNamespace = "MustExtend"; 11875let isExtendable = 1; 11876let opExtendable = 3; 11877let isExtentSigned = 0; 11878let opExtentBits = 6; 11879let opExtentAlign = 0; 11880} 11881def L4_loadbzw4_ap : HInst< 11882(outs DoubleRegs:$Rdd32, IntRegs:$Re32), 11883(ins u32_0Imm:$II), 11884"$Rdd32 = memubh($Re32=#$II)", 11885tc_3b5b7ef9, TypeLD>, Enc_7fa7f6 { 11886let Inst{7-7} = 0b0; 11887let Inst{13-12} = 0b01; 11888let Inst{31-21} = 0b10011010101; 11889let addrMode = AbsoluteSet; 11890let accessSize = WordAccess; 11891let mayLoad = 1; 11892let isExtended = 1; 11893let DecoderNamespace = "MustExtend"; 11894let isExtendable = 1; 11895let opExtendable = 2; 11896let isExtentSigned = 0; 11897let opExtentBits = 6; 11898let opExtentAlign = 0; 11899} 11900def L4_loadbzw4_ur : HInst< 11901(outs DoubleRegs:$Rdd32), 11902(ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II), 11903"$Rdd32 = memubh($Rt32<<#$Ii+#$II)", 11904tc_bab0eed9, TypeLD>, Enc_6185fe { 11905let Inst{12-12} = 0b1; 11906let Inst{31-21} = 0b10011100101; 11907let addrMode = BaseLongOffset; 11908let accessSize = WordAccess; 11909let mayLoad = 1; 11910let isExtended = 1; 11911let InputType = "imm"; 11912let DecoderNamespace = "MustExtend"; 11913let isExtendable = 1; 11914let opExtendable = 3; 11915let isExtentSigned = 0; 11916let opExtentBits = 6; 11917let opExtentAlign = 0; 11918} 11919def L4_loadd_locked : HInst< 11920(outs DoubleRegs:$Rdd32), 11921(ins IntRegs:$Rs32), 11922"$Rdd32 = memd_locked($Rs32)", 11923tc_b43e7930, TypeLD>, Enc_3a3d62 { 11924let Inst{13-5} = 0b010000000; 11925let Inst{31-21} = 0b10010010000; 11926let accessSize = DoubleWordAccess; 11927let mayLoad = 1; 11928let isSoloAX = 1; 11929} 11930def L4_loadrb_ap : HInst< 11931(outs IntRegs:$Rd32, IntRegs:$Re32), 11932(ins u32_0Imm:$II), 11933"$Rd32 = memb($Re32=#$II)", 11934tc_3b5b7ef9, TypeLD>, Enc_323f2d { 11935let Inst{7-7} = 0b0; 11936let Inst{13-12} = 0b01; 11937let Inst{31-21} = 0b10011011000; 11938let hasNewValue = 1; 11939let opNewValue = 0; 11940let addrMode = AbsoluteSet; 11941let accessSize = ByteAccess; 11942let mayLoad = 1; 11943let isExtended = 1; 11944let DecoderNamespace = "MustExtend"; 11945let isExtendable = 1; 11946let opExtendable = 2; 11947let isExtentSigned = 0; 11948let opExtentBits = 6; 11949let opExtentAlign = 0; 11950} 11951def L4_loadrb_rr : HInst< 11952(outs IntRegs:$Rd32), 11953(ins IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), 11954"$Rd32 = memb($Rs32+$Rt32<<#$Ii)", 11955tc_bf061958, TypeLD>, Enc_da664b, AddrModeRel, ImmRegShl { 11956let Inst{6-5} = 0b00; 11957let Inst{31-21} = 0b00111010000; 11958let hasNewValue = 1; 11959let opNewValue = 0; 11960let addrMode = BaseRegOffset; 11961let accessSize = ByteAccess; 11962let mayLoad = 1; 11963let CextOpcode = "L2_loadrb"; 11964let InputType = "reg"; 11965let BaseOpcode = "L4_loadrb_rr"; 11966let isPredicable = 1; 11967} 11968def L4_loadrb_ur : HInst< 11969(outs IntRegs:$Rd32), 11970(ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II), 11971"$Rd32 = memb($Rt32<<#$Ii+#$II)", 11972tc_bab0eed9, TypeLD>, Enc_4f677b, AddrModeRel, ImmRegShl { 11973let Inst{12-12} = 0b1; 11974let Inst{31-21} = 0b10011101000; 11975let hasNewValue = 1; 11976let opNewValue = 0; 11977let addrMode = BaseLongOffset; 11978let accessSize = ByteAccess; 11979let mayLoad = 1; 11980let isExtended = 1; 11981let CextOpcode = "L2_loadrb"; 11982let InputType = "imm"; 11983let DecoderNamespace = "MustExtend"; 11984let isExtendable = 1; 11985let opExtendable = 3; 11986let isExtentSigned = 0; 11987let opExtentBits = 6; 11988let opExtentAlign = 0; 11989} 11990def L4_loadrd_ap : HInst< 11991(outs DoubleRegs:$Rdd32, IntRegs:$Re32), 11992(ins u32_0Imm:$II), 11993"$Rdd32 = memd($Re32=#$II)", 11994tc_3b5b7ef9, TypeLD>, Enc_7fa7f6 { 11995let Inst{7-7} = 0b0; 11996let Inst{13-12} = 0b01; 11997let Inst{31-21} = 0b10011011110; 11998let addrMode = AbsoluteSet; 11999let accessSize = DoubleWordAccess; 12000let mayLoad = 1; 12001let isExtended = 1; 12002let DecoderNamespace = "MustExtend"; 12003let isExtendable = 1; 12004let opExtendable = 2; 12005let isExtentSigned = 0; 12006let opExtentBits = 6; 12007let opExtentAlign = 0; 12008} 12009def L4_loadrd_rr : HInst< 12010(outs DoubleRegs:$Rdd32), 12011(ins IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), 12012"$Rdd32 = memd($Rs32+$Rt32<<#$Ii)", 12013tc_bf061958, TypeLD>, Enc_84bff1, AddrModeRel, ImmRegShl { 12014let Inst{6-5} = 0b00; 12015let Inst{31-21} = 0b00111010110; 12016let addrMode = BaseRegOffset; 12017let accessSize = DoubleWordAccess; 12018let mayLoad = 1; 12019let CextOpcode = "L2_loadrd"; 12020let InputType = "reg"; 12021let BaseOpcode = "L4_loadrd_rr"; 12022let isPredicable = 1; 12023} 12024def L4_loadrd_ur : HInst< 12025(outs DoubleRegs:$Rdd32), 12026(ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II), 12027"$Rdd32 = memd($Rt32<<#$Ii+#$II)", 12028tc_bab0eed9, TypeLD>, Enc_6185fe, AddrModeRel, ImmRegShl { 12029let Inst{12-12} = 0b1; 12030let Inst{31-21} = 0b10011101110; 12031let addrMode = BaseLongOffset; 12032let accessSize = DoubleWordAccess; 12033let mayLoad = 1; 12034let isExtended = 1; 12035let CextOpcode = "L2_loadrd"; 12036let InputType = "imm"; 12037let DecoderNamespace = "MustExtend"; 12038let isExtendable = 1; 12039let opExtendable = 3; 12040let isExtentSigned = 0; 12041let opExtentBits = 6; 12042let opExtentAlign = 0; 12043} 12044def L4_loadrh_ap : HInst< 12045(outs IntRegs:$Rd32, IntRegs:$Re32), 12046(ins u32_0Imm:$II), 12047"$Rd32 = memh($Re32=#$II)", 12048tc_3b5b7ef9, TypeLD>, Enc_323f2d { 12049let Inst{7-7} = 0b0; 12050let Inst{13-12} = 0b01; 12051let Inst{31-21} = 0b10011011010; 12052let hasNewValue = 1; 12053let opNewValue = 0; 12054let addrMode = AbsoluteSet; 12055let accessSize = HalfWordAccess; 12056let mayLoad = 1; 12057let isExtended = 1; 12058let DecoderNamespace = "MustExtend"; 12059let isExtendable = 1; 12060let opExtendable = 2; 12061let isExtentSigned = 0; 12062let opExtentBits = 6; 12063let opExtentAlign = 0; 12064} 12065def L4_loadrh_rr : HInst< 12066(outs IntRegs:$Rd32), 12067(ins IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), 12068"$Rd32 = memh($Rs32+$Rt32<<#$Ii)", 12069tc_bf061958, TypeLD>, Enc_da664b, AddrModeRel, ImmRegShl { 12070let Inst{6-5} = 0b00; 12071let Inst{31-21} = 0b00111010010; 12072let hasNewValue = 1; 12073let opNewValue = 0; 12074let addrMode = BaseRegOffset; 12075let accessSize = HalfWordAccess; 12076let mayLoad = 1; 12077let CextOpcode = "L2_loadrh"; 12078let InputType = "reg"; 12079let BaseOpcode = "L4_loadrh_rr"; 12080let isPredicable = 1; 12081} 12082def L4_loadrh_ur : HInst< 12083(outs IntRegs:$Rd32), 12084(ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II), 12085"$Rd32 = memh($Rt32<<#$Ii+#$II)", 12086tc_bab0eed9, TypeLD>, Enc_4f677b, AddrModeRel, ImmRegShl { 12087let Inst{12-12} = 0b1; 12088let Inst{31-21} = 0b10011101010; 12089let hasNewValue = 1; 12090let opNewValue = 0; 12091let addrMode = BaseLongOffset; 12092let accessSize = HalfWordAccess; 12093let mayLoad = 1; 12094let isExtended = 1; 12095let CextOpcode = "L2_loadrh"; 12096let InputType = "imm"; 12097let DecoderNamespace = "MustExtend"; 12098let isExtendable = 1; 12099let opExtendable = 3; 12100let isExtentSigned = 0; 12101let opExtentBits = 6; 12102let opExtentAlign = 0; 12103} 12104def L4_loadri_ap : HInst< 12105(outs IntRegs:$Rd32, IntRegs:$Re32), 12106(ins u32_0Imm:$II), 12107"$Rd32 = memw($Re32=#$II)", 12108tc_3b5b7ef9, TypeLD>, Enc_323f2d { 12109let Inst{7-7} = 0b0; 12110let Inst{13-12} = 0b01; 12111let Inst{31-21} = 0b10011011100; 12112let hasNewValue = 1; 12113let opNewValue = 0; 12114let addrMode = AbsoluteSet; 12115let accessSize = WordAccess; 12116let mayLoad = 1; 12117let isExtended = 1; 12118let DecoderNamespace = "MustExtend"; 12119let isExtendable = 1; 12120let opExtendable = 2; 12121let isExtentSigned = 0; 12122let opExtentBits = 6; 12123let opExtentAlign = 0; 12124} 12125def L4_loadri_rr : HInst< 12126(outs IntRegs:$Rd32), 12127(ins IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), 12128"$Rd32 = memw($Rs32+$Rt32<<#$Ii)", 12129tc_bf061958, TypeLD>, Enc_da664b, AddrModeRel, ImmRegShl { 12130let Inst{6-5} = 0b00; 12131let Inst{31-21} = 0b00111010100; 12132let hasNewValue = 1; 12133let opNewValue = 0; 12134let addrMode = BaseRegOffset; 12135let accessSize = WordAccess; 12136let mayLoad = 1; 12137let CextOpcode = "L2_loadri"; 12138let InputType = "reg"; 12139let BaseOpcode = "L4_loadri_rr"; 12140let isPredicable = 1; 12141} 12142def L4_loadri_ur : HInst< 12143(outs IntRegs:$Rd32), 12144(ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II), 12145"$Rd32 = memw($Rt32<<#$Ii+#$II)", 12146tc_bab0eed9, TypeLD>, Enc_4f677b, AddrModeRel, ImmRegShl { 12147let Inst{12-12} = 0b1; 12148let Inst{31-21} = 0b10011101100; 12149let hasNewValue = 1; 12150let opNewValue = 0; 12151let addrMode = BaseLongOffset; 12152let accessSize = WordAccess; 12153let mayLoad = 1; 12154let isExtended = 1; 12155let CextOpcode = "L2_loadri"; 12156let InputType = "imm"; 12157let DecoderNamespace = "MustExtend"; 12158let isExtendable = 1; 12159let opExtendable = 3; 12160let isExtentSigned = 0; 12161let opExtentBits = 6; 12162let opExtentAlign = 0; 12163} 12164def L4_loadrub_ap : HInst< 12165(outs IntRegs:$Rd32, IntRegs:$Re32), 12166(ins u32_0Imm:$II), 12167"$Rd32 = memub($Re32=#$II)", 12168tc_3b5b7ef9, TypeLD>, Enc_323f2d { 12169let Inst{7-7} = 0b0; 12170let Inst{13-12} = 0b01; 12171let Inst{31-21} = 0b10011011001; 12172let hasNewValue = 1; 12173let opNewValue = 0; 12174let addrMode = AbsoluteSet; 12175let accessSize = ByteAccess; 12176let mayLoad = 1; 12177let isExtended = 1; 12178let DecoderNamespace = "MustExtend"; 12179let isExtendable = 1; 12180let opExtendable = 2; 12181let isExtentSigned = 0; 12182let opExtentBits = 6; 12183let opExtentAlign = 0; 12184} 12185def L4_loadrub_rr : HInst< 12186(outs IntRegs:$Rd32), 12187(ins IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), 12188"$Rd32 = memub($Rs32+$Rt32<<#$Ii)", 12189tc_bf061958, TypeLD>, Enc_da664b, AddrModeRel, ImmRegShl { 12190let Inst{6-5} = 0b00; 12191let Inst{31-21} = 0b00111010001; 12192let hasNewValue = 1; 12193let opNewValue = 0; 12194let addrMode = BaseRegOffset; 12195let accessSize = ByteAccess; 12196let mayLoad = 1; 12197let CextOpcode = "L2_loadrub"; 12198let InputType = "reg"; 12199let BaseOpcode = "L4_loadrub_rr"; 12200let isPredicable = 1; 12201} 12202def L4_loadrub_ur : HInst< 12203(outs IntRegs:$Rd32), 12204(ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II), 12205"$Rd32 = memub($Rt32<<#$Ii+#$II)", 12206tc_bab0eed9, TypeLD>, Enc_4f677b, AddrModeRel, ImmRegShl { 12207let Inst{12-12} = 0b1; 12208let Inst{31-21} = 0b10011101001; 12209let hasNewValue = 1; 12210let opNewValue = 0; 12211let addrMode = BaseLongOffset; 12212let accessSize = ByteAccess; 12213let mayLoad = 1; 12214let isExtended = 1; 12215let CextOpcode = "L2_loadrub"; 12216let InputType = "imm"; 12217let DecoderNamespace = "MustExtend"; 12218let isExtendable = 1; 12219let opExtendable = 3; 12220let isExtentSigned = 0; 12221let opExtentBits = 6; 12222let opExtentAlign = 0; 12223} 12224def L4_loadruh_ap : HInst< 12225(outs IntRegs:$Rd32, IntRegs:$Re32), 12226(ins u32_0Imm:$II), 12227"$Rd32 = memuh($Re32=#$II)", 12228tc_3b5b7ef9, TypeLD>, Enc_323f2d { 12229let Inst{7-7} = 0b0; 12230let Inst{13-12} = 0b01; 12231let Inst{31-21} = 0b10011011011; 12232let hasNewValue = 1; 12233let opNewValue = 0; 12234let addrMode = AbsoluteSet; 12235let accessSize = HalfWordAccess; 12236let mayLoad = 1; 12237let isExtended = 1; 12238let DecoderNamespace = "MustExtend"; 12239let isExtendable = 1; 12240let opExtendable = 2; 12241let isExtentSigned = 0; 12242let opExtentBits = 6; 12243let opExtentAlign = 0; 12244} 12245def L4_loadruh_rr : HInst< 12246(outs IntRegs:$Rd32), 12247(ins IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), 12248"$Rd32 = memuh($Rs32+$Rt32<<#$Ii)", 12249tc_bf061958, TypeLD>, Enc_da664b, AddrModeRel, ImmRegShl { 12250let Inst{6-5} = 0b00; 12251let Inst{31-21} = 0b00111010011; 12252let hasNewValue = 1; 12253let opNewValue = 0; 12254let addrMode = BaseRegOffset; 12255let accessSize = HalfWordAccess; 12256let mayLoad = 1; 12257let CextOpcode = "L2_loadruh"; 12258let InputType = "reg"; 12259let BaseOpcode = "L4_loadruh_rr"; 12260let isPredicable = 1; 12261} 12262def L4_loadruh_ur : HInst< 12263(outs IntRegs:$Rd32), 12264(ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II), 12265"$Rd32 = memuh($Rt32<<#$Ii+#$II)", 12266tc_bab0eed9, TypeLD>, Enc_4f677b, AddrModeRel, ImmRegShl { 12267let Inst{12-12} = 0b1; 12268let Inst{31-21} = 0b10011101011; 12269let hasNewValue = 1; 12270let opNewValue = 0; 12271let addrMode = BaseLongOffset; 12272let accessSize = HalfWordAccess; 12273let mayLoad = 1; 12274let isExtended = 1; 12275let CextOpcode = "L2_loadruh"; 12276let InputType = "imm"; 12277let DecoderNamespace = "MustExtend"; 12278let isExtendable = 1; 12279let opExtendable = 3; 12280let isExtentSigned = 0; 12281let opExtentBits = 6; 12282let opExtentAlign = 0; 12283} 12284def L4_or_memopb_io : HInst< 12285(outs), 12286(ins IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Rt32), 12287"memb($Rs32+#$Ii) |= $Rt32", 12288tc_7186d325, TypeV4LDST>, Enc_d44e31 { 12289let Inst{6-5} = 0b11; 12290let Inst{13-13} = 0b0; 12291let Inst{31-21} = 0b00111110000; 12292let addrMode = BaseImmOffset; 12293let accessSize = ByteAccess; 12294let mayLoad = 1; 12295let isRestrictNoSlot1Store = 1; 12296let mayStore = 1; 12297let isExtendable = 1; 12298let opExtendable = 1; 12299let isExtentSigned = 0; 12300let opExtentBits = 6; 12301let opExtentAlign = 0; 12302} 12303def L4_or_memopb_zomap : HInst< 12304(outs), 12305(ins IntRegs:$Rs32, IntRegs:$Rt32), 12306"memb($Rs32) |= $Rt32", 12307tc_7186d325, TypeMAPPING> { 12308let isPseudo = 1; 12309let isCodeGenOnly = 1; 12310} 12311def L4_or_memoph_io : HInst< 12312(outs), 12313(ins IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32), 12314"memh($Rs32+#$Ii) |= $Rt32", 12315tc_7186d325, TypeV4LDST>, Enc_163a3c { 12316let Inst{6-5} = 0b11; 12317let Inst{13-13} = 0b0; 12318let Inst{31-21} = 0b00111110001; 12319let addrMode = BaseImmOffset; 12320let accessSize = HalfWordAccess; 12321let mayLoad = 1; 12322let isRestrictNoSlot1Store = 1; 12323let mayStore = 1; 12324let isExtendable = 1; 12325let opExtendable = 1; 12326let isExtentSigned = 0; 12327let opExtentBits = 7; 12328let opExtentAlign = 1; 12329} 12330def L4_or_memoph_zomap : HInst< 12331(outs), 12332(ins IntRegs:$Rs32, IntRegs:$Rt32), 12333"memh($Rs32) |= $Rt32", 12334tc_7186d325, TypeMAPPING> { 12335let isPseudo = 1; 12336let isCodeGenOnly = 1; 12337} 12338def L4_or_memopw_io : HInst< 12339(outs), 12340(ins IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Rt32), 12341"memw($Rs32+#$Ii) |= $Rt32", 12342tc_7186d325, TypeV4LDST>, Enc_226535 { 12343let Inst{6-5} = 0b11; 12344let Inst{13-13} = 0b0; 12345let Inst{31-21} = 0b00111110010; 12346let addrMode = BaseImmOffset; 12347let accessSize = WordAccess; 12348let mayLoad = 1; 12349let isRestrictNoSlot1Store = 1; 12350let mayStore = 1; 12351let isExtendable = 1; 12352let opExtendable = 1; 12353let isExtentSigned = 0; 12354let opExtentBits = 8; 12355let opExtentAlign = 2; 12356} 12357def L4_or_memopw_zomap : HInst< 12358(outs), 12359(ins IntRegs:$Rs32, IntRegs:$Rt32), 12360"memw($Rs32) |= $Rt32", 12361tc_7186d325, TypeMAPPING> { 12362let isPseudo = 1; 12363let isCodeGenOnly = 1; 12364} 12365def L4_ploadrbf_abs : HInst< 12366(outs IntRegs:$Rd32), 12367(ins PredRegs:$Pt4, u32_0Imm:$Ii), 12368"if (!$Pt4) $Rd32 = memb(#$Ii)", 12369tc_7646c131, TypeLD>, Enc_2301d6, AddrModeRel { 12370let Inst{7-5} = 0b100; 12371let Inst{13-11} = 0b101; 12372let Inst{31-21} = 0b10011111000; 12373let isPredicated = 1; 12374let isPredicatedFalse = 1; 12375let hasNewValue = 1; 12376let opNewValue = 0; 12377let addrMode = Absolute; 12378let accessSize = ByteAccess; 12379let mayLoad = 1; 12380let isExtended = 1; 12381let CextOpcode = "L2_loadrb"; 12382let BaseOpcode = "L4_loadrb_abs"; 12383let DecoderNamespace = "MustExtend"; 12384let isExtendable = 1; 12385let opExtendable = 2; 12386let isExtentSigned = 0; 12387let opExtentBits = 6; 12388let opExtentAlign = 0; 12389} 12390def L4_ploadrbf_rr : HInst< 12391(outs IntRegs:$Rd32), 12392(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), 12393"if (!$Pv4) $Rd32 = memb($Rs32+$Rt32<<#$Ii)", 12394tc_e4b3cb20, TypeLD>, Enc_2e1979, AddrModeRel { 12395let Inst{31-21} = 0b00110001000; 12396let isPredicated = 1; 12397let isPredicatedFalse = 1; 12398let hasNewValue = 1; 12399let opNewValue = 0; 12400let addrMode = BaseRegOffset; 12401let accessSize = ByteAccess; 12402let mayLoad = 1; 12403let CextOpcode = "L2_loadrb"; 12404let InputType = "reg"; 12405let BaseOpcode = "L4_loadrb_rr"; 12406} 12407def L4_ploadrbfnew_abs : HInst< 12408(outs IntRegs:$Rd32), 12409(ins PredRegs:$Pt4, u32_0Imm:$Ii), 12410"if (!$Pt4.new) $Rd32 = memb(#$Ii)", 12411tc_3b5b7ef9, TypeLD>, Enc_2301d6, AddrModeRel { 12412let Inst{7-5} = 0b100; 12413let Inst{13-11} = 0b111; 12414let Inst{31-21} = 0b10011111000; 12415let isPredicated = 1; 12416let isPredicatedFalse = 1; 12417let hasNewValue = 1; 12418let opNewValue = 0; 12419let addrMode = Absolute; 12420let accessSize = ByteAccess; 12421let isPredicatedNew = 1; 12422let mayLoad = 1; 12423let isExtended = 1; 12424let CextOpcode = "L2_loadrb"; 12425let BaseOpcode = "L4_loadrb_abs"; 12426let DecoderNamespace = "MustExtend"; 12427let isExtendable = 1; 12428let opExtendable = 2; 12429let isExtentSigned = 0; 12430let opExtentBits = 6; 12431let opExtentAlign = 0; 12432} 12433def L4_ploadrbfnew_rr : HInst< 12434(outs IntRegs:$Rd32), 12435(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), 12436"if (!$Pv4.new) $Rd32 = memb($Rs32+$Rt32<<#$Ii)", 12437tc_25a78932, TypeLD>, Enc_2e1979, AddrModeRel { 12438let Inst{31-21} = 0b00110011000; 12439let isPredicated = 1; 12440let isPredicatedFalse = 1; 12441let hasNewValue = 1; 12442let opNewValue = 0; 12443let addrMode = BaseRegOffset; 12444let accessSize = ByteAccess; 12445let isPredicatedNew = 1; 12446let mayLoad = 1; 12447let CextOpcode = "L2_loadrb"; 12448let InputType = "reg"; 12449let BaseOpcode = "L4_loadrb_rr"; 12450} 12451def L4_ploadrbt_abs : HInst< 12452(outs IntRegs:$Rd32), 12453(ins PredRegs:$Pt4, u32_0Imm:$Ii), 12454"if ($Pt4) $Rd32 = memb(#$Ii)", 12455tc_7646c131, TypeLD>, Enc_2301d6, AddrModeRel { 12456let Inst{7-5} = 0b100; 12457let Inst{13-11} = 0b100; 12458let Inst{31-21} = 0b10011111000; 12459let isPredicated = 1; 12460let hasNewValue = 1; 12461let opNewValue = 0; 12462let addrMode = Absolute; 12463let accessSize = ByteAccess; 12464let mayLoad = 1; 12465let isExtended = 1; 12466let CextOpcode = "L2_loadrb"; 12467let BaseOpcode = "L4_loadrb_abs"; 12468let DecoderNamespace = "MustExtend"; 12469let isExtendable = 1; 12470let opExtendable = 2; 12471let isExtentSigned = 0; 12472let opExtentBits = 6; 12473let opExtentAlign = 0; 12474} 12475def L4_ploadrbt_rr : HInst< 12476(outs IntRegs:$Rd32), 12477(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), 12478"if ($Pv4) $Rd32 = memb($Rs32+$Rt32<<#$Ii)", 12479tc_e4b3cb20, TypeLD>, Enc_2e1979, AddrModeRel { 12480let Inst{31-21} = 0b00110000000; 12481let isPredicated = 1; 12482let hasNewValue = 1; 12483let opNewValue = 0; 12484let addrMode = BaseRegOffset; 12485let accessSize = ByteAccess; 12486let mayLoad = 1; 12487let CextOpcode = "L2_loadrb"; 12488let InputType = "reg"; 12489let BaseOpcode = "L4_loadrb_rr"; 12490} 12491def L4_ploadrbtnew_abs : HInst< 12492(outs IntRegs:$Rd32), 12493(ins PredRegs:$Pt4, u32_0Imm:$Ii), 12494"if ($Pt4.new) $Rd32 = memb(#$Ii)", 12495tc_3b5b7ef9, TypeLD>, Enc_2301d6, AddrModeRel { 12496let Inst{7-5} = 0b100; 12497let Inst{13-11} = 0b110; 12498let Inst{31-21} = 0b10011111000; 12499let isPredicated = 1; 12500let hasNewValue = 1; 12501let opNewValue = 0; 12502let addrMode = Absolute; 12503let accessSize = ByteAccess; 12504let isPredicatedNew = 1; 12505let mayLoad = 1; 12506let isExtended = 1; 12507let CextOpcode = "L2_loadrb"; 12508let BaseOpcode = "L4_loadrb_abs"; 12509let DecoderNamespace = "MustExtend"; 12510let isExtendable = 1; 12511let opExtendable = 2; 12512let isExtentSigned = 0; 12513let opExtentBits = 6; 12514let opExtentAlign = 0; 12515} 12516def L4_ploadrbtnew_rr : HInst< 12517(outs IntRegs:$Rd32), 12518(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), 12519"if ($Pv4.new) $Rd32 = memb($Rs32+$Rt32<<#$Ii)", 12520tc_25a78932, TypeLD>, Enc_2e1979, AddrModeRel { 12521let Inst{31-21} = 0b00110010000; 12522let isPredicated = 1; 12523let hasNewValue = 1; 12524let opNewValue = 0; 12525let addrMode = BaseRegOffset; 12526let accessSize = ByteAccess; 12527let isPredicatedNew = 1; 12528let mayLoad = 1; 12529let CextOpcode = "L2_loadrb"; 12530let InputType = "reg"; 12531let BaseOpcode = "L4_loadrb_rr"; 12532} 12533def L4_ploadrdf_abs : HInst< 12534(outs DoubleRegs:$Rdd32), 12535(ins PredRegs:$Pt4, u32_0Imm:$Ii), 12536"if (!$Pt4) $Rdd32 = memd(#$Ii)", 12537tc_7646c131, TypeLD>, Enc_2a7b91, AddrModeRel { 12538let Inst{7-5} = 0b100; 12539let Inst{13-11} = 0b101; 12540let Inst{31-21} = 0b10011111110; 12541let isPredicated = 1; 12542let isPredicatedFalse = 1; 12543let addrMode = Absolute; 12544let accessSize = DoubleWordAccess; 12545let mayLoad = 1; 12546let isExtended = 1; 12547let CextOpcode = "L2_loadrd"; 12548let BaseOpcode = "L4_loadrd_abs"; 12549let DecoderNamespace = "MustExtend"; 12550let isExtendable = 1; 12551let opExtendable = 2; 12552let isExtentSigned = 0; 12553let opExtentBits = 6; 12554let opExtentAlign = 0; 12555} 12556def L4_ploadrdf_rr : HInst< 12557(outs DoubleRegs:$Rdd32), 12558(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), 12559"if (!$Pv4) $Rdd32 = memd($Rs32+$Rt32<<#$Ii)", 12560tc_e4b3cb20, TypeLD>, Enc_98c0b8, AddrModeRel { 12561let Inst{31-21} = 0b00110001110; 12562let isPredicated = 1; 12563let isPredicatedFalse = 1; 12564let addrMode = BaseRegOffset; 12565let accessSize = DoubleWordAccess; 12566let mayLoad = 1; 12567let CextOpcode = "L2_loadrd"; 12568let InputType = "reg"; 12569let BaseOpcode = "L4_loadrd_rr"; 12570} 12571def L4_ploadrdfnew_abs : HInst< 12572(outs DoubleRegs:$Rdd32), 12573(ins PredRegs:$Pt4, u32_0Imm:$Ii), 12574"if (!$Pt4.new) $Rdd32 = memd(#$Ii)", 12575tc_3b5b7ef9, TypeLD>, Enc_2a7b91, AddrModeRel { 12576let Inst{7-5} = 0b100; 12577let Inst{13-11} = 0b111; 12578let Inst{31-21} = 0b10011111110; 12579let isPredicated = 1; 12580let isPredicatedFalse = 1; 12581let addrMode = Absolute; 12582let accessSize = DoubleWordAccess; 12583let isPredicatedNew = 1; 12584let mayLoad = 1; 12585let isExtended = 1; 12586let CextOpcode = "L2_loadrd"; 12587let BaseOpcode = "L4_loadrd_abs"; 12588let DecoderNamespace = "MustExtend"; 12589let isExtendable = 1; 12590let opExtendable = 2; 12591let isExtentSigned = 0; 12592let opExtentBits = 6; 12593let opExtentAlign = 0; 12594} 12595def L4_ploadrdfnew_rr : HInst< 12596(outs DoubleRegs:$Rdd32), 12597(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), 12598"if (!$Pv4.new) $Rdd32 = memd($Rs32+$Rt32<<#$Ii)", 12599tc_25a78932, TypeLD>, Enc_98c0b8, AddrModeRel { 12600let Inst{31-21} = 0b00110011110; 12601let isPredicated = 1; 12602let isPredicatedFalse = 1; 12603let addrMode = BaseRegOffset; 12604let accessSize = DoubleWordAccess; 12605let isPredicatedNew = 1; 12606let mayLoad = 1; 12607let CextOpcode = "L2_loadrd"; 12608let InputType = "reg"; 12609let BaseOpcode = "L4_loadrd_rr"; 12610} 12611def L4_ploadrdt_abs : HInst< 12612(outs DoubleRegs:$Rdd32), 12613(ins PredRegs:$Pt4, u32_0Imm:$Ii), 12614"if ($Pt4) $Rdd32 = memd(#$Ii)", 12615tc_7646c131, TypeLD>, Enc_2a7b91, AddrModeRel { 12616let Inst{7-5} = 0b100; 12617let Inst{13-11} = 0b100; 12618let Inst{31-21} = 0b10011111110; 12619let isPredicated = 1; 12620let addrMode = Absolute; 12621let accessSize = DoubleWordAccess; 12622let mayLoad = 1; 12623let isExtended = 1; 12624let CextOpcode = "L2_loadrd"; 12625let BaseOpcode = "L4_loadrd_abs"; 12626let DecoderNamespace = "MustExtend"; 12627let isExtendable = 1; 12628let opExtendable = 2; 12629let isExtentSigned = 0; 12630let opExtentBits = 6; 12631let opExtentAlign = 0; 12632} 12633def L4_ploadrdt_rr : HInst< 12634(outs DoubleRegs:$Rdd32), 12635(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), 12636"if ($Pv4) $Rdd32 = memd($Rs32+$Rt32<<#$Ii)", 12637tc_e4b3cb20, TypeLD>, Enc_98c0b8, AddrModeRel { 12638let Inst{31-21} = 0b00110000110; 12639let isPredicated = 1; 12640let addrMode = BaseRegOffset; 12641let accessSize = DoubleWordAccess; 12642let mayLoad = 1; 12643let CextOpcode = "L2_loadrd"; 12644let InputType = "reg"; 12645let BaseOpcode = "L4_loadrd_rr"; 12646} 12647def L4_ploadrdtnew_abs : HInst< 12648(outs DoubleRegs:$Rdd32), 12649(ins PredRegs:$Pt4, u32_0Imm:$Ii), 12650"if ($Pt4.new) $Rdd32 = memd(#$Ii)", 12651tc_3b5b7ef9, TypeLD>, Enc_2a7b91, AddrModeRel { 12652let Inst{7-5} = 0b100; 12653let Inst{13-11} = 0b110; 12654let Inst{31-21} = 0b10011111110; 12655let isPredicated = 1; 12656let addrMode = Absolute; 12657let accessSize = DoubleWordAccess; 12658let isPredicatedNew = 1; 12659let mayLoad = 1; 12660let isExtended = 1; 12661let CextOpcode = "L2_loadrd"; 12662let BaseOpcode = "L4_loadrd_abs"; 12663let DecoderNamespace = "MustExtend"; 12664let isExtendable = 1; 12665let opExtendable = 2; 12666let isExtentSigned = 0; 12667let opExtentBits = 6; 12668let opExtentAlign = 0; 12669} 12670def L4_ploadrdtnew_rr : HInst< 12671(outs DoubleRegs:$Rdd32), 12672(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), 12673"if ($Pv4.new) $Rdd32 = memd($Rs32+$Rt32<<#$Ii)", 12674tc_25a78932, TypeLD>, Enc_98c0b8, AddrModeRel { 12675let Inst{31-21} = 0b00110010110; 12676let isPredicated = 1; 12677let addrMode = BaseRegOffset; 12678let accessSize = DoubleWordAccess; 12679let isPredicatedNew = 1; 12680let mayLoad = 1; 12681let CextOpcode = "L2_loadrd"; 12682let InputType = "reg"; 12683let BaseOpcode = "L4_loadrd_rr"; 12684} 12685def L4_ploadrhf_abs : HInst< 12686(outs IntRegs:$Rd32), 12687(ins PredRegs:$Pt4, u32_0Imm:$Ii), 12688"if (!$Pt4) $Rd32 = memh(#$Ii)", 12689tc_7646c131, TypeLD>, Enc_2301d6, AddrModeRel { 12690let Inst{7-5} = 0b100; 12691let Inst{13-11} = 0b101; 12692let Inst{31-21} = 0b10011111010; 12693let isPredicated = 1; 12694let isPredicatedFalse = 1; 12695let hasNewValue = 1; 12696let opNewValue = 0; 12697let addrMode = Absolute; 12698let accessSize = HalfWordAccess; 12699let mayLoad = 1; 12700let isExtended = 1; 12701let CextOpcode = "L2_loadrh"; 12702let BaseOpcode = "L4_loadrh_abs"; 12703let DecoderNamespace = "MustExtend"; 12704let isExtendable = 1; 12705let opExtendable = 2; 12706let isExtentSigned = 0; 12707let opExtentBits = 6; 12708let opExtentAlign = 0; 12709} 12710def L4_ploadrhf_rr : HInst< 12711(outs IntRegs:$Rd32), 12712(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), 12713"if (!$Pv4) $Rd32 = memh($Rs32+$Rt32<<#$Ii)", 12714tc_e4b3cb20, TypeLD>, Enc_2e1979, AddrModeRel { 12715let Inst{31-21} = 0b00110001010; 12716let isPredicated = 1; 12717let isPredicatedFalse = 1; 12718let hasNewValue = 1; 12719let opNewValue = 0; 12720let addrMode = BaseRegOffset; 12721let accessSize = HalfWordAccess; 12722let mayLoad = 1; 12723let CextOpcode = "L2_loadrh"; 12724let InputType = "reg"; 12725let BaseOpcode = "L4_loadrh_rr"; 12726} 12727def L4_ploadrhfnew_abs : HInst< 12728(outs IntRegs:$Rd32), 12729(ins PredRegs:$Pt4, u32_0Imm:$Ii), 12730"if (!$Pt4.new) $Rd32 = memh(#$Ii)", 12731tc_3b5b7ef9, TypeLD>, Enc_2301d6, AddrModeRel { 12732let Inst{7-5} = 0b100; 12733let Inst{13-11} = 0b111; 12734let Inst{31-21} = 0b10011111010; 12735let isPredicated = 1; 12736let isPredicatedFalse = 1; 12737let hasNewValue = 1; 12738let opNewValue = 0; 12739let addrMode = Absolute; 12740let accessSize = HalfWordAccess; 12741let isPredicatedNew = 1; 12742let mayLoad = 1; 12743let isExtended = 1; 12744let CextOpcode = "L2_loadrh"; 12745let BaseOpcode = "L4_loadrh_abs"; 12746let DecoderNamespace = "MustExtend"; 12747let isExtendable = 1; 12748let opExtendable = 2; 12749let isExtentSigned = 0; 12750let opExtentBits = 6; 12751let opExtentAlign = 0; 12752} 12753def L4_ploadrhfnew_rr : HInst< 12754(outs IntRegs:$Rd32), 12755(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), 12756"if (!$Pv4.new) $Rd32 = memh($Rs32+$Rt32<<#$Ii)", 12757tc_25a78932, TypeLD>, Enc_2e1979, AddrModeRel { 12758let Inst{31-21} = 0b00110011010; 12759let isPredicated = 1; 12760let isPredicatedFalse = 1; 12761let hasNewValue = 1; 12762let opNewValue = 0; 12763let addrMode = BaseRegOffset; 12764let accessSize = HalfWordAccess; 12765let isPredicatedNew = 1; 12766let mayLoad = 1; 12767let CextOpcode = "L2_loadrh"; 12768let InputType = "reg"; 12769let BaseOpcode = "L4_loadrh_rr"; 12770} 12771def L4_ploadrht_abs : HInst< 12772(outs IntRegs:$Rd32), 12773(ins PredRegs:$Pt4, u32_0Imm:$Ii), 12774"if ($Pt4) $Rd32 = memh(#$Ii)", 12775tc_7646c131, TypeLD>, Enc_2301d6, AddrModeRel { 12776let Inst{7-5} = 0b100; 12777let Inst{13-11} = 0b100; 12778let Inst{31-21} = 0b10011111010; 12779let isPredicated = 1; 12780let hasNewValue = 1; 12781let opNewValue = 0; 12782let addrMode = Absolute; 12783let accessSize = HalfWordAccess; 12784let mayLoad = 1; 12785let isExtended = 1; 12786let CextOpcode = "L2_loadrh"; 12787let BaseOpcode = "L4_loadrh_abs"; 12788let DecoderNamespace = "MustExtend"; 12789let isExtendable = 1; 12790let opExtendable = 2; 12791let isExtentSigned = 0; 12792let opExtentBits = 6; 12793let opExtentAlign = 0; 12794} 12795def L4_ploadrht_rr : HInst< 12796(outs IntRegs:$Rd32), 12797(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), 12798"if ($Pv4) $Rd32 = memh($Rs32+$Rt32<<#$Ii)", 12799tc_e4b3cb20, TypeLD>, Enc_2e1979, AddrModeRel { 12800let Inst{31-21} = 0b00110000010; 12801let isPredicated = 1; 12802let hasNewValue = 1; 12803let opNewValue = 0; 12804let addrMode = BaseRegOffset; 12805let accessSize = HalfWordAccess; 12806let mayLoad = 1; 12807let CextOpcode = "L2_loadrh"; 12808let InputType = "reg"; 12809let BaseOpcode = "L4_loadrh_rr"; 12810} 12811def L4_ploadrhtnew_abs : HInst< 12812(outs IntRegs:$Rd32), 12813(ins PredRegs:$Pt4, u32_0Imm:$Ii), 12814"if ($Pt4.new) $Rd32 = memh(#$Ii)", 12815tc_3b5b7ef9, TypeLD>, Enc_2301d6, AddrModeRel { 12816let Inst{7-5} = 0b100; 12817let Inst{13-11} = 0b110; 12818let Inst{31-21} = 0b10011111010; 12819let isPredicated = 1; 12820let hasNewValue = 1; 12821let opNewValue = 0; 12822let addrMode = Absolute; 12823let accessSize = HalfWordAccess; 12824let isPredicatedNew = 1; 12825let mayLoad = 1; 12826let isExtended = 1; 12827let CextOpcode = "L2_loadrh"; 12828let BaseOpcode = "L4_loadrh_abs"; 12829let DecoderNamespace = "MustExtend"; 12830let isExtendable = 1; 12831let opExtendable = 2; 12832let isExtentSigned = 0; 12833let opExtentBits = 6; 12834let opExtentAlign = 0; 12835} 12836def L4_ploadrhtnew_rr : HInst< 12837(outs IntRegs:$Rd32), 12838(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), 12839"if ($Pv4.new) $Rd32 = memh($Rs32+$Rt32<<#$Ii)", 12840tc_25a78932, TypeLD>, Enc_2e1979, AddrModeRel { 12841let Inst{31-21} = 0b00110010010; 12842let isPredicated = 1; 12843let hasNewValue = 1; 12844let opNewValue = 0; 12845let addrMode = BaseRegOffset; 12846let accessSize = HalfWordAccess; 12847let isPredicatedNew = 1; 12848let mayLoad = 1; 12849let CextOpcode = "L2_loadrh"; 12850let InputType = "reg"; 12851let BaseOpcode = "L4_loadrh_rr"; 12852} 12853def L4_ploadrif_abs : HInst< 12854(outs IntRegs:$Rd32), 12855(ins PredRegs:$Pt4, u32_0Imm:$Ii), 12856"if (!$Pt4) $Rd32 = memw(#$Ii)", 12857tc_7646c131, TypeLD>, Enc_2301d6, AddrModeRel { 12858let Inst{7-5} = 0b100; 12859let Inst{13-11} = 0b101; 12860let Inst{31-21} = 0b10011111100; 12861let isPredicated = 1; 12862let isPredicatedFalse = 1; 12863let hasNewValue = 1; 12864let opNewValue = 0; 12865let addrMode = Absolute; 12866let accessSize = WordAccess; 12867let mayLoad = 1; 12868let isExtended = 1; 12869let CextOpcode = "L2_loadri"; 12870let BaseOpcode = "L4_loadri_abs"; 12871let DecoderNamespace = "MustExtend"; 12872let isExtendable = 1; 12873let opExtendable = 2; 12874let isExtentSigned = 0; 12875let opExtentBits = 6; 12876let opExtentAlign = 0; 12877} 12878def L4_ploadrif_rr : HInst< 12879(outs IntRegs:$Rd32), 12880(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), 12881"if (!$Pv4) $Rd32 = memw($Rs32+$Rt32<<#$Ii)", 12882tc_e4b3cb20, TypeLD>, Enc_2e1979, AddrModeRel { 12883let Inst{31-21} = 0b00110001100; 12884let isPredicated = 1; 12885let isPredicatedFalse = 1; 12886let hasNewValue = 1; 12887let opNewValue = 0; 12888let addrMode = BaseRegOffset; 12889let accessSize = WordAccess; 12890let mayLoad = 1; 12891let CextOpcode = "L2_loadri"; 12892let InputType = "reg"; 12893let BaseOpcode = "L4_loadri_rr"; 12894} 12895def L4_ploadrifnew_abs : HInst< 12896(outs IntRegs:$Rd32), 12897(ins PredRegs:$Pt4, u32_0Imm:$Ii), 12898"if (!$Pt4.new) $Rd32 = memw(#$Ii)", 12899tc_3b5b7ef9, TypeLD>, Enc_2301d6, AddrModeRel { 12900let Inst{7-5} = 0b100; 12901let Inst{13-11} = 0b111; 12902let Inst{31-21} = 0b10011111100; 12903let isPredicated = 1; 12904let isPredicatedFalse = 1; 12905let hasNewValue = 1; 12906let opNewValue = 0; 12907let addrMode = Absolute; 12908let accessSize = WordAccess; 12909let isPredicatedNew = 1; 12910let mayLoad = 1; 12911let isExtended = 1; 12912let CextOpcode = "L2_loadri"; 12913let BaseOpcode = "L4_loadri_abs"; 12914let DecoderNamespace = "MustExtend"; 12915let isExtendable = 1; 12916let opExtendable = 2; 12917let isExtentSigned = 0; 12918let opExtentBits = 6; 12919let opExtentAlign = 0; 12920} 12921def L4_ploadrifnew_rr : HInst< 12922(outs IntRegs:$Rd32), 12923(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), 12924"if (!$Pv4.new) $Rd32 = memw($Rs32+$Rt32<<#$Ii)", 12925tc_25a78932, TypeLD>, Enc_2e1979, AddrModeRel { 12926let Inst{31-21} = 0b00110011100; 12927let isPredicated = 1; 12928let isPredicatedFalse = 1; 12929let hasNewValue = 1; 12930let opNewValue = 0; 12931let addrMode = BaseRegOffset; 12932let accessSize = WordAccess; 12933let isPredicatedNew = 1; 12934let mayLoad = 1; 12935let CextOpcode = "L2_loadri"; 12936let InputType = "reg"; 12937let BaseOpcode = "L4_loadri_rr"; 12938} 12939def L4_ploadrit_abs : HInst< 12940(outs IntRegs:$Rd32), 12941(ins PredRegs:$Pt4, u32_0Imm:$Ii), 12942"if ($Pt4) $Rd32 = memw(#$Ii)", 12943tc_7646c131, TypeLD>, Enc_2301d6, AddrModeRel { 12944let Inst{7-5} = 0b100; 12945let Inst{13-11} = 0b100; 12946let Inst{31-21} = 0b10011111100; 12947let isPredicated = 1; 12948let hasNewValue = 1; 12949let opNewValue = 0; 12950let addrMode = Absolute; 12951let accessSize = WordAccess; 12952let mayLoad = 1; 12953let isExtended = 1; 12954let CextOpcode = "L2_loadri"; 12955let BaseOpcode = "L4_loadri_abs"; 12956let DecoderNamespace = "MustExtend"; 12957let isExtendable = 1; 12958let opExtendable = 2; 12959let isExtentSigned = 0; 12960let opExtentBits = 6; 12961let opExtentAlign = 0; 12962} 12963def L4_ploadrit_rr : HInst< 12964(outs IntRegs:$Rd32), 12965(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), 12966"if ($Pv4) $Rd32 = memw($Rs32+$Rt32<<#$Ii)", 12967tc_e4b3cb20, TypeLD>, Enc_2e1979, AddrModeRel { 12968let Inst{31-21} = 0b00110000100; 12969let isPredicated = 1; 12970let hasNewValue = 1; 12971let opNewValue = 0; 12972let addrMode = BaseRegOffset; 12973let accessSize = WordAccess; 12974let mayLoad = 1; 12975let CextOpcode = "L2_loadri"; 12976let InputType = "reg"; 12977let BaseOpcode = "L4_loadri_rr"; 12978} 12979def L4_ploadritnew_abs : HInst< 12980(outs IntRegs:$Rd32), 12981(ins PredRegs:$Pt4, u32_0Imm:$Ii), 12982"if ($Pt4.new) $Rd32 = memw(#$Ii)", 12983tc_3b5b7ef9, TypeLD>, Enc_2301d6, AddrModeRel { 12984let Inst{7-5} = 0b100; 12985let Inst{13-11} = 0b110; 12986let Inst{31-21} = 0b10011111100; 12987let isPredicated = 1; 12988let hasNewValue = 1; 12989let opNewValue = 0; 12990let addrMode = Absolute; 12991let accessSize = WordAccess; 12992let isPredicatedNew = 1; 12993let mayLoad = 1; 12994let isExtended = 1; 12995let CextOpcode = "L2_loadri"; 12996let BaseOpcode = "L4_loadri_abs"; 12997let DecoderNamespace = "MustExtend"; 12998let isExtendable = 1; 12999let opExtendable = 2; 13000let isExtentSigned = 0; 13001let opExtentBits = 6; 13002let opExtentAlign = 0; 13003} 13004def L4_ploadritnew_rr : HInst< 13005(outs IntRegs:$Rd32), 13006(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), 13007"if ($Pv4.new) $Rd32 = memw($Rs32+$Rt32<<#$Ii)", 13008tc_25a78932, TypeLD>, Enc_2e1979, AddrModeRel { 13009let Inst{31-21} = 0b00110010100; 13010let isPredicated = 1; 13011let hasNewValue = 1; 13012let opNewValue = 0; 13013let addrMode = BaseRegOffset; 13014let accessSize = WordAccess; 13015let isPredicatedNew = 1; 13016let mayLoad = 1; 13017let CextOpcode = "L2_loadri"; 13018let InputType = "reg"; 13019let BaseOpcode = "L4_loadri_rr"; 13020} 13021def L4_ploadrubf_abs : HInst< 13022(outs IntRegs:$Rd32), 13023(ins PredRegs:$Pt4, u32_0Imm:$Ii), 13024"if (!$Pt4) $Rd32 = memub(#$Ii)", 13025tc_7646c131, TypeLD>, Enc_2301d6, AddrModeRel { 13026let Inst{7-5} = 0b100; 13027let Inst{13-11} = 0b101; 13028let Inst{31-21} = 0b10011111001; 13029let isPredicated = 1; 13030let isPredicatedFalse = 1; 13031let hasNewValue = 1; 13032let opNewValue = 0; 13033let addrMode = Absolute; 13034let accessSize = ByteAccess; 13035let mayLoad = 1; 13036let isExtended = 1; 13037let CextOpcode = "L2_loadrub"; 13038let BaseOpcode = "L4_loadrub_abs"; 13039let DecoderNamespace = "MustExtend"; 13040let isExtendable = 1; 13041let opExtendable = 2; 13042let isExtentSigned = 0; 13043let opExtentBits = 6; 13044let opExtentAlign = 0; 13045} 13046def L4_ploadrubf_rr : HInst< 13047(outs IntRegs:$Rd32), 13048(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), 13049"if (!$Pv4) $Rd32 = memub($Rs32+$Rt32<<#$Ii)", 13050tc_e4b3cb20, TypeLD>, Enc_2e1979, AddrModeRel { 13051let Inst{31-21} = 0b00110001001; 13052let isPredicated = 1; 13053let isPredicatedFalse = 1; 13054let hasNewValue = 1; 13055let opNewValue = 0; 13056let addrMode = BaseRegOffset; 13057let accessSize = ByteAccess; 13058let mayLoad = 1; 13059let CextOpcode = "L2_loadrub"; 13060let InputType = "reg"; 13061let BaseOpcode = "L4_loadrub_rr"; 13062} 13063def L4_ploadrubfnew_abs : HInst< 13064(outs IntRegs:$Rd32), 13065(ins PredRegs:$Pt4, u32_0Imm:$Ii), 13066"if (!$Pt4.new) $Rd32 = memub(#$Ii)", 13067tc_3b5b7ef9, TypeLD>, Enc_2301d6, AddrModeRel { 13068let Inst{7-5} = 0b100; 13069let Inst{13-11} = 0b111; 13070let Inst{31-21} = 0b10011111001; 13071let isPredicated = 1; 13072let isPredicatedFalse = 1; 13073let hasNewValue = 1; 13074let opNewValue = 0; 13075let addrMode = Absolute; 13076let accessSize = ByteAccess; 13077let isPredicatedNew = 1; 13078let mayLoad = 1; 13079let isExtended = 1; 13080let CextOpcode = "L2_loadrub"; 13081let BaseOpcode = "L4_loadrub_abs"; 13082let DecoderNamespace = "MustExtend"; 13083let isExtendable = 1; 13084let opExtendable = 2; 13085let isExtentSigned = 0; 13086let opExtentBits = 6; 13087let opExtentAlign = 0; 13088} 13089def L4_ploadrubfnew_rr : HInst< 13090(outs IntRegs:$Rd32), 13091(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), 13092"if (!$Pv4.new) $Rd32 = memub($Rs32+$Rt32<<#$Ii)", 13093tc_25a78932, TypeLD>, Enc_2e1979, AddrModeRel { 13094let Inst{31-21} = 0b00110011001; 13095let isPredicated = 1; 13096let isPredicatedFalse = 1; 13097let hasNewValue = 1; 13098let opNewValue = 0; 13099let addrMode = BaseRegOffset; 13100let accessSize = ByteAccess; 13101let isPredicatedNew = 1; 13102let mayLoad = 1; 13103let CextOpcode = "L2_loadrub"; 13104let InputType = "reg"; 13105let BaseOpcode = "L4_loadrub_rr"; 13106} 13107def L4_ploadrubt_abs : HInst< 13108(outs IntRegs:$Rd32), 13109(ins PredRegs:$Pt4, u32_0Imm:$Ii), 13110"if ($Pt4) $Rd32 = memub(#$Ii)", 13111tc_7646c131, TypeLD>, Enc_2301d6, AddrModeRel { 13112let Inst{7-5} = 0b100; 13113let Inst{13-11} = 0b100; 13114let Inst{31-21} = 0b10011111001; 13115let isPredicated = 1; 13116let hasNewValue = 1; 13117let opNewValue = 0; 13118let addrMode = Absolute; 13119let accessSize = ByteAccess; 13120let mayLoad = 1; 13121let isExtended = 1; 13122let CextOpcode = "L2_loadrub"; 13123let BaseOpcode = "L4_loadrub_abs"; 13124let DecoderNamespace = "MustExtend"; 13125let isExtendable = 1; 13126let opExtendable = 2; 13127let isExtentSigned = 0; 13128let opExtentBits = 6; 13129let opExtentAlign = 0; 13130} 13131def L4_ploadrubt_rr : HInst< 13132(outs IntRegs:$Rd32), 13133(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), 13134"if ($Pv4) $Rd32 = memub($Rs32+$Rt32<<#$Ii)", 13135tc_e4b3cb20, TypeLD>, Enc_2e1979, AddrModeRel { 13136let Inst{31-21} = 0b00110000001; 13137let isPredicated = 1; 13138let hasNewValue = 1; 13139let opNewValue = 0; 13140let addrMode = BaseRegOffset; 13141let accessSize = ByteAccess; 13142let mayLoad = 1; 13143let CextOpcode = "L2_loadrub"; 13144let InputType = "reg"; 13145let BaseOpcode = "L4_loadrub_rr"; 13146} 13147def L4_ploadrubtnew_abs : HInst< 13148(outs IntRegs:$Rd32), 13149(ins PredRegs:$Pt4, u32_0Imm:$Ii), 13150"if ($Pt4.new) $Rd32 = memub(#$Ii)", 13151tc_3b5b7ef9, TypeLD>, Enc_2301d6, AddrModeRel { 13152let Inst{7-5} = 0b100; 13153let Inst{13-11} = 0b110; 13154let Inst{31-21} = 0b10011111001; 13155let isPredicated = 1; 13156let hasNewValue = 1; 13157let opNewValue = 0; 13158let addrMode = Absolute; 13159let accessSize = ByteAccess; 13160let isPredicatedNew = 1; 13161let mayLoad = 1; 13162let isExtended = 1; 13163let CextOpcode = "L2_loadrub"; 13164let BaseOpcode = "L4_loadrub_abs"; 13165let DecoderNamespace = "MustExtend"; 13166let isExtendable = 1; 13167let opExtendable = 2; 13168let isExtentSigned = 0; 13169let opExtentBits = 6; 13170let opExtentAlign = 0; 13171} 13172def L4_ploadrubtnew_rr : HInst< 13173(outs IntRegs:$Rd32), 13174(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), 13175"if ($Pv4.new) $Rd32 = memub($Rs32+$Rt32<<#$Ii)", 13176tc_25a78932, TypeLD>, Enc_2e1979, AddrModeRel { 13177let Inst{31-21} = 0b00110010001; 13178let isPredicated = 1; 13179let hasNewValue = 1; 13180let opNewValue = 0; 13181let addrMode = BaseRegOffset; 13182let accessSize = ByteAccess; 13183let isPredicatedNew = 1; 13184let mayLoad = 1; 13185let CextOpcode = "L2_loadrub"; 13186let InputType = "reg"; 13187let BaseOpcode = "L4_loadrub_rr"; 13188} 13189def L4_ploadruhf_abs : HInst< 13190(outs IntRegs:$Rd32), 13191(ins PredRegs:$Pt4, u32_0Imm:$Ii), 13192"if (!$Pt4) $Rd32 = memuh(#$Ii)", 13193tc_7646c131, TypeLD>, Enc_2301d6, AddrModeRel { 13194let Inst{7-5} = 0b100; 13195let Inst{13-11} = 0b101; 13196let Inst{31-21} = 0b10011111011; 13197let isPredicated = 1; 13198let isPredicatedFalse = 1; 13199let hasNewValue = 1; 13200let opNewValue = 0; 13201let addrMode = Absolute; 13202let accessSize = HalfWordAccess; 13203let mayLoad = 1; 13204let isExtended = 1; 13205let CextOpcode = "L2_loadruh"; 13206let BaseOpcode = "L4_loadruh_abs"; 13207let DecoderNamespace = "MustExtend"; 13208let isExtendable = 1; 13209let opExtendable = 2; 13210let isExtentSigned = 0; 13211let opExtentBits = 6; 13212let opExtentAlign = 0; 13213} 13214def L4_ploadruhf_rr : HInst< 13215(outs IntRegs:$Rd32), 13216(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), 13217"if (!$Pv4) $Rd32 = memuh($Rs32+$Rt32<<#$Ii)", 13218tc_e4b3cb20, TypeLD>, Enc_2e1979, AddrModeRel { 13219let Inst{31-21} = 0b00110001011; 13220let isPredicated = 1; 13221let isPredicatedFalse = 1; 13222let hasNewValue = 1; 13223let opNewValue = 0; 13224let addrMode = BaseRegOffset; 13225let accessSize = HalfWordAccess; 13226let mayLoad = 1; 13227let CextOpcode = "L2_loadruh"; 13228let InputType = "reg"; 13229let BaseOpcode = "L4_loadruh_rr"; 13230} 13231def L4_ploadruhfnew_abs : HInst< 13232(outs IntRegs:$Rd32), 13233(ins PredRegs:$Pt4, u32_0Imm:$Ii), 13234"if (!$Pt4.new) $Rd32 = memuh(#$Ii)", 13235tc_3b5b7ef9, TypeLD>, Enc_2301d6, AddrModeRel { 13236let Inst{7-5} = 0b100; 13237let Inst{13-11} = 0b111; 13238let Inst{31-21} = 0b10011111011; 13239let isPredicated = 1; 13240let isPredicatedFalse = 1; 13241let hasNewValue = 1; 13242let opNewValue = 0; 13243let addrMode = Absolute; 13244let accessSize = HalfWordAccess; 13245let isPredicatedNew = 1; 13246let mayLoad = 1; 13247let isExtended = 1; 13248let CextOpcode = "L2_loadruh"; 13249let BaseOpcode = "L4_loadruh_abs"; 13250let DecoderNamespace = "MustExtend"; 13251let isExtendable = 1; 13252let opExtendable = 2; 13253let isExtentSigned = 0; 13254let opExtentBits = 6; 13255let opExtentAlign = 0; 13256} 13257def L4_ploadruhfnew_rr : HInst< 13258(outs IntRegs:$Rd32), 13259(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), 13260"if (!$Pv4.new) $Rd32 = memuh($Rs32+$Rt32<<#$Ii)", 13261tc_25a78932, TypeLD>, Enc_2e1979, AddrModeRel { 13262let Inst{31-21} = 0b00110011011; 13263let isPredicated = 1; 13264let isPredicatedFalse = 1; 13265let hasNewValue = 1; 13266let opNewValue = 0; 13267let addrMode = BaseRegOffset; 13268let accessSize = HalfWordAccess; 13269let isPredicatedNew = 1; 13270let mayLoad = 1; 13271let CextOpcode = "L2_loadruh"; 13272let InputType = "reg"; 13273let BaseOpcode = "L4_loadruh_rr"; 13274} 13275def L4_ploadruht_abs : HInst< 13276(outs IntRegs:$Rd32), 13277(ins PredRegs:$Pt4, u32_0Imm:$Ii), 13278"if ($Pt4) $Rd32 = memuh(#$Ii)", 13279tc_7646c131, TypeLD>, Enc_2301d6, AddrModeRel { 13280let Inst{7-5} = 0b100; 13281let Inst{13-11} = 0b100; 13282let Inst{31-21} = 0b10011111011; 13283let isPredicated = 1; 13284let hasNewValue = 1; 13285let opNewValue = 0; 13286let addrMode = Absolute; 13287let accessSize = HalfWordAccess; 13288let mayLoad = 1; 13289let isExtended = 1; 13290let CextOpcode = "L2_loadruh"; 13291let BaseOpcode = "L4_loadruh_abs"; 13292let DecoderNamespace = "MustExtend"; 13293let isExtendable = 1; 13294let opExtendable = 2; 13295let isExtentSigned = 0; 13296let opExtentBits = 6; 13297let opExtentAlign = 0; 13298} 13299def L4_ploadruht_rr : HInst< 13300(outs IntRegs:$Rd32), 13301(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), 13302"if ($Pv4) $Rd32 = memuh($Rs32+$Rt32<<#$Ii)", 13303tc_e4b3cb20, TypeLD>, Enc_2e1979, AddrModeRel { 13304let Inst{31-21} = 0b00110000011; 13305let isPredicated = 1; 13306let hasNewValue = 1; 13307let opNewValue = 0; 13308let addrMode = BaseRegOffset; 13309let accessSize = HalfWordAccess; 13310let mayLoad = 1; 13311let CextOpcode = "L2_loadruh"; 13312let InputType = "reg"; 13313let BaseOpcode = "L4_loadruh_rr"; 13314} 13315def L4_ploadruhtnew_abs : HInst< 13316(outs IntRegs:$Rd32), 13317(ins PredRegs:$Pt4, u32_0Imm:$Ii), 13318"if ($Pt4.new) $Rd32 = memuh(#$Ii)", 13319tc_3b5b7ef9, TypeLD>, Enc_2301d6, AddrModeRel { 13320let Inst{7-5} = 0b100; 13321let Inst{13-11} = 0b110; 13322let Inst{31-21} = 0b10011111011; 13323let isPredicated = 1; 13324let hasNewValue = 1; 13325let opNewValue = 0; 13326let addrMode = Absolute; 13327let accessSize = HalfWordAccess; 13328let isPredicatedNew = 1; 13329let mayLoad = 1; 13330let isExtended = 1; 13331let CextOpcode = "L2_loadruh"; 13332let BaseOpcode = "L4_loadruh_abs"; 13333let DecoderNamespace = "MustExtend"; 13334let isExtendable = 1; 13335let opExtendable = 2; 13336let isExtentSigned = 0; 13337let opExtentBits = 6; 13338let opExtentAlign = 0; 13339} 13340def L4_ploadruhtnew_rr : HInst< 13341(outs IntRegs:$Rd32), 13342(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), 13343"if ($Pv4.new) $Rd32 = memuh($Rs32+$Rt32<<#$Ii)", 13344tc_25a78932, TypeLD>, Enc_2e1979, AddrModeRel { 13345let Inst{31-21} = 0b00110010011; 13346let isPredicated = 1; 13347let hasNewValue = 1; 13348let opNewValue = 0; 13349let addrMode = BaseRegOffset; 13350let accessSize = HalfWordAccess; 13351let isPredicatedNew = 1; 13352let mayLoad = 1; 13353let CextOpcode = "L2_loadruh"; 13354let InputType = "reg"; 13355let BaseOpcode = "L4_loadruh_rr"; 13356} 13357def L4_return : HInst< 13358(outs DoubleRegs:$Rdd32), 13359(ins IntRegs:$Rs32), 13360"$Rdd32 = dealloc_return($Rs32):raw", 13361tc_675e4897, TypeLD>, Enc_3a3d62, PredNewRel { 13362let Inst{13-5} = 0b000000000; 13363let Inst{31-21} = 0b10010110000; 13364let isTerminator = 1; 13365let isIndirectBranch = 1; 13366let accessSize = DoubleWordAccess; 13367let mayLoad = 1; 13368let cofMax1 = 1; 13369let isRestrictNoSlot1Store = 1; 13370let isReturn = 1; 13371let Uses = [FRAMEKEY]; 13372let Defs = [PC, R29]; 13373let BaseOpcode = "L4_return"; 13374let isBarrier = 1; 13375let isPredicable = 1; 13376let isTaken = 1; 13377} 13378def L4_return_f : HInst< 13379(outs DoubleRegs:$Rdd32), 13380(ins PredRegs:$Pv4, IntRegs:$Rs32), 13381"if (!$Pv4) $Rdd32 = dealloc_return($Rs32):raw", 13382tc_2b8da4c2, TypeLD>, Enc_b7fad3, PredNewRel { 13383let Inst{7-5} = 0b000; 13384let Inst{13-10} = 0b1100; 13385let Inst{31-21} = 0b10010110000; 13386let isPredicated = 1; 13387let isPredicatedFalse = 1; 13388let isTerminator = 1; 13389let isIndirectBranch = 1; 13390let accessSize = DoubleWordAccess; 13391let mayLoad = 1; 13392let cofMax1 = 1; 13393let isRestrictNoSlot1Store = 1; 13394let isReturn = 1; 13395let Uses = [FRAMEKEY]; 13396let Defs = [PC, R29]; 13397let BaseOpcode = "L4_return"; 13398let isTaken = Inst{12}; 13399} 13400def L4_return_fnew_pnt : HInst< 13401(outs DoubleRegs:$Rdd32), 13402(ins PredRegs:$Pv4, IntRegs:$Rs32), 13403"if (!$Pv4.new) $Rdd32 = dealloc_return($Rs32):nt:raw", 13404tc_9da59d12, TypeLD>, Enc_b7fad3, PredNewRel { 13405let Inst{7-5} = 0b000; 13406let Inst{13-10} = 0b1010; 13407let Inst{31-21} = 0b10010110000; 13408let isPredicated = 1; 13409let isPredicatedFalse = 1; 13410let isTerminator = 1; 13411let isIndirectBranch = 1; 13412let accessSize = DoubleWordAccess; 13413let isPredicatedNew = 1; 13414let mayLoad = 1; 13415let cofMax1 = 1; 13416let isRestrictNoSlot1Store = 1; 13417let isReturn = 1; 13418let Uses = [FRAMEKEY]; 13419let Defs = [PC, R29]; 13420let BaseOpcode = "L4_return"; 13421let isTaken = Inst{12}; 13422} 13423def L4_return_fnew_pt : HInst< 13424(outs DoubleRegs:$Rdd32), 13425(ins PredRegs:$Pv4, IntRegs:$Rs32), 13426"if (!$Pv4.new) $Rdd32 = dealloc_return($Rs32):t:raw", 13427tc_9da59d12, TypeLD>, Enc_b7fad3, PredNewRel { 13428let Inst{7-5} = 0b000; 13429let Inst{13-10} = 0b1110; 13430let Inst{31-21} = 0b10010110000; 13431let isPredicated = 1; 13432let isPredicatedFalse = 1; 13433let isTerminator = 1; 13434let isIndirectBranch = 1; 13435let accessSize = DoubleWordAccess; 13436let isPredicatedNew = 1; 13437let mayLoad = 1; 13438let cofMax1 = 1; 13439let isRestrictNoSlot1Store = 1; 13440let isReturn = 1; 13441let Uses = [FRAMEKEY]; 13442let Defs = [PC, R29]; 13443let BaseOpcode = "L4_return"; 13444let isTaken = Inst{12}; 13445} 13446def L4_return_map_to_raw_f : HInst< 13447(outs), 13448(ins PredRegs:$Pv4), 13449"if (!$Pv4) dealloc_return", 13450tc_2b8da4c2, TypeMAPPING>, Requires<[HasV65]> { 13451let isPseudo = 1; 13452let isCodeGenOnly = 1; 13453} 13454def L4_return_map_to_raw_fnew_pnt : HInst< 13455(outs), 13456(ins PredRegs:$Pv4), 13457"if (!$Pv4.new) dealloc_return:nt", 13458tc_9da59d12, TypeMAPPING>, Requires<[HasV65]> { 13459let isPseudo = 1; 13460let isCodeGenOnly = 1; 13461} 13462def L4_return_map_to_raw_fnew_pt : HInst< 13463(outs), 13464(ins PredRegs:$Pv4), 13465"if (!$Pv4.new) dealloc_return:t", 13466tc_9da59d12, TypeMAPPING>, Requires<[HasV65]> { 13467let isPseudo = 1; 13468let isCodeGenOnly = 1; 13469} 13470def L4_return_map_to_raw_t : HInst< 13471(outs), 13472(ins PredRegs:$Pv4), 13473"if ($Pv4) dealloc_return", 13474tc_4d5fa3a1, TypeMAPPING>, Requires<[HasV65]> { 13475let isPseudo = 1; 13476let isCodeGenOnly = 1; 13477} 13478def L4_return_map_to_raw_tnew_pnt : HInst< 13479(outs), 13480(ins PredRegs:$Pv4), 13481"if ($Pv4.new) dealloc_return:nt", 13482tc_e06f432a, TypeMAPPING>, Requires<[HasV65]> { 13483let isPseudo = 1; 13484let isCodeGenOnly = 1; 13485} 13486def L4_return_map_to_raw_tnew_pt : HInst< 13487(outs), 13488(ins PredRegs:$Pv4), 13489"if ($Pv4.new) dealloc_return:t", 13490tc_e06f432a, TypeMAPPING>, Requires<[HasV65]> { 13491let isPseudo = 1; 13492let isCodeGenOnly = 1; 13493} 13494def L4_return_t : HInst< 13495(outs DoubleRegs:$Rdd32), 13496(ins PredRegs:$Pv4, IntRegs:$Rs32), 13497"if ($Pv4) $Rdd32 = dealloc_return($Rs32):raw", 13498tc_2b8da4c2, TypeLD>, Enc_b7fad3, PredNewRel { 13499let Inst{7-5} = 0b000; 13500let Inst{13-10} = 0b0100; 13501let Inst{31-21} = 0b10010110000; 13502let isPredicated = 1; 13503let isTerminator = 1; 13504let isIndirectBranch = 1; 13505let accessSize = DoubleWordAccess; 13506let mayLoad = 1; 13507let cofMax1 = 1; 13508let isRestrictNoSlot1Store = 1; 13509let isReturn = 1; 13510let Uses = [FRAMEKEY]; 13511let Defs = [PC, R29]; 13512let BaseOpcode = "L4_return"; 13513let isTaken = Inst{12}; 13514} 13515def L4_return_tnew_pnt : HInst< 13516(outs DoubleRegs:$Rdd32), 13517(ins PredRegs:$Pv4, IntRegs:$Rs32), 13518"if ($Pv4.new) $Rdd32 = dealloc_return($Rs32):nt:raw", 13519tc_9da59d12, TypeLD>, Enc_b7fad3, PredNewRel { 13520let Inst{7-5} = 0b000; 13521let Inst{13-10} = 0b0010; 13522let Inst{31-21} = 0b10010110000; 13523let isPredicated = 1; 13524let isTerminator = 1; 13525let isIndirectBranch = 1; 13526let accessSize = DoubleWordAccess; 13527let isPredicatedNew = 1; 13528let mayLoad = 1; 13529let cofMax1 = 1; 13530let isRestrictNoSlot1Store = 1; 13531let isReturn = 1; 13532let Uses = [FRAMEKEY]; 13533let Defs = [PC, R29]; 13534let BaseOpcode = "L4_return"; 13535let isTaken = Inst{12}; 13536} 13537def L4_return_tnew_pt : HInst< 13538(outs DoubleRegs:$Rdd32), 13539(ins PredRegs:$Pv4, IntRegs:$Rs32), 13540"if ($Pv4.new) $Rdd32 = dealloc_return($Rs32):t:raw", 13541tc_9da59d12, TypeLD>, Enc_b7fad3, PredNewRel { 13542let Inst{7-5} = 0b000; 13543let Inst{13-10} = 0b0110; 13544let Inst{31-21} = 0b10010110000; 13545let isPredicated = 1; 13546let isTerminator = 1; 13547let isIndirectBranch = 1; 13548let accessSize = DoubleWordAccess; 13549let isPredicatedNew = 1; 13550let mayLoad = 1; 13551let cofMax1 = 1; 13552let isRestrictNoSlot1Store = 1; 13553let isReturn = 1; 13554let Uses = [FRAMEKEY]; 13555let Defs = [PC, R29]; 13556let BaseOpcode = "L4_return"; 13557let isTaken = Inst{12}; 13558} 13559def L4_sub_memopb_io : HInst< 13560(outs), 13561(ins IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Rt32), 13562"memb($Rs32+#$Ii) -= $Rt32", 13563tc_7186d325, TypeV4LDST>, Enc_d44e31 { 13564let Inst{6-5} = 0b01; 13565let Inst{13-13} = 0b0; 13566let Inst{31-21} = 0b00111110000; 13567let addrMode = BaseImmOffset; 13568let accessSize = ByteAccess; 13569let mayLoad = 1; 13570let isRestrictNoSlot1Store = 1; 13571let mayStore = 1; 13572let isExtendable = 1; 13573let opExtendable = 1; 13574let isExtentSigned = 0; 13575let opExtentBits = 6; 13576let opExtentAlign = 0; 13577} 13578def L4_sub_memopb_zomap : HInst< 13579(outs), 13580(ins IntRegs:$Rs32, IntRegs:$Rt32), 13581"memb($Rs32) -= $Rt32", 13582tc_7186d325, TypeMAPPING> { 13583let isPseudo = 1; 13584let isCodeGenOnly = 1; 13585} 13586def L4_sub_memoph_io : HInst< 13587(outs), 13588(ins IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32), 13589"memh($Rs32+#$Ii) -= $Rt32", 13590tc_7186d325, TypeV4LDST>, Enc_163a3c { 13591let Inst{6-5} = 0b01; 13592let Inst{13-13} = 0b0; 13593let Inst{31-21} = 0b00111110001; 13594let addrMode = BaseImmOffset; 13595let accessSize = HalfWordAccess; 13596let mayLoad = 1; 13597let isRestrictNoSlot1Store = 1; 13598let mayStore = 1; 13599let isExtendable = 1; 13600let opExtendable = 1; 13601let isExtentSigned = 0; 13602let opExtentBits = 7; 13603let opExtentAlign = 1; 13604} 13605def L4_sub_memoph_zomap : HInst< 13606(outs), 13607(ins IntRegs:$Rs32, IntRegs:$Rt32), 13608"memh($Rs32) -= $Rt32", 13609tc_7186d325, TypeMAPPING> { 13610let isPseudo = 1; 13611let isCodeGenOnly = 1; 13612} 13613def L4_sub_memopw_io : HInst< 13614(outs), 13615(ins IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Rt32), 13616"memw($Rs32+#$Ii) -= $Rt32", 13617tc_7186d325, TypeV4LDST>, Enc_226535 { 13618let Inst{6-5} = 0b01; 13619let Inst{13-13} = 0b0; 13620let Inst{31-21} = 0b00111110010; 13621let addrMode = BaseImmOffset; 13622let accessSize = WordAccess; 13623let mayLoad = 1; 13624let isRestrictNoSlot1Store = 1; 13625let mayStore = 1; 13626let isExtendable = 1; 13627let opExtendable = 1; 13628let isExtentSigned = 0; 13629let opExtentBits = 8; 13630let opExtentAlign = 2; 13631} 13632def L4_sub_memopw_zomap : HInst< 13633(outs), 13634(ins IntRegs:$Rs32, IntRegs:$Rt32), 13635"memw($Rs32) -= $Rt32", 13636tc_7186d325, TypeMAPPING> { 13637let isPseudo = 1; 13638let isCodeGenOnly = 1; 13639} 13640def L6_deallocframe_map_to_raw : HInst< 13641(outs), 13642(ins), 13643"deallocframe", 13644tc_15aa71c5, TypeMAPPING>, Requires<[HasV65]> { 13645let isPseudo = 1; 13646let isCodeGenOnly = 1; 13647} 13648def L6_memcpy : HInst< 13649(outs), 13650(ins IntRegs:$Rs32, IntRegs:$Rt32, ModRegs:$Mu2), 13651"memcpy($Rs32,$Rt32,$Mu2)", 13652tc_a6b1eca9, TypeLD>, Enc_a75aa6, Requires<[HasV66]> { 13653let Inst{7-0} = 0b01000000; 13654let Inst{31-21} = 0b10010010000; 13655let mayLoad = 1; 13656let isSolo = 1; 13657let mayStore = 1; 13658} 13659def L6_return_map_to_raw : HInst< 13660(outs), 13661(ins), 13662"dealloc_return", 13663tc_675e4897, TypeMAPPING>, Requires<[HasV65]> { 13664let isPseudo = 1; 13665let isCodeGenOnly = 1; 13666} 13667def M2_acci : HInst< 13668(outs IntRegs:$Rx32), 13669(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), 13670"$Rx32 += add($Rs32,$Rt32)", 13671tc_f675fee8, TypeM>, Enc_2ae154, ImmRegRel { 13672let Inst{7-5} = 0b001; 13673let Inst{13-13} = 0b0; 13674let Inst{31-21} = 0b11101111000; 13675let hasNewValue = 1; 13676let opNewValue = 0; 13677let prefersSlot3 = 1; 13678let CextOpcode = "M2_acci"; 13679let InputType = "reg"; 13680let Constraints = "$Rx32 = $Rx32in"; 13681} 13682def M2_accii : HInst< 13683(outs IntRegs:$Rx32), 13684(ins IntRegs:$Rx32in, IntRegs:$Rs32, s32_0Imm:$Ii), 13685"$Rx32 += add($Rs32,#$Ii)", 13686tc_f675fee8, TypeM>, Enc_c90aca, ImmRegRel { 13687let Inst{13-13} = 0b0; 13688let Inst{31-21} = 0b11100010000; 13689let hasNewValue = 1; 13690let opNewValue = 0; 13691let prefersSlot3 = 1; 13692let CextOpcode = "M2_acci"; 13693let InputType = "imm"; 13694let isExtendable = 1; 13695let opExtendable = 3; 13696let isExtentSigned = 1; 13697let opExtentBits = 8; 13698let opExtentAlign = 0; 13699let Constraints = "$Rx32 = $Rx32in"; 13700} 13701def M2_cmaci_s0 : HInst< 13702(outs DoubleRegs:$Rxx32), 13703(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), 13704"$Rxx32 += cmpyi($Rs32,$Rt32)", 13705tc_d773585a, TypeM>, Enc_61f0b0 { 13706let Inst{7-5} = 0b001; 13707let Inst{13-13} = 0b0; 13708let Inst{31-21} = 0b11100111000; 13709let prefersSlot3 = 1; 13710let Constraints = "$Rxx32 = $Rxx32in"; 13711} 13712def M2_cmacr_s0 : HInst< 13713(outs DoubleRegs:$Rxx32), 13714(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), 13715"$Rxx32 += cmpyr($Rs32,$Rt32)", 13716tc_d773585a, TypeM>, Enc_61f0b0 { 13717let Inst{7-5} = 0b010; 13718let Inst{13-13} = 0b0; 13719let Inst{31-21} = 0b11100111000; 13720let prefersSlot3 = 1; 13721let Constraints = "$Rxx32 = $Rxx32in"; 13722} 13723def M2_cmacs_s0 : HInst< 13724(outs DoubleRegs:$Rxx32), 13725(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), 13726"$Rxx32 += cmpy($Rs32,$Rt32):sat", 13727tc_d773585a, TypeM>, Enc_61f0b0 { 13728let Inst{7-5} = 0b110; 13729let Inst{13-13} = 0b0; 13730let Inst{31-21} = 0b11100111000; 13731let prefersSlot3 = 1; 13732let Defs = [USR_OVF]; 13733let Constraints = "$Rxx32 = $Rxx32in"; 13734} 13735def M2_cmacs_s1 : HInst< 13736(outs DoubleRegs:$Rxx32), 13737(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), 13738"$Rxx32 += cmpy($Rs32,$Rt32):<<1:sat", 13739tc_d773585a, TypeM>, Enc_61f0b0 { 13740let Inst{7-5} = 0b110; 13741let Inst{13-13} = 0b0; 13742let Inst{31-21} = 0b11100111100; 13743let prefersSlot3 = 1; 13744let Defs = [USR_OVF]; 13745let Constraints = "$Rxx32 = $Rxx32in"; 13746} 13747def M2_cmacsc_s0 : HInst< 13748(outs DoubleRegs:$Rxx32), 13749(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), 13750"$Rxx32 += cmpy($Rs32,$Rt32*):sat", 13751tc_d773585a, TypeM>, Enc_61f0b0 { 13752let Inst{7-5} = 0b110; 13753let Inst{13-13} = 0b0; 13754let Inst{31-21} = 0b11100111010; 13755let prefersSlot3 = 1; 13756let Defs = [USR_OVF]; 13757let Constraints = "$Rxx32 = $Rxx32in"; 13758} 13759def M2_cmacsc_s1 : HInst< 13760(outs DoubleRegs:$Rxx32), 13761(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), 13762"$Rxx32 += cmpy($Rs32,$Rt32*):<<1:sat", 13763tc_d773585a, TypeM>, Enc_61f0b0 { 13764let Inst{7-5} = 0b110; 13765let Inst{13-13} = 0b0; 13766let Inst{31-21} = 0b11100111110; 13767let prefersSlot3 = 1; 13768let Defs = [USR_OVF]; 13769let Constraints = "$Rxx32 = $Rxx32in"; 13770} 13771def M2_cmpyi_s0 : HInst< 13772(outs DoubleRegs:$Rdd32), 13773(ins IntRegs:$Rs32, IntRegs:$Rt32), 13774"$Rdd32 = cmpyi($Rs32,$Rt32)", 13775tc_bafaade3, TypeM>, Enc_be32a5 { 13776let Inst{7-5} = 0b001; 13777let Inst{13-13} = 0b0; 13778let Inst{31-21} = 0b11100101000; 13779let prefersSlot3 = 1; 13780} 13781def M2_cmpyr_s0 : HInst< 13782(outs DoubleRegs:$Rdd32), 13783(ins IntRegs:$Rs32, IntRegs:$Rt32), 13784"$Rdd32 = cmpyr($Rs32,$Rt32)", 13785tc_bafaade3, TypeM>, Enc_be32a5 { 13786let Inst{7-5} = 0b010; 13787let Inst{13-13} = 0b0; 13788let Inst{31-21} = 0b11100101000; 13789let prefersSlot3 = 1; 13790} 13791def M2_cmpyrs_s0 : HInst< 13792(outs IntRegs:$Rd32), 13793(ins IntRegs:$Rs32, IntRegs:$Rt32), 13794"$Rd32 = cmpy($Rs32,$Rt32):rnd:sat", 13795tc_bafaade3, TypeM>, Enc_5ab2be { 13796let Inst{7-5} = 0b110; 13797let Inst{13-13} = 0b0; 13798let Inst{31-21} = 0b11101101001; 13799let hasNewValue = 1; 13800let opNewValue = 0; 13801let prefersSlot3 = 1; 13802let Defs = [USR_OVF]; 13803} 13804def M2_cmpyrs_s1 : HInst< 13805(outs IntRegs:$Rd32), 13806(ins IntRegs:$Rs32, IntRegs:$Rt32), 13807"$Rd32 = cmpy($Rs32,$Rt32):<<1:rnd:sat", 13808tc_bafaade3, TypeM>, Enc_5ab2be { 13809let Inst{7-5} = 0b110; 13810let Inst{13-13} = 0b0; 13811let Inst{31-21} = 0b11101101101; 13812let hasNewValue = 1; 13813let opNewValue = 0; 13814let prefersSlot3 = 1; 13815let Defs = [USR_OVF]; 13816} 13817def M2_cmpyrsc_s0 : HInst< 13818(outs IntRegs:$Rd32), 13819(ins IntRegs:$Rs32, IntRegs:$Rt32), 13820"$Rd32 = cmpy($Rs32,$Rt32*):rnd:sat", 13821tc_bafaade3, TypeM>, Enc_5ab2be { 13822let Inst{7-5} = 0b110; 13823let Inst{13-13} = 0b0; 13824let Inst{31-21} = 0b11101101011; 13825let hasNewValue = 1; 13826let opNewValue = 0; 13827let prefersSlot3 = 1; 13828let Defs = [USR_OVF]; 13829} 13830def M2_cmpyrsc_s1 : HInst< 13831(outs IntRegs:$Rd32), 13832(ins IntRegs:$Rs32, IntRegs:$Rt32), 13833"$Rd32 = cmpy($Rs32,$Rt32*):<<1:rnd:sat", 13834tc_bafaade3, TypeM>, Enc_5ab2be { 13835let Inst{7-5} = 0b110; 13836let Inst{13-13} = 0b0; 13837let Inst{31-21} = 0b11101101111; 13838let hasNewValue = 1; 13839let opNewValue = 0; 13840let prefersSlot3 = 1; 13841let Defs = [USR_OVF]; 13842} 13843def M2_cmpys_s0 : HInst< 13844(outs DoubleRegs:$Rdd32), 13845(ins IntRegs:$Rs32, IntRegs:$Rt32), 13846"$Rdd32 = cmpy($Rs32,$Rt32):sat", 13847tc_bafaade3, TypeM>, Enc_be32a5 { 13848let Inst{7-5} = 0b110; 13849let Inst{13-13} = 0b0; 13850let Inst{31-21} = 0b11100101000; 13851let prefersSlot3 = 1; 13852let Defs = [USR_OVF]; 13853} 13854def M2_cmpys_s1 : HInst< 13855(outs DoubleRegs:$Rdd32), 13856(ins IntRegs:$Rs32, IntRegs:$Rt32), 13857"$Rdd32 = cmpy($Rs32,$Rt32):<<1:sat", 13858tc_bafaade3, TypeM>, Enc_be32a5 { 13859let Inst{7-5} = 0b110; 13860let Inst{13-13} = 0b0; 13861let Inst{31-21} = 0b11100101100; 13862let prefersSlot3 = 1; 13863let Defs = [USR_OVF]; 13864} 13865def M2_cmpysc_s0 : HInst< 13866(outs DoubleRegs:$Rdd32), 13867(ins IntRegs:$Rs32, IntRegs:$Rt32), 13868"$Rdd32 = cmpy($Rs32,$Rt32*):sat", 13869tc_bafaade3, TypeM>, Enc_be32a5 { 13870let Inst{7-5} = 0b110; 13871let Inst{13-13} = 0b0; 13872let Inst{31-21} = 0b11100101010; 13873let prefersSlot3 = 1; 13874let Defs = [USR_OVF]; 13875} 13876def M2_cmpysc_s1 : HInst< 13877(outs DoubleRegs:$Rdd32), 13878(ins IntRegs:$Rs32, IntRegs:$Rt32), 13879"$Rdd32 = cmpy($Rs32,$Rt32*):<<1:sat", 13880tc_bafaade3, TypeM>, Enc_be32a5 { 13881let Inst{7-5} = 0b110; 13882let Inst{13-13} = 0b0; 13883let Inst{31-21} = 0b11100101110; 13884let prefersSlot3 = 1; 13885let Defs = [USR_OVF]; 13886} 13887def M2_cnacs_s0 : HInst< 13888(outs DoubleRegs:$Rxx32), 13889(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), 13890"$Rxx32 -= cmpy($Rs32,$Rt32):sat", 13891tc_d773585a, TypeM>, Enc_61f0b0 { 13892let Inst{7-5} = 0b111; 13893let Inst{13-13} = 0b0; 13894let Inst{31-21} = 0b11100111000; 13895let prefersSlot3 = 1; 13896let Defs = [USR_OVF]; 13897let Constraints = "$Rxx32 = $Rxx32in"; 13898} 13899def M2_cnacs_s1 : HInst< 13900(outs DoubleRegs:$Rxx32), 13901(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), 13902"$Rxx32 -= cmpy($Rs32,$Rt32):<<1:sat", 13903tc_d773585a, TypeM>, Enc_61f0b0 { 13904let Inst{7-5} = 0b111; 13905let Inst{13-13} = 0b0; 13906let Inst{31-21} = 0b11100111100; 13907let prefersSlot3 = 1; 13908let Defs = [USR_OVF]; 13909let Constraints = "$Rxx32 = $Rxx32in"; 13910} 13911def M2_cnacsc_s0 : HInst< 13912(outs DoubleRegs:$Rxx32), 13913(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), 13914"$Rxx32 -= cmpy($Rs32,$Rt32*):sat", 13915tc_d773585a, TypeM>, Enc_61f0b0 { 13916let Inst{7-5} = 0b111; 13917let Inst{13-13} = 0b0; 13918let Inst{31-21} = 0b11100111010; 13919let prefersSlot3 = 1; 13920let Defs = [USR_OVF]; 13921let Constraints = "$Rxx32 = $Rxx32in"; 13922} 13923def M2_cnacsc_s1 : HInst< 13924(outs DoubleRegs:$Rxx32), 13925(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), 13926"$Rxx32 -= cmpy($Rs32,$Rt32*):<<1:sat", 13927tc_d773585a, TypeM>, Enc_61f0b0 { 13928let Inst{7-5} = 0b111; 13929let Inst{13-13} = 0b0; 13930let Inst{31-21} = 0b11100111110; 13931let prefersSlot3 = 1; 13932let Defs = [USR_OVF]; 13933let Constraints = "$Rxx32 = $Rxx32in"; 13934} 13935def M2_dpmpyss_acc_s0 : HInst< 13936(outs DoubleRegs:$Rxx32), 13937(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), 13938"$Rxx32 += mpy($Rs32,$Rt32)", 13939tc_d773585a, TypeM>, Enc_61f0b0 { 13940let Inst{7-5} = 0b000; 13941let Inst{13-13} = 0b0; 13942let Inst{31-21} = 0b11100111000; 13943let prefersSlot3 = 1; 13944let Constraints = "$Rxx32 = $Rxx32in"; 13945} 13946def M2_dpmpyss_nac_s0 : HInst< 13947(outs DoubleRegs:$Rxx32), 13948(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), 13949"$Rxx32 -= mpy($Rs32,$Rt32)", 13950tc_d773585a, TypeM>, Enc_61f0b0 { 13951let Inst{7-5} = 0b000; 13952let Inst{13-13} = 0b0; 13953let Inst{31-21} = 0b11100111001; 13954let prefersSlot3 = 1; 13955let Constraints = "$Rxx32 = $Rxx32in"; 13956} 13957def M2_dpmpyss_rnd_s0 : HInst< 13958(outs IntRegs:$Rd32), 13959(ins IntRegs:$Rs32, IntRegs:$Rt32), 13960"$Rd32 = mpy($Rs32,$Rt32):rnd", 13961tc_bafaade3, TypeM>, Enc_5ab2be { 13962let Inst{7-5} = 0b001; 13963let Inst{13-13} = 0b0; 13964let Inst{31-21} = 0b11101101001; 13965let hasNewValue = 1; 13966let opNewValue = 0; 13967let prefersSlot3 = 1; 13968} 13969def M2_dpmpyss_s0 : HInst< 13970(outs DoubleRegs:$Rdd32), 13971(ins IntRegs:$Rs32, IntRegs:$Rt32), 13972"$Rdd32 = mpy($Rs32,$Rt32)", 13973tc_bafaade3, TypeM>, Enc_be32a5 { 13974let Inst{7-5} = 0b000; 13975let Inst{13-13} = 0b0; 13976let Inst{31-21} = 0b11100101000; 13977let prefersSlot3 = 1; 13978} 13979def M2_dpmpyuu_acc_s0 : HInst< 13980(outs DoubleRegs:$Rxx32), 13981(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), 13982"$Rxx32 += mpyu($Rs32,$Rt32)", 13983tc_d773585a, TypeM>, Enc_61f0b0 { 13984let Inst{7-5} = 0b000; 13985let Inst{13-13} = 0b0; 13986let Inst{31-21} = 0b11100111010; 13987let prefersSlot3 = 1; 13988let Constraints = "$Rxx32 = $Rxx32in"; 13989} 13990def M2_dpmpyuu_nac_s0 : HInst< 13991(outs DoubleRegs:$Rxx32), 13992(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), 13993"$Rxx32 -= mpyu($Rs32,$Rt32)", 13994tc_d773585a, TypeM>, Enc_61f0b0 { 13995let Inst{7-5} = 0b000; 13996let Inst{13-13} = 0b0; 13997let Inst{31-21} = 0b11100111011; 13998let prefersSlot3 = 1; 13999let Constraints = "$Rxx32 = $Rxx32in"; 14000} 14001def M2_dpmpyuu_s0 : HInst< 14002(outs DoubleRegs:$Rdd32), 14003(ins IntRegs:$Rs32, IntRegs:$Rt32), 14004"$Rdd32 = mpyu($Rs32,$Rt32)", 14005tc_bafaade3, TypeM>, Enc_be32a5 { 14006let Inst{7-5} = 0b000; 14007let Inst{13-13} = 0b0; 14008let Inst{31-21} = 0b11100101010; 14009let prefersSlot3 = 1; 14010} 14011def M2_hmmpyh_rs1 : HInst< 14012(outs IntRegs:$Rd32), 14013(ins IntRegs:$Rs32, IntRegs:$Rt32), 14014"$Rd32 = mpy($Rs32,$Rt32.h):<<1:rnd:sat", 14015tc_bafaade3, TypeM>, Enc_5ab2be { 14016let Inst{7-5} = 0b100; 14017let Inst{13-13} = 0b0; 14018let Inst{31-21} = 0b11101101101; 14019let hasNewValue = 1; 14020let opNewValue = 0; 14021let prefersSlot3 = 1; 14022let Defs = [USR_OVF]; 14023} 14024def M2_hmmpyh_s1 : HInst< 14025(outs IntRegs:$Rd32), 14026(ins IntRegs:$Rs32, IntRegs:$Rt32), 14027"$Rd32 = mpy($Rs32,$Rt32.h):<<1:sat", 14028tc_bafaade3, TypeM>, Enc_5ab2be { 14029let Inst{7-5} = 0b000; 14030let Inst{13-13} = 0b0; 14031let Inst{31-21} = 0b11101101101; 14032let hasNewValue = 1; 14033let opNewValue = 0; 14034let prefersSlot3 = 1; 14035let Defs = [USR_OVF]; 14036} 14037def M2_hmmpyl_rs1 : HInst< 14038(outs IntRegs:$Rd32), 14039(ins IntRegs:$Rs32, IntRegs:$Rt32), 14040"$Rd32 = mpy($Rs32,$Rt32.l):<<1:rnd:sat", 14041tc_bafaade3, TypeM>, Enc_5ab2be { 14042let Inst{7-5} = 0b100; 14043let Inst{13-13} = 0b0; 14044let Inst{31-21} = 0b11101101111; 14045let hasNewValue = 1; 14046let opNewValue = 0; 14047let prefersSlot3 = 1; 14048let Defs = [USR_OVF]; 14049} 14050def M2_hmmpyl_s1 : HInst< 14051(outs IntRegs:$Rd32), 14052(ins IntRegs:$Rs32, IntRegs:$Rt32), 14053"$Rd32 = mpy($Rs32,$Rt32.l):<<1:sat", 14054tc_bafaade3, TypeM>, Enc_5ab2be { 14055let Inst{7-5} = 0b001; 14056let Inst{13-13} = 0b0; 14057let Inst{31-21} = 0b11101101101; 14058let hasNewValue = 1; 14059let opNewValue = 0; 14060let prefersSlot3 = 1; 14061let Defs = [USR_OVF]; 14062} 14063def M2_maci : HInst< 14064(outs IntRegs:$Rx32), 14065(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), 14066"$Rx32 += mpyi($Rs32,$Rt32)", 14067tc_d773585a, TypeM>, Enc_2ae154, ImmRegRel { 14068let Inst{7-5} = 0b000; 14069let Inst{13-13} = 0b0; 14070let Inst{31-21} = 0b11101111000; 14071let hasNewValue = 1; 14072let opNewValue = 0; 14073let prefersSlot3 = 1; 14074let CextOpcode = "M2_maci"; 14075let InputType = "reg"; 14076let Constraints = "$Rx32 = $Rx32in"; 14077} 14078def M2_macsin : HInst< 14079(outs IntRegs:$Rx32), 14080(ins IntRegs:$Rx32in, IntRegs:$Rs32, u32_0Imm:$Ii), 14081"$Rx32 -= mpyi($Rs32,#$Ii)", 14082tc_05d3a09b, TypeM>, Enc_c90aca { 14083let Inst{13-13} = 0b0; 14084let Inst{31-21} = 0b11100001100; 14085let hasNewValue = 1; 14086let opNewValue = 0; 14087let prefersSlot3 = 1; 14088let InputType = "imm"; 14089let isExtendable = 1; 14090let opExtendable = 3; 14091let isExtentSigned = 0; 14092let opExtentBits = 8; 14093let opExtentAlign = 0; 14094let Constraints = "$Rx32 = $Rx32in"; 14095} 14096def M2_macsip : HInst< 14097(outs IntRegs:$Rx32), 14098(ins IntRegs:$Rx32in, IntRegs:$Rs32, u32_0Imm:$Ii), 14099"$Rx32 += mpyi($Rs32,#$Ii)", 14100tc_05d3a09b, TypeM>, Enc_c90aca, ImmRegRel { 14101let Inst{13-13} = 0b0; 14102let Inst{31-21} = 0b11100001000; 14103let hasNewValue = 1; 14104let opNewValue = 0; 14105let prefersSlot3 = 1; 14106let CextOpcode = "M2_maci"; 14107let InputType = "imm"; 14108let isExtendable = 1; 14109let opExtendable = 3; 14110let isExtentSigned = 0; 14111let opExtentBits = 8; 14112let opExtentAlign = 0; 14113let Constraints = "$Rx32 = $Rx32in"; 14114} 14115def M2_mmachs_rs0 : HInst< 14116(outs DoubleRegs:$Rxx32), 14117(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 14118"$Rxx32 += vmpywoh($Rss32,$Rtt32):rnd:sat", 14119tc_d773585a, TypeM>, Enc_88c16c { 14120let Inst{7-5} = 0b111; 14121let Inst{13-13} = 0b0; 14122let Inst{31-21} = 0b11101010001; 14123let prefersSlot3 = 1; 14124let Defs = [USR_OVF]; 14125let Constraints = "$Rxx32 = $Rxx32in"; 14126} 14127def M2_mmachs_rs1 : HInst< 14128(outs DoubleRegs:$Rxx32), 14129(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 14130"$Rxx32 += vmpywoh($Rss32,$Rtt32):<<1:rnd:sat", 14131tc_d773585a, TypeM>, Enc_88c16c { 14132let Inst{7-5} = 0b111; 14133let Inst{13-13} = 0b0; 14134let Inst{31-21} = 0b11101010101; 14135let prefersSlot3 = 1; 14136let Defs = [USR_OVF]; 14137let Constraints = "$Rxx32 = $Rxx32in"; 14138} 14139def M2_mmachs_s0 : HInst< 14140(outs DoubleRegs:$Rxx32), 14141(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 14142"$Rxx32 += vmpywoh($Rss32,$Rtt32):sat", 14143tc_d773585a, TypeM>, Enc_88c16c { 14144let Inst{7-5} = 0b111; 14145let Inst{13-13} = 0b0; 14146let Inst{31-21} = 0b11101010000; 14147let prefersSlot3 = 1; 14148let Defs = [USR_OVF]; 14149let Constraints = "$Rxx32 = $Rxx32in"; 14150} 14151def M2_mmachs_s1 : HInst< 14152(outs DoubleRegs:$Rxx32), 14153(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 14154"$Rxx32 += vmpywoh($Rss32,$Rtt32):<<1:sat", 14155tc_d773585a, TypeM>, Enc_88c16c { 14156let Inst{7-5} = 0b111; 14157let Inst{13-13} = 0b0; 14158let Inst{31-21} = 0b11101010100; 14159let prefersSlot3 = 1; 14160let Defs = [USR_OVF]; 14161let Constraints = "$Rxx32 = $Rxx32in"; 14162} 14163def M2_mmacls_rs0 : HInst< 14164(outs DoubleRegs:$Rxx32), 14165(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 14166"$Rxx32 += vmpyweh($Rss32,$Rtt32):rnd:sat", 14167tc_d773585a, TypeM>, Enc_88c16c { 14168let Inst{7-5} = 0b101; 14169let Inst{13-13} = 0b0; 14170let Inst{31-21} = 0b11101010001; 14171let prefersSlot3 = 1; 14172let Defs = [USR_OVF]; 14173let Constraints = "$Rxx32 = $Rxx32in"; 14174} 14175def M2_mmacls_rs1 : HInst< 14176(outs DoubleRegs:$Rxx32), 14177(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 14178"$Rxx32 += vmpyweh($Rss32,$Rtt32):<<1:rnd:sat", 14179tc_d773585a, TypeM>, Enc_88c16c { 14180let Inst{7-5} = 0b101; 14181let Inst{13-13} = 0b0; 14182let Inst{31-21} = 0b11101010101; 14183let prefersSlot3 = 1; 14184let Defs = [USR_OVF]; 14185let Constraints = "$Rxx32 = $Rxx32in"; 14186} 14187def M2_mmacls_s0 : HInst< 14188(outs DoubleRegs:$Rxx32), 14189(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 14190"$Rxx32 += vmpyweh($Rss32,$Rtt32):sat", 14191tc_d773585a, TypeM>, Enc_88c16c { 14192let Inst{7-5} = 0b101; 14193let Inst{13-13} = 0b0; 14194let Inst{31-21} = 0b11101010000; 14195let prefersSlot3 = 1; 14196let Defs = [USR_OVF]; 14197let Constraints = "$Rxx32 = $Rxx32in"; 14198} 14199def M2_mmacls_s1 : HInst< 14200(outs DoubleRegs:$Rxx32), 14201(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 14202"$Rxx32 += vmpyweh($Rss32,$Rtt32):<<1:sat", 14203tc_d773585a, TypeM>, Enc_88c16c { 14204let Inst{7-5} = 0b101; 14205let Inst{13-13} = 0b0; 14206let Inst{31-21} = 0b11101010100; 14207let prefersSlot3 = 1; 14208let Defs = [USR_OVF]; 14209let Constraints = "$Rxx32 = $Rxx32in"; 14210} 14211def M2_mmacuhs_rs0 : HInst< 14212(outs DoubleRegs:$Rxx32), 14213(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 14214"$Rxx32 += vmpywouh($Rss32,$Rtt32):rnd:sat", 14215tc_d773585a, TypeM>, Enc_88c16c { 14216let Inst{7-5} = 0b111; 14217let Inst{13-13} = 0b0; 14218let Inst{31-21} = 0b11101010011; 14219let prefersSlot3 = 1; 14220let Defs = [USR_OVF]; 14221let Constraints = "$Rxx32 = $Rxx32in"; 14222} 14223def M2_mmacuhs_rs1 : HInst< 14224(outs DoubleRegs:$Rxx32), 14225(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 14226"$Rxx32 += vmpywouh($Rss32,$Rtt32):<<1:rnd:sat", 14227tc_d773585a, TypeM>, Enc_88c16c { 14228let Inst{7-5} = 0b111; 14229let Inst{13-13} = 0b0; 14230let Inst{31-21} = 0b11101010111; 14231let prefersSlot3 = 1; 14232let Defs = [USR_OVF]; 14233let Constraints = "$Rxx32 = $Rxx32in"; 14234} 14235def M2_mmacuhs_s0 : HInst< 14236(outs DoubleRegs:$Rxx32), 14237(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 14238"$Rxx32 += vmpywouh($Rss32,$Rtt32):sat", 14239tc_d773585a, TypeM>, Enc_88c16c { 14240let Inst{7-5} = 0b111; 14241let Inst{13-13} = 0b0; 14242let Inst{31-21} = 0b11101010010; 14243let prefersSlot3 = 1; 14244let Defs = [USR_OVF]; 14245let Constraints = "$Rxx32 = $Rxx32in"; 14246} 14247def M2_mmacuhs_s1 : HInst< 14248(outs DoubleRegs:$Rxx32), 14249(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 14250"$Rxx32 += vmpywouh($Rss32,$Rtt32):<<1:sat", 14251tc_d773585a, TypeM>, Enc_88c16c { 14252let Inst{7-5} = 0b111; 14253let Inst{13-13} = 0b0; 14254let Inst{31-21} = 0b11101010110; 14255let prefersSlot3 = 1; 14256let Defs = [USR_OVF]; 14257let Constraints = "$Rxx32 = $Rxx32in"; 14258} 14259def M2_mmaculs_rs0 : HInst< 14260(outs DoubleRegs:$Rxx32), 14261(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 14262"$Rxx32 += vmpyweuh($Rss32,$Rtt32):rnd:sat", 14263tc_d773585a, TypeM>, Enc_88c16c { 14264let Inst{7-5} = 0b101; 14265let Inst{13-13} = 0b0; 14266let Inst{31-21} = 0b11101010011; 14267let prefersSlot3 = 1; 14268let Defs = [USR_OVF]; 14269let Constraints = "$Rxx32 = $Rxx32in"; 14270} 14271def M2_mmaculs_rs1 : HInst< 14272(outs DoubleRegs:$Rxx32), 14273(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 14274"$Rxx32 += vmpyweuh($Rss32,$Rtt32):<<1:rnd:sat", 14275tc_d773585a, TypeM>, Enc_88c16c { 14276let Inst{7-5} = 0b101; 14277let Inst{13-13} = 0b0; 14278let Inst{31-21} = 0b11101010111; 14279let prefersSlot3 = 1; 14280let Defs = [USR_OVF]; 14281let Constraints = "$Rxx32 = $Rxx32in"; 14282} 14283def M2_mmaculs_s0 : HInst< 14284(outs DoubleRegs:$Rxx32), 14285(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 14286"$Rxx32 += vmpyweuh($Rss32,$Rtt32):sat", 14287tc_d773585a, TypeM>, Enc_88c16c { 14288let Inst{7-5} = 0b101; 14289let Inst{13-13} = 0b0; 14290let Inst{31-21} = 0b11101010010; 14291let prefersSlot3 = 1; 14292let Defs = [USR_OVF]; 14293let Constraints = "$Rxx32 = $Rxx32in"; 14294} 14295def M2_mmaculs_s1 : HInst< 14296(outs DoubleRegs:$Rxx32), 14297(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 14298"$Rxx32 += vmpyweuh($Rss32,$Rtt32):<<1:sat", 14299tc_d773585a, TypeM>, Enc_88c16c { 14300let Inst{7-5} = 0b101; 14301let Inst{13-13} = 0b0; 14302let Inst{31-21} = 0b11101010110; 14303let prefersSlot3 = 1; 14304let Defs = [USR_OVF]; 14305let Constraints = "$Rxx32 = $Rxx32in"; 14306} 14307def M2_mmpyh_rs0 : HInst< 14308(outs DoubleRegs:$Rdd32), 14309(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 14310"$Rdd32 = vmpywoh($Rss32,$Rtt32):rnd:sat", 14311tc_bafaade3, TypeM>, Enc_a56825 { 14312let Inst{7-5} = 0b111; 14313let Inst{13-13} = 0b0; 14314let Inst{31-21} = 0b11101000001; 14315let prefersSlot3 = 1; 14316let Defs = [USR_OVF]; 14317} 14318def M2_mmpyh_rs1 : HInst< 14319(outs DoubleRegs:$Rdd32), 14320(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 14321"$Rdd32 = vmpywoh($Rss32,$Rtt32):<<1:rnd:sat", 14322tc_bafaade3, TypeM>, Enc_a56825 { 14323let Inst{7-5} = 0b111; 14324let Inst{13-13} = 0b0; 14325let Inst{31-21} = 0b11101000101; 14326let prefersSlot3 = 1; 14327let Defs = [USR_OVF]; 14328} 14329def M2_mmpyh_s0 : HInst< 14330(outs DoubleRegs:$Rdd32), 14331(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 14332"$Rdd32 = vmpywoh($Rss32,$Rtt32):sat", 14333tc_bafaade3, TypeM>, Enc_a56825 { 14334let Inst{7-5} = 0b111; 14335let Inst{13-13} = 0b0; 14336let Inst{31-21} = 0b11101000000; 14337let prefersSlot3 = 1; 14338let Defs = [USR_OVF]; 14339} 14340def M2_mmpyh_s1 : HInst< 14341(outs DoubleRegs:$Rdd32), 14342(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 14343"$Rdd32 = vmpywoh($Rss32,$Rtt32):<<1:sat", 14344tc_bafaade3, TypeM>, Enc_a56825 { 14345let Inst{7-5} = 0b111; 14346let Inst{13-13} = 0b0; 14347let Inst{31-21} = 0b11101000100; 14348let prefersSlot3 = 1; 14349let Defs = [USR_OVF]; 14350} 14351def M2_mmpyl_rs0 : HInst< 14352(outs DoubleRegs:$Rdd32), 14353(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 14354"$Rdd32 = vmpyweh($Rss32,$Rtt32):rnd:sat", 14355tc_bafaade3, TypeM>, Enc_a56825 { 14356let Inst{7-5} = 0b101; 14357let Inst{13-13} = 0b0; 14358let Inst{31-21} = 0b11101000001; 14359let prefersSlot3 = 1; 14360let Defs = [USR_OVF]; 14361} 14362def M2_mmpyl_rs1 : HInst< 14363(outs DoubleRegs:$Rdd32), 14364(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 14365"$Rdd32 = vmpyweh($Rss32,$Rtt32):<<1:rnd:sat", 14366tc_bafaade3, TypeM>, Enc_a56825 { 14367let Inst{7-5} = 0b101; 14368let Inst{13-13} = 0b0; 14369let Inst{31-21} = 0b11101000101; 14370let prefersSlot3 = 1; 14371let Defs = [USR_OVF]; 14372} 14373def M2_mmpyl_s0 : HInst< 14374(outs DoubleRegs:$Rdd32), 14375(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 14376"$Rdd32 = vmpyweh($Rss32,$Rtt32):sat", 14377tc_bafaade3, TypeM>, Enc_a56825 { 14378let Inst{7-5} = 0b101; 14379let Inst{13-13} = 0b0; 14380let Inst{31-21} = 0b11101000000; 14381let prefersSlot3 = 1; 14382let Defs = [USR_OVF]; 14383} 14384def M2_mmpyl_s1 : HInst< 14385(outs DoubleRegs:$Rdd32), 14386(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 14387"$Rdd32 = vmpyweh($Rss32,$Rtt32):<<1:sat", 14388tc_bafaade3, TypeM>, Enc_a56825 { 14389let Inst{7-5} = 0b101; 14390let Inst{13-13} = 0b0; 14391let Inst{31-21} = 0b11101000100; 14392let prefersSlot3 = 1; 14393let Defs = [USR_OVF]; 14394} 14395def M2_mmpyuh_rs0 : HInst< 14396(outs DoubleRegs:$Rdd32), 14397(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 14398"$Rdd32 = vmpywouh($Rss32,$Rtt32):rnd:sat", 14399tc_bafaade3, TypeM>, Enc_a56825 { 14400let Inst{7-5} = 0b111; 14401let Inst{13-13} = 0b0; 14402let Inst{31-21} = 0b11101000011; 14403let prefersSlot3 = 1; 14404let Defs = [USR_OVF]; 14405} 14406def M2_mmpyuh_rs1 : HInst< 14407(outs DoubleRegs:$Rdd32), 14408(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 14409"$Rdd32 = vmpywouh($Rss32,$Rtt32):<<1:rnd:sat", 14410tc_bafaade3, TypeM>, Enc_a56825 { 14411let Inst{7-5} = 0b111; 14412let Inst{13-13} = 0b0; 14413let Inst{31-21} = 0b11101000111; 14414let prefersSlot3 = 1; 14415let Defs = [USR_OVF]; 14416} 14417def M2_mmpyuh_s0 : HInst< 14418(outs DoubleRegs:$Rdd32), 14419(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 14420"$Rdd32 = vmpywouh($Rss32,$Rtt32):sat", 14421tc_bafaade3, TypeM>, Enc_a56825 { 14422let Inst{7-5} = 0b111; 14423let Inst{13-13} = 0b0; 14424let Inst{31-21} = 0b11101000010; 14425let prefersSlot3 = 1; 14426let Defs = [USR_OVF]; 14427} 14428def M2_mmpyuh_s1 : HInst< 14429(outs DoubleRegs:$Rdd32), 14430(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 14431"$Rdd32 = vmpywouh($Rss32,$Rtt32):<<1:sat", 14432tc_bafaade3, TypeM>, Enc_a56825 { 14433let Inst{7-5} = 0b111; 14434let Inst{13-13} = 0b0; 14435let Inst{31-21} = 0b11101000110; 14436let prefersSlot3 = 1; 14437let Defs = [USR_OVF]; 14438} 14439def M2_mmpyul_rs0 : HInst< 14440(outs DoubleRegs:$Rdd32), 14441(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 14442"$Rdd32 = vmpyweuh($Rss32,$Rtt32):rnd:sat", 14443tc_bafaade3, TypeM>, Enc_a56825 { 14444let Inst{7-5} = 0b101; 14445let Inst{13-13} = 0b0; 14446let Inst{31-21} = 0b11101000011; 14447let prefersSlot3 = 1; 14448let Defs = [USR_OVF]; 14449} 14450def M2_mmpyul_rs1 : HInst< 14451(outs DoubleRegs:$Rdd32), 14452(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 14453"$Rdd32 = vmpyweuh($Rss32,$Rtt32):<<1:rnd:sat", 14454tc_bafaade3, TypeM>, Enc_a56825 { 14455let Inst{7-5} = 0b101; 14456let Inst{13-13} = 0b0; 14457let Inst{31-21} = 0b11101000111; 14458let prefersSlot3 = 1; 14459let Defs = [USR_OVF]; 14460} 14461def M2_mmpyul_s0 : HInst< 14462(outs DoubleRegs:$Rdd32), 14463(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 14464"$Rdd32 = vmpyweuh($Rss32,$Rtt32):sat", 14465tc_bafaade3, TypeM>, Enc_a56825 { 14466let Inst{7-5} = 0b101; 14467let Inst{13-13} = 0b0; 14468let Inst{31-21} = 0b11101000010; 14469let prefersSlot3 = 1; 14470let Defs = [USR_OVF]; 14471} 14472def M2_mmpyul_s1 : HInst< 14473(outs DoubleRegs:$Rdd32), 14474(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 14475"$Rdd32 = vmpyweuh($Rss32,$Rtt32):<<1:sat", 14476tc_bafaade3, TypeM>, Enc_a56825 { 14477let Inst{7-5} = 0b101; 14478let Inst{13-13} = 0b0; 14479let Inst{31-21} = 0b11101000110; 14480let prefersSlot3 = 1; 14481let Defs = [USR_OVF]; 14482} 14483def M2_mnaci : HInst< 14484(outs IntRegs:$Rx32), 14485(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), 14486"$Rx32 -= mpyi($Rs32,$Rt32)", 14487tc_bdceeac1, TypeM>, Enc_2ae154, Requires<[HasV66]> { 14488let Inst{7-5} = 0b000; 14489let Inst{13-13} = 0b0; 14490let Inst{31-21} = 0b11101111100; 14491let hasNewValue = 1; 14492let opNewValue = 0; 14493let prefersSlot3 = 1; 14494let Constraints = "$Rx32 = $Rx32in"; 14495} 14496def M2_mpy_acc_hh_s0 : HInst< 14497(outs IntRegs:$Rx32), 14498(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), 14499"$Rx32 += mpy($Rs32.h,$Rt32.h)", 14500tc_d773585a, TypeM>, Enc_2ae154 { 14501let Inst{7-5} = 0b011; 14502let Inst{13-13} = 0b0; 14503let Inst{31-21} = 0b11101110000; 14504let hasNewValue = 1; 14505let opNewValue = 0; 14506let prefersSlot3 = 1; 14507let Constraints = "$Rx32 = $Rx32in"; 14508} 14509def M2_mpy_acc_hh_s1 : HInst< 14510(outs IntRegs:$Rx32), 14511(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), 14512"$Rx32 += mpy($Rs32.h,$Rt32.h):<<1", 14513tc_d773585a, TypeM>, Enc_2ae154 { 14514let Inst{7-5} = 0b011; 14515let Inst{13-13} = 0b0; 14516let Inst{31-21} = 0b11101110100; 14517let hasNewValue = 1; 14518let opNewValue = 0; 14519let prefersSlot3 = 1; 14520let Constraints = "$Rx32 = $Rx32in"; 14521} 14522def M2_mpy_acc_hl_s0 : HInst< 14523(outs IntRegs:$Rx32), 14524(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), 14525"$Rx32 += mpy($Rs32.h,$Rt32.l)", 14526tc_d773585a, TypeM>, Enc_2ae154 { 14527let Inst{7-5} = 0b010; 14528let Inst{13-13} = 0b0; 14529let Inst{31-21} = 0b11101110000; 14530let hasNewValue = 1; 14531let opNewValue = 0; 14532let prefersSlot3 = 1; 14533let Constraints = "$Rx32 = $Rx32in"; 14534} 14535def M2_mpy_acc_hl_s1 : HInst< 14536(outs IntRegs:$Rx32), 14537(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), 14538"$Rx32 += mpy($Rs32.h,$Rt32.l):<<1", 14539tc_d773585a, TypeM>, Enc_2ae154 { 14540let Inst{7-5} = 0b010; 14541let Inst{13-13} = 0b0; 14542let Inst{31-21} = 0b11101110100; 14543let hasNewValue = 1; 14544let opNewValue = 0; 14545let prefersSlot3 = 1; 14546let Constraints = "$Rx32 = $Rx32in"; 14547} 14548def M2_mpy_acc_lh_s0 : HInst< 14549(outs IntRegs:$Rx32), 14550(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), 14551"$Rx32 += mpy($Rs32.l,$Rt32.h)", 14552tc_d773585a, TypeM>, Enc_2ae154 { 14553let Inst{7-5} = 0b001; 14554let Inst{13-13} = 0b0; 14555let Inst{31-21} = 0b11101110000; 14556let hasNewValue = 1; 14557let opNewValue = 0; 14558let prefersSlot3 = 1; 14559let Constraints = "$Rx32 = $Rx32in"; 14560} 14561def M2_mpy_acc_lh_s1 : HInst< 14562(outs IntRegs:$Rx32), 14563(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), 14564"$Rx32 += mpy($Rs32.l,$Rt32.h):<<1", 14565tc_d773585a, TypeM>, Enc_2ae154 { 14566let Inst{7-5} = 0b001; 14567let Inst{13-13} = 0b0; 14568let Inst{31-21} = 0b11101110100; 14569let hasNewValue = 1; 14570let opNewValue = 0; 14571let prefersSlot3 = 1; 14572let Constraints = "$Rx32 = $Rx32in"; 14573} 14574def M2_mpy_acc_ll_s0 : HInst< 14575(outs IntRegs:$Rx32), 14576(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), 14577"$Rx32 += mpy($Rs32.l,$Rt32.l)", 14578tc_d773585a, TypeM>, Enc_2ae154 { 14579let Inst{7-5} = 0b000; 14580let Inst{13-13} = 0b0; 14581let Inst{31-21} = 0b11101110000; 14582let hasNewValue = 1; 14583let opNewValue = 0; 14584let prefersSlot3 = 1; 14585let Constraints = "$Rx32 = $Rx32in"; 14586} 14587def M2_mpy_acc_ll_s1 : HInst< 14588(outs IntRegs:$Rx32), 14589(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), 14590"$Rx32 += mpy($Rs32.l,$Rt32.l):<<1", 14591tc_d773585a, TypeM>, Enc_2ae154 { 14592let Inst{7-5} = 0b000; 14593let Inst{13-13} = 0b0; 14594let Inst{31-21} = 0b11101110100; 14595let hasNewValue = 1; 14596let opNewValue = 0; 14597let prefersSlot3 = 1; 14598let Constraints = "$Rx32 = $Rx32in"; 14599} 14600def M2_mpy_acc_sat_hh_s0 : HInst< 14601(outs IntRegs:$Rx32), 14602(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), 14603"$Rx32 += mpy($Rs32.h,$Rt32.h):sat", 14604tc_d773585a, TypeM>, Enc_2ae154 { 14605let Inst{7-5} = 0b111; 14606let Inst{13-13} = 0b0; 14607let Inst{31-21} = 0b11101110000; 14608let hasNewValue = 1; 14609let opNewValue = 0; 14610let prefersSlot3 = 1; 14611let Defs = [USR_OVF]; 14612let Constraints = "$Rx32 = $Rx32in"; 14613} 14614def M2_mpy_acc_sat_hh_s1 : HInst< 14615(outs IntRegs:$Rx32), 14616(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), 14617"$Rx32 += mpy($Rs32.h,$Rt32.h):<<1:sat", 14618tc_d773585a, TypeM>, Enc_2ae154 { 14619let Inst{7-5} = 0b111; 14620let Inst{13-13} = 0b0; 14621let Inst{31-21} = 0b11101110100; 14622let hasNewValue = 1; 14623let opNewValue = 0; 14624let prefersSlot3 = 1; 14625let Defs = [USR_OVF]; 14626let Constraints = "$Rx32 = $Rx32in"; 14627} 14628def M2_mpy_acc_sat_hl_s0 : HInst< 14629(outs IntRegs:$Rx32), 14630(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), 14631"$Rx32 += mpy($Rs32.h,$Rt32.l):sat", 14632tc_d773585a, TypeM>, Enc_2ae154 { 14633let Inst{7-5} = 0b110; 14634let Inst{13-13} = 0b0; 14635let Inst{31-21} = 0b11101110000; 14636let hasNewValue = 1; 14637let opNewValue = 0; 14638let prefersSlot3 = 1; 14639let Defs = [USR_OVF]; 14640let Constraints = "$Rx32 = $Rx32in"; 14641} 14642def M2_mpy_acc_sat_hl_s1 : HInst< 14643(outs IntRegs:$Rx32), 14644(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), 14645"$Rx32 += mpy($Rs32.h,$Rt32.l):<<1:sat", 14646tc_d773585a, TypeM>, Enc_2ae154 { 14647let Inst{7-5} = 0b110; 14648let Inst{13-13} = 0b0; 14649let Inst{31-21} = 0b11101110100; 14650let hasNewValue = 1; 14651let opNewValue = 0; 14652let prefersSlot3 = 1; 14653let Defs = [USR_OVF]; 14654let Constraints = "$Rx32 = $Rx32in"; 14655} 14656def M2_mpy_acc_sat_lh_s0 : HInst< 14657(outs IntRegs:$Rx32), 14658(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), 14659"$Rx32 += mpy($Rs32.l,$Rt32.h):sat", 14660tc_d773585a, TypeM>, Enc_2ae154 { 14661let Inst{7-5} = 0b101; 14662let Inst{13-13} = 0b0; 14663let Inst{31-21} = 0b11101110000; 14664let hasNewValue = 1; 14665let opNewValue = 0; 14666let prefersSlot3 = 1; 14667let Defs = [USR_OVF]; 14668let Constraints = "$Rx32 = $Rx32in"; 14669} 14670def M2_mpy_acc_sat_lh_s1 : HInst< 14671(outs IntRegs:$Rx32), 14672(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), 14673"$Rx32 += mpy($Rs32.l,$Rt32.h):<<1:sat", 14674tc_d773585a, TypeM>, Enc_2ae154 { 14675let Inst{7-5} = 0b101; 14676let Inst{13-13} = 0b0; 14677let Inst{31-21} = 0b11101110100; 14678let hasNewValue = 1; 14679let opNewValue = 0; 14680let prefersSlot3 = 1; 14681let Defs = [USR_OVF]; 14682let Constraints = "$Rx32 = $Rx32in"; 14683} 14684def M2_mpy_acc_sat_ll_s0 : HInst< 14685(outs IntRegs:$Rx32), 14686(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), 14687"$Rx32 += mpy($Rs32.l,$Rt32.l):sat", 14688tc_d773585a, TypeM>, Enc_2ae154 { 14689let Inst{7-5} = 0b100; 14690let Inst{13-13} = 0b0; 14691let Inst{31-21} = 0b11101110000; 14692let hasNewValue = 1; 14693let opNewValue = 0; 14694let prefersSlot3 = 1; 14695let Defs = [USR_OVF]; 14696let Constraints = "$Rx32 = $Rx32in"; 14697} 14698def M2_mpy_acc_sat_ll_s1 : HInst< 14699(outs IntRegs:$Rx32), 14700(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), 14701"$Rx32 += mpy($Rs32.l,$Rt32.l):<<1:sat", 14702tc_d773585a, TypeM>, Enc_2ae154 { 14703let Inst{7-5} = 0b100; 14704let Inst{13-13} = 0b0; 14705let Inst{31-21} = 0b11101110100; 14706let hasNewValue = 1; 14707let opNewValue = 0; 14708let prefersSlot3 = 1; 14709let Defs = [USR_OVF]; 14710let Constraints = "$Rx32 = $Rx32in"; 14711} 14712def M2_mpy_hh_s0 : HInst< 14713(outs IntRegs:$Rd32), 14714(ins IntRegs:$Rs32, IntRegs:$Rt32), 14715"$Rd32 = mpy($Rs32.h,$Rt32.h)", 14716tc_bafaade3, TypeM>, Enc_5ab2be { 14717let Inst{7-5} = 0b011; 14718let Inst{13-13} = 0b0; 14719let Inst{31-21} = 0b11101100000; 14720let hasNewValue = 1; 14721let opNewValue = 0; 14722let prefersSlot3 = 1; 14723} 14724def M2_mpy_hh_s1 : HInst< 14725(outs IntRegs:$Rd32), 14726(ins IntRegs:$Rs32, IntRegs:$Rt32), 14727"$Rd32 = mpy($Rs32.h,$Rt32.h):<<1", 14728tc_bafaade3, TypeM>, Enc_5ab2be { 14729let Inst{7-5} = 0b011; 14730let Inst{13-13} = 0b0; 14731let Inst{31-21} = 0b11101100100; 14732let hasNewValue = 1; 14733let opNewValue = 0; 14734let prefersSlot3 = 1; 14735} 14736def M2_mpy_hl_s0 : HInst< 14737(outs IntRegs:$Rd32), 14738(ins IntRegs:$Rs32, IntRegs:$Rt32), 14739"$Rd32 = mpy($Rs32.h,$Rt32.l)", 14740tc_bafaade3, TypeM>, Enc_5ab2be { 14741let Inst{7-5} = 0b010; 14742let Inst{13-13} = 0b0; 14743let Inst{31-21} = 0b11101100000; 14744let hasNewValue = 1; 14745let opNewValue = 0; 14746let prefersSlot3 = 1; 14747} 14748def M2_mpy_hl_s1 : HInst< 14749(outs IntRegs:$Rd32), 14750(ins IntRegs:$Rs32, IntRegs:$Rt32), 14751"$Rd32 = mpy($Rs32.h,$Rt32.l):<<1", 14752tc_bafaade3, TypeM>, Enc_5ab2be { 14753let Inst{7-5} = 0b010; 14754let Inst{13-13} = 0b0; 14755let Inst{31-21} = 0b11101100100; 14756let hasNewValue = 1; 14757let opNewValue = 0; 14758let prefersSlot3 = 1; 14759} 14760def M2_mpy_lh_s0 : HInst< 14761(outs IntRegs:$Rd32), 14762(ins IntRegs:$Rs32, IntRegs:$Rt32), 14763"$Rd32 = mpy($Rs32.l,$Rt32.h)", 14764tc_bafaade3, TypeM>, Enc_5ab2be { 14765let Inst{7-5} = 0b001; 14766let Inst{13-13} = 0b0; 14767let Inst{31-21} = 0b11101100000; 14768let hasNewValue = 1; 14769let opNewValue = 0; 14770let prefersSlot3 = 1; 14771} 14772def M2_mpy_lh_s1 : HInst< 14773(outs IntRegs:$Rd32), 14774(ins IntRegs:$Rs32, IntRegs:$Rt32), 14775"$Rd32 = mpy($Rs32.l,$Rt32.h):<<1", 14776tc_bafaade3, TypeM>, Enc_5ab2be { 14777let Inst{7-5} = 0b001; 14778let Inst{13-13} = 0b0; 14779let Inst{31-21} = 0b11101100100; 14780let hasNewValue = 1; 14781let opNewValue = 0; 14782let prefersSlot3 = 1; 14783} 14784def M2_mpy_ll_s0 : HInst< 14785(outs IntRegs:$Rd32), 14786(ins IntRegs:$Rs32, IntRegs:$Rt32), 14787"$Rd32 = mpy($Rs32.l,$Rt32.l)", 14788tc_bafaade3, TypeM>, Enc_5ab2be { 14789let Inst{7-5} = 0b000; 14790let Inst{13-13} = 0b0; 14791let Inst{31-21} = 0b11101100000; 14792let hasNewValue = 1; 14793let opNewValue = 0; 14794let prefersSlot3 = 1; 14795} 14796def M2_mpy_ll_s1 : HInst< 14797(outs IntRegs:$Rd32), 14798(ins IntRegs:$Rs32, IntRegs:$Rt32), 14799"$Rd32 = mpy($Rs32.l,$Rt32.l):<<1", 14800tc_bafaade3, TypeM>, Enc_5ab2be { 14801let Inst{7-5} = 0b000; 14802let Inst{13-13} = 0b0; 14803let Inst{31-21} = 0b11101100100; 14804let hasNewValue = 1; 14805let opNewValue = 0; 14806let prefersSlot3 = 1; 14807} 14808def M2_mpy_nac_hh_s0 : HInst< 14809(outs IntRegs:$Rx32), 14810(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), 14811"$Rx32 -= mpy($Rs32.h,$Rt32.h)", 14812tc_d773585a, TypeM>, Enc_2ae154 { 14813let Inst{7-5} = 0b011; 14814let Inst{13-13} = 0b0; 14815let Inst{31-21} = 0b11101110001; 14816let hasNewValue = 1; 14817let opNewValue = 0; 14818let prefersSlot3 = 1; 14819let Constraints = "$Rx32 = $Rx32in"; 14820} 14821def M2_mpy_nac_hh_s1 : HInst< 14822(outs IntRegs:$Rx32), 14823(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), 14824"$Rx32 -= mpy($Rs32.h,$Rt32.h):<<1", 14825tc_d773585a, TypeM>, Enc_2ae154 { 14826let Inst{7-5} = 0b011; 14827let Inst{13-13} = 0b0; 14828let Inst{31-21} = 0b11101110101; 14829let hasNewValue = 1; 14830let opNewValue = 0; 14831let prefersSlot3 = 1; 14832let Constraints = "$Rx32 = $Rx32in"; 14833} 14834def M2_mpy_nac_hl_s0 : HInst< 14835(outs IntRegs:$Rx32), 14836(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), 14837"$Rx32 -= mpy($Rs32.h,$Rt32.l)", 14838tc_d773585a, TypeM>, Enc_2ae154 { 14839let Inst{7-5} = 0b010; 14840let Inst{13-13} = 0b0; 14841let Inst{31-21} = 0b11101110001; 14842let hasNewValue = 1; 14843let opNewValue = 0; 14844let prefersSlot3 = 1; 14845let Constraints = "$Rx32 = $Rx32in"; 14846} 14847def M2_mpy_nac_hl_s1 : HInst< 14848(outs IntRegs:$Rx32), 14849(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), 14850"$Rx32 -= mpy($Rs32.h,$Rt32.l):<<1", 14851tc_d773585a, TypeM>, Enc_2ae154 { 14852let Inst{7-5} = 0b010; 14853let Inst{13-13} = 0b0; 14854let Inst{31-21} = 0b11101110101; 14855let hasNewValue = 1; 14856let opNewValue = 0; 14857let prefersSlot3 = 1; 14858let Constraints = "$Rx32 = $Rx32in"; 14859} 14860def M2_mpy_nac_lh_s0 : HInst< 14861(outs IntRegs:$Rx32), 14862(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), 14863"$Rx32 -= mpy($Rs32.l,$Rt32.h)", 14864tc_d773585a, TypeM>, Enc_2ae154 { 14865let Inst{7-5} = 0b001; 14866let Inst{13-13} = 0b0; 14867let Inst{31-21} = 0b11101110001; 14868let hasNewValue = 1; 14869let opNewValue = 0; 14870let prefersSlot3 = 1; 14871let Constraints = "$Rx32 = $Rx32in"; 14872} 14873def M2_mpy_nac_lh_s1 : HInst< 14874(outs IntRegs:$Rx32), 14875(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), 14876"$Rx32 -= mpy($Rs32.l,$Rt32.h):<<1", 14877tc_d773585a, TypeM>, Enc_2ae154 { 14878let Inst{7-5} = 0b001; 14879let Inst{13-13} = 0b0; 14880let Inst{31-21} = 0b11101110101; 14881let hasNewValue = 1; 14882let opNewValue = 0; 14883let prefersSlot3 = 1; 14884let Constraints = "$Rx32 = $Rx32in"; 14885} 14886def M2_mpy_nac_ll_s0 : HInst< 14887(outs IntRegs:$Rx32), 14888(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), 14889"$Rx32 -= mpy($Rs32.l,$Rt32.l)", 14890tc_d773585a, TypeM>, Enc_2ae154 { 14891let Inst{7-5} = 0b000; 14892let Inst{13-13} = 0b0; 14893let Inst{31-21} = 0b11101110001; 14894let hasNewValue = 1; 14895let opNewValue = 0; 14896let prefersSlot3 = 1; 14897let Constraints = "$Rx32 = $Rx32in"; 14898} 14899def M2_mpy_nac_ll_s1 : HInst< 14900(outs IntRegs:$Rx32), 14901(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), 14902"$Rx32 -= mpy($Rs32.l,$Rt32.l):<<1", 14903tc_d773585a, TypeM>, Enc_2ae154 { 14904let Inst{7-5} = 0b000; 14905let Inst{13-13} = 0b0; 14906let Inst{31-21} = 0b11101110101; 14907let hasNewValue = 1; 14908let opNewValue = 0; 14909let prefersSlot3 = 1; 14910let Constraints = "$Rx32 = $Rx32in"; 14911} 14912def M2_mpy_nac_sat_hh_s0 : HInst< 14913(outs IntRegs:$Rx32), 14914(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), 14915"$Rx32 -= mpy($Rs32.h,$Rt32.h):sat", 14916tc_d773585a, TypeM>, Enc_2ae154 { 14917let Inst{7-5} = 0b111; 14918let Inst{13-13} = 0b0; 14919let Inst{31-21} = 0b11101110001; 14920let hasNewValue = 1; 14921let opNewValue = 0; 14922let prefersSlot3 = 1; 14923let Defs = [USR_OVF]; 14924let Constraints = "$Rx32 = $Rx32in"; 14925} 14926def M2_mpy_nac_sat_hh_s1 : HInst< 14927(outs IntRegs:$Rx32), 14928(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), 14929"$Rx32 -= mpy($Rs32.h,$Rt32.h):<<1:sat", 14930tc_d773585a, TypeM>, Enc_2ae154 { 14931let Inst{7-5} = 0b111; 14932let Inst{13-13} = 0b0; 14933let Inst{31-21} = 0b11101110101; 14934let hasNewValue = 1; 14935let opNewValue = 0; 14936let prefersSlot3 = 1; 14937let Defs = [USR_OVF]; 14938let Constraints = "$Rx32 = $Rx32in"; 14939} 14940def M2_mpy_nac_sat_hl_s0 : HInst< 14941(outs IntRegs:$Rx32), 14942(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), 14943"$Rx32 -= mpy($Rs32.h,$Rt32.l):sat", 14944tc_d773585a, TypeM>, Enc_2ae154 { 14945let Inst{7-5} = 0b110; 14946let Inst{13-13} = 0b0; 14947let Inst{31-21} = 0b11101110001; 14948let hasNewValue = 1; 14949let opNewValue = 0; 14950let prefersSlot3 = 1; 14951let Defs = [USR_OVF]; 14952let Constraints = "$Rx32 = $Rx32in"; 14953} 14954def M2_mpy_nac_sat_hl_s1 : HInst< 14955(outs IntRegs:$Rx32), 14956(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), 14957"$Rx32 -= mpy($Rs32.h,$Rt32.l):<<1:sat", 14958tc_d773585a, TypeM>, Enc_2ae154 { 14959let Inst{7-5} = 0b110; 14960let Inst{13-13} = 0b0; 14961let Inst{31-21} = 0b11101110101; 14962let hasNewValue = 1; 14963let opNewValue = 0; 14964let prefersSlot3 = 1; 14965let Defs = [USR_OVF]; 14966let Constraints = "$Rx32 = $Rx32in"; 14967} 14968def M2_mpy_nac_sat_lh_s0 : HInst< 14969(outs IntRegs:$Rx32), 14970(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), 14971"$Rx32 -= mpy($Rs32.l,$Rt32.h):sat", 14972tc_d773585a, TypeM>, Enc_2ae154 { 14973let Inst{7-5} = 0b101; 14974let Inst{13-13} = 0b0; 14975let Inst{31-21} = 0b11101110001; 14976let hasNewValue = 1; 14977let opNewValue = 0; 14978let prefersSlot3 = 1; 14979let Defs = [USR_OVF]; 14980let Constraints = "$Rx32 = $Rx32in"; 14981} 14982def M2_mpy_nac_sat_lh_s1 : HInst< 14983(outs IntRegs:$Rx32), 14984(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), 14985"$Rx32 -= mpy($Rs32.l,$Rt32.h):<<1:sat", 14986tc_d773585a, TypeM>, Enc_2ae154 { 14987let Inst{7-5} = 0b101; 14988let Inst{13-13} = 0b0; 14989let Inst{31-21} = 0b11101110101; 14990let hasNewValue = 1; 14991let opNewValue = 0; 14992let prefersSlot3 = 1; 14993let Defs = [USR_OVF]; 14994let Constraints = "$Rx32 = $Rx32in"; 14995} 14996def M2_mpy_nac_sat_ll_s0 : HInst< 14997(outs IntRegs:$Rx32), 14998(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), 14999"$Rx32 -= mpy($Rs32.l,$Rt32.l):sat", 15000tc_d773585a, TypeM>, Enc_2ae154 { 15001let Inst{7-5} = 0b100; 15002let Inst{13-13} = 0b0; 15003let Inst{31-21} = 0b11101110001; 15004let hasNewValue = 1; 15005let opNewValue = 0; 15006let prefersSlot3 = 1; 15007let Defs = [USR_OVF]; 15008let Constraints = "$Rx32 = $Rx32in"; 15009} 15010def M2_mpy_nac_sat_ll_s1 : HInst< 15011(outs IntRegs:$Rx32), 15012(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), 15013"$Rx32 -= mpy($Rs32.l,$Rt32.l):<<1:sat", 15014tc_d773585a, TypeM>, Enc_2ae154 { 15015let Inst{7-5} = 0b100; 15016let Inst{13-13} = 0b0; 15017let Inst{31-21} = 0b11101110101; 15018let hasNewValue = 1; 15019let opNewValue = 0; 15020let prefersSlot3 = 1; 15021let Defs = [USR_OVF]; 15022let Constraints = "$Rx32 = $Rx32in"; 15023} 15024def M2_mpy_rnd_hh_s0 : HInst< 15025(outs IntRegs:$Rd32), 15026(ins IntRegs:$Rs32, IntRegs:$Rt32), 15027"$Rd32 = mpy($Rs32.h,$Rt32.h):rnd", 15028tc_bafaade3, TypeM>, Enc_5ab2be { 15029let Inst{7-5} = 0b011; 15030let Inst{13-13} = 0b0; 15031let Inst{31-21} = 0b11101100001; 15032let hasNewValue = 1; 15033let opNewValue = 0; 15034let prefersSlot3 = 1; 15035} 15036def M2_mpy_rnd_hh_s1 : HInst< 15037(outs IntRegs:$Rd32), 15038(ins IntRegs:$Rs32, IntRegs:$Rt32), 15039"$Rd32 = mpy($Rs32.h,$Rt32.h):<<1:rnd", 15040tc_bafaade3, TypeM>, Enc_5ab2be { 15041let Inst{7-5} = 0b011; 15042let Inst{13-13} = 0b0; 15043let Inst{31-21} = 0b11101100101; 15044let hasNewValue = 1; 15045let opNewValue = 0; 15046let prefersSlot3 = 1; 15047} 15048def M2_mpy_rnd_hl_s0 : HInst< 15049(outs IntRegs:$Rd32), 15050(ins IntRegs:$Rs32, IntRegs:$Rt32), 15051"$Rd32 = mpy($Rs32.h,$Rt32.l):rnd", 15052tc_bafaade3, TypeM>, Enc_5ab2be { 15053let Inst{7-5} = 0b010; 15054let Inst{13-13} = 0b0; 15055let Inst{31-21} = 0b11101100001; 15056let hasNewValue = 1; 15057let opNewValue = 0; 15058let prefersSlot3 = 1; 15059} 15060def M2_mpy_rnd_hl_s1 : HInst< 15061(outs IntRegs:$Rd32), 15062(ins IntRegs:$Rs32, IntRegs:$Rt32), 15063"$Rd32 = mpy($Rs32.h,$Rt32.l):<<1:rnd", 15064tc_bafaade3, TypeM>, Enc_5ab2be { 15065let Inst{7-5} = 0b010; 15066let Inst{13-13} = 0b0; 15067let Inst{31-21} = 0b11101100101; 15068let hasNewValue = 1; 15069let opNewValue = 0; 15070let prefersSlot3 = 1; 15071} 15072def M2_mpy_rnd_lh_s0 : HInst< 15073(outs IntRegs:$Rd32), 15074(ins IntRegs:$Rs32, IntRegs:$Rt32), 15075"$Rd32 = mpy($Rs32.l,$Rt32.h):rnd", 15076tc_bafaade3, TypeM>, Enc_5ab2be { 15077let Inst{7-5} = 0b001; 15078let Inst{13-13} = 0b0; 15079let Inst{31-21} = 0b11101100001; 15080let hasNewValue = 1; 15081let opNewValue = 0; 15082let prefersSlot3 = 1; 15083} 15084def M2_mpy_rnd_lh_s1 : HInst< 15085(outs IntRegs:$Rd32), 15086(ins IntRegs:$Rs32, IntRegs:$Rt32), 15087"$Rd32 = mpy($Rs32.l,$Rt32.h):<<1:rnd", 15088tc_bafaade3, TypeM>, Enc_5ab2be { 15089let Inst{7-5} = 0b001; 15090let Inst{13-13} = 0b0; 15091let Inst{31-21} = 0b11101100101; 15092let hasNewValue = 1; 15093let opNewValue = 0; 15094let prefersSlot3 = 1; 15095} 15096def M2_mpy_rnd_ll_s0 : HInst< 15097(outs IntRegs:$Rd32), 15098(ins IntRegs:$Rs32, IntRegs:$Rt32), 15099"$Rd32 = mpy($Rs32.l,$Rt32.l):rnd", 15100tc_bafaade3, TypeM>, Enc_5ab2be { 15101let Inst{7-5} = 0b000; 15102let Inst{13-13} = 0b0; 15103let Inst{31-21} = 0b11101100001; 15104let hasNewValue = 1; 15105let opNewValue = 0; 15106let prefersSlot3 = 1; 15107} 15108def M2_mpy_rnd_ll_s1 : HInst< 15109(outs IntRegs:$Rd32), 15110(ins IntRegs:$Rs32, IntRegs:$Rt32), 15111"$Rd32 = mpy($Rs32.l,$Rt32.l):<<1:rnd", 15112tc_bafaade3, TypeM>, Enc_5ab2be { 15113let Inst{7-5} = 0b000; 15114let Inst{13-13} = 0b0; 15115let Inst{31-21} = 0b11101100101; 15116let hasNewValue = 1; 15117let opNewValue = 0; 15118let prefersSlot3 = 1; 15119} 15120def M2_mpy_sat_hh_s0 : HInst< 15121(outs IntRegs:$Rd32), 15122(ins IntRegs:$Rs32, IntRegs:$Rt32), 15123"$Rd32 = mpy($Rs32.h,$Rt32.h):sat", 15124tc_bafaade3, TypeM>, Enc_5ab2be { 15125let Inst{7-5} = 0b111; 15126let Inst{13-13} = 0b0; 15127let Inst{31-21} = 0b11101100000; 15128let hasNewValue = 1; 15129let opNewValue = 0; 15130let prefersSlot3 = 1; 15131let Defs = [USR_OVF]; 15132} 15133def M2_mpy_sat_hh_s1 : HInst< 15134(outs IntRegs:$Rd32), 15135(ins IntRegs:$Rs32, IntRegs:$Rt32), 15136"$Rd32 = mpy($Rs32.h,$Rt32.h):<<1:sat", 15137tc_bafaade3, TypeM>, Enc_5ab2be { 15138let Inst{7-5} = 0b111; 15139let Inst{13-13} = 0b0; 15140let Inst{31-21} = 0b11101100100; 15141let hasNewValue = 1; 15142let opNewValue = 0; 15143let prefersSlot3 = 1; 15144let Defs = [USR_OVF]; 15145} 15146def M2_mpy_sat_hl_s0 : HInst< 15147(outs IntRegs:$Rd32), 15148(ins IntRegs:$Rs32, IntRegs:$Rt32), 15149"$Rd32 = mpy($Rs32.h,$Rt32.l):sat", 15150tc_bafaade3, TypeM>, Enc_5ab2be { 15151let Inst{7-5} = 0b110; 15152let Inst{13-13} = 0b0; 15153let Inst{31-21} = 0b11101100000; 15154let hasNewValue = 1; 15155let opNewValue = 0; 15156let prefersSlot3 = 1; 15157let Defs = [USR_OVF]; 15158} 15159def M2_mpy_sat_hl_s1 : HInst< 15160(outs IntRegs:$Rd32), 15161(ins IntRegs:$Rs32, IntRegs:$Rt32), 15162"$Rd32 = mpy($Rs32.h,$Rt32.l):<<1:sat", 15163tc_bafaade3, TypeM>, Enc_5ab2be { 15164let Inst{7-5} = 0b110; 15165let Inst{13-13} = 0b0; 15166let Inst{31-21} = 0b11101100100; 15167let hasNewValue = 1; 15168let opNewValue = 0; 15169let prefersSlot3 = 1; 15170let Defs = [USR_OVF]; 15171} 15172def M2_mpy_sat_lh_s0 : HInst< 15173(outs IntRegs:$Rd32), 15174(ins IntRegs:$Rs32, IntRegs:$Rt32), 15175"$Rd32 = mpy($Rs32.l,$Rt32.h):sat", 15176tc_bafaade3, TypeM>, Enc_5ab2be { 15177let Inst{7-5} = 0b101; 15178let Inst{13-13} = 0b0; 15179let Inst{31-21} = 0b11101100000; 15180let hasNewValue = 1; 15181let opNewValue = 0; 15182let prefersSlot3 = 1; 15183let Defs = [USR_OVF]; 15184} 15185def M2_mpy_sat_lh_s1 : HInst< 15186(outs IntRegs:$Rd32), 15187(ins IntRegs:$Rs32, IntRegs:$Rt32), 15188"$Rd32 = mpy($Rs32.l,$Rt32.h):<<1:sat", 15189tc_bafaade3, TypeM>, Enc_5ab2be { 15190let Inst{7-5} = 0b101; 15191let Inst{13-13} = 0b0; 15192let Inst{31-21} = 0b11101100100; 15193let hasNewValue = 1; 15194let opNewValue = 0; 15195let prefersSlot3 = 1; 15196let Defs = [USR_OVF]; 15197} 15198def M2_mpy_sat_ll_s0 : HInst< 15199(outs IntRegs:$Rd32), 15200(ins IntRegs:$Rs32, IntRegs:$Rt32), 15201"$Rd32 = mpy($Rs32.l,$Rt32.l):sat", 15202tc_bafaade3, TypeM>, Enc_5ab2be { 15203let Inst{7-5} = 0b100; 15204let Inst{13-13} = 0b0; 15205let Inst{31-21} = 0b11101100000; 15206let hasNewValue = 1; 15207let opNewValue = 0; 15208let prefersSlot3 = 1; 15209let Defs = [USR_OVF]; 15210} 15211def M2_mpy_sat_ll_s1 : HInst< 15212(outs IntRegs:$Rd32), 15213(ins IntRegs:$Rs32, IntRegs:$Rt32), 15214"$Rd32 = mpy($Rs32.l,$Rt32.l):<<1:sat", 15215tc_bafaade3, TypeM>, Enc_5ab2be { 15216let Inst{7-5} = 0b100; 15217let Inst{13-13} = 0b0; 15218let Inst{31-21} = 0b11101100100; 15219let hasNewValue = 1; 15220let opNewValue = 0; 15221let prefersSlot3 = 1; 15222let Defs = [USR_OVF]; 15223} 15224def M2_mpy_sat_rnd_hh_s0 : HInst< 15225(outs IntRegs:$Rd32), 15226(ins IntRegs:$Rs32, IntRegs:$Rt32), 15227"$Rd32 = mpy($Rs32.h,$Rt32.h):rnd:sat", 15228tc_bafaade3, TypeM>, Enc_5ab2be { 15229let Inst{7-5} = 0b111; 15230let Inst{13-13} = 0b0; 15231let Inst{31-21} = 0b11101100001; 15232let hasNewValue = 1; 15233let opNewValue = 0; 15234let prefersSlot3 = 1; 15235let Defs = [USR_OVF]; 15236} 15237def M2_mpy_sat_rnd_hh_s1 : HInst< 15238(outs IntRegs:$Rd32), 15239(ins IntRegs:$Rs32, IntRegs:$Rt32), 15240"$Rd32 = mpy($Rs32.h,$Rt32.h):<<1:rnd:sat", 15241tc_bafaade3, TypeM>, Enc_5ab2be { 15242let Inst{7-5} = 0b111; 15243let Inst{13-13} = 0b0; 15244let Inst{31-21} = 0b11101100101; 15245let hasNewValue = 1; 15246let opNewValue = 0; 15247let prefersSlot3 = 1; 15248let Defs = [USR_OVF]; 15249} 15250def M2_mpy_sat_rnd_hl_s0 : HInst< 15251(outs IntRegs:$Rd32), 15252(ins IntRegs:$Rs32, IntRegs:$Rt32), 15253"$Rd32 = mpy($Rs32.h,$Rt32.l):rnd:sat", 15254tc_bafaade3, TypeM>, Enc_5ab2be { 15255let Inst{7-5} = 0b110; 15256let Inst{13-13} = 0b0; 15257let Inst{31-21} = 0b11101100001; 15258let hasNewValue = 1; 15259let opNewValue = 0; 15260let prefersSlot3 = 1; 15261let Defs = [USR_OVF]; 15262} 15263def M2_mpy_sat_rnd_hl_s1 : HInst< 15264(outs IntRegs:$Rd32), 15265(ins IntRegs:$Rs32, IntRegs:$Rt32), 15266"$Rd32 = mpy($Rs32.h,$Rt32.l):<<1:rnd:sat", 15267tc_bafaade3, TypeM>, Enc_5ab2be { 15268let Inst{7-5} = 0b110; 15269let Inst{13-13} = 0b0; 15270let Inst{31-21} = 0b11101100101; 15271let hasNewValue = 1; 15272let opNewValue = 0; 15273let prefersSlot3 = 1; 15274let Defs = [USR_OVF]; 15275} 15276def M2_mpy_sat_rnd_lh_s0 : HInst< 15277(outs IntRegs:$Rd32), 15278(ins IntRegs:$Rs32, IntRegs:$Rt32), 15279"$Rd32 = mpy($Rs32.l,$Rt32.h):rnd:sat", 15280tc_bafaade3, TypeM>, Enc_5ab2be { 15281let Inst{7-5} = 0b101; 15282let Inst{13-13} = 0b0; 15283let Inst{31-21} = 0b11101100001; 15284let hasNewValue = 1; 15285let opNewValue = 0; 15286let prefersSlot3 = 1; 15287let Defs = [USR_OVF]; 15288} 15289def M2_mpy_sat_rnd_lh_s1 : HInst< 15290(outs IntRegs:$Rd32), 15291(ins IntRegs:$Rs32, IntRegs:$Rt32), 15292"$Rd32 = mpy($Rs32.l,$Rt32.h):<<1:rnd:sat", 15293tc_bafaade3, TypeM>, Enc_5ab2be { 15294let Inst{7-5} = 0b101; 15295let Inst{13-13} = 0b0; 15296let Inst{31-21} = 0b11101100101; 15297let hasNewValue = 1; 15298let opNewValue = 0; 15299let prefersSlot3 = 1; 15300let Defs = [USR_OVF]; 15301} 15302def M2_mpy_sat_rnd_ll_s0 : HInst< 15303(outs IntRegs:$Rd32), 15304(ins IntRegs:$Rs32, IntRegs:$Rt32), 15305"$Rd32 = mpy($Rs32.l,$Rt32.l):rnd:sat", 15306tc_bafaade3, TypeM>, Enc_5ab2be { 15307let Inst{7-5} = 0b100; 15308let Inst{13-13} = 0b0; 15309let Inst{31-21} = 0b11101100001; 15310let hasNewValue = 1; 15311let opNewValue = 0; 15312let prefersSlot3 = 1; 15313let Defs = [USR_OVF]; 15314} 15315def M2_mpy_sat_rnd_ll_s1 : HInst< 15316(outs IntRegs:$Rd32), 15317(ins IntRegs:$Rs32, IntRegs:$Rt32), 15318"$Rd32 = mpy($Rs32.l,$Rt32.l):<<1:rnd:sat", 15319tc_bafaade3, TypeM>, Enc_5ab2be { 15320let Inst{7-5} = 0b100; 15321let Inst{13-13} = 0b0; 15322let Inst{31-21} = 0b11101100101; 15323let hasNewValue = 1; 15324let opNewValue = 0; 15325let prefersSlot3 = 1; 15326let Defs = [USR_OVF]; 15327} 15328def M2_mpy_up : HInst< 15329(outs IntRegs:$Rd32), 15330(ins IntRegs:$Rs32, IntRegs:$Rt32), 15331"$Rd32 = mpy($Rs32,$Rt32)", 15332tc_bafaade3, TypeM>, Enc_5ab2be { 15333let Inst{7-5} = 0b001; 15334let Inst{13-13} = 0b0; 15335let Inst{31-21} = 0b11101101000; 15336let hasNewValue = 1; 15337let opNewValue = 0; 15338let prefersSlot3 = 1; 15339} 15340def M2_mpy_up_s1 : HInst< 15341(outs IntRegs:$Rd32), 15342(ins IntRegs:$Rs32, IntRegs:$Rt32), 15343"$Rd32 = mpy($Rs32,$Rt32):<<1", 15344tc_bafaade3, TypeM>, Enc_5ab2be { 15345let Inst{7-5} = 0b010; 15346let Inst{13-13} = 0b0; 15347let Inst{31-21} = 0b11101101101; 15348let hasNewValue = 1; 15349let opNewValue = 0; 15350let prefersSlot3 = 1; 15351} 15352def M2_mpy_up_s1_sat : HInst< 15353(outs IntRegs:$Rd32), 15354(ins IntRegs:$Rs32, IntRegs:$Rt32), 15355"$Rd32 = mpy($Rs32,$Rt32):<<1:sat", 15356tc_bafaade3, TypeM>, Enc_5ab2be { 15357let Inst{7-5} = 0b000; 15358let Inst{13-13} = 0b0; 15359let Inst{31-21} = 0b11101101111; 15360let hasNewValue = 1; 15361let opNewValue = 0; 15362let prefersSlot3 = 1; 15363let Defs = [USR_OVF]; 15364} 15365def M2_mpyd_acc_hh_s0 : HInst< 15366(outs DoubleRegs:$Rxx32), 15367(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), 15368"$Rxx32 += mpy($Rs32.h,$Rt32.h)", 15369tc_d773585a, TypeM>, Enc_61f0b0 { 15370let Inst{7-5} = 0b011; 15371let Inst{13-13} = 0b0; 15372let Inst{31-21} = 0b11100110000; 15373let prefersSlot3 = 1; 15374let Constraints = "$Rxx32 = $Rxx32in"; 15375} 15376def M2_mpyd_acc_hh_s1 : HInst< 15377(outs DoubleRegs:$Rxx32), 15378(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), 15379"$Rxx32 += mpy($Rs32.h,$Rt32.h):<<1", 15380tc_d773585a, TypeM>, Enc_61f0b0 { 15381let Inst{7-5} = 0b011; 15382let Inst{13-13} = 0b0; 15383let Inst{31-21} = 0b11100110100; 15384let prefersSlot3 = 1; 15385let Constraints = "$Rxx32 = $Rxx32in"; 15386} 15387def M2_mpyd_acc_hl_s0 : HInst< 15388(outs DoubleRegs:$Rxx32), 15389(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), 15390"$Rxx32 += mpy($Rs32.h,$Rt32.l)", 15391tc_d773585a, TypeM>, Enc_61f0b0 { 15392let Inst{7-5} = 0b010; 15393let Inst{13-13} = 0b0; 15394let Inst{31-21} = 0b11100110000; 15395let prefersSlot3 = 1; 15396let Constraints = "$Rxx32 = $Rxx32in"; 15397} 15398def M2_mpyd_acc_hl_s1 : HInst< 15399(outs DoubleRegs:$Rxx32), 15400(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), 15401"$Rxx32 += mpy($Rs32.h,$Rt32.l):<<1", 15402tc_d773585a, TypeM>, Enc_61f0b0 { 15403let Inst{7-5} = 0b010; 15404let Inst{13-13} = 0b0; 15405let Inst{31-21} = 0b11100110100; 15406let prefersSlot3 = 1; 15407let Constraints = "$Rxx32 = $Rxx32in"; 15408} 15409def M2_mpyd_acc_lh_s0 : HInst< 15410(outs DoubleRegs:$Rxx32), 15411(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), 15412"$Rxx32 += mpy($Rs32.l,$Rt32.h)", 15413tc_d773585a, TypeM>, Enc_61f0b0 { 15414let Inst{7-5} = 0b001; 15415let Inst{13-13} = 0b0; 15416let Inst{31-21} = 0b11100110000; 15417let prefersSlot3 = 1; 15418let Constraints = "$Rxx32 = $Rxx32in"; 15419} 15420def M2_mpyd_acc_lh_s1 : HInst< 15421(outs DoubleRegs:$Rxx32), 15422(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), 15423"$Rxx32 += mpy($Rs32.l,$Rt32.h):<<1", 15424tc_d773585a, TypeM>, Enc_61f0b0 { 15425let Inst{7-5} = 0b001; 15426let Inst{13-13} = 0b0; 15427let Inst{31-21} = 0b11100110100; 15428let prefersSlot3 = 1; 15429let Constraints = "$Rxx32 = $Rxx32in"; 15430} 15431def M2_mpyd_acc_ll_s0 : HInst< 15432(outs DoubleRegs:$Rxx32), 15433(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), 15434"$Rxx32 += mpy($Rs32.l,$Rt32.l)", 15435tc_d773585a, TypeM>, Enc_61f0b0 { 15436let Inst{7-5} = 0b000; 15437let Inst{13-13} = 0b0; 15438let Inst{31-21} = 0b11100110000; 15439let prefersSlot3 = 1; 15440let Constraints = "$Rxx32 = $Rxx32in"; 15441} 15442def M2_mpyd_acc_ll_s1 : HInst< 15443(outs DoubleRegs:$Rxx32), 15444(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), 15445"$Rxx32 += mpy($Rs32.l,$Rt32.l):<<1", 15446tc_d773585a, TypeM>, Enc_61f0b0 { 15447let Inst{7-5} = 0b000; 15448let Inst{13-13} = 0b0; 15449let Inst{31-21} = 0b11100110100; 15450let prefersSlot3 = 1; 15451let Constraints = "$Rxx32 = $Rxx32in"; 15452} 15453def M2_mpyd_hh_s0 : HInst< 15454(outs DoubleRegs:$Rdd32), 15455(ins IntRegs:$Rs32, IntRegs:$Rt32), 15456"$Rdd32 = mpy($Rs32.h,$Rt32.h)", 15457tc_bafaade3, TypeM>, Enc_be32a5 { 15458let Inst{7-5} = 0b011; 15459let Inst{13-13} = 0b0; 15460let Inst{31-21} = 0b11100100000; 15461let prefersSlot3 = 1; 15462} 15463def M2_mpyd_hh_s1 : HInst< 15464(outs DoubleRegs:$Rdd32), 15465(ins IntRegs:$Rs32, IntRegs:$Rt32), 15466"$Rdd32 = mpy($Rs32.h,$Rt32.h):<<1", 15467tc_bafaade3, TypeM>, Enc_be32a5 { 15468let Inst{7-5} = 0b011; 15469let Inst{13-13} = 0b0; 15470let Inst{31-21} = 0b11100100100; 15471let prefersSlot3 = 1; 15472} 15473def M2_mpyd_hl_s0 : HInst< 15474(outs DoubleRegs:$Rdd32), 15475(ins IntRegs:$Rs32, IntRegs:$Rt32), 15476"$Rdd32 = mpy($Rs32.h,$Rt32.l)", 15477tc_bafaade3, TypeM>, Enc_be32a5 { 15478let Inst{7-5} = 0b010; 15479let Inst{13-13} = 0b0; 15480let Inst{31-21} = 0b11100100000; 15481let prefersSlot3 = 1; 15482} 15483def M2_mpyd_hl_s1 : HInst< 15484(outs DoubleRegs:$Rdd32), 15485(ins IntRegs:$Rs32, IntRegs:$Rt32), 15486"$Rdd32 = mpy($Rs32.h,$Rt32.l):<<1", 15487tc_bafaade3, TypeM>, Enc_be32a5 { 15488let Inst{7-5} = 0b010; 15489let Inst{13-13} = 0b0; 15490let Inst{31-21} = 0b11100100100; 15491let prefersSlot3 = 1; 15492} 15493def M2_mpyd_lh_s0 : HInst< 15494(outs DoubleRegs:$Rdd32), 15495(ins IntRegs:$Rs32, IntRegs:$Rt32), 15496"$Rdd32 = mpy($Rs32.l,$Rt32.h)", 15497tc_bafaade3, TypeM>, Enc_be32a5 { 15498let Inst{7-5} = 0b001; 15499let Inst{13-13} = 0b0; 15500let Inst{31-21} = 0b11100100000; 15501let prefersSlot3 = 1; 15502} 15503def M2_mpyd_lh_s1 : HInst< 15504(outs DoubleRegs:$Rdd32), 15505(ins IntRegs:$Rs32, IntRegs:$Rt32), 15506"$Rdd32 = mpy($Rs32.l,$Rt32.h):<<1", 15507tc_bafaade3, TypeM>, Enc_be32a5 { 15508let Inst{7-5} = 0b001; 15509let Inst{13-13} = 0b0; 15510let Inst{31-21} = 0b11100100100; 15511let prefersSlot3 = 1; 15512} 15513def M2_mpyd_ll_s0 : HInst< 15514(outs DoubleRegs:$Rdd32), 15515(ins IntRegs:$Rs32, IntRegs:$Rt32), 15516"$Rdd32 = mpy($Rs32.l,$Rt32.l)", 15517tc_bafaade3, TypeM>, Enc_be32a5 { 15518let Inst{7-5} = 0b000; 15519let Inst{13-13} = 0b0; 15520let Inst{31-21} = 0b11100100000; 15521let prefersSlot3 = 1; 15522} 15523def M2_mpyd_ll_s1 : HInst< 15524(outs DoubleRegs:$Rdd32), 15525(ins IntRegs:$Rs32, IntRegs:$Rt32), 15526"$Rdd32 = mpy($Rs32.l,$Rt32.l):<<1", 15527tc_bafaade3, TypeM>, Enc_be32a5 { 15528let Inst{7-5} = 0b000; 15529let Inst{13-13} = 0b0; 15530let Inst{31-21} = 0b11100100100; 15531let prefersSlot3 = 1; 15532} 15533def M2_mpyd_nac_hh_s0 : HInst< 15534(outs DoubleRegs:$Rxx32), 15535(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), 15536"$Rxx32 -= mpy($Rs32.h,$Rt32.h)", 15537tc_d773585a, TypeM>, Enc_61f0b0 { 15538let Inst{7-5} = 0b011; 15539let Inst{13-13} = 0b0; 15540let Inst{31-21} = 0b11100110001; 15541let prefersSlot3 = 1; 15542let Constraints = "$Rxx32 = $Rxx32in"; 15543} 15544def M2_mpyd_nac_hh_s1 : HInst< 15545(outs DoubleRegs:$Rxx32), 15546(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), 15547"$Rxx32 -= mpy($Rs32.h,$Rt32.h):<<1", 15548tc_d773585a, TypeM>, Enc_61f0b0 { 15549let Inst{7-5} = 0b011; 15550let Inst{13-13} = 0b0; 15551let Inst{31-21} = 0b11100110101; 15552let prefersSlot3 = 1; 15553let Constraints = "$Rxx32 = $Rxx32in"; 15554} 15555def M2_mpyd_nac_hl_s0 : HInst< 15556(outs DoubleRegs:$Rxx32), 15557(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), 15558"$Rxx32 -= mpy($Rs32.h,$Rt32.l)", 15559tc_d773585a, TypeM>, Enc_61f0b0 { 15560let Inst{7-5} = 0b010; 15561let Inst{13-13} = 0b0; 15562let Inst{31-21} = 0b11100110001; 15563let prefersSlot3 = 1; 15564let Constraints = "$Rxx32 = $Rxx32in"; 15565} 15566def M2_mpyd_nac_hl_s1 : HInst< 15567(outs DoubleRegs:$Rxx32), 15568(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), 15569"$Rxx32 -= mpy($Rs32.h,$Rt32.l):<<1", 15570tc_d773585a, TypeM>, Enc_61f0b0 { 15571let Inst{7-5} = 0b010; 15572let Inst{13-13} = 0b0; 15573let Inst{31-21} = 0b11100110101; 15574let prefersSlot3 = 1; 15575let Constraints = "$Rxx32 = $Rxx32in"; 15576} 15577def M2_mpyd_nac_lh_s0 : HInst< 15578(outs DoubleRegs:$Rxx32), 15579(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), 15580"$Rxx32 -= mpy($Rs32.l,$Rt32.h)", 15581tc_d773585a, TypeM>, Enc_61f0b0 { 15582let Inst{7-5} = 0b001; 15583let Inst{13-13} = 0b0; 15584let Inst{31-21} = 0b11100110001; 15585let prefersSlot3 = 1; 15586let Constraints = "$Rxx32 = $Rxx32in"; 15587} 15588def M2_mpyd_nac_lh_s1 : HInst< 15589(outs DoubleRegs:$Rxx32), 15590(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), 15591"$Rxx32 -= mpy($Rs32.l,$Rt32.h):<<1", 15592tc_d773585a, TypeM>, Enc_61f0b0 { 15593let Inst{7-5} = 0b001; 15594let Inst{13-13} = 0b0; 15595let Inst{31-21} = 0b11100110101; 15596let prefersSlot3 = 1; 15597let Constraints = "$Rxx32 = $Rxx32in"; 15598} 15599def M2_mpyd_nac_ll_s0 : HInst< 15600(outs DoubleRegs:$Rxx32), 15601(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), 15602"$Rxx32 -= mpy($Rs32.l,$Rt32.l)", 15603tc_d773585a, TypeM>, Enc_61f0b0 { 15604let Inst{7-5} = 0b000; 15605let Inst{13-13} = 0b0; 15606let Inst{31-21} = 0b11100110001; 15607let prefersSlot3 = 1; 15608let Constraints = "$Rxx32 = $Rxx32in"; 15609} 15610def M2_mpyd_nac_ll_s1 : HInst< 15611(outs DoubleRegs:$Rxx32), 15612(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), 15613"$Rxx32 -= mpy($Rs32.l,$Rt32.l):<<1", 15614tc_d773585a, TypeM>, Enc_61f0b0 { 15615let Inst{7-5} = 0b000; 15616let Inst{13-13} = 0b0; 15617let Inst{31-21} = 0b11100110101; 15618let prefersSlot3 = 1; 15619let Constraints = "$Rxx32 = $Rxx32in"; 15620} 15621def M2_mpyd_rnd_hh_s0 : HInst< 15622(outs DoubleRegs:$Rdd32), 15623(ins IntRegs:$Rs32, IntRegs:$Rt32), 15624"$Rdd32 = mpy($Rs32.h,$Rt32.h):rnd", 15625tc_bafaade3, TypeM>, Enc_be32a5 { 15626let Inst{7-5} = 0b011; 15627let Inst{13-13} = 0b0; 15628let Inst{31-21} = 0b11100100001; 15629let prefersSlot3 = 1; 15630} 15631def M2_mpyd_rnd_hh_s1 : HInst< 15632(outs DoubleRegs:$Rdd32), 15633(ins IntRegs:$Rs32, IntRegs:$Rt32), 15634"$Rdd32 = mpy($Rs32.h,$Rt32.h):<<1:rnd", 15635tc_bafaade3, TypeM>, Enc_be32a5 { 15636let Inst{7-5} = 0b011; 15637let Inst{13-13} = 0b0; 15638let Inst{31-21} = 0b11100100101; 15639let prefersSlot3 = 1; 15640} 15641def M2_mpyd_rnd_hl_s0 : HInst< 15642(outs DoubleRegs:$Rdd32), 15643(ins IntRegs:$Rs32, IntRegs:$Rt32), 15644"$Rdd32 = mpy($Rs32.h,$Rt32.l):rnd", 15645tc_bafaade3, TypeM>, Enc_be32a5 { 15646let Inst{7-5} = 0b010; 15647let Inst{13-13} = 0b0; 15648let Inst{31-21} = 0b11100100001; 15649let prefersSlot3 = 1; 15650} 15651def M2_mpyd_rnd_hl_s1 : HInst< 15652(outs DoubleRegs:$Rdd32), 15653(ins IntRegs:$Rs32, IntRegs:$Rt32), 15654"$Rdd32 = mpy($Rs32.h,$Rt32.l):<<1:rnd", 15655tc_bafaade3, TypeM>, Enc_be32a5 { 15656let Inst{7-5} = 0b010; 15657let Inst{13-13} = 0b0; 15658let Inst{31-21} = 0b11100100101; 15659let prefersSlot3 = 1; 15660} 15661def M2_mpyd_rnd_lh_s0 : HInst< 15662(outs DoubleRegs:$Rdd32), 15663(ins IntRegs:$Rs32, IntRegs:$Rt32), 15664"$Rdd32 = mpy($Rs32.l,$Rt32.h):rnd", 15665tc_bafaade3, TypeM>, Enc_be32a5 { 15666let Inst{7-5} = 0b001; 15667let Inst{13-13} = 0b0; 15668let Inst{31-21} = 0b11100100001; 15669let prefersSlot3 = 1; 15670} 15671def M2_mpyd_rnd_lh_s1 : HInst< 15672(outs DoubleRegs:$Rdd32), 15673(ins IntRegs:$Rs32, IntRegs:$Rt32), 15674"$Rdd32 = mpy($Rs32.l,$Rt32.h):<<1:rnd", 15675tc_bafaade3, TypeM>, Enc_be32a5 { 15676let Inst{7-5} = 0b001; 15677let Inst{13-13} = 0b0; 15678let Inst{31-21} = 0b11100100101; 15679let prefersSlot3 = 1; 15680} 15681def M2_mpyd_rnd_ll_s0 : HInst< 15682(outs DoubleRegs:$Rdd32), 15683(ins IntRegs:$Rs32, IntRegs:$Rt32), 15684"$Rdd32 = mpy($Rs32.l,$Rt32.l):rnd", 15685tc_bafaade3, TypeM>, Enc_be32a5 { 15686let Inst{7-5} = 0b000; 15687let Inst{13-13} = 0b0; 15688let Inst{31-21} = 0b11100100001; 15689let prefersSlot3 = 1; 15690} 15691def M2_mpyd_rnd_ll_s1 : HInst< 15692(outs DoubleRegs:$Rdd32), 15693(ins IntRegs:$Rs32, IntRegs:$Rt32), 15694"$Rdd32 = mpy($Rs32.l,$Rt32.l):<<1:rnd", 15695tc_bafaade3, TypeM>, Enc_be32a5 { 15696let Inst{7-5} = 0b000; 15697let Inst{13-13} = 0b0; 15698let Inst{31-21} = 0b11100100101; 15699let prefersSlot3 = 1; 15700} 15701def M2_mpyi : HInst< 15702(outs IntRegs:$Rd32), 15703(ins IntRegs:$Rs32, IntRegs:$Rt32), 15704"$Rd32 = mpyi($Rs32,$Rt32)", 15705tc_bafaade3, TypeM>, Enc_5ab2be, ImmRegRel { 15706let Inst{7-5} = 0b000; 15707let Inst{13-13} = 0b0; 15708let Inst{31-21} = 0b11101101000; 15709let hasNewValue = 1; 15710let opNewValue = 0; 15711let prefersSlot3 = 1; 15712let CextOpcode = "M2_mpyi"; 15713let InputType = "reg"; 15714} 15715def M2_mpysin : HInst< 15716(outs IntRegs:$Rd32), 15717(ins IntRegs:$Rs32, u8_0Imm:$Ii), 15718"$Rd32 = -mpyi($Rs32,#$Ii)", 15719tc_c8ce0b5c, TypeM>, Enc_b8c967 { 15720let Inst{13-13} = 0b0; 15721let Inst{31-21} = 0b11100000100; 15722let hasNewValue = 1; 15723let opNewValue = 0; 15724let prefersSlot3 = 1; 15725} 15726def M2_mpysip : HInst< 15727(outs IntRegs:$Rd32), 15728(ins IntRegs:$Rs32, u32_0Imm:$Ii), 15729"$Rd32 = +mpyi($Rs32,#$Ii)", 15730tc_c8ce0b5c, TypeM>, Enc_b8c967 { 15731let Inst{13-13} = 0b0; 15732let Inst{31-21} = 0b11100000000; 15733let hasNewValue = 1; 15734let opNewValue = 0; 15735let prefersSlot3 = 1; 15736let isExtendable = 1; 15737let opExtendable = 2; 15738let isExtentSigned = 0; 15739let opExtentBits = 8; 15740let opExtentAlign = 0; 15741} 15742def M2_mpysmi : HInst< 15743(outs IntRegs:$Rd32), 15744(ins IntRegs:$Rs32, m32_0Imm:$Ii), 15745"$Rd32 = mpyi($Rs32,#$Ii)", 15746tc_c8ce0b5c, TypeM>, ImmRegRel { 15747let hasNewValue = 1; 15748let opNewValue = 0; 15749let CextOpcode = "M2_mpyi"; 15750let InputType = "imm"; 15751let isPseudo = 1; 15752let isExtendable = 1; 15753let opExtendable = 2; 15754let isExtentSigned = 1; 15755let opExtentBits = 9; 15756let opExtentAlign = 0; 15757} 15758def M2_mpysu_up : HInst< 15759(outs IntRegs:$Rd32), 15760(ins IntRegs:$Rs32, IntRegs:$Rt32), 15761"$Rd32 = mpysu($Rs32,$Rt32)", 15762tc_bafaade3, TypeM>, Enc_5ab2be { 15763let Inst{7-5} = 0b001; 15764let Inst{13-13} = 0b0; 15765let Inst{31-21} = 0b11101101011; 15766let hasNewValue = 1; 15767let opNewValue = 0; 15768let prefersSlot3 = 1; 15769} 15770def M2_mpyu_acc_hh_s0 : HInst< 15771(outs IntRegs:$Rx32), 15772(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), 15773"$Rx32 += mpyu($Rs32.h,$Rt32.h)", 15774tc_d773585a, TypeM>, Enc_2ae154 { 15775let Inst{7-5} = 0b011; 15776let Inst{13-13} = 0b0; 15777let Inst{31-21} = 0b11101110010; 15778let hasNewValue = 1; 15779let opNewValue = 0; 15780let prefersSlot3 = 1; 15781let Constraints = "$Rx32 = $Rx32in"; 15782} 15783def M2_mpyu_acc_hh_s1 : HInst< 15784(outs IntRegs:$Rx32), 15785(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), 15786"$Rx32 += mpyu($Rs32.h,$Rt32.h):<<1", 15787tc_d773585a, TypeM>, Enc_2ae154 { 15788let Inst{7-5} = 0b011; 15789let Inst{13-13} = 0b0; 15790let Inst{31-21} = 0b11101110110; 15791let hasNewValue = 1; 15792let opNewValue = 0; 15793let prefersSlot3 = 1; 15794let Constraints = "$Rx32 = $Rx32in"; 15795} 15796def M2_mpyu_acc_hl_s0 : HInst< 15797(outs IntRegs:$Rx32), 15798(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), 15799"$Rx32 += mpyu($Rs32.h,$Rt32.l)", 15800tc_d773585a, TypeM>, Enc_2ae154 { 15801let Inst{7-5} = 0b010; 15802let Inst{13-13} = 0b0; 15803let Inst{31-21} = 0b11101110010; 15804let hasNewValue = 1; 15805let opNewValue = 0; 15806let prefersSlot3 = 1; 15807let Constraints = "$Rx32 = $Rx32in"; 15808} 15809def M2_mpyu_acc_hl_s1 : HInst< 15810(outs IntRegs:$Rx32), 15811(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), 15812"$Rx32 += mpyu($Rs32.h,$Rt32.l):<<1", 15813tc_d773585a, TypeM>, Enc_2ae154 { 15814let Inst{7-5} = 0b010; 15815let Inst{13-13} = 0b0; 15816let Inst{31-21} = 0b11101110110; 15817let hasNewValue = 1; 15818let opNewValue = 0; 15819let prefersSlot3 = 1; 15820let Constraints = "$Rx32 = $Rx32in"; 15821} 15822def M2_mpyu_acc_lh_s0 : HInst< 15823(outs IntRegs:$Rx32), 15824(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), 15825"$Rx32 += mpyu($Rs32.l,$Rt32.h)", 15826tc_d773585a, TypeM>, Enc_2ae154 { 15827let Inst{7-5} = 0b001; 15828let Inst{13-13} = 0b0; 15829let Inst{31-21} = 0b11101110010; 15830let hasNewValue = 1; 15831let opNewValue = 0; 15832let prefersSlot3 = 1; 15833let Constraints = "$Rx32 = $Rx32in"; 15834} 15835def M2_mpyu_acc_lh_s1 : HInst< 15836(outs IntRegs:$Rx32), 15837(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), 15838"$Rx32 += mpyu($Rs32.l,$Rt32.h):<<1", 15839tc_d773585a, TypeM>, Enc_2ae154 { 15840let Inst{7-5} = 0b001; 15841let Inst{13-13} = 0b0; 15842let Inst{31-21} = 0b11101110110; 15843let hasNewValue = 1; 15844let opNewValue = 0; 15845let prefersSlot3 = 1; 15846let Constraints = "$Rx32 = $Rx32in"; 15847} 15848def M2_mpyu_acc_ll_s0 : HInst< 15849(outs IntRegs:$Rx32), 15850(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), 15851"$Rx32 += mpyu($Rs32.l,$Rt32.l)", 15852tc_d773585a, TypeM>, Enc_2ae154 { 15853let Inst{7-5} = 0b000; 15854let Inst{13-13} = 0b0; 15855let Inst{31-21} = 0b11101110010; 15856let hasNewValue = 1; 15857let opNewValue = 0; 15858let prefersSlot3 = 1; 15859let Constraints = "$Rx32 = $Rx32in"; 15860} 15861def M2_mpyu_acc_ll_s1 : HInst< 15862(outs IntRegs:$Rx32), 15863(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), 15864"$Rx32 += mpyu($Rs32.l,$Rt32.l):<<1", 15865tc_d773585a, TypeM>, Enc_2ae154 { 15866let Inst{7-5} = 0b000; 15867let Inst{13-13} = 0b0; 15868let Inst{31-21} = 0b11101110110; 15869let hasNewValue = 1; 15870let opNewValue = 0; 15871let prefersSlot3 = 1; 15872let Constraints = "$Rx32 = $Rx32in"; 15873} 15874def M2_mpyu_hh_s0 : HInst< 15875(outs IntRegs:$Rd32), 15876(ins IntRegs:$Rs32, IntRegs:$Rt32), 15877"$Rd32 = mpyu($Rs32.h,$Rt32.h)", 15878tc_bafaade3, TypeM>, Enc_5ab2be { 15879let Inst{7-5} = 0b011; 15880let Inst{13-13} = 0b0; 15881let Inst{31-21} = 0b11101100010; 15882let hasNewValue = 1; 15883let opNewValue = 0; 15884let prefersSlot3 = 1; 15885} 15886def M2_mpyu_hh_s1 : HInst< 15887(outs IntRegs:$Rd32), 15888(ins IntRegs:$Rs32, IntRegs:$Rt32), 15889"$Rd32 = mpyu($Rs32.h,$Rt32.h):<<1", 15890tc_bafaade3, TypeM>, Enc_5ab2be { 15891let Inst{7-5} = 0b011; 15892let Inst{13-13} = 0b0; 15893let Inst{31-21} = 0b11101100110; 15894let hasNewValue = 1; 15895let opNewValue = 0; 15896let prefersSlot3 = 1; 15897} 15898def M2_mpyu_hl_s0 : HInst< 15899(outs IntRegs:$Rd32), 15900(ins IntRegs:$Rs32, IntRegs:$Rt32), 15901"$Rd32 = mpyu($Rs32.h,$Rt32.l)", 15902tc_bafaade3, TypeM>, Enc_5ab2be { 15903let Inst{7-5} = 0b010; 15904let Inst{13-13} = 0b0; 15905let Inst{31-21} = 0b11101100010; 15906let hasNewValue = 1; 15907let opNewValue = 0; 15908let prefersSlot3 = 1; 15909} 15910def M2_mpyu_hl_s1 : HInst< 15911(outs IntRegs:$Rd32), 15912(ins IntRegs:$Rs32, IntRegs:$Rt32), 15913"$Rd32 = mpyu($Rs32.h,$Rt32.l):<<1", 15914tc_bafaade3, TypeM>, Enc_5ab2be { 15915let Inst{7-5} = 0b010; 15916let Inst{13-13} = 0b0; 15917let Inst{31-21} = 0b11101100110; 15918let hasNewValue = 1; 15919let opNewValue = 0; 15920let prefersSlot3 = 1; 15921} 15922def M2_mpyu_lh_s0 : HInst< 15923(outs IntRegs:$Rd32), 15924(ins IntRegs:$Rs32, IntRegs:$Rt32), 15925"$Rd32 = mpyu($Rs32.l,$Rt32.h)", 15926tc_bafaade3, TypeM>, Enc_5ab2be { 15927let Inst{7-5} = 0b001; 15928let Inst{13-13} = 0b0; 15929let Inst{31-21} = 0b11101100010; 15930let hasNewValue = 1; 15931let opNewValue = 0; 15932let prefersSlot3 = 1; 15933} 15934def M2_mpyu_lh_s1 : HInst< 15935(outs IntRegs:$Rd32), 15936(ins IntRegs:$Rs32, IntRegs:$Rt32), 15937"$Rd32 = mpyu($Rs32.l,$Rt32.h):<<1", 15938tc_bafaade3, TypeM>, Enc_5ab2be { 15939let Inst{7-5} = 0b001; 15940let Inst{13-13} = 0b0; 15941let Inst{31-21} = 0b11101100110; 15942let hasNewValue = 1; 15943let opNewValue = 0; 15944let prefersSlot3 = 1; 15945} 15946def M2_mpyu_ll_s0 : HInst< 15947(outs IntRegs:$Rd32), 15948(ins IntRegs:$Rs32, IntRegs:$Rt32), 15949"$Rd32 = mpyu($Rs32.l,$Rt32.l)", 15950tc_bafaade3, TypeM>, Enc_5ab2be { 15951let Inst{7-5} = 0b000; 15952let Inst{13-13} = 0b0; 15953let Inst{31-21} = 0b11101100010; 15954let hasNewValue = 1; 15955let opNewValue = 0; 15956let prefersSlot3 = 1; 15957} 15958def M2_mpyu_ll_s1 : HInst< 15959(outs IntRegs:$Rd32), 15960(ins IntRegs:$Rs32, IntRegs:$Rt32), 15961"$Rd32 = mpyu($Rs32.l,$Rt32.l):<<1", 15962tc_bafaade3, TypeM>, Enc_5ab2be { 15963let Inst{7-5} = 0b000; 15964let Inst{13-13} = 0b0; 15965let Inst{31-21} = 0b11101100110; 15966let hasNewValue = 1; 15967let opNewValue = 0; 15968let prefersSlot3 = 1; 15969} 15970def M2_mpyu_nac_hh_s0 : HInst< 15971(outs IntRegs:$Rx32), 15972(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), 15973"$Rx32 -= mpyu($Rs32.h,$Rt32.h)", 15974tc_d773585a, TypeM>, Enc_2ae154 { 15975let Inst{7-5} = 0b011; 15976let Inst{13-13} = 0b0; 15977let Inst{31-21} = 0b11101110011; 15978let hasNewValue = 1; 15979let opNewValue = 0; 15980let prefersSlot3 = 1; 15981let Constraints = "$Rx32 = $Rx32in"; 15982} 15983def M2_mpyu_nac_hh_s1 : HInst< 15984(outs IntRegs:$Rx32), 15985(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), 15986"$Rx32 -= mpyu($Rs32.h,$Rt32.h):<<1", 15987tc_d773585a, TypeM>, Enc_2ae154 { 15988let Inst{7-5} = 0b011; 15989let Inst{13-13} = 0b0; 15990let Inst{31-21} = 0b11101110111; 15991let hasNewValue = 1; 15992let opNewValue = 0; 15993let prefersSlot3 = 1; 15994let Constraints = "$Rx32 = $Rx32in"; 15995} 15996def M2_mpyu_nac_hl_s0 : HInst< 15997(outs IntRegs:$Rx32), 15998(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), 15999"$Rx32 -= mpyu($Rs32.h,$Rt32.l)", 16000tc_d773585a, TypeM>, Enc_2ae154 { 16001let Inst{7-5} = 0b010; 16002let Inst{13-13} = 0b0; 16003let Inst{31-21} = 0b11101110011; 16004let hasNewValue = 1; 16005let opNewValue = 0; 16006let prefersSlot3 = 1; 16007let Constraints = "$Rx32 = $Rx32in"; 16008} 16009def M2_mpyu_nac_hl_s1 : HInst< 16010(outs IntRegs:$Rx32), 16011(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), 16012"$Rx32 -= mpyu($Rs32.h,$Rt32.l):<<1", 16013tc_d773585a, TypeM>, Enc_2ae154 { 16014let Inst{7-5} = 0b010; 16015let Inst{13-13} = 0b0; 16016let Inst{31-21} = 0b11101110111; 16017let hasNewValue = 1; 16018let opNewValue = 0; 16019let prefersSlot3 = 1; 16020let Constraints = "$Rx32 = $Rx32in"; 16021} 16022def M2_mpyu_nac_lh_s0 : HInst< 16023(outs IntRegs:$Rx32), 16024(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), 16025"$Rx32 -= mpyu($Rs32.l,$Rt32.h)", 16026tc_d773585a, TypeM>, Enc_2ae154 { 16027let Inst{7-5} = 0b001; 16028let Inst{13-13} = 0b0; 16029let Inst{31-21} = 0b11101110011; 16030let hasNewValue = 1; 16031let opNewValue = 0; 16032let prefersSlot3 = 1; 16033let Constraints = "$Rx32 = $Rx32in"; 16034} 16035def M2_mpyu_nac_lh_s1 : HInst< 16036(outs IntRegs:$Rx32), 16037(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), 16038"$Rx32 -= mpyu($Rs32.l,$Rt32.h):<<1", 16039tc_d773585a, TypeM>, Enc_2ae154 { 16040let Inst{7-5} = 0b001; 16041let Inst{13-13} = 0b0; 16042let Inst{31-21} = 0b11101110111; 16043let hasNewValue = 1; 16044let opNewValue = 0; 16045let prefersSlot3 = 1; 16046let Constraints = "$Rx32 = $Rx32in"; 16047} 16048def M2_mpyu_nac_ll_s0 : HInst< 16049(outs IntRegs:$Rx32), 16050(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), 16051"$Rx32 -= mpyu($Rs32.l,$Rt32.l)", 16052tc_d773585a, TypeM>, Enc_2ae154 { 16053let Inst{7-5} = 0b000; 16054let Inst{13-13} = 0b0; 16055let Inst{31-21} = 0b11101110011; 16056let hasNewValue = 1; 16057let opNewValue = 0; 16058let prefersSlot3 = 1; 16059let Constraints = "$Rx32 = $Rx32in"; 16060} 16061def M2_mpyu_nac_ll_s1 : HInst< 16062(outs IntRegs:$Rx32), 16063(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), 16064"$Rx32 -= mpyu($Rs32.l,$Rt32.l):<<1", 16065tc_d773585a, TypeM>, Enc_2ae154 { 16066let Inst{7-5} = 0b000; 16067let Inst{13-13} = 0b0; 16068let Inst{31-21} = 0b11101110111; 16069let hasNewValue = 1; 16070let opNewValue = 0; 16071let prefersSlot3 = 1; 16072let Constraints = "$Rx32 = $Rx32in"; 16073} 16074def M2_mpyu_up : HInst< 16075(outs IntRegs:$Rd32), 16076(ins IntRegs:$Rs32, IntRegs:$Rt32), 16077"$Rd32 = mpyu($Rs32,$Rt32)", 16078tc_bafaade3, TypeM>, Enc_5ab2be { 16079let Inst{7-5} = 0b001; 16080let Inst{13-13} = 0b0; 16081let Inst{31-21} = 0b11101101010; 16082let hasNewValue = 1; 16083let opNewValue = 0; 16084let prefersSlot3 = 1; 16085} 16086def M2_mpyud_acc_hh_s0 : HInst< 16087(outs DoubleRegs:$Rxx32), 16088(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), 16089"$Rxx32 += mpyu($Rs32.h,$Rt32.h)", 16090tc_d773585a, TypeM>, Enc_61f0b0 { 16091let Inst{7-5} = 0b011; 16092let Inst{13-13} = 0b0; 16093let Inst{31-21} = 0b11100110010; 16094let prefersSlot3 = 1; 16095let Constraints = "$Rxx32 = $Rxx32in"; 16096} 16097def M2_mpyud_acc_hh_s1 : HInst< 16098(outs DoubleRegs:$Rxx32), 16099(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), 16100"$Rxx32 += mpyu($Rs32.h,$Rt32.h):<<1", 16101tc_d773585a, TypeM>, Enc_61f0b0 { 16102let Inst{7-5} = 0b011; 16103let Inst{13-13} = 0b0; 16104let Inst{31-21} = 0b11100110110; 16105let prefersSlot3 = 1; 16106let Constraints = "$Rxx32 = $Rxx32in"; 16107} 16108def M2_mpyud_acc_hl_s0 : HInst< 16109(outs DoubleRegs:$Rxx32), 16110(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), 16111"$Rxx32 += mpyu($Rs32.h,$Rt32.l)", 16112tc_d773585a, TypeM>, Enc_61f0b0 { 16113let Inst{7-5} = 0b010; 16114let Inst{13-13} = 0b0; 16115let Inst{31-21} = 0b11100110010; 16116let prefersSlot3 = 1; 16117let Constraints = "$Rxx32 = $Rxx32in"; 16118} 16119def M2_mpyud_acc_hl_s1 : HInst< 16120(outs DoubleRegs:$Rxx32), 16121(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), 16122"$Rxx32 += mpyu($Rs32.h,$Rt32.l):<<1", 16123tc_d773585a, TypeM>, Enc_61f0b0 { 16124let Inst{7-5} = 0b010; 16125let Inst{13-13} = 0b0; 16126let Inst{31-21} = 0b11100110110; 16127let prefersSlot3 = 1; 16128let Constraints = "$Rxx32 = $Rxx32in"; 16129} 16130def M2_mpyud_acc_lh_s0 : HInst< 16131(outs DoubleRegs:$Rxx32), 16132(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), 16133"$Rxx32 += mpyu($Rs32.l,$Rt32.h)", 16134tc_d773585a, TypeM>, Enc_61f0b0 { 16135let Inst{7-5} = 0b001; 16136let Inst{13-13} = 0b0; 16137let Inst{31-21} = 0b11100110010; 16138let prefersSlot3 = 1; 16139let Constraints = "$Rxx32 = $Rxx32in"; 16140} 16141def M2_mpyud_acc_lh_s1 : HInst< 16142(outs DoubleRegs:$Rxx32), 16143(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), 16144"$Rxx32 += mpyu($Rs32.l,$Rt32.h):<<1", 16145tc_d773585a, TypeM>, Enc_61f0b0 { 16146let Inst{7-5} = 0b001; 16147let Inst{13-13} = 0b0; 16148let Inst{31-21} = 0b11100110110; 16149let prefersSlot3 = 1; 16150let Constraints = "$Rxx32 = $Rxx32in"; 16151} 16152def M2_mpyud_acc_ll_s0 : HInst< 16153(outs DoubleRegs:$Rxx32), 16154(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), 16155"$Rxx32 += mpyu($Rs32.l,$Rt32.l)", 16156tc_d773585a, TypeM>, Enc_61f0b0 { 16157let Inst{7-5} = 0b000; 16158let Inst{13-13} = 0b0; 16159let Inst{31-21} = 0b11100110010; 16160let prefersSlot3 = 1; 16161let Constraints = "$Rxx32 = $Rxx32in"; 16162} 16163def M2_mpyud_acc_ll_s1 : HInst< 16164(outs DoubleRegs:$Rxx32), 16165(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), 16166"$Rxx32 += mpyu($Rs32.l,$Rt32.l):<<1", 16167tc_d773585a, TypeM>, Enc_61f0b0 { 16168let Inst{7-5} = 0b000; 16169let Inst{13-13} = 0b0; 16170let Inst{31-21} = 0b11100110110; 16171let prefersSlot3 = 1; 16172let Constraints = "$Rxx32 = $Rxx32in"; 16173} 16174def M2_mpyud_hh_s0 : HInst< 16175(outs DoubleRegs:$Rdd32), 16176(ins IntRegs:$Rs32, IntRegs:$Rt32), 16177"$Rdd32 = mpyu($Rs32.h,$Rt32.h)", 16178tc_bafaade3, TypeM>, Enc_be32a5 { 16179let Inst{7-5} = 0b011; 16180let Inst{13-13} = 0b0; 16181let Inst{31-21} = 0b11100100010; 16182let prefersSlot3 = 1; 16183} 16184def M2_mpyud_hh_s1 : HInst< 16185(outs DoubleRegs:$Rdd32), 16186(ins IntRegs:$Rs32, IntRegs:$Rt32), 16187"$Rdd32 = mpyu($Rs32.h,$Rt32.h):<<1", 16188tc_bafaade3, TypeM>, Enc_be32a5 { 16189let Inst{7-5} = 0b011; 16190let Inst{13-13} = 0b0; 16191let Inst{31-21} = 0b11100100110; 16192let prefersSlot3 = 1; 16193} 16194def M2_mpyud_hl_s0 : HInst< 16195(outs DoubleRegs:$Rdd32), 16196(ins IntRegs:$Rs32, IntRegs:$Rt32), 16197"$Rdd32 = mpyu($Rs32.h,$Rt32.l)", 16198tc_bafaade3, TypeM>, Enc_be32a5 { 16199let Inst{7-5} = 0b010; 16200let Inst{13-13} = 0b0; 16201let Inst{31-21} = 0b11100100010; 16202let prefersSlot3 = 1; 16203} 16204def M2_mpyud_hl_s1 : HInst< 16205(outs DoubleRegs:$Rdd32), 16206(ins IntRegs:$Rs32, IntRegs:$Rt32), 16207"$Rdd32 = mpyu($Rs32.h,$Rt32.l):<<1", 16208tc_bafaade3, TypeM>, Enc_be32a5 { 16209let Inst{7-5} = 0b010; 16210let Inst{13-13} = 0b0; 16211let Inst{31-21} = 0b11100100110; 16212let prefersSlot3 = 1; 16213} 16214def M2_mpyud_lh_s0 : HInst< 16215(outs DoubleRegs:$Rdd32), 16216(ins IntRegs:$Rs32, IntRegs:$Rt32), 16217"$Rdd32 = mpyu($Rs32.l,$Rt32.h)", 16218tc_bafaade3, TypeM>, Enc_be32a5 { 16219let Inst{7-5} = 0b001; 16220let Inst{13-13} = 0b0; 16221let Inst{31-21} = 0b11100100010; 16222let prefersSlot3 = 1; 16223} 16224def M2_mpyud_lh_s1 : HInst< 16225(outs DoubleRegs:$Rdd32), 16226(ins IntRegs:$Rs32, IntRegs:$Rt32), 16227"$Rdd32 = mpyu($Rs32.l,$Rt32.h):<<1", 16228tc_bafaade3, TypeM>, Enc_be32a5 { 16229let Inst{7-5} = 0b001; 16230let Inst{13-13} = 0b0; 16231let Inst{31-21} = 0b11100100110; 16232let prefersSlot3 = 1; 16233} 16234def M2_mpyud_ll_s0 : HInst< 16235(outs DoubleRegs:$Rdd32), 16236(ins IntRegs:$Rs32, IntRegs:$Rt32), 16237"$Rdd32 = mpyu($Rs32.l,$Rt32.l)", 16238tc_bafaade3, TypeM>, Enc_be32a5 { 16239let Inst{7-5} = 0b000; 16240let Inst{13-13} = 0b0; 16241let Inst{31-21} = 0b11100100010; 16242let prefersSlot3 = 1; 16243} 16244def M2_mpyud_ll_s1 : HInst< 16245(outs DoubleRegs:$Rdd32), 16246(ins IntRegs:$Rs32, IntRegs:$Rt32), 16247"$Rdd32 = mpyu($Rs32.l,$Rt32.l):<<1", 16248tc_bafaade3, TypeM>, Enc_be32a5 { 16249let Inst{7-5} = 0b000; 16250let Inst{13-13} = 0b0; 16251let Inst{31-21} = 0b11100100110; 16252let prefersSlot3 = 1; 16253} 16254def M2_mpyud_nac_hh_s0 : HInst< 16255(outs DoubleRegs:$Rxx32), 16256(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), 16257"$Rxx32 -= mpyu($Rs32.h,$Rt32.h)", 16258tc_d773585a, TypeM>, Enc_61f0b0 { 16259let Inst{7-5} = 0b011; 16260let Inst{13-13} = 0b0; 16261let Inst{31-21} = 0b11100110011; 16262let prefersSlot3 = 1; 16263let Constraints = "$Rxx32 = $Rxx32in"; 16264} 16265def M2_mpyud_nac_hh_s1 : HInst< 16266(outs DoubleRegs:$Rxx32), 16267(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), 16268"$Rxx32 -= mpyu($Rs32.h,$Rt32.h):<<1", 16269tc_d773585a, TypeM>, Enc_61f0b0 { 16270let Inst{7-5} = 0b011; 16271let Inst{13-13} = 0b0; 16272let Inst{31-21} = 0b11100110111; 16273let prefersSlot3 = 1; 16274let Constraints = "$Rxx32 = $Rxx32in"; 16275} 16276def M2_mpyud_nac_hl_s0 : HInst< 16277(outs DoubleRegs:$Rxx32), 16278(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), 16279"$Rxx32 -= mpyu($Rs32.h,$Rt32.l)", 16280tc_d773585a, TypeM>, Enc_61f0b0 { 16281let Inst{7-5} = 0b010; 16282let Inst{13-13} = 0b0; 16283let Inst{31-21} = 0b11100110011; 16284let prefersSlot3 = 1; 16285let Constraints = "$Rxx32 = $Rxx32in"; 16286} 16287def M2_mpyud_nac_hl_s1 : HInst< 16288(outs DoubleRegs:$Rxx32), 16289(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), 16290"$Rxx32 -= mpyu($Rs32.h,$Rt32.l):<<1", 16291tc_d773585a, TypeM>, Enc_61f0b0 { 16292let Inst{7-5} = 0b010; 16293let Inst{13-13} = 0b0; 16294let Inst{31-21} = 0b11100110111; 16295let prefersSlot3 = 1; 16296let Constraints = "$Rxx32 = $Rxx32in"; 16297} 16298def M2_mpyud_nac_lh_s0 : HInst< 16299(outs DoubleRegs:$Rxx32), 16300(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), 16301"$Rxx32 -= mpyu($Rs32.l,$Rt32.h)", 16302tc_d773585a, TypeM>, Enc_61f0b0 { 16303let Inst{7-5} = 0b001; 16304let Inst{13-13} = 0b0; 16305let Inst{31-21} = 0b11100110011; 16306let prefersSlot3 = 1; 16307let Constraints = "$Rxx32 = $Rxx32in"; 16308} 16309def M2_mpyud_nac_lh_s1 : HInst< 16310(outs DoubleRegs:$Rxx32), 16311(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), 16312"$Rxx32 -= mpyu($Rs32.l,$Rt32.h):<<1", 16313tc_d773585a, TypeM>, Enc_61f0b0 { 16314let Inst{7-5} = 0b001; 16315let Inst{13-13} = 0b0; 16316let Inst{31-21} = 0b11100110111; 16317let prefersSlot3 = 1; 16318let Constraints = "$Rxx32 = $Rxx32in"; 16319} 16320def M2_mpyud_nac_ll_s0 : HInst< 16321(outs DoubleRegs:$Rxx32), 16322(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), 16323"$Rxx32 -= mpyu($Rs32.l,$Rt32.l)", 16324tc_d773585a, TypeM>, Enc_61f0b0 { 16325let Inst{7-5} = 0b000; 16326let Inst{13-13} = 0b0; 16327let Inst{31-21} = 0b11100110011; 16328let prefersSlot3 = 1; 16329let Constraints = "$Rxx32 = $Rxx32in"; 16330} 16331def M2_mpyud_nac_ll_s1 : HInst< 16332(outs DoubleRegs:$Rxx32), 16333(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), 16334"$Rxx32 -= mpyu($Rs32.l,$Rt32.l):<<1", 16335tc_d773585a, TypeM>, Enc_61f0b0 { 16336let Inst{7-5} = 0b000; 16337let Inst{13-13} = 0b0; 16338let Inst{31-21} = 0b11100110111; 16339let prefersSlot3 = 1; 16340let Constraints = "$Rxx32 = $Rxx32in"; 16341} 16342def M2_mpyui : HInst< 16343(outs IntRegs:$Rd32), 16344(ins IntRegs:$Rs32, IntRegs:$Rt32), 16345"$Rd32 = mpyui($Rs32,$Rt32)", 16346tc_bafaade3, TypeM> { 16347let hasNewValue = 1; 16348let opNewValue = 0; 16349let isPseudo = 1; 16350let isCodeGenOnly = 1; 16351} 16352def M2_nacci : HInst< 16353(outs IntRegs:$Rx32), 16354(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), 16355"$Rx32 -= add($Rs32,$Rt32)", 16356tc_f675fee8, TypeM>, Enc_2ae154 { 16357let Inst{7-5} = 0b001; 16358let Inst{13-13} = 0b0; 16359let Inst{31-21} = 0b11101111100; 16360let hasNewValue = 1; 16361let opNewValue = 0; 16362let prefersSlot3 = 1; 16363let InputType = "reg"; 16364let Constraints = "$Rx32 = $Rx32in"; 16365} 16366def M2_naccii : HInst< 16367(outs IntRegs:$Rx32), 16368(ins IntRegs:$Rx32in, IntRegs:$Rs32, s32_0Imm:$Ii), 16369"$Rx32 -= add($Rs32,#$Ii)", 16370tc_f675fee8, TypeM>, Enc_c90aca { 16371let Inst{13-13} = 0b0; 16372let Inst{31-21} = 0b11100010100; 16373let hasNewValue = 1; 16374let opNewValue = 0; 16375let prefersSlot3 = 1; 16376let InputType = "imm"; 16377let isExtendable = 1; 16378let opExtendable = 3; 16379let isExtentSigned = 1; 16380let opExtentBits = 8; 16381let opExtentAlign = 0; 16382let Constraints = "$Rx32 = $Rx32in"; 16383} 16384def M2_subacc : HInst< 16385(outs IntRegs:$Rx32), 16386(ins IntRegs:$Rx32in, IntRegs:$Rt32, IntRegs:$Rs32), 16387"$Rx32 += sub($Rt32,$Rs32)", 16388tc_f675fee8, TypeM>, Enc_a568d4 { 16389let Inst{7-5} = 0b011; 16390let Inst{13-13} = 0b0; 16391let Inst{31-21} = 0b11101111000; 16392let hasNewValue = 1; 16393let opNewValue = 0; 16394let prefersSlot3 = 1; 16395let InputType = "reg"; 16396let Constraints = "$Rx32 = $Rx32in"; 16397} 16398def M2_vabsdiffh : HInst< 16399(outs DoubleRegs:$Rdd32), 16400(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), 16401"$Rdd32 = vabsdiffh($Rtt32,$Rss32)", 16402tc_002cb246, TypeM>, Enc_ea23e4 { 16403let Inst{7-5} = 0b000; 16404let Inst{13-13} = 0b0; 16405let Inst{31-21} = 0b11101000011; 16406let prefersSlot3 = 1; 16407} 16408def M2_vabsdiffw : HInst< 16409(outs DoubleRegs:$Rdd32), 16410(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), 16411"$Rdd32 = vabsdiffw($Rtt32,$Rss32)", 16412tc_002cb246, TypeM>, Enc_ea23e4 { 16413let Inst{7-5} = 0b000; 16414let Inst{13-13} = 0b0; 16415let Inst{31-21} = 0b11101000001; 16416let prefersSlot3 = 1; 16417} 16418def M2_vcmac_s0_sat_i : HInst< 16419(outs DoubleRegs:$Rxx32), 16420(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 16421"$Rxx32 += vcmpyi($Rss32,$Rtt32):sat", 16422tc_d773585a, TypeM>, Enc_88c16c { 16423let Inst{7-5} = 0b100; 16424let Inst{13-13} = 0b0; 16425let Inst{31-21} = 0b11101010010; 16426let prefersSlot3 = 1; 16427let Defs = [USR_OVF]; 16428let Constraints = "$Rxx32 = $Rxx32in"; 16429} 16430def M2_vcmac_s0_sat_r : HInst< 16431(outs DoubleRegs:$Rxx32), 16432(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 16433"$Rxx32 += vcmpyr($Rss32,$Rtt32):sat", 16434tc_d773585a, TypeM>, Enc_88c16c { 16435let Inst{7-5} = 0b100; 16436let Inst{13-13} = 0b0; 16437let Inst{31-21} = 0b11101010001; 16438let prefersSlot3 = 1; 16439let Defs = [USR_OVF]; 16440let Constraints = "$Rxx32 = $Rxx32in"; 16441} 16442def M2_vcmpy_s0_sat_i : HInst< 16443(outs DoubleRegs:$Rdd32), 16444(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 16445"$Rdd32 = vcmpyi($Rss32,$Rtt32):sat", 16446tc_bafaade3, TypeM>, Enc_a56825 { 16447let Inst{7-5} = 0b110; 16448let Inst{13-13} = 0b0; 16449let Inst{31-21} = 0b11101000010; 16450let prefersSlot3 = 1; 16451let Defs = [USR_OVF]; 16452} 16453def M2_vcmpy_s0_sat_r : HInst< 16454(outs DoubleRegs:$Rdd32), 16455(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 16456"$Rdd32 = vcmpyr($Rss32,$Rtt32):sat", 16457tc_bafaade3, TypeM>, Enc_a56825 { 16458let Inst{7-5} = 0b110; 16459let Inst{13-13} = 0b0; 16460let Inst{31-21} = 0b11101000001; 16461let prefersSlot3 = 1; 16462let Defs = [USR_OVF]; 16463} 16464def M2_vcmpy_s1_sat_i : HInst< 16465(outs DoubleRegs:$Rdd32), 16466(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 16467"$Rdd32 = vcmpyi($Rss32,$Rtt32):<<1:sat", 16468tc_bafaade3, TypeM>, Enc_a56825 { 16469let Inst{7-5} = 0b110; 16470let Inst{13-13} = 0b0; 16471let Inst{31-21} = 0b11101000110; 16472let prefersSlot3 = 1; 16473let Defs = [USR_OVF]; 16474} 16475def M2_vcmpy_s1_sat_r : HInst< 16476(outs DoubleRegs:$Rdd32), 16477(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 16478"$Rdd32 = vcmpyr($Rss32,$Rtt32):<<1:sat", 16479tc_bafaade3, TypeM>, Enc_a56825 { 16480let Inst{7-5} = 0b110; 16481let Inst{13-13} = 0b0; 16482let Inst{31-21} = 0b11101000101; 16483let prefersSlot3 = 1; 16484let Defs = [USR_OVF]; 16485} 16486def M2_vdmacs_s0 : HInst< 16487(outs DoubleRegs:$Rxx32), 16488(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 16489"$Rxx32 += vdmpy($Rss32,$Rtt32):sat", 16490tc_d773585a, TypeM>, Enc_88c16c { 16491let Inst{7-5} = 0b100; 16492let Inst{13-13} = 0b0; 16493let Inst{31-21} = 0b11101010000; 16494let prefersSlot3 = 1; 16495let Defs = [USR_OVF]; 16496let Constraints = "$Rxx32 = $Rxx32in"; 16497} 16498def M2_vdmacs_s1 : HInst< 16499(outs DoubleRegs:$Rxx32), 16500(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 16501"$Rxx32 += vdmpy($Rss32,$Rtt32):<<1:sat", 16502tc_d773585a, TypeM>, Enc_88c16c { 16503let Inst{7-5} = 0b100; 16504let Inst{13-13} = 0b0; 16505let Inst{31-21} = 0b11101010100; 16506let prefersSlot3 = 1; 16507let Defs = [USR_OVF]; 16508let Constraints = "$Rxx32 = $Rxx32in"; 16509} 16510def M2_vdmpyrs_s0 : HInst< 16511(outs IntRegs:$Rd32), 16512(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 16513"$Rd32 = vdmpy($Rss32,$Rtt32):rnd:sat", 16514tc_bafaade3, TypeM>, Enc_d2216a { 16515let Inst{7-5} = 0b000; 16516let Inst{13-13} = 0b0; 16517let Inst{31-21} = 0b11101001000; 16518let hasNewValue = 1; 16519let opNewValue = 0; 16520let prefersSlot3 = 1; 16521let Defs = [USR_OVF]; 16522} 16523def M2_vdmpyrs_s1 : HInst< 16524(outs IntRegs:$Rd32), 16525(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 16526"$Rd32 = vdmpy($Rss32,$Rtt32):<<1:rnd:sat", 16527tc_bafaade3, TypeM>, Enc_d2216a { 16528let Inst{7-5} = 0b000; 16529let Inst{13-13} = 0b0; 16530let Inst{31-21} = 0b11101001100; 16531let hasNewValue = 1; 16532let opNewValue = 0; 16533let prefersSlot3 = 1; 16534let Defs = [USR_OVF]; 16535} 16536def M2_vdmpys_s0 : HInst< 16537(outs DoubleRegs:$Rdd32), 16538(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 16539"$Rdd32 = vdmpy($Rss32,$Rtt32):sat", 16540tc_bafaade3, TypeM>, Enc_a56825 { 16541let Inst{7-5} = 0b100; 16542let Inst{13-13} = 0b0; 16543let Inst{31-21} = 0b11101000000; 16544let prefersSlot3 = 1; 16545let Defs = [USR_OVF]; 16546} 16547def M2_vdmpys_s1 : HInst< 16548(outs DoubleRegs:$Rdd32), 16549(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 16550"$Rdd32 = vdmpy($Rss32,$Rtt32):<<1:sat", 16551tc_bafaade3, TypeM>, Enc_a56825 { 16552let Inst{7-5} = 0b100; 16553let Inst{13-13} = 0b0; 16554let Inst{31-21} = 0b11101000100; 16555let prefersSlot3 = 1; 16556let Defs = [USR_OVF]; 16557} 16558def M2_vmac2 : HInst< 16559(outs DoubleRegs:$Rxx32), 16560(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), 16561"$Rxx32 += vmpyh($Rs32,$Rt32)", 16562tc_d773585a, TypeM>, Enc_61f0b0 { 16563let Inst{7-5} = 0b001; 16564let Inst{13-13} = 0b0; 16565let Inst{31-21} = 0b11100111001; 16566let prefersSlot3 = 1; 16567let Constraints = "$Rxx32 = $Rxx32in"; 16568} 16569def M2_vmac2es : HInst< 16570(outs DoubleRegs:$Rxx32), 16571(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 16572"$Rxx32 += vmpyeh($Rss32,$Rtt32)", 16573tc_d773585a, TypeM>, Enc_88c16c { 16574let Inst{7-5} = 0b010; 16575let Inst{13-13} = 0b0; 16576let Inst{31-21} = 0b11101010001; 16577let prefersSlot3 = 1; 16578let Constraints = "$Rxx32 = $Rxx32in"; 16579} 16580def M2_vmac2es_s0 : HInst< 16581(outs DoubleRegs:$Rxx32), 16582(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 16583"$Rxx32 += vmpyeh($Rss32,$Rtt32):sat", 16584tc_d773585a, TypeM>, Enc_88c16c { 16585let Inst{7-5} = 0b110; 16586let Inst{13-13} = 0b0; 16587let Inst{31-21} = 0b11101010000; 16588let prefersSlot3 = 1; 16589let Defs = [USR_OVF]; 16590let Constraints = "$Rxx32 = $Rxx32in"; 16591} 16592def M2_vmac2es_s1 : HInst< 16593(outs DoubleRegs:$Rxx32), 16594(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 16595"$Rxx32 += vmpyeh($Rss32,$Rtt32):<<1:sat", 16596tc_d773585a, TypeM>, Enc_88c16c { 16597let Inst{7-5} = 0b110; 16598let Inst{13-13} = 0b0; 16599let Inst{31-21} = 0b11101010100; 16600let prefersSlot3 = 1; 16601let Defs = [USR_OVF]; 16602let Constraints = "$Rxx32 = $Rxx32in"; 16603} 16604def M2_vmac2s_s0 : HInst< 16605(outs DoubleRegs:$Rxx32), 16606(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), 16607"$Rxx32 += vmpyh($Rs32,$Rt32):sat", 16608tc_d773585a, TypeM>, Enc_61f0b0 { 16609let Inst{7-5} = 0b101; 16610let Inst{13-13} = 0b0; 16611let Inst{31-21} = 0b11100111000; 16612let prefersSlot3 = 1; 16613let Defs = [USR_OVF]; 16614let Constraints = "$Rxx32 = $Rxx32in"; 16615} 16616def M2_vmac2s_s1 : HInst< 16617(outs DoubleRegs:$Rxx32), 16618(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), 16619"$Rxx32 += vmpyh($Rs32,$Rt32):<<1:sat", 16620tc_d773585a, TypeM>, Enc_61f0b0 { 16621let Inst{7-5} = 0b101; 16622let Inst{13-13} = 0b0; 16623let Inst{31-21} = 0b11100111100; 16624let prefersSlot3 = 1; 16625let Defs = [USR_OVF]; 16626let Constraints = "$Rxx32 = $Rxx32in"; 16627} 16628def M2_vmac2su_s0 : HInst< 16629(outs DoubleRegs:$Rxx32), 16630(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), 16631"$Rxx32 += vmpyhsu($Rs32,$Rt32):sat", 16632tc_d773585a, TypeM>, Enc_61f0b0 { 16633let Inst{7-5} = 0b101; 16634let Inst{13-13} = 0b0; 16635let Inst{31-21} = 0b11100111011; 16636let prefersSlot3 = 1; 16637let Defs = [USR_OVF]; 16638let Constraints = "$Rxx32 = $Rxx32in"; 16639} 16640def M2_vmac2su_s1 : HInst< 16641(outs DoubleRegs:$Rxx32), 16642(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), 16643"$Rxx32 += vmpyhsu($Rs32,$Rt32):<<1:sat", 16644tc_d773585a, TypeM>, Enc_61f0b0 { 16645let Inst{7-5} = 0b101; 16646let Inst{13-13} = 0b0; 16647let Inst{31-21} = 0b11100111111; 16648let prefersSlot3 = 1; 16649let Defs = [USR_OVF]; 16650let Constraints = "$Rxx32 = $Rxx32in"; 16651} 16652def M2_vmpy2es_s0 : HInst< 16653(outs DoubleRegs:$Rdd32), 16654(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 16655"$Rdd32 = vmpyeh($Rss32,$Rtt32):sat", 16656tc_bafaade3, TypeM>, Enc_a56825 { 16657let Inst{7-5} = 0b110; 16658let Inst{13-13} = 0b0; 16659let Inst{31-21} = 0b11101000000; 16660let prefersSlot3 = 1; 16661let Defs = [USR_OVF]; 16662} 16663def M2_vmpy2es_s1 : HInst< 16664(outs DoubleRegs:$Rdd32), 16665(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 16666"$Rdd32 = vmpyeh($Rss32,$Rtt32):<<1:sat", 16667tc_bafaade3, TypeM>, Enc_a56825 { 16668let Inst{7-5} = 0b110; 16669let Inst{13-13} = 0b0; 16670let Inst{31-21} = 0b11101000100; 16671let prefersSlot3 = 1; 16672let Defs = [USR_OVF]; 16673} 16674def M2_vmpy2s_s0 : HInst< 16675(outs DoubleRegs:$Rdd32), 16676(ins IntRegs:$Rs32, IntRegs:$Rt32), 16677"$Rdd32 = vmpyh($Rs32,$Rt32):sat", 16678tc_bafaade3, TypeM>, Enc_be32a5 { 16679let Inst{7-5} = 0b101; 16680let Inst{13-13} = 0b0; 16681let Inst{31-21} = 0b11100101000; 16682let prefersSlot3 = 1; 16683let Defs = [USR_OVF]; 16684} 16685def M2_vmpy2s_s0pack : HInst< 16686(outs IntRegs:$Rd32), 16687(ins IntRegs:$Rs32, IntRegs:$Rt32), 16688"$Rd32 = vmpyh($Rs32,$Rt32):rnd:sat", 16689tc_bafaade3, TypeM>, Enc_5ab2be { 16690let Inst{7-5} = 0b111; 16691let Inst{13-13} = 0b0; 16692let Inst{31-21} = 0b11101101001; 16693let hasNewValue = 1; 16694let opNewValue = 0; 16695let prefersSlot3 = 1; 16696let Defs = [USR_OVF]; 16697} 16698def M2_vmpy2s_s1 : HInst< 16699(outs DoubleRegs:$Rdd32), 16700(ins IntRegs:$Rs32, IntRegs:$Rt32), 16701"$Rdd32 = vmpyh($Rs32,$Rt32):<<1:sat", 16702tc_bafaade3, TypeM>, Enc_be32a5 { 16703let Inst{7-5} = 0b101; 16704let Inst{13-13} = 0b0; 16705let Inst{31-21} = 0b11100101100; 16706let prefersSlot3 = 1; 16707let Defs = [USR_OVF]; 16708} 16709def M2_vmpy2s_s1pack : HInst< 16710(outs IntRegs:$Rd32), 16711(ins IntRegs:$Rs32, IntRegs:$Rt32), 16712"$Rd32 = vmpyh($Rs32,$Rt32):<<1:rnd:sat", 16713tc_bafaade3, TypeM>, Enc_5ab2be { 16714let Inst{7-5} = 0b111; 16715let Inst{13-13} = 0b0; 16716let Inst{31-21} = 0b11101101101; 16717let hasNewValue = 1; 16718let opNewValue = 0; 16719let prefersSlot3 = 1; 16720let Defs = [USR_OVF]; 16721} 16722def M2_vmpy2su_s0 : HInst< 16723(outs DoubleRegs:$Rdd32), 16724(ins IntRegs:$Rs32, IntRegs:$Rt32), 16725"$Rdd32 = vmpyhsu($Rs32,$Rt32):sat", 16726tc_bafaade3, TypeM>, Enc_be32a5 { 16727let Inst{7-5} = 0b111; 16728let Inst{13-13} = 0b0; 16729let Inst{31-21} = 0b11100101000; 16730let prefersSlot3 = 1; 16731let Defs = [USR_OVF]; 16732} 16733def M2_vmpy2su_s1 : HInst< 16734(outs DoubleRegs:$Rdd32), 16735(ins IntRegs:$Rs32, IntRegs:$Rt32), 16736"$Rdd32 = vmpyhsu($Rs32,$Rt32):<<1:sat", 16737tc_bafaade3, TypeM>, Enc_be32a5 { 16738let Inst{7-5} = 0b111; 16739let Inst{13-13} = 0b0; 16740let Inst{31-21} = 0b11100101100; 16741let prefersSlot3 = 1; 16742let Defs = [USR_OVF]; 16743} 16744def M2_vraddh : HInst< 16745(outs IntRegs:$Rd32), 16746(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 16747"$Rd32 = vraddh($Rss32,$Rtt32)", 16748tc_bafaade3, TypeM>, Enc_d2216a { 16749let Inst{7-5} = 0b111; 16750let Inst{13-13} = 0b0; 16751let Inst{31-21} = 0b11101001001; 16752let hasNewValue = 1; 16753let opNewValue = 0; 16754let prefersSlot3 = 1; 16755} 16756def M2_vradduh : HInst< 16757(outs IntRegs:$Rd32), 16758(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 16759"$Rd32 = vradduh($Rss32,$Rtt32)", 16760tc_bafaade3, TypeM>, Enc_d2216a { 16761let Inst{7-5} = 0b001; 16762let Inst{13-13} = 0b0; 16763let Inst{31-21} = 0b11101001000; 16764let hasNewValue = 1; 16765let opNewValue = 0; 16766let prefersSlot3 = 1; 16767} 16768def M2_vrcmaci_s0 : HInst< 16769(outs DoubleRegs:$Rxx32), 16770(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 16771"$Rxx32 += vrcmpyi($Rss32,$Rtt32)", 16772tc_d773585a, TypeM>, Enc_88c16c { 16773let Inst{7-5} = 0b000; 16774let Inst{13-13} = 0b0; 16775let Inst{31-21} = 0b11101010000; 16776let prefersSlot3 = 1; 16777let Constraints = "$Rxx32 = $Rxx32in"; 16778} 16779def M2_vrcmaci_s0c : HInst< 16780(outs DoubleRegs:$Rxx32), 16781(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 16782"$Rxx32 += vrcmpyi($Rss32,$Rtt32*)", 16783tc_d773585a, TypeM>, Enc_88c16c { 16784let Inst{7-5} = 0b000; 16785let Inst{13-13} = 0b0; 16786let Inst{31-21} = 0b11101010010; 16787let prefersSlot3 = 1; 16788let Constraints = "$Rxx32 = $Rxx32in"; 16789} 16790def M2_vrcmacr_s0 : HInst< 16791(outs DoubleRegs:$Rxx32), 16792(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 16793"$Rxx32 += vrcmpyr($Rss32,$Rtt32)", 16794tc_d773585a, TypeM>, Enc_88c16c { 16795let Inst{7-5} = 0b001; 16796let Inst{13-13} = 0b0; 16797let Inst{31-21} = 0b11101010000; 16798let prefersSlot3 = 1; 16799let Constraints = "$Rxx32 = $Rxx32in"; 16800} 16801def M2_vrcmacr_s0c : HInst< 16802(outs DoubleRegs:$Rxx32), 16803(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 16804"$Rxx32 += vrcmpyr($Rss32,$Rtt32*)", 16805tc_d773585a, TypeM>, Enc_88c16c { 16806let Inst{7-5} = 0b001; 16807let Inst{13-13} = 0b0; 16808let Inst{31-21} = 0b11101010011; 16809let prefersSlot3 = 1; 16810let Constraints = "$Rxx32 = $Rxx32in"; 16811} 16812def M2_vrcmpyi_s0 : HInst< 16813(outs DoubleRegs:$Rdd32), 16814(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 16815"$Rdd32 = vrcmpyi($Rss32,$Rtt32)", 16816tc_bafaade3, TypeM>, Enc_a56825 { 16817let Inst{7-5} = 0b000; 16818let Inst{13-13} = 0b0; 16819let Inst{31-21} = 0b11101000000; 16820let prefersSlot3 = 1; 16821} 16822def M2_vrcmpyi_s0c : HInst< 16823(outs DoubleRegs:$Rdd32), 16824(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 16825"$Rdd32 = vrcmpyi($Rss32,$Rtt32*)", 16826tc_bafaade3, TypeM>, Enc_a56825 { 16827let Inst{7-5} = 0b000; 16828let Inst{13-13} = 0b0; 16829let Inst{31-21} = 0b11101000010; 16830let prefersSlot3 = 1; 16831} 16832def M2_vrcmpyr_s0 : HInst< 16833(outs DoubleRegs:$Rdd32), 16834(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 16835"$Rdd32 = vrcmpyr($Rss32,$Rtt32)", 16836tc_bafaade3, TypeM>, Enc_a56825 { 16837let Inst{7-5} = 0b001; 16838let Inst{13-13} = 0b0; 16839let Inst{31-21} = 0b11101000000; 16840let prefersSlot3 = 1; 16841} 16842def M2_vrcmpyr_s0c : HInst< 16843(outs DoubleRegs:$Rdd32), 16844(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 16845"$Rdd32 = vrcmpyr($Rss32,$Rtt32*)", 16846tc_bafaade3, TypeM>, Enc_a56825 { 16847let Inst{7-5} = 0b001; 16848let Inst{13-13} = 0b0; 16849let Inst{31-21} = 0b11101000011; 16850let prefersSlot3 = 1; 16851} 16852def M2_vrcmpys_acc_s1 : HInst< 16853(outs DoubleRegs:$Rxx32), 16854(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32), 16855"$Rxx32 += vrcmpys($Rss32,$Rt32):<<1:sat", 16856tc_d773585a, TypeM> { 16857let isPseudo = 1; 16858let Constraints = "$Rxx32 = $Rxx32in"; 16859} 16860def M2_vrcmpys_acc_s1_h : HInst< 16861(outs DoubleRegs:$Rxx32), 16862(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 16863"$Rxx32 += vrcmpys($Rss32,$Rtt32):<<1:sat:raw:hi", 16864tc_d773585a, TypeM>, Enc_88c16c { 16865let Inst{7-5} = 0b100; 16866let Inst{13-13} = 0b0; 16867let Inst{31-21} = 0b11101010101; 16868let prefersSlot3 = 1; 16869let Defs = [USR_OVF]; 16870let Constraints = "$Rxx32 = $Rxx32in"; 16871} 16872def M2_vrcmpys_acc_s1_l : HInst< 16873(outs DoubleRegs:$Rxx32), 16874(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 16875"$Rxx32 += vrcmpys($Rss32,$Rtt32):<<1:sat:raw:lo", 16876tc_d773585a, TypeM>, Enc_88c16c { 16877let Inst{7-5} = 0b100; 16878let Inst{13-13} = 0b0; 16879let Inst{31-21} = 0b11101010111; 16880let prefersSlot3 = 1; 16881let Defs = [USR_OVF]; 16882let Constraints = "$Rxx32 = $Rxx32in"; 16883} 16884def M2_vrcmpys_s1 : HInst< 16885(outs DoubleRegs:$Rdd32), 16886(ins DoubleRegs:$Rss32, IntRegs:$Rt32), 16887"$Rdd32 = vrcmpys($Rss32,$Rt32):<<1:sat", 16888tc_bafaade3, TypeM> { 16889let isPseudo = 1; 16890} 16891def M2_vrcmpys_s1_h : HInst< 16892(outs DoubleRegs:$Rdd32), 16893(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 16894"$Rdd32 = vrcmpys($Rss32,$Rtt32):<<1:sat:raw:hi", 16895tc_bafaade3, TypeM>, Enc_a56825 { 16896let Inst{7-5} = 0b100; 16897let Inst{13-13} = 0b0; 16898let Inst{31-21} = 0b11101000101; 16899let prefersSlot3 = 1; 16900let Defs = [USR_OVF]; 16901} 16902def M2_vrcmpys_s1_l : HInst< 16903(outs DoubleRegs:$Rdd32), 16904(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 16905"$Rdd32 = vrcmpys($Rss32,$Rtt32):<<1:sat:raw:lo", 16906tc_bafaade3, TypeM>, Enc_a56825 { 16907let Inst{7-5} = 0b100; 16908let Inst{13-13} = 0b0; 16909let Inst{31-21} = 0b11101000111; 16910let prefersSlot3 = 1; 16911let Defs = [USR_OVF]; 16912} 16913def M2_vrcmpys_s1rp : HInst< 16914(outs IntRegs:$Rd32), 16915(ins DoubleRegs:$Rss32, IntRegs:$Rt32), 16916"$Rd32 = vrcmpys($Rss32,$Rt32):<<1:rnd:sat", 16917tc_bafaade3, TypeM> { 16918let hasNewValue = 1; 16919let opNewValue = 0; 16920let isPseudo = 1; 16921} 16922def M2_vrcmpys_s1rp_h : HInst< 16923(outs IntRegs:$Rd32), 16924(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 16925"$Rd32 = vrcmpys($Rss32,$Rtt32):<<1:rnd:sat:raw:hi", 16926tc_bafaade3, TypeM>, Enc_d2216a { 16927let Inst{7-5} = 0b110; 16928let Inst{13-13} = 0b0; 16929let Inst{31-21} = 0b11101001101; 16930let hasNewValue = 1; 16931let opNewValue = 0; 16932let prefersSlot3 = 1; 16933let Defs = [USR_OVF]; 16934} 16935def M2_vrcmpys_s1rp_l : HInst< 16936(outs IntRegs:$Rd32), 16937(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 16938"$Rd32 = vrcmpys($Rss32,$Rtt32):<<1:rnd:sat:raw:lo", 16939tc_bafaade3, TypeM>, Enc_d2216a { 16940let Inst{7-5} = 0b111; 16941let Inst{13-13} = 0b0; 16942let Inst{31-21} = 0b11101001101; 16943let hasNewValue = 1; 16944let opNewValue = 0; 16945let prefersSlot3 = 1; 16946let Defs = [USR_OVF]; 16947} 16948def M2_vrmac_s0 : HInst< 16949(outs DoubleRegs:$Rxx32), 16950(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 16951"$Rxx32 += vrmpyh($Rss32,$Rtt32)", 16952tc_d773585a, TypeM>, Enc_88c16c { 16953let Inst{7-5} = 0b010; 16954let Inst{13-13} = 0b0; 16955let Inst{31-21} = 0b11101010000; 16956let prefersSlot3 = 1; 16957let Constraints = "$Rxx32 = $Rxx32in"; 16958} 16959def M2_vrmpy_s0 : HInst< 16960(outs DoubleRegs:$Rdd32), 16961(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 16962"$Rdd32 = vrmpyh($Rss32,$Rtt32)", 16963tc_bafaade3, TypeM>, Enc_a56825 { 16964let Inst{7-5} = 0b010; 16965let Inst{13-13} = 0b0; 16966let Inst{31-21} = 0b11101000000; 16967let prefersSlot3 = 1; 16968} 16969def M2_xor_xacc : HInst< 16970(outs IntRegs:$Rx32), 16971(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), 16972"$Rx32 ^= xor($Rs32,$Rt32)", 16973tc_f429765c, TypeM>, Enc_2ae154 { 16974let Inst{7-5} = 0b011; 16975let Inst{13-13} = 0b0; 16976let Inst{31-21} = 0b11101111100; 16977let hasNewValue = 1; 16978let opNewValue = 0; 16979let prefersSlot3 = 1; 16980let InputType = "reg"; 16981let Constraints = "$Rx32 = $Rx32in"; 16982} 16983def M4_and_and : HInst< 16984(outs IntRegs:$Rx32), 16985(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), 16986"$Rx32 &= and($Rs32,$Rt32)", 16987tc_f429765c, TypeM>, Enc_2ae154 { 16988let Inst{7-5} = 0b000; 16989let Inst{13-13} = 0b0; 16990let Inst{31-21} = 0b11101111010; 16991let hasNewValue = 1; 16992let opNewValue = 0; 16993let prefersSlot3 = 1; 16994let InputType = "reg"; 16995let Constraints = "$Rx32 = $Rx32in"; 16996} 16997def M4_and_andn : HInst< 16998(outs IntRegs:$Rx32), 16999(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), 17000"$Rx32 &= and($Rs32,~$Rt32)", 17001tc_f429765c, TypeM>, Enc_2ae154 { 17002let Inst{7-5} = 0b001; 17003let Inst{13-13} = 0b0; 17004let Inst{31-21} = 0b11101111001; 17005let hasNewValue = 1; 17006let opNewValue = 0; 17007let prefersSlot3 = 1; 17008let InputType = "reg"; 17009let Constraints = "$Rx32 = $Rx32in"; 17010} 17011def M4_and_or : HInst< 17012(outs IntRegs:$Rx32), 17013(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), 17014"$Rx32 &= or($Rs32,$Rt32)", 17015tc_f429765c, TypeM>, Enc_2ae154 { 17016let Inst{7-5} = 0b001; 17017let Inst{13-13} = 0b0; 17018let Inst{31-21} = 0b11101111010; 17019let hasNewValue = 1; 17020let opNewValue = 0; 17021let prefersSlot3 = 1; 17022let InputType = "reg"; 17023let Constraints = "$Rx32 = $Rx32in"; 17024} 17025def M4_and_xor : HInst< 17026(outs IntRegs:$Rx32), 17027(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), 17028"$Rx32 &= xor($Rs32,$Rt32)", 17029tc_f429765c, TypeM>, Enc_2ae154 { 17030let Inst{7-5} = 0b010; 17031let Inst{13-13} = 0b0; 17032let Inst{31-21} = 0b11101111010; 17033let hasNewValue = 1; 17034let opNewValue = 0; 17035let prefersSlot3 = 1; 17036let InputType = "reg"; 17037let Constraints = "$Rx32 = $Rx32in"; 17038} 17039def M4_cmpyi_wh : HInst< 17040(outs IntRegs:$Rd32), 17041(ins DoubleRegs:$Rss32, IntRegs:$Rt32), 17042"$Rd32 = cmpyiwh($Rss32,$Rt32):<<1:rnd:sat", 17043tc_bafaade3, TypeS_3op>, Enc_3d5b28 { 17044let Inst{7-5} = 0b100; 17045let Inst{13-13} = 0b0; 17046let Inst{31-21} = 0b11000101000; 17047let hasNewValue = 1; 17048let opNewValue = 0; 17049let prefersSlot3 = 1; 17050let Defs = [USR_OVF]; 17051} 17052def M4_cmpyi_whc : HInst< 17053(outs IntRegs:$Rd32), 17054(ins DoubleRegs:$Rss32, IntRegs:$Rt32), 17055"$Rd32 = cmpyiwh($Rss32,$Rt32*):<<1:rnd:sat", 17056tc_bafaade3, TypeS_3op>, Enc_3d5b28 { 17057let Inst{7-5} = 0b101; 17058let Inst{13-13} = 0b0; 17059let Inst{31-21} = 0b11000101000; 17060let hasNewValue = 1; 17061let opNewValue = 0; 17062let prefersSlot3 = 1; 17063let Defs = [USR_OVF]; 17064} 17065def M4_cmpyr_wh : HInst< 17066(outs IntRegs:$Rd32), 17067(ins DoubleRegs:$Rss32, IntRegs:$Rt32), 17068"$Rd32 = cmpyrwh($Rss32,$Rt32):<<1:rnd:sat", 17069tc_bafaade3, TypeS_3op>, Enc_3d5b28 { 17070let Inst{7-5} = 0b110; 17071let Inst{13-13} = 0b0; 17072let Inst{31-21} = 0b11000101000; 17073let hasNewValue = 1; 17074let opNewValue = 0; 17075let prefersSlot3 = 1; 17076let Defs = [USR_OVF]; 17077} 17078def M4_cmpyr_whc : HInst< 17079(outs IntRegs:$Rd32), 17080(ins DoubleRegs:$Rss32, IntRegs:$Rt32), 17081"$Rd32 = cmpyrwh($Rss32,$Rt32*):<<1:rnd:sat", 17082tc_bafaade3, TypeS_3op>, Enc_3d5b28 { 17083let Inst{7-5} = 0b111; 17084let Inst{13-13} = 0b0; 17085let Inst{31-21} = 0b11000101000; 17086let hasNewValue = 1; 17087let opNewValue = 0; 17088let prefersSlot3 = 1; 17089let Defs = [USR_OVF]; 17090} 17091def M4_mac_up_s1_sat : HInst< 17092(outs IntRegs:$Rx32), 17093(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), 17094"$Rx32 += mpy($Rs32,$Rt32):<<1:sat", 17095tc_d773585a, TypeM>, Enc_2ae154 { 17096let Inst{7-5} = 0b000; 17097let Inst{13-13} = 0b0; 17098let Inst{31-21} = 0b11101111011; 17099let hasNewValue = 1; 17100let opNewValue = 0; 17101let prefersSlot3 = 1; 17102let Defs = [USR_OVF]; 17103let InputType = "reg"; 17104let Constraints = "$Rx32 = $Rx32in"; 17105} 17106def M4_mpyri_addi : HInst< 17107(outs IntRegs:$Rd32), 17108(ins u32_0Imm:$Ii, IntRegs:$Rs32, u6_0Imm:$II), 17109"$Rd32 = add(#$Ii,mpyi($Rs32,#$II))", 17110tc_05d3a09b, TypeALU64>, Enc_322e1b, ImmRegRel { 17111let Inst{31-24} = 0b11011000; 17112let hasNewValue = 1; 17113let opNewValue = 0; 17114let prefersSlot3 = 1; 17115let CextOpcode = "M4_mpyri_addr"; 17116let isExtendable = 1; 17117let opExtendable = 1; 17118let isExtentSigned = 0; 17119let opExtentBits = 6; 17120let opExtentAlign = 0; 17121} 17122def M4_mpyri_addr : HInst< 17123(outs IntRegs:$Rd32), 17124(ins IntRegs:$Ru32, IntRegs:$Rs32, u32_0Imm:$Ii), 17125"$Rd32 = add($Ru32,mpyi($Rs32,#$Ii))", 17126tc_05d3a09b, TypeALU64>, Enc_420cf3, ImmRegRel { 17127let Inst{31-23} = 0b110111111; 17128let hasNewValue = 1; 17129let opNewValue = 0; 17130let prefersSlot3 = 1; 17131let CextOpcode = "M4_mpyri_addr"; 17132let InputType = "imm"; 17133let isExtendable = 1; 17134let opExtendable = 3; 17135let isExtentSigned = 0; 17136let opExtentBits = 6; 17137let opExtentAlign = 0; 17138} 17139def M4_mpyri_addr_u2 : HInst< 17140(outs IntRegs:$Rd32), 17141(ins IntRegs:$Ru32, u6_2Imm:$Ii, IntRegs:$Rs32), 17142"$Rd32 = add($Ru32,mpyi(#$Ii,$Rs32))", 17143tc_1a2fd869, TypeALU64>, Enc_277737 { 17144let Inst{31-23} = 0b110111110; 17145let hasNewValue = 1; 17146let opNewValue = 0; 17147let prefersSlot3 = 1; 17148} 17149def M4_mpyrr_addi : HInst< 17150(outs IntRegs:$Rd32), 17151(ins u32_0Imm:$Ii, IntRegs:$Rs32, IntRegs:$Rt32), 17152"$Rd32 = add(#$Ii,mpyi($Rs32,$Rt32))", 17153tc_d773585a, TypeALU64>, Enc_a7b8e8, ImmRegRel { 17154let Inst{31-23} = 0b110101110; 17155let hasNewValue = 1; 17156let opNewValue = 0; 17157let prefersSlot3 = 1; 17158let CextOpcode = "M4_mpyrr_addr"; 17159let InputType = "imm"; 17160let isExtendable = 1; 17161let opExtendable = 1; 17162let isExtentSigned = 0; 17163let opExtentBits = 6; 17164let opExtentAlign = 0; 17165} 17166def M4_mpyrr_addr : HInst< 17167(outs IntRegs:$Ry32), 17168(ins IntRegs:$Ru32, IntRegs:$Ry32in, IntRegs:$Rs32), 17169"$Ry32 = add($Ru32,mpyi($Ry32in,$Rs32))", 17170tc_d773585a, TypeM>, Enc_7f1a05, ImmRegRel { 17171let Inst{7-5} = 0b000; 17172let Inst{13-13} = 0b0; 17173let Inst{31-21} = 0b11100011000; 17174let hasNewValue = 1; 17175let opNewValue = 0; 17176let prefersSlot3 = 1; 17177let CextOpcode = "M4_mpyrr_addr"; 17178let InputType = "reg"; 17179let Constraints = "$Ry32 = $Ry32in"; 17180} 17181def M4_nac_up_s1_sat : HInst< 17182(outs IntRegs:$Rx32), 17183(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), 17184"$Rx32 -= mpy($Rs32,$Rt32):<<1:sat", 17185tc_d773585a, TypeM>, Enc_2ae154 { 17186let Inst{7-5} = 0b001; 17187let Inst{13-13} = 0b0; 17188let Inst{31-21} = 0b11101111011; 17189let hasNewValue = 1; 17190let opNewValue = 0; 17191let prefersSlot3 = 1; 17192let Defs = [USR_OVF]; 17193let InputType = "reg"; 17194let Constraints = "$Rx32 = $Rx32in"; 17195} 17196def M4_or_and : HInst< 17197(outs IntRegs:$Rx32), 17198(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), 17199"$Rx32 |= and($Rs32,$Rt32)", 17200tc_f429765c, TypeM>, Enc_2ae154 { 17201let Inst{7-5} = 0b011; 17202let Inst{13-13} = 0b0; 17203let Inst{31-21} = 0b11101111010; 17204let hasNewValue = 1; 17205let opNewValue = 0; 17206let prefersSlot3 = 1; 17207let InputType = "reg"; 17208let Constraints = "$Rx32 = $Rx32in"; 17209} 17210def M4_or_andn : HInst< 17211(outs IntRegs:$Rx32), 17212(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), 17213"$Rx32 |= and($Rs32,~$Rt32)", 17214tc_f429765c, TypeM>, Enc_2ae154 { 17215let Inst{7-5} = 0b000; 17216let Inst{13-13} = 0b0; 17217let Inst{31-21} = 0b11101111001; 17218let hasNewValue = 1; 17219let opNewValue = 0; 17220let prefersSlot3 = 1; 17221let InputType = "reg"; 17222let Constraints = "$Rx32 = $Rx32in"; 17223} 17224def M4_or_or : HInst< 17225(outs IntRegs:$Rx32), 17226(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), 17227"$Rx32 |= or($Rs32,$Rt32)", 17228tc_f429765c, TypeM>, Enc_2ae154 { 17229let Inst{7-5} = 0b000; 17230let Inst{13-13} = 0b0; 17231let Inst{31-21} = 0b11101111110; 17232let hasNewValue = 1; 17233let opNewValue = 0; 17234let prefersSlot3 = 1; 17235let InputType = "reg"; 17236let Constraints = "$Rx32 = $Rx32in"; 17237} 17238def M4_or_xor : HInst< 17239(outs IntRegs:$Rx32), 17240(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), 17241"$Rx32 |= xor($Rs32,$Rt32)", 17242tc_f429765c, TypeM>, Enc_2ae154 { 17243let Inst{7-5} = 0b001; 17244let Inst{13-13} = 0b0; 17245let Inst{31-21} = 0b11101111110; 17246let hasNewValue = 1; 17247let opNewValue = 0; 17248let prefersSlot3 = 1; 17249let InputType = "reg"; 17250let Constraints = "$Rx32 = $Rx32in"; 17251} 17252def M4_pmpyw : HInst< 17253(outs DoubleRegs:$Rdd32), 17254(ins IntRegs:$Rs32, IntRegs:$Rt32), 17255"$Rdd32 = pmpyw($Rs32,$Rt32)", 17256tc_bafaade3, TypeM>, Enc_be32a5 { 17257let Inst{7-5} = 0b111; 17258let Inst{13-13} = 0b0; 17259let Inst{31-21} = 0b11100101010; 17260let prefersSlot3 = 1; 17261} 17262def M4_pmpyw_acc : HInst< 17263(outs DoubleRegs:$Rxx32), 17264(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), 17265"$Rxx32 ^= pmpyw($Rs32,$Rt32)", 17266tc_d773585a, TypeM>, Enc_61f0b0 { 17267let Inst{7-5} = 0b111; 17268let Inst{13-13} = 0b0; 17269let Inst{31-21} = 0b11100111001; 17270let prefersSlot3 = 1; 17271let Constraints = "$Rxx32 = $Rxx32in"; 17272} 17273def M4_vpmpyh : HInst< 17274(outs DoubleRegs:$Rdd32), 17275(ins IntRegs:$Rs32, IntRegs:$Rt32), 17276"$Rdd32 = vpmpyh($Rs32,$Rt32)", 17277tc_bafaade3, TypeM>, Enc_be32a5 { 17278let Inst{7-5} = 0b111; 17279let Inst{13-13} = 0b0; 17280let Inst{31-21} = 0b11100101110; 17281let prefersSlot3 = 1; 17282} 17283def M4_vpmpyh_acc : HInst< 17284(outs DoubleRegs:$Rxx32), 17285(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), 17286"$Rxx32 ^= vpmpyh($Rs32,$Rt32)", 17287tc_d773585a, TypeM>, Enc_61f0b0 { 17288let Inst{7-5} = 0b111; 17289let Inst{13-13} = 0b0; 17290let Inst{31-21} = 0b11100111101; 17291let prefersSlot3 = 1; 17292let Constraints = "$Rxx32 = $Rxx32in"; 17293} 17294def M4_vrmpyeh_acc_s0 : HInst< 17295(outs DoubleRegs:$Rxx32), 17296(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 17297"$Rxx32 += vrmpyweh($Rss32,$Rtt32)", 17298tc_d773585a, TypeM>, Enc_88c16c { 17299let Inst{7-5} = 0b110; 17300let Inst{13-13} = 0b0; 17301let Inst{31-21} = 0b11101010001; 17302let prefersSlot3 = 1; 17303let Constraints = "$Rxx32 = $Rxx32in"; 17304} 17305def M4_vrmpyeh_acc_s1 : HInst< 17306(outs DoubleRegs:$Rxx32), 17307(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 17308"$Rxx32 += vrmpyweh($Rss32,$Rtt32):<<1", 17309tc_d773585a, TypeM>, Enc_88c16c { 17310let Inst{7-5} = 0b110; 17311let Inst{13-13} = 0b0; 17312let Inst{31-21} = 0b11101010101; 17313let prefersSlot3 = 1; 17314let Constraints = "$Rxx32 = $Rxx32in"; 17315} 17316def M4_vrmpyeh_s0 : HInst< 17317(outs DoubleRegs:$Rdd32), 17318(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 17319"$Rdd32 = vrmpyweh($Rss32,$Rtt32)", 17320tc_bafaade3, TypeM>, Enc_a56825 { 17321let Inst{7-5} = 0b100; 17322let Inst{13-13} = 0b0; 17323let Inst{31-21} = 0b11101000010; 17324let prefersSlot3 = 1; 17325} 17326def M4_vrmpyeh_s1 : HInst< 17327(outs DoubleRegs:$Rdd32), 17328(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 17329"$Rdd32 = vrmpyweh($Rss32,$Rtt32):<<1", 17330tc_bafaade3, TypeM>, Enc_a56825 { 17331let Inst{7-5} = 0b100; 17332let Inst{13-13} = 0b0; 17333let Inst{31-21} = 0b11101000110; 17334let prefersSlot3 = 1; 17335} 17336def M4_vrmpyoh_acc_s0 : HInst< 17337(outs DoubleRegs:$Rxx32), 17338(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 17339"$Rxx32 += vrmpywoh($Rss32,$Rtt32)", 17340tc_d773585a, TypeM>, Enc_88c16c { 17341let Inst{7-5} = 0b110; 17342let Inst{13-13} = 0b0; 17343let Inst{31-21} = 0b11101010011; 17344let prefersSlot3 = 1; 17345let Constraints = "$Rxx32 = $Rxx32in"; 17346} 17347def M4_vrmpyoh_acc_s1 : HInst< 17348(outs DoubleRegs:$Rxx32), 17349(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 17350"$Rxx32 += vrmpywoh($Rss32,$Rtt32):<<1", 17351tc_d773585a, TypeM>, Enc_88c16c { 17352let Inst{7-5} = 0b110; 17353let Inst{13-13} = 0b0; 17354let Inst{31-21} = 0b11101010111; 17355let prefersSlot3 = 1; 17356let Constraints = "$Rxx32 = $Rxx32in"; 17357} 17358def M4_vrmpyoh_s0 : HInst< 17359(outs DoubleRegs:$Rdd32), 17360(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 17361"$Rdd32 = vrmpywoh($Rss32,$Rtt32)", 17362tc_bafaade3, TypeM>, Enc_a56825 { 17363let Inst{7-5} = 0b010; 17364let Inst{13-13} = 0b0; 17365let Inst{31-21} = 0b11101000001; 17366let prefersSlot3 = 1; 17367} 17368def M4_vrmpyoh_s1 : HInst< 17369(outs DoubleRegs:$Rdd32), 17370(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 17371"$Rdd32 = vrmpywoh($Rss32,$Rtt32):<<1", 17372tc_bafaade3, TypeM>, Enc_a56825 { 17373let Inst{7-5} = 0b010; 17374let Inst{13-13} = 0b0; 17375let Inst{31-21} = 0b11101000101; 17376let prefersSlot3 = 1; 17377} 17378def M4_xor_and : HInst< 17379(outs IntRegs:$Rx32), 17380(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), 17381"$Rx32 ^= and($Rs32,$Rt32)", 17382tc_f429765c, TypeM>, Enc_2ae154 { 17383let Inst{7-5} = 0b010; 17384let Inst{13-13} = 0b0; 17385let Inst{31-21} = 0b11101111110; 17386let hasNewValue = 1; 17387let opNewValue = 0; 17388let prefersSlot3 = 1; 17389let InputType = "reg"; 17390let Constraints = "$Rx32 = $Rx32in"; 17391} 17392def M4_xor_andn : HInst< 17393(outs IntRegs:$Rx32), 17394(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), 17395"$Rx32 ^= and($Rs32,~$Rt32)", 17396tc_f429765c, TypeM>, Enc_2ae154 { 17397let Inst{7-5} = 0b010; 17398let Inst{13-13} = 0b0; 17399let Inst{31-21} = 0b11101111001; 17400let hasNewValue = 1; 17401let opNewValue = 0; 17402let prefersSlot3 = 1; 17403let InputType = "reg"; 17404let Constraints = "$Rx32 = $Rx32in"; 17405} 17406def M4_xor_or : HInst< 17407(outs IntRegs:$Rx32), 17408(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), 17409"$Rx32 ^= or($Rs32,$Rt32)", 17410tc_f429765c, TypeM>, Enc_2ae154 { 17411let Inst{7-5} = 0b011; 17412let Inst{13-13} = 0b0; 17413let Inst{31-21} = 0b11101111110; 17414let hasNewValue = 1; 17415let opNewValue = 0; 17416let prefersSlot3 = 1; 17417let InputType = "reg"; 17418let Constraints = "$Rx32 = $Rx32in"; 17419} 17420def M4_xor_xacc : HInst< 17421(outs DoubleRegs:$Rxx32), 17422(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 17423"$Rxx32 ^= xor($Rss32,$Rtt32)", 17424tc_f429765c, TypeS_3op>, Enc_88c16c { 17425let Inst{7-5} = 0b000; 17426let Inst{13-13} = 0b0; 17427let Inst{31-21} = 0b11001010100; 17428let prefersSlot3 = 1; 17429let Constraints = "$Rxx32 = $Rxx32in"; 17430} 17431def M5_vdmacbsu : HInst< 17432(outs DoubleRegs:$Rxx32), 17433(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 17434"$Rxx32 += vdmpybsu($Rss32,$Rtt32):sat", 17435tc_d773585a, TypeM>, Enc_88c16c { 17436let Inst{7-5} = 0b001; 17437let Inst{13-13} = 0b0; 17438let Inst{31-21} = 0b11101010001; 17439let prefersSlot3 = 1; 17440let Defs = [USR_OVF]; 17441let Constraints = "$Rxx32 = $Rxx32in"; 17442} 17443def M5_vdmpybsu : HInst< 17444(outs DoubleRegs:$Rdd32), 17445(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 17446"$Rdd32 = vdmpybsu($Rss32,$Rtt32):sat", 17447tc_bafaade3, TypeM>, Enc_a56825 { 17448let Inst{7-5} = 0b001; 17449let Inst{13-13} = 0b0; 17450let Inst{31-21} = 0b11101000101; 17451let prefersSlot3 = 1; 17452let Defs = [USR_OVF]; 17453} 17454def M5_vmacbsu : HInst< 17455(outs DoubleRegs:$Rxx32), 17456(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), 17457"$Rxx32 += vmpybsu($Rs32,$Rt32)", 17458tc_d773585a, TypeM>, Enc_61f0b0 { 17459let Inst{7-5} = 0b001; 17460let Inst{13-13} = 0b0; 17461let Inst{31-21} = 0b11100111110; 17462let prefersSlot3 = 1; 17463let Constraints = "$Rxx32 = $Rxx32in"; 17464} 17465def M5_vmacbuu : HInst< 17466(outs DoubleRegs:$Rxx32), 17467(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), 17468"$Rxx32 += vmpybu($Rs32,$Rt32)", 17469tc_d773585a, TypeM>, Enc_61f0b0 { 17470let Inst{7-5} = 0b001; 17471let Inst{13-13} = 0b0; 17472let Inst{31-21} = 0b11100111100; 17473let prefersSlot3 = 1; 17474let Constraints = "$Rxx32 = $Rxx32in"; 17475} 17476def M5_vmpybsu : HInst< 17477(outs DoubleRegs:$Rdd32), 17478(ins IntRegs:$Rs32, IntRegs:$Rt32), 17479"$Rdd32 = vmpybsu($Rs32,$Rt32)", 17480tc_bafaade3, TypeM>, Enc_be32a5 { 17481let Inst{7-5} = 0b001; 17482let Inst{13-13} = 0b0; 17483let Inst{31-21} = 0b11100101010; 17484let prefersSlot3 = 1; 17485} 17486def M5_vmpybuu : HInst< 17487(outs DoubleRegs:$Rdd32), 17488(ins IntRegs:$Rs32, IntRegs:$Rt32), 17489"$Rdd32 = vmpybu($Rs32,$Rt32)", 17490tc_bafaade3, TypeM>, Enc_be32a5 { 17491let Inst{7-5} = 0b001; 17492let Inst{13-13} = 0b0; 17493let Inst{31-21} = 0b11100101100; 17494let prefersSlot3 = 1; 17495} 17496def M5_vrmacbsu : HInst< 17497(outs DoubleRegs:$Rxx32), 17498(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 17499"$Rxx32 += vrmpybsu($Rss32,$Rtt32)", 17500tc_d773585a, TypeM>, Enc_88c16c { 17501let Inst{7-5} = 0b001; 17502let Inst{13-13} = 0b0; 17503let Inst{31-21} = 0b11101010110; 17504let prefersSlot3 = 1; 17505let Constraints = "$Rxx32 = $Rxx32in"; 17506} 17507def M5_vrmacbuu : HInst< 17508(outs DoubleRegs:$Rxx32), 17509(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 17510"$Rxx32 += vrmpybu($Rss32,$Rtt32)", 17511tc_d773585a, TypeM>, Enc_88c16c { 17512let Inst{7-5} = 0b001; 17513let Inst{13-13} = 0b0; 17514let Inst{31-21} = 0b11101010100; 17515let prefersSlot3 = 1; 17516let Constraints = "$Rxx32 = $Rxx32in"; 17517} 17518def M5_vrmpybsu : HInst< 17519(outs DoubleRegs:$Rdd32), 17520(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 17521"$Rdd32 = vrmpybsu($Rss32,$Rtt32)", 17522tc_bafaade3, TypeM>, Enc_a56825 { 17523let Inst{7-5} = 0b001; 17524let Inst{13-13} = 0b0; 17525let Inst{31-21} = 0b11101000110; 17526let prefersSlot3 = 1; 17527} 17528def M5_vrmpybuu : HInst< 17529(outs DoubleRegs:$Rdd32), 17530(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 17531"$Rdd32 = vrmpybu($Rss32,$Rtt32)", 17532tc_bafaade3, TypeM>, Enc_a56825 { 17533let Inst{7-5} = 0b001; 17534let Inst{13-13} = 0b0; 17535let Inst{31-21} = 0b11101000100; 17536let prefersSlot3 = 1; 17537} 17538def M6_vabsdiffb : HInst< 17539(outs DoubleRegs:$Rdd32), 17540(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), 17541"$Rdd32 = vabsdiffb($Rtt32,$Rss32)", 17542tc_9461ff31, TypeM>, Enc_ea23e4, Requires<[HasV62]> { 17543let Inst{7-5} = 0b000; 17544let Inst{13-13} = 0b0; 17545let Inst{31-21} = 0b11101000111; 17546let prefersSlot3 = 1; 17547} 17548def M6_vabsdiffub : HInst< 17549(outs DoubleRegs:$Rdd32), 17550(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), 17551"$Rdd32 = vabsdiffub($Rtt32,$Rss32)", 17552tc_9461ff31, TypeM>, Enc_ea23e4, Requires<[HasV62]> { 17553let Inst{7-5} = 0b000; 17554let Inst{13-13} = 0b0; 17555let Inst{31-21} = 0b11101000101; 17556let prefersSlot3 = 1; 17557} 17558def PS_loadrbabs : HInst< 17559(outs IntRegs:$Rd32), 17560(ins u32_0Imm:$Ii), 17561"$Rd32 = memb(#$Ii)", 17562tc_c4db48cb, TypeV2LDST>, Enc_25bef0, AddrModeRel { 17563let Inst{24-21} = 0b1000; 17564let Inst{31-27} = 0b01001; 17565let hasNewValue = 1; 17566let opNewValue = 0; 17567let addrMode = Absolute; 17568let accessSize = ByteAccess; 17569let mayLoad = 1; 17570let isExtended = 1; 17571let CextOpcode = "L2_loadrb"; 17572let BaseOpcode = "L4_loadrb_abs"; 17573let isPredicable = 1; 17574let DecoderNamespace = "MustExtend"; 17575let isExtended = 1; 17576let opExtendable = 1; 17577let isExtentSigned = 0; 17578let opExtentBits = 16; 17579let opExtentAlign = 0; 17580} 17581def PS_loadrdabs : HInst< 17582(outs DoubleRegs:$Rdd32), 17583(ins u29_3Imm:$Ii), 17584"$Rdd32 = memd(#$Ii)", 17585tc_c4db48cb, TypeV2LDST>, Enc_509701, AddrModeRel { 17586let Inst{24-21} = 0b1110; 17587let Inst{31-27} = 0b01001; 17588let addrMode = Absolute; 17589let accessSize = DoubleWordAccess; 17590let mayLoad = 1; 17591let isExtended = 1; 17592let CextOpcode = "L2_loadrd"; 17593let BaseOpcode = "L4_loadrd_abs"; 17594let isPredicable = 1; 17595let DecoderNamespace = "MustExtend"; 17596let isExtended = 1; 17597let opExtendable = 1; 17598let isExtentSigned = 0; 17599let opExtentBits = 19; 17600let opExtentAlign = 3; 17601} 17602def PS_loadrhabs : HInst< 17603(outs IntRegs:$Rd32), 17604(ins u31_1Imm:$Ii), 17605"$Rd32 = memh(#$Ii)", 17606tc_c4db48cb, TypeV2LDST>, Enc_8df4be, AddrModeRel { 17607let Inst{24-21} = 0b1010; 17608let Inst{31-27} = 0b01001; 17609let hasNewValue = 1; 17610let opNewValue = 0; 17611let addrMode = Absolute; 17612let accessSize = HalfWordAccess; 17613let mayLoad = 1; 17614let isExtended = 1; 17615let CextOpcode = "L2_loadrh"; 17616let BaseOpcode = "L4_loadrh_abs"; 17617let isPredicable = 1; 17618let DecoderNamespace = "MustExtend"; 17619let isExtended = 1; 17620let opExtendable = 1; 17621let isExtentSigned = 0; 17622let opExtentBits = 17; 17623let opExtentAlign = 1; 17624} 17625def PS_loadriabs : HInst< 17626(outs IntRegs:$Rd32), 17627(ins u30_2Imm:$Ii), 17628"$Rd32 = memw(#$Ii)", 17629tc_c4db48cb, TypeV2LDST>, Enc_4f4ed7, AddrModeRel { 17630let Inst{24-21} = 0b1100; 17631let Inst{31-27} = 0b01001; 17632let hasNewValue = 1; 17633let opNewValue = 0; 17634let addrMode = Absolute; 17635let accessSize = WordAccess; 17636let mayLoad = 1; 17637let isExtended = 1; 17638let CextOpcode = "L2_loadri"; 17639let BaseOpcode = "L4_loadri_abs"; 17640let isPredicable = 1; 17641let DecoderNamespace = "MustExtend"; 17642let isExtended = 1; 17643let opExtendable = 1; 17644let isExtentSigned = 0; 17645let opExtentBits = 18; 17646let opExtentAlign = 2; 17647} 17648def PS_loadrubabs : HInst< 17649(outs IntRegs:$Rd32), 17650(ins u32_0Imm:$Ii), 17651"$Rd32 = memub(#$Ii)", 17652tc_c4db48cb, TypeV2LDST>, Enc_25bef0, AddrModeRel { 17653let Inst{24-21} = 0b1001; 17654let Inst{31-27} = 0b01001; 17655let hasNewValue = 1; 17656let opNewValue = 0; 17657let addrMode = Absolute; 17658let accessSize = ByteAccess; 17659let mayLoad = 1; 17660let isExtended = 1; 17661let CextOpcode = "L2_loadrub"; 17662let BaseOpcode = "L4_loadrub_abs"; 17663let isPredicable = 1; 17664let DecoderNamespace = "MustExtend"; 17665let isExtended = 1; 17666let opExtendable = 1; 17667let isExtentSigned = 0; 17668let opExtentBits = 16; 17669let opExtentAlign = 0; 17670} 17671def PS_loadruhabs : HInst< 17672(outs IntRegs:$Rd32), 17673(ins u31_1Imm:$Ii), 17674"$Rd32 = memuh(#$Ii)", 17675tc_c4db48cb, TypeV2LDST>, Enc_8df4be, AddrModeRel { 17676let Inst{24-21} = 0b1011; 17677let Inst{31-27} = 0b01001; 17678let hasNewValue = 1; 17679let opNewValue = 0; 17680let addrMode = Absolute; 17681let accessSize = HalfWordAccess; 17682let mayLoad = 1; 17683let isExtended = 1; 17684let CextOpcode = "L2_loadruh"; 17685let BaseOpcode = "L4_loadruh_abs"; 17686let isPredicable = 1; 17687let DecoderNamespace = "MustExtend"; 17688let isExtended = 1; 17689let opExtendable = 1; 17690let isExtentSigned = 0; 17691let opExtentBits = 17; 17692let opExtentAlign = 1; 17693} 17694def PS_storerbabs : HInst< 17695(outs), 17696(ins u32_0Imm:$Ii, IntRegs:$Rt32), 17697"memb(#$Ii) = $Rt32", 17698tc_0371abea, TypeV2LDST>, Enc_1b64fb, AddrModeRel { 17699let Inst{24-21} = 0b0000; 17700let Inst{31-27} = 0b01001; 17701let addrMode = Absolute; 17702let accessSize = ByteAccess; 17703let isExtended = 1; 17704let mayStore = 1; 17705let CextOpcode = "S2_storerb"; 17706let BaseOpcode = "S2_storerbabs"; 17707let isPredicable = 1; 17708let isNVStorable = 1; 17709let DecoderNamespace = "MustExtend"; 17710let isExtended = 1; 17711let opExtendable = 0; 17712let isExtentSigned = 0; 17713let opExtentBits = 16; 17714let opExtentAlign = 0; 17715} 17716def PS_storerbnewabs : HInst< 17717(outs), 17718(ins u32_0Imm:$Ii, IntRegs:$Nt8), 17719"memb(#$Ii) = $Nt8.new", 17720tc_5bf126a6, TypeV2LDST>, Enc_ad1831, AddrModeRel { 17721let Inst{12-11} = 0b00; 17722let Inst{24-21} = 0b0101; 17723let Inst{31-27} = 0b01001; 17724let addrMode = Absolute; 17725let accessSize = ByteAccess; 17726let isNVStore = 1; 17727let isNewValue = 1; 17728let isExtended = 1; 17729let isRestrictNoSlot1Store = 1; 17730let mayStore = 1; 17731let CextOpcode = "S2_storerb"; 17732let BaseOpcode = "S2_storerbabs"; 17733let isPredicable = 1; 17734let DecoderNamespace = "MustExtend"; 17735let isExtended = 1; 17736let opExtendable = 0; 17737let isExtentSigned = 0; 17738let opExtentBits = 16; 17739let opExtentAlign = 0; 17740let opNewValue = 1; 17741} 17742def PS_storerdabs : HInst< 17743(outs), 17744(ins u29_3Imm:$Ii, DoubleRegs:$Rtt32), 17745"memd(#$Ii) = $Rtt32", 17746tc_0371abea, TypeV2LDST>, Enc_5c124a, AddrModeRel { 17747let Inst{24-21} = 0b0110; 17748let Inst{31-27} = 0b01001; 17749let addrMode = Absolute; 17750let accessSize = DoubleWordAccess; 17751let isExtended = 1; 17752let mayStore = 1; 17753let CextOpcode = "S2_storerd"; 17754let BaseOpcode = "S2_storerdabs"; 17755let isPredicable = 1; 17756let DecoderNamespace = "MustExtend"; 17757let isExtended = 1; 17758let opExtendable = 0; 17759let isExtentSigned = 0; 17760let opExtentBits = 19; 17761let opExtentAlign = 3; 17762} 17763def PS_storerfabs : HInst< 17764(outs), 17765(ins u31_1Imm:$Ii, IntRegs:$Rt32), 17766"memh(#$Ii) = $Rt32.h", 17767tc_0371abea, TypeV2LDST>, Enc_fda92c, AddrModeRel { 17768let Inst{24-21} = 0b0011; 17769let Inst{31-27} = 0b01001; 17770let addrMode = Absolute; 17771let accessSize = HalfWordAccess; 17772let isExtended = 1; 17773let mayStore = 1; 17774let CextOpcode = "S2_storerf"; 17775let BaseOpcode = "S2_storerfabs"; 17776let isPredicable = 1; 17777let DecoderNamespace = "MustExtend"; 17778let isExtended = 1; 17779let opExtendable = 0; 17780let isExtentSigned = 0; 17781let opExtentBits = 17; 17782let opExtentAlign = 1; 17783} 17784def PS_storerhabs : HInst< 17785(outs), 17786(ins u31_1Imm:$Ii, IntRegs:$Rt32), 17787"memh(#$Ii) = $Rt32", 17788tc_0371abea, TypeV2LDST>, Enc_fda92c, AddrModeRel { 17789let Inst{24-21} = 0b0010; 17790let Inst{31-27} = 0b01001; 17791let addrMode = Absolute; 17792let accessSize = HalfWordAccess; 17793let isExtended = 1; 17794let mayStore = 1; 17795let CextOpcode = "S2_storerh"; 17796let BaseOpcode = "S2_storerhabs"; 17797let isPredicable = 1; 17798let isNVStorable = 1; 17799let DecoderNamespace = "MustExtend"; 17800let isExtended = 1; 17801let opExtendable = 0; 17802let isExtentSigned = 0; 17803let opExtentBits = 17; 17804let opExtentAlign = 1; 17805} 17806def PS_storerhnewabs : HInst< 17807(outs), 17808(ins u31_1Imm:$Ii, IntRegs:$Nt8), 17809"memh(#$Ii) = $Nt8.new", 17810tc_5bf126a6, TypeV2LDST>, Enc_bc03e5, AddrModeRel { 17811let Inst{12-11} = 0b01; 17812let Inst{24-21} = 0b0101; 17813let Inst{31-27} = 0b01001; 17814let addrMode = Absolute; 17815let accessSize = HalfWordAccess; 17816let isNVStore = 1; 17817let isNewValue = 1; 17818let isExtended = 1; 17819let isRestrictNoSlot1Store = 1; 17820let mayStore = 1; 17821let CextOpcode = "S2_storerh"; 17822let BaseOpcode = "S2_storerhabs"; 17823let isPredicable = 1; 17824let DecoderNamespace = "MustExtend"; 17825let isExtended = 1; 17826let opExtendable = 0; 17827let isExtentSigned = 0; 17828let opExtentBits = 17; 17829let opExtentAlign = 1; 17830let opNewValue = 1; 17831} 17832def PS_storeriabs : HInst< 17833(outs), 17834(ins u30_2Imm:$Ii, IntRegs:$Rt32), 17835"memw(#$Ii) = $Rt32", 17836tc_0371abea, TypeV2LDST>, Enc_541f26, AddrModeRel { 17837let Inst{24-21} = 0b0100; 17838let Inst{31-27} = 0b01001; 17839let addrMode = Absolute; 17840let accessSize = WordAccess; 17841let isExtended = 1; 17842let mayStore = 1; 17843let CextOpcode = "S2_storeri"; 17844let BaseOpcode = "S2_storeriabs"; 17845let isPredicable = 1; 17846let isNVStorable = 1; 17847let DecoderNamespace = "MustExtend"; 17848let isExtended = 1; 17849let opExtendable = 0; 17850let isExtentSigned = 0; 17851let opExtentBits = 18; 17852let opExtentAlign = 2; 17853} 17854def PS_storerinewabs : HInst< 17855(outs), 17856(ins u30_2Imm:$Ii, IntRegs:$Nt8), 17857"memw(#$Ii) = $Nt8.new", 17858tc_5bf126a6, TypeV2LDST>, Enc_78cbf0, AddrModeRel { 17859let Inst{12-11} = 0b10; 17860let Inst{24-21} = 0b0101; 17861let Inst{31-27} = 0b01001; 17862let addrMode = Absolute; 17863let accessSize = WordAccess; 17864let isNVStore = 1; 17865let isNewValue = 1; 17866let isExtended = 1; 17867let isRestrictNoSlot1Store = 1; 17868let mayStore = 1; 17869let CextOpcode = "S2_storeri"; 17870let BaseOpcode = "S2_storeriabs"; 17871let isPredicable = 1; 17872let DecoderNamespace = "MustExtend"; 17873let isExtended = 1; 17874let opExtendable = 0; 17875let isExtentSigned = 0; 17876let opExtentBits = 18; 17877let opExtentAlign = 2; 17878let opNewValue = 1; 17879} 17880def S2_addasl_rrri : HInst< 17881(outs IntRegs:$Rd32), 17882(ins IntRegs:$Rt32, IntRegs:$Rs32, u3_0Imm:$Ii), 17883"$Rd32 = addasl($Rt32,$Rs32,#$Ii)", 17884tc_f675fee8, TypeS_3op>, Enc_47ef61 { 17885let Inst{13-13} = 0b0; 17886let Inst{31-21} = 0b11000100000; 17887let hasNewValue = 1; 17888let opNewValue = 0; 17889let prefersSlot3 = 1; 17890} 17891def S2_allocframe : HInst< 17892(outs IntRegs:$Rx32), 17893(ins IntRegs:$Rx32in, u11_3Imm:$Ii), 17894"allocframe($Rx32,#$Ii):raw", 17895tc_b44ecf75, TypeST>, Enc_22c845 { 17896let Inst{13-11} = 0b000; 17897let Inst{31-21} = 0b10100000100; 17898let hasNewValue = 1; 17899let opNewValue = 0; 17900let addrMode = BaseImmOffset; 17901let accessSize = DoubleWordAccess; 17902let mayStore = 1; 17903let Uses = [FRAMEKEY, FRAMELIMIT, R30, R31]; 17904let Defs = [R30]; 17905let Constraints = "$Rx32 = $Rx32in"; 17906} 17907def S2_asl_i_p : HInst< 17908(outs DoubleRegs:$Rdd32), 17909(ins DoubleRegs:$Rss32, u6_0Imm:$Ii), 17910"$Rdd32 = asl($Rss32,#$Ii)", 17911tc_946df596, TypeS_2op>, Enc_5eac98 { 17912let Inst{7-5} = 0b010; 17913let Inst{31-21} = 0b10000000000; 17914} 17915def S2_asl_i_p_acc : HInst< 17916(outs DoubleRegs:$Rxx32), 17917(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii), 17918"$Rxx32 += asl($Rss32,#$Ii)", 17919tc_f675fee8, TypeS_2op>, Enc_70fb07 { 17920let Inst{7-5} = 0b110; 17921let Inst{31-21} = 0b10000010000; 17922let prefersSlot3 = 1; 17923let Constraints = "$Rxx32 = $Rxx32in"; 17924} 17925def S2_asl_i_p_and : HInst< 17926(outs DoubleRegs:$Rxx32), 17927(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii), 17928"$Rxx32 &= asl($Rss32,#$Ii)", 17929tc_f429765c, TypeS_2op>, Enc_70fb07 { 17930let Inst{7-5} = 0b010; 17931let Inst{31-21} = 0b10000010010; 17932let prefersSlot3 = 1; 17933let Constraints = "$Rxx32 = $Rxx32in"; 17934} 17935def S2_asl_i_p_nac : HInst< 17936(outs DoubleRegs:$Rxx32), 17937(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii), 17938"$Rxx32 -= asl($Rss32,#$Ii)", 17939tc_f675fee8, TypeS_2op>, Enc_70fb07 { 17940let Inst{7-5} = 0b010; 17941let Inst{31-21} = 0b10000010000; 17942let prefersSlot3 = 1; 17943let Constraints = "$Rxx32 = $Rxx32in"; 17944} 17945def S2_asl_i_p_or : HInst< 17946(outs DoubleRegs:$Rxx32), 17947(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii), 17948"$Rxx32 |= asl($Rss32,#$Ii)", 17949tc_f429765c, TypeS_2op>, Enc_70fb07 { 17950let Inst{7-5} = 0b110; 17951let Inst{31-21} = 0b10000010010; 17952let prefersSlot3 = 1; 17953let Constraints = "$Rxx32 = $Rxx32in"; 17954} 17955def S2_asl_i_p_xacc : HInst< 17956(outs DoubleRegs:$Rxx32), 17957(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii), 17958"$Rxx32 ^= asl($Rss32,#$Ii)", 17959tc_f429765c, TypeS_2op>, Enc_70fb07 { 17960let Inst{7-5} = 0b010; 17961let Inst{31-21} = 0b10000010100; 17962let prefersSlot3 = 1; 17963let Constraints = "$Rxx32 = $Rxx32in"; 17964} 17965def S2_asl_i_r : HInst< 17966(outs IntRegs:$Rd32), 17967(ins IntRegs:$Rs32, u5_0Imm:$Ii), 17968"$Rd32 = asl($Rs32,#$Ii)", 17969tc_946df596, TypeS_2op>, Enc_a05677 { 17970let Inst{7-5} = 0b010; 17971let Inst{13-13} = 0b0; 17972let Inst{31-21} = 0b10001100000; 17973let hasNewValue = 1; 17974let opNewValue = 0; 17975} 17976def S2_asl_i_r_acc : HInst< 17977(outs IntRegs:$Rx32), 17978(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii), 17979"$Rx32 += asl($Rs32,#$Ii)", 17980tc_f675fee8, TypeS_2op>, Enc_28a2dc { 17981let Inst{7-5} = 0b110; 17982let Inst{13-13} = 0b0; 17983let Inst{31-21} = 0b10001110000; 17984let hasNewValue = 1; 17985let opNewValue = 0; 17986let prefersSlot3 = 1; 17987let Constraints = "$Rx32 = $Rx32in"; 17988} 17989def S2_asl_i_r_and : HInst< 17990(outs IntRegs:$Rx32), 17991(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii), 17992"$Rx32 &= asl($Rs32,#$Ii)", 17993tc_f429765c, TypeS_2op>, Enc_28a2dc { 17994let Inst{7-5} = 0b010; 17995let Inst{13-13} = 0b0; 17996let Inst{31-21} = 0b10001110010; 17997let hasNewValue = 1; 17998let opNewValue = 0; 17999let prefersSlot3 = 1; 18000let Constraints = "$Rx32 = $Rx32in"; 18001} 18002def S2_asl_i_r_nac : HInst< 18003(outs IntRegs:$Rx32), 18004(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii), 18005"$Rx32 -= asl($Rs32,#$Ii)", 18006tc_f675fee8, TypeS_2op>, Enc_28a2dc { 18007let Inst{7-5} = 0b010; 18008let Inst{13-13} = 0b0; 18009let Inst{31-21} = 0b10001110000; 18010let hasNewValue = 1; 18011let opNewValue = 0; 18012let prefersSlot3 = 1; 18013let Constraints = "$Rx32 = $Rx32in"; 18014} 18015def S2_asl_i_r_or : HInst< 18016(outs IntRegs:$Rx32), 18017(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii), 18018"$Rx32 |= asl($Rs32,#$Ii)", 18019tc_f429765c, TypeS_2op>, Enc_28a2dc { 18020let Inst{7-5} = 0b110; 18021let Inst{13-13} = 0b0; 18022let Inst{31-21} = 0b10001110010; 18023let hasNewValue = 1; 18024let opNewValue = 0; 18025let prefersSlot3 = 1; 18026let Constraints = "$Rx32 = $Rx32in"; 18027} 18028def S2_asl_i_r_sat : HInst< 18029(outs IntRegs:$Rd32), 18030(ins IntRegs:$Rs32, u5_0Imm:$Ii), 18031"$Rd32 = asl($Rs32,#$Ii):sat", 18032tc_779080bf, TypeS_2op>, Enc_a05677 { 18033let Inst{7-5} = 0b010; 18034let Inst{13-13} = 0b0; 18035let Inst{31-21} = 0b10001100010; 18036let hasNewValue = 1; 18037let opNewValue = 0; 18038let prefersSlot3 = 1; 18039let Defs = [USR_OVF]; 18040} 18041def S2_asl_i_r_xacc : HInst< 18042(outs IntRegs:$Rx32), 18043(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii), 18044"$Rx32 ^= asl($Rs32,#$Ii)", 18045tc_f429765c, TypeS_2op>, Enc_28a2dc { 18046let Inst{7-5} = 0b010; 18047let Inst{13-13} = 0b0; 18048let Inst{31-21} = 0b10001110100; 18049let hasNewValue = 1; 18050let opNewValue = 0; 18051let prefersSlot3 = 1; 18052let Constraints = "$Rx32 = $Rx32in"; 18053} 18054def S2_asl_i_vh : HInst< 18055(outs DoubleRegs:$Rdd32), 18056(ins DoubleRegs:$Rss32, u4_0Imm:$Ii), 18057"$Rdd32 = vaslh($Rss32,#$Ii)", 18058tc_946df596, TypeS_2op>, Enc_12b6e9 { 18059let Inst{7-5} = 0b010; 18060let Inst{13-12} = 0b00; 18061let Inst{31-21} = 0b10000000100; 18062} 18063def S2_asl_i_vw : HInst< 18064(outs DoubleRegs:$Rdd32), 18065(ins DoubleRegs:$Rss32, u5_0Imm:$Ii), 18066"$Rdd32 = vaslw($Rss32,#$Ii)", 18067tc_946df596, TypeS_2op>, Enc_7e5a82 { 18068let Inst{7-5} = 0b010; 18069let Inst{13-13} = 0b0; 18070let Inst{31-21} = 0b10000000010; 18071} 18072def S2_asl_r_p : HInst< 18073(outs DoubleRegs:$Rdd32), 18074(ins DoubleRegs:$Rss32, IntRegs:$Rt32), 18075"$Rdd32 = asl($Rss32,$Rt32)", 18076tc_946df596, TypeS_3op>, Enc_927852 { 18077let Inst{7-5} = 0b100; 18078let Inst{13-13} = 0b0; 18079let Inst{31-21} = 0b11000011100; 18080} 18081def S2_asl_r_p_acc : HInst< 18082(outs DoubleRegs:$Rxx32), 18083(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32), 18084"$Rxx32 += asl($Rss32,$Rt32)", 18085tc_f675fee8, TypeS_3op>, Enc_1aa186 { 18086let Inst{7-5} = 0b100; 18087let Inst{13-13} = 0b0; 18088let Inst{31-21} = 0b11001011110; 18089let prefersSlot3 = 1; 18090let Constraints = "$Rxx32 = $Rxx32in"; 18091} 18092def S2_asl_r_p_and : HInst< 18093(outs DoubleRegs:$Rxx32), 18094(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32), 18095"$Rxx32 &= asl($Rss32,$Rt32)", 18096tc_f429765c, TypeS_3op>, Enc_1aa186 { 18097let Inst{7-5} = 0b100; 18098let Inst{13-13} = 0b0; 18099let Inst{31-21} = 0b11001011010; 18100let prefersSlot3 = 1; 18101let Constraints = "$Rxx32 = $Rxx32in"; 18102} 18103def S2_asl_r_p_nac : HInst< 18104(outs DoubleRegs:$Rxx32), 18105(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32), 18106"$Rxx32 -= asl($Rss32,$Rt32)", 18107tc_f675fee8, TypeS_3op>, Enc_1aa186 { 18108let Inst{7-5} = 0b100; 18109let Inst{13-13} = 0b0; 18110let Inst{31-21} = 0b11001011100; 18111let prefersSlot3 = 1; 18112let Constraints = "$Rxx32 = $Rxx32in"; 18113} 18114def S2_asl_r_p_or : HInst< 18115(outs DoubleRegs:$Rxx32), 18116(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32), 18117"$Rxx32 |= asl($Rss32,$Rt32)", 18118tc_f429765c, TypeS_3op>, Enc_1aa186 { 18119let Inst{7-5} = 0b100; 18120let Inst{13-13} = 0b0; 18121let Inst{31-21} = 0b11001011000; 18122let prefersSlot3 = 1; 18123let Constraints = "$Rxx32 = $Rxx32in"; 18124} 18125def S2_asl_r_p_xor : HInst< 18126(outs DoubleRegs:$Rxx32), 18127(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32), 18128"$Rxx32 ^= asl($Rss32,$Rt32)", 18129tc_f429765c, TypeS_3op>, Enc_1aa186 { 18130let Inst{7-5} = 0b100; 18131let Inst{13-13} = 0b0; 18132let Inst{31-21} = 0b11001011011; 18133let prefersSlot3 = 1; 18134let Constraints = "$Rxx32 = $Rxx32in"; 18135} 18136def S2_asl_r_r : HInst< 18137(outs IntRegs:$Rd32), 18138(ins IntRegs:$Rs32, IntRegs:$Rt32), 18139"$Rd32 = asl($Rs32,$Rt32)", 18140tc_946df596, TypeS_3op>, Enc_5ab2be { 18141let Inst{7-5} = 0b100; 18142let Inst{13-13} = 0b0; 18143let Inst{31-21} = 0b11000110010; 18144let hasNewValue = 1; 18145let opNewValue = 0; 18146} 18147def S2_asl_r_r_acc : HInst< 18148(outs IntRegs:$Rx32), 18149(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), 18150"$Rx32 += asl($Rs32,$Rt32)", 18151tc_f675fee8, TypeS_3op>, Enc_2ae154 { 18152let Inst{7-5} = 0b100; 18153let Inst{13-13} = 0b0; 18154let Inst{31-21} = 0b11001100110; 18155let hasNewValue = 1; 18156let opNewValue = 0; 18157let prefersSlot3 = 1; 18158let Constraints = "$Rx32 = $Rx32in"; 18159} 18160def S2_asl_r_r_and : HInst< 18161(outs IntRegs:$Rx32), 18162(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), 18163"$Rx32 &= asl($Rs32,$Rt32)", 18164tc_f429765c, TypeS_3op>, Enc_2ae154 { 18165let Inst{7-5} = 0b100; 18166let Inst{13-13} = 0b0; 18167let Inst{31-21} = 0b11001100010; 18168let hasNewValue = 1; 18169let opNewValue = 0; 18170let prefersSlot3 = 1; 18171let Constraints = "$Rx32 = $Rx32in"; 18172} 18173def S2_asl_r_r_nac : HInst< 18174(outs IntRegs:$Rx32), 18175(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), 18176"$Rx32 -= asl($Rs32,$Rt32)", 18177tc_f675fee8, TypeS_3op>, Enc_2ae154 { 18178let Inst{7-5} = 0b100; 18179let Inst{13-13} = 0b0; 18180let Inst{31-21} = 0b11001100100; 18181let hasNewValue = 1; 18182let opNewValue = 0; 18183let prefersSlot3 = 1; 18184let Constraints = "$Rx32 = $Rx32in"; 18185} 18186def S2_asl_r_r_or : HInst< 18187(outs IntRegs:$Rx32), 18188(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), 18189"$Rx32 |= asl($Rs32,$Rt32)", 18190tc_f429765c, TypeS_3op>, Enc_2ae154 { 18191let Inst{7-5} = 0b100; 18192let Inst{13-13} = 0b0; 18193let Inst{31-21} = 0b11001100000; 18194let hasNewValue = 1; 18195let opNewValue = 0; 18196let prefersSlot3 = 1; 18197let Constraints = "$Rx32 = $Rx32in"; 18198} 18199def S2_asl_r_r_sat : HInst< 18200(outs IntRegs:$Rd32), 18201(ins IntRegs:$Rs32, IntRegs:$Rt32), 18202"$Rd32 = asl($Rs32,$Rt32):sat", 18203tc_779080bf, TypeS_3op>, Enc_5ab2be { 18204let Inst{7-5} = 0b100; 18205let Inst{13-13} = 0b0; 18206let Inst{31-21} = 0b11000110000; 18207let hasNewValue = 1; 18208let opNewValue = 0; 18209let prefersSlot3 = 1; 18210let Defs = [USR_OVF]; 18211} 18212def S2_asl_r_vh : HInst< 18213(outs DoubleRegs:$Rdd32), 18214(ins DoubleRegs:$Rss32, IntRegs:$Rt32), 18215"$Rdd32 = vaslh($Rss32,$Rt32)", 18216tc_946df596, TypeS_3op>, Enc_927852 { 18217let Inst{7-5} = 0b100; 18218let Inst{13-13} = 0b0; 18219let Inst{31-21} = 0b11000011010; 18220} 18221def S2_asl_r_vw : HInst< 18222(outs DoubleRegs:$Rdd32), 18223(ins DoubleRegs:$Rss32, IntRegs:$Rt32), 18224"$Rdd32 = vaslw($Rss32,$Rt32)", 18225tc_946df596, TypeS_3op>, Enc_927852 { 18226let Inst{7-5} = 0b100; 18227let Inst{13-13} = 0b0; 18228let Inst{31-21} = 0b11000011000; 18229} 18230def S2_asr_i_p : HInst< 18231(outs DoubleRegs:$Rdd32), 18232(ins DoubleRegs:$Rss32, u6_0Imm:$Ii), 18233"$Rdd32 = asr($Rss32,#$Ii)", 18234tc_946df596, TypeS_2op>, Enc_5eac98 { 18235let Inst{7-5} = 0b000; 18236let Inst{31-21} = 0b10000000000; 18237} 18238def S2_asr_i_p_acc : HInst< 18239(outs DoubleRegs:$Rxx32), 18240(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii), 18241"$Rxx32 += asr($Rss32,#$Ii)", 18242tc_f675fee8, TypeS_2op>, Enc_70fb07 { 18243let Inst{7-5} = 0b100; 18244let Inst{31-21} = 0b10000010000; 18245let prefersSlot3 = 1; 18246let Constraints = "$Rxx32 = $Rxx32in"; 18247} 18248def S2_asr_i_p_and : HInst< 18249(outs DoubleRegs:$Rxx32), 18250(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii), 18251"$Rxx32 &= asr($Rss32,#$Ii)", 18252tc_f429765c, TypeS_2op>, Enc_70fb07 { 18253let Inst{7-5} = 0b000; 18254let Inst{31-21} = 0b10000010010; 18255let prefersSlot3 = 1; 18256let Constraints = "$Rxx32 = $Rxx32in"; 18257} 18258def S2_asr_i_p_nac : HInst< 18259(outs DoubleRegs:$Rxx32), 18260(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii), 18261"$Rxx32 -= asr($Rss32,#$Ii)", 18262tc_f675fee8, TypeS_2op>, Enc_70fb07 { 18263let Inst{7-5} = 0b000; 18264let Inst{31-21} = 0b10000010000; 18265let prefersSlot3 = 1; 18266let Constraints = "$Rxx32 = $Rxx32in"; 18267} 18268def S2_asr_i_p_or : HInst< 18269(outs DoubleRegs:$Rxx32), 18270(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii), 18271"$Rxx32 |= asr($Rss32,#$Ii)", 18272tc_f429765c, TypeS_2op>, Enc_70fb07 { 18273let Inst{7-5} = 0b100; 18274let Inst{31-21} = 0b10000010010; 18275let prefersSlot3 = 1; 18276let Constraints = "$Rxx32 = $Rxx32in"; 18277} 18278def S2_asr_i_p_rnd : HInst< 18279(outs DoubleRegs:$Rdd32), 18280(ins DoubleRegs:$Rss32, u6_0Imm:$Ii), 18281"$Rdd32 = asr($Rss32,#$Ii):rnd", 18282tc_002cb246, TypeS_2op>, Enc_5eac98 { 18283let Inst{7-5} = 0b111; 18284let Inst{31-21} = 0b10000000110; 18285let prefersSlot3 = 1; 18286} 18287def S2_asr_i_p_rnd_goodsyntax : HInst< 18288(outs DoubleRegs:$Rdd32), 18289(ins DoubleRegs:$Rss32, u6_0Imm:$Ii), 18290"$Rdd32 = asrrnd($Rss32,#$Ii)", 18291tc_002cb246, TypeS_2op> { 18292let isPseudo = 1; 18293} 18294def S2_asr_i_r : HInst< 18295(outs IntRegs:$Rd32), 18296(ins IntRegs:$Rs32, u5_0Imm:$Ii), 18297"$Rd32 = asr($Rs32,#$Ii)", 18298tc_946df596, TypeS_2op>, Enc_a05677 { 18299let Inst{7-5} = 0b000; 18300let Inst{13-13} = 0b0; 18301let Inst{31-21} = 0b10001100000; 18302let hasNewValue = 1; 18303let opNewValue = 0; 18304} 18305def S2_asr_i_r_acc : HInst< 18306(outs IntRegs:$Rx32), 18307(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii), 18308"$Rx32 += asr($Rs32,#$Ii)", 18309tc_f675fee8, TypeS_2op>, Enc_28a2dc { 18310let Inst{7-5} = 0b100; 18311let Inst{13-13} = 0b0; 18312let Inst{31-21} = 0b10001110000; 18313let hasNewValue = 1; 18314let opNewValue = 0; 18315let prefersSlot3 = 1; 18316let Constraints = "$Rx32 = $Rx32in"; 18317} 18318def S2_asr_i_r_and : HInst< 18319(outs IntRegs:$Rx32), 18320(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii), 18321"$Rx32 &= asr($Rs32,#$Ii)", 18322tc_f429765c, TypeS_2op>, Enc_28a2dc { 18323let Inst{7-5} = 0b000; 18324let Inst{13-13} = 0b0; 18325let Inst{31-21} = 0b10001110010; 18326let hasNewValue = 1; 18327let opNewValue = 0; 18328let prefersSlot3 = 1; 18329let Constraints = "$Rx32 = $Rx32in"; 18330} 18331def S2_asr_i_r_nac : HInst< 18332(outs IntRegs:$Rx32), 18333(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii), 18334"$Rx32 -= asr($Rs32,#$Ii)", 18335tc_f675fee8, TypeS_2op>, Enc_28a2dc { 18336let Inst{7-5} = 0b000; 18337let Inst{13-13} = 0b0; 18338let Inst{31-21} = 0b10001110000; 18339let hasNewValue = 1; 18340let opNewValue = 0; 18341let prefersSlot3 = 1; 18342let Constraints = "$Rx32 = $Rx32in"; 18343} 18344def S2_asr_i_r_or : HInst< 18345(outs IntRegs:$Rx32), 18346(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii), 18347"$Rx32 |= asr($Rs32,#$Ii)", 18348tc_f429765c, TypeS_2op>, Enc_28a2dc { 18349let Inst{7-5} = 0b100; 18350let Inst{13-13} = 0b0; 18351let Inst{31-21} = 0b10001110010; 18352let hasNewValue = 1; 18353let opNewValue = 0; 18354let prefersSlot3 = 1; 18355let Constraints = "$Rx32 = $Rx32in"; 18356} 18357def S2_asr_i_r_rnd : HInst< 18358(outs IntRegs:$Rd32), 18359(ins IntRegs:$Rs32, u5_0Imm:$Ii), 18360"$Rd32 = asr($Rs32,#$Ii):rnd", 18361tc_002cb246, TypeS_2op>, Enc_a05677 { 18362let Inst{7-5} = 0b000; 18363let Inst{13-13} = 0b0; 18364let Inst{31-21} = 0b10001100010; 18365let hasNewValue = 1; 18366let opNewValue = 0; 18367let prefersSlot3 = 1; 18368} 18369def S2_asr_i_r_rnd_goodsyntax : HInst< 18370(outs IntRegs:$Rd32), 18371(ins IntRegs:$Rs32, u5_0Imm:$Ii), 18372"$Rd32 = asrrnd($Rs32,#$Ii)", 18373tc_002cb246, TypeS_2op> { 18374let hasNewValue = 1; 18375let opNewValue = 0; 18376let isPseudo = 1; 18377} 18378def S2_asr_i_svw_trun : HInst< 18379(outs IntRegs:$Rd32), 18380(ins DoubleRegs:$Rss32, u5_0Imm:$Ii), 18381"$Rd32 = vasrw($Rss32,#$Ii)", 18382tc_4414d8b1, TypeS_2op>, Enc_8dec2e { 18383let Inst{7-5} = 0b010; 18384let Inst{13-13} = 0b0; 18385let Inst{31-21} = 0b10001000110; 18386let hasNewValue = 1; 18387let opNewValue = 0; 18388let prefersSlot3 = 1; 18389} 18390def S2_asr_i_vh : HInst< 18391(outs DoubleRegs:$Rdd32), 18392(ins DoubleRegs:$Rss32, u4_0Imm:$Ii), 18393"$Rdd32 = vasrh($Rss32,#$Ii)", 18394tc_946df596, TypeS_2op>, Enc_12b6e9 { 18395let Inst{7-5} = 0b000; 18396let Inst{13-12} = 0b00; 18397let Inst{31-21} = 0b10000000100; 18398} 18399def S2_asr_i_vw : HInst< 18400(outs DoubleRegs:$Rdd32), 18401(ins DoubleRegs:$Rss32, u5_0Imm:$Ii), 18402"$Rdd32 = vasrw($Rss32,#$Ii)", 18403tc_946df596, TypeS_2op>, Enc_7e5a82 { 18404let Inst{7-5} = 0b000; 18405let Inst{13-13} = 0b0; 18406let Inst{31-21} = 0b10000000010; 18407} 18408def S2_asr_r_p : HInst< 18409(outs DoubleRegs:$Rdd32), 18410(ins DoubleRegs:$Rss32, IntRegs:$Rt32), 18411"$Rdd32 = asr($Rss32,$Rt32)", 18412tc_946df596, TypeS_3op>, Enc_927852 { 18413let Inst{7-5} = 0b000; 18414let Inst{13-13} = 0b0; 18415let Inst{31-21} = 0b11000011100; 18416} 18417def S2_asr_r_p_acc : HInst< 18418(outs DoubleRegs:$Rxx32), 18419(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32), 18420"$Rxx32 += asr($Rss32,$Rt32)", 18421tc_f675fee8, TypeS_3op>, Enc_1aa186 { 18422let Inst{7-5} = 0b000; 18423let Inst{13-13} = 0b0; 18424let Inst{31-21} = 0b11001011110; 18425let prefersSlot3 = 1; 18426let Constraints = "$Rxx32 = $Rxx32in"; 18427} 18428def S2_asr_r_p_and : HInst< 18429(outs DoubleRegs:$Rxx32), 18430(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32), 18431"$Rxx32 &= asr($Rss32,$Rt32)", 18432tc_f429765c, TypeS_3op>, Enc_1aa186 { 18433let Inst{7-5} = 0b000; 18434let Inst{13-13} = 0b0; 18435let Inst{31-21} = 0b11001011010; 18436let prefersSlot3 = 1; 18437let Constraints = "$Rxx32 = $Rxx32in"; 18438} 18439def S2_asr_r_p_nac : HInst< 18440(outs DoubleRegs:$Rxx32), 18441(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32), 18442"$Rxx32 -= asr($Rss32,$Rt32)", 18443tc_f675fee8, TypeS_3op>, Enc_1aa186 { 18444let Inst{7-5} = 0b000; 18445let Inst{13-13} = 0b0; 18446let Inst{31-21} = 0b11001011100; 18447let prefersSlot3 = 1; 18448let Constraints = "$Rxx32 = $Rxx32in"; 18449} 18450def S2_asr_r_p_or : HInst< 18451(outs DoubleRegs:$Rxx32), 18452(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32), 18453"$Rxx32 |= asr($Rss32,$Rt32)", 18454tc_f429765c, TypeS_3op>, Enc_1aa186 { 18455let Inst{7-5} = 0b000; 18456let Inst{13-13} = 0b0; 18457let Inst{31-21} = 0b11001011000; 18458let prefersSlot3 = 1; 18459let Constraints = "$Rxx32 = $Rxx32in"; 18460} 18461def S2_asr_r_p_xor : HInst< 18462(outs DoubleRegs:$Rxx32), 18463(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32), 18464"$Rxx32 ^= asr($Rss32,$Rt32)", 18465tc_f429765c, TypeS_3op>, Enc_1aa186 { 18466let Inst{7-5} = 0b000; 18467let Inst{13-13} = 0b0; 18468let Inst{31-21} = 0b11001011011; 18469let prefersSlot3 = 1; 18470let Constraints = "$Rxx32 = $Rxx32in"; 18471} 18472def S2_asr_r_r : HInst< 18473(outs IntRegs:$Rd32), 18474(ins IntRegs:$Rs32, IntRegs:$Rt32), 18475"$Rd32 = asr($Rs32,$Rt32)", 18476tc_946df596, TypeS_3op>, Enc_5ab2be { 18477let Inst{7-5} = 0b000; 18478let Inst{13-13} = 0b0; 18479let Inst{31-21} = 0b11000110010; 18480let hasNewValue = 1; 18481let opNewValue = 0; 18482} 18483def S2_asr_r_r_acc : HInst< 18484(outs IntRegs:$Rx32), 18485(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), 18486"$Rx32 += asr($Rs32,$Rt32)", 18487tc_f675fee8, TypeS_3op>, Enc_2ae154 { 18488let Inst{7-5} = 0b000; 18489let Inst{13-13} = 0b0; 18490let Inst{31-21} = 0b11001100110; 18491let hasNewValue = 1; 18492let opNewValue = 0; 18493let prefersSlot3 = 1; 18494let Constraints = "$Rx32 = $Rx32in"; 18495} 18496def S2_asr_r_r_and : HInst< 18497(outs IntRegs:$Rx32), 18498(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), 18499"$Rx32 &= asr($Rs32,$Rt32)", 18500tc_f429765c, TypeS_3op>, Enc_2ae154 { 18501let Inst{7-5} = 0b000; 18502let Inst{13-13} = 0b0; 18503let Inst{31-21} = 0b11001100010; 18504let hasNewValue = 1; 18505let opNewValue = 0; 18506let prefersSlot3 = 1; 18507let Constraints = "$Rx32 = $Rx32in"; 18508} 18509def S2_asr_r_r_nac : HInst< 18510(outs IntRegs:$Rx32), 18511(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), 18512"$Rx32 -= asr($Rs32,$Rt32)", 18513tc_f675fee8, TypeS_3op>, Enc_2ae154 { 18514let Inst{7-5} = 0b000; 18515let Inst{13-13} = 0b0; 18516let Inst{31-21} = 0b11001100100; 18517let hasNewValue = 1; 18518let opNewValue = 0; 18519let prefersSlot3 = 1; 18520let Constraints = "$Rx32 = $Rx32in"; 18521} 18522def S2_asr_r_r_or : HInst< 18523(outs IntRegs:$Rx32), 18524(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), 18525"$Rx32 |= asr($Rs32,$Rt32)", 18526tc_f429765c, TypeS_3op>, Enc_2ae154 { 18527let Inst{7-5} = 0b000; 18528let Inst{13-13} = 0b0; 18529let Inst{31-21} = 0b11001100000; 18530let hasNewValue = 1; 18531let opNewValue = 0; 18532let prefersSlot3 = 1; 18533let Constraints = "$Rx32 = $Rx32in"; 18534} 18535def S2_asr_r_r_sat : HInst< 18536(outs IntRegs:$Rd32), 18537(ins IntRegs:$Rs32, IntRegs:$Rt32), 18538"$Rd32 = asr($Rs32,$Rt32):sat", 18539tc_779080bf, TypeS_3op>, Enc_5ab2be { 18540let Inst{7-5} = 0b000; 18541let Inst{13-13} = 0b0; 18542let Inst{31-21} = 0b11000110000; 18543let hasNewValue = 1; 18544let opNewValue = 0; 18545let prefersSlot3 = 1; 18546let Defs = [USR_OVF]; 18547} 18548def S2_asr_r_svw_trun : HInst< 18549(outs IntRegs:$Rd32), 18550(ins DoubleRegs:$Rss32, IntRegs:$Rt32), 18551"$Rd32 = vasrw($Rss32,$Rt32)", 18552tc_4414d8b1, TypeS_3op>, Enc_3d5b28 { 18553let Inst{7-5} = 0b010; 18554let Inst{13-13} = 0b0; 18555let Inst{31-21} = 0b11000101000; 18556let hasNewValue = 1; 18557let opNewValue = 0; 18558let prefersSlot3 = 1; 18559} 18560def S2_asr_r_vh : HInst< 18561(outs DoubleRegs:$Rdd32), 18562(ins DoubleRegs:$Rss32, IntRegs:$Rt32), 18563"$Rdd32 = vasrh($Rss32,$Rt32)", 18564tc_946df596, TypeS_3op>, Enc_927852 { 18565let Inst{7-5} = 0b000; 18566let Inst{13-13} = 0b0; 18567let Inst{31-21} = 0b11000011010; 18568} 18569def S2_asr_r_vw : HInst< 18570(outs DoubleRegs:$Rdd32), 18571(ins DoubleRegs:$Rss32, IntRegs:$Rt32), 18572"$Rdd32 = vasrw($Rss32,$Rt32)", 18573tc_946df596, TypeS_3op>, Enc_927852 { 18574let Inst{7-5} = 0b000; 18575let Inst{13-13} = 0b0; 18576let Inst{31-21} = 0b11000011000; 18577} 18578def S2_brev : HInst< 18579(outs IntRegs:$Rd32), 18580(ins IntRegs:$Rs32), 18581"$Rd32 = brev($Rs32)", 18582tc_14b5c689, TypeS_2op>, Enc_5e2823 { 18583let Inst{13-5} = 0b000000110; 18584let Inst{31-21} = 0b10001100010; 18585let hasNewValue = 1; 18586let opNewValue = 0; 18587let prefersSlot3 = 1; 18588} 18589def S2_brevp : HInst< 18590(outs DoubleRegs:$Rdd32), 18591(ins DoubleRegs:$Rss32), 18592"$Rdd32 = brev($Rss32)", 18593tc_14b5c689, TypeS_2op>, Enc_b9c5fb { 18594let Inst{13-5} = 0b000000110; 18595let Inst{31-21} = 0b10000000110; 18596let prefersSlot3 = 1; 18597} 18598def S2_cabacdecbin : HInst< 18599(outs DoubleRegs:$Rdd32), 18600(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 18601"$Rdd32 = decbin($Rss32,$Rtt32)", 18602tc_76851da1, TypeS_3op>, Enc_a56825 { 18603let Inst{7-5} = 0b110; 18604let Inst{13-13} = 0b0; 18605let Inst{31-21} = 0b11000001110; 18606let isPredicateLate = 1; 18607let prefersSlot3 = 1; 18608let Defs = [P0]; 18609} 18610def S2_cl0 : HInst< 18611(outs IntRegs:$Rd32), 18612(ins IntRegs:$Rs32), 18613"$Rd32 = cl0($Rs32)", 18614tc_14b5c689, TypeS_2op>, Enc_5e2823 { 18615let Inst{13-5} = 0b000000101; 18616let Inst{31-21} = 0b10001100000; 18617let hasNewValue = 1; 18618let opNewValue = 0; 18619let prefersSlot3 = 1; 18620} 18621def S2_cl0p : HInst< 18622(outs IntRegs:$Rd32), 18623(ins DoubleRegs:$Rss32), 18624"$Rd32 = cl0($Rss32)", 18625tc_14b5c689, TypeS_2op>, Enc_90cd8b { 18626let Inst{13-5} = 0b000000010; 18627let Inst{31-21} = 0b10001000010; 18628let hasNewValue = 1; 18629let opNewValue = 0; 18630let prefersSlot3 = 1; 18631} 18632def S2_cl1 : HInst< 18633(outs IntRegs:$Rd32), 18634(ins IntRegs:$Rs32), 18635"$Rd32 = cl1($Rs32)", 18636tc_14b5c689, TypeS_2op>, Enc_5e2823 { 18637let Inst{13-5} = 0b000000110; 18638let Inst{31-21} = 0b10001100000; 18639let hasNewValue = 1; 18640let opNewValue = 0; 18641let prefersSlot3 = 1; 18642} 18643def S2_cl1p : HInst< 18644(outs IntRegs:$Rd32), 18645(ins DoubleRegs:$Rss32), 18646"$Rd32 = cl1($Rss32)", 18647tc_14b5c689, TypeS_2op>, Enc_90cd8b { 18648let Inst{13-5} = 0b000000100; 18649let Inst{31-21} = 0b10001000010; 18650let hasNewValue = 1; 18651let opNewValue = 0; 18652let prefersSlot3 = 1; 18653} 18654def S2_clb : HInst< 18655(outs IntRegs:$Rd32), 18656(ins IntRegs:$Rs32), 18657"$Rd32 = clb($Rs32)", 18658tc_14b5c689, TypeS_2op>, Enc_5e2823 { 18659let Inst{13-5} = 0b000000100; 18660let Inst{31-21} = 0b10001100000; 18661let hasNewValue = 1; 18662let opNewValue = 0; 18663let prefersSlot3 = 1; 18664} 18665def S2_clbnorm : HInst< 18666(outs IntRegs:$Rd32), 18667(ins IntRegs:$Rs32), 18668"$Rd32 = normamt($Rs32)", 18669tc_14b5c689, TypeS_2op>, Enc_5e2823 { 18670let Inst{13-5} = 0b000000111; 18671let Inst{31-21} = 0b10001100000; 18672let hasNewValue = 1; 18673let opNewValue = 0; 18674let prefersSlot3 = 1; 18675} 18676def S2_clbp : HInst< 18677(outs IntRegs:$Rd32), 18678(ins DoubleRegs:$Rss32), 18679"$Rd32 = clb($Rss32)", 18680tc_14b5c689, TypeS_2op>, Enc_90cd8b { 18681let Inst{13-5} = 0b000000000; 18682let Inst{31-21} = 0b10001000010; 18683let hasNewValue = 1; 18684let opNewValue = 0; 18685let prefersSlot3 = 1; 18686} 18687def S2_clrbit_i : HInst< 18688(outs IntRegs:$Rd32), 18689(ins IntRegs:$Rs32, u5_0Imm:$Ii), 18690"$Rd32 = clrbit($Rs32,#$Ii)", 18691tc_946df596, TypeS_2op>, Enc_a05677 { 18692let Inst{7-5} = 0b001; 18693let Inst{13-13} = 0b0; 18694let Inst{31-21} = 0b10001100110; 18695let hasNewValue = 1; 18696let opNewValue = 0; 18697} 18698def S2_clrbit_r : HInst< 18699(outs IntRegs:$Rd32), 18700(ins IntRegs:$Rs32, IntRegs:$Rt32), 18701"$Rd32 = clrbit($Rs32,$Rt32)", 18702tc_946df596, TypeS_3op>, Enc_5ab2be { 18703let Inst{7-5} = 0b010; 18704let Inst{13-13} = 0b0; 18705let Inst{31-21} = 0b11000110100; 18706let hasNewValue = 1; 18707let opNewValue = 0; 18708} 18709def S2_ct0 : HInst< 18710(outs IntRegs:$Rd32), 18711(ins IntRegs:$Rs32), 18712"$Rd32 = ct0($Rs32)", 18713tc_14b5c689, TypeS_2op>, Enc_5e2823 { 18714let Inst{13-5} = 0b000000100; 18715let Inst{31-21} = 0b10001100010; 18716let hasNewValue = 1; 18717let opNewValue = 0; 18718let prefersSlot3 = 1; 18719} 18720def S2_ct0p : HInst< 18721(outs IntRegs:$Rd32), 18722(ins DoubleRegs:$Rss32), 18723"$Rd32 = ct0($Rss32)", 18724tc_14b5c689, TypeS_2op>, Enc_90cd8b { 18725let Inst{13-5} = 0b000000010; 18726let Inst{31-21} = 0b10001000111; 18727let hasNewValue = 1; 18728let opNewValue = 0; 18729let prefersSlot3 = 1; 18730} 18731def S2_ct1 : HInst< 18732(outs IntRegs:$Rd32), 18733(ins IntRegs:$Rs32), 18734"$Rd32 = ct1($Rs32)", 18735tc_14b5c689, TypeS_2op>, Enc_5e2823 { 18736let Inst{13-5} = 0b000000101; 18737let Inst{31-21} = 0b10001100010; 18738let hasNewValue = 1; 18739let opNewValue = 0; 18740let prefersSlot3 = 1; 18741} 18742def S2_ct1p : HInst< 18743(outs IntRegs:$Rd32), 18744(ins DoubleRegs:$Rss32), 18745"$Rd32 = ct1($Rss32)", 18746tc_14b5c689, TypeS_2op>, Enc_90cd8b { 18747let Inst{13-5} = 0b000000100; 18748let Inst{31-21} = 0b10001000111; 18749let hasNewValue = 1; 18750let opNewValue = 0; 18751let prefersSlot3 = 1; 18752} 18753def S2_deinterleave : HInst< 18754(outs DoubleRegs:$Rdd32), 18755(ins DoubleRegs:$Rss32), 18756"$Rdd32 = deinterleave($Rss32)", 18757tc_14b5c689, TypeS_2op>, Enc_b9c5fb { 18758let Inst{13-5} = 0b000000100; 18759let Inst{31-21} = 0b10000000110; 18760let prefersSlot3 = 1; 18761} 18762def S2_extractu : HInst< 18763(outs IntRegs:$Rd32), 18764(ins IntRegs:$Rs32, u5_0Imm:$Ii, u5_0Imm:$II), 18765"$Rd32 = extractu($Rs32,#$Ii,#$II)", 18766tc_f675fee8, TypeS_2op>, Enc_b388cf { 18767let Inst{13-13} = 0b0; 18768let Inst{31-23} = 0b100011010; 18769let hasNewValue = 1; 18770let opNewValue = 0; 18771let prefersSlot3 = 1; 18772} 18773def S2_extractu_rp : HInst< 18774(outs IntRegs:$Rd32), 18775(ins IntRegs:$Rs32, DoubleRegs:$Rtt32), 18776"$Rd32 = extractu($Rs32,$Rtt32)", 18777tc_002cb246, TypeS_3op>, Enc_e07374 { 18778let Inst{7-5} = 0b000; 18779let Inst{13-13} = 0b0; 18780let Inst{31-21} = 0b11001001000; 18781let hasNewValue = 1; 18782let opNewValue = 0; 18783let prefersSlot3 = 1; 18784} 18785def S2_extractup : HInst< 18786(outs DoubleRegs:$Rdd32), 18787(ins DoubleRegs:$Rss32, u6_0Imm:$Ii, u6_0Imm:$II), 18788"$Rdd32 = extractu($Rss32,#$Ii,#$II)", 18789tc_f675fee8, TypeS_2op>, Enc_b84c4c { 18790let Inst{31-24} = 0b10000001; 18791let prefersSlot3 = 1; 18792} 18793def S2_extractup_rp : HInst< 18794(outs DoubleRegs:$Rdd32), 18795(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 18796"$Rdd32 = extractu($Rss32,$Rtt32)", 18797tc_002cb246, TypeS_3op>, Enc_a56825 { 18798let Inst{7-5} = 0b000; 18799let Inst{13-13} = 0b0; 18800let Inst{31-21} = 0b11000001000; 18801let prefersSlot3 = 1; 18802} 18803def S2_insert : HInst< 18804(outs IntRegs:$Rx32), 18805(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii, u5_0Imm:$II), 18806"$Rx32 = insert($Rs32,#$Ii,#$II)", 18807tc_bfec0f01, TypeS_2op>, Enc_a1e29d { 18808let Inst{13-13} = 0b0; 18809let Inst{31-23} = 0b100011110; 18810let hasNewValue = 1; 18811let opNewValue = 0; 18812let prefersSlot3 = 1; 18813let Constraints = "$Rx32 = $Rx32in"; 18814} 18815def S2_insert_rp : HInst< 18816(outs IntRegs:$Rx32), 18817(ins IntRegs:$Rx32in, IntRegs:$Rs32, DoubleRegs:$Rtt32), 18818"$Rx32 = insert($Rs32,$Rtt32)", 18819tc_f429765c, TypeS_3op>, Enc_179b35 { 18820let Inst{7-5} = 0b000; 18821let Inst{13-13} = 0b0; 18822let Inst{31-21} = 0b11001000000; 18823let hasNewValue = 1; 18824let opNewValue = 0; 18825let prefersSlot3 = 1; 18826let Constraints = "$Rx32 = $Rx32in"; 18827} 18828def S2_insertp : HInst< 18829(outs DoubleRegs:$Rxx32), 18830(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii, u6_0Imm:$II), 18831"$Rxx32 = insert($Rss32,#$Ii,#$II)", 18832tc_bfec0f01, TypeS_2op>, Enc_143a3c { 18833let Inst{31-24} = 0b10000011; 18834let prefersSlot3 = 1; 18835let Constraints = "$Rxx32 = $Rxx32in"; 18836} 18837def S2_insertp_rp : HInst< 18838(outs DoubleRegs:$Rxx32), 18839(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 18840"$Rxx32 = insert($Rss32,$Rtt32)", 18841tc_f429765c, TypeS_3op>, Enc_88c16c { 18842let Inst{7-5} = 0b000; 18843let Inst{13-13} = 0b0; 18844let Inst{31-21} = 0b11001010000; 18845let prefersSlot3 = 1; 18846let Constraints = "$Rxx32 = $Rxx32in"; 18847} 18848def S2_interleave : HInst< 18849(outs DoubleRegs:$Rdd32), 18850(ins DoubleRegs:$Rss32), 18851"$Rdd32 = interleave($Rss32)", 18852tc_14b5c689, TypeS_2op>, Enc_b9c5fb { 18853let Inst{13-5} = 0b000000101; 18854let Inst{31-21} = 0b10000000110; 18855let prefersSlot3 = 1; 18856} 18857def S2_lfsp : HInst< 18858(outs DoubleRegs:$Rdd32), 18859(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 18860"$Rdd32 = lfs($Rss32,$Rtt32)", 18861tc_002cb246, TypeS_3op>, Enc_a56825 { 18862let Inst{7-5} = 0b110; 18863let Inst{13-13} = 0b0; 18864let Inst{31-21} = 0b11000001100; 18865let prefersSlot3 = 1; 18866} 18867def S2_lsl_r_p : HInst< 18868(outs DoubleRegs:$Rdd32), 18869(ins DoubleRegs:$Rss32, IntRegs:$Rt32), 18870"$Rdd32 = lsl($Rss32,$Rt32)", 18871tc_946df596, TypeS_3op>, Enc_927852 { 18872let Inst{7-5} = 0b110; 18873let Inst{13-13} = 0b0; 18874let Inst{31-21} = 0b11000011100; 18875} 18876def S2_lsl_r_p_acc : HInst< 18877(outs DoubleRegs:$Rxx32), 18878(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32), 18879"$Rxx32 += lsl($Rss32,$Rt32)", 18880tc_f675fee8, TypeS_3op>, Enc_1aa186 { 18881let Inst{7-5} = 0b110; 18882let Inst{13-13} = 0b0; 18883let Inst{31-21} = 0b11001011110; 18884let prefersSlot3 = 1; 18885let Constraints = "$Rxx32 = $Rxx32in"; 18886} 18887def S2_lsl_r_p_and : HInst< 18888(outs DoubleRegs:$Rxx32), 18889(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32), 18890"$Rxx32 &= lsl($Rss32,$Rt32)", 18891tc_f429765c, TypeS_3op>, Enc_1aa186 { 18892let Inst{7-5} = 0b110; 18893let Inst{13-13} = 0b0; 18894let Inst{31-21} = 0b11001011010; 18895let prefersSlot3 = 1; 18896let Constraints = "$Rxx32 = $Rxx32in"; 18897} 18898def S2_lsl_r_p_nac : HInst< 18899(outs DoubleRegs:$Rxx32), 18900(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32), 18901"$Rxx32 -= lsl($Rss32,$Rt32)", 18902tc_f675fee8, TypeS_3op>, Enc_1aa186 { 18903let Inst{7-5} = 0b110; 18904let Inst{13-13} = 0b0; 18905let Inst{31-21} = 0b11001011100; 18906let prefersSlot3 = 1; 18907let Constraints = "$Rxx32 = $Rxx32in"; 18908} 18909def S2_lsl_r_p_or : HInst< 18910(outs DoubleRegs:$Rxx32), 18911(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32), 18912"$Rxx32 |= lsl($Rss32,$Rt32)", 18913tc_f429765c, TypeS_3op>, Enc_1aa186 { 18914let Inst{7-5} = 0b110; 18915let Inst{13-13} = 0b0; 18916let Inst{31-21} = 0b11001011000; 18917let prefersSlot3 = 1; 18918let Constraints = "$Rxx32 = $Rxx32in"; 18919} 18920def S2_lsl_r_p_xor : HInst< 18921(outs DoubleRegs:$Rxx32), 18922(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32), 18923"$Rxx32 ^= lsl($Rss32,$Rt32)", 18924tc_f429765c, TypeS_3op>, Enc_1aa186 { 18925let Inst{7-5} = 0b110; 18926let Inst{13-13} = 0b0; 18927let Inst{31-21} = 0b11001011011; 18928let prefersSlot3 = 1; 18929let Constraints = "$Rxx32 = $Rxx32in"; 18930} 18931def S2_lsl_r_r : HInst< 18932(outs IntRegs:$Rd32), 18933(ins IntRegs:$Rs32, IntRegs:$Rt32), 18934"$Rd32 = lsl($Rs32,$Rt32)", 18935tc_946df596, TypeS_3op>, Enc_5ab2be { 18936let Inst{7-5} = 0b110; 18937let Inst{13-13} = 0b0; 18938let Inst{31-21} = 0b11000110010; 18939let hasNewValue = 1; 18940let opNewValue = 0; 18941} 18942def S2_lsl_r_r_acc : HInst< 18943(outs IntRegs:$Rx32), 18944(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), 18945"$Rx32 += lsl($Rs32,$Rt32)", 18946tc_f675fee8, TypeS_3op>, Enc_2ae154 { 18947let Inst{7-5} = 0b110; 18948let Inst{13-13} = 0b0; 18949let Inst{31-21} = 0b11001100110; 18950let hasNewValue = 1; 18951let opNewValue = 0; 18952let prefersSlot3 = 1; 18953let Constraints = "$Rx32 = $Rx32in"; 18954} 18955def S2_lsl_r_r_and : HInst< 18956(outs IntRegs:$Rx32), 18957(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), 18958"$Rx32 &= lsl($Rs32,$Rt32)", 18959tc_f429765c, TypeS_3op>, Enc_2ae154 { 18960let Inst{7-5} = 0b110; 18961let Inst{13-13} = 0b0; 18962let Inst{31-21} = 0b11001100010; 18963let hasNewValue = 1; 18964let opNewValue = 0; 18965let prefersSlot3 = 1; 18966let Constraints = "$Rx32 = $Rx32in"; 18967} 18968def S2_lsl_r_r_nac : HInst< 18969(outs IntRegs:$Rx32), 18970(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), 18971"$Rx32 -= lsl($Rs32,$Rt32)", 18972tc_f675fee8, TypeS_3op>, Enc_2ae154 { 18973let Inst{7-5} = 0b110; 18974let Inst{13-13} = 0b0; 18975let Inst{31-21} = 0b11001100100; 18976let hasNewValue = 1; 18977let opNewValue = 0; 18978let prefersSlot3 = 1; 18979let Constraints = "$Rx32 = $Rx32in"; 18980} 18981def S2_lsl_r_r_or : HInst< 18982(outs IntRegs:$Rx32), 18983(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), 18984"$Rx32 |= lsl($Rs32,$Rt32)", 18985tc_f429765c, TypeS_3op>, Enc_2ae154 { 18986let Inst{7-5} = 0b110; 18987let Inst{13-13} = 0b0; 18988let Inst{31-21} = 0b11001100000; 18989let hasNewValue = 1; 18990let opNewValue = 0; 18991let prefersSlot3 = 1; 18992let Constraints = "$Rx32 = $Rx32in"; 18993} 18994def S2_lsl_r_vh : HInst< 18995(outs DoubleRegs:$Rdd32), 18996(ins DoubleRegs:$Rss32, IntRegs:$Rt32), 18997"$Rdd32 = vlslh($Rss32,$Rt32)", 18998tc_946df596, TypeS_3op>, Enc_927852 { 18999let Inst{7-5} = 0b110; 19000let Inst{13-13} = 0b0; 19001let Inst{31-21} = 0b11000011010; 19002} 19003def S2_lsl_r_vw : HInst< 19004(outs DoubleRegs:$Rdd32), 19005(ins DoubleRegs:$Rss32, IntRegs:$Rt32), 19006"$Rdd32 = vlslw($Rss32,$Rt32)", 19007tc_946df596, TypeS_3op>, Enc_927852 { 19008let Inst{7-5} = 0b110; 19009let Inst{13-13} = 0b0; 19010let Inst{31-21} = 0b11000011000; 19011} 19012def S2_lsr_i_p : HInst< 19013(outs DoubleRegs:$Rdd32), 19014(ins DoubleRegs:$Rss32, u6_0Imm:$Ii), 19015"$Rdd32 = lsr($Rss32,#$Ii)", 19016tc_946df596, TypeS_2op>, Enc_5eac98 { 19017let Inst{7-5} = 0b001; 19018let Inst{31-21} = 0b10000000000; 19019} 19020def S2_lsr_i_p_acc : HInst< 19021(outs DoubleRegs:$Rxx32), 19022(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii), 19023"$Rxx32 += lsr($Rss32,#$Ii)", 19024tc_f675fee8, TypeS_2op>, Enc_70fb07 { 19025let Inst{7-5} = 0b101; 19026let Inst{31-21} = 0b10000010000; 19027let prefersSlot3 = 1; 19028let Constraints = "$Rxx32 = $Rxx32in"; 19029} 19030def S2_lsr_i_p_and : HInst< 19031(outs DoubleRegs:$Rxx32), 19032(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii), 19033"$Rxx32 &= lsr($Rss32,#$Ii)", 19034tc_f429765c, TypeS_2op>, Enc_70fb07 { 19035let Inst{7-5} = 0b001; 19036let Inst{31-21} = 0b10000010010; 19037let prefersSlot3 = 1; 19038let Constraints = "$Rxx32 = $Rxx32in"; 19039} 19040def S2_lsr_i_p_nac : HInst< 19041(outs DoubleRegs:$Rxx32), 19042(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii), 19043"$Rxx32 -= lsr($Rss32,#$Ii)", 19044tc_f675fee8, TypeS_2op>, Enc_70fb07 { 19045let Inst{7-5} = 0b001; 19046let Inst{31-21} = 0b10000010000; 19047let prefersSlot3 = 1; 19048let Constraints = "$Rxx32 = $Rxx32in"; 19049} 19050def S2_lsr_i_p_or : HInst< 19051(outs DoubleRegs:$Rxx32), 19052(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii), 19053"$Rxx32 |= lsr($Rss32,#$Ii)", 19054tc_f429765c, TypeS_2op>, Enc_70fb07 { 19055let Inst{7-5} = 0b101; 19056let Inst{31-21} = 0b10000010010; 19057let prefersSlot3 = 1; 19058let Constraints = "$Rxx32 = $Rxx32in"; 19059} 19060def S2_lsr_i_p_xacc : HInst< 19061(outs DoubleRegs:$Rxx32), 19062(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii), 19063"$Rxx32 ^= lsr($Rss32,#$Ii)", 19064tc_f429765c, TypeS_2op>, Enc_70fb07 { 19065let Inst{7-5} = 0b001; 19066let Inst{31-21} = 0b10000010100; 19067let prefersSlot3 = 1; 19068let Constraints = "$Rxx32 = $Rxx32in"; 19069} 19070def S2_lsr_i_r : HInst< 19071(outs IntRegs:$Rd32), 19072(ins IntRegs:$Rs32, u5_0Imm:$Ii), 19073"$Rd32 = lsr($Rs32,#$Ii)", 19074tc_946df596, TypeS_2op>, Enc_a05677 { 19075let Inst{7-5} = 0b001; 19076let Inst{13-13} = 0b0; 19077let Inst{31-21} = 0b10001100000; 19078let hasNewValue = 1; 19079let opNewValue = 0; 19080} 19081def S2_lsr_i_r_acc : HInst< 19082(outs IntRegs:$Rx32), 19083(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii), 19084"$Rx32 += lsr($Rs32,#$Ii)", 19085tc_f675fee8, TypeS_2op>, Enc_28a2dc { 19086let Inst{7-5} = 0b101; 19087let Inst{13-13} = 0b0; 19088let Inst{31-21} = 0b10001110000; 19089let hasNewValue = 1; 19090let opNewValue = 0; 19091let prefersSlot3 = 1; 19092let Constraints = "$Rx32 = $Rx32in"; 19093} 19094def S2_lsr_i_r_and : HInst< 19095(outs IntRegs:$Rx32), 19096(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii), 19097"$Rx32 &= lsr($Rs32,#$Ii)", 19098tc_f429765c, TypeS_2op>, Enc_28a2dc { 19099let Inst{7-5} = 0b001; 19100let Inst{13-13} = 0b0; 19101let Inst{31-21} = 0b10001110010; 19102let hasNewValue = 1; 19103let opNewValue = 0; 19104let prefersSlot3 = 1; 19105let Constraints = "$Rx32 = $Rx32in"; 19106} 19107def S2_lsr_i_r_nac : HInst< 19108(outs IntRegs:$Rx32), 19109(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii), 19110"$Rx32 -= lsr($Rs32,#$Ii)", 19111tc_f675fee8, TypeS_2op>, Enc_28a2dc { 19112let Inst{7-5} = 0b001; 19113let Inst{13-13} = 0b0; 19114let Inst{31-21} = 0b10001110000; 19115let hasNewValue = 1; 19116let opNewValue = 0; 19117let prefersSlot3 = 1; 19118let Constraints = "$Rx32 = $Rx32in"; 19119} 19120def S2_lsr_i_r_or : HInst< 19121(outs IntRegs:$Rx32), 19122(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii), 19123"$Rx32 |= lsr($Rs32,#$Ii)", 19124tc_f429765c, TypeS_2op>, Enc_28a2dc { 19125let Inst{7-5} = 0b101; 19126let Inst{13-13} = 0b0; 19127let Inst{31-21} = 0b10001110010; 19128let hasNewValue = 1; 19129let opNewValue = 0; 19130let prefersSlot3 = 1; 19131let Constraints = "$Rx32 = $Rx32in"; 19132} 19133def S2_lsr_i_r_xacc : HInst< 19134(outs IntRegs:$Rx32), 19135(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii), 19136"$Rx32 ^= lsr($Rs32,#$Ii)", 19137tc_f429765c, TypeS_2op>, Enc_28a2dc { 19138let Inst{7-5} = 0b001; 19139let Inst{13-13} = 0b0; 19140let Inst{31-21} = 0b10001110100; 19141let hasNewValue = 1; 19142let opNewValue = 0; 19143let prefersSlot3 = 1; 19144let Constraints = "$Rx32 = $Rx32in"; 19145} 19146def S2_lsr_i_vh : HInst< 19147(outs DoubleRegs:$Rdd32), 19148(ins DoubleRegs:$Rss32, u4_0Imm:$Ii), 19149"$Rdd32 = vlsrh($Rss32,#$Ii)", 19150tc_946df596, TypeS_2op>, Enc_12b6e9 { 19151let Inst{7-5} = 0b001; 19152let Inst{13-12} = 0b00; 19153let Inst{31-21} = 0b10000000100; 19154} 19155def S2_lsr_i_vw : HInst< 19156(outs DoubleRegs:$Rdd32), 19157(ins DoubleRegs:$Rss32, u5_0Imm:$Ii), 19158"$Rdd32 = vlsrw($Rss32,#$Ii)", 19159tc_946df596, TypeS_2op>, Enc_7e5a82 { 19160let Inst{7-5} = 0b001; 19161let Inst{13-13} = 0b0; 19162let Inst{31-21} = 0b10000000010; 19163} 19164def S2_lsr_r_p : HInst< 19165(outs DoubleRegs:$Rdd32), 19166(ins DoubleRegs:$Rss32, IntRegs:$Rt32), 19167"$Rdd32 = lsr($Rss32,$Rt32)", 19168tc_946df596, TypeS_3op>, Enc_927852 { 19169let Inst{7-5} = 0b010; 19170let Inst{13-13} = 0b0; 19171let Inst{31-21} = 0b11000011100; 19172} 19173def S2_lsr_r_p_acc : HInst< 19174(outs DoubleRegs:$Rxx32), 19175(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32), 19176"$Rxx32 += lsr($Rss32,$Rt32)", 19177tc_f675fee8, TypeS_3op>, Enc_1aa186 { 19178let Inst{7-5} = 0b010; 19179let Inst{13-13} = 0b0; 19180let Inst{31-21} = 0b11001011110; 19181let prefersSlot3 = 1; 19182let Constraints = "$Rxx32 = $Rxx32in"; 19183} 19184def S2_lsr_r_p_and : HInst< 19185(outs DoubleRegs:$Rxx32), 19186(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32), 19187"$Rxx32 &= lsr($Rss32,$Rt32)", 19188tc_f429765c, TypeS_3op>, Enc_1aa186 { 19189let Inst{7-5} = 0b010; 19190let Inst{13-13} = 0b0; 19191let Inst{31-21} = 0b11001011010; 19192let prefersSlot3 = 1; 19193let Constraints = "$Rxx32 = $Rxx32in"; 19194} 19195def S2_lsr_r_p_nac : HInst< 19196(outs DoubleRegs:$Rxx32), 19197(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32), 19198"$Rxx32 -= lsr($Rss32,$Rt32)", 19199tc_f675fee8, TypeS_3op>, Enc_1aa186 { 19200let Inst{7-5} = 0b010; 19201let Inst{13-13} = 0b0; 19202let Inst{31-21} = 0b11001011100; 19203let prefersSlot3 = 1; 19204let Constraints = "$Rxx32 = $Rxx32in"; 19205} 19206def S2_lsr_r_p_or : HInst< 19207(outs DoubleRegs:$Rxx32), 19208(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32), 19209"$Rxx32 |= lsr($Rss32,$Rt32)", 19210tc_f429765c, TypeS_3op>, Enc_1aa186 { 19211let Inst{7-5} = 0b010; 19212let Inst{13-13} = 0b0; 19213let Inst{31-21} = 0b11001011000; 19214let prefersSlot3 = 1; 19215let Constraints = "$Rxx32 = $Rxx32in"; 19216} 19217def S2_lsr_r_p_xor : HInst< 19218(outs DoubleRegs:$Rxx32), 19219(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32), 19220"$Rxx32 ^= lsr($Rss32,$Rt32)", 19221tc_f429765c, TypeS_3op>, Enc_1aa186 { 19222let Inst{7-5} = 0b010; 19223let Inst{13-13} = 0b0; 19224let Inst{31-21} = 0b11001011011; 19225let prefersSlot3 = 1; 19226let Constraints = "$Rxx32 = $Rxx32in"; 19227} 19228def S2_lsr_r_r : HInst< 19229(outs IntRegs:$Rd32), 19230(ins IntRegs:$Rs32, IntRegs:$Rt32), 19231"$Rd32 = lsr($Rs32,$Rt32)", 19232tc_946df596, TypeS_3op>, Enc_5ab2be { 19233let Inst{7-5} = 0b010; 19234let Inst{13-13} = 0b0; 19235let Inst{31-21} = 0b11000110010; 19236let hasNewValue = 1; 19237let opNewValue = 0; 19238} 19239def S2_lsr_r_r_acc : HInst< 19240(outs IntRegs:$Rx32), 19241(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), 19242"$Rx32 += lsr($Rs32,$Rt32)", 19243tc_f675fee8, TypeS_3op>, Enc_2ae154 { 19244let Inst{7-5} = 0b010; 19245let Inst{13-13} = 0b0; 19246let Inst{31-21} = 0b11001100110; 19247let hasNewValue = 1; 19248let opNewValue = 0; 19249let prefersSlot3 = 1; 19250let Constraints = "$Rx32 = $Rx32in"; 19251} 19252def S2_lsr_r_r_and : HInst< 19253(outs IntRegs:$Rx32), 19254(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), 19255"$Rx32 &= lsr($Rs32,$Rt32)", 19256tc_f429765c, TypeS_3op>, Enc_2ae154 { 19257let Inst{7-5} = 0b010; 19258let Inst{13-13} = 0b0; 19259let Inst{31-21} = 0b11001100010; 19260let hasNewValue = 1; 19261let opNewValue = 0; 19262let prefersSlot3 = 1; 19263let Constraints = "$Rx32 = $Rx32in"; 19264} 19265def S2_lsr_r_r_nac : HInst< 19266(outs IntRegs:$Rx32), 19267(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), 19268"$Rx32 -= lsr($Rs32,$Rt32)", 19269tc_f675fee8, TypeS_3op>, Enc_2ae154 { 19270let Inst{7-5} = 0b010; 19271let Inst{13-13} = 0b0; 19272let Inst{31-21} = 0b11001100100; 19273let hasNewValue = 1; 19274let opNewValue = 0; 19275let prefersSlot3 = 1; 19276let Constraints = "$Rx32 = $Rx32in"; 19277} 19278def S2_lsr_r_r_or : HInst< 19279(outs IntRegs:$Rx32), 19280(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), 19281"$Rx32 |= lsr($Rs32,$Rt32)", 19282tc_f429765c, TypeS_3op>, Enc_2ae154 { 19283let Inst{7-5} = 0b010; 19284let Inst{13-13} = 0b0; 19285let Inst{31-21} = 0b11001100000; 19286let hasNewValue = 1; 19287let opNewValue = 0; 19288let prefersSlot3 = 1; 19289let Constraints = "$Rx32 = $Rx32in"; 19290} 19291def S2_lsr_r_vh : HInst< 19292(outs DoubleRegs:$Rdd32), 19293(ins DoubleRegs:$Rss32, IntRegs:$Rt32), 19294"$Rdd32 = vlsrh($Rss32,$Rt32)", 19295tc_946df596, TypeS_3op>, Enc_927852 { 19296let Inst{7-5} = 0b010; 19297let Inst{13-13} = 0b0; 19298let Inst{31-21} = 0b11000011010; 19299} 19300def S2_lsr_r_vw : HInst< 19301(outs DoubleRegs:$Rdd32), 19302(ins DoubleRegs:$Rss32, IntRegs:$Rt32), 19303"$Rdd32 = vlsrw($Rss32,$Rt32)", 19304tc_946df596, TypeS_3op>, Enc_927852 { 19305let Inst{7-5} = 0b010; 19306let Inst{13-13} = 0b0; 19307let Inst{31-21} = 0b11000011000; 19308} 19309def S2_mask : HInst< 19310(outs IntRegs:$Rd32), 19311(ins u5_0Imm:$Ii, u5_0Imm:$II), 19312"$Rd32 = mask(#$Ii,#$II)", 19313tc_9461ff31, TypeS_2op>, Enc_c85e2a, Requires<[HasV66]> { 19314let Inst{13-13} = 0b1; 19315let Inst{20-16} = 0b00000; 19316let Inst{31-23} = 0b100011010; 19317let hasNewValue = 1; 19318let opNewValue = 0; 19319let prefersSlot3 = 1; 19320} 19321def S2_packhl : HInst< 19322(outs DoubleRegs:$Rdd32), 19323(ins IntRegs:$Rs32, IntRegs:$Rt32), 19324"$Rdd32 = packhl($Rs32,$Rt32)", 19325tc_5a2711e5, TypeALU32_3op>, Enc_be32a5 { 19326let Inst{7-5} = 0b000; 19327let Inst{13-13} = 0b0; 19328let Inst{31-21} = 0b11110101100; 19329let InputType = "reg"; 19330} 19331def S2_parityp : HInst< 19332(outs IntRegs:$Rd32), 19333(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 19334"$Rd32 = parity($Rss32,$Rtt32)", 19335tc_002cb246, TypeALU64>, Enc_d2216a { 19336let Inst{7-5} = 0b000; 19337let Inst{13-13} = 0b0; 19338let Inst{31-21} = 0b11010000000; 19339let hasNewValue = 1; 19340let opNewValue = 0; 19341let prefersSlot3 = 1; 19342} 19343def S2_pstorerbf_io : HInst< 19344(outs), 19345(ins PredRegs:$Pv4, IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Rt32), 19346"if (!$Pv4) memb($Rs32+#$Ii) = $Rt32", 19347tc_f8e23f0b, TypeV2LDST>, Enc_da8d43, AddrModeRel { 19348let Inst{2-2} = 0b0; 19349let Inst{31-21} = 0b01000100000; 19350let isPredicated = 1; 19351let isPredicatedFalse = 1; 19352let addrMode = BaseImmOffset; 19353let accessSize = ByteAccess; 19354let mayStore = 1; 19355let CextOpcode = "S2_storerb"; 19356let InputType = "imm"; 19357let BaseOpcode = "S2_storerb_io"; 19358let isNVStorable = 1; 19359let isExtendable = 1; 19360let opExtendable = 2; 19361let isExtentSigned = 0; 19362let opExtentBits = 6; 19363let opExtentAlign = 0; 19364} 19365def S2_pstorerbf_pi : HInst< 19366(outs IntRegs:$Rx32), 19367(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_0Imm:$Ii, IntRegs:$Rt32), 19368"if (!$Pv4) memb($Rx32++#$Ii) = $Rt32", 19369tc_24b66c99, TypeST>, Enc_cc449f, AddrModeRel { 19370let Inst{2-2} = 0b1; 19371let Inst{7-7} = 0b0; 19372let Inst{13-13} = 0b1; 19373let Inst{31-21} = 0b10101011000; 19374let isPredicated = 1; 19375let isPredicatedFalse = 1; 19376let addrMode = PostInc; 19377let accessSize = ByteAccess; 19378let mayStore = 1; 19379let BaseOpcode = "S2_storerb_pi"; 19380let isNVStorable = 1; 19381let Constraints = "$Rx32 = $Rx32in"; 19382} 19383def S2_pstorerbf_zomap : HInst< 19384(outs), 19385(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32), 19386"if (!$Pv4) memb($Rs32) = $Rt32", 19387tc_f8e23f0b, TypeMAPPING> { 19388let isPseudo = 1; 19389let isCodeGenOnly = 1; 19390} 19391def S2_pstorerbfnew_pi : HInst< 19392(outs IntRegs:$Rx32), 19393(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_0Imm:$Ii, IntRegs:$Rt32), 19394"if (!$Pv4.new) memb($Rx32++#$Ii) = $Rt32", 19395tc_53559e35, TypeST>, Enc_cc449f, AddrModeRel { 19396let Inst{2-2} = 0b1; 19397let Inst{7-7} = 0b1; 19398let Inst{13-13} = 0b1; 19399let Inst{31-21} = 0b10101011000; 19400let isPredicated = 1; 19401let isPredicatedFalse = 1; 19402let addrMode = PostInc; 19403let accessSize = ByteAccess; 19404let isPredicatedNew = 1; 19405let mayStore = 1; 19406let BaseOpcode = "S2_storerb_pi"; 19407let isNVStorable = 1; 19408let Constraints = "$Rx32 = $Rx32in"; 19409} 19410def S2_pstorerbnewf_io : HInst< 19411(outs), 19412(ins PredRegs:$Pv4, IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Nt8), 19413"if (!$Pv4) memb($Rs32+#$Ii) = $Nt8.new", 19414tc_8fb7ab1b, TypeV2LDST>, Enc_585242, AddrModeRel { 19415let Inst{2-2} = 0b0; 19416let Inst{12-11} = 0b00; 19417let Inst{31-21} = 0b01000100101; 19418let isPredicated = 1; 19419let isPredicatedFalse = 1; 19420let addrMode = BaseImmOffset; 19421let accessSize = ByteAccess; 19422let isNVStore = 1; 19423let isNewValue = 1; 19424let isRestrictNoSlot1Store = 1; 19425let mayStore = 1; 19426let CextOpcode = "S2_storerb"; 19427let InputType = "imm"; 19428let BaseOpcode = "S2_storerb_io"; 19429let isExtendable = 1; 19430let opExtendable = 2; 19431let isExtentSigned = 0; 19432let opExtentBits = 6; 19433let opExtentAlign = 0; 19434let opNewValue = 3; 19435} 19436def S2_pstorerbnewf_pi : HInst< 19437(outs IntRegs:$Rx32), 19438(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_0Imm:$Ii, IntRegs:$Nt8), 19439"if (!$Pv4) memb($Rx32++#$Ii) = $Nt8.new", 19440tc_838b34ea, TypeST>, Enc_52a5dd, AddrModeRel { 19441let Inst{2-2} = 0b1; 19442let Inst{7-7} = 0b0; 19443let Inst{13-11} = 0b100; 19444let Inst{31-21} = 0b10101011101; 19445let isPredicated = 1; 19446let isPredicatedFalse = 1; 19447let addrMode = PostInc; 19448let accessSize = ByteAccess; 19449let isNVStore = 1; 19450let isNewValue = 1; 19451let isRestrictNoSlot1Store = 1; 19452let mayStore = 1; 19453let CextOpcode = "S2_storerb"; 19454let BaseOpcode = "S2_storerb_pi"; 19455let opNewValue = 4; 19456let Constraints = "$Rx32 = $Rx32in"; 19457} 19458def S2_pstorerbnewf_zomap : HInst< 19459(outs), 19460(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8), 19461"if (!$Pv4) memb($Rs32) = $Nt8.new", 19462tc_8fb7ab1b, TypeMAPPING> { 19463let isPseudo = 1; 19464let isCodeGenOnly = 1; 19465let opNewValue = 2; 19466} 19467def S2_pstorerbnewfnew_pi : HInst< 19468(outs IntRegs:$Rx32), 19469(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_0Imm:$Ii, IntRegs:$Nt8), 19470"if (!$Pv4.new) memb($Rx32++#$Ii) = $Nt8.new", 19471tc_d65dbf51, TypeST>, Enc_52a5dd, AddrModeRel { 19472let Inst{2-2} = 0b1; 19473let Inst{7-7} = 0b1; 19474let Inst{13-11} = 0b100; 19475let Inst{31-21} = 0b10101011101; 19476let isPredicated = 1; 19477let isPredicatedFalse = 1; 19478let addrMode = PostInc; 19479let accessSize = ByteAccess; 19480let isNVStore = 1; 19481let isPredicatedNew = 1; 19482let isNewValue = 1; 19483let isRestrictNoSlot1Store = 1; 19484let mayStore = 1; 19485let CextOpcode = "S2_storerb"; 19486let BaseOpcode = "S2_storerb_pi"; 19487let opNewValue = 4; 19488let Constraints = "$Rx32 = $Rx32in"; 19489} 19490def S2_pstorerbnewt_io : HInst< 19491(outs), 19492(ins PredRegs:$Pv4, IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Nt8), 19493"if ($Pv4) memb($Rs32+#$Ii) = $Nt8.new", 19494tc_8fb7ab1b, TypeV2LDST>, Enc_585242, AddrModeRel { 19495let Inst{2-2} = 0b0; 19496let Inst{12-11} = 0b00; 19497let Inst{31-21} = 0b01000000101; 19498let isPredicated = 1; 19499let addrMode = BaseImmOffset; 19500let accessSize = ByteAccess; 19501let isNVStore = 1; 19502let isNewValue = 1; 19503let isRestrictNoSlot1Store = 1; 19504let mayStore = 1; 19505let CextOpcode = "S2_storerb"; 19506let InputType = "imm"; 19507let BaseOpcode = "S2_storerb_io"; 19508let isExtendable = 1; 19509let opExtendable = 2; 19510let isExtentSigned = 0; 19511let opExtentBits = 6; 19512let opExtentAlign = 0; 19513let opNewValue = 3; 19514} 19515def S2_pstorerbnewt_pi : HInst< 19516(outs IntRegs:$Rx32), 19517(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_0Imm:$Ii, IntRegs:$Nt8), 19518"if ($Pv4) memb($Rx32++#$Ii) = $Nt8.new", 19519tc_838b34ea, TypeST>, Enc_52a5dd, AddrModeRel { 19520let Inst{2-2} = 0b0; 19521let Inst{7-7} = 0b0; 19522let Inst{13-11} = 0b100; 19523let Inst{31-21} = 0b10101011101; 19524let isPredicated = 1; 19525let addrMode = PostInc; 19526let accessSize = ByteAccess; 19527let isNVStore = 1; 19528let isNewValue = 1; 19529let isRestrictNoSlot1Store = 1; 19530let mayStore = 1; 19531let CextOpcode = "S2_storerb"; 19532let BaseOpcode = "S2_storerb_pi"; 19533let opNewValue = 4; 19534let Constraints = "$Rx32 = $Rx32in"; 19535} 19536def S2_pstorerbnewt_zomap : HInst< 19537(outs), 19538(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8), 19539"if ($Pv4) memb($Rs32) = $Nt8.new", 19540tc_8fb7ab1b, TypeMAPPING> { 19541let isPseudo = 1; 19542let isCodeGenOnly = 1; 19543let opNewValue = 2; 19544} 19545def S2_pstorerbnewtnew_pi : HInst< 19546(outs IntRegs:$Rx32), 19547(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_0Imm:$Ii, IntRegs:$Nt8), 19548"if ($Pv4.new) memb($Rx32++#$Ii) = $Nt8.new", 19549tc_d65dbf51, TypeST>, Enc_52a5dd, AddrModeRel { 19550let Inst{2-2} = 0b0; 19551let Inst{7-7} = 0b1; 19552let Inst{13-11} = 0b100; 19553let Inst{31-21} = 0b10101011101; 19554let isPredicated = 1; 19555let addrMode = PostInc; 19556let accessSize = ByteAccess; 19557let isNVStore = 1; 19558let isPredicatedNew = 1; 19559let isNewValue = 1; 19560let isRestrictNoSlot1Store = 1; 19561let mayStore = 1; 19562let CextOpcode = "S2_storerb"; 19563let BaseOpcode = "S2_storerb_pi"; 19564let opNewValue = 4; 19565let Constraints = "$Rx32 = $Rx32in"; 19566} 19567def S2_pstorerbt_io : HInst< 19568(outs), 19569(ins PredRegs:$Pv4, IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Rt32), 19570"if ($Pv4) memb($Rs32+#$Ii) = $Rt32", 19571tc_f8e23f0b, TypeV2LDST>, Enc_da8d43, AddrModeRel { 19572let Inst{2-2} = 0b0; 19573let Inst{31-21} = 0b01000000000; 19574let isPredicated = 1; 19575let addrMode = BaseImmOffset; 19576let accessSize = ByteAccess; 19577let mayStore = 1; 19578let CextOpcode = "S2_storerb"; 19579let InputType = "imm"; 19580let BaseOpcode = "S2_storerb_io"; 19581let isNVStorable = 1; 19582let isExtendable = 1; 19583let opExtendable = 2; 19584let isExtentSigned = 0; 19585let opExtentBits = 6; 19586let opExtentAlign = 0; 19587} 19588def S2_pstorerbt_pi : HInst< 19589(outs IntRegs:$Rx32), 19590(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_0Imm:$Ii, IntRegs:$Rt32), 19591"if ($Pv4) memb($Rx32++#$Ii) = $Rt32", 19592tc_24b66c99, TypeST>, Enc_cc449f, AddrModeRel { 19593let Inst{2-2} = 0b0; 19594let Inst{7-7} = 0b0; 19595let Inst{13-13} = 0b1; 19596let Inst{31-21} = 0b10101011000; 19597let isPredicated = 1; 19598let addrMode = PostInc; 19599let accessSize = ByteAccess; 19600let mayStore = 1; 19601let BaseOpcode = "S2_storerb_pi"; 19602let isNVStorable = 1; 19603let Constraints = "$Rx32 = $Rx32in"; 19604} 19605def S2_pstorerbt_zomap : HInst< 19606(outs), 19607(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32), 19608"if ($Pv4) memb($Rs32) = $Rt32", 19609tc_f8e23f0b, TypeMAPPING> { 19610let isPseudo = 1; 19611let isCodeGenOnly = 1; 19612} 19613def S2_pstorerbtnew_pi : HInst< 19614(outs IntRegs:$Rx32), 19615(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_0Imm:$Ii, IntRegs:$Rt32), 19616"if ($Pv4.new) memb($Rx32++#$Ii) = $Rt32", 19617tc_53559e35, TypeST>, Enc_cc449f, AddrModeRel { 19618let Inst{2-2} = 0b0; 19619let Inst{7-7} = 0b1; 19620let Inst{13-13} = 0b1; 19621let Inst{31-21} = 0b10101011000; 19622let isPredicated = 1; 19623let addrMode = PostInc; 19624let accessSize = ByteAccess; 19625let isPredicatedNew = 1; 19626let mayStore = 1; 19627let BaseOpcode = "S2_storerb_pi"; 19628let isNVStorable = 1; 19629let Constraints = "$Rx32 = $Rx32in"; 19630} 19631def S2_pstorerdf_io : HInst< 19632(outs), 19633(ins PredRegs:$Pv4, IntRegs:$Rs32, u29_3Imm:$Ii, DoubleRegs:$Rtt32), 19634"if (!$Pv4) memd($Rs32+#$Ii) = $Rtt32", 19635tc_f8e23f0b, TypeV2LDST>, Enc_57a33e, AddrModeRel { 19636let Inst{2-2} = 0b0; 19637let Inst{31-21} = 0b01000100110; 19638let isPredicated = 1; 19639let isPredicatedFalse = 1; 19640let addrMode = BaseImmOffset; 19641let accessSize = DoubleWordAccess; 19642let mayStore = 1; 19643let CextOpcode = "S2_storerd"; 19644let InputType = "imm"; 19645let BaseOpcode = "S2_storerd_io"; 19646let isExtendable = 1; 19647let opExtendable = 2; 19648let isExtentSigned = 0; 19649let opExtentBits = 9; 19650let opExtentAlign = 3; 19651} 19652def S2_pstorerdf_pi : HInst< 19653(outs IntRegs:$Rx32), 19654(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_3Imm:$Ii, DoubleRegs:$Rtt32), 19655"if (!$Pv4) memd($Rx32++#$Ii) = $Rtt32", 19656tc_24b66c99, TypeST>, Enc_9a33d5, AddrModeRel { 19657let Inst{2-2} = 0b1; 19658let Inst{7-7} = 0b0; 19659let Inst{13-13} = 0b1; 19660let Inst{31-21} = 0b10101011110; 19661let isPredicated = 1; 19662let isPredicatedFalse = 1; 19663let addrMode = PostInc; 19664let accessSize = DoubleWordAccess; 19665let mayStore = 1; 19666let CextOpcode = "S2_storerd"; 19667let BaseOpcode = "S2_storerd_pi"; 19668let Constraints = "$Rx32 = $Rx32in"; 19669} 19670def S2_pstorerdf_zomap : HInst< 19671(outs), 19672(ins PredRegs:$Pv4, IntRegs:$Rs32, DoubleRegs:$Rtt32), 19673"if (!$Pv4) memd($Rs32) = $Rtt32", 19674tc_f8e23f0b, TypeMAPPING> { 19675let isPseudo = 1; 19676let isCodeGenOnly = 1; 19677} 19678def S2_pstorerdfnew_pi : HInst< 19679(outs IntRegs:$Rx32), 19680(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_3Imm:$Ii, DoubleRegs:$Rtt32), 19681"if (!$Pv4.new) memd($Rx32++#$Ii) = $Rtt32", 19682tc_53559e35, TypeST>, Enc_9a33d5, AddrModeRel { 19683let Inst{2-2} = 0b1; 19684let Inst{7-7} = 0b1; 19685let Inst{13-13} = 0b1; 19686let Inst{31-21} = 0b10101011110; 19687let isPredicated = 1; 19688let isPredicatedFalse = 1; 19689let addrMode = PostInc; 19690let accessSize = DoubleWordAccess; 19691let isPredicatedNew = 1; 19692let mayStore = 1; 19693let CextOpcode = "S2_storerd"; 19694let BaseOpcode = "S2_storerd_pi"; 19695let Constraints = "$Rx32 = $Rx32in"; 19696} 19697def S2_pstorerdt_io : HInst< 19698(outs), 19699(ins PredRegs:$Pv4, IntRegs:$Rs32, u29_3Imm:$Ii, DoubleRegs:$Rtt32), 19700"if ($Pv4) memd($Rs32+#$Ii) = $Rtt32", 19701tc_f8e23f0b, TypeV2LDST>, Enc_57a33e, AddrModeRel { 19702let Inst{2-2} = 0b0; 19703let Inst{31-21} = 0b01000000110; 19704let isPredicated = 1; 19705let addrMode = BaseImmOffset; 19706let accessSize = DoubleWordAccess; 19707let mayStore = 1; 19708let CextOpcode = "S2_storerd"; 19709let InputType = "imm"; 19710let BaseOpcode = "S2_storerd_io"; 19711let isExtendable = 1; 19712let opExtendable = 2; 19713let isExtentSigned = 0; 19714let opExtentBits = 9; 19715let opExtentAlign = 3; 19716} 19717def S2_pstorerdt_pi : HInst< 19718(outs IntRegs:$Rx32), 19719(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_3Imm:$Ii, DoubleRegs:$Rtt32), 19720"if ($Pv4) memd($Rx32++#$Ii) = $Rtt32", 19721tc_24b66c99, TypeST>, Enc_9a33d5, AddrModeRel { 19722let Inst{2-2} = 0b0; 19723let Inst{7-7} = 0b0; 19724let Inst{13-13} = 0b1; 19725let Inst{31-21} = 0b10101011110; 19726let isPredicated = 1; 19727let addrMode = PostInc; 19728let accessSize = DoubleWordAccess; 19729let mayStore = 1; 19730let CextOpcode = "S2_storerd"; 19731let BaseOpcode = "S2_storerd_pi"; 19732let Constraints = "$Rx32 = $Rx32in"; 19733} 19734def S2_pstorerdt_zomap : HInst< 19735(outs), 19736(ins PredRegs:$Pv4, IntRegs:$Rs32, DoubleRegs:$Rtt32), 19737"if ($Pv4) memd($Rs32) = $Rtt32", 19738tc_f8e23f0b, TypeMAPPING> { 19739let isPseudo = 1; 19740let isCodeGenOnly = 1; 19741} 19742def S2_pstorerdtnew_pi : HInst< 19743(outs IntRegs:$Rx32), 19744(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_3Imm:$Ii, DoubleRegs:$Rtt32), 19745"if ($Pv4.new) memd($Rx32++#$Ii) = $Rtt32", 19746tc_53559e35, TypeST>, Enc_9a33d5, AddrModeRel { 19747let Inst{2-2} = 0b0; 19748let Inst{7-7} = 0b1; 19749let Inst{13-13} = 0b1; 19750let Inst{31-21} = 0b10101011110; 19751let isPredicated = 1; 19752let addrMode = PostInc; 19753let accessSize = DoubleWordAccess; 19754let isPredicatedNew = 1; 19755let mayStore = 1; 19756let CextOpcode = "S2_storerd"; 19757let BaseOpcode = "S2_storerd_pi"; 19758let Constraints = "$Rx32 = $Rx32in"; 19759} 19760def S2_pstorerff_io : HInst< 19761(outs), 19762(ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32), 19763"if (!$Pv4) memh($Rs32+#$Ii) = $Rt32.h", 19764tc_f8e23f0b, TypeV2LDST>, Enc_e8c45e, AddrModeRel { 19765let Inst{2-2} = 0b0; 19766let Inst{31-21} = 0b01000100011; 19767let isPredicated = 1; 19768let isPredicatedFalse = 1; 19769let addrMode = BaseImmOffset; 19770let accessSize = HalfWordAccess; 19771let mayStore = 1; 19772let CextOpcode = "S2_storerf"; 19773let InputType = "imm"; 19774let BaseOpcode = "S2_storerf_io"; 19775let isExtendable = 1; 19776let opExtendable = 2; 19777let isExtentSigned = 0; 19778let opExtentBits = 7; 19779let opExtentAlign = 1; 19780} 19781def S2_pstorerff_pi : HInst< 19782(outs IntRegs:$Rx32), 19783(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Rt32), 19784"if (!$Pv4) memh($Rx32++#$Ii) = $Rt32.h", 19785tc_24b66c99, TypeST>, Enc_b886fd, AddrModeRel { 19786let Inst{2-2} = 0b1; 19787let Inst{7-7} = 0b0; 19788let Inst{13-13} = 0b1; 19789let Inst{31-21} = 0b10101011011; 19790let isPredicated = 1; 19791let isPredicatedFalse = 1; 19792let addrMode = PostInc; 19793let accessSize = HalfWordAccess; 19794let mayStore = 1; 19795let CextOpcode = "S2_storerf"; 19796let BaseOpcode = "S2_storerf_pi"; 19797let Constraints = "$Rx32 = $Rx32in"; 19798} 19799def S2_pstorerff_zomap : HInst< 19800(outs), 19801(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32), 19802"if (!$Pv4) memh($Rs32) = $Rt32.h", 19803tc_f8e23f0b, TypeMAPPING> { 19804let isPseudo = 1; 19805let isCodeGenOnly = 1; 19806} 19807def S2_pstorerffnew_pi : HInst< 19808(outs IntRegs:$Rx32), 19809(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Rt32), 19810"if (!$Pv4.new) memh($Rx32++#$Ii) = $Rt32.h", 19811tc_53559e35, TypeST>, Enc_b886fd, AddrModeRel { 19812let Inst{2-2} = 0b1; 19813let Inst{7-7} = 0b1; 19814let Inst{13-13} = 0b1; 19815let Inst{31-21} = 0b10101011011; 19816let isPredicated = 1; 19817let isPredicatedFalse = 1; 19818let addrMode = PostInc; 19819let accessSize = HalfWordAccess; 19820let isPredicatedNew = 1; 19821let mayStore = 1; 19822let CextOpcode = "S2_storerf"; 19823let BaseOpcode = "S2_storerf_pi"; 19824let Constraints = "$Rx32 = $Rx32in"; 19825} 19826def S2_pstorerft_io : HInst< 19827(outs), 19828(ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32), 19829"if ($Pv4) memh($Rs32+#$Ii) = $Rt32.h", 19830tc_f8e23f0b, TypeV2LDST>, Enc_e8c45e, AddrModeRel { 19831let Inst{2-2} = 0b0; 19832let Inst{31-21} = 0b01000000011; 19833let isPredicated = 1; 19834let addrMode = BaseImmOffset; 19835let accessSize = HalfWordAccess; 19836let mayStore = 1; 19837let CextOpcode = "S2_storerf"; 19838let InputType = "imm"; 19839let BaseOpcode = "S2_storerf_io"; 19840let isExtendable = 1; 19841let opExtendable = 2; 19842let isExtentSigned = 0; 19843let opExtentBits = 7; 19844let opExtentAlign = 1; 19845} 19846def S2_pstorerft_pi : HInst< 19847(outs IntRegs:$Rx32), 19848(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Rt32), 19849"if ($Pv4) memh($Rx32++#$Ii) = $Rt32.h", 19850tc_24b66c99, TypeST>, Enc_b886fd, AddrModeRel { 19851let Inst{2-2} = 0b0; 19852let Inst{7-7} = 0b0; 19853let Inst{13-13} = 0b1; 19854let Inst{31-21} = 0b10101011011; 19855let isPredicated = 1; 19856let addrMode = PostInc; 19857let accessSize = HalfWordAccess; 19858let mayStore = 1; 19859let CextOpcode = "S2_storerf"; 19860let BaseOpcode = "S2_storerf_pi"; 19861let Constraints = "$Rx32 = $Rx32in"; 19862} 19863def S2_pstorerft_zomap : HInst< 19864(outs), 19865(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32), 19866"if ($Pv4) memh($Rs32) = $Rt32.h", 19867tc_f8e23f0b, TypeMAPPING> { 19868let isPseudo = 1; 19869let isCodeGenOnly = 1; 19870} 19871def S2_pstorerftnew_pi : HInst< 19872(outs IntRegs:$Rx32), 19873(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Rt32), 19874"if ($Pv4.new) memh($Rx32++#$Ii) = $Rt32.h", 19875tc_53559e35, TypeST>, Enc_b886fd, AddrModeRel { 19876let Inst{2-2} = 0b0; 19877let Inst{7-7} = 0b1; 19878let Inst{13-13} = 0b1; 19879let Inst{31-21} = 0b10101011011; 19880let isPredicated = 1; 19881let addrMode = PostInc; 19882let accessSize = HalfWordAccess; 19883let isPredicatedNew = 1; 19884let mayStore = 1; 19885let CextOpcode = "S2_storerf"; 19886let BaseOpcode = "S2_storerf_pi"; 19887let Constraints = "$Rx32 = $Rx32in"; 19888} 19889def S2_pstorerhf_io : HInst< 19890(outs), 19891(ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32), 19892"if (!$Pv4) memh($Rs32+#$Ii) = $Rt32", 19893tc_f8e23f0b, TypeV2LDST>, Enc_e8c45e, AddrModeRel { 19894let Inst{2-2} = 0b0; 19895let Inst{31-21} = 0b01000100010; 19896let isPredicated = 1; 19897let isPredicatedFalse = 1; 19898let addrMode = BaseImmOffset; 19899let accessSize = HalfWordAccess; 19900let mayStore = 1; 19901let CextOpcode = "S2_storerh"; 19902let InputType = "imm"; 19903let BaseOpcode = "S2_storerh_io"; 19904let isNVStorable = 1; 19905let isExtendable = 1; 19906let opExtendable = 2; 19907let isExtentSigned = 0; 19908let opExtentBits = 7; 19909let opExtentAlign = 1; 19910} 19911def S2_pstorerhf_pi : HInst< 19912(outs IntRegs:$Rx32), 19913(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Rt32), 19914"if (!$Pv4) memh($Rx32++#$Ii) = $Rt32", 19915tc_24b66c99, TypeST>, Enc_b886fd, AddrModeRel { 19916let Inst{2-2} = 0b1; 19917let Inst{7-7} = 0b0; 19918let Inst{13-13} = 0b1; 19919let Inst{31-21} = 0b10101011010; 19920let isPredicated = 1; 19921let isPredicatedFalse = 1; 19922let addrMode = PostInc; 19923let accessSize = HalfWordAccess; 19924let mayStore = 1; 19925let BaseOpcode = "S2_storerh_pi"; 19926let isNVStorable = 1; 19927let Constraints = "$Rx32 = $Rx32in"; 19928} 19929def S2_pstorerhf_zomap : HInst< 19930(outs), 19931(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32), 19932"if (!$Pv4) memh($Rs32) = $Rt32", 19933tc_f8e23f0b, TypeMAPPING> { 19934let isPseudo = 1; 19935let isCodeGenOnly = 1; 19936} 19937def S2_pstorerhfnew_pi : HInst< 19938(outs IntRegs:$Rx32), 19939(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Rt32), 19940"if (!$Pv4.new) memh($Rx32++#$Ii) = $Rt32", 19941tc_53559e35, TypeST>, Enc_b886fd, AddrModeRel { 19942let Inst{2-2} = 0b1; 19943let Inst{7-7} = 0b1; 19944let Inst{13-13} = 0b1; 19945let Inst{31-21} = 0b10101011010; 19946let isPredicated = 1; 19947let isPredicatedFalse = 1; 19948let addrMode = PostInc; 19949let accessSize = HalfWordAccess; 19950let isPredicatedNew = 1; 19951let mayStore = 1; 19952let BaseOpcode = "S2_storerh_pi"; 19953let isNVStorable = 1; 19954let Constraints = "$Rx32 = $Rx32in"; 19955} 19956def S2_pstorerhnewf_io : HInst< 19957(outs), 19958(ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Nt8), 19959"if (!$Pv4) memh($Rs32+#$Ii) = $Nt8.new", 19960tc_8fb7ab1b, TypeV2LDST>, Enc_f44229, AddrModeRel { 19961let Inst{2-2} = 0b0; 19962let Inst{12-11} = 0b01; 19963let Inst{31-21} = 0b01000100101; 19964let isPredicated = 1; 19965let isPredicatedFalse = 1; 19966let addrMode = BaseImmOffset; 19967let accessSize = HalfWordAccess; 19968let isNVStore = 1; 19969let isNewValue = 1; 19970let isRestrictNoSlot1Store = 1; 19971let mayStore = 1; 19972let CextOpcode = "S2_storerh"; 19973let InputType = "imm"; 19974let BaseOpcode = "S2_storerh_io"; 19975let isExtendable = 1; 19976let opExtendable = 2; 19977let isExtentSigned = 0; 19978let opExtentBits = 7; 19979let opExtentAlign = 1; 19980let opNewValue = 3; 19981} 19982def S2_pstorerhnewf_pi : HInst< 19983(outs IntRegs:$Rx32), 19984(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Nt8), 19985"if (!$Pv4) memh($Rx32++#$Ii) = $Nt8.new", 19986tc_838b34ea, TypeST>, Enc_31aa6a, AddrModeRel { 19987let Inst{2-2} = 0b1; 19988let Inst{7-7} = 0b0; 19989let Inst{13-11} = 0b101; 19990let Inst{31-21} = 0b10101011101; 19991let isPredicated = 1; 19992let isPredicatedFalse = 1; 19993let addrMode = PostInc; 19994let accessSize = HalfWordAccess; 19995let isNVStore = 1; 19996let isNewValue = 1; 19997let isRestrictNoSlot1Store = 1; 19998let mayStore = 1; 19999let CextOpcode = "S2_storerh"; 20000let BaseOpcode = "S2_storerh_pi"; 20001let opNewValue = 4; 20002let Constraints = "$Rx32 = $Rx32in"; 20003} 20004def S2_pstorerhnewf_zomap : HInst< 20005(outs), 20006(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8), 20007"if (!$Pv4) memh($Rs32) = $Nt8.new", 20008tc_8fb7ab1b, TypeMAPPING> { 20009let isPseudo = 1; 20010let isCodeGenOnly = 1; 20011let opNewValue = 2; 20012} 20013def S2_pstorerhnewfnew_pi : HInst< 20014(outs IntRegs:$Rx32), 20015(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Nt8), 20016"if (!$Pv4.new) memh($Rx32++#$Ii) = $Nt8.new", 20017tc_d65dbf51, TypeST>, Enc_31aa6a, AddrModeRel { 20018let Inst{2-2} = 0b1; 20019let Inst{7-7} = 0b1; 20020let Inst{13-11} = 0b101; 20021let Inst{31-21} = 0b10101011101; 20022let isPredicated = 1; 20023let isPredicatedFalse = 1; 20024let addrMode = PostInc; 20025let accessSize = HalfWordAccess; 20026let isNVStore = 1; 20027let isPredicatedNew = 1; 20028let isNewValue = 1; 20029let isRestrictNoSlot1Store = 1; 20030let mayStore = 1; 20031let CextOpcode = "S2_storerh"; 20032let BaseOpcode = "S2_storerh_pi"; 20033let opNewValue = 4; 20034let Constraints = "$Rx32 = $Rx32in"; 20035} 20036def S2_pstorerhnewt_io : HInst< 20037(outs), 20038(ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Nt8), 20039"if ($Pv4) memh($Rs32+#$Ii) = $Nt8.new", 20040tc_8fb7ab1b, TypeV2LDST>, Enc_f44229, AddrModeRel { 20041let Inst{2-2} = 0b0; 20042let Inst{12-11} = 0b01; 20043let Inst{31-21} = 0b01000000101; 20044let isPredicated = 1; 20045let addrMode = BaseImmOffset; 20046let accessSize = HalfWordAccess; 20047let isNVStore = 1; 20048let isNewValue = 1; 20049let isRestrictNoSlot1Store = 1; 20050let mayStore = 1; 20051let CextOpcode = "S2_storerh"; 20052let InputType = "imm"; 20053let BaseOpcode = "S2_storerh_io"; 20054let isExtendable = 1; 20055let opExtendable = 2; 20056let isExtentSigned = 0; 20057let opExtentBits = 7; 20058let opExtentAlign = 1; 20059let opNewValue = 3; 20060} 20061def S2_pstorerhnewt_pi : HInst< 20062(outs IntRegs:$Rx32), 20063(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Nt8), 20064"if ($Pv4) memh($Rx32++#$Ii) = $Nt8.new", 20065tc_838b34ea, TypeST>, Enc_31aa6a, AddrModeRel { 20066let Inst{2-2} = 0b0; 20067let Inst{7-7} = 0b0; 20068let Inst{13-11} = 0b101; 20069let Inst{31-21} = 0b10101011101; 20070let isPredicated = 1; 20071let addrMode = PostInc; 20072let accessSize = HalfWordAccess; 20073let isNVStore = 1; 20074let isNewValue = 1; 20075let isRestrictNoSlot1Store = 1; 20076let mayStore = 1; 20077let CextOpcode = "S2_storerh"; 20078let BaseOpcode = "S2_storerh_pi"; 20079let opNewValue = 4; 20080let Constraints = "$Rx32 = $Rx32in"; 20081} 20082def S2_pstorerhnewt_zomap : HInst< 20083(outs), 20084(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8), 20085"if ($Pv4) memh($Rs32) = $Nt8.new", 20086tc_8fb7ab1b, TypeMAPPING> { 20087let isPseudo = 1; 20088let isCodeGenOnly = 1; 20089let opNewValue = 2; 20090} 20091def S2_pstorerhnewtnew_pi : HInst< 20092(outs IntRegs:$Rx32), 20093(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Nt8), 20094"if ($Pv4.new) memh($Rx32++#$Ii) = $Nt8.new", 20095tc_d65dbf51, TypeST>, Enc_31aa6a, AddrModeRel { 20096let Inst{2-2} = 0b0; 20097let Inst{7-7} = 0b1; 20098let Inst{13-11} = 0b101; 20099let Inst{31-21} = 0b10101011101; 20100let isPredicated = 1; 20101let addrMode = PostInc; 20102let accessSize = HalfWordAccess; 20103let isNVStore = 1; 20104let isPredicatedNew = 1; 20105let isNewValue = 1; 20106let isRestrictNoSlot1Store = 1; 20107let mayStore = 1; 20108let CextOpcode = "S2_storerh"; 20109let BaseOpcode = "S2_storerh_pi"; 20110let opNewValue = 4; 20111let Constraints = "$Rx32 = $Rx32in"; 20112} 20113def S2_pstorerht_io : HInst< 20114(outs), 20115(ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32), 20116"if ($Pv4) memh($Rs32+#$Ii) = $Rt32", 20117tc_f8e23f0b, TypeV2LDST>, Enc_e8c45e, AddrModeRel { 20118let Inst{2-2} = 0b0; 20119let Inst{31-21} = 0b01000000010; 20120let isPredicated = 1; 20121let addrMode = BaseImmOffset; 20122let accessSize = HalfWordAccess; 20123let mayStore = 1; 20124let CextOpcode = "S2_storerh"; 20125let InputType = "imm"; 20126let BaseOpcode = "S2_storerh_io"; 20127let isNVStorable = 1; 20128let isExtendable = 1; 20129let opExtendable = 2; 20130let isExtentSigned = 0; 20131let opExtentBits = 7; 20132let opExtentAlign = 1; 20133} 20134def S2_pstorerht_pi : HInst< 20135(outs IntRegs:$Rx32), 20136(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Rt32), 20137"if ($Pv4) memh($Rx32++#$Ii) = $Rt32", 20138tc_24b66c99, TypeST>, Enc_b886fd, AddrModeRel { 20139let Inst{2-2} = 0b0; 20140let Inst{7-7} = 0b0; 20141let Inst{13-13} = 0b1; 20142let Inst{31-21} = 0b10101011010; 20143let isPredicated = 1; 20144let addrMode = PostInc; 20145let accessSize = HalfWordAccess; 20146let mayStore = 1; 20147let BaseOpcode = "S2_storerh_pi"; 20148let isNVStorable = 1; 20149let Constraints = "$Rx32 = $Rx32in"; 20150} 20151def S2_pstorerht_zomap : HInst< 20152(outs), 20153(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32), 20154"if ($Pv4) memh($Rs32) = $Rt32", 20155tc_f8e23f0b, TypeMAPPING> { 20156let isPseudo = 1; 20157let isCodeGenOnly = 1; 20158} 20159def S2_pstorerhtnew_pi : HInst< 20160(outs IntRegs:$Rx32), 20161(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Rt32), 20162"if ($Pv4.new) memh($Rx32++#$Ii) = $Rt32", 20163tc_53559e35, TypeST>, Enc_b886fd, AddrModeRel { 20164let Inst{2-2} = 0b0; 20165let Inst{7-7} = 0b1; 20166let Inst{13-13} = 0b1; 20167let Inst{31-21} = 0b10101011010; 20168let isPredicated = 1; 20169let addrMode = PostInc; 20170let accessSize = HalfWordAccess; 20171let isPredicatedNew = 1; 20172let mayStore = 1; 20173let BaseOpcode = "S2_storerh_pi"; 20174let isNVStorable = 1; 20175let Constraints = "$Rx32 = $Rx32in"; 20176} 20177def S2_pstorerif_io : HInst< 20178(outs), 20179(ins PredRegs:$Pv4, IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Rt32), 20180"if (!$Pv4) memw($Rs32+#$Ii) = $Rt32", 20181tc_f8e23f0b, TypeV2LDST>, Enc_397f23, AddrModeRel { 20182let Inst{2-2} = 0b0; 20183let Inst{31-21} = 0b01000100100; 20184let isPredicated = 1; 20185let isPredicatedFalse = 1; 20186let addrMode = BaseImmOffset; 20187let accessSize = WordAccess; 20188let mayStore = 1; 20189let CextOpcode = "S2_storeri"; 20190let InputType = "imm"; 20191let BaseOpcode = "S2_storeri_io"; 20192let isNVStorable = 1; 20193let isExtendable = 1; 20194let opExtendable = 2; 20195let isExtentSigned = 0; 20196let opExtentBits = 8; 20197let opExtentAlign = 2; 20198} 20199def S2_pstorerif_pi : HInst< 20200(outs IntRegs:$Rx32), 20201(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_2Imm:$Ii, IntRegs:$Rt32), 20202"if (!$Pv4) memw($Rx32++#$Ii) = $Rt32", 20203tc_24b66c99, TypeST>, Enc_7eaeb6, AddrModeRel { 20204let Inst{2-2} = 0b1; 20205let Inst{7-7} = 0b0; 20206let Inst{13-13} = 0b1; 20207let Inst{31-21} = 0b10101011100; 20208let isPredicated = 1; 20209let isPredicatedFalse = 1; 20210let addrMode = PostInc; 20211let accessSize = WordAccess; 20212let mayStore = 1; 20213let BaseOpcode = "S2_storeri_pi"; 20214let isNVStorable = 1; 20215let Constraints = "$Rx32 = $Rx32in"; 20216} 20217def S2_pstorerif_zomap : HInst< 20218(outs), 20219(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32), 20220"if (!$Pv4) memw($Rs32) = $Rt32", 20221tc_f8e23f0b, TypeMAPPING> { 20222let isPseudo = 1; 20223let isCodeGenOnly = 1; 20224} 20225def S2_pstorerifnew_pi : HInst< 20226(outs IntRegs:$Rx32), 20227(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_2Imm:$Ii, IntRegs:$Rt32), 20228"if (!$Pv4.new) memw($Rx32++#$Ii) = $Rt32", 20229tc_53559e35, TypeST>, Enc_7eaeb6, AddrModeRel { 20230let Inst{2-2} = 0b1; 20231let Inst{7-7} = 0b1; 20232let Inst{13-13} = 0b1; 20233let Inst{31-21} = 0b10101011100; 20234let isPredicated = 1; 20235let isPredicatedFalse = 1; 20236let addrMode = PostInc; 20237let accessSize = WordAccess; 20238let isPredicatedNew = 1; 20239let mayStore = 1; 20240let CextOpcode = "S2_storeri"; 20241let BaseOpcode = "S2_storeri_pi"; 20242let isNVStorable = 1; 20243let Constraints = "$Rx32 = $Rx32in"; 20244} 20245def S2_pstorerinewf_io : HInst< 20246(outs), 20247(ins PredRegs:$Pv4, IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Nt8), 20248"if (!$Pv4) memw($Rs32+#$Ii) = $Nt8.new", 20249tc_8fb7ab1b, TypeV2LDST>, Enc_8dbdfe, AddrModeRel { 20250let Inst{2-2} = 0b0; 20251let Inst{12-11} = 0b10; 20252let Inst{31-21} = 0b01000100101; 20253let isPredicated = 1; 20254let isPredicatedFalse = 1; 20255let addrMode = BaseImmOffset; 20256let accessSize = WordAccess; 20257let isNVStore = 1; 20258let isNewValue = 1; 20259let isRestrictNoSlot1Store = 1; 20260let mayStore = 1; 20261let CextOpcode = "S2_storeri"; 20262let InputType = "imm"; 20263let BaseOpcode = "S2_storeri_io"; 20264let isExtendable = 1; 20265let opExtendable = 2; 20266let isExtentSigned = 0; 20267let opExtentBits = 8; 20268let opExtentAlign = 2; 20269let opNewValue = 3; 20270} 20271def S2_pstorerinewf_pi : HInst< 20272(outs IntRegs:$Rx32), 20273(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_2Imm:$Ii, IntRegs:$Nt8), 20274"if (!$Pv4) memw($Rx32++#$Ii) = $Nt8.new", 20275tc_838b34ea, TypeST>, Enc_65f095, AddrModeRel { 20276let Inst{2-2} = 0b1; 20277let Inst{7-7} = 0b0; 20278let Inst{13-11} = 0b110; 20279let Inst{31-21} = 0b10101011101; 20280let isPredicated = 1; 20281let isPredicatedFalse = 1; 20282let addrMode = PostInc; 20283let accessSize = WordAccess; 20284let isNVStore = 1; 20285let isNewValue = 1; 20286let isRestrictNoSlot1Store = 1; 20287let mayStore = 1; 20288let CextOpcode = "S2_storeri"; 20289let BaseOpcode = "S2_storeri_pi"; 20290let opNewValue = 4; 20291let Constraints = "$Rx32 = $Rx32in"; 20292} 20293def S2_pstorerinewf_zomap : HInst< 20294(outs), 20295(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8), 20296"if (!$Pv4) memw($Rs32) = $Nt8.new", 20297tc_8fb7ab1b, TypeMAPPING> { 20298let isPseudo = 1; 20299let isCodeGenOnly = 1; 20300let opNewValue = 2; 20301} 20302def S2_pstorerinewfnew_pi : HInst< 20303(outs IntRegs:$Rx32), 20304(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_2Imm:$Ii, IntRegs:$Nt8), 20305"if (!$Pv4.new) memw($Rx32++#$Ii) = $Nt8.new", 20306tc_d65dbf51, TypeST>, Enc_65f095, AddrModeRel { 20307let Inst{2-2} = 0b1; 20308let Inst{7-7} = 0b1; 20309let Inst{13-11} = 0b110; 20310let Inst{31-21} = 0b10101011101; 20311let isPredicated = 1; 20312let isPredicatedFalse = 1; 20313let addrMode = PostInc; 20314let accessSize = WordAccess; 20315let isNVStore = 1; 20316let isPredicatedNew = 1; 20317let isNewValue = 1; 20318let isRestrictNoSlot1Store = 1; 20319let mayStore = 1; 20320let CextOpcode = "S2_storeri"; 20321let BaseOpcode = "S2_storeri_pi"; 20322let opNewValue = 4; 20323let Constraints = "$Rx32 = $Rx32in"; 20324} 20325def S2_pstorerinewt_io : HInst< 20326(outs), 20327(ins PredRegs:$Pv4, IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Nt8), 20328"if ($Pv4) memw($Rs32+#$Ii) = $Nt8.new", 20329tc_8fb7ab1b, TypeV2LDST>, Enc_8dbdfe, AddrModeRel { 20330let Inst{2-2} = 0b0; 20331let Inst{12-11} = 0b10; 20332let Inst{31-21} = 0b01000000101; 20333let isPredicated = 1; 20334let addrMode = BaseImmOffset; 20335let accessSize = WordAccess; 20336let isNVStore = 1; 20337let isNewValue = 1; 20338let isRestrictNoSlot1Store = 1; 20339let mayStore = 1; 20340let CextOpcode = "S2_storeri"; 20341let InputType = "imm"; 20342let BaseOpcode = "S2_storeri_io"; 20343let isExtendable = 1; 20344let opExtendable = 2; 20345let isExtentSigned = 0; 20346let opExtentBits = 8; 20347let opExtentAlign = 2; 20348let opNewValue = 3; 20349} 20350def S2_pstorerinewt_pi : HInst< 20351(outs IntRegs:$Rx32), 20352(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_2Imm:$Ii, IntRegs:$Nt8), 20353"if ($Pv4) memw($Rx32++#$Ii) = $Nt8.new", 20354tc_838b34ea, TypeST>, Enc_65f095, AddrModeRel { 20355let Inst{2-2} = 0b0; 20356let Inst{7-7} = 0b0; 20357let Inst{13-11} = 0b110; 20358let Inst{31-21} = 0b10101011101; 20359let isPredicated = 1; 20360let addrMode = PostInc; 20361let accessSize = WordAccess; 20362let isNVStore = 1; 20363let isNewValue = 1; 20364let isRestrictNoSlot1Store = 1; 20365let mayStore = 1; 20366let CextOpcode = "S2_storeri"; 20367let BaseOpcode = "S2_storeri_pi"; 20368let opNewValue = 4; 20369let Constraints = "$Rx32 = $Rx32in"; 20370} 20371def S2_pstorerinewt_zomap : HInst< 20372(outs), 20373(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8), 20374"if ($Pv4) memw($Rs32) = $Nt8.new", 20375tc_8fb7ab1b, TypeMAPPING> { 20376let isPseudo = 1; 20377let isCodeGenOnly = 1; 20378let opNewValue = 2; 20379} 20380def S2_pstorerinewtnew_pi : HInst< 20381(outs IntRegs:$Rx32), 20382(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_2Imm:$Ii, IntRegs:$Nt8), 20383"if ($Pv4.new) memw($Rx32++#$Ii) = $Nt8.new", 20384tc_d65dbf51, TypeST>, Enc_65f095, AddrModeRel { 20385let Inst{2-2} = 0b0; 20386let Inst{7-7} = 0b1; 20387let Inst{13-11} = 0b110; 20388let Inst{31-21} = 0b10101011101; 20389let isPredicated = 1; 20390let addrMode = PostInc; 20391let accessSize = WordAccess; 20392let isNVStore = 1; 20393let isPredicatedNew = 1; 20394let isNewValue = 1; 20395let isRestrictNoSlot1Store = 1; 20396let mayStore = 1; 20397let CextOpcode = "S2_storeri"; 20398let BaseOpcode = "S2_storeri_pi"; 20399let opNewValue = 4; 20400let Constraints = "$Rx32 = $Rx32in"; 20401} 20402def S2_pstorerit_io : HInst< 20403(outs), 20404(ins PredRegs:$Pv4, IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Rt32), 20405"if ($Pv4) memw($Rs32+#$Ii) = $Rt32", 20406tc_f8e23f0b, TypeV2LDST>, Enc_397f23, AddrModeRel { 20407let Inst{2-2} = 0b0; 20408let Inst{31-21} = 0b01000000100; 20409let isPredicated = 1; 20410let addrMode = BaseImmOffset; 20411let accessSize = WordAccess; 20412let mayStore = 1; 20413let CextOpcode = "S2_storeri"; 20414let InputType = "imm"; 20415let BaseOpcode = "S2_storeri_io"; 20416let isNVStorable = 1; 20417let isExtendable = 1; 20418let opExtendable = 2; 20419let isExtentSigned = 0; 20420let opExtentBits = 8; 20421let opExtentAlign = 2; 20422} 20423def S2_pstorerit_pi : HInst< 20424(outs IntRegs:$Rx32), 20425(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_2Imm:$Ii, IntRegs:$Rt32), 20426"if ($Pv4) memw($Rx32++#$Ii) = $Rt32", 20427tc_24b66c99, TypeST>, Enc_7eaeb6, AddrModeRel { 20428let Inst{2-2} = 0b0; 20429let Inst{7-7} = 0b0; 20430let Inst{13-13} = 0b1; 20431let Inst{31-21} = 0b10101011100; 20432let isPredicated = 1; 20433let addrMode = PostInc; 20434let accessSize = WordAccess; 20435let mayStore = 1; 20436let BaseOpcode = "S2_storeri_pi"; 20437let isNVStorable = 1; 20438let Constraints = "$Rx32 = $Rx32in"; 20439} 20440def S2_pstorerit_zomap : HInst< 20441(outs), 20442(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32), 20443"if ($Pv4) memw($Rs32) = $Rt32", 20444tc_f8e23f0b, TypeMAPPING> { 20445let isPseudo = 1; 20446let isCodeGenOnly = 1; 20447} 20448def S2_pstoreritnew_pi : HInst< 20449(outs IntRegs:$Rx32), 20450(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_2Imm:$Ii, IntRegs:$Rt32), 20451"if ($Pv4.new) memw($Rx32++#$Ii) = $Rt32", 20452tc_53559e35, TypeST>, Enc_7eaeb6, AddrModeRel { 20453let Inst{2-2} = 0b0; 20454let Inst{7-7} = 0b1; 20455let Inst{13-13} = 0b1; 20456let Inst{31-21} = 0b10101011100; 20457let isPredicated = 1; 20458let addrMode = PostInc; 20459let accessSize = WordAccess; 20460let isPredicatedNew = 1; 20461let mayStore = 1; 20462let BaseOpcode = "S2_storeri_pi"; 20463let isNVStorable = 1; 20464let Constraints = "$Rx32 = $Rx32in"; 20465} 20466def S2_setbit_i : HInst< 20467(outs IntRegs:$Rd32), 20468(ins IntRegs:$Rs32, u5_0Imm:$Ii), 20469"$Rd32 = setbit($Rs32,#$Ii)", 20470tc_946df596, TypeS_2op>, Enc_a05677 { 20471let Inst{7-5} = 0b000; 20472let Inst{13-13} = 0b0; 20473let Inst{31-21} = 0b10001100110; 20474let hasNewValue = 1; 20475let opNewValue = 0; 20476} 20477def S2_setbit_r : HInst< 20478(outs IntRegs:$Rd32), 20479(ins IntRegs:$Rs32, IntRegs:$Rt32), 20480"$Rd32 = setbit($Rs32,$Rt32)", 20481tc_946df596, TypeS_3op>, Enc_5ab2be { 20482let Inst{7-5} = 0b000; 20483let Inst{13-13} = 0b0; 20484let Inst{31-21} = 0b11000110100; 20485let hasNewValue = 1; 20486let opNewValue = 0; 20487} 20488def S2_shuffeb : HInst< 20489(outs DoubleRegs:$Rdd32), 20490(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 20491"$Rdd32 = shuffeb($Rss32,$Rtt32)", 20492tc_946df596, TypeS_3op>, Enc_a56825 { 20493let Inst{7-5} = 0b010; 20494let Inst{13-13} = 0b0; 20495let Inst{31-21} = 0b11000001000; 20496} 20497def S2_shuffeh : HInst< 20498(outs DoubleRegs:$Rdd32), 20499(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 20500"$Rdd32 = shuffeh($Rss32,$Rtt32)", 20501tc_946df596, TypeS_3op>, Enc_a56825 { 20502let Inst{7-5} = 0b110; 20503let Inst{13-13} = 0b0; 20504let Inst{31-21} = 0b11000001000; 20505} 20506def S2_shuffob : HInst< 20507(outs DoubleRegs:$Rdd32), 20508(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), 20509"$Rdd32 = shuffob($Rtt32,$Rss32)", 20510tc_946df596, TypeS_3op>, Enc_ea23e4 { 20511let Inst{7-5} = 0b100; 20512let Inst{13-13} = 0b0; 20513let Inst{31-21} = 0b11000001000; 20514} 20515def S2_shuffoh : HInst< 20516(outs DoubleRegs:$Rdd32), 20517(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), 20518"$Rdd32 = shuffoh($Rtt32,$Rss32)", 20519tc_946df596, TypeS_3op>, Enc_ea23e4 { 20520let Inst{7-5} = 0b000; 20521let Inst{13-13} = 0b0; 20522let Inst{31-21} = 0b11000001100; 20523} 20524def S2_storerb_io : HInst< 20525(outs), 20526(ins IntRegs:$Rs32, s32_0Imm:$Ii, IntRegs:$Rt32), 20527"memb($Rs32+#$Ii) = $Rt32", 20528tc_30b9bb4a, TypeST>, Enc_448f7f, AddrModeRel, PostInc_BaseImm { 20529let Inst{24-21} = 0b1000; 20530let Inst{31-27} = 0b10100; 20531let addrMode = BaseImmOffset; 20532let accessSize = ByteAccess; 20533let mayStore = 1; 20534let CextOpcode = "S2_storerb"; 20535let InputType = "imm"; 20536let BaseOpcode = "S2_storerb_io"; 20537let isPredicable = 1; 20538let isNVStorable = 1; 20539let isExtendable = 1; 20540let opExtendable = 1; 20541let isExtentSigned = 1; 20542let opExtentBits = 11; 20543let opExtentAlign = 0; 20544} 20545def S2_storerb_pbr : HInst< 20546(outs IntRegs:$Rx32), 20547(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32), 20548"memb($Rx32++$Mu2:brev) = $Rt32", 20549tc_da97ee82, TypeST>, Enc_d5c73f, AddrModeRel { 20550let Inst{7-0} = 0b00000000; 20551let Inst{31-21} = 0b10101111000; 20552let addrMode = PostInc; 20553let accessSize = ByteAccess; 20554let mayStore = 1; 20555let BaseOpcode = "S2_storerb_pbr"; 20556let isNVStorable = 1; 20557let Constraints = "$Rx32 = $Rx32in"; 20558} 20559def S2_storerb_pci : HInst< 20560(outs IntRegs:$Rx32), 20561(ins IntRegs:$Rx32in, s4_0Imm:$Ii, ModRegs:$Mu2, IntRegs:$Rt32), 20562"memb($Rx32++#$Ii:circ($Mu2)) = $Rt32", 20563tc_e86aa961, TypeST>, Enc_b15941, AddrModeRel { 20564let Inst{2-0} = 0b000; 20565let Inst{7-7} = 0b0; 20566let Inst{31-21} = 0b10101001000; 20567let addrMode = PostInc; 20568let accessSize = ByteAccess; 20569let mayStore = 1; 20570let Uses = [CS]; 20571let BaseOpcode = "S2_storerb_pci"; 20572let isNVStorable = 1; 20573let Constraints = "$Rx32 = $Rx32in"; 20574} 20575def S2_storerb_pcr : HInst< 20576(outs IntRegs:$Rx32), 20577(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32), 20578"memb($Rx32++I:circ($Mu2)) = $Rt32", 20579tc_da97ee82, TypeST>, Enc_d5c73f, AddrModeRel { 20580let Inst{7-0} = 0b00000010; 20581let Inst{31-21} = 0b10101001000; 20582let addrMode = PostInc; 20583let accessSize = ByteAccess; 20584let mayStore = 1; 20585let Uses = [CS]; 20586let BaseOpcode = "S2_storerb_pcr"; 20587let isNVStorable = 1; 20588let Constraints = "$Rx32 = $Rx32in"; 20589} 20590def S2_storerb_pi : HInst< 20591(outs IntRegs:$Rx32), 20592(ins IntRegs:$Rx32in, s4_0Imm:$Ii, IntRegs:$Rt32), 20593"memb($Rx32++#$Ii) = $Rt32", 20594tc_da97ee82, TypeST>, Enc_10bc21, AddrModeRel, PostInc_BaseImm { 20595let Inst{2-0} = 0b000; 20596let Inst{7-7} = 0b0; 20597let Inst{13-13} = 0b0; 20598let Inst{31-21} = 0b10101011000; 20599let addrMode = PostInc; 20600let accessSize = ByteAccess; 20601let mayStore = 1; 20602let CextOpcode = "S2_storerb"; 20603let BaseOpcode = "S2_storerb_pi"; 20604let isPredicable = 1; 20605let isNVStorable = 1; 20606let Constraints = "$Rx32 = $Rx32in"; 20607} 20608def S2_storerb_pr : HInst< 20609(outs IntRegs:$Rx32), 20610(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32), 20611"memb($Rx32++$Mu2) = $Rt32", 20612tc_da97ee82, TypeST>, Enc_d5c73f { 20613let Inst{7-0} = 0b00000000; 20614let Inst{31-21} = 0b10101101000; 20615let addrMode = PostInc; 20616let accessSize = ByteAccess; 20617let mayStore = 1; 20618let isNVStorable = 1; 20619let Constraints = "$Rx32 = $Rx32in"; 20620} 20621def S2_storerb_zomap : HInst< 20622(outs), 20623(ins IntRegs:$Rs32, IntRegs:$Rt32), 20624"memb($Rs32) = $Rt32", 20625tc_30b9bb4a, TypeMAPPING> { 20626let isPseudo = 1; 20627let isCodeGenOnly = 1; 20628} 20629def S2_storerbgp : HInst< 20630(outs), 20631(ins u32_0Imm:$Ii, IntRegs:$Rt32), 20632"memb(gp+#$Ii) = $Rt32", 20633tc_0371abea, TypeV2LDST>, Enc_1b64fb, AddrModeRel { 20634let Inst{24-21} = 0b0000; 20635let Inst{31-27} = 0b01001; 20636let accessSize = ByteAccess; 20637let mayStore = 1; 20638let Uses = [GP]; 20639let BaseOpcode = "S2_storerbabs"; 20640let isPredicable = 1; 20641let isNVStorable = 1; 20642let opExtendable = 0; 20643let isExtentSigned = 0; 20644let opExtentBits = 16; 20645let opExtentAlign = 0; 20646} 20647def S2_storerbnew_io : HInst< 20648(outs), 20649(ins IntRegs:$Rs32, s32_0Imm:$Ii, IntRegs:$Nt8), 20650"memb($Rs32+#$Ii) = $Nt8.new", 20651tc_be9602ff, TypeST>, Enc_4df4e9, AddrModeRel { 20652let Inst{12-11} = 0b00; 20653let Inst{24-21} = 0b1101; 20654let Inst{31-27} = 0b10100; 20655let addrMode = BaseImmOffset; 20656let accessSize = ByteAccess; 20657let isNVStore = 1; 20658let isNewValue = 1; 20659let isRestrictNoSlot1Store = 1; 20660let mayStore = 1; 20661let CextOpcode = "S2_storerb"; 20662let InputType = "imm"; 20663let BaseOpcode = "S2_storerb_io"; 20664let isPredicable = 1; 20665let isExtendable = 1; 20666let opExtendable = 1; 20667let isExtentSigned = 1; 20668let opExtentBits = 11; 20669let opExtentAlign = 0; 20670let opNewValue = 2; 20671} 20672def S2_storerbnew_pbr : HInst< 20673(outs IntRegs:$Rx32), 20674(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Nt8), 20675"memb($Rx32++$Mu2:brev) = $Nt8.new", 20676tc_c79a189f, TypeST>, Enc_8dbe85, AddrModeRel { 20677let Inst{7-0} = 0b00000000; 20678let Inst{12-11} = 0b00; 20679let Inst{31-21} = 0b10101111101; 20680let addrMode = PostInc; 20681let accessSize = ByteAccess; 20682let isNVStore = 1; 20683let isNewValue = 1; 20684let isRestrictNoSlot1Store = 1; 20685let mayStore = 1; 20686let BaseOpcode = "S2_storerb_pbr"; 20687let opNewValue = 3; 20688let Constraints = "$Rx32 = $Rx32in"; 20689} 20690def S2_storerbnew_pci : HInst< 20691(outs IntRegs:$Rx32), 20692(ins IntRegs:$Rx32in, s4_0Imm:$Ii, ModRegs:$Mu2, IntRegs:$Nt8), 20693"memb($Rx32++#$Ii:circ($Mu2)) = $Nt8.new", 20694tc_d5c0729a, TypeST>, Enc_96ce4f, AddrModeRel { 20695let Inst{2-0} = 0b000; 20696let Inst{7-7} = 0b0; 20697let Inst{12-11} = 0b00; 20698let Inst{31-21} = 0b10101001101; 20699let addrMode = PostInc; 20700let accessSize = ByteAccess; 20701let isNVStore = 1; 20702let isNewValue = 1; 20703let isRestrictNoSlot1Store = 1; 20704let mayStore = 1; 20705let Uses = [CS]; 20706let BaseOpcode = "S2_storerb_pci"; 20707let opNewValue = 4; 20708let Constraints = "$Rx32 = $Rx32in"; 20709} 20710def S2_storerbnew_pcr : HInst< 20711(outs IntRegs:$Rx32), 20712(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Nt8), 20713"memb($Rx32++I:circ($Mu2)) = $Nt8.new", 20714tc_c79a189f, TypeST>, Enc_8dbe85, AddrModeRel { 20715let Inst{7-0} = 0b00000010; 20716let Inst{12-11} = 0b00; 20717let Inst{31-21} = 0b10101001101; 20718let addrMode = PostInc; 20719let accessSize = ByteAccess; 20720let isNVStore = 1; 20721let isNewValue = 1; 20722let isRestrictNoSlot1Store = 1; 20723let mayStore = 1; 20724let Uses = [CS]; 20725let BaseOpcode = "S2_storerb_pcr"; 20726let opNewValue = 3; 20727let Constraints = "$Rx32 = $Rx32in"; 20728} 20729def S2_storerbnew_pi : HInst< 20730(outs IntRegs:$Rx32), 20731(ins IntRegs:$Rx32in, s4_0Imm:$Ii, IntRegs:$Nt8), 20732"memb($Rx32++#$Ii) = $Nt8.new", 20733tc_c79a189f, TypeST>, Enc_c7cd90, AddrModeRel { 20734let Inst{2-0} = 0b000; 20735let Inst{7-7} = 0b0; 20736let Inst{13-11} = 0b000; 20737let Inst{31-21} = 0b10101011101; 20738let addrMode = PostInc; 20739let accessSize = ByteAccess; 20740let isNVStore = 1; 20741let isNewValue = 1; 20742let isRestrictNoSlot1Store = 1; 20743let mayStore = 1; 20744let BaseOpcode = "S2_storerb_pi"; 20745let isPredicable = 1; 20746let isNVStorable = 1; 20747let opNewValue = 3; 20748let Constraints = "$Rx32 = $Rx32in"; 20749} 20750def S2_storerbnew_pr : HInst< 20751(outs IntRegs:$Rx32), 20752(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Nt8), 20753"memb($Rx32++$Mu2) = $Nt8.new", 20754tc_c79a189f, TypeST>, Enc_8dbe85 { 20755let Inst{7-0} = 0b00000000; 20756let Inst{12-11} = 0b00; 20757let Inst{31-21} = 0b10101101101; 20758let addrMode = PostInc; 20759let accessSize = ByteAccess; 20760let isNVStore = 1; 20761let isNewValue = 1; 20762let isRestrictNoSlot1Store = 1; 20763let mayStore = 1; 20764let opNewValue = 3; 20765let Constraints = "$Rx32 = $Rx32in"; 20766} 20767def S2_storerbnew_zomap : HInst< 20768(outs), 20769(ins IntRegs:$Rs32, IntRegs:$Nt8), 20770"memb($Rs32) = $Nt8.new", 20771tc_be9602ff, TypeMAPPING> { 20772let isPseudo = 1; 20773let isCodeGenOnly = 1; 20774let opNewValue = 1; 20775} 20776def S2_storerbnewgp : HInst< 20777(outs), 20778(ins u32_0Imm:$Ii, IntRegs:$Nt8), 20779"memb(gp+#$Ii) = $Nt8.new", 20780tc_5bf126a6, TypeV2LDST>, Enc_ad1831, AddrModeRel { 20781let Inst{12-11} = 0b00; 20782let Inst{24-21} = 0b0101; 20783let Inst{31-27} = 0b01001; 20784let accessSize = ByteAccess; 20785let isNVStore = 1; 20786let isNewValue = 1; 20787let isRestrictNoSlot1Store = 1; 20788let mayStore = 1; 20789let Uses = [GP]; 20790let BaseOpcode = "S2_storerbabs"; 20791let isPredicable = 1; 20792let opExtendable = 0; 20793let isExtentSigned = 0; 20794let opExtentBits = 16; 20795let opExtentAlign = 0; 20796let opNewValue = 1; 20797} 20798def S2_storerd_io : HInst< 20799(outs), 20800(ins IntRegs:$Rs32, s29_3Imm:$Ii, DoubleRegs:$Rtt32), 20801"memd($Rs32+#$Ii) = $Rtt32", 20802tc_30b9bb4a, TypeST>, Enc_ce6828, AddrModeRel, PostInc_BaseImm { 20803let Inst{24-21} = 0b1110; 20804let Inst{31-27} = 0b10100; 20805let addrMode = BaseImmOffset; 20806let accessSize = DoubleWordAccess; 20807let mayStore = 1; 20808let CextOpcode = "S2_storerd"; 20809let InputType = "imm"; 20810let BaseOpcode = "S2_storerd_io"; 20811let isPredicable = 1; 20812let isExtendable = 1; 20813let opExtendable = 1; 20814let isExtentSigned = 1; 20815let opExtentBits = 14; 20816let opExtentAlign = 3; 20817} 20818def S2_storerd_pbr : HInst< 20819(outs IntRegs:$Rx32), 20820(ins IntRegs:$Rx32in, ModRegs:$Mu2, DoubleRegs:$Rtt32), 20821"memd($Rx32++$Mu2:brev) = $Rtt32", 20822tc_da97ee82, TypeST>, Enc_928ca1 { 20823let Inst{7-0} = 0b00000000; 20824let Inst{31-21} = 0b10101111110; 20825let addrMode = PostInc; 20826let accessSize = DoubleWordAccess; 20827let mayStore = 1; 20828let Constraints = "$Rx32 = $Rx32in"; 20829} 20830def S2_storerd_pci : HInst< 20831(outs IntRegs:$Rx32), 20832(ins IntRegs:$Rx32in, s4_3Imm:$Ii, ModRegs:$Mu2, DoubleRegs:$Rtt32), 20833"memd($Rx32++#$Ii:circ($Mu2)) = $Rtt32", 20834tc_e86aa961, TypeST>, Enc_395cc4 { 20835let Inst{2-0} = 0b000; 20836let Inst{7-7} = 0b0; 20837let Inst{31-21} = 0b10101001110; 20838let addrMode = PostInc; 20839let accessSize = DoubleWordAccess; 20840let mayStore = 1; 20841let Uses = [CS]; 20842let Constraints = "$Rx32 = $Rx32in"; 20843} 20844def S2_storerd_pcr : HInst< 20845(outs IntRegs:$Rx32), 20846(ins IntRegs:$Rx32in, ModRegs:$Mu2, DoubleRegs:$Rtt32), 20847"memd($Rx32++I:circ($Mu2)) = $Rtt32", 20848tc_da97ee82, TypeST>, Enc_928ca1 { 20849let Inst{7-0} = 0b00000010; 20850let Inst{31-21} = 0b10101001110; 20851let addrMode = PostInc; 20852let accessSize = DoubleWordAccess; 20853let mayStore = 1; 20854let Uses = [CS]; 20855let Constraints = "$Rx32 = $Rx32in"; 20856} 20857def S2_storerd_pi : HInst< 20858(outs IntRegs:$Rx32), 20859(ins IntRegs:$Rx32in, s4_3Imm:$Ii, DoubleRegs:$Rtt32), 20860"memd($Rx32++#$Ii) = $Rtt32", 20861tc_da97ee82, TypeST>, Enc_85bf58, AddrModeRel, PostInc_BaseImm { 20862let Inst{2-0} = 0b000; 20863let Inst{7-7} = 0b0; 20864let Inst{13-13} = 0b0; 20865let Inst{31-21} = 0b10101011110; 20866let addrMode = PostInc; 20867let accessSize = DoubleWordAccess; 20868let mayStore = 1; 20869let CextOpcode = "S2_storerd"; 20870let BaseOpcode = "S2_storerd_pi"; 20871let isPredicable = 1; 20872let Constraints = "$Rx32 = $Rx32in"; 20873} 20874def S2_storerd_pr : HInst< 20875(outs IntRegs:$Rx32), 20876(ins IntRegs:$Rx32in, ModRegs:$Mu2, DoubleRegs:$Rtt32), 20877"memd($Rx32++$Mu2) = $Rtt32", 20878tc_da97ee82, TypeST>, Enc_928ca1 { 20879let Inst{7-0} = 0b00000000; 20880let Inst{31-21} = 0b10101101110; 20881let addrMode = PostInc; 20882let accessSize = DoubleWordAccess; 20883let mayStore = 1; 20884let Constraints = "$Rx32 = $Rx32in"; 20885} 20886def S2_storerd_zomap : HInst< 20887(outs), 20888(ins IntRegs:$Rs32, DoubleRegs:$Rtt32), 20889"memd($Rs32) = $Rtt32", 20890tc_30b9bb4a, TypeMAPPING> { 20891let isPseudo = 1; 20892let isCodeGenOnly = 1; 20893} 20894def S2_storerdgp : HInst< 20895(outs), 20896(ins u29_3Imm:$Ii, DoubleRegs:$Rtt32), 20897"memd(gp+#$Ii) = $Rtt32", 20898tc_0371abea, TypeV2LDST>, Enc_5c124a, AddrModeRel { 20899let Inst{24-21} = 0b0110; 20900let Inst{31-27} = 0b01001; 20901let accessSize = DoubleWordAccess; 20902let mayStore = 1; 20903let Uses = [GP]; 20904let BaseOpcode = "S2_storerdabs"; 20905let isPredicable = 1; 20906let opExtendable = 0; 20907let isExtentSigned = 0; 20908let opExtentBits = 19; 20909let opExtentAlign = 3; 20910} 20911def S2_storerf_io : HInst< 20912(outs), 20913(ins IntRegs:$Rs32, s31_1Imm:$Ii, IntRegs:$Rt32), 20914"memh($Rs32+#$Ii) = $Rt32.h", 20915tc_30b9bb4a, TypeST>, Enc_e957fb, AddrModeRel, PostInc_BaseImm { 20916let Inst{24-21} = 0b1011; 20917let Inst{31-27} = 0b10100; 20918let addrMode = BaseImmOffset; 20919let accessSize = HalfWordAccess; 20920let mayStore = 1; 20921let CextOpcode = "S2_storerf"; 20922let InputType = "imm"; 20923let BaseOpcode = "S2_storerf_io"; 20924let isPredicable = 1; 20925let isExtendable = 1; 20926let opExtendable = 1; 20927let isExtentSigned = 1; 20928let opExtentBits = 12; 20929let opExtentAlign = 1; 20930} 20931def S2_storerf_pbr : HInst< 20932(outs IntRegs:$Rx32), 20933(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32), 20934"memh($Rx32++$Mu2:brev) = $Rt32.h", 20935tc_da97ee82, TypeST>, Enc_d5c73f { 20936let Inst{7-0} = 0b00000000; 20937let Inst{31-21} = 0b10101111011; 20938let addrMode = PostInc; 20939let accessSize = HalfWordAccess; 20940let mayStore = 1; 20941let Constraints = "$Rx32 = $Rx32in"; 20942} 20943def S2_storerf_pci : HInst< 20944(outs IntRegs:$Rx32), 20945(ins IntRegs:$Rx32in, s4_1Imm:$Ii, ModRegs:$Mu2, IntRegs:$Rt32), 20946"memh($Rx32++#$Ii:circ($Mu2)) = $Rt32.h", 20947tc_e86aa961, TypeST>, Enc_935d9b { 20948let Inst{2-0} = 0b000; 20949let Inst{7-7} = 0b0; 20950let Inst{31-21} = 0b10101001011; 20951let addrMode = PostInc; 20952let accessSize = HalfWordAccess; 20953let mayStore = 1; 20954let Uses = [CS]; 20955let Constraints = "$Rx32 = $Rx32in"; 20956} 20957def S2_storerf_pcr : HInst< 20958(outs IntRegs:$Rx32), 20959(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32), 20960"memh($Rx32++I:circ($Mu2)) = $Rt32.h", 20961tc_da97ee82, TypeST>, Enc_d5c73f { 20962let Inst{7-0} = 0b00000010; 20963let Inst{31-21} = 0b10101001011; 20964let addrMode = PostInc; 20965let accessSize = HalfWordAccess; 20966let mayStore = 1; 20967let Uses = [CS]; 20968let Constraints = "$Rx32 = $Rx32in"; 20969} 20970def S2_storerf_pi : HInst< 20971(outs IntRegs:$Rx32), 20972(ins IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Rt32), 20973"memh($Rx32++#$Ii) = $Rt32.h", 20974tc_da97ee82, TypeST>, Enc_052c7d, AddrModeRel, PostInc_BaseImm { 20975let Inst{2-0} = 0b000; 20976let Inst{7-7} = 0b0; 20977let Inst{13-13} = 0b0; 20978let Inst{31-21} = 0b10101011011; 20979let addrMode = PostInc; 20980let accessSize = HalfWordAccess; 20981let mayStore = 1; 20982let CextOpcode = "S2_storerf"; 20983let BaseOpcode = "S2_storerf_pi"; 20984let isPredicable = 1; 20985let Constraints = "$Rx32 = $Rx32in"; 20986} 20987def S2_storerf_pr : HInst< 20988(outs IntRegs:$Rx32), 20989(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32), 20990"memh($Rx32++$Mu2) = $Rt32.h", 20991tc_da97ee82, TypeST>, Enc_d5c73f { 20992let Inst{7-0} = 0b00000000; 20993let Inst{31-21} = 0b10101101011; 20994let addrMode = PostInc; 20995let accessSize = HalfWordAccess; 20996let mayStore = 1; 20997let Constraints = "$Rx32 = $Rx32in"; 20998} 20999def S2_storerf_zomap : HInst< 21000(outs), 21001(ins IntRegs:$Rs32, IntRegs:$Rt32), 21002"memh($Rs32) = $Rt32.h", 21003tc_30b9bb4a, TypeMAPPING> { 21004let isPseudo = 1; 21005let isCodeGenOnly = 1; 21006} 21007def S2_storerfgp : HInst< 21008(outs), 21009(ins u31_1Imm:$Ii, IntRegs:$Rt32), 21010"memh(gp+#$Ii) = $Rt32.h", 21011tc_0371abea, TypeV2LDST>, Enc_fda92c, AddrModeRel { 21012let Inst{24-21} = 0b0011; 21013let Inst{31-27} = 0b01001; 21014let accessSize = HalfWordAccess; 21015let mayStore = 1; 21016let Uses = [GP]; 21017let BaseOpcode = "S2_storerfabs"; 21018let isPredicable = 1; 21019let opExtendable = 0; 21020let isExtentSigned = 0; 21021let opExtentBits = 17; 21022let opExtentAlign = 1; 21023} 21024def S2_storerh_io : HInst< 21025(outs), 21026(ins IntRegs:$Rs32, s31_1Imm:$Ii, IntRegs:$Rt32), 21027"memh($Rs32+#$Ii) = $Rt32", 21028tc_30b9bb4a, TypeST>, Enc_e957fb, AddrModeRel, PostInc_BaseImm { 21029let Inst{24-21} = 0b1010; 21030let Inst{31-27} = 0b10100; 21031let addrMode = BaseImmOffset; 21032let accessSize = HalfWordAccess; 21033let mayStore = 1; 21034let CextOpcode = "S2_storerh"; 21035let InputType = "imm"; 21036let BaseOpcode = "S2_storerh_io"; 21037let isPredicable = 1; 21038let isNVStorable = 1; 21039let isExtendable = 1; 21040let opExtendable = 1; 21041let isExtentSigned = 1; 21042let opExtentBits = 12; 21043let opExtentAlign = 1; 21044} 21045def S2_storerh_pbr : HInst< 21046(outs IntRegs:$Rx32), 21047(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32), 21048"memh($Rx32++$Mu2:brev) = $Rt32", 21049tc_da97ee82, TypeST>, Enc_d5c73f, AddrModeRel { 21050let Inst{7-0} = 0b00000000; 21051let Inst{31-21} = 0b10101111010; 21052let addrMode = PostInc; 21053let accessSize = HalfWordAccess; 21054let mayStore = 1; 21055let BaseOpcode = "S2_storerh_pbr"; 21056let isNVStorable = 1; 21057let Constraints = "$Rx32 = $Rx32in"; 21058} 21059def S2_storerh_pci : HInst< 21060(outs IntRegs:$Rx32), 21061(ins IntRegs:$Rx32in, s4_1Imm:$Ii, ModRegs:$Mu2, IntRegs:$Rt32), 21062"memh($Rx32++#$Ii:circ($Mu2)) = $Rt32", 21063tc_e86aa961, TypeST>, Enc_935d9b, AddrModeRel { 21064let Inst{2-0} = 0b000; 21065let Inst{7-7} = 0b0; 21066let Inst{31-21} = 0b10101001010; 21067let addrMode = PostInc; 21068let accessSize = HalfWordAccess; 21069let mayStore = 1; 21070let Uses = [CS]; 21071let BaseOpcode = "S2_storerh_pci"; 21072let isNVStorable = 1; 21073let Constraints = "$Rx32 = $Rx32in"; 21074} 21075def S2_storerh_pcr : HInst< 21076(outs IntRegs:$Rx32), 21077(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32), 21078"memh($Rx32++I:circ($Mu2)) = $Rt32", 21079tc_da97ee82, TypeST>, Enc_d5c73f, AddrModeRel { 21080let Inst{7-0} = 0b00000010; 21081let Inst{31-21} = 0b10101001010; 21082let addrMode = PostInc; 21083let accessSize = HalfWordAccess; 21084let mayStore = 1; 21085let Uses = [CS]; 21086let BaseOpcode = "S2_storerh_pcr"; 21087let isNVStorable = 1; 21088let Constraints = "$Rx32 = $Rx32in"; 21089} 21090def S2_storerh_pi : HInst< 21091(outs IntRegs:$Rx32), 21092(ins IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Rt32), 21093"memh($Rx32++#$Ii) = $Rt32", 21094tc_da97ee82, TypeST>, Enc_052c7d, AddrModeRel, PostInc_BaseImm { 21095let Inst{2-0} = 0b000; 21096let Inst{7-7} = 0b0; 21097let Inst{13-13} = 0b0; 21098let Inst{31-21} = 0b10101011010; 21099let addrMode = PostInc; 21100let accessSize = HalfWordAccess; 21101let mayStore = 1; 21102let CextOpcode = "S2_storerh"; 21103let BaseOpcode = "S2_storerh_pi"; 21104let isPredicable = 1; 21105let isNVStorable = 1; 21106let Constraints = "$Rx32 = $Rx32in"; 21107} 21108def S2_storerh_pr : HInst< 21109(outs IntRegs:$Rx32), 21110(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32), 21111"memh($Rx32++$Mu2) = $Rt32", 21112tc_da97ee82, TypeST>, Enc_d5c73f { 21113let Inst{7-0} = 0b00000000; 21114let Inst{31-21} = 0b10101101010; 21115let addrMode = PostInc; 21116let accessSize = HalfWordAccess; 21117let mayStore = 1; 21118let isNVStorable = 1; 21119let Constraints = "$Rx32 = $Rx32in"; 21120} 21121def S2_storerh_zomap : HInst< 21122(outs), 21123(ins IntRegs:$Rs32, IntRegs:$Rt32), 21124"memh($Rs32) = $Rt32", 21125tc_30b9bb4a, TypeMAPPING> { 21126let isPseudo = 1; 21127let isCodeGenOnly = 1; 21128} 21129def S2_storerhgp : HInst< 21130(outs), 21131(ins u31_1Imm:$Ii, IntRegs:$Rt32), 21132"memh(gp+#$Ii) = $Rt32", 21133tc_0371abea, TypeV2LDST>, Enc_fda92c, AddrModeRel { 21134let Inst{24-21} = 0b0010; 21135let Inst{31-27} = 0b01001; 21136let accessSize = HalfWordAccess; 21137let mayStore = 1; 21138let Uses = [GP]; 21139let BaseOpcode = "S2_storerhabs"; 21140let isPredicable = 1; 21141let isNVStorable = 1; 21142let opExtendable = 0; 21143let isExtentSigned = 0; 21144let opExtentBits = 17; 21145let opExtentAlign = 1; 21146} 21147def S2_storerhnew_io : HInst< 21148(outs), 21149(ins IntRegs:$Rs32, s31_1Imm:$Ii, IntRegs:$Nt8), 21150"memh($Rs32+#$Ii) = $Nt8.new", 21151tc_be9602ff, TypeST>, Enc_0d8870, AddrModeRel { 21152let Inst{12-11} = 0b01; 21153let Inst{24-21} = 0b1101; 21154let Inst{31-27} = 0b10100; 21155let addrMode = BaseImmOffset; 21156let accessSize = HalfWordAccess; 21157let isNVStore = 1; 21158let isNewValue = 1; 21159let isRestrictNoSlot1Store = 1; 21160let mayStore = 1; 21161let CextOpcode = "S2_storerh"; 21162let InputType = "imm"; 21163let BaseOpcode = "S2_storerh_io"; 21164let isPredicable = 1; 21165let isExtendable = 1; 21166let opExtendable = 1; 21167let isExtentSigned = 1; 21168let opExtentBits = 12; 21169let opExtentAlign = 1; 21170let opNewValue = 2; 21171} 21172def S2_storerhnew_pbr : HInst< 21173(outs IntRegs:$Rx32), 21174(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Nt8), 21175"memh($Rx32++$Mu2:brev) = $Nt8.new", 21176tc_c79a189f, TypeST>, Enc_8dbe85, AddrModeRel { 21177let Inst{7-0} = 0b00000000; 21178let Inst{12-11} = 0b01; 21179let Inst{31-21} = 0b10101111101; 21180let addrMode = PostInc; 21181let accessSize = HalfWordAccess; 21182let isNVStore = 1; 21183let isNewValue = 1; 21184let isRestrictNoSlot1Store = 1; 21185let mayStore = 1; 21186let BaseOpcode = "S2_storerh_pbr"; 21187let opNewValue = 3; 21188let Constraints = "$Rx32 = $Rx32in"; 21189} 21190def S2_storerhnew_pci : HInst< 21191(outs IntRegs:$Rx32), 21192(ins IntRegs:$Rx32in, s4_1Imm:$Ii, ModRegs:$Mu2, IntRegs:$Nt8), 21193"memh($Rx32++#$Ii:circ($Mu2)) = $Nt8.new", 21194tc_d5c0729a, TypeST>, Enc_91b9fe, AddrModeRel { 21195let Inst{2-0} = 0b000; 21196let Inst{7-7} = 0b0; 21197let Inst{12-11} = 0b01; 21198let Inst{31-21} = 0b10101001101; 21199let addrMode = PostInc; 21200let accessSize = HalfWordAccess; 21201let isNVStore = 1; 21202let isNewValue = 1; 21203let isRestrictNoSlot1Store = 1; 21204let mayStore = 1; 21205let Uses = [CS]; 21206let BaseOpcode = "S2_storerh_pci"; 21207let opNewValue = 4; 21208let Constraints = "$Rx32 = $Rx32in"; 21209} 21210def S2_storerhnew_pcr : HInst< 21211(outs IntRegs:$Rx32), 21212(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Nt8), 21213"memh($Rx32++I:circ($Mu2)) = $Nt8.new", 21214tc_c79a189f, TypeST>, Enc_8dbe85, AddrModeRel { 21215let Inst{7-0} = 0b00000010; 21216let Inst{12-11} = 0b01; 21217let Inst{31-21} = 0b10101001101; 21218let addrMode = PostInc; 21219let accessSize = HalfWordAccess; 21220let isNVStore = 1; 21221let isNewValue = 1; 21222let isRestrictNoSlot1Store = 1; 21223let mayStore = 1; 21224let Uses = [CS]; 21225let BaseOpcode = "S2_storerh_pcr"; 21226let opNewValue = 3; 21227let Constraints = "$Rx32 = $Rx32in"; 21228} 21229def S2_storerhnew_pi : HInst< 21230(outs IntRegs:$Rx32), 21231(ins IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Nt8), 21232"memh($Rx32++#$Ii) = $Nt8.new", 21233tc_c79a189f, TypeST>, Enc_e26546, AddrModeRel { 21234let Inst{2-0} = 0b000; 21235let Inst{7-7} = 0b0; 21236let Inst{13-11} = 0b001; 21237let Inst{31-21} = 0b10101011101; 21238let addrMode = PostInc; 21239let accessSize = HalfWordAccess; 21240let isNVStore = 1; 21241let isNewValue = 1; 21242let isRestrictNoSlot1Store = 1; 21243let mayStore = 1; 21244let BaseOpcode = "S2_storerh_pi"; 21245let isNVStorable = 1; 21246let isPredicable = 1; 21247let opNewValue = 3; 21248let Constraints = "$Rx32 = $Rx32in"; 21249} 21250def S2_storerhnew_pr : HInst< 21251(outs IntRegs:$Rx32), 21252(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Nt8), 21253"memh($Rx32++$Mu2) = $Nt8.new", 21254tc_c79a189f, TypeST>, Enc_8dbe85 { 21255let Inst{7-0} = 0b00000000; 21256let Inst{12-11} = 0b01; 21257let Inst{31-21} = 0b10101101101; 21258let addrMode = PostInc; 21259let accessSize = HalfWordAccess; 21260let isNVStore = 1; 21261let isNewValue = 1; 21262let isRestrictNoSlot1Store = 1; 21263let mayStore = 1; 21264let opNewValue = 3; 21265let Constraints = "$Rx32 = $Rx32in"; 21266} 21267def S2_storerhnew_zomap : HInst< 21268(outs), 21269(ins IntRegs:$Rs32, IntRegs:$Nt8), 21270"memh($Rs32) = $Nt8.new", 21271tc_be9602ff, TypeMAPPING> { 21272let isPseudo = 1; 21273let isCodeGenOnly = 1; 21274let opNewValue = 1; 21275} 21276def S2_storerhnewgp : HInst< 21277(outs), 21278(ins u31_1Imm:$Ii, IntRegs:$Nt8), 21279"memh(gp+#$Ii) = $Nt8.new", 21280tc_5bf126a6, TypeV2LDST>, Enc_bc03e5, AddrModeRel { 21281let Inst{12-11} = 0b01; 21282let Inst{24-21} = 0b0101; 21283let Inst{31-27} = 0b01001; 21284let accessSize = HalfWordAccess; 21285let isNVStore = 1; 21286let isNewValue = 1; 21287let isRestrictNoSlot1Store = 1; 21288let mayStore = 1; 21289let Uses = [GP]; 21290let BaseOpcode = "S2_storerhabs"; 21291let isPredicable = 1; 21292let opExtendable = 0; 21293let isExtentSigned = 0; 21294let opExtentBits = 17; 21295let opExtentAlign = 1; 21296let opNewValue = 1; 21297} 21298def S2_storeri_io : HInst< 21299(outs), 21300(ins IntRegs:$Rs32, s30_2Imm:$Ii, IntRegs:$Rt32), 21301"memw($Rs32+#$Ii) = $Rt32", 21302tc_30b9bb4a, TypeST>, Enc_143445, AddrModeRel, PostInc_BaseImm { 21303let Inst{24-21} = 0b1100; 21304let Inst{31-27} = 0b10100; 21305let addrMode = BaseImmOffset; 21306let accessSize = WordAccess; 21307let mayStore = 1; 21308let CextOpcode = "S2_storeri"; 21309let InputType = "imm"; 21310let BaseOpcode = "S2_storeri_io"; 21311let isPredicable = 1; 21312let isNVStorable = 1; 21313let isExtendable = 1; 21314let opExtendable = 1; 21315let isExtentSigned = 1; 21316let opExtentBits = 13; 21317let opExtentAlign = 2; 21318} 21319def S2_storeri_pbr : HInst< 21320(outs IntRegs:$Rx32), 21321(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32), 21322"memw($Rx32++$Mu2:brev) = $Rt32", 21323tc_da97ee82, TypeST>, Enc_d5c73f, AddrModeRel { 21324let Inst{7-0} = 0b00000000; 21325let Inst{31-21} = 0b10101111100; 21326let addrMode = PostInc; 21327let accessSize = WordAccess; 21328let mayStore = 1; 21329let BaseOpcode = "S2_storeri_pbr"; 21330let isNVStorable = 1; 21331let Constraints = "$Rx32 = $Rx32in"; 21332} 21333def S2_storeri_pci : HInst< 21334(outs IntRegs:$Rx32), 21335(ins IntRegs:$Rx32in, s4_2Imm:$Ii, ModRegs:$Mu2, IntRegs:$Rt32), 21336"memw($Rx32++#$Ii:circ($Mu2)) = $Rt32", 21337tc_e86aa961, TypeST>, Enc_79b8c8, AddrModeRel { 21338let Inst{2-0} = 0b000; 21339let Inst{7-7} = 0b0; 21340let Inst{31-21} = 0b10101001100; 21341let addrMode = PostInc; 21342let accessSize = WordAccess; 21343let mayStore = 1; 21344let Uses = [CS]; 21345let BaseOpcode = "S2_storeri_pci"; 21346let isNVStorable = 1; 21347let Constraints = "$Rx32 = $Rx32in"; 21348} 21349def S2_storeri_pcr : HInst< 21350(outs IntRegs:$Rx32), 21351(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32), 21352"memw($Rx32++I:circ($Mu2)) = $Rt32", 21353tc_da97ee82, TypeST>, Enc_d5c73f, AddrModeRel { 21354let Inst{7-0} = 0b00000010; 21355let Inst{31-21} = 0b10101001100; 21356let addrMode = PostInc; 21357let accessSize = WordAccess; 21358let mayStore = 1; 21359let Uses = [CS]; 21360let BaseOpcode = "S2_storeri_pcr"; 21361let isNVStorable = 1; 21362let Constraints = "$Rx32 = $Rx32in"; 21363} 21364def S2_storeri_pi : HInst< 21365(outs IntRegs:$Rx32), 21366(ins IntRegs:$Rx32in, s4_2Imm:$Ii, IntRegs:$Rt32), 21367"memw($Rx32++#$Ii) = $Rt32", 21368tc_da97ee82, TypeST>, Enc_db40cd, AddrModeRel, PostInc_BaseImm { 21369let Inst{2-0} = 0b000; 21370let Inst{7-7} = 0b0; 21371let Inst{13-13} = 0b0; 21372let Inst{31-21} = 0b10101011100; 21373let addrMode = PostInc; 21374let accessSize = WordAccess; 21375let mayStore = 1; 21376let CextOpcode = "S2_storeri"; 21377let BaseOpcode = "S2_storeri_pi"; 21378let isPredicable = 1; 21379let isNVStorable = 1; 21380let Constraints = "$Rx32 = $Rx32in"; 21381} 21382def S2_storeri_pr : HInst< 21383(outs IntRegs:$Rx32), 21384(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32), 21385"memw($Rx32++$Mu2) = $Rt32", 21386tc_da97ee82, TypeST>, Enc_d5c73f { 21387let Inst{7-0} = 0b00000000; 21388let Inst{31-21} = 0b10101101100; 21389let addrMode = PostInc; 21390let accessSize = WordAccess; 21391let mayStore = 1; 21392let isNVStorable = 1; 21393let Constraints = "$Rx32 = $Rx32in"; 21394} 21395def S2_storeri_zomap : HInst< 21396(outs), 21397(ins IntRegs:$Rs32, IntRegs:$Rt32), 21398"memw($Rs32) = $Rt32", 21399tc_30b9bb4a, TypeMAPPING> { 21400let isPseudo = 1; 21401let isCodeGenOnly = 1; 21402} 21403def S2_storerigp : HInst< 21404(outs), 21405(ins u30_2Imm:$Ii, IntRegs:$Rt32), 21406"memw(gp+#$Ii) = $Rt32", 21407tc_0371abea, TypeV2LDST>, Enc_541f26, AddrModeRel { 21408let Inst{24-21} = 0b0100; 21409let Inst{31-27} = 0b01001; 21410let accessSize = WordAccess; 21411let mayStore = 1; 21412let Uses = [GP]; 21413let BaseOpcode = "S2_storeriabs"; 21414let isPredicable = 1; 21415let isNVStorable = 1; 21416let opExtendable = 0; 21417let isExtentSigned = 0; 21418let opExtentBits = 18; 21419let opExtentAlign = 2; 21420} 21421def S2_storerinew_io : HInst< 21422(outs), 21423(ins IntRegs:$Rs32, s30_2Imm:$Ii, IntRegs:$Nt8), 21424"memw($Rs32+#$Ii) = $Nt8.new", 21425tc_be9602ff, TypeST>, Enc_690862, AddrModeRel { 21426let Inst{12-11} = 0b10; 21427let Inst{24-21} = 0b1101; 21428let Inst{31-27} = 0b10100; 21429let addrMode = BaseImmOffset; 21430let accessSize = WordAccess; 21431let isNVStore = 1; 21432let isNewValue = 1; 21433let isRestrictNoSlot1Store = 1; 21434let mayStore = 1; 21435let CextOpcode = "S2_storeri"; 21436let InputType = "imm"; 21437let BaseOpcode = "S2_storeri_io"; 21438let isPredicable = 1; 21439let isExtendable = 1; 21440let opExtendable = 1; 21441let isExtentSigned = 1; 21442let opExtentBits = 13; 21443let opExtentAlign = 2; 21444let opNewValue = 2; 21445} 21446def S2_storerinew_pbr : HInst< 21447(outs IntRegs:$Rx32), 21448(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Nt8), 21449"memw($Rx32++$Mu2:brev) = $Nt8.new", 21450tc_c79a189f, TypeST>, Enc_8dbe85, AddrModeRel { 21451let Inst{7-0} = 0b00000000; 21452let Inst{12-11} = 0b10; 21453let Inst{31-21} = 0b10101111101; 21454let addrMode = PostInc; 21455let accessSize = WordAccess; 21456let isNVStore = 1; 21457let isNewValue = 1; 21458let isRestrictNoSlot1Store = 1; 21459let mayStore = 1; 21460let BaseOpcode = "S2_storeri_pbr"; 21461let opNewValue = 3; 21462let Constraints = "$Rx32 = $Rx32in"; 21463} 21464def S2_storerinew_pci : HInst< 21465(outs IntRegs:$Rx32), 21466(ins IntRegs:$Rx32in, s4_2Imm:$Ii, ModRegs:$Mu2, IntRegs:$Nt8), 21467"memw($Rx32++#$Ii:circ($Mu2)) = $Nt8.new", 21468tc_d5c0729a, TypeST>, Enc_3f97c8, AddrModeRel { 21469let Inst{2-0} = 0b000; 21470let Inst{7-7} = 0b0; 21471let Inst{12-11} = 0b10; 21472let Inst{31-21} = 0b10101001101; 21473let addrMode = PostInc; 21474let accessSize = WordAccess; 21475let isNVStore = 1; 21476let isNewValue = 1; 21477let isRestrictNoSlot1Store = 1; 21478let mayStore = 1; 21479let Uses = [CS]; 21480let BaseOpcode = "S2_storeri_pci"; 21481let opNewValue = 4; 21482let Constraints = "$Rx32 = $Rx32in"; 21483} 21484def S2_storerinew_pcr : HInst< 21485(outs IntRegs:$Rx32), 21486(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Nt8), 21487"memw($Rx32++I:circ($Mu2)) = $Nt8.new", 21488tc_c79a189f, TypeST>, Enc_8dbe85, AddrModeRel { 21489let Inst{7-0} = 0b00000010; 21490let Inst{12-11} = 0b10; 21491let Inst{31-21} = 0b10101001101; 21492let addrMode = PostInc; 21493let accessSize = WordAccess; 21494let isNVStore = 1; 21495let isNewValue = 1; 21496let isRestrictNoSlot1Store = 1; 21497let mayStore = 1; 21498let Uses = [CS]; 21499let BaseOpcode = "S2_storeri_pcr"; 21500let opNewValue = 3; 21501let Constraints = "$Rx32 = $Rx32in"; 21502} 21503def S2_storerinew_pi : HInst< 21504(outs IntRegs:$Rx32), 21505(ins IntRegs:$Rx32in, s4_2Imm:$Ii, IntRegs:$Nt8), 21506"memw($Rx32++#$Ii) = $Nt8.new", 21507tc_c79a189f, TypeST>, Enc_223005, AddrModeRel { 21508let Inst{2-0} = 0b000; 21509let Inst{7-7} = 0b0; 21510let Inst{13-11} = 0b010; 21511let Inst{31-21} = 0b10101011101; 21512let addrMode = PostInc; 21513let accessSize = WordAccess; 21514let isNVStore = 1; 21515let isNewValue = 1; 21516let isRestrictNoSlot1Store = 1; 21517let mayStore = 1; 21518let BaseOpcode = "S2_storeri_pi"; 21519let isPredicable = 1; 21520let opNewValue = 3; 21521let Constraints = "$Rx32 = $Rx32in"; 21522} 21523def S2_storerinew_pr : HInst< 21524(outs IntRegs:$Rx32), 21525(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Nt8), 21526"memw($Rx32++$Mu2) = $Nt8.new", 21527tc_c79a189f, TypeST>, Enc_8dbe85 { 21528let Inst{7-0} = 0b00000000; 21529let Inst{12-11} = 0b10; 21530let Inst{31-21} = 0b10101101101; 21531let addrMode = PostInc; 21532let accessSize = WordAccess; 21533let isNVStore = 1; 21534let isNewValue = 1; 21535let isRestrictNoSlot1Store = 1; 21536let mayStore = 1; 21537let opNewValue = 3; 21538let Constraints = "$Rx32 = $Rx32in"; 21539} 21540def S2_storerinew_zomap : HInst< 21541(outs), 21542(ins IntRegs:$Rs32, IntRegs:$Nt8), 21543"memw($Rs32) = $Nt8.new", 21544tc_be9602ff, TypeMAPPING> { 21545let isPseudo = 1; 21546let isCodeGenOnly = 1; 21547let opNewValue = 1; 21548} 21549def S2_storerinewgp : HInst< 21550(outs), 21551(ins u30_2Imm:$Ii, IntRegs:$Nt8), 21552"memw(gp+#$Ii) = $Nt8.new", 21553tc_5bf126a6, TypeV2LDST>, Enc_78cbf0, AddrModeRel { 21554let Inst{12-11} = 0b10; 21555let Inst{24-21} = 0b0101; 21556let Inst{31-27} = 0b01001; 21557let accessSize = WordAccess; 21558let isNVStore = 1; 21559let isNewValue = 1; 21560let isRestrictNoSlot1Store = 1; 21561let mayStore = 1; 21562let Uses = [GP]; 21563let BaseOpcode = "S2_storeriabs"; 21564let isPredicable = 1; 21565let opExtendable = 0; 21566let isExtentSigned = 0; 21567let opExtentBits = 18; 21568let opExtentAlign = 2; 21569let opNewValue = 1; 21570} 21571def S2_storew_locked : HInst< 21572(outs PredRegs:$Pd4), 21573(ins IntRegs:$Rs32, IntRegs:$Rt32), 21574"memw_locked($Rs32,$Pd4) = $Rt32", 21575tc_5abb5e3f, TypeST>, Enc_c2b48e { 21576let Inst{7-2} = 0b000000; 21577let Inst{13-13} = 0b0; 21578let Inst{31-21} = 0b10100000101; 21579let accessSize = WordAccess; 21580let isPredicateLate = 1; 21581let isSoloAX = 1; 21582let mayStore = 1; 21583} 21584def S2_svsathb : HInst< 21585(outs IntRegs:$Rd32), 21586(ins IntRegs:$Rs32), 21587"$Rd32 = vsathb($Rs32)", 21588tc_0ae0825c, TypeS_2op>, Enc_5e2823 { 21589let Inst{13-5} = 0b000000000; 21590let Inst{31-21} = 0b10001100100; 21591let hasNewValue = 1; 21592let opNewValue = 0; 21593let Defs = [USR_OVF]; 21594} 21595def S2_svsathub : HInst< 21596(outs IntRegs:$Rd32), 21597(ins IntRegs:$Rs32), 21598"$Rd32 = vsathub($Rs32)", 21599tc_0ae0825c, TypeS_2op>, Enc_5e2823 { 21600let Inst{13-5} = 0b000000010; 21601let Inst{31-21} = 0b10001100100; 21602let hasNewValue = 1; 21603let opNewValue = 0; 21604let Defs = [USR_OVF]; 21605} 21606def S2_tableidxb : HInst< 21607(outs IntRegs:$Rx32), 21608(ins IntRegs:$Rx32in, IntRegs:$Rs32, u4_0Imm:$Ii, s6_0Imm:$II), 21609"$Rx32 = tableidxb($Rs32,#$Ii,#$II):raw", 21610tc_bfec0f01, TypeS_2op>, Enc_cd82bc { 21611let Inst{31-22} = 0b1000011100; 21612let hasNewValue = 1; 21613let opNewValue = 0; 21614let prefersSlot3 = 1; 21615let Constraints = "$Rx32 = $Rx32in"; 21616} 21617def S2_tableidxb_goodsyntax : HInst< 21618(outs IntRegs:$Rx32), 21619(ins IntRegs:$Rx32in, IntRegs:$Rs32, u4_0Imm:$Ii, u5_0Imm:$II), 21620"$Rx32 = tableidxb($Rs32,#$Ii,#$II)", 21621tc_bfec0f01, TypeS_2op> { 21622let hasNewValue = 1; 21623let opNewValue = 0; 21624let isPseudo = 1; 21625let isCodeGenOnly = 1; 21626let Constraints = "$Rx32 = $Rx32in"; 21627} 21628def S2_tableidxd : HInst< 21629(outs IntRegs:$Rx32), 21630(ins IntRegs:$Rx32in, IntRegs:$Rs32, u4_0Imm:$Ii, s6_0Imm:$II), 21631"$Rx32 = tableidxd($Rs32,#$Ii,#$II):raw", 21632tc_bfec0f01, TypeS_2op>, Enc_cd82bc { 21633let Inst{31-22} = 0b1000011111; 21634let hasNewValue = 1; 21635let opNewValue = 0; 21636let prefersSlot3 = 1; 21637let Constraints = "$Rx32 = $Rx32in"; 21638} 21639def S2_tableidxd_goodsyntax : HInst< 21640(outs IntRegs:$Rx32), 21641(ins IntRegs:$Rx32in, IntRegs:$Rs32, u4_0Imm:$Ii, u5_0Imm:$II), 21642"$Rx32 = tableidxd($Rs32,#$Ii,#$II)", 21643tc_bfec0f01, TypeS_2op> { 21644let hasNewValue = 1; 21645let opNewValue = 0; 21646let isPseudo = 1; 21647let Constraints = "$Rx32 = $Rx32in"; 21648} 21649def S2_tableidxh : HInst< 21650(outs IntRegs:$Rx32), 21651(ins IntRegs:$Rx32in, IntRegs:$Rs32, u4_0Imm:$Ii, s6_0Imm:$II), 21652"$Rx32 = tableidxh($Rs32,#$Ii,#$II):raw", 21653tc_bfec0f01, TypeS_2op>, Enc_cd82bc { 21654let Inst{31-22} = 0b1000011101; 21655let hasNewValue = 1; 21656let opNewValue = 0; 21657let prefersSlot3 = 1; 21658let Constraints = "$Rx32 = $Rx32in"; 21659} 21660def S2_tableidxh_goodsyntax : HInst< 21661(outs IntRegs:$Rx32), 21662(ins IntRegs:$Rx32in, IntRegs:$Rs32, u4_0Imm:$Ii, u5_0Imm:$II), 21663"$Rx32 = tableidxh($Rs32,#$Ii,#$II)", 21664tc_bfec0f01, TypeS_2op> { 21665let hasNewValue = 1; 21666let opNewValue = 0; 21667let isPseudo = 1; 21668let Constraints = "$Rx32 = $Rx32in"; 21669} 21670def S2_tableidxw : HInst< 21671(outs IntRegs:$Rx32), 21672(ins IntRegs:$Rx32in, IntRegs:$Rs32, u4_0Imm:$Ii, s6_0Imm:$II), 21673"$Rx32 = tableidxw($Rs32,#$Ii,#$II):raw", 21674tc_bfec0f01, TypeS_2op>, Enc_cd82bc { 21675let Inst{31-22} = 0b1000011110; 21676let hasNewValue = 1; 21677let opNewValue = 0; 21678let prefersSlot3 = 1; 21679let Constraints = "$Rx32 = $Rx32in"; 21680} 21681def S2_tableidxw_goodsyntax : HInst< 21682(outs IntRegs:$Rx32), 21683(ins IntRegs:$Rx32in, IntRegs:$Rs32, u4_0Imm:$Ii, u5_0Imm:$II), 21684"$Rx32 = tableidxw($Rs32,#$Ii,#$II)", 21685tc_bfec0f01, TypeS_2op> { 21686let hasNewValue = 1; 21687let opNewValue = 0; 21688let isPseudo = 1; 21689let Constraints = "$Rx32 = $Rx32in"; 21690} 21691def S2_togglebit_i : HInst< 21692(outs IntRegs:$Rd32), 21693(ins IntRegs:$Rs32, u5_0Imm:$Ii), 21694"$Rd32 = togglebit($Rs32,#$Ii)", 21695tc_946df596, TypeS_2op>, Enc_a05677 { 21696let Inst{7-5} = 0b010; 21697let Inst{13-13} = 0b0; 21698let Inst{31-21} = 0b10001100110; 21699let hasNewValue = 1; 21700let opNewValue = 0; 21701} 21702def S2_togglebit_r : HInst< 21703(outs IntRegs:$Rd32), 21704(ins IntRegs:$Rs32, IntRegs:$Rt32), 21705"$Rd32 = togglebit($Rs32,$Rt32)", 21706tc_946df596, TypeS_3op>, Enc_5ab2be { 21707let Inst{7-5} = 0b100; 21708let Inst{13-13} = 0b0; 21709let Inst{31-21} = 0b11000110100; 21710let hasNewValue = 1; 21711let opNewValue = 0; 21712} 21713def S2_tstbit_i : HInst< 21714(outs PredRegs:$Pd4), 21715(ins IntRegs:$Rs32, u5_0Imm:$Ii), 21716"$Pd4 = tstbit($Rs32,#$Ii)", 21717tc_643b4717, TypeS_2op>, Enc_83ee64 { 21718let Inst{7-2} = 0b000000; 21719let Inst{13-13} = 0b0; 21720let Inst{31-21} = 0b10000101000; 21721} 21722def S2_tstbit_r : HInst< 21723(outs PredRegs:$Pd4), 21724(ins IntRegs:$Rs32, IntRegs:$Rt32), 21725"$Pd4 = tstbit($Rs32,$Rt32)", 21726tc_85d5d03f, TypeS_3op>, Enc_c2b48e { 21727let Inst{7-2} = 0b000000; 21728let Inst{13-13} = 0b0; 21729let Inst{31-21} = 0b11000111000; 21730} 21731def S2_valignib : HInst< 21732(outs DoubleRegs:$Rdd32), 21733(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32, u3_0Imm:$Ii), 21734"$Rdd32 = valignb($Rtt32,$Rss32,#$Ii)", 21735tc_b4b5c03a, TypeS_3op>, Enc_729ff7 { 21736let Inst{13-13} = 0b0; 21737let Inst{31-21} = 0b11000000000; 21738} 21739def S2_valignrb : HInst< 21740(outs DoubleRegs:$Rdd32), 21741(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32, PredRegs:$Pu4), 21742"$Rdd32 = valignb($Rtt32,$Rss32,$Pu4)", 21743tc_b4b5c03a, TypeS_3op>, Enc_8c6530 { 21744let Inst{7-7} = 0b0; 21745let Inst{13-13} = 0b0; 21746let Inst{31-21} = 0b11000010000; 21747} 21748def S2_vcnegh : HInst< 21749(outs DoubleRegs:$Rdd32), 21750(ins DoubleRegs:$Rss32, IntRegs:$Rt32), 21751"$Rdd32 = vcnegh($Rss32,$Rt32)", 21752tc_779080bf, TypeS_3op>, Enc_927852 { 21753let Inst{7-5} = 0b010; 21754let Inst{13-13} = 0b0; 21755let Inst{31-21} = 0b11000011110; 21756let prefersSlot3 = 1; 21757let Defs = [USR_OVF]; 21758} 21759def S2_vcrotate : HInst< 21760(outs DoubleRegs:$Rdd32), 21761(ins DoubleRegs:$Rss32, IntRegs:$Rt32), 21762"$Rdd32 = vcrotate($Rss32,$Rt32)", 21763tc_002cb246, TypeS_3op>, Enc_927852 { 21764let Inst{7-5} = 0b000; 21765let Inst{13-13} = 0b0; 21766let Inst{31-21} = 0b11000011110; 21767let prefersSlot3 = 1; 21768let Defs = [USR_OVF]; 21769} 21770def S2_vrcnegh : HInst< 21771(outs DoubleRegs:$Rxx32), 21772(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32), 21773"$Rxx32 += vrcnegh($Rss32,$Rt32)", 21774tc_d773585a, TypeS_3op>, Enc_1aa186 { 21775let Inst{7-5} = 0b111; 21776let Inst{13-13} = 0b1; 21777let Inst{31-21} = 0b11001011001; 21778let prefersSlot3 = 1; 21779let Constraints = "$Rxx32 = $Rxx32in"; 21780} 21781def S2_vrndpackwh : HInst< 21782(outs IntRegs:$Rd32), 21783(ins DoubleRegs:$Rss32), 21784"$Rd32 = vrndwh($Rss32)", 21785tc_14b5c689, TypeS_2op>, Enc_90cd8b { 21786let Inst{13-5} = 0b000000100; 21787let Inst{31-21} = 0b10001000100; 21788let hasNewValue = 1; 21789let opNewValue = 0; 21790let prefersSlot3 = 1; 21791} 21792def S2_vrndpackwhs : HInst< 21793(outs IntRegs:$Rd32), 21794(ins DoubleRegs:$Rss32), 21795"$Rd32 = vrndwh($Rss32):sat", 21796tc_cf8126ae, TypeS_2op>, Enc_90cd8b { 21797let Inst{13-5} = 0b000000110; 21798let Inst{31-21} = 0b10001000100; 21799let hasNewValue = 1; 21800let opNewValue = 0; 21801let prefersSlot3 = 1; 21802let Defs = [USR_OVF]; 21803} 21804def S2_vsathb : HInst< 21805(outs IntRegs:$Rd32), 21806(ins DoubleRegs:$Rss32), 21807"$Rd32 = vsathb($Rss32)", 21808tc_0ae0825c, TypeS_2op>, Enc_90cd8b { 21809let Inst{13-5} = 0b000000110; 21810let Inst{31-21} = 0b10001000000; 21811let hasNewValue = 1; 21812let opNewValue = 0; 21813let Defs = [USR_OVF]; 21814} 21815def S2_vsathb_nopack : HInst< 21816(outs DoubleRegs:$Rdd32), 21817(ins DoubleRegs:$Rss32), 21818"$Rdd32 = vsathb($Rss32)", 21819tc_0ae0825c, TypeS_2op>, Enc_b9c5fb { 21820let Inst{13-5} = 0b000000111; 21821let Inst{31-21} = 0b10000000000; 21822let Defs = [USR_OVF]; 21823} 21824def S2_vsathub : HInst< 21825(outs IntRegs:$Rd32), 21826(ins DoubleRegs:$Rss32), 21827"$Rd32 = vsathub($Rss32)", 21828tc_0ae0825c, TypeS_2op>, Enc_90cd8b { 21829let Inst{13-5} = 0b000000000; 21830let Inst{31-21} = 0b10001000000; 21831let hasNewValue = 1; 21832let opNewValue = 0; 21833let Defs = [USR_OVF]; 21834} 21835def S2_vsathub_nopack : HInst< 21836(outs DoubleRegs:$Rdd32), 21837(ins DoubleRegs:$Rss32), 21838"$Rdd32 = vsathub($Rss32)", 21839tc_0ae0825c, TypeS_2op>, Enc_b9c5fb { 21840let Inst{13-5} = 0b000000100; 21841let Inst{31-21} = 0b10000000000; 21842let Defs = [USR_OVF]; 21843} 21844def S2_vsatwh : HInst< 21845(outs IntRegs:$Rd32), 21846(ins DoubleRegs:$Rss32), 21847"$Rd32 = vsatwh($Rss32)", 21848tc_0ae0825c, TypeS_2op>, Enc_90cd8b { 21849let Inst{13-5} = 0b000000010; 21850let Inst{31-21} = 0b10001000000; 21851let hasNewValue = 1; 21852let opNewValue = 0; 21853let Defs = [USR_OVF]; 21854} 21855def S2_vsatwh_nopack : HInst< 21856(outs DoubleRegs:$Rdd32), 21857(ins DoubleRegs:$Rss32), 21858"$Rdd32 = vsatwh($Rss32)", 21859tc_0ae0825c, TypeS_2op>, Enc_b9c5fb { 21860let Inst{13-5} = 0b000000110; 21861let Inst{31-21} = 0b10000000000; 21862let Defs = [USR_OVF]; 21863} 21864def S2_vsatwuh : HInst< 21865(outs IntRegs:$Rd32), 21866(ins DoubleRegs:$Rss32), 21867"$Rd32 = vsatwuh($Rss32)", 21868tc_0ae0825c, TypeS_2op>, Enc_90cd8b { 21869let Inst{13-5} = 0b000000100; 21870let Inst{31-21} = 0b10001000000; 21871let hasNewValue = 1; 21872let opNewValue = 0; 21873let Defs = [USR_OVF]; 21874} 21875def S2_vsatwuh_nopack : HInst< 21876(outs DoubleRegs:$Rdd32), 21877(ins DoubleRegs:$Rss32), 21878"$Rdd32 = vsatwuh($Rss32)", 21879tc_0ae0825c, TypeS_2op>, Enc_b9c5fb { 21880let Inst{13-5} = 0b000000101; 21881let Inst{31-21} = 0b10000000000; 21882let Defs = [USR_OVF]; 21883} 21884def S2_vsplatrb : HInst< 21885(outs IntRegs:$Rd32), 21886(ins IntRegs:$Rs32), 21887"$Rd32 = vsplatb($Rs32)", 21888tc_0ae0825c, TypeS_2op>, Enc_5e2823 { 21889let Inst{13-5} = 0b000000111; 21890let Inst{31-21} = 0b10001100010; 21891let hasNewValue = 1; 21892let opNewValue = 0; 21893let isReMaterializable = 1; 21894let isAsCheapAsAMove = 1; 21895} 21896def S2_vsplatrh : HInst< 21897(outs DoubleRegs:$Rdd32), 21898(ins IntRegs:$Rs32), 21899"$Rdd32 = vsplath($Rs32)", 21900tc_0ae0825c, TypeS_2op>, Enc_3a3d62 { 21901let Inst{13-5} = 0b000000010; 21902let Inst{31-21} = 0b10000100010; 21903let isReMaterializable = 1; 21904let isAsCheapAsAMove = 1; 21905} 21906def S2_vspliceib : HInst< 21907(outs DoubleRegs:$Rdd32), 21908(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32, u3_0Imm:$Ii), 21909"$Rdd32 = vspliceb($Rss32,$Rtt32,#$Ii)", 21910tc_b4b5c03a, TypeS_3op>, Enc_d50cd3 { 21911let Inst{13-13} = 0b0; 21912let Inst{31-21} = 0b11000000100; 21913} 21914def S2_vsplicerb : HInst< 21915(outs DoubleRegs:$Rdd32), 21916(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32, PredRegs:$Pu4), 21917"$Rdd32 = vspliceb($Rss32,$Rtt32,$Pu4)", 21918tc_b4b5c03a, TypeS_3op>, Enc_dbd70c { 21919let Inst{7-7} = 0b0; 21920let Inst{13-13} = 0b0; 21921let Inst{31-21} = 0b11000010100; 21922} 21923def S2_vsxtbh : HInst< 21924(outs DoubleRegs:$Rdd32), 21925(ins IntRegs:$Rs32), 21926"$Rdd32 = vsxtbh($Rs32)", 21927tc_0ae0825c, TypeS_2op>, Enc_3a3d62 { 21928let Inst{13-5} = 0b000000000; 21929let Inst{31-21} = 0b10000100000; 21930let isReMaterializable = 1; 21931let isAsCheapAsAMove = 1; 21932} 21933def S2_vsxthw : HInst< 21934(outs DoubleRegs:$Rdd32), 21935(ins IntRegs:$Rs32), 21936"$Rdd32 = vsxthw($Rs32)", 21937tc_0ae0825c, TypeS_2op>, Enc_3a3d62 { 21938let Inst{13-5} = 0b000000100; 21939let Inst{31-21} = 0b10000100000; 21940let isReMaterializable = 1; 21941let isAsCheapAsAMove = 1; 21942} 21943def S2_vtrunehb : HInst< 21944(outs IntRegs:$Rd32), 21945(ins DoubleRegs:$Rss32), 21946"$Rd32 = vtrunehb($Rss32)", 21947tc_0ae0825c, TypeS_2op>, Enc_90cd8b { 21948let Inst{13-5} = 0b000000010; 21949let Inst{31-21} = 0b10001000100; 21950let hasNewValue = 1; 21951let opNewValue = 0; 21952} 21953def S2_vtrunewh : HInst< 21954(outs DoubleRegs:$Rdd32), 21955(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 21956"$Rdd32 = vtrunewh($Rss32,$Rtt32)", 21957tc_946df596, TypeS_3op>, Enc_a56825 { 21958let Inst{7-5} = 0b010; 21959let Inst{13-13} = 0b0; 21960let Inst{31-21} = 0b11000001100; 21961} 21962def S2_vtrunohb : HInst< 21963(outs IntRegs:$Rd32), 21964(ins DoubleRegs:$Rss32), 21965"$Rd32 = vtrunohb($Rss32)", 21966tc_0ae0825c, TypeS_2op>, Enc_90cd8b { 21967let Inst{13-5} = 0b000000000; 21968let Inst{31-21} = 0b10001000100; 21969let hasNewValue = 1; 21970let opNewValue = 0; 21971} 21972def S2_vtrunowh : HInst< 21973(outs DoubleRegs:$Rdd32), 21974(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 21975"$Rdd32 = vtrunowh($Rss32,$Rtt32)", 21976tc_946df596, TypeS_3op>, Enc_a56825 { 21977let Inst{7-5} = 0b100; 21978let Inst{13-13} = 0b0; 21979let Inst{31-21} = 0b11000001100; 21980} 21981def S2_vzxtbh : HInst< 21982(outs DoubleRegs:$Rdd32), 21983(ins IntRegs:$Rs32), 21984"$Rdd32 = vzxtbh($Rs32)", 21985tc_0ae0825c, TypeS_2op>, Enc_3a3d62 { 21986let Inst{13-5} = 0b000000010; 21987let Inst{31-21} = 0b10000100000; 21988let isReMaterializable = 1; 21989let isAsCheapAsAMove = 1; 21990} 21991def S2_vzxthw : HInst< 21992(outs DoubleRegs:$Rdd32), 21993(ins IntRegs:$Rs32), 21994"$Rdd32 = vzxthw($Rs32)", 21995tc_0ae0825c, TypeS_2op>, Enc_3a3d62 { 21996let Inst{13-5} = 0b000000110; 21997let Inst{31-21} = 0b10000100000; 21998let isReMaterializable = 1; 21999let isAsCheapAsAMove = 1; 22000} 22001def S4_addaddi : HInst< 22002(outs IntRegs:$Rd32), 22003(ins IntRegs:$Rs32, IntRegs:$Ru32, s32_0Imm:$Ii), 22004"$Rd32 = add($Rs32,add($Ru32,#$Ii))", 22005tc_f675fee8, TypeALU64>, Enc_8b8d61 { 22006let Inst{31-23} = 0b110110110; 22007let hasNewValue = 1; 22008let opNewValue = 0; 22009let prefersSlot3 = 1; 22010let isExtendable = 1; 22011let opExtendable = 3; 22012let isExtentSigned = 1; 22013let opExtentBits = 6; 22014let opExtentAlign = 0; 22015} 22016def S4_addi_asl_ri : HInst< 22017(outs IntRegs:$Rx32), 22018(ins u32_0Imm:$Ii, IntRegs:$Rx32in, u5_0Imm:$II), 22019"$Rx32 = add(#$Ii,asl($Rx32in,#$II))", 22020tc_f675fee8, TypeALU64>, Enc_c31910 { 22021let Inst{2-0} = 0b100; 22022let Inst{4-4} = 0b0; 22023let Inst{31-24} = 0b11011110; 22024let hasNewValue = 1; 22025let opNewValue = 0; 22026let prefersSlot3 = 1; 22027let isExtendable = 1; 22028let opExtendable = 1; 22029let isExtentSigned = 0; 22030let opExtentBits = 8; 22031let opExtentAlign = 0; 22032let Constraints = "$Rx32 = $Rx32in"; 22033} 22034def S4_addi_lsr_ri : HInst< 22035(outs IntRegs:$Rx32), 22036(ins u32_0Imm:$Ii, IntRegs:$Rx32in, u5_0Imm:$II), 22037"$Rx32 = add(#$Ii,lsr($Rx32in,#$II))", 22038tc_f675fee8, TypeALU64>, Enc_c31910 { 22039let Inst{2-0} = 0b100; 22040let Inst{4-4} = 0b1; 22041let Inst{31-24} = 0b11011110; 22042let hasNewValue = 1; 22043let opNewValue = 0; 22044let prefersSlot3 = 1; 22045let isExtendable = 1; 22046let opExtendable = 1; 22047let isExtentSigned = 0; 22048let opExtentBits = 8; 22049let opExtentAlign = 0; 22050let Constraints = "$Rx32 = $Rx32in"; 22051} 22052def S4_andi_asl_ri : HInst< 22053(outs IntRegs:$Rx32), 22054(ins u32_0Imm:$Ii, IntRegs:$Rx32in, u5_0Imm:$II), 22055"$Rx32 = and(#$Ii,asl($Rx32in,#$II))", 22056tc_f429765c, TypeALU64>, Enc_c31910 { 22057let Inst{2-0} = 0b000; 22058let Inst{4-4} = 0b0; 22059let Inst{31-24} = 0b11011110; 22060let hasNewValue = 1; 22061let opNewValue = 0; 22062let prefersSlot3 = 1; 22063let isExtendable = 1; 22064let opExtendable = 1; 22065let isExtentSigned = 0; 22066let opExtentBits = 8; 22067let opExtentAlign = 0; 22068let Constraints = "$Rx32 = $Rx32in"; 22069} 22070def S4_andi_lsr_ri : HInst< 22071(outs IntRegs:$Rx32), 22072(ins u32_0Imm:$Ii, IntRegs:$Rx32in, u5_0Imm:$II), 22073"$Rx32 = and(#$Ii,lsr($Rx32in,#$II))", 22074tc_f429765c, TypeALU64>, Enc_c31910 { 22075let Inst{2-0} = 0b000; 22076let Inst{4-4} = 0b1; 22077let Inst{31-24} = 0b11011110; 22078let hasNewValue = 1; 22079let opNewValue = 0; 22080let prefersSlot3 = 1; 22081let isExtendable = 1; 22082let opExtendable = 1; 22083let isExtentSigned = 0; 22084let opExtentBits = 8; 22085let opExtentAlign = 0; 22086let Constraints = "$Rx32 = $Rx32in"; 22087} 22088def S4_clbaddi : HInst< 22089(outs IntRegs:$Rd32), 22090(ins IntRegs:$Rs32, s6_0Imm:$Ii), 22091"$Rd32 = add(clb($Rs32),#$Ii)", 22092tc_002cb246, TypeS_2op>, Enc_9fae8a { 22093let Inst{7-5} = 0b000; 22094let Inst{31-21} = 0b10001100001; 22095let hasNewValue = 1; 22096let opNewValue = 0; 22097let prefersSlot3 = 1; 22098} 22099def S4_clbpaddi : HInst< 22100(outs IntRegs:$Rd32), 22101(ins DoubleRegs:$Rss32, s6_0Imm:$Ii), 22102"$Rd32 = add(clb($Rss32),#$Ii)", 22103tc_002cb246, TypeS_2op>, Enc_a1640c { 22104let Inst{7-5} = 0b010; 22105let Inst{31-21} = 0b10001000011; 22106let hasNewValue = 1; 22107let opNewValue = 0; 22108let prefersSlot3 = 1; 22109} 22110def S4_clbpnorm : HInst< 22111(outs IntRegs:$Rd32), 22112(ins DoubleRegs:$Rss32), 22113"$Rd32 = normamt($Rss32)", 22114tc_14b5c689, TypeS_2op>, Enc_90cd8b { 22115let Inst{13-5} = 0b000000000; 22116let Inst{31-21} = 0b10001000011; 22117let hasNewValue = 1; 22118let opNewValue = 0; 22119let prefersSlot3 = 1; 22120} 22121def S4_extract : HInst< 22122(outs IntRegs:$Rd32), 22123(ins IntRegs:$Rs32, u5_0Imm:$Ii, u5_0Imm:$II), 22124"$Rd32 = extract($Rs32,#$Ii,#$II)", 22125tc_f675fee8, TypeS_2op>, Enc_b388cf { 22126let Inst{13-13} = 0b0; 22127let Inst{31-23} = 0b100011011; 22128let hasNewValue = 1; 22129let opNewValue = 0; 22130let prefersSlot3 = 1; 22131} 22132def S4_extract_rp : HInst< 22133(outs IntRegs:$Rd32), 22134(ins IntRegs:$Rs32, DoubleRegs:$Rtt32), 22135"$Rd32 = extract($Rs32,$Rtt32)", 22136tc_002cb246, TypeS_3op>, Enc_e07374 { 22137let Inst{7-5} = 0b010; 22138let Inst{13-13} = 0b0; 22139let Inst{31-21} = 0b11001001000; 22140let hasNewValue = 1; 22141let opNewValue = 0; 22142let prefersSlot3 = 1; 22143} 22144def S4_extractp : HInst< 22145(outs DoubleRegs:$Rdd32), 22146(ins DoubleRegs:$Rss32, u6_0Imm:$Ii, u6_0Imm:$II), 22147"$Rdd32 = extract($Rss32,#$Ii,#$II)", 22148tc_f675fee8, TypeS_2op>, Enc_b84c4c { 22149let Inst{31-24} = 0b10001010; 22150let prefersSlot3 = 1; 22151} 22152def S4_extractp_rp : HInst< 22153(outs DoubleRegs:$Rdd32), 22154(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 22155"$Rdd32 = extract($Rss32,$Rtt32)", 22156tc_002cb246, TypeS_3op>, Enc_a56825 { 22157let Inst{7-5} = 0b100; 22158let Inst{13-13} = 0b0; 22159let Inst{31-21} = 0b11000001110; 22160let prefersSlot3 = 1; 22161} 22162def S4_lsli : HInst< 22163(outs IntRegs:$Rd32), 22164(ins s6_0Imm:$Ii, IntRegs:$Rt32), 22165"$Rd32 = lsl(#$Ii,$Rt32)", 22166tc_946df596, TypeS_3op>, Enc_fef969 { 22167let Inst{7-6} = 0b11; 22168let Inst{13-13} = 0b0; 22169let Inst{31-21} = 0b11000110100; 22170let hasNewValue = 1; 22171let opNewValue = 0; 22172} 22173def S4_ntstbit_i : HInst< 22174(outs PredRegs:$Pd4), 22175(ins IntRegs:$Rs32, u5_0Imm:$Ii), 22176"$Pd4 = !tstbit($Rs32,#$Ii)", 22177tc_643b4717, TypeS_2op>, Enc_83ee64 { 22178let Inst{7-2} = 0b000000; 22179let Inst{13-13} = 0b0; 22180let Inst{31-21} = 0b10000101001; 22181} 22182def S4_ntstbit_r : HInst< 22183(outs PredRegs:$Pd4), 22184(ins IntRegs:$Rs32, IntRegs:$Rt32), 22185"$Pd4 = !tstbit($Rs32,$Rt32)", 22186tc_85d5d03f, TypeS_3op>, Enc_c2b48e { 22187let Inst{7-2} = 0b000000; 22188let Inst{13-13} = 0b0; 22189let Inst{31-21} = 0b11000111001; 22190} 22191def S4_or_andi : HInst< 22192(outs IntRegs:$Rx32), 22193(ins IntRegs:$Rx32in, IntRegs:$Rs32, s32_0Imm:$Ii), 22194"$Rx32 |= and($Rs32,#$Ii)", 22195tc_f429765c, TypeALU64>, Enc_b0e9d8 { 22196let Inst{31-22} = 0b1101101000; 22197let hasNewValue = 1; 22198let opNewValue = 0; 22199let prefersSlot3 = 1; 22200let InputType = "imm"; 22201let isExtendable = 1; 22202let opExtendable = 3; 22203let isExtentSigned = 1; 22204let opExtentBits = 10; 22205let opExtentAlign = 0; 22206let Constraints = "$Rx32 = $Rx32in"; 22207} 22208def S4_or_andix : HInst< 22209(outs IntRegs:$Rx32), 22210(ins IntRegs:$Ru32, IntRegs:$Rx32in, s32_0Imm:$Ii), 22211"$Rx32 = or($Ru32,and($Rx32in,#$Ii))", 22212tc_f429765c, TypeALU64>, Enc_b4e6cf { 22213let Inst{31-22} = 0b1101101001; 22214let hasNewValue = 1; 22215let opNewValue = 0; 22216let prefersSlot3 = 1; 22217let isExtendable = 1; 22218let opExtendable = 3; 22219let isExtentSigned = 1; 22220let opExtentBits = 10; 22221let opExtentAlign = 0; 22222let Constraints = "$Rx32 = $Rx32in"; 22223} 22224def S4_or_ori : HInst< 22225(outs IntRegs:$Rx32), 22226(ins IntRegs:$Rx32in, IntRegs:$Rs32, s32_0Imm:$Ii), 22227"$Rx32 |= or($Rs32,#$Ii)", 22228tc_f429765c, TypeALU64>, Enc_b0e9d8 { 22229let Inst{31-22} = 0b1101101010; 22230let hasNewValue = 1; 22231let opNewValue = 0; 22232let prefersSlot3 = 1; 22233let InputType = "imm"; 22234let isExtendable = 1; 22235let opExtendable = 3; 22236let isExtentSigned = 1; 22237let opExtentBits = 10; 22238let opExtentAlign = 0; 22239let Constraints = "$Rx32 = $Rx32in"; 22240} 22241def S4_ori_asl_ri : HInst< 22242(outs IntRegs:$Rx32), 22243(ins u32_0Imm:$Ii, IntRegs:$Rx32in, u5_0Imm:$II), 22244"$Rx32 = or(#$Ii,asl($Rx32in,#$II))", 22245tc_f429765c, TypeALU64>, Enc_c31910 { 22246let Inst{2-0} = 0b010; 22247let Inst{4-4} = 0b0; 22248let Inst{31-24} = 0b11011110; 22249let hasNewValue = 1; 22250let opNewValue = 0; 22251let prefersSlot3 = 1; 22252let isExtendable = 1; 22253let opExtendable = 1; 22254let isExtentSigned = 0; 22255let opExtentBits = 8; 22256let opExtentAlign = 0; 22257let Constraints = "$Rx32 = $Rx32in"; 22258} 22259def S4_ori_lsr_ri : HInst< 22260(outs IntRegs:$Rx32), 22261(ins u32_0Imm:$Ii, IntRegs:$Rx32in, u5_0Imm:$II), 22262"$Rx32 = or(#$Ii,lsr($Rx32in,#$II))", 22263tc_f429765c, TypeALU64>, Enc_c31910 { 22264let Inst{2-0} = 0b010; 22265let Inst{4-4} = 0b1; 22266let Inst{31-24} = 0b11011110; 22267let hasNewValue = 1; 22268let opNewValue = 0; 22269let prefersSlot3 = 1; 22270let isExtendable = 1; 22271let opExtendable = 1; 22272let isExtentSigned = 0; 22273let opExtentBits = 8; 22274let opExtentAlign = 0; 22275let Constraints = "$Rx32 = $Rx32in"; 22276} 22277def S4_parity : HInst< 22278(outs IntRegs:$Rd32), 22279(ins IntRegs:$Rs32, IntRegs:$Rt32), 22280"$Rd32 = parity($Rs32,$Rt32)", 22281tc_002cb246, TypeALU64>, Enc_5ab2be { 22282let Inst{7-5} = 0b000; 22283let Inst{13-13} = 0b0; 22284let Inst{31-21} = 0b11010101111; 22285let hasNewValue = 1; 22286let opNewValue = 0; 22287let prefersSlot3 = 1; 22288} 22289def S4_pstorerbf_abs : HInst< 22290(outs), 22291(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32), 22292"if (!$Pv4) memb(#$Ii) = $Rt32", 22293tc_362c6592, TypeST>, Enc_1cf4ca, AddrModeRel { 22294let Inst{2-2} = 0b1; 22295let Inst{7-7} = 0b1; 22296let Inst{13-13} = 0b0; 22297let Inst{31-18} = 0b10101111000000; 22298let isPredicated = 1; 22299let isPredicatedFalse = 1; 22300let addrMode = Absolute; 22301let accessSize = ByteAccess; 22302let isExtended = 1; 22303let mayStore = 1; 22304let CextOpcode = "S2_storerb"; 22305let BaseOpcode = "S2_storerbabs"; 22306let isNVStorable = 1; 22307let DecoderNamespace = "MustExtend"; 22308let isExtendable = 1; 22309let opExtendable = 1; 22310let isExtentSigned = 0; 22311let opExtentBits = 6; 22312let opExtentAlign = 0; 22313} 22314def S4_pstorerbf_rr : HInst< 22315(outs), 22316(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32), 22317"if (!$Pv4) memb($Rs32+$Ru32<<#$Ii) = $Rt32", 22318tc_3962fa26, TypeST>, Enc_6339d5, AddrModeRel { 22319let Inst{31-21} = 0b00110101000; 22320let isPredicated = 1; 22321let isPredicatedFalse = 1; 22322let addrMode = BaseRegOffset; 22323let accessSize = ByteAccess; 22324let mayStore = 1; 22325let CextOpcode = "S2_storerb"; 22326let InputType = "reg"; 22327let BaseOpcode = "S4_storerb_rr"; 22328let isNVStorable = 1; 22329} 22330def S4_pstorerbfnew_abs : HInst< 22331(outs), 22332(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32), 22333"if (!$Pv4.new) memb(#$Ii) = $Rt32", 22334tc_da4a37ed, TypeST>, Enc_1cf4ca, AddrModeRel { 22335let Inst{2-2} = 0b1; 22336let Inst{7-7} = 0b1; 22337let Inst{13-13} = 0b1; 22338let Inst{31-18} = 0b10101111000000; 22339let isPredicated = 1; 22340let isPredicatedFalse = 1; 22341let addrMode = Absolute; 22342let accessSize = ByteAccess; 22343let isPredicatedNew = 1; 22344let isExtended = 1; 22345let mayStore = 1; 22346let CextOpcode = "S2_storerb"; 22347let BaseOpcode = "S2_storerbabs"; 22348let isNVStorable = 1; 22349let DecoderNamespace = "MustExtend"; 22350let isExtendable = 1; 22351let opExtendable = 1; 22352let isExtentSigned = 0; 22353let opExtentBits = 6; 22354let opExtentAlign = 0; 22355} 22356def S4_pstorerbfnew_io : HInst< 22357(outs), 22358(ins PredRegs:$Pv4, IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Rt32), 22359"if (!$Pv4.new) memb($Rs32+#$Ii) = $Rt32", 22360tc_da97ee82, TypeV2LDST>, Enc_da8d43, AddrModeRel { 22361let Inst{2-2} = 0b0; 22362let Inst{31-21} = 0b01000110000; 22363let isPredicated = 1; 22364let isPredicatedFalse = 1; 22365let addrMode = BaseImmOffset; 22366let accessSize = ByteAccess; 22367let isPredicatedNew = 1; 22368let mayStore = 1; 22369let CextOpcode = "S2_storerb"; 22370let InputType = "imm"; 22371let BaseOpcode = "S2_storerb_io"; 22372let isNVStorable = 1; 22373let isExtendable = 1; 22374let opExtendable = 2; 22375let isExtentSigned = 0; 22376let opExtentBits = 6; 22377let opExtentAlign = 0; 22378} 22379def S4_pstorerbfnew_rr : HInst< 22380(outs), 22381(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32), 22382"if (!$Pv4.new) memb($Rs32+$Ru32<<#$Ii) = $Rt32", 22383tc_40116ca8, TypeST>, Enc_6339d5, AddrModeRel { 22384let Inst{31-21} = 0b00110111000; 22385let isPredicated = 1; 22386let isPredicatedFalse = 1; 22387let addrMode = BaseRegOffset; 22388let accessSize = ByteAccess; 22389let isPredicatedNew = 1; 22390let mayStore = 1; 22391let CextOpcode = "S2_storerb"; 22392let InputType = "reg"; 22393let BaseOpcode = "S4_storerb_rr"; 22394let isNVStorable = 1; 22395} 22396def S4_pstorerbfnew_zomap : HInst< 22397(outs), 22398(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32), 22399"if (!$Pv4.new) memb($Rs32) = $Rt32", 22400tc_da97ee82, TypeMAPPING> { 22401let isPseudo = 1; 22402let isCodeGenOnly = 1; 22403} 22404def S4_pstorerbnewf_abs : HInst< 22405(outs), 22406(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8), 22407"if (!$Pv4) memb(#$Ii) = $Nt8.new", 22408tc_4b68bce4, TypeST>, Enc_44215c, AddrModeRel { 22409let Inst{2-2} = 0b1; 22410let Inst{7-7} = 0b1; 22411let Inst{13-11} = 0b000; 22412let Inst{31-18} = 0b10101111101000; 22413let isPredicated = 1; 22414let isPredicatedFalse = 1; 22415let addrMode = Absolute; 22416let accessSize = ByteAccess; 22417let isNVStore = 1; 22418let isNewValue = 1; 22419let isExtended = 1; 22420let isRestrictNoSlot1Store = 1; 22421let mayStore = 1; 22422let CextOpcode = "S2_storerb"; 22423let BaseOpcode = "S2_storerbabs"; 22424let DecoderNamespace = "MustExtend"; 22425let isExtendable = 1; 22426let opExtendable = 1; 22427let isExtentSigned = 0; 22428let opExtentBits = 6; 22429let opExtentAlign = 0; 22430let opNewValue = 2; 22431} 22432def S4_pstorerbnewf_rr : HInst< 22433(outs), 22434(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8), 22435"if (!$Pv4) memb($Rs32+$Ru32<<#$Ii) = $Nt8.new", 22436tc_e95795ec, TypeST>, Enc_47ee5e, AddrModeRel { 22437let Inst{4-3} = 0b00; 22438let Inst{31-21} = 0b00110101101; 22439let isPredicated = 1; 22440let isPredicatedFalse = 1; 22441let addrMode = BaseRegOffset; 22442let accessSize = ByteAccess; 22443let isNVStore = 1; 22444let isNewValue = 1; 22445let isRestrictNoSlot1Store = 1; 22446let mayStore = 1; 22447let CextOpcode = "S2_storerb"; 22448let InputType = "reg"; 22449let BaseOpcode = "S4_storerb_rr"; 22450let opNewValue = 4; 22451} 22452def S4_pstorerbnewfnew_abs : HInst< 22453(outs), 22454(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8), 22455"if (!$Pv4.new) memb(#$Ii) = $Nt8.new", 22456tc_d2e63d61, TypeST>, Enc_44215c, AddrModeRel { 22457let Inst{2-2} = 0b1; 22458let Inst{7-7} = 0b1; 22459let Inst{13-11} = 0b100; 22460let Inst{31-18} = 0b10101111101000; 22461let isPredicated = 1; 22462let isPredicatedFalse = 1; 22463let addrMode = Absolute; 22464let accessSize = ByteAccess; 22465let isNVStore = 1; 22466let isPredicatedNew = 1; 22467let isNewValue = 1; 22468let isExtended = 1; 22469let isRestrictNoSlot1Store = 1; 22470let mayStore = 1; 22471let CextOpcode = "S2_storerb"; 22472let BaseOpcode = "S2_storerbabs"; 22473let DecoderNamespace = "MustExtend"; 22474let isExtendable = 1; 22475let opExtendable = 1; 22476let isExtentSigned = 0; 22477let opExtentBits = 6; 22478let opExtentAlign = 0; 22479let opNewValue = 2; 22480} 22481def S4_pstorerbnewfnew_io : HInst< 22482(outs), 22483(ins PredRegs:$Pv4, IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Nt8), 22484"if (!$Pv4.new) memb($Rs32+#$Ii) = $Nt8.new", 22485tc_c79a189f, TypeV2LDST>, Enc_585242, AddrModeRel { 22486let Inst{2-2} = 0b0; 22487let Inst{12-11} = 0b00; 22488let Inst{31-21} = 0b01000110101; 22489let isPredicated = 1; 22490let isPredicatedFalse = 1; 22491let addrMode = BaseImmOffset; 22492let accessSize = ByteAccess; 22493let isNVStore = 1; 22494let isPredicatedNew = 1; 22495let isNewValue = 1; 22496let isRestrictNoSlot1Store = 1; 22497let mayStore = 1; 22498let CextOpcode = "S2_storerb"; 22499let InputType = "imm"; 22500let BaseOpcode = "S2_storerb_io"; 22501let isExtendable = 1; 22502let opExtendable = 2; 22503let isExtentSigned = 0; 22504let opExtentBits = 6; 22505let opExtentAlign = 0; 22506let opNewValue = 3; 22507} 22508def S4_pstorerbnewfnew_rr : HInst< 22509(outs), 22510(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8), 22511"if (!$Pv4.new) memb($Rs32+$Ru32<<#$Ii) = $Nt8.new", 22512tc_b90a29b1, TypeST>, Enc_47ee5e, AddrModeRel { 22513let Inst{4-3} = 0b00; 22514let Inst{31-21} = 0b00110111101; 22515let isPredicated = 1; 22516let isPredicatedFalse = 1; 22517let addrMode = BaseRegOffset; 22518let accessSize = ByteAccess; 22519let isNVStore = 1; 22520let isPredicatedNew = 1; 22521let isNewValue = 1; 22522let isRestrictNoSlot1Store = 1; 22523let mayStore = 1; 22524let CextOpcode = "S2_storerb"; 22525let InputType = "reg"; 22526let BaseOpcode = "S4_storerb_rr"; 22527let opNewValue = 4; 22528} 22529def S4_pstorerbnewfnew_zomap : HInst< 22530(outs), 22531(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8), 22532"if (!$Pv4.new) memb($Rs32) = $Nt8.new", 22533tc_c79a189f, TypeMAPPING> { 22534let isPseudo = 1; 22535let isCodeGenOnly = 1; 22536let opNewValue = 2; 22537} 22538def S4_pstorerbnewt_abs : HInst< 22539(outs), 22540(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8), 22541"if ($Pv4) memb(#$Ii) = $Nt8.new", 22542tc_4b68bce4, TypeST>, Enc_44215c, AddrModeRel { 22543let Inst{2-2} = 0b0; 22544let Inst{7-7} = 0b1; 22545let Inst{13-11} = 0b000; 22546let Inst{31-18} = 0b10101111101000; 22547let isPredicated = 1; 22548let addrMode = Absolute; 22549let accessSize = ByteAccess; 22550let isNVStore = 1; 22551let isNewValue = 1; 22552let isExtended = 1; 22553let isRestrictNoSlot1Store = 1; 22554let mayStore = 1; 22555let CextOpcode = "S2_storerb"; 22556let BaseOpcode = "S2_storerbabs"; 22557let DecoderNamespace = "MustExtend"; 22558let isExtendable = 1; 22559let opExtendable = 1; 22560let isExtentSigned = 0; 22561let opExtentBits = 6; 22562let opExtentAlign = 0; 22563let opNewValue = 2; 22564} 22565def S4_pstorerbnewt_rr : HInst< 22566(outs), 22567(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8), 22568"if ($Pv4) memb($Rs32+$Ru32<<#$Ii) = $Nt8.new", 22569tc_e95795ec, TypeST>, Enc_47ee5e, AddrModeRel { 22570let Inst{4-3} = 0b00; 22571let Inst{31-21} = 0b00110100101; 22572let isPredicated = 1; 22573let addrMode = BaseRegOffset; 22574let accessSize = ByteAccess; 22575let isNVStore = 1; 22576let isNewValue = 1; 22577let isRestrictNoSlot1Store = 1; 22578let mayStore = 1; 22579let CextOpcode = "S2_storerb"; 22580let InputType = "reg"; 22581let BaseOpcode = "S4_storerb_rr"; 22582let opNewValue = 4; 22583} 22584def S4_pstorerbnewtnew_abs : HInst< 22585(outs), 22586(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8), 22587"if ($Pv4.new) memb(#$Ii) = $Nt8.new", 22588tc_d2e63d61, TypeST>, Enc_44215c, AddrModeRel { 22589let Inst{2-2} = 0b0; 22590let Inst{7-7} = 0b1; 22591let Inst{13-11} = 0b100; 22592let Inst{31-18} = 0b10101111101000; 22593let isPredicated = 1; 22594let addrMode = Absolute; 22595let accessSize = ByteAccess; 22596let isNVStore = 1; 22597let isPredicatedNew = 1; 22598let isNewValue = 1; 22599let isExtended = 1; 22600let isRestrictNoSlot1Store = 1; 22601let mayStore = 1; 22602let CextOpcode = "S2_storerb"; 22603let BaseOpcode = "S2_storerbabs"; 22604let DecoderNamespace = "MustExtend"; 22605let isExtendable = 1; 22606let opExtendable = 1; 22607let isExtentSigned = 0; 22608let opExtentBits = 6; 22609let opExtentAlign = 0; 22610let opNewValue = 2; 22611} 22612def S4_pstorerbnewtnew_io : HInst< 22613(outs), 22614(ins PredRegs:$Pv4, IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Nt8), 22615"if ($Pv4.new) memb($Rs32+#$Ii) = $Nt8.new", 22616tc_c79a189f, TypeV2LDST>, Enc_585242, AddrModeRel { 22617let Inst{2-2} = 0b0; 22618let Inst{12-11} = 0b00; 22619let Inst{31-21} = 0b01000010101; 22620let isPredicated = 1; 22621let addrMode = BaseImmOffset; 22622let accessSize = ByteAccess; 22623let isNVStore = 1; 22624let isPredicatedNew = 1; 22625let isNewValue = 1; 22626let isRestrictNoSlot1Store = 1; 22627let mayStore = 1; 22628let CextOpcode = "S2_storerb"; 22629let InputType = "imm"; 22630let BaseOpcode = "S2_storerb_io"; 22631let isExtendable = 1; 22632let opExtendable = 2; 22633let isExtentSigned = 0; 22634let opExtentBits = 6; 22635let opExtentAlign = 0; 22636let opNewValue = 3; 22637} 22638def S4_pstorerbnewtnew_rr : HInst< 22639(outs), 22640(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8), 22641"if ($Pv4.new) memb($Rs32+$Ru32<<#$Ii) = $Nt8.new", 22642tc_b90a29b1, TypeST>, Enc_47ee5e, AddrModeRel { 22643let Inst{4-3} = 0b00; 22644let Inst{31-21} = 0b00110110101; 22645let isPredicated = 1; 22646let addrMode = BaseRegOffset; 22647let accessSize = ByteAccess; 22648let isNVStore = 1; 22649let isPredicatedNew = 1; 22650let isNewValue = 1; 22651let isRestrictNoSlot1Store = 1; 22652let mayStore = 1; 22653let CextOpcode = "S2_storerb"; 22654let InputType = "reg"; 22655let BaseOpcode = "S4_storerb_rr"; 22656let opNewValue = 4; 22657} 22658def S4_pstorerbnewtnew_zomap : HInst< 22659(outs), 22660(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8), 22661"if ($Pv4.new) memb($Rs32) = $Nt8.new", 22662tc_c79a189f, TypeMAPPING> { 22663let isPseudo = 1; 22664let isCodeGenOnly = 1; 22665let opNewValue = 2; 22666} 22667def S4_pstorerbt_abs : HInst< 22668(outs), 22669(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32), 22670"if ($Pv4) memb(#$Ii) = $Rt32", 22671tc_362c6592, TypeST>, Enc_1cf4ca, AddrModeRel { 22672let Inst{2-2} = 0b0; 22673let Inst{7-7} = 0b1; 22674let Inst{13-13} = 0b0; 22675let Inst{31-18} = 0b10101111000000; 22676let isPredicated = 1; 22677let addrMode = Absolute; 22678let accessSize = ByteAccess; 22679let isExtended = 1; 22680let mayStore = 1; 22681let CextOpcode = "S2_storerb"; 22682let BaseOpcode = "S2_storerbabs"; 22683let isNVStorable = 1; 22684let DecoderNamespace = "MustExtend"; 22685let isExtendable = 1; 22686let opExtendable = 1; 22687let isExtentSigned = 0; 22688let opExtentBits = 6; 22689let opExtentAlign = 0; 22690} 22691def S4_pstorerbt_rr : HInst< 22692(outs), 22693(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32), 22694"if ($Pv4) memb($Rs32+$Ru32<<#$Ii) = $Rt32", 22695tc_3962fa26, TypeST>, Enc_6339d5, AddrModeRel { 22696let Inst{31-21} = 0b00110100000; 22697let isPredicated = 1; 22698let addrMode = BaseRegOffset; 22699let accessSize = ByteAccess; 22700let mayStore = 1; 22701let CextOpcode = "S2_storerb"; 22702let InputType = "reg"; 22703let BaseOpcode = "S4_storerb_rr"; 22704let isNVStorable = 1; 22705} 22706def S4_pstorerbtnew_abs : HInst< 22707(outs), 22708(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32), 22709"if ($Pv4.new) memb(#$Ii) = $Rt32", 22710tc_da4a37ed, TypeST>, Enc_1cf4ca, AddrModeRel { 22711let Inst{2-2} = 0b0; 22712let Inst{7-7} = 0b1; 22713let Inst{13-13} = 0b1; 22714let Inst{31-18} = 0b10101111000000; 22715let isPredicated = 1; 22716let addrMode = Absolute; 22717let accessSize = ByteAccess; 22718let isPredicatedNew = 1; 22719let isExtended = 1; 22720let mayStore = 1; 22721let CextOpcode = "S2_storerb"; 22722let BaseOpcode = "S2_storerbabs"; 22723let isNVStorable = 1; 22724let DecoderNamespace = "MustExtend"; 22725let isExtendable = 1; 22726let opExtendable = 1; 22727let isExtentSigned = 0; 22728let opExtentBits = 6; 22729let opExtentAlign = 0; 22730} 22731def S4_pstorerbtnew_io : HInst< 22732(outs), 22733(ins PredRegs:$Pv4, IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Rt32), 22734"if ($Pv4.new) memb($Rs32+#$Ii) = $Rt32", 22735tc_da97ee82, TypeV2LDST>, Enc_da8d43, AddrModeRel { 22736let Inst{2-2} = 0b0; 22737let Inst{31-21} = 0b01000010000; 22738let isPredicated = 1; 22739let addrMode = BaseImmOffset; 22740let accessSize = ByteAccess; 22741let isPredicatedNew = 1; 22742let mayStore = 1; 22743let CextOpcode = "S2_storerb"; 22744let InputType = "imm"; 22745let BaseOpcode = "S2_storerb_io"; 22746let isNVStorable = 1; 22747let isExtendable = 1; 22748let opExtendable = 2; 22749let isExtentSigned = 0; 22750let opExtentBits = 6; 22751let opExtentAlign = 0; 22752} 22753def S4_pstorerbtnew_rr : HInst< 22754(outs), 22755(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32), 22756"if ($Pv4.new) memb($Rs32+$Ru32<<#$Ii) = $Rt32", 22757tc_40116ca8, TypeST>, Enc_6339d5, AddrModeRel { 22758let Inst{31-21} = 0b00110110000; 22759let isPredicated = 1; 22760let addrMode = BaseRegOffset; 22761let accessSize = ByteAccess; 22762let isPredicatedNew = 1; 22763let mayStore = 1; 22764let CextOpcode = "S2_storerb"; 22765let InputType = "reg"; 22766let BaseOpcode = "S4_storerb_rr"; 22767let isNVStorable = 1; 22768} 22769def S4_pstorerbtnew_zomap : HInst< 22770(outs), 22771(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32), 22772"if ($Pv4.new) memb($Rs32) = $Rt32", 22773tc_da97ee82, TypeMAPPING> { 22774let isPseudo = 1; 22775let isCodeGenOnly = 1; 22776} 22777def S4_pstorerdf_abs : HInst< 22778(outs), 22779(ins PredRegs:$Pv4, u32_0Imm:$Ii, DoubleRegs:$Rtt32), 22780"if (!$Pv4) memd(#$Ii) = $Rtt32", 22781tc_362c6592, TypeST>, Enc_50b5ac, AddrModeRel { 22782let Inst{2-2} = 0b1; 22783let Inst{7-7} = 0b1; 22784let Inst{13-13} = 0b0; 22785let Inst{31-18} = 0b10101111110000; 22786let isPredicated = 1; 22787let isPredicatedFalse = 1; 22788let addrMode = Absolute; 22789let accessSize = DoubleWordAccess; 22790let isExtended = 1; 22791let mayStore = 1; 22792let CextOpcode = "S2_storerd"; 22793let BaseOpcode = "S2_storerdabs"; 22794let DecoderNamespace = "MustExtend"; 22795let isExtendable = 1; 22796let opExtendable = 1; 22797let isExtentSigned = 0; 22798let opExtentBits = 6; 22799let opExtentAlign = 0; 22800} 22801def S4_pstorerdf_rr : HInst< 22802(outs), 22803(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, DoubleRegs:$Rtt32), 22804"if (!$Pv4) memd($Rs32+$Ru32<<#$Ii) = $Rtt32", 22805tc_3962fa26, TypeST>, Enc_1a9974, AddrModeRel { 22806let Inst{31-21} = 0b00110101110; 22807let isPredicated = 1; 22808let isPredicatedFalse = 1; 22809let addrMode = BaseRegOffset; 22810let accessSize = DoubleWordAccess; 22811let mayStore = 1; 22812let CextOpcode = "S2_storerd"; 22813let InputType = "reg"; 22814let BaseOpcode = "S2_storerd_rr"; 22815} 22816def S4_pstorerdfnew_abs : HInst< 22817(outs), 22818(ins PredRegs:$Pv4, u32_0Imm:$Ii, DoubleRegs:$Rtt32), 22819"if (!$Pv4.new) memd(#$Ii) = $Rtt32", 22820tc_da4a37ed, TypeST>, Enc_50b5ac, AddrModeRel { 22821let Inst{2-2} = 0b1; 22822let Inst{7-7} = 0b1; 22823let Inst{13-13} = 0b1; 22824let Inst{31-18} = 0b10101111110000; 22825let isPredicated = 1; 22826let isPredicatedFalse = 1; 22827let addrMode = Absolute; 22828let accessSize = DoubleWordAccess; 22829let isPredicatedNew = 1; 22830let isExtended = 1; 22831let mayStore = 1; 22832let CextOpcode = "S2_storerd"; 22833let BaseOpcode = "S2_storerdabs"; 22834let DecoderNamespace = "MustExtend"; 22835let isExtendable = 1; 22836let opExtendable = 1; 22837let isExtentSigned = 0; 22838let opExtentBits = 6; 22839let opExtentAlign = 0; 22840} 22841def S4_pstorerdfnew_io : HInst< 22842(outs), 22843(ins PredRegs:$Pv4, IntRegs:$Rs32, u29_3Imm:$Ii, DoubleRegs:$Rtt32), 22844"if (!$Pv4.new) memd($Rs32+#$Ii) = $Rtt32", 22845tc_da97ee82, TypeV2LDST>, Enc_57a33e, AddrModeRel { 22846let Inst{2-2} = 0b0; 22847let Inst{31-21} = 0b01000110110; 22848let isPredicated = 1; 22849let isPredicatedFalse = 1; 22850let addrMode = BaseImmOffset; 22851let accessSize = DoubleWordAccess; 22852let isPredicatedNew = 1; 22853let mayStore = 1; 22854let CextOpcode = "S2_storerd"; 22855let InputType = "imm"; 22856let BaseOpcode = "S2_storerd_io"; 22857let isExtendable = 1; 22858let opExtendable = 2; 22859let isExtentSigned = 0; 22860let opExtentBits = 9; 22861let opExtentAlign = 3; 22862} 22863def S4_pstorerdfnew_rr : HInst< 22864(outs), 22865(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, DoubleRegs:$Rtt32), 22866"if (!$Pv4.new) memd($Rs32+$Ru32<<#$Ii) = $Rtt32", 22867tc_40116ca8, TypeST>, Enc_1a9974, AddrModeRel { 22868let Inst{31-21} = 0b00110111110; 22869let isPredicated = 1; 22870let isPredicatedFalse = 1; 22871let addrMode = BaseRegOffset; 22872let accessSize = DoubleWordAccess; 22873let isPredicatedNew = 1; 22874let mayStore = 1; 22875let CextOpcode = "S2_storerd"; 22876let InputType = "reg"; 22877let BaseOpcode = "S2_storerd_rr"; 22878} 22879def S4_pstorerdfnew_zomap : HInst< 22880(outs), 22881(ins PredRegs:$Pv4, IntRegs:$Rs32, DoubleRegs:$Rtt32), 22882"if (!$Pv4.new) memd($Rs32) = $Rtt32", 22883tc_da97ee82, TypeMAPPING> { 22884let isPseudo = 1; 22885let isCodeGenOnly = 1; 22886} 22887def S4_pstorerdt_abs : HInst< 22888(outs), 22889(ins PredRegs:$Pv4, u32_0Imm:$Ii, DoubleRegs:$Rtt32), 22890"if ($Pv4) memd(#$Ii) = $Rtt32", 22891tc_362c6592, TypeST>, Enc_50b5ac, AddrModeRel { 22892let Inst{2-2} = 0b0; 22893let Inst{7-7} = 0b1; 22894let Inst{13-13} = 0b0; 22895let Inst{31-18} = 0b10101111110000; 22896let isPredicated = 1; 22897let addrMode = Absolute; 22898let accessSize = DoubleWordAccess; 22899let isExtended = 1; 22900let mayStore = 1; 22901let CextOpcode = "S2_storerd"; 22902let BaseOpcode = "S2_storerdabs"; 22903let DecoderNamespace = "MustExtend"; 22904let isExtendable = 1; 22905let opExtendable = 1; 22906let isExtentSigned = 0; 22907let opExtentBits = 6; 22908let opExtentAlign = 0; 22909} 22910def S4_pstorerdt_rr : HInst< 22911(outs), 22912(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, DoubleRegs:$Rtt32), 22913"if ($Pv4) memd($Rs32+$Ru32<<#$Ii) = $Rtt32", 22914tc_3962fa26, TypeST>, Enc_1a9974, AddrModeRel { 22915let Inst{31-21} = 0b00110100110; 22916let isPredicated = 1; 22917let addrMode = BaseRegOffset; 22918let accessSize = DoubleWordAccess; 22919let mayStore = 1; 22920let CextOpcode = "S2_storerd"; 22921let InputType = "reg"; 22922let BaseOpcode = "S2_storerd_rr"; 22923} 22924def S4_pstorerdtnew_abs : HInst< 22925(outs), 22926(ins PredRegs:$Pv4, u32_0Imm:$Ii, DoubleRegs:$Rtt32), 22927"if ($Pv4.new) memd(#$Ii) = $Rtt32", 22928tc_da4a37ed, TypeST>, Enc_50b5ac, AddrModeRel { 22929let Inst{2-2} = 0b0; 22930let Inst{7-7} = 0b1; 22931let Inst{13-13} = 0b1; 22932let Inst{31-18} = 0b10101111110000; 22933let isPredicated = 1; 22934let addrMode = Absolute; 22935let accessSize = DoubleWordAccess; 22936let isPredicatedNew = 1; 22937let isExtended = 1; 22938let mayStore = 1; 22939let CextOpcode = "S2_storerd"; 22940let BaseOpcode = "S2_storerdabs"; 22941let DecoderNamespace = "MustExtend"; 22942let isExtendable = 1; 22943let opExtendable = 1; 22944let isExtentSigned = 0; 22945let opExtentBits = 6; 22946let opExtentAlign = 0; 22947} 22948def S4_pstorerdtnew_io : HInst< 22949(outs), 22950(ins PredRegs:$Pv4, IntRegs:$Rs32, u29_3Imm:$Ii, DoubleRegs:$Rtt32), 22951"if ($Pv4.new) memd($Rs32+#$Ii) = $Rtt32", 22952tc_da97ee82, TypeV2LDST>, Enc_57a33e, AddrModeRel { 22953let Inst{2-2} = 0b0; 22954let Inst{31-21} = 0b01000010110; 22955let isPredicated = 1; 22956let addrMode = BaseImmOffset; 22957let accessSize = DoubleWordAccess; 22958let isPredicatedNew = 1; 22959let mayStore = 1; 22960let CextOpcode = "S2_storerd"; 22961let InputType = "imm"; 22962let BaseOpcode = "S2_storerd_io"; 22963let isExtendable = 1; 22964let opExtendable = 2; 22965let isExtentSigned = 0; 22966let opExtentBits = 9; 22967let opExtentAlign = 3; 22968} 22969def S4_pstorerdtnew_rr : HInst< 22970(outs), 22971(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, DoubleRegs:$Rtt32), 22972"if ($Pv4.new) memd($Rs32+$Ru32<<#$Ii) = $Rtt32", 22973tc_40116ca8, TypeST>, Enc_1a9974, AddrModeRel { 22974let Inst{31-21} = 0b00110110110; 22975let isPredicated = 1; 22976let addrMode = BaseRegOffset; 22977let accessSize = DoubleWordAccess; 22978let isPredicatedNew = 1; 22979let mayStore = 1; 22980let CextOpcode = "S2_storerd"; 22981let InputType = "reg"; 22982let BaseOpcode = "S2_storerd_rr"; 22983} 22984def S4_pstorerdtnew_zomap : HInst< 22985(outs), 22986(ins PredRegs:$Pv4, IntRegs:$Rs32, DoubleRegs:$Rtt32), 22987"if ($Pv4.new) memd($Rs32) = $Rtt32", 22988tc_da97ee82, TypeMAPPING> { 22989let isPseudo = 1; 22990let isCodeGenOnly = 1; 22991} 22992def S4_pstorerff_abs : HInst< 22993(outs), 22994(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32), 22995"if (!$Pv4) memh(#$Ii) = $Rt32.h", 22996tc_362c6592, TypeST>, Enc_1cf4ca, AddrModeRel { 22997let Inst{2-2} = 0b1; 22998let Inst{7-7} = 0b1; 22999let Inst{13-13} = 0b0; 23000let Inst{31-18} = 0b10101111011000; 23001let isPredicated = 1; 23002let isPredicatedFalse = 1; 23003let addrMode = Absolute; 23004let accessSize = HalfWordAccess; 23005let isExtended = 1; 23006let mayStore = 1; 23007let CextOpcode = "S2_storerf"; 23008let BaseOpcode = "S2_storerfabs"; 23009let DecoderNamespace = "MustExtend"; 23010let isExtendable = 1; 23011let opExtendable = 1; 23012let isExtentSigned = 0; 23013let opExtentBits = 6; 23014let opExtentAlign = 0; 23015} 23016def S4_pstorerff_rr : HInst< 23017(outs), 23018(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32), 23019"if (!$Pv4) memh($Rs32+$Ru32<<#$Ii) = $Rt32.h", 23020tc_3962fa26, TypeST>, Enc_6339d5, AddrModeRel { 23021let Inst{31-21} = 0b00110101011; 23022let isPredicated = 1; 23023let isPredicatedFalse = 1; 23024let addrMode = BaseRegOffset; 23025let accessSize = HalfWordAccess; 23026let mayStore = 1; 23027let CextOpcode = "S2_storerf"; 23028let InputType = "reg"; 23029let BaseOpcode = "S4_storerf_rr"; 23030} 23031def S4_pstorerffnew_abs : HInst< 23032(outs), 23033(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32), 23034"if (!$Pv4.new) memh(#$Ii) = $Rt32.h", 23035tc_da4a37ed, TypeST>, Enc_1cf4ca, AddrModeRel { 23036let Inst{2-2} = 0b1; 23037let Inst{7-7} = 0b1; 23038let Inst{13-13} = 0b1; 23039let Inst{31-18} = 0b10101111011000; 23040let isPredicated = 1; 23041let isPredicatedFalse = 1; 23042let addrMode = Absolute; 23043let accessSize = HalfWordAccess; 23044let isPredicatedNew = 1; 23045let isExtended = 1; 23046let mayStore = 1; 23047let CextOpcode = "S2_storerf"; 23048let BaseOpcode = "S2_storerfabs"; 23049let DecoderNamespace = "MustExtend"; 23050let isExtendable = 1; 23051let opExtendable = 1; 23052let isExtentSigned = 0; 23053let opExtentBits = 6; 23054let opExtentAlign = 0; 23055} 23056def S4_pstorerffnew_io : HInst< 23057(outs), 23058(ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32), 23059"if (!$Pv4.new) memh($Rs32+#$Ii) = $Rt32.h", 23060tc_da97ee82, TypeV2LDST>, Enc_e8c45e, AddrModeRel { 23061let Inst{2-2} = 0b0; 23062let Inst{31-21} = 0b01000110011; 23063let isPredicated = 1; 23064let isPredicatedFalse = 1; 23065let addrMode = BaseImmOffset; 23066let accessSize = HalfWordAccess; 23067let isPredicatedNew = 1; 23068let mayStore = 1; 23069let CextOpcode = "S2_storerf"; 23070let InputType = "imm"; 23071let BaseOpcode = "S2_storerf_io"; 23072let isExtendable = 1; 23073let opExtendable = 2; 23074let isExtentSigned = 0; 23075let opExtentBits = 7; 23076let opExtentAlign = 1; 23077} 23078def S4_pstorerffnew_rr : HInst< 23079(outs), 23080(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32), 23081"if (!$Pv4.new) memh($Rs32+$Ru32<<#$Ii) = $Rt32.h", 23082tc_40116ca8, TypeST>, Enc_6339d5, AddrModeRel { 23083let Inst{31-21} = 0b00110111011; 23084let isPredicated = 1; 23085let isPredicatedFalse = 1; 23086let addrMode = BaseRegOffset; 23087let accessSize = HalfWordAccess; 23088let isPredicatedNew = 1; 23089let mayStore = 1; 23090let CextOpcode = "S2_storerf"; 23091let InputType = "reg"; 23092let BaseOpcode = "S4_storerf_rr"; 23093} 23094def S4_pstorerffnew_zomap : HInst< 23095(outs), 23096(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32), 23097"if (!$Pv4.new) memh($Rs32) = $Rt32.h", 23098tc_da97ee82, TypeMAPPING> { 23099let isPseudo = 1; 23100let isCodeGenOnly = 1; 23101} 23102def S4_pstorerft_abs : HInst< 23103(outs), 23104(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32), 23105"if ($Pv4) memh(#$Ii) = $Rt32.h", 23106tc_362c6592, TypeST>, Enc_1cf4ca, AddrModeRel { 23107let Inst{2-2} = 0b0; 23108let Inst{7-7} = 0b1; 23109let Inst{13-13} = 0b0; 23110let Inst{31-18} = 0b10101111011000; 23111let isPredicated = 1; 23112let addrMode = Absolute; 23113let accessSize = HalfWordAccess; 23114let isExtended = 1; 23115let mayStore = 1; 23116let CextOpcode = "S2_storerf"; 23117let BaseOpcode = "S2_storerfabs"; 23118let DecoderNamespace = "MustExtend"; 23119let isExtendable = 1; 23120let opExtendable = 1; 23121let isExtentSigned = 0; 23122let opExtentBits = 6; 23123let opExtentAlign = 0; 23124} 23125def S4_pstorerft_rr : HInst< 23126(outs), 23127(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32), 23128"if ($Pv4) memh($Rs32+$Ru32<<#$Ii) = $Rt32.h", 23129tc_3962fa26, TypeST>, Enc_6339d5, AddrModeRel { 23130let Inst{31-21} = 0b00110100011; 23131let isPredicated = 1; 23132let addrMode = BaseRegOffset; 23133let accessSize = HalfWordAccess; 23134let mayStore = 1; 23135let CextOpcode = "S2_storerf"; 23136let InputType = "reg"; 23137let BaseOpcode = "S4_storerf_rr"; 23138} 23139def S4_pstorerftnew_abs : HInst< 23140(outs), 23141(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32), 23142"if ($Pv4.new) memh(#$Ii) = $Rt32.h", 23143tc_da4a37ed, TypeST>, Enc_1cf4ca, AddrModeRel { 23144let Inst{2-2} = 0b0; 23145let Inst{7-7} = 0b1; 23146let Inst{13-13} = 0b1; 23147let Inst{31-18} = 0b10101111011000; 23148let isPredicated = 1; 23149let addrMode = Absolute; 23150let accessSize = HalfWordAccess; 23151let isPredicatedNew = 1; 23152let isExtended = 1; 23153let mayStore = 1; 23154let CextOpcode = "S2_storerf"; 23155let BaseOpcode = "S2_storerfabs"; 23156let DecoderNamespace = "MustExtend"; 23157let isExtendable = 1; 23158let opExtendable = 1; 23159let isExtentSigned = 0; 23160let opExtentBits = 6; 23161let opExtentAlign = 0; 23162} 23163def S4_pstorerftnew_io : HInst< 23164(outs), 23165(ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32), 23166"if ($Pv4.new) memh($Rs32+#$Ii) = $Rt32.h", 23167tc_da97ee82, TypeV2LDST>, Enc_e8c45e, AddrModeRel { 23168let Inst{2-2} = 0b0; 23169let Inst{31-21} = 0b01000010011; 23170let isPredicated = 1; 23171let addrMode = BaseImmOffset; 23172let accessSize = HalfWordAccess; 23173let isPredicatedNew = 1; 23174let mayStore = 1; 23175let CextOpcode = "S2_storerf"; 23176let InputType = "imm"; 23177let BaseOpcode = "S2_storerf_io"; 23178let isExtendable = 1; 23179let opExtendable = 2; 23180let isExtentSigned = 0; 23181let opExtentBits = 7; 23182let opExtentAlign = 1; 23183} 23184def S4_pstorerftnew_rr : HInst< 23185(outs), 23186(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32), 23187"if ($Pv4.new) memh($Rs32+$Ru32<<#$Ii) = $Rt32.h", 23188tc_40116ca8, TypeST>, Enc_6339d5, AddrModeRel { 23189let Inst{31-21} = 0b00110110011; 23190let isPredicated = 1; 23191let addrMode = BaseRegOffset; 23192let accessSize = HalfWordAccess; 23193let isPredicatedNew = 1; 23194let mayStore = 1; 23195let CextOpcode = "S2_storerf"; 23196let InputType = "reg"; 23197let BaseOpcode = "S4_storerf_rr"; 23198} 23199def S4_pstorerftnew_zomap : HInst< 23200(outs), 23201(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32), 23202"if ($Pv4.new) memh($Rs32) = $Rt32.h", 23203tc_da97ee82, TypeMAPPING> { 23204let isPseudo = 1; 23205let isCodeGenOnly = 1; 23206} 23207def S4_pstorerhf_abs : HInst< 23208(outs), 23209(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32), 23210"if (!$Pv4) memh(#$Ii) = $Rt32", 23211tc_362c6592, TypeST>, Enc_1cf4ca, AddrModeRel { 23212let Inst{2-2} = 0b1; 23213let Inst{7-7} = 0b1; 23214let Inst{13-13} = 0b0; 23215let Inst{31-18} = 0b10101111010000; 23216let isPredicated = 1; 23217let isPredicatedFalse = 1; 23218let addrMode = Absolute; 23219let accessSize = HalfWordAccess; 23220let isExtended = 1; 23221let mayStore = 1; 23222let CextOpcode = "S2_storerh"; 23223let BaseOpcode = "S2_storerhabs"; 23224let isNVStorable = 1; 23225let DecoderNamespace = "MustExtend"; 23226let isExtendable = 1; 23227let opExtendable = 1; 23228let isExtentSigned = 0; 23229let opExtentBits = 6; 23230let opExtentAlign = 0; 23231} 23232def S4_pstorerhf_rr : HInst< 23233(outs), 23234(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32), 23235"if (!$Pv4) memh($Rs32+$Ru32<<#$Ii) = $Rt32", 23236tc_3962fa26, TypeST>, Enc_6339d5, AddrModeRel { 23237let Inst{31-21} = 0b00110101010; 23238let isPredicated = 1; 23239let isPredicatedFalse = 1; 23240let addrMode = BaseRegOffset; 23241let accessSize = HalfWordAccess; 23242let mayStore = 1; 23243let CextOpcode = "S2_storerh"; 23244let InputType = "reg"; 23245let BaseOpcode = "S2_storerh_rr"; 23246let isNVStorable = 1; 23247} 23248def S4_pstorerhfnew_abs : HInst< 23249(outs), 23250(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32), 23251"if (!$Pv4.new) memh(#$Ii) = $Rt32", 23252tc_da4a37ed, TypeST>, Enc_1cf4ca, AddrModeRel { 23253let Inst{2-2} = 0b1; 23254let Inst{7-7} = 0b1; 23255let Inst{13-13} = 0b1; 23256let Inst{31-18} = 0b10101111010000; 23257let isPredicated = 1; 23258let isPredicatedFalse = 1; 23259let addrMode = Absolute; 23260let accessSize = HalfWordAccess; 23261let isPredicatedNew = 1; 23262let isExtended = 1; 23263let mayStore = 1; 23264let CextOpcode = "S2_storerh"; 23265let BaseOpcode = "S2_storerhabs"; 23266let isNVStorable = 1; 23267let DecoderNamespace = "MustExtend"; 23268let isExtendable = 1; 23269let opExtendable = 1; 23270let isExtentSigned = 0; 23271let opExtentBits = 6; 23272let opExtentAlign = 0; 23273} 23274def S4_pstorerhfnew_io : HInst< 23275(outs), 23276(ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32), 23277"if (!$Pv4.new) memh($Rs32+#$Ii) = $Rt32", 23278tc_da97ee82, TypeV2LDST>, Enc_e8c45e, AddrModeRel { 23279let Inst{2-2} = 0b0; 23280let Inst{31-21} = 0b01000110010; 23281let isPredicated = 1; 23282let isPredicatedFalse = 1; 23283let addrMode = BaseImmOffset; 23284let accessSize = HalfWordAccess; 23285let isPredicatedNew = 1; 23286let mayStore = 1; 23287let CextOpcode = "S2_storerh"; 23288let InputType = "imm"; 23289let BaseOpcode = "S2_storerh_io"; 23290let isNVStorable = 1; 23291let isExtendable = 1; 23292let opExtendable = 2; 23293let isExtentSigned = 0; 23294let opExtentBits = 7; 23295let opExtentAlign = 1; 23296} 23297def S4_pstorerhfnew_rr : HInst< 23298(outs), 23299(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32), 23300"if (!$Pv4.new) memh($Rs32+$Ru32<<#$Ii) = $Rt32", 23301tc_40116ca8, TypeST>, Enc_6339d5, AddrModeRel { 23302let Inst{31-21} = 0b00110111010; 23303let isPredicated = 1; 23304let isPredicatedFalse = 1; 23305let addrMode = BaseRegOffset; 23306let accessSize = HalfWordAccess; 23307let isPredicatedNew = 1; 23308let mayStore = 1; 23309let CextOpcode = "S2_storerh"; 23310let InputType = "reg"; 23311let BaseOpcode = "S2_storerh_rr"; 23312let isNVStorable = 1; 23313} 23314def S4_pstorerhfnew_zomap : HInst< 23315(outs), 23316(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32), 23317"if (!$Pv4.new) memh($Rs32) = $Rt32", 23318tc_da97ee82, TypeMAPPING> { 23319let isPseudo = 1; 23320let isCodeGenOnly = 1; 23321} 23322def S4_pstorerhnewf_abs : HInst< 23323(outs), 23324(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8), 23325"if (!$Pv4) memh(#$Ii) = $Nt8.new", 23326tc_4b68bce4, TypeST>, Enc_44215c, AddrModeRel { 23327let Inst{2-2} = 0b1; 23328let Inst{7-7} = 0b1; 23329let Inst{13-11} = 0b001; 23330let Inst{31-18} = 0b10101111101000; 23331let isPredicated = 1; 23332let isPredicatedFalse = 1; 23333let addrMode = Absolute; 23334let accessSize = HalfWordAccess; 23335let isNVStore = 1; 23336let isNewValue = 1; 23337let isExtended = 1; 23338let isRestrictNoSlot1Store = 1; 23339let mayStore = 1; 23340let CextOpcode = "S2_storerh"; 23341let BaseOpcode = "S2_storerhabs"; 23342let DecoderNamespace = "MustExtend"; 23343let isExtendable = 1; 23344let opExtendable = 1; 23345let isExtentSigned = 0; 23346let opExtentBits = 6; 23347let opExtentAlign = 0; 23348let opNewValue = 2; 23349} 23350def S4_pstorerhnewf_rr : HInst< 23351(outs), 23352(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8), 23353"if (!$Pv4) memh($Rs32+$Ru32<<#$Ii) = $Nt8.new", 23354tc_e95795ec, TypeST>, Enc_47ee5e, AddrModeRel { 23355let Inst{4-3} = 0b01; 23356let Inst{31-21} = 0b00110101101; 23357let isPredicated = 1; 23358let isPredicatedFalse = 1; 23359let addrMode = BaseRegOffset; 23360let accessSize = HalfWordAccess; 23361let isNVStore = 1; 23362let isNewValue = 1; 23363let isRestrictNoSlot1Store = 1; 23364let mayStore = 1; 23365let CextOpcode = "S2_storerh"; 23366let InputType = "reg"; 23367let BaseOpcode = "S2_storerh_rr"; 23368let opNewValue = 4; 23369} 23370def S4_pstorerhnewfnew_abs : HInst< 23371(outs), 23372(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8), 23373"if (!$Pv4.new) memh(#$Ii) = $Nt8.new", 23374tc_d2e63d61, TypeST>, Enc_44215c, AddrModeRel { 23375let Inst{2-2} = 0b1; 23376let Inst{7-7} = 0b1; 23377let Inst{13-11} = 0b101; 23378let Inst{31-18} = 0b10101111101000; 23379let isPredicated = 1; 23380let isPredicatedFalse = 1; 23381let addrMode = Absolute; 23382let accessSize = HalfWordAccess; 23383let isNVStore = 1; 23384let isPredicatedNew = 1; 23385let isNewValue = 1; 23386let isExtended = 1; 23387let isRestrictNoSlot1Store = 1; 23388let mayStore = 1; 23389let CextOpcode = "S2_storerh"; 23390let BaseOpcode = "S2_storerhabs"; 23391let DecoderNamespace = "MustExtend"; 23392let isExtendable = 1; 23393let opExtendable = 1; 23394let isExtentSigned = 0; 23395let opExtentBits = 6; 23396let opExtentAlign = 0; 23397let opNewValue = 2; 23398} 23399def S4_pstorerhnewfnew_io : HInst< 23400(outs), 23401(ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Nt8), 23402"if (!$Pv4.new) memh($Rs32+#$Ii) = $Nt8.new", 23403tc_c79a189f, TypeV2LDST>, Enc_f44229, AddrModeRel { 23404let Inst{2-2} = 0b0; 23405let Inst{12-11} = 0b01; 23406let Inst{31-21} = 0b01000110101; 23407let isPredicated = 1; 23408let isPredicatedFalse = 1; 23409let addrMode = BaseImmOffset; 23410let accessSize = HalfWordAccess; 23411let isNVStore = 1; 23412let isPredicatedNew = 1; 23413let isNewValue = 1; 23414let isRestrictNoSlot1Store = 1; 23415let mayStore = 1; 23416let CextOpcode = "S2_storerh"; 23417let InputType = "imm"; 23418let BaseOpcode = "S2_storerh_io"; 23419let isExtendable = 1; 23420let opExtendable = 2; 23421let isExtentSigned = 0; 23422let opExtentBits = 7; 23423let opExtentAlign = 1; 23424let opNewValue = 3; 23425} 23426def S4_pstorerhnewfnew_rr : HInst< 23427(outs), 23428(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8), 23429"if (!$Pv4.new) memh($Rs32+$Ru32<<#$Ii) = $Nt8.new", 23430tc_b90a29b1, TypeST>, Enc_47ee5e, AddrModeRel { 23431let Inst{4-3} = 0b01; 23432let Inst{31-21} = 0b00110111101; 23433let isPredicated = 1; 23434let isPredicatedFalse = 1; 23435let addrMode = BaseRegOffset; 23436let accessSize = HalfWordAccess; 23437let isNVStore = 1; 23438let isPredicatedNew = 1; 23439let isNewValue = 1; 23440let isRestrictNoSlot1Store = 1; 23441let mayStore = 1; 23442let CextOpcode = "S2_storerh"; 23443let InputType = "reg"; 23444let BaseOpcode = "S2_storerh_rr"; 23445let opNewValue = 4; 23446} 23447def S4_pstorerhnewfnew_zomap : HInst< 23448(outs), 23449(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8), 23450"if (!$Pv4.new) memh($Rs32) = $Nt8.new", 23451tc_c79a189f, TypeMAPPING> { 23452let isPseudo = 1; 23453let isCodeGenOnly = 1; 23454let opNewValue = 2; 23455} 23456def S4_pstorerhnewt_abs : HInst< 23457(outs), 23458(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8), 23459"if ($Pv4) memh(#$Ii) = $Nt8.new", 23460tc_4b68bce4, TypeST>, Enc_44215c, AddrModeRel { 23461let Inst{2-2} = 0b0; 23462let Inst{7-7} = 0b1; 23463let Inst{13-11} = 0b001; 23464let Inst{31-18} = 0b10101111101000; 23465let isPredicated = 1; 23466let addrMode = Absolute; 23467let accessSize = HalfWordAccess; 23468let isNVStore = 1; 23469let isNewValue = 1; 23470let isExtended = 1; 23471let isRestrictNoSlot1Store = 1; 23472let mayStore = 1; 23473let CextOpcode = "S2_storerh"; 23474let BaseOpcode = "S2_storerhabs"; 23475let DecoderNamespace = "MustExtend"; 23476let isExtendable = 1; 23477let opExtendable = 1; 23478let isExtentSigned = 0; 23479let opExtentBits = 6; 23480let opExtentAlign = 0; 23481let opNewValue = 2; 23482} 23483def S4_pstorerhnewt_rr : HInst< 23484(outs), 23485(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8), 23486"if ($Pv4) memh($Rs32+$Ru32<<#$Ii) = $Nt8.new", 23487tc_e95795ec, TypeST>, Enc_47ee5e, AddrModeRel { 23488let Inst{4-3} = 0b01; 23489let Inst{31-21} = 0b00110100101; 23490let isPredicated = 1; 23491let addrMode = BaseRegOffset; 23492let accessSize = HalfWordAccess; 23493let isNVStore = 1; 23494let isNewValue = 1; 23495let isRestrictNoSlot1Store = 1; 23496let mayStore = 1; 23497let CextOpcode = "S2_storerh"; 23498let InputType = "reg"; 23499let BaseOpcode = "S2_storerh_rr"; 23500let opNewValue = 4; 23501} 23502def S4_pstorerhnewtnew_abs : HInst< 23503(outs), 23504(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8), 23505"if ($Pv4.new) memh(#$Ii) = $Nt8.new", 23506tc_d2e63d61, TypeST>, Enc_44215c, AddrModeRel { 23507let Inst{2-2} = 0b0; 23508let Inst{7-7} = 0b1; 23509let Inst{13-11} = 0b101; 23510let Inst{31-18} = 0b10101111101000; 23511let isPredicated = 1; 23512let addrMode = Absolute; 23513let accessSize = HalfWordAccess; 23514let isNVStore = 1; 23515let isPredicatedNew = 1; 23516let isNewValue = 1; 23517let isExtended = 1; 23518let isRestrictNoSlot1Store = 1; 23519let mayStore = 1; 23520let CextOpcode = "S2_storerh"; 23521let BaseOpcode = "S2_storerhabs"; 23522let DecoderNamespace = "MustExtend"; 23523let isExtendable = 1; 23524let opExtendable = 1; 23525let isExtentSigned = 0; 23526let opExtentBits = 6; 23527let opExtentAlign = 0; 23528let opNewValue = 2; 23529} 23530def S4_pstorerhnewtnew_io : HInst< 23531(outs), 23532(ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Nt8), 23533"if ($Pv4.new) memh($Rs32+#$Ii) = $Nt8.new", 23534tc_c79a189f, TypeV2LDST>, Enc_f44229, AddrModeRel { 23535let Inst{2-2} = 0b0; 23536let Inst{12-11} = 0b01; 23537let Inst{31-21} = 0b01000010101; 23538let isPredicated = 1; 23539let addrMode = BaseImmOffset; 23540let accessSize = HalfWordAccess; 23541let isNVStore = 1; 23542let isPredicatedNew = 1; 23543let isNewValue = 1; 23544let isRestrictNoSlot1Store = 1; 23545let mayStore = 1; 23546let CextOpcode = "S2_storerh"; 23547let InputType = "imm"; 23548let BaseOpcode = "S2_storerh_io"; 23549let isExtendable = 1; 23550let opExtendable = 2; 23551let isExtentSigned = 0; 23552let opExtentBits = 7; 23553let opExtentAlign = 1; 23554let opNewValue = 3; 23555} 23556def S4_pstorerhnewtnew_rr : HInst< 23557(outs), 23558(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8), 23559"if ($Pv4.new) memh($Rs32+$Ru32<<#$Ii) = $Nt8.new", 23560tc_b90a29b1, TypeST>, Enc_47ee5e, AddrModeRel { 23561let Inst{4-3} = 0b01; 23562let Inst{31-21} = 0b00110110101; 23563let isPredicated = 1; 23564let addrMode = BaseRegOffset; 23565let accessSize = HalfWordAccess; 23566let isNVStore = 1; 23567let isPredicatedNew = 1; 23568let isNewValue = 1; 23569let isRestrictNoSlot1Store = 1; 23570let mayStore = 1; 23571let CextOpcode = "S2_storerh"; 23572let InputType = "reg"; 23573let BaseOpcode = "S2_storerh_rr"; 23574let opNewValue = 4; 23575} 23576def S4_pstorerhnewtnew_zomap : HInst< 23577(outs), 23578(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8), 23579"if ($Pv4.new) memh($Rs32) = $Nt8.new", 23580tc_c79a189f, TypeMAPPING> { 23581let isPseudo = 1; 23582let isCodeGenOnly = 1; 23583let opNewValue = 2; 23584} 23585def S4_pstorerht_abs : HInst< 23586(outs), 23587(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32), 23588"if ($Pv4) memh(#$Ii) = $Rt32", 23589tc_362c6592, TypeST>, Enc_1cf4ca, AddrModeRel { 23590let Inst{2-2} = 0b0; 23591let Inst{7-7} = 0b1; 23592let Inst{13-13} = 0b0; 23593let Inst{31-18} = 0b10101111010000; 23594let isPredicated = 1; 23595let addrMode = Absolute; 23596let accessSize = HalfWordAccess; 23597let isExtended = 1; 23598let mayStore = 1; 23599let CextOpcode = "S2_storerh"; 23600let BaseOpcode = "S2_storerhabs"; 23601let isNVStorable = 1; 23602let DecoderNamespace = "MustExtend"; 23603let isExtendable = 1; 23604let opExtendable = 1; 23605let isExtentSigned = 0; 23606let opExtentBits = 6; 23607let opExtentAlign = 0; 23608} 23609def S4_pstorerht_rr : HInst< 23610(outs), 23611(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32), 23612"if ($Pv4) memh($Rs32+$Ru32<<#$Ii) = $Rt32", 23613tc_3962fa26, TypeST>, Enc_6339d5, AddrModeRel { 23614let Inst{31-21} = 0b00110100010; 23615let isPredicated = 1; 23616let addrMode = BaseRegOffset; 23617let accessSize = HalfWordAccess; 23618let mayStore = 1; 23619let CextOpcode = "S2_storerh"; 23620let InputType = "reg"; 23621let BaseOpcode = "S2_storerh_rr"; 23622let isNVStorable = 1; 23623} 23624def S4_pstorerhtnew_abs : HInst< 23625(outs), 23626(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32), 23627"if ($Pv4.new) memh(#$Ii) = $Rt32", 23628tc_da4a37ed, TypeST>, Enc_1cf4ca, AddrModeRel { 23629let Inst{2-2} = 0b0; 23630let Inst{7-7} = 0b1; 23631let Inst{13-13} = 0b1; 23632let Inst{31-18} = 0b10101111010000; 23633let isPredicated = 1; 23634let addrMode = Absolute; 23635let accessSize = HalfWordAccess; 23636let isPredicatedNew = 1; 23637let isExtended = 1; 23638let mayStore = 1; 23639let CextOpcode = "S2_storerh"; 23640let BaseOpcode = "S2_storerhabs"; 23641let isNVStorable = 1; 23642let DecoderNamespace = "MustExtend"; 23643let isExtendable = 1; 23644let opExtendable = 1; 23645let isExtentSigned = 0; 23646let opExtentBits = 6; 23647let opExtentAlign = 0; 23648} 23649def S4_pstorerhtnew_io : HInst< 23650(outs), 23651(ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32), 23652"if ($Pv4.new) memh($Rs32+#$Ii) = $Rt32", 23653tc_da97ee82, TypeV2LDST>, Enc_e8c45e, AddrModeRel { 23654let Inst{2-2} = 0b0; 23655let Inst{31-21} = 0b01000010010; 23656let isPredicated = 1; 23657let addrMode = BaseImmOffset; 23658let accessSize = HalfWordAccess; 23659let isPredicatedNew = 1; 23660let mayStore = 1; 23661let CextOpcode = "S2_storerh"; 23662let InputType = "imm"; 23663let BaseOpcode = "S2_storerh_io"; 23664let isNVStorable = 1; 23665let isExtendable = 1; 23666let opExtendable = 2; 23667let isExtentSigned = 0; 23668let opExtentBits = 7; 23669let opExtentAlign = 1; 23670} 23671def S4_pstorerhtnew_rr : HInst< 23672(outs), 23673(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32), 23674"if ($Pv4.new) memh($Rs32+$Ru32<<#$Ii) = $Rt32", 23675tc_40116ca8, TypeST>, Enc_6339d5, AddrModeRel { 23676let Inst{31-21} = 0b00110110010; 23677let isPredicated = 1; 23678let addrMode = BaseRegOffset; 23679let accessSize = HalfWordAccess; 23680let isPredicatedNew = 1; 23681let mayStore = 1; 23682let CextOpcode = "S2_storerh"; 23683let InputType = "reg"; 23684let BaseOpcode = "S2_storerh_rr"; 23685let isNVStorable = 1; 23686} 23687def S4_pstorerhtnew_zomap : HInst< 23688(outs), 23689(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32), 23690"if ($Pv4.new) memh($Rs32) = $Rt32", 23691tc_da97ee82, TypeMAPPING> { 23692let isPseudo = 1; 23693let isCodeGenOnly = 1; 23694} 23695def S4_pstorerif_abs : HInst< 23696(outs), 23697(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32), 23698"if (!$Pv4) memw(#$Ii) = $Rt32", 23699tc_362c6592, TypeST>, Enc_1cf4ca, AddrModeRel { 23700let Inst{2-2} = 0b1; 23701let Inst{7-7} = 0b1; 23702let Inst{13-13} = 0b0; 23703let Inst{31-18} = 0b10101111100000; 23704let isPredicated = 1; 23705let isPredicatedFalse = 1; 23706let addrMode = Absolute; 23707let accessSize = WordAccess; 23708let isExtended = 1; 23709let mayStore = 1; 23710let CextOpcode = "S2_storeri"; 23711let BaseOpcode = "S2_storeriabs"; 23712let isNVStorable = 1; 23713let DecoderNamespace = "MustExtend"; 23714let isExtendable = 1; 23715let opExtendable = 1; 23716let isExtentSigned = 0; 23717let opExtentBits = 6; 23718let opExtentAlign = 0; 23719} 23720def S4_pstorerif_rr : HInst< 23721(outs), 23722(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32), 23723"if (!$Pv4) memw($Rs32+$Ru32<<#$Ii) = $Rt32", 23724tc_3962fa26, TypeST>, Enc_6339d5, AddrModeRel { 23725let Inst{31-21} = 0b00110101100; 23726let isPredicated = 1; 23727let isPredicatedFalse = 1; 23728let addrMode = BaseRegOffset; 23729let accessSize = WordAccess; 23730let mayStore = 1; 23731let CextOpcode = "S2_storeri"; 23732let InputType = "reg"; 23733let BaseOpcode = "S2_storeri_rr"; 23734let isNVStorable = 1; 23735} 23736def S4_pstorerifnew_abs : HInst< 23737(outs), 23738(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32), 23739"if (!$Pv4.new) memw(#$Ii) = $Rt32", 23740tc_da4a37ed, TypeST>, Enc_1cf4ca, AddrModeRel { 23741let Inst{2-2} = 0b1; 23742let Inst{7-7} = 0b1; 23743let Inst{13-13} = 0b1; 23744let Inst{31-18} = 0b10101111100000; 23745let isPredicated = 1; 23746let isPredicatedFalse = 1; 23747let addrMode = Absolute; 23748let accessSize = WordAccess; 23749let isPredicatedNew = 1; 23750let isExtended = 1; 23751let mayStore = 1; 23752let CextOpcode = "S2_storeri"; 23753let BaseOpcode = "S2_storeriabs"; 23754let isNVStorable = 1; 23755let DecoderNamespace = "MustExtend"; 23756let isExtendable = 1; 23757let opExtendable = 1; 23758let isExtentSigned = 0; 23759let opExtentBits = 6; 23760let opExtentAlign = 0; 23761} 23762def S4_pstorerifnew_io : HInst< 23763(outs), 23764(ins PredRegs:$Pv4, IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Rt32), 23765"if (!$Pv4.new) memw($Rs32+#$Ii) = $Rt32", 23766tc_da97ee82, TypeV2LDST>, Enc_397f23, AddrModeRel { 23767let Inst{2-2} = 0b0; 23768let Inst{31-21} = 0b01000110100; 23769let isPredicated = 1; 23770let isPredicatedFalse = 1; 23771let addrMode = BaseImmOffset; 23772let accessSize = WordAccess; 23773let isPredicatedNew = 1; 23774let mayStore = 1; 23775let CextOpcode = "S2_storeri"; 23776let InputType = "imm"; 23777let BaseOpcode = "S2_storeri_io"; 23778let isNVStorable = 1; 23779let isExtendable = 1; 23780let opExtendable = 2; 23781let isExtentSigned = 0; 23782let opExtentBits = 8; 23783let opExtentAlign = 2; 23784} 23785def S4_pstorerifnew_rr : HInst< 23786(outs), 23787(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32), 23788"if (!$Pv4.new) memw($Rs32+$Ru32<<#$Ii) = $Rt32", 23789tc_40116ca8, TypeST>, Enc_6339d5, AddrModeRel { 23790let Inst{31-21} = 0b00110111100; 23791let isPredicated = 1; 23792let isPredicatedFalse = 1; 23793let addrMode = BaseRegOffset; 23794let accessSize = WordAccess; 23795let isPredicatedNew = 1; 23796let mayStore = 1; 23797let CextOpcode = "S2_storeri"; 23798let InputType = "reg"; 23799let BaseOpcode = "S2_storeri_rr"; 23800let isNVStorable = 1; 23801} 23802def S4_pstorerifnew_zomap : HInst< 23803(outs), 23804(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32), 23805"if (!$Pv4.new) memw($Rs32) = $Rt32", 23806tc_da97ee82, TypeMAPPING> { 23807let isPseudo = 1; 23808let isCodeGenOnly = 1; 23809} 23810def S4_pstorerinewf_abs : HInst< 23811(outs), 23812(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8), 23813"if (!$Pv4) memw(#$Ii) = $Nt8.new", 23814tc_4b68bce4, TypeST>, Enc_44215c, AddrModeRel { 23815let Inst{2-2} = 0b1; 23816let Inst{7-7} = 0b1; 23817let Inst{13-11} = 0b010; 23818let Inst{31-18} = 0b10101111101000; 23819let isPredicated = 1; 23820let isPredicatedFalse = 1; 23821let addrMode = Absolute; 23822let accessSize = WordAccess; 23823let isNVStore = 1; 23824let isNewValue = 1; 23825let isExtended = 1; 23826let isRestrictNoSlot1Store = 1; 23827let mayStore = 1; 23828let CextOpcode = "S2_storeri"; 23829let BaseOpcode = "S2_storeriabs"; 23830let DecoderNamespace = "MustExtend"; 23831let isExtendable = 1; 23832let opExtendable = 1; 23833let isExtentSigned = 0; 23834let opExtentBits = 6; 23835let opExtentAlign = 0; 23836let opNewValue = 2; 23837} 23838def S4_pstorerinewf_rr : HInst< 23839(outs), 23840(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8), 23841"if (!$Pv4) memw($Rs32+$Ru32<<#$Ii) = $Nt8.new", 23842tc_e95795ec, TypeST>, Enc_47ee5e, AddrModeRel { 23843let Inst{4-3} = 0b10; 23844let Inst{31-21} = 0b00110101101; 23845let isPredicated = 1; 23846let isPredicatedFalse = 1; 23847let addrMode = BaseRegOffset; 23848let accessSize = WordAccess; 23849let isNVStore = 1; 23850let isNewValue = 1; 23851let isRestrictNoSlot1Store = 1; 23852let mayStore = 1; 23853let CextOpcode = "S2_storeri"; 23854let InputType = "reg"; 23855let BaseOpcode = "S2_storeri_rr"; 23856let opNewValue = 4; 23857} 23858def S4_pstorerinewfnew_abs : HInst< 23859(outs), 23860(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8), 23861"if (!$Pv4.new) memw(#$Ii) = $Nt8.new", 23862tc_d2e63d61, TypeST>, Enc_44215c, AddrModeRel { 23863let Inst{2-2} = 0b1; 23864let Inst{7-7} = 0b1; 23865let Inst{13-11} = 0b110; 23866let Inst{31-18} = 0b10101111101000; 23867let isPredicated = 1; 23868let isPredicatedFalse = 1; 23869let addrMode = Absolute; 23870let accessSize = WordAccess; 23871let isNVStore = 1; 23872let isPredicatedNew = 1; 23873let isNewValue = 1; 23874let isExtended = 1; 23875let isRestrictNoSlot1Store = 1; 23876let mayStore = 1; 23877let CextOpcode = "S2_storeri"; 23878let BaseOpcode = "S2_storeriabs"; 23879let DecoderNamespace = "MustExtend"; 23880let isExtendable = 1; 23881let opExtendable = 1; 23882let isExtentSigned = 0; 23883let opExtentBits = 6; 23884let opExtentAlign = 0; 23885let opNewValue = 2; 23886} 23887def S4_pstorerinewfnew_io : HInst< 23888(outs), 23889(ins PredRegs:$Pv4, IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Nt8), 23890"if (!$Pv4.new) memw($Rs32+#$Ii) = $Nt8.new", 23891tc_c79a189f, TypeV2LDST>, Enc_8dbdfe, AddrModeRel { 23892let Inst{2-2} = 0b0; 23893let Inst{12-11} = 0b10; 23894let Inst{31-21} = 0b01000110101; 23895let isPredicated = 1; 23896let isPredicatedFalse = 1; 23897let addrMode = BaseImmOffset; 23898let accessSize = WordAccess; 23899let isNVStore = 1; 23900let isPredicatedNew = 1; 23901let isNewValue = 1; 23902let isRestrictNoSlot1Store = 1; 23903let mayStore = 1; 23904let CextOpcode = "S2_storeri"; 23905let InputType = "imm"; 23906let BaseOpcode = "S2_storeri_io"; 23907let isExtendable = 1; 23908let opExtendable = 2; 23909let isExtentSigned = 0; 23910let opExtentBits = 8; 23911let opExtentAlign = 2; 23912let opNewValue = 3; 23913} 23914def S4_pstorerinewfnew_rr : HInst< 23915(outs), 23916(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8), 23917"if (!$Pv4.new) memw($Rs32+$Ru32<<#$Ii) = $Nt8.new", 23918tc_b90a29b1, TypeST>, Enc_47ee5e, AddrModeRel { 23919let Inst{4-3} = 0b10; 23920let Inst{31-21} = 0b00110111101; 23921let isPredicated = 1; 23922let isPredicatedFalse = 1; 23923let addrMode = BaseRegOffset; 23924let accessSize = WordAccess; 23925let isNVStore = 1; 23926let isPredicatedNew = 1; 23927let isNewValue = 1; 23928let isRestrictNoSlot1Store = 1; 23929let mayStore = 1; 23930let CextOpcode = "S2_storeri"; 23931let InputType = "reg"; 23932let BaseOpcode = "S2_storeri_rr"; 23933let opNewValue = 4; 23934} 23935def S4_pstorerinewfnew_zomap : HInst< 23936(outs), 23937(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8), 23938"if (!$Pv4.new) memw($Rs32) = $Nt8.new", 23939tc_c79a189f, TypeMAPPING> { 23940let isPseudo = 1; 23941let isCodeGenOnly = 1; 23942let opNewValue = 2; 23943} 23944def S4_pstorerinewt_abs : HInst< 23945(outs), 23946(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8), 23947"if ($Pv4) memw(#$Ii) = $Nt8.new", 23948tc_4b68bce4, TypeST>, Enc_44215c, AddrModeRel { 23949let Inst{2-2} = 0b0; 23950let Inst{7-7} = 0b1; 23951let Inst{13-11} = 0b010; 23952let Inst{31-18} = 0b10101111101000; 23953let isPredicated = 1; 23954let addrMode = Absolute; 23955let accessSize = WordAccess; 23956let isNVStore = 1; 23957let isNewValue = 1; 23958let isExtended = 1; 23959let isRestrictNoSlot1Store = 1; 23960let mayStore = 1; 23961let CextOpcode = "S2_storeri"; 23962let BaseOpcode = "S2_storeriabs"; 23963let DecoderNamespace = "MustExtend"; 23964let isExtendable = 1; 23965let opExtendable = 1; 23966let isExtentSigned = 0; 23967let opExtentBits = 6; 23968let opExtentAlign = 0; 23969let opNewValue = 2; 23970} 23971def S4_pstorerinewt_rr : HInst< 23972(outs), 23973(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8), 23974"if ($Pv4) memw($Rs32+$Ru32<<#$Ii) = $Nt8.new", 23975tc_e95795ec, TypeST>, Enc_47ee5e, AddrModeRel { 23976let Inst{4-3} = 0b10; 23977let Inst{31-21} = 0b00110100101; 23978let isPredicated = 1; 23979let addrMode = BaseRegOffset; 23980let accessSize = WordAccess; 23981let isNVStore = 1; 23982let isNewValue = 1; 23983let isRestrictNoSlot1Store = 1; 23984let mayStore = 1; 23985let CextOpcode = "S2_storeri"; 23986let InputType = "reg"; 23987let BaseOpcode = "S2_storeri_rr"; 23988let opNewValue = 4; 23989} 23990def S4_pstorerinewtnew_abs : HInst< 23991(outs), 23992(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8), 23993"if ($Pv4.new) memw(#$Ii) = $Nt8.new", 23994tc_d2e63d61, TypeST>, Enc_44215c, AddrModeRel { 23995let Inst{2-2} = 0b0; 23996let Inst{7-7} = 0b1; 23997let Inst{13-11} = 0b110; 23998let Inst{31-18} = 0b10101111101000; 23999let isPredicated = 1; 24000let addrMode = Absolute; 24001let accessSize = WordAccess; 24002let isNVStore = 1; 24003let isPredicatedNew = 1; 24004let isNewValue = 1; 24005let isExtended = 1; 24006let isRestrictNoSlot1Store = 1; 24007let mayStore = 1; 24008let CextOpcode = "S2_storeri"; 24009let BaseOpcode = "S2_storeriabs"; 24010let DecoderNamespace = "MustExtend"; 24011let isExtendable = 1; 24012let opExtendable = 1; 24013let isExtentSigned = 0; 24014let opExtentBits = 6; 24015let opExtentAlign = 0; 24016let opNewValue = 2; 24017} 24018def S4_pstorerinewtnew_io : HInst< 24019(outs), 24020(ins PredRegs:$Pv4, IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Nt8), 24021"if ($Pv4.new) memw($Rs32+#$Ii) = $Nt8.new", 24022tc_c79a189f, TypeV2LDST>, Enc_8dbdfe, AddrModeRel { 24023let Inst{2-2} = 0b0; 24024let Inst{12-11} = 0b10; 24025let Inst{31-21} = 0b01000010101; 24026let isPredicated = 1; 24027let addrMode = BaseImmOffset; 24028let accessSize = WordAccess; 24029let isNVStore = 1; 24030let isPredicatedNew = 1; 24031let isNewValue = 1; 24032let isRestrictNoSlot1Store = 1; 24033let mayStore = 1; 24034let CextOpcode = "S2_storeri"; 24035let InputType = "imm"; 24036let BaseOpcode = "S2_storeri_io"; 24037let isExtendable = 1; 24038let opExtendable = 2; 24039let isExtentSigned = 0; 24040let opExtentBits = 8; 24041let opExtentAlign = 2; 24042let opNewValue = 3; 24043} 24044def S4_pstorerinewtnew_rr : HInst< 24045(outs), 24046(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8), 24047"if ($Pv4.new) memw($Rs32+$Ru32<<#$Ii) = $Nt8.new", 24048tc_b90a29b1, TypeST>, Enc_47ee5e, AddrModeRel { 24049let Inst{4-3} = 0b10; 24050let Inst{31-21} = 0b00110110101; 24051let isPredicated = 1; 24052let addrMode = BaseRegOffset; 24053let accessSize = WordAccess; 24054let isNVStore = 1; 24055let isPredicatedNew = 1; 24056let isNewValue = 1; 24057let isRestrictNoSlot1Store = 1; 24058let mayStore = 1; 24059let CextOpcode = "S2_storeri"; 24060let InputType = "reg"; 24061let BaseOpcode = "S2_storeri_rr"; 24062let opNewValue = 4; 24063} 24064def S4_pstorerinewtnew_zomap : HInst< 24065(outs), 24066(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8), 24067"if ($Pv4.new) memw($Rs32) = $Nt8.new", 24068tc_c79a189f, TypeMAPPING> { 24069let isPseudo = 1; 24070let isCodeGenOnly = 1; 24071let opNewValue = 2; 24072} 24073def S4_pstorerit_abs : HInst< 24074(outs), 24075(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32), 24076"if ($Pv4) memw(#$Ii) = $Rt32", 24077tc_362c6592, TypeST>, Enc_1cf4ca, AddrModeRel { 24078let Inst{2-2} = 0b0; 24079let Inst{7-7} = 0b1; 24080let Inst{13-13} = 0b0; 24081let Inst{31-18} = 0b10101111100000; 24082let isPredicated = 1; 24083let addrMode = Absolute; 24084let accessSize = WordAccess; 24085let isExtended = 1; 24086let mayStore = 1; 24087let CextOpcode = "S2_storeri"; 24088let BaseOpcode = "S2_storeriabs"; 24089let isNVStorable = 1; 24090let DecoderNamespace = "MustExtend"; 24091let isExtendable = 1; 24092let opExtendable = 1; 24093let isExtentSigned = 0; 24094let opExtentBits = 6; 24095let opExtentAlign = 0; 24096} 24097def S4_pstorerit_rr : HInst< 24098(outs), 24099(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32), 24100"if ($Pv4) memw($Rs32+$Ru32<<#$Ii) = $Rt32", 24101tc_3962fa26, TypeST>, Enc_6339d5, AddrModeRel { 24102let Inst{31-21} = 0b00110100100; 24103let isPredicated = 1; 24104let addrMode = BaseRegOffset; 24105let accessSize = WordAccess; 24106let mayStore = 1; 24107let CextOpcode = "S2_storeri"; 24108let InputType = "reg"; 24109let BaseOpcode = "S2_storeri_rr"; 24110let isNVStorable = 1; 24111} 24112def S4_pstoreritnew_abs : HInst< 24113(outs), 24114(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32), 24115"if ($Pv4.new) memw(#$Ii) = $Rt32", 24116tc_da4a37ed, TypeST>, Enc_1cf4ca, AddrModeRel { 24117let Inst{2-2} = 0b0; 24118let Inst{7-7} = 0b1; 24119let Inst{13-13} = 0b1; 24120let Inst{31-18} = 0b10101111100000; 24121let isPredicated = 1; 24122let addrMode = Absolute; 24123let accessSize = WordAccess; 24124let isPredicatedNew = 1; 24125let isExtended = 1; 24126let mayStore = 1; 24127let CextOpcode = "S2_storeri"; 24128let BaseOpcode = "S2_storeriabs"; 24129let isNVStorable = 1; 24130let DecoderNamespace = "MustExtend"; 24131let isExtendable = 1; 24132let opExtendable = 1; 24133let isExtentSigned = 0; 24134let opExtentBits = 6; 24135let opExtentAlign = 0; 24136} 24137def S4_pstoreritnew_io : HInst< 24138(outs), 24139(ins PredRegs:$Pv4, IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Rt32), 24140"if ($Pv4.new) memw($Rs32+#$Ii) = $Rt32", 24141tc_da97ee82, TypeV2LDST>, Enc_397f23, AddrModeRel { 24142let Inst{2-2} = 0b0; 24143let Inst{31-21} = 0b01000010100; 24144let isPredicated = 1; 24145let addrMode = BaseImmOffset; 24146let accessSize = WordAccess; 24147let isPredicatedNew = 1; 24148let mayStore = 1; 24149let CextOpcode = "S2_storeri"; 24150let InputType = "imm"; 24151let BaseOpcode = "S2_storeri_io"; 24152let isNVStorable = 1; 24153let isExtendable = 1; 24154let opExtendable = 2; 24155let isExtentSigned = 0; 24156let opExtentBits = 8; 24157let opExtentAlign = 2; 24158} 24159def S4_pstoreritnew_rr : HInst< 24160(outs), 24161(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32), 24162"if ($Pv4.new) memw($Rs32+$Ru32<<#$Ii) = $Rt32", 24163tc_40116ca8, TypeST>, Enc_6339d5, AddrModeRel { 24164let Inst{31-21} = 0b00110110100; 24165let isPredicated = 1; 24166let addrMode = BaseRegOffset; 24167let accessSize = WordAccess; 24168let isPredicatedNew = 1; 24169let mayStore = 1; 24170let CextOpcode = "S2_storeri"; 24171let InputType = "reg"; 24172let BaseOpcode = "S2_storeri_rr"; 24173let isNVStorable = 1; 24174} 24175def S4_pstoreritnew_zomap : HInst< 24176(outs), 24177(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32), 24178"if ($Pv4.new) memw($Rs32) = $Rt32", 24179tc_da97ee82, TypeMAPPING> { 24180let isPseudo = 1; 24181let isCodeGenOnly = 1; 24182} 24183def S4_stored_locked : HInst< 24184(outs PredRegs:$Pd4), 24185(ins IntRegs:$Rs32, DoubleRegs:$Rtt32), 24186"memd_locked($Rs32,$Pd4) = $Rtt32", 24187tc_5abb5e3f, TypeST>, Enc_d7dc10 { 24188let Inst{7-2} = 0b000000; 24189let Inst{13-13} = 0b0; 24190let Inst{31-21} = 0b10100000111; 24191let accessSize = DoubleWordAccess; 24192let isPredicateLate = 1; 24193let isSoloAX = 1; 24194let mayStore = 1; 24195} 24196def S4_storeirb_io : HInst< 24197(outs), 24198(ins IntRegs:$Rs32, u6_0Imm:$Ii, s32_0Imm:$II), 24199"memb($Rs32+#$Ii) = #$II", 24200tc_b83e6d73, TypeST>, Enc_8203bb, PredNewRel { 24201let Inst{31-21} = 0b00111100000; 24202let addrMode = BaseImmOffset; 24203let accessSize = ByteAccess; 24204let mayStore = 1; 24205let CextOpcode = "S2_storerb"; 24206let InputType = "imm"; 24207let BaseOpcode = "S4_storeirb_io"; 24208let isPredicable = 1; 24209let isExtendable = 1; 24210let opExtendable = 2; 24211let isExtentSigned = 1; 24212let opExtentBits = 8; 24213let opExtentAlign = 0; 24214} 24215def S4_storeirb_zomap : HInst< 24216(outs), 24217(ins IntRegs:$Rs32, s8_0Imm:$II), 24218"memb($Rs32) = #$II", 24219tc_b83e6d73, TypeMAPPING> { 24220let isPseudo = 1; 24221let isCodeGenOnly = 1; 24222} 24223def S4_storeirbf_io : HInst< 24224(outs), 24225(ins PredRegs:$Pv4, IntRegs:$Rs32, u6_0Imm:$Ii, s32_0Imm:$II), 24226"if (!$Pv4) memb($Rs32+#$Ii) = #$II", 24227tc_0b2be201, TypeST>, Enc_d7a65e, PredNewRel { 24228let Inst{31-21} = 0b00111000100; 24229let isPredicated = 1; 24230let isPredicatedFalse = 1; 24231let addrMode = BaseImmOffset; 24232let accessSize = ByteAccess; 24233let mayStore = 1; 24234let CextOpcode = "S2_storerb"; 24235let InputType = "imm"; 24236let BaseOpcode = "S4_storeirb_io"; 24237let isExtendable = 1; 24238let opExtendable = 3; 24239let isExtentSigned = 1; 24240let opExtentBits = 6; 24241let opExtentAlign = 0; 24242} 24243def S4_storeirbf_zomap : HInst< 24244(outs), 24245(ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II), 24246"if (!$Pv4) memb($Rs32) = #$II", 24247tc_0b2be201, TypeMAPPING> { 24248let isPseudo = 1; 24249let isCodeGenOnly = 1; 24250} 24251def S4_storeirbfnew_io : HInst< 24252(outs), 24253(ins PredRegs:$Pv4, IntRegs:$Rs32, u6_0Imm:$Ii, s32_0Imm:$II), 24254"if (!$Pv4.new) memb($Rs32+#$Ii) = #$II", 24255tc_c4f596e3, TypeST>, Enc_d7a65e, PredNewRel { 24256let Inst{31-21} = 0b00111001100; 24257let isPredicated = 1; 24258let isPredicatedFalse = 1; 24259let addrMode = BaseImmOffset; 24260let accessSize = ByteAccess; 24261let isPredicatedNew = 1; 24262let mayStore = 1; 24263let CextOpcode = "S2_storerb"; 24264let InputType = "imm"; 24265let BaseOpcode = "S4_storeirb_io"; 24266let isExtendable = 1; 24267let opExtendable = 3; 24268let isExtentSigned = 1; 24269let opExtentBits = 6; 24270let opExtentAlign = 0; 24271} 24272def S4_storeirbfnew_zomap : HInst< 24273(outs), 24274(ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II), 24275"if (!$Pv4.new) memb($Rs32) = #$II", 24276tc_c4f596e3, TypeMAPPING> { 24277let isPseudo = 1; 24278let isCodeGenOnly = 1; 24279} 24280def S4_storeirbt_io : HInst< 24281(outs), 24282(ins PredRegs:$Pv4, IntRegs:$Rs32, u6_0Imm:$Ii, s32_0Imm:$II), 24283"if ($Pv4) memb($Rs32+#$Ii) = #$II", 24284tc_0b2be201, TypeST>, Enc_d7a65e, PredNewRel { 24285let Inst{31-21} = 0b00111000000; 24286let isPredicated = 1; 24287let addrMode = BaseImmOffset; 24288let accessSize = ByteAccess; 24289let mayStore = 1; 24290let CextOpcode = "S2_storerb"; 24291let InputType = "imm"; 24292let BaseOpcode = "S4_storeirb_io"; 24293let isExtendable = 1; 24294let opExtendable = 3; 24295let isExtentSigned = 1; 24296let opExtentBits = 6; 24297let opExtentAlign = 0; 24298} 24299def S4_storeirbt_zomap : HInst< 24300(outs), 24301(ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II), 24302"if ($Pv4) memb($Rs32) = #$II", 24303tc_0b2be201, TypeMAPPING> { 24304let isPseudo = 1; 24305let isCodeGenOnly = 1; 24306} 24307def S4_storeirbtnew_io : HInst< 24308(outs), 24309(ins PredRegs:$Pv4, IntRegs:$Rs32, u6_0Imm:$Ii, s32_0Imm:$II), 24310"if ($Pv4.new) memb($Rs32+#$Ii) = #$II", 24311tc_c4f596e3, TypeST>, Enc_d7a65e, PredNewRel { 24312let Inst{31-21} = 0b00111001000; 24313let isPredicated = 1; 24314let addrMode = BaseImmOffset; 24315let accessSize = ByteAccess; 24316let isPredicatedNew = 1; 24317let mayStore = 1; 24318let CextOpcode = "S2_storerb"; 24319let InputType = "imm"; 24320let BaseOpcode = "S4_storeirb_io"; 24321let isExtendable = 1; 24322let opExtendable = 3; 24323let isExtentSigned = 1; 24324let opExtentBits = 6; 24325let opExtentAlign = 0; 24326} 24327def S4_storeirbtnew_zomap : HInst< 24328(outs), 24329(ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II), 24330"if ($Pv4.new) memb($Rs32) = #$II", 24331tc_c4f596e3, TypeMAPPING> { 24332let isPseudo = 1; 24333let isCodeGenOnly = 1; 24334} 24335def S4_storeirh_io : HInst< 24336(outs), 24337(ins IntRegs:$Rs32, u6_1Imm:$Ii, s32_0Imm:$II), 24338"memh($Rs32+#$Ii) = #$II", 24339tc_b83e6d73, TypeST>, Enc_a803e0, PredNewRel { 24340let Inst{31-21} = 0b00111100001; 24341let addrMode = BaseImmOffset; 24342let accessSize = HalfWordAccess; 24343let mayStore = 1; 24344let CextOpcode = "S2_storerh"; 24345let InputType = "imm"; 24346let BaseOpcode = "S4_storeirh_io"; 24347let isPredicable = 1; 24348let isExtendable = 1; 24349let opExtendable = 2; 24350let isExtentSigned = 1; 24351let opExtentBits = 8; 24352let opExtentAlign = 0; 24353} 24354def S4_storeirh_zomap : HInst< 24355(outs), 24356(ins IntRegs:$Rs32, s8_0Imm:$II), 24357"memh($Rs32) = #$II", 24358tc_b83e6d73, TypeMAPPING> { 24359let isPseudo = 1; 24360let isCodeGenOnly = 1; 24361} 24362def S4_storeirhf_io : HInst< 24363(outs), 24364(ins PredRegs:$Pv4, IntRegs:$Rs32, u6_1Imm:$Ii, s32_0Imm:$II), 24365"if (!$Pv4) memh($Rs32+#$Ii) = #$II", 24366tc_0b2be201, TypeST>, Enc_f20719, PredNewRel { 24367let Inst{31-21} = 0b00111000101; 24368let isPredicated = 1; 24369let isPredicatedFalse = 1; 24370let addrMode = BaseImmOffset; 24371let accessSize = HalfWordAccess; 24372let mayStore = 1; 24373let CextOpcode = "S2_storerh"; 24374let InputType = "imm"; 24375let BaseOpcode = "S4_storeirh_io"; 24376let isExtendable = 1; 24377let opExtendable = 3; 24378let isExtentSigned = 1; 24379let opExtentBits = 6; 24380let opExtentAlign = 0; 24381} 24382def S4_storeirhf_zomap : HInst< 24383(outs), 24384(ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II), 24385"if (!$Pv4) memh($Rs32) = #$II", 24386tc_0b2be201, TypeMAPPING> { 24387let isPseudo = 1; 24388let isCodeGenOnly = 1; 24389} 24390def S4_storeirhfnew_io : HInst< 24391(outs), 24392(ins PredRegs:$Pv4, IntRegs:$Rs32, u6_1Imm:$Ii, s32_0Imm:$II), 24393"if (!$Pv4.new) memh($Rs32+#$Ii) = #$II", 24394tc_c4f596e3, TypeST>, Enc_f20719, PredNewRel { 24395let Inst{31-21} = 0b00111001101; 24396let isPredicated = 1; 24397let isPredicatedFalse = 1; 24398let addrMode = BaseImmOffset; 24399let accessSize = HalfWordAccess; 24400let isPredicatedNew = 1; 24401let mayStore = 1; 24402let CextOpcode = "S2_storerh"; 24403let InputType = "imm"; 24404let BaseOpcode = "S4_storeirh_io"; 24405let isExtendable = 1; 24406let opExtendable = 3; 24407let isExtentSigned = 1; 24408let opExtentBits = 6; 24409let opExtentAlign = 0; 24410} 24411def S4_storeirhfnew_zomap : HInst< 24412(outs), 24413(ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II), 24414"if (!$Pv4.new) memh($Rs32) = #$II", 24415tc_c4f596e3, TypeMAPPING> { 24416let isPseudo = 1; 24417let isCodeGenOnly = 1; 24418} 24419def S4_storeirht_io : HInst< 24420(outs), 24421(ins PredRegs:$Pv4, IntRegs:$Rs32, u6_1Imm:$Ii, s32_0Imm:$II), 24422"if ($Pv4) memh($Rs32+#$Ii) = #$II", 24423tc_0b2be201, TypeST>, Enc_f20719, PredNewRel { 24424let Inst{31-21} = 0b00111000001; 24425let isPredicated = 1; 24426let addrMode = BaseImmOffset; 24427let accessSize = HalfWordAccess; 24428let mayStore = 1; 24429let CextOpcode = "S2_storerh"; 24430let InputType = "imm"; 24431let BaseOpcode = "S4_storeirh_io"; 24432let isExtendable = 1; 24433let opExtendable = 3; 24434let isExtentSigned = 1; 24435let opExtentBits = 6; 24436let opExtentAlign = 0; 24437} 24438def S4_storeirht_zomap : HInst< 24439(outs), 24440(ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II), 24441"if ($Pv4) memh($Rs32) = #$II", 24442tc_0b2be201, TypeMAPPING> { 24443let isPseudo = 1; 24444let isCodeGenOnly = 1; 24445} 24446def S4_storeirhtnew_io : HInst< 24447(outs), 24448(ins PredRegs:$Pv4, IntRegs:$Rs32, u6_1Imm:$Ii, s32_0Imm:$II), 24449"if ($Pv4.new) memh($Rs32+#$Ii) = #$II", 24450tc_c4f596e3, TypeST>, Enc_f20719, PredNewRel { 24451let Inst{31-21} = 0b00111001001; 24452let isPredicated = 1; 24453let addrMode = BaseImmOffset; 24454let accessSize = HalfWordAccess; 24455let isPredicatedNew = 1; 24456let mayStore = 1; 24457let CextOpcode = "S2_storerh"; 24458let InputType = "imm"; 24459let BaseOpcode = "S4_storeirh_io"; 24460let isExtendable = 1; 24461let opExtendable = 3; 24462let isExtentSigned = 1; 24463let opExtentBits = 6; 24464let opExtentAlign = 0; 24465} 24466def S4_storeirhtnew_zomap : HInst< 24467(outs), 24468(ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II), 24469"if ($Pv4.new) memh($Rs32) = #$II", 24470tc_c4f596e3, TypeMAPPING> { 24471let isPseudo = 1; 24472let isCodeGenOnly = 1; 24473} 24474def S4_storeiri_io : HInst< 24475(outs), 24476(ins IntRegs:$Rs32, u6_2Imm:$Ii, s32_0Imm:$II), 24477"memw($Rs32+#$Ii) = #$II", 24478tc_b83e6d73, TypeST>, Enc_f37377, PredNewRel { 24479let Inst{31-21} = 0b00111100010; 24480let addrMode = BaseImmOffset; 24481let accessSize = WordAccess; 24482let mayStore = 1; 24483let CextOpcode = "S2_storeri"; 24484let InputType = "imm"; 24485let BaseOpcode = "S4_storeiri_io"; 24486let isPredicable = 1; 24487let isExtendable = 1; 24488let opExtendable = 2; 24489let isExtentSigned = 1; 24490let opExtentBits = 8; 24491let opExtentAlign = 0; 24492} 24493def S4_storeiri_zomap : HInst< 24494(outs), 24495(ins IntRegs:$Rs32, s8_0Imm:$II), 24496"memw($Rs32) = #$II", 24497tc_b83e6d73, TypeMAPPING> { 24498let isPseudo = 1; 24499let isCodeGenOnly = 1; 24500} 24501def S4_storeirif_io : HInst< 24502(outs), 24503(ins PredRegs:$Pv4, IntRegs:$Rs32, u6_2Imm:$Ii, s32_0Imm:$II), 24504"if (!$Pv4) memw($Rs32+#$Ii) = #$II", 24505tc_0b2be201, TypeST>, Enc_5ccba9, PredNewRel { 24506let Inst{31-21} = 0b00111000110; 24507let isPredicated = 1; 24508let isPredicatedFalse = 1; 24509let addrMode = BaseImmOffset; 24510let accessSize = WordAccess; 24511let mayStore = 1; 24512let CextOpcode = "S2_storeri"; 24513let InputType = "imm"; 24514let BaseOpcode = "S4_storeiri_io"; 24515let isExtendable = 1; 24516let opExtendable = 3; 24517let isExtentSigned = 1; 24518let opExtentBits = 6; 24519let opExtentAlign = 0; 24520} 24521def S4_storeirif_zomap : HInst< 24522(outs), 24523(ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II), 24524"if (!$Pv4) memw($Rs32) = #$II", 24525tc_0b2be201, TypeMAPPING> { 24526let isPseudo = 1; 24527let isCodeGenOnly = 1; 24528} 24529def S4_storeirifnew_io : HInst< 24530(outs), 24531(ins PredRegs:$Pv4, IntRegs:$Rs32, u6_2Imm:$Ii, s32_0Imm:$II), 24532"if (!$Pv4.new) memw($Rs32+#$Ii) = #$II", 24533tc_c4f596e3, TypeST>, Enc_5ccba9, PredNewRel { 24534let Inst{31-21} = 0b00111001110; 24535let isPredicated = 1; 24536let isPredicatedFalse = 1; 24537let addrMode = BaseImmOffset; 24538let accessSize = WordAccess; 24539let isPredicatedNew = 1; 24540let mayStore = 1; 24541let CextOpcode = "S2_storeri"; 24542let InputType = "imm"; 24543let BaseOpcode = "S4_storeiri_io"; 24544let isExtendable = 1; 24545let opExtendable = 3; 24546let isExtentSigned = 1; 24547let opExtentBits = 6; 24548let opExtentAlign = 0; 24549} 24550def S4_storeirifnew_zomap : HInst< 24551(outs), 24552(ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II), 24553"if (!$Pv4.new) memw($Rs32) = #$II", 24554tc_c4f596e3, TypeMAPPING> { 24555let isPseudo = 1; 24556let isCodeGenOnly = 1; 24557} 24558def S4_storeirit_io : HInst< 24559(outs), 24560(ins PredRegs:$Pv4, IntRegs:$Rs32, u6_2Imm:$Ii, s32_0Imm:$II), 24561"if ($Pv4) memw($Rs32+#$Ii) = #$II", 24562tc_0b2be201, TypeST>, Enc_5ccba9, PredNewRel { 24563let Inst{31-21} = 0b00111000010; 24564let isPredicated = 1; 24565let addrMode = BaseImmOffset; 24566let accessSize = WordAccess; 24567let mayStore = 1; 24568let CextOpcode = "S2_storeri"; 24569let InputType = "imm"; 24570let BaseOpcode = "S4_storeiri_io"; 24571let isExtendable = 1; 24572let opExtendable = 3; 24573let isExtentSigned = 1; 24574let opExtentBits = 6; 24575let opExtentAlign = 0; 24576} 24577def S4_storeirit_zomap : HInst< 24578(outs), 24579(ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II), 24580"if ($Pv4) memw($Rs32) = #$II", 24581tc_0b2be201, TypeMAPPING> { 24582let isPseudo = 1; 24583let isCodeGenOnly = 1; 24584} 24585def S4_storeiritnew_io : HInst< 24586(outs), 24587(ins PredRegs:$Pv4, IntRegs:$Rs32, u6_2Imm:$Ii, s32_0Imm:$II), 24588"if ($Pv4.new) memw($Rs32+#$Ii) = #$II", 24589tc_c4f596e3, TypeST>, Enc_5ccba9, PredNewRel { 24590let Inst{31-21} = 0b00111001010; 24591let isPredicated = 1; 24592let addrMode = BaseImmOffset; 24593let accessSize = WordAccess; 24594let isPredicatedNew = 1; 24595let mayStore = 1; 24596let CextOpcode = "S2_storeri"; 24597let InputType = "imm"; 24598let BaseOpcode = "S4_storeiri_io"; 24599let isExtendable = 1; 24600let opExtendable = 3; 24601let isExtentSigned = 1; 24602let opExtentBits = 6; 24603let opExtentAlign = 0; 24604} 24605def S4_storeiritnew_zomap : HInst< 24606(outs), 24607(ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II), 24608"if ($Pv4.new) memw($Rs32) = #$II", 24609tc_c4f596e3, TypeMAPPING> { 24610let isPseudo = 1; 24611let isCodeGenOnly = 1; 24612} 24613def S4_storerb_ap : HInst< 24614(outs IntRegs:$Re32), 24615(ins u32_0Imm:$II, IntRegs:$Rt32), 24616"memb($Re32=#$II) = $Rt32", 24617tc_da4a37ed, TypeST>, Enc_8bcba4, AddrModeRel { 24618let Inst{7-6} = 0b10; 24619let Inst{13-13} = 0b0; 24620let Inst{31-21} = 0b10101011000; 24621let addrMode = AbsoluteSet; 24622let accessSize = ByteAccess; 24623let isExtended = 1; 24624let mayStore = 1; 24625let BaseOpcode = "S2_storerb_ap"; 24626let isNVStorable = 1; 24627let DecoderNamespace = "MustExtend"; 24628let isExtendable = 1; 24629let opExtendable = 1; 24630let isExtentSigned = 0; 24631let opExtentBits = 6; 24632let opExtentAlign = 0; 24633} 24634def S4_storerb_rr : HInst< 24635(outs), 24636(ins IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32), 24637"memb($Rs32+$Ru32<<#$Ii) = $Rt32", 24638tc_5aee39f7, TypeST>, Enc_eca7c8, AddrModeRel, ImmRegShl { 24639let Inst{6-5} = 0b00; 24640let Inst{31-21} = 0b00111011000; 24641let addrMode = BaseRegOffset; 24642let accessSize = ByteAccess; 24643let mayStore = 1; 24644let CextOpcode = "S2_storerb"; 24645let InputType = "reg"; 24646let BaseOpcode = "S4_storerb_rr"; 24647let isNVStorable = 1; 24648let isPredicable = 1; 24649} 24650def S4_storerb_ur : HInst< 24651(outs), 24652(ins IntRegs:$Ru32, u2_0Imm:$Ii, u32_0Imm:$II, IntRegs:$Rt32), 24653"memb($Ru32<<#$Ii+#$II) = $Rt32", 24654tc_14b272fa, TypeST>, Enc_9ea4cf, AddrModeRel, ImmRegShl { 24655let Inst{7-7} = 0b1; 24656let Inst{31-21} = 0b10101101000; 24657let addrMode = BaseLongOffset; 24658let accessSize = ByteAccess; 24659let isExtended = 1; 24660let mayStore = 1; 24661let CextOpcode = "S2_storerb"; 24662let InputType = "imm"; 24663let BaseOpcode = "S4_storerb_ur"; 24664let isNVStorable = 1; 24665let DecoderNamespace = "MustExtend"; 24666let isExtendable = 1; 24667let opExtendable = 2; 24668let isExtentSigned = 0; 24669let opExtentBits = 6; 24670let opExtentAlign = 0; 24671} 24672def S4_storerbnew_ap : HInst< 24673(outs IntRegs:$Re32), 24674(ins u32_0Imm:$II, IntRegs:$Nt8), 24675"memb($Re32=#$II) = $Nt8.new", 24676tc_d2e63d61, TypeST>, Enc_724154, AddrModeRel { 24677let Inst{7-6} = 0b10; 24678let Inst{13-11} = 0b000; 24679let Inst{31-21} = 0b10101011101; 24680let addrMode = AbsoluteSet; 24681let accessSize = ByteAccess; 24682let isNVStore = 1; 24683let isNewValue = 1; 24684let isExtended = 1; 24685let isRestrictNoSlot1Store = 1; 24686let mayStore = 1; 24687let BaseOpcode = "S2_storerb_ap"; 24688let DecoderNamespace = "MustExtend"; 24689let isExtendable = 1; 24690let opExtendable = 1; 24691let isExtentSigned = 0; 24692let opExtentBits = 6; 24693let opExtentAlign = 0; 24694let opNewValue = 2; 24695} 24696def S4_storerbnew_rr : HInst< 24697(outs), 24698(ins IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8), 24699"memb($Rs32+$Ru32<<#$Ii) = $Nt8.new", 24700tc_67435e81, TypeST>, Enc_c6220b, AddrModeRel { 24701let Inst{6-3} = 0b0000; 24702let Inst{31-21} = 0b00111011101; 24703let addrMode = BaseRegOffset; 24704let accessSize = ByteAccess; 24705let isNVStore = 1; 24706let isNewValue = 1; 24707let isRestrictNoSlot1Store = 1; 24708let mayStore = 1; 24709let CextOpcode = "S2_storerb"; 24710let InputType = "reg"; 24711let BaseOpcode = "S4_storerb_rr"; 24712let isPredicable = 1; 24713let opNewValue = 3; 24714} 24715def S4_storerbnew_ur : HInst< 24716(outs), 24717(ins IntRegs:$Ru32, u2_0Imm:$Ii, u32_0Imm:$II, IntRegs:$Nt8), 24718"memb($Ru32<<#$Ii+#$II) = $Nt8.new", 24719tc_fcc3ddf9, TypeST>, Enc_7eb485, AddrModeRel { 24720let Inst{7-7} = 0b1; 24721let Inst{12-11} = 0b00; 24722let Inst{31-21} = 0b10101101101; 24723let addrMode = BaseLongOffset; 24724let accessSize = ByteAccess; 24725let isNVStore = 1; 24726let isNewValue = 1; 24727let isExtended = 1; 24728let isRestrictNoSlot1Store = 1; 24729let mayStore = 1; 24730let CextOpcode = "S2_storerb"; 24731let BaseOpcode = "S4_storerb_ur"; 24732let DecoderNamespace = "MustExtend"; 24733let isExtendable = 1; 24734let opExtendable = 2; 24735let isExtentSigned = 0; 24736let opExtentBits = 6; 24737let opExtentAlign = 0; 24738let opNewValue = 3; 24739} 24740def S4_storerd_ap : HInst< 24741(outs IntRegs:$Re32), 24742(ins u32_0Imm:$II, DoubleRegs:$Rtt32), 24743"memd($Re32=#$II) = $Rtt32", 24744tc_da4a37ed, TypeST>, Enc_c7a204 { 24745let Inst{7-6} = 0b10; 24746let Inst{13-13} = 0b0; 24747let Inst{31-21} = 0b10101011110; 24748let addrMode = AbsoluteSet; 24749let accessSize = DoubleWordAccess; 24750let isExtended = 1; 24751let mayStore = 1; 24752let BaseOpcode = "S4_storerd_ap"; 24753let DecoderNamespace = "MustExtend"; 24754let isExtendable = 1; 24755let opExtendable = 1; 24756let isExtentSigned = 0; 24757let opExtentBits = 6; 24758let opExtentAlign = 0; 24759} 24760def S4_storerd_rr : HInst< 24761(outs), 24762(ins IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, DoubleRegs:$Rtt32), 24763"memd($Rs32+$Ru32<<#$Ii) = $Rtt32", 24764tc_5aee39f7, TypeST>, Enc_55355c, AddrModeRel, ImmRegShl { 24765let Inst{6-5} = 0b00; 24766let Inst{31-21} = 0b00111011110; 24767let addrMode = BaseRegOffset; 24768let accessSize = DoubleWordAccess; 24769let mayStore = 1; 24770let CextOpcode = "S2_storerd"; 24771let InputType = "reg"; 24772let BaseOpcode = "S2_storerd_rr"; 24773let isPredicable = 1; 24774} 24775def S4_storerd_ur : HInst< 24776(outs), 24777(ins IntRegs:$Ru32, u2_0Imm:$Ii, u32_0Imm:$II, DoubleRegs:$Rtt32), 24778"memd($Ru32<<#$Ii+#$II) = $Rtt32", 24779tc_14b272fa, TypeST>, Enc_f79415, AddrModeRel, ImmRegShl { 24780let Inst{7-7} = 0b1; 24781let Inst{31-21} = 0b10101101110; 24782let addrMode = BaseLongOffset; 24783let accessSize = DoubleWordAccess; 24784let isExtended = 1; 24785let mayStore = 1; 24786let CextOpcode = "S2_storerd"; 24787let InputType = "imm"; 24788let BaseOpcode = "S2_storerd_ur"; 24789let DecoderNamespace = "MustExtend"; 24790let isExtendable = 1; 24791let opExtendable = 2; 24792let isExtentSigned = 0; 24793let opExtentBits = 6; 24794let opExtentAlign = 0; 24795} 24796def S4_storerf_ap : HInst< 24797(outs IntRegs:$Re32), 24798(ins u32_0Imm:$II, IntRegs:$Rt32), 24799"memh($Re32=#$II) = $Rt32.h", 24800tc_da4a37ed, TypeST>, Enc_8bcba4 { 24801let Inst{7-6} = 0b10; 24802let Inst{13-13} = 0b0; 24803let Inst{31-21} = 0b10101011011; 24804let addrMode = AbsoluteSet; 24805let accessSize = HalfWordAccess; 24806let isExtended = 1; 24807let mayStore = 1; 24808let BaseOpcode = "S4_storerf_ap"; 24809let DecoderNamespace = "MustExtend"; 24810let isExtendable = 1; 24811let opExtendable = 1; 24812let isExtentSigned = 0; 24813let opExtentBits = 6; 24814let opExtentAlign = 0; 24815} 24816def S4_storerf_rr : HInst< 24817(outs), 24818(ins IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32), 24819"memh($Rs32+$Ru32<<#$Ii) = $Rt32.h", 24820tc_5aee39f7, TypeST>, Enc_eca7c8, AddrModeRel, ImmRegShl { 24821let Inst{6-5} = 0b00; 24822let Inst{31-21} = 0b00111011011; 24823let addrMode = BaseRegOffset; 24824let accessSize = HalfWordAccess; 24825let mayStore = 1; 24826let CextOpcode = "S2_storerf"; 24827let InputType = "reg"; 24828let BaseOpcode = "S4_storerf_rr"; 24829let isPredicable = 1; 24830} 24831def S4_storerf_ur : HInst< 24832(outs), 24833(ins IntRegs:$Ru32, u2_0Imm:$Ii, u32_0Imm:$II, IntRegs:$Rt32), 24834"memh($Ru32<<#$Ii+#$II) = $Rt32.h", 24835tc_14b272fa, TypeST>, Enc_9ea4cf, AddrModeRel, ImmRegShl { 24836let Inst{7-7} = 0b1; 24837let Inst{31-21} = 0b10101101011; 24838let addrMode = BaseLongOffset; 24839let accessSize = HalfWordAccess; 24840let isExtended = 1; 24841let mayStore = 1; 24842let CextOpcode = "S2_storerf"; 24843let InputType = "imm"; 24844let BaseOpcode = "S4_storerf_rr"; 24845let DecoderNamespace = "MustExtend"; 24846let isExtendable = 1; 24847let opExtendable = 2; 24848let isExtentSigned = 0; 24849let opExtentBits = 6; 24850let opExtentAlign = 0; 24851} 24852def S4_storerh_ap : HInst< 24853(outs IntRegs:$Re32), 24854(ins u32_0Imm:$II, IntRegs:$Rt32), 24855"memh($Re32=#$II) = $Rt32", 24856tc_da4a37ed, TypeST>, Enc_8bcba4, AddrModeRel { 24857let Inst{7-6} = 0b10; 24858let Inst{13-13} = 0b0; 24859let Inst{31-21} = 0b10101011010; 24860let addrMode = AbsoluteSet; 24861let accessSize = HalfWordAccess; 24862let isExtended = 1; 24863let mayStore = 1; 24864let BaseOpcode = "S2_storerh_ap"; 24865let isNVStorable = 1; 24866let DecoderNamespace = "MustExtend"; 24867let isExtendable = 1; 24868let opExtendable = 1; 24869let isExtentSigned = 0; 24870let opExtentBits = 6; 24871let opExtentAlign = 0; 24872} 24873def S4_storerh_rr : HInst< 24874(outs), 24875(ins IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32), 24876"memh($Rs32+$Ru32<<#$Ii) = $Rt32", 24877tc_5aee39f7, TypeST>, Enc_eca7c8, AddrModeRel, ImmRegShl { 24878let Inst{6-5} = 0b00; 24879let Inst{31-21} = 0b00111011010; 24880let addrMode = BaseRegOffset; 24881let accessSize = HalfWordAccess; 24882let mayStore = 1; 24883let CextOpcode = "S2_storerh"; 24884let InputType = "reg"; 24885let BaseOpcode = "S2_storerh_rr"; 24886let isNVStorable = 1; 24887let isPredicable = 1; 24888} 24889def S4_storerh_ur : HInst< 24890(outs), 24891(ins IntRegs:$Ru32, u2_0Imm:$Ii, u32_0Imm:$II, IntRegs:$Rt32), 24892"memh($Ru32<<#$Ii+#$II) = $Rt32", 24893tc_14b272fa, TypeST>, Enc_9ea4cf, AddrModeRel, ImmRegShl { 24894let Inst{7-7} = 0b1; 24895let Inst{31-21} = 0b10101101010; 24896let addrMode = BaseLongOffset; 24897let accessSize = HalfWordAccess; 24898let isExtended = 1; 24899let mayStore = 1; 24900let CextOpcode = "S2_storerh"; 24901let InputType = "imm"; 24902let BaseOpcode = "S2_storerh_ur"; 24903let isNVStorable = 1; 24904let DecoderNamespace = "MustExtend"; 24905let isExtendable = 1; 24906let opExtendable = 2; 24907let isExtentSigned = 0; 24908let opExtentBits = 6; 24909let opExtentAlign = 0; 24910} 24911def S4_storerhnew_ap : HInst< 24912(outs IntRegs:$Re32), 24913(ins u32_0Imm:$II, IntRegs:$Nt8), 24914"memh($Re32=#$II) = $Nt8.new", 24915tc_d2e63d61, TypeST>, Enc_724154, AddrModeRel { 24916let Inst{7-6} = 0b10; 24917let Inst{13-11} = 0b001; 24918let Inst{31-21} = 0b10101011101; 24919let addrMode = AbsoluteSet; 24920let accessSize = HalfWordAccess; 24921let isNVStore = 1; 24922let isNewValue = 1; 24923let isExtended = 1; 24924let isRestrictNoSlot1Store = 1; 24925let mayStore = 1; 24926let BaseOpcode = "S2_storerh_ap"; 24927let DecoderNamespace = "MustExtend"; 24928let isExtendable = 1; 24929let opExtendable = 1; 24930let isExtentSigned = 0; 24931let opExtentBits = 6; 24932let opExtentAlign = 0; 24933let opNewValue = 2; 24934} 24935def S4_storerhnew_rr : HInst< 24936(outs), 24937(ins IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8), 24938"memh($Rs32+$Ru32<<#$Ii) = $Nt8.new", 24939tc_67435e81, TypeST>, Enc_c6220b, AddrModeRel { 24940let Inst{6-3} = 0b0001; 24941let Inst{31-21} = 0b00111011101; 24942let addrMode = BaseRegOffset; 24943let accessSize = HalfWordAccess; 24944let isNVStore = 1; 24945let isNewValue = 1; 24946let isRestrictNoSlot1Store = 1; 24947let mayStore = 1; 24948let CextOpcode = "S2_storerh"; 24949let InputType = "reg"; 24950let BaseOpcode = "S2_storerh_rr"; 24951let isPredicable = 1; 24952let opNewValue = 3; 24953} 24954def S4_storerhnew_ur : HInst< 24955(outs), 24956(ins IntRegs:$Ru32, u2_0Imm:$Ii, u32_0Imm:$II, IntRegs:$Nt8), 24957"memh($Ru32<<#$Ii+#$II) = $Nt8.new", 24958tc_fcc3ddf9, TypeST>, Enc_7eb485, AddrModeRel { 24959let Inst{7-7} = 0b1; 24960let Inst{12-11} = 0b01; 24961let Inst{31-21} = 0b10101101101; 24962let addrMode = BaseLongOffset; 24963let accessSize = HalfWordAccess; 24964let isNVStore = 1; 24965let isNewValue = 1; 24966let isExtended = 1; 24967let isRestrictNoSlot1Store = 1; 24968let mayStore = 1; 24969let CextOpcode = "S2_storerh"; 24970let BaseOpcode = "S2_storerh_ur"; 24971let DecoderNamespace = "MustExtend"; 24972let isExtendable = 1; 24973let opExtendable = 2; 24974let isExtentSigned = 0; 24975let opExtentBits = 6; 24976let opExtentAlign = 0; 24977let opNewValue = 3; 24978} 24979def S4_storeri_ap : HInst< 24980(outs IntRegs:$Re32), 24981(ins u32_0Imm:$II, IntRegs:$Rt32), 24982"memw($Re32=#$II) = $Rt32", 24983tc_da4a37ed, TypeST>, Enc_8bcba4, AddrModeRel { 24984let Inst{7-6} = 0b10; 24985let Inst{13-13} = 0b0; 24986let Inst{31-21} = 0b10101011100; 24987let addrMode = AbsoluteSet; 24988let accessSize = WordAccess; 24989let isExtended = 1; 24990let mayStore = 1; 24991let BaseOpcode = "S2_storeri_ap"; 24992let isNVStorable = 1; 24993let DecoderNamespace = "MustExtend"; 24994let isExtendable = 1; 24995let opExtendable = 1; 24996let isExtentSigned = 0; 24997let opExtentBits = 6; 24998let opExtentAlign = 0; 24999} 25000def S4_storeri_rr : HInst< 25001(outs), 25002(ins IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32), 25003"memw($Rs32+$Ru32<<#$Ii) = $Rt32", 25004tc_5aee39f7, TypeST>, Enc_eca7c8, AddrModeRel, ImmRegShl { 25005let Inst{6-5} = 0b00; 25006let Inst{31-21} = 0b00111011100; 25007let addrMode = BaseRegOffset; 25008let accessSize = WordAccess; 25009let mayStore = 1; 25010let CextOpcode = "S2_storeri"; 25011let InputType = "reg"; 25012let BaseOpcode = "S2_storeri_rr"; 25013let isNVStorable = 1; 25014let isPredicable = 1; 25015} 25016def S4_storeri_ur : HInst< 25017(outs), 25018(ins IntRegs:$Ru32, u2_0Imm:$Ii, u32_0Imm:$II, IntRegs:$Rt32), 25019"memw($Ru32<<#$Ii+#$II) = $Rt32", 25020tc_14b272fa, TypeST>, Enc_9ea4cf, AddrModeRel, ImmRegShl { 25021let Inst{7-7} = 0b1; 25022let Inst{31-21} = 0b10101101100; 25023let addrMode = BaseLongOffset; 25024let accessSize = WordAccess; 25025let isExtended = 1; 25026let mayStore = 1; 25027let CextOpcode = "S2_storeri"; 25028let InputType = "imm"; 25029let BaseOpcode = "S2_storeri_ur"; 25030let isNVStorable = 1; 25031let DecoderNamespace = "MustExtend"; 25032let isExtendable = 1; 25033let opExtendable = 2; 25034let isExtentSigned = 0; 25035let opExtentBits = 6; 25036let opExtentAlign = 0; 25037} 25038def S4_storerinew_ap : HInst< 25039(outs IntRegs:$Re32), 25040(ins u32_0Imm:$II, IntRegs:$Nt8), 25041"memw($Re32=#$II) = $Nt8.new", 25042tc_d2e63d61, TypeST>, Enc_724154, AddrModeRel { 25043let Inst{7-6} = 0b10; 25044let Inst{13-11} = 0b010; 25045let Inst{31-21} = 0b10101011101; 25046let addrMode = AbsoluteSet; 25047let accessSize = WordAccess; 25048let isNVStore = 1; 25049let isNewValue = 1; 25050let isExtended = 1; 25051let isRestrictNoSlot1Store = 1; 25052let mayStore = 1; 25053let BaseOpcode = "S2_storeri_ap"; 25054let DecoderNamespace = "MustExtend"; 25055let isExtendable = 1; 25056let opExtendable = 1; 25057let isExtentSigned = 0; 25058let opExtentBits = 6; 25059let opExtentAlign = 0; 25060let opNewValue = 2; 25061} 25062def S4_storerinew_rr : HInst< 25063(outs), 25064(ins IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8), 25065"memw($Rs32+$Ru32<<#$Ii) = $Nt8.new", 25066tc_67435e81, TypeST>, Enc_c6220b, AddrModeRel { 25067let Inst{6-3} = 0b0010; 25068let Inst{31-21} = 0b00111011101; 25069let addrMode = BaseRegOffset; 25070let accessSize = WordAccess; 25071let isNVStore = 1; 25072let isNewValue = 1; 25073let isRestrictNoSlot1Store = 1; 25074let mayStore = 1; 25075let CextOpcode = "S2_storeri"; 25076let InputType = "reg"; 25077let BaseOpcode = "S2_storeri_rr"; 25078let isPredicable = 1; 25079let opNewValue = 3; 25080} 25081def S4_storerinew_ur : HInst< 25082(outs), 25083(ins IntRegs:$Ru32, u2_0Imm:$Ii, u32_0Imm:$II, IntRegs:$Nt8), 25084"memw($Ru32<<#$Ii+#$II) = $Nt8.new", 25085tc_fcc3ddf9, TypeST>, Enc_7eb485, AddrModeRel { 25086let Inst{7-7} = 0b1; 25087let Inst{12-11} = 0b10; 25088let Inst{31-21} = 0b10101101101; 25089let addrMode = BaseLongOffset; 25090let accessSize = WordAccess; 25091let isNVStore = 1; 25092let isNewValue = 1; 25093let isExtended = 1; 25094let isRestrictNoSlot1Store = 1; 25095let mayStore = 1; 25096let CextOpcode = "S2_storeri"; 25097let BaseOpcode = "S2_storeri_ur"; 25098let DecoderNamespace = "MustExtend"; 25099let isExtendable = 1; 25100let opExtendable = 2; 25101let isExtentSigned = 0; 25102let opExtentBits = 6; 25103let opExtentAlign = 0; 25104let opNewValue = 3; 25105} 25106def S4_subaddi : HInst< 25107(outs IntRegs:$Rd32), 25108(ins IntRegs:$Rs32, s32_0Imm:$Ii, IntRegs:$Ru32), 25109"$Rd32 = add($Rs32,sub(#$Ii,$Ru32))", 25110tc_f675fee8, TypeALU64>, Enc_8b8d61 { 25111let Inst{31-23} = 0b110110111; 25112let hasNewValue = 1; 25113let opNewValue = 0; 25114let prefersSlot3 = 1; 25115let isExtendable = 1; 25116let opExtendable = 2; 25117let isExtentSigned = 1; 25118let opExtentBits = 6; 25119let opExtentAlign = 0; 25120} 25121def S4_subi_asl_ri : HInst< 25122(outs IntRegs:$Rx32), 25123(ins u32_0Imm:$Ii, IntRegs:$Rx32in, u5_0Imm:$II), 25124"$Rx32 = sub(#$Ii,asl($Rx32in,#$II))", 25125tc_f675fee8, TypeALU64>, Enc_c31910 { 25126let Inst{2-0} = 0b110; 25127let Inst{4-4} = 0b0; 25128let Inst{31-24} = 0b11011110; 25129let hasNewValue = 1; 25130let opNewValue = 0; 25131let prefersSlot3 = 1; 25132let isExtendable = 1; 25133let opExtendable = 1; 25134let isExtentSigned = 0; 25135let opExtentBits = 8; 25136let opExtentAlign = 0; 25137let Constraints = "$Rx32 = $Rx32in"; 25138} 25139def S4_subi_lsr_ri : HInst< 25140(outs IntRegs:$Rx32), 25141(ins u32_0Imm:$Ii, IntRegs:$Rx32in, u5_0Imm:$II), 25142"$Rx32 = sub(#$Ii,lsr($Rx32in,#$II))", 25143tc_f675fee8, TypeALU64>, Enc_c31910 { 25144let Inst{2-0} = 0b110; 25145let Inst{4-4} = 0b1; 25146let Inst{31-24} = 0b11011110; 25147let hasNewValue = 1; 25148let opNewValue = 0; 25149let prefersSlot3 = 1; 25150let isExtendable = 1; 25151let opExtendable = 1; 25152let isExtentSigned = 0; 25153let opExtentBits = 8; 25154let opExtentAlign = 0; 25155let Constraints = "$Rx32 = $Rx32in"; 25156} 25157def S4_vrcrotate : HInst< 25158(outs DoubleRegs:$Rdd32), 25159(ins DoubleRegs:$Rss32, IntRegs:$Rt32, u2_0Imm:$Ii), 25160"$Rdd32 = vrcrotate($Rss32,$Rt32,#$Ii)", 25161tc_13bfbcf9, TypeS_3op>, Enc_645d54 { 25162let Inst{7-6} = 0b11; 25163let Inst{31-21} = 0b11000011110; 25164let prefersSlot3 = 1; 25165} 25166def S4_vrcrotate_acc : HInst< 25167(outs DoubleRegs:$Rxx32), 25168(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32, u2_0Imm:$Ii), 25169"$Rxx32 += vrcrotate($Rss32,$Rt32,#$Ii)", 25170tc_9debc299, TypeS_3op>, Enc_b72622 { 25171let Inst{7-6} = 0b00; 25172let Inst{31-21} = 0b11001011101; 25173let prefersSlot3 = 1; 25174let Constraints = "$Rxx32 = $Rxx32in"; 25175} 25176def S4_vxaddsubh : HInst< 25177(outs DoubleRegs:$Rdd32), 25178(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 25179"$Rdd32 = vxaddsubh($Rss32,$Rtt32):sat", 25180tc_779080bf, TypeS_3op>, Enc_a56825 { 25181let Inst{7-5} = 0b100; 25182let Inst{13-13} = 0b0; 25183let Inst{31-21} = 0b11000001010; 25184let prefersSlot3 = 1; 25185let Defs = [USR_OVF]; 25186} 25187def S4_vxaddsubhr : HInst< 25188(outs DoubleRegs:$Rdd32), 25189(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 25190"$Rdd32 = vxaddsubh($Rss32,$Rtt32):rnd:>>1:sat", 25191tc_002cb246, TypeS_3op>, Enc_a56825 { 25192let Inst{7-5} = 0b000; 25193let Inst{13-13} = 0b0; 25194let Inst{31-21} = 0b11000001110; 25195let prefersSlot3 = 1; 25196let Defs = [USR_OVF]; 25197} 25198def S4_vxaddsubw : HInst< 25199(outs DoubleRegs:$Rdd32), 25200(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 25201"$Rdd32 = vxaddsubw($Rss32,$Rtt32):sat", 25202tc_779080bf, TypeS_3op>, Enc_a56825 { 25203let Inst{7-5} = 0b000; 25204let Inst{13-13} = 0b0; 25205let Inst{31-21} = 0b11000001010; 25206let prefersSlot3 = 1; 25207let Defs = [USR_OVF]; 25208} 25209def S4_vxsubaddh : HInst< 25210(outs DoubleRegs:$Rdd32), 25211(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 25212"$Rdd32 = vxsubaddh($Rss32,$Rtt32):sat", 25213tc_779080bf, TypeS_3op>, Enc_a56825 { 25214let Inst{7-5} = 0b110; 25215let Inst{13-13} = 0b0; 25216let Inst{31-21} = 0b11000001010; 25217let prefersSlot3 = 1; 25218let Defs = [USR_OVF]; 25219} 25220def S4_vxsubaddhr : HInst< 25221(outs DoubleRegs:$Rdd32), 25222(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 25223"$Rdd32 = vxsubaddh($Rss32,$Rtt32):rnd:>>1:sat", 25224tc_002cb246, TypeS_3op>, Enc_a56825 { 25225let Inst{7-5} = 0b010; 25226let Inst{13-13} = 0b0; 25227let Inst{31-21} = 0b11000001110; 25228let prefersSlot3 = 1; 25229let Defs = [USR_OVF]; 25230} 25231def S4_vxsubaddw : HInst< 25232(outs DoubleRegs:$Rdd32), 25233(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 25234"$Rdd32 = vxsubaddw($Rss32,$Rtt32):sat", 25235tc_779080bf, TypeS_3op>, Enc_a56825 { 25236let Inst{7-5} = 0b010; 25237let Inst{13-13} = 0b0; 25238let Inst{31-21} = 0b11000001010; 25239let prefersSlot3 = 1; 25240let Defs = [USR_OVF]; 25241} 25242def S5_asrhub_rnd_sat : HInst< 25243(outs IntRegs:$Rd32), 25244(ins DoubleRegs:$Rss32, u4_0Imm:$Ii), 25245"$Rd32 = vasrhub($Rss32,#$Ii):raw", 25246tc_002cb246, TypeS_2op>, Enc_11a146 { 25247let Inst{7-5} = 0b100; 25248let Inst{13-12} = 0b00; 25249let Inst{31-21} = 0b10001000011; 25250let hasNewValue = 1; 25251let opNewValue = 0; 25252let prefersSlot3 = 1; 25253let Defs = [USR_OVF]; 25254} 25255def S5_asrhub_rnd_sat_goodsyntax : HInst< 25256(outs IntRegs:$Rd32), 25257(ins DoubleRegs:$Rss32, u4_0Imm:$Ii), 25258"$Rd32 = vasrhub($Rss32,#$Ii):rnd:sat", 25259tc_002cb246, TypeS_2op> { 25260let hasNewValue = 1; 25261let opNewValue = 0; 25262let isPseudo = 1; 25263} 25264def S5_asrhub_sat : HInst< 25265(outs IntRegs:$Rd32), 25266(ins DoubleRegs:$Rss32, u4_0Imm:$Ii), 25267"$Rd32 = vasrhub($Rss32,#$Ii):sat", 25268tc_002cb246, TypeS_2op>, Enc_11a146 { 25269let Inst{7-5} = 0b101; 25270let Inst{13-12} = 0b00; 25271let Inst{31-21} = 0b10001000011; 25272let hasNewValue = 1; 25273let opNewValue = 0; 25274let prefersSlot3 = 1; 25275let Defs = [USR_OVF]; 25276} 25277def S5_popcountp : HInst< 25278(outs IntRegs:$Rd32), 25279(ins DoubleRegs:$Rss32), 25280"$Rd32 = popcount($Rss32)", 25281tc_703e822c, TypeS_2op>, Enc_90cd8b { 25282let Inst{13-5} = 0b000000011; 25283let Inst{31-21} = 0b10001000011; 25284let hasNewValue = 1; 25285let opNewValue = 0; 25286let prefersSlot3 = 1; 25287} 25288def S5_vasrhrnd : HInst< 25289(outs DoubleRegs:$Rdd32), 25290(ins DoubleRegs:$Rss32, u4_0Imm:$Ii), 25291"$Rdd32 = vasrh($Rss32,#$Ii):raw", 25292tc_002cb246, TypeS_2op>, Enc_12b6e9 { 25293let Inst{7-5} = 0b000; 25294let Inst{13-12} = 0b00; 25295let Inst{31-21} = 0b10000000001; 25296let prefersSlot3 = 1; 25297} 25298def S5_vasrhrnd_goodsyntax : HInst< 25299(outs DoubleRegs:$Rdd32), 25300(ins DoubleRegs:$Rss32, u4_0Imm:$Ii), 25301"$Rdd32 = vasrh($Rss32,#$Ii):rnd", 25302tc_002cb246, TypeS_2op> { 25303let isPseudo = 1; 25304} 25305def S6_allocframe_to_raw : HInst< 25306(outs), 25307(ins u11_3Imm:$Ii), 25308"allocframe(#$Ii)", 25309tc_b44ecf75, TypeMAPPING>, Requires<[HasV65]> { 25310let isPseudo = 1; 25311let isCodeGenOnly = 1; 25312} 25313def S6_rol_i_p : HInst< 25314(outs DoubleRegs:$Rdd32), 25315(ins DoubleRegs:$Rss32, u6_0Imm:$Ii), 25316"$Rdd32 = rol($Rss32,#$Ii)", 25317tc_1fc97744, TypeS_2op>, Enc_5eac98, Requires<[HasV60]> { 25318let Inst{7-5} = 0b011; 25319let Inst{31-21} = 0b10000000000; 25320} 25321def S6_rol_i_p_acc : HInst< 25322(outs DoubleRegs:$Rxx32), 25323(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii), 25324"$Rxx32 += rol($Rss32,#$Ii)", 25325tc_784490da, TypeS_2op>, Enc_70fb07, Requires<[HasV60]> { 25326let Inst{7-5} = 0b111; 25327let Inst{31-21} = 0b10000010000; 25328let prefersSlot3 = 1; 25329let Constraints = "$Rxx32 = $Rxx32in"; 25330} 25331def S6_rol_i_p_and : HInst< 25332(outs DoubleRegs:$Rxx32), 25333(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii), 25334"$Rxx32 &= rol($Rss32,#$Ii)", 25335tc_784490da, TypeS_2op>, Enc_70fb07, Requires<[HasV60]> { 25336let Inst{7-5} = 0b011; 25337let Inst{31-21} = 0b10000010010; 25338let prefersSlot3 = 1; 25339let Constraints = "$Rxx32 = $Rxx32in"; 25340} 25341def S6_rol_i_p_nac : HInst< 25342(outs DoubleRegs:$Rxx32), 25343(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii), 25344"$Rxx32 -= rol($Rss32,#$Ii)", 25345tc_784490da, TypeS_2op>, Enc_70fb07, Requires<[HasV60]> { 25346let Inst{7-5} = 0b011; 25347let Inst{31-21} = 0b10000010000; 25348let prefersSlot3 = 1; 25349let Constraints = "$Rxx32 = $Rxx32in"; 25350} 25351def S6_rol_i_p_or : HInst< 25352(outs DoubleRegs:$Rxx32), 25353(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii), 25354"$Rxx32 |= rol($Rss32,#$Ii)", 25355tc_784490da, TypeS_2op>, Enc_70fb07, Requires<[HasV60]> { 25356let Inst{7-5} = 0b111; 25357let Inst{31-21} = 0b10000010010; 25358let prefersSlot3 = 1; 25359let Constraints = "$Rxx32 = $Rxx32in"; 25360} 25361def S6_rol_i_p_xacc : HInst< 25362(outs DoubleRegs:$Rxx32), 25363(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii), 25364"$Rxx32 ^= rol($Rss32,#$Ii)", 25365tc_784490da, TypeS_2op>, Enc_70fb07, Requires<[HasV60]> { 25366let Inst{7-5} = 0b011; 25367let Inst{31-21} = 0b10000010100; 25368let prefersSlot3 = 1; 25369let Constraints = "$Rxx32 = $Rxx32in"; 25370} 25371def S6_rol_i_r : HInst< 25372(outs IntRegs:$Rd32), 25373(ins IntRegs:$Rs32, u5_0Imm:$Ii), 25374"$Rd32 = rol($Rs32,#$Ii)", 25375tc_1fc97744, TypeS_2op>, Enc_a05677, Requires<[HasV60]> { 25376let Inst{7-5} = 0b011; 25377let Inst{13-13} = 0b0; 25378let Inst{31-21} = 0b10001100000; 25379let hasNewValue = 1; 25380let opNewValue = 0; 25381} 25382def S6_rol_i_r_acc : HInst< 25383(outs IntRegs:$Rx32), 25384(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii), 25385"$Rx32 += rol($Rs32,#$Ii)", 25386tc_784490da, TypeS_2op>, Enc_28a2dc, Requires<[HasV60]> { 25387let Inst{7-5} = 0b111; 25388let Inst{13-13} = 0b0; 25389let Inst{31-21} = 0b10001110000; 25390let hasNewValue = 1; 25391let opNewValue = 0; 25392let prefersSlot3 = 1; 25393let Constraints = "$Rx32 = $Rx32in"; 25394} 25395def S6_rol_i_r_and : HInst< 25396(outs IntRegs:$Rx32), 25397(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii), 25398"$Rx32 &= rol($Rs32,#$Ii)", 25399tc_784490da, TypeS_2op>, Enc_28a2dc, Requires<[HasV60]> { 25400let Inst{7-5} = 0b011; 25401let Inst{13-13} = 0b0; 25402let Inst{31-21} = 0b10001110010; 25403let hasNewValue = 1; 25404let opNewValue = 0; 25405let prefersSlot3 = 1; 25406let Constraints = "$Rx32 = $Rx32in"; 25407} 25408def S6_rol_i_r_nac : HInst< 25409(outs IntRegs:$Rx32), 25410(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii), 25411"$Rx32 -= rol($Rs32,#$Ii)", 25412tc_784490da, TypeS_2op>, Enc_28a2dc, Requires<[HasV60]> { 25413let Inst{7-5} = 0b011; 25414let Inst{13-13} = 0b0; 25415let Inst{31-21} = 0b10001110000; 25416let hasNewValue = 1; 25417let opNewValue = 0; 25418let prefersSlot3 = 1; 25419let Constraints = "$Rx32 = $Rx32in"; 25420} 25421def S6_rol_i_r_or : HInst< 25422(outs IntRegs:$Rx32), 25423(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii), 25424"$Rx32 |= rol($Rs32,#$Ii)", 25425tc_784490da, TypeS_2op>, Enc_28a2dc, Requires<[HasV60]> { 25426let Inst{7-5} = 0b111; 25427let Inst{13-13} = 0b0; 25428let Inst{31-21} = 0b10001110010; 25429let hasNewValue = 1; 25430let opNewValue = 0; 25431let prefersSlot3 = 1; 25432let Constraints = "$Rx32 = $Rx32in"; 25433} 25434def S6_rol_i_r_xacc : HInst< 25435(outs IntRegs:$Rx32), 25436(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii), 25437"$Rx32 ^= rol($Rs32,#$Ii)", 25438tc_784490da, TypeS_2op>, Enc_28a2dc, Requires<[HasV60]> { 25439let Inst{7-5} = 0b011; 25440let Inst{13-13} = 0b0; 25441let Inst{31-21} = 0b10001110100; 25442let hasNewValue = 1; 25443let opNewValue = 0; 25444let prefersSlot3 = 1; 25445let Constraints = "$Rx32 = $Rx32in"; 25446} 25447def S6_vsplatrbp : HInst< 25448(outs DoubleRegs:$Rdd32), 25449(ins IntRegs:$Rs32), 25450"$Rdd32 = vsplatb($Rs32)", 25451tc_a1c00888, TypeS_2op>, Enc_3a3d62, Requires<[HasV62]> { 25452let Inst{13-5} = 0b000000100; 25453let Inst{31-21} = 0b10000100010; 25454} 25455def S6_vtrunehb_ppp : HInst< 25456(outs DoubleRegs:$Rdd32), 25457(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 25458"$Rdd32 = vtrunehb($Rss32,$Rtt32)", 25459tc_1fc97744, TypeS_3op>, Enc_a56825, Requires<[HasV62]> { 25460let Inst{7-5} = 0b011; 25461let Inst{13-13} = 0b0; 25462let Inst{31-21} = 0b11000001100; 25463} 25464def S6_vtrunohb_ppp : HInst< 25465(outs DoubleRegs:$Rdd32), 25466(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), 25467"$Rdd32 = vtrunohb($Rss32,$Rtt32)", 25468tc_1fc97744, TypeS_3op>, Enc_a56825, Requires<[HasV62]> { 25469let Inst{7-5} = 0b101; 25470let Inst{13-13} = 0b0; 25471let Inst{31-21} = 0b11000001100; 25472} 25473def SA1_addi : HInst< 25474(outs GeneralSubRegs:$Rx16), 25475(ins IntRegs:$Rx16in, s32_0Imm:$Ii), 25476"$Rx16 = add($Rx16in,#$Ii)", 25477tc_0a705168, TypeSUBINSN>, Enc_93af4c { 25478let Inst{12-11} = 0b00; 25479let hasNewValue = 1; 25480let opNewValue = 0; 25481let AsmVariantName = "NonParsable"; 25482let DecoderNamespace = "SUBINSN_A"; 25483let isExtendable = 1; 25484let opExtendable = 2; 25485let isExtentSigned = 1; 25486let opExtentBits = 7; 25487let opExtentAlign = 0; 25488let Constraints = "$Rx16 = $Rx16in"; 25489} 25490def SA1_addrx : HInst< 25491(outs GeneralSubRegs:$Rx16), 25492(ins IntRegs:$Rx16in, GeneralSubRegs:$Rs16), 25493"$Rx16 = add($Rx16in,$Rs16)", 25494tc_0a705168, TypeSUBINSN>, Enc_0527db { 25495let Inst{12-8} = 0b11000; 25496let hasNewValue = 1; 25497let opNewValue = 0; 25498let AsmVariantName = "NonParsable"; 25499let DecoderNamespace = "SUBINSN_A"; 25500let Constraints = "$Rx16 = $Rx16in"; 25501} 25502def SA1_addsp : HInst< 25503(outs GeneralSubRegs:$Rd16), 25504(ins u6_2Imm:$Ii), 25505"$Rd16 = add(r29,#$Ii)", 25506tc_9fc3dae0, TypeSUBINSN>, Enc_2df31d { 25507let Inst{12-10} = 0b011; 25508let hasNewValue = 1; 25509let opNewValue = 0; 25510let AsmVariantName = "NonParsable"; 25511let Uses = [R29]; 25512let DecoderNamespace = "SUBINSN_A"; 25513} 25514def SA1_and1 : HInst< 25515(outs GeneralSubRegs:$Rd16), 25516(ins GeneralSubRegs:$Rs16), 25517"$Rd16 = and($Rs16,#1)", 25518tc_9fc3dae0, TypeSUBINSN>, Enc_97d666 { 25519let Inst{12-8} = 0b10010; 25520let hasNewValue = 1; 25521let opNewValue = 0; 25522let AsmVariantName = "NonParsable"; 25523let DecoderNamespace = "SUBINSN_A"; 25524} 25525def SA1_clrf : HInst< 25526(outs GeneralSubRegs:$Rd16), 25527(ins), 25528"if (!p0) $Rd16 = #0", 25529tc_a1123dda, TypeSUBINSN>, Enc_1f5ba6 { 25530let Inst{12-4} = 0b110100111; 25531let isPredicated = 1; 25532let isPredicatedFalse = 1; 25533let hasNewValue = 1; 25534let opNewValue = 0; 25535let AsmVariantName = "NonParsable"; 25536let Uses = [P0]; 25537let DecoderNamespace = "SUBINSN_A"; 25538} 25539def SA1_clrfnew : HInst< 25540(outs GeneralSubRegs:$Rd16), 25541(ins), 25542"if (!p0.new) $Rd16 = #0", 25543tc_8b3e402a, TypeSUBINSN>, Enc_1f5ba6 { 25544let Inst{12-4} = 0b110100101; 25545let isPredicated = 1; 25546let isPredicatedFalse = 1; 25547let hasNewValue = 1; 25548let opNewValue = 0; 25549let AsmVariantName = "NonParsable"; 25550let isPredicatedNew = 1; 25551let Uses = [P0]; 25552let DecoderNamespace = "SUBINSN_A"; 25553} 25554def SA1_clrt : HInst< 25555(outs GeneralSubRegs:$Rd16), 25556(ins), 25557"if (p0) $Rd16 = #0", 25558tc_a1123dda, TypeSUBINSN>, Enc_1f5ba6 { 25559let Inst{12-4} = 0b110100110; 25560let isPredicated = 1; 25561let hasNewValue = 1; 25562let opNewValue = 0; 25563let AsmVariantName = "NonParsable"; 25564let Uses = [P0]; 25565let DecoderNamespace = "SUBINSN_A"; 25566} 25567def SA1_clrtnew : HInst< 25568(outs GeneralSubRegs:$Rd16), 25569(ins), 25570"if (p0.new) $Rd16 = #0", 25571tc_8b3e402a, TypeSUBINSN>, Enc_1f5ba6 { 25572let Inst{12-4} = 0b110100100; 25573let isPredicated = 1; 25574let hasNewValue = 1; 25575let opNewValue = 0; 25576let AsmVariantName = "NonParsable"; 25577let isPredicatedNew = 1; 25578let Uses = [P0]; 25579let DecoderNamespace = "SUBINSN_A"; 25580} 25581def SA1_cmpeqi : HInst< 25582(outs), 25583(ins GeneralSubRegs:$Rs16, u2_0Imm:$Ii), 25584"p0 = cmp.eq($Rs16,#$Ii)", 25585tc_5b7c0967, TypeSUBINSN>, Enc_63eaeb { 25586let Inst{3-2} = 0b00; 25587let Inst{12-8} = 0b11001; 25588let AsmVariantName = "NonParsable"; 25589let Defs = [P0]; 25590let DecoderNamespace = "SUBINSN_A"; 25591} 25592def SA1_combine0i : HInst< 25593(outs GeneralDoubleLow8Regs:$Rdd8), 25594(ins u2_0Imm:$Ii), 25595"$Rdd8 = combine(#0,#$Ii)", 25596tc_9fc3dae0, TypeSUBINSN>, Enc_ed48be { 25597let Inst{4-3} = 0b00; 25598let Inst{12-7} = 0b111000; 25599let hasNewValue = 1; 25600let opNewValue = 0; 25601let AsmVariantName = "NonParsable"; 25602let DecoderNamespace = "SUBINSN_A"; 25603} 25604def SA1_combine1i : HInst< 25605(outs GeneralDoubleLow8Regs:$Rdd8), 25606(ins u2_0Imm:$Ii), 25607"$Rdd8 = combine(#1,#$Ii)", 25608tc_9fc3dae0, TypeSUBINSN>, Enc_ed48be { 25609let Inst{4-3} = 0b01; 25610let Inst{12-7} = 0b111000; 25611let hasNewValue = 1; 25612let opNewValue = 0; 25613let AsmVariantName = "NonParsable"; 25614let DecoderNamespace = "SUBINSN_A"; 25615} 25616def SA1_combine2i : HInst< 25617(outs GeneralDoubleLow8Regs:$Rdd8), 25618(ins u2_0Imm:$Ii), 25619"$Rdd8 = combine(#2,#$Ii)", 25620tc_9fc3dae0, TypeSUBINSN>, Enc_ed48be { 25621let Inst{4-3} = 0b10; 25622let Inst{12-7} = 0b111000; 25623let hasNewValue = 1; 25624let opNewValue = 0; 25625let AsmVariantName = "NonParsable"; 25626let DecoderNamespace = "SUBINSN_A"; 25627} 25628def SA1_combine3i : HInst< 25629(outs GeneralDoubleLow8Regs:$Rdd8), 25630(ins u2_0Imm:$Ii), 25631"$Rdd8 = combine(#3,#$Ii)", 25632tc_9fc3dae0, TypeSUBINSN>, Enc_ed48be { 25633let Inst{4-3} = 0b11; 25634let Inst{12-7} = 0b111000; 25635let hasNewValue = 1; 25636let opNewValue = 0; 25637let AsmVariantName = "NonParsable"; 25638let DecoderNamespace = "SUBINSN_A"; 25639} 25640def SA1_combinerz : HInst< 25641(outs GeneralDoubleLow8Regs:$Rdd8), 25642(ins GeneralSubRegs:$Rs16), 25643"$Rdd8 = combine($Rs16,#0)", 25644tc_9fc3dae0, TypeSUBINSN>, Enc_399e12 { 25645let Inst{3-3} = 0b1; 25646let Inst{12-8} = 0b11101; 25647let hasNewValue = 1; 25648let opNewValue = 0; 25649let AsmVariantName = "NonParsable"; 25650let DecoderNamespace = "SUBINSN_A"; 25651} 25652def SA1_combinezr : HInst< 25653(outs GeneralDoubleLow8Regs:$Rdd8), 25654(ins GeneralSubRegs:$Rs16), 25655"$Rdd8 = combine(#0,$Rs16)", 25656tc_9fc3dae0, TypeSUBINSN>, Enc_399e12 { 25657let Inst{3-3} = 0b0; 25658let Inst{12-8} = 0b11101; 25659let hasNewValue = 1; 25660let opNewValue = 0; 25661let AsmVariantName = "NonParsable"; 25662let DecoderNamespace = "SUBINSN_A"; 25663} 25664def SA1_dec : HInst< 25665(outs GeneralSubRegs:$Rd16), 25666(ins GeneralSubRegs:$Rs16, n1Const:$n1), 25667"$Rd16 = add($Rs16,#$n1)", 25668tc_0a705168, TypeSUBINSN>, Enc_ee5ed0 { 25669let Inst{12-8} = 0b10011; 25670let hasNewValue = 1; 25671let opNewValue = 0; 25672let AsmVariantName = "NonParsable"; 25673let DecoderNamespace = "SUBINSN_A"; 25674} 25675def SA1_inc : HInst< 25676(outs GeneralSubRegs:$Rd16), 25677(ins GeneralSubRegs:$Rs16), 25678"$Rd16 = add($Rs16,#1)", 25679tc_9fc3dae0, TypeSUBINSN>, Enc_97d666 { 25680let Inst{12-8} = 0b10001; 25681let hasNewValue = 1; 25682let opNewValue = 0; 25683let AsmVariantName = "NonParsable"; 25684let DecoderNamespace = "SUBINSN_A"; 25685} 25686def SA1_seti : HInst< 25687(outs GeneralSubRegs:$Rd16), 25688(ins u32_0Imm:$Ii), 25689"$Rd16 = #$Ii", 25690tc_9fc3dae0, TypeSUBINSN>, Enc_e39bb2 { 25691let Inst{12-10} = 0b010; 25692let hasNewValue = 1; 25693let opNewValue = 0; 25694let AsmVariantName = "NonParsable"; 25695let DecoderNamespace = "SUBINSN_A"; 25696let isExtendable = 1; 25697let opExtendable = 1; 25698let isExtentSigned = 0; 25699let opExtentBits = 6; 25700let opExtentAlign = 0; 25701} 25702def SA1_setin1 : HInst< 25703(outs GeneralSubRegs:$Rd16), 25704(ins n1Const:$n1), 25705"$Rd16 = #$n1", 25706tc_9fc3dae0, TypeSUBINSN>, Enc_7a0ea6 { 25707let Inst{12-4} = 0b110100000; 25708let hasNewValue = 1; 25709let opNewValue = 0; 25710let AsmVariantName = "NonParsable"; 25711let DecoderNamespace = "SUBINSN_A"; 25712} 25713def SA1_sxtb : HInst< 25714(outs GeneralSubRegs:$Rd16), 25715(ins GeneralSubRegs:$Rs16), 25716"$Rd16 = sxtb($Rs16)", 25717tc_9fc3dae0, TypeSUBINSN>, Enc_97d666 { 25718let Inst{12-8} = 0b10101; 25719let hasNewValue = 1; 25720let opNewValue = 0; 25721let AsmVariantName = "NonParsable"; 25722let DecoderNamespace = "SUBINSN_A"; 25723} 25724def SA1_sxth : HInst< 25725(outs GeneralSubRegs:$Rd16), 25726(ins GeneralSubRegs:$Rs16), 25727"$Rd16 = sxth($Rs16)", 25728tc_9fc3dae0, TypeSUBINSN>, Enc_97d666 { 25729let Inst{12-8} = 0b10100; 25730let hasNewValue = 1; 25731let opNewValue = 0; 25732let AsmVariantName = "NonParsable"; 25733let DecoderNamespace = "SUBINSN_A"; 25734} 25735def SA1_tfr : HInst< 25736(outs GeneralSubRegs:$Rd16), 25737(ins GeneralSubRegs:$Rs16), 25738"$Rd16 = $Rs16", 25739tc_9fc3dae0, TypeSUBINSN>, Enc_97d666 { 25740let Inst{12-8} = 0b10000; 25741let hasNewValue = 1; 25742let opNewValue = 0; 25743let AsmVariantName = "NonParsable"; 25744let DecoderNamespace = "SUBINSN_A"; 25745} 25746def SA1_zxtb : HInst< 25747(outs GeneralSubRegs:$Rd16), 25748(ins GeneralSubRegs:$Rs16), 25749"$Rd16 = and($Rs16,#255)", 25750tc_9fc3dae0, TypeSUBINSN>, Enc_97d666 { 25751let Inst{12-8} = 0b10111; 25752let hasNewValue = 1; 25753let opNewValue = 0; 25754let AsmVariantName = "NonParsable"; 25755let DecoderNamespace = "SUBINSN_A"; 25756} 25757def SA1_zxth : HInst< 25758(outs GeneralSubRegs:$Rd16), 25759(ins GeneralSubRegs:$Rs16), 25760"$Rd16 = zxth($Rs16)", 25761tc_9fc3dae0, TypeSUBINSN>, Enc_97d666 { 25762let Inst{12-8} = 0b10110; 25763let hasNewValue = 1; 25764let opNewValue = 0; 25765let AsmVariantName = "NonParsable"; 25766let DecoderNamespace = "SUBINSN_A"; 25767} 25768def SL1_loadri_io : HInst< 25769(outs GeneralSubRegs:$Rd16), 25770(ins GeneralSubRegs:$Rs16, u4_2Imm:$Ii), 25771"$Rd16 = memw($Rs16+#$Ii)", 25772tc_17e0d2cd, TypeSUBINSN>, Enc_53dca9 { 25773let Inst{12-12} = 0b0; 25774let hasNewValue = 1; 25775let opNewValue = 0; 25776let addrMode = BaseImmOffset; 25777let accessSize = WordAccess; 25778let AsmVariantName = "NonParsable"; 25779let mayLoad = 1; 25780let DecoderNamespace = "SUBINSN_L1"; 25781} 25782def SL1_loadrub_io : HInst< 25783(outs GeneralSubRegs:$Rd16), 25784(ins GeneralSubRegs:$Rs16, u4_0Imm:$Ii), 25785"$Rd16 = memub($Rs16+#$Ii)", 25786tc_17e0d2cd, TypeSUBINSN>, Enc_c175d0 { 25787let Inst{12-12} = 0b1; 25788let hasNewValue = 1; 25789let opNewValue = 0; 25790let addrMode = BaseImmOffset; 25791let accessSize = ByteAccess; 25792let AsmVariantName = "NonParsable"; 25793let mayLoad = 1; 25794let DecoderNamespace = "SUBINSN_L1"; 25795} 25796def SL2_deallocframe : HInst< 25797(outs), 25798(ins), 25799"deallocframe", 25800tc_39dfefe8, TypeSUBINSN>, Enc_e3b0c4 { 25801let Inst{12-0} = 0b1111100000000; 25802let accessSize = DoubleWordAccess; 25803let AsmVariantName = "NonParsable"; 25804let mayLoad = 1; 25805let Uses = [FRAMEKEY, R30]; 25806let Defs = [R30, R29, R31]; 25807let DecoderNamespace = "SUBINSN_L2"; 25808} 25809def SL2_jumpr31 : HInst< 25810(outs), 25811(ins), 25812"jumpr r31", 25813tc_b4407292, TypeSUBINSN>, Enc_e3b0c4 { 25814let Inst{12-0} = 0b1111111000000; 25815let isTerminator = 1; 25816let isIndirectBranch = 1; 25817let AsmVariantName = "NonParsable"; 25818let cofMax1 = 1; 25819let isReturn = 1; 25820let Uses = [R31]; 25821let Defs = [PC]; 25822let DecoderNamespace = "SUBINSN_L2"; 25823} 25824def SL2_jumpr31_f : HInst< 25825(outs), 25826(ins), 25827"if (!p0) jumpr r31", 25828tc_b4407292, TypeSUBINSN>, Enc_e3b0c4 { 25829let Inst{12-0} = 0b1111111000101; 25830let isPredicated = 1; 25831let isPredicatedFalse = 1; 25832let isTerminator = 1; 25833let isIndirectBranch = 1; 25834let AsmVariantName = "NonParsable"; 25835let cofMax1 = 1; 25836let isReturn = 1; 25837let Uses = [P0, R31]; 25838let Defs = [PC]; 25839let isTaken = Inst{4}; 25840let DecoderNamespace = "SUBINSN_L2"; 25841} 25842def SL2_jumpr31_fnew : HInst< 25843(outs), 25844(ins), 25845"if (!p0.new) jumpr:nt r31", 25846tc_b4407292, TypeSUBINSN>, Enc_e3b0c4 { 25847let Inst{12-0} = 0b1111111000111; 25848let isPredicated = 1; 25849let isPredicatedFalse = 1; 25850let isTerminator = 1; 25851let isIndirectBranch = 1; 25852let AsmVariantName = "NonParsable"; 25853let isPredicatedNew = 1; 25854let cofMax1 = 1; 25855let isReturn = 1; 25856let Uses = [P0, R31]; 25857let Defs = [PC]; 25858let isTaken = Inst{4}; 25859let DecoderNamespace = "SUBINSN_L2"; 25860} 25861def SL2_jumpr31_t : HInst< 25862(outs), 25863(ins), 25864"if (p0) jumpr r31", 25865tc_b4407292, TypeSUBINSN>, Enc_e3b0c4 { 25866let Inst{12-0} = 0b1111111000100; 25867let isPredicated = 1; 25868let isTerminator = 1; 25869let isIndirectBranch = 1; 25870let AsmVariantName = "NonParsable"; 25871let cofMax1 = 1; 25872let isReturn = 1; 25873let Uses = [P0, R31]; 25874let Defs = [PC]; 25875let isTaken = Inst{4}; 25876let DecoderNamespace = "SUBINSN_L2"; 25877} 25878def SL2_jumpr31_tnew : HInst< 25879(outs), 25880(ins), 25881"if (p0.new) jumpr:nt r31", 25882tc_b4407292, TypeSUBINSN>, Enc_e3b0c4 { 25883let Inst{12-0} = 0b1111111000110; 25884let isPredicated = 1; 25885let isTerminator = 1; 25886let isIndirectBranch = 1; 25887let AsmVariantName = "NonParsable"; 25888let isPredicatedNew = 1; 25889let cofMax1 = 1; 25890let isReturn = 1; 25891let Uses = [P0, R31]; 25892let Defs = [PC]; 25893let isTaken = Inst{4}; 25894let DecoderNamespace = "SUBINSN_L2"; 25895} 25896def SL2_loadrb_io : HInst< 25897(outs GeneralSubRegs:$Rd16), 25898(ins GeneralSubRegs:$Rs16, u3_0Imm:$Ii), 25899"$Rd16 = memb($Rs16+#$Ii)", 25900tc_17e0d2cd, TypeSUBINSN>, Enc_2fbf3c { 25901let Inst{12-11} = 0b10; 25902let hasNewValue = 1; 25903let opNewValue = 0; 25904let addrMode = BaseImmOffset; 25905let accessSize = ByteAccess; 25906let AsmVariantName = "NonParsable"; 25907let mayLoad = 1; 25908let DecoderNamespace = "SUBINSN_L2"; 25909} 25910def SL2_loadrd_sp : HInst< 25911(outs GeneralDoubleLow8Regs:$Rdd8), 25912(ins u5_3Imm:$Ii), 25913"$Rdd8 = memd(r29+#$Ii)", 25914tc_c4db48cb, TypeSUBINSN>, Enc_86a14b { 25915let Inst{12-8} = 0b11110; 25916let hasNewValue = 1; 25917let opNewValue = 0; 25918let addrMode = BaseImmOffset; 25919let accessSize = DoubleWordAccess; 25920let AsmVariantName = "NonParsable"; 25921let mayLoad = 1; 25922let Uses = [R29]; 25923let DecoderNamespace = "SUBINSN_L2"; 25924} 25925def SL2_loadrh_io : HInst< 25926(outs GeneralSubRegs:$Rd16), 25927(ins GeneralSubRegs:$Rs16, u3_1Imm:$Ii), 25928"$Rd16 = memh($Rs16+#$Ii)", 25929tc_17e0d2cd, TypeSUBINSN>, Enc_2bae10 { 25930let Inst{12-11} = 0b00; 25931let hasNewValue = 1; 25932let opNewValue = 0; 25933let addrMode = BaseImmOffset; 25934let accessSize = HalfWordAccess; 25935let AsmVariantName = "NonParsable"; 25936let mayLoad = 1; 25937let DecoderNamespace = "SUBINSN_L2"; 25938} 25939def SL2_loadri_sp : HInst< 25940(outs GeneralSubRegs:$Rd16), 25941(ins u5_2Imm:$Ii), 25942"$Rd16 = memw(r29+#$Ii)", 25943tc_c4db48cb, TypeSUBINSN>, Enc_51635c { 25944let Inst{12-9} = 0b1110; 25945let hasNewValue = 1; 25946let opNewValue = 0; 25947let addrMode = BaseImmOffset; 25948let accessSize = WordAccess; 25949let AsmVariantName = "NonParsable"; 25950let mayLoad = 1; 25951let Uses = [R29]; 25952let DecoderNamespace = "SUBINSN_L2"; 25953} 25954def SL2_loadruh_io : HInst< 25955(outs GeneralSubRegs:$Rd16), 25956(ins GeneralSubRegs:$Rs16, u3_1Imm:$Ii), 25957"$Rd16 = memuh($Rs16+#$Ii)", 25958tc_17e0d2cd, TypeSUBINSN>, Enc_2bae10 { 25959let Inst{12-11} = 0b01; 25960let hasNewValue = 1; 25961let opNewValue = 0; 25962let addrMode = BaseImmOffset; 25963let accessSize = HalfWordAccess; 25964let AsmVariantName = "NonParsable"; 25965let mayLoad = 1; 25966let DecoderNamespace = "SUBINSN_L2"; 25967} 25968def SL2_return : HInst< 25969(outs), 25970(ins), 25971"dealloc_return", 25972tc_36153880, TypeSUBINSN>, Enc_e3b0c4 { 25973let Inst{12-0} = 0b1111101000000; 25974let isTerminator = 1; 25975let isIndirectBranch = 1; 25976let accessSize = DoubleWordAccess; 25977let AsmVariantName = "NonParsable"; 25978let mayLoad = 1; 25979let cofMax1 = 1; 25980let isRestrictNoSlot1Store = 1; 25981let isReturn = 1; 25982let Uses = [FRAMEKEY, R30]; 25983let Defs = [PC, R30, R29, R31]; 25984let DecoderNamespace = "SUBINSN_L2"; 25985} 25986def SL2_return_f : HInst< 25987(outs), 25988(ins), 25989"if (!p0) dealloc_return", 25990tc_36153880, TypeSUBINSN>, Enc_e3b0c4 { 25991let Inst{12-0} = 0b1111101000101; 25992let isPredicated = 1; 25993let isPredicatedFalse = 1; 25994let isTerminator = 1; 25995let isIndirectBranch = 1; 25996let accessSize = DoubleWordAccess; 25997let AsmVariantName = "NonParsable"; 25998let mayLoad = 1; 25999let cofMax1 = 1; 26000let isRestrictNoSlot1Store = 1; 26001let isReturn = 1; 26002let Uses = [FRAMEKEY, P0, R30]; 26003let Defs = [PC, R30, R29, R31]; 26004let isTaken = Inst{4}; 26005let DecoderNamespace = "SUBINSN_L2"; 26006} 26007def SL2_return_fnew : HInst< 26008(outs), 26009(ins), 26010"if (!p0.new) dealloc_return:nt", 26011tc_36153880, TypeSUBINSN>, Enc_e3b0c4 { 26012let Inst{12-0} = 0b1111101000111; 26013let isPredicated = 1; 26014let isPredicatedFalse = 1; 26015let isTerminator = 1; 26016let isIndirectBranch = 1; 26017let accessSize = DoubleWordAccess; 26018let AsmVariantName = "NonParsable"; 26019let isPredicatedNew = 1; 26020let mayLoad = 1; 26021let cofMax1 = 1; 26022let isRestrictNoSlot1Store = 1; 26023let isReturn = 1; 26024let Uses = [FRAMEKEY, P0, R30]; 26025let Defs = [PC, R30, R29, R31]; 26026let isTaken = Inst{4}; 26027let DecoderNamespace = "SUBINSN_L2"; 26028} 26029def SL2_return_t : HInst< 26030(outs), 26031(ins), 26032"if (p0) dealloc_return", 26033tc_36153880, TypeSUBINSN>, Enc_e3b0c4 { 26034let Inst{12-0} = 0b1111101000100; 26035let isPredicated = 1; 26036let isTerminator = 1; 26037let isIndirectBranch = 1; 26038let accessSize = DoubleWordAccess; 26039let AsmVariantName = "NonParsable"; 26040let mayLoad = 1; 26041let cofMax1 = 1; 26042let isRestrictNoSlot1Store = 1; 26043let isReturn = 1; 26044let Uses = [FRAMEKEY, P0, R30]; 26045let Defs = [PC, R30, R29, R31]; 26046let isTaken = Inst{4}; 26047let DecoderNamespace = "SUBINSN_L2"; 26048} 26049def SL2_return_tnew : HInst< 26050(outs), 26051(ins), 26052"if (p0.new) dealloc_return:nt", 26053tc_36153880, TypeSUBINSN>, Enc_e3b0c4 { 26054let Inst{12-0} = 0b1111101000110; 26055let isPredicated = 1; 26056let isTerminator = 1; 26057let isIndirectBranch = 1; 26058let accessSize = DoubleWordAccess; 26059let AsmVariantName = "NonParsable"; 26060let isPredicatedNew = 1; 26061let mayLoad = 1; 26062let cofMax1 = 1; 26063let isRestrictNoSlot1Store = 1; 26064let isReturn = 1; 26065let Uses = [FRAMEKEY, P0, R30]; 26066let Defs = [PC, R30, R29, R31]; 26067let isTaken = Inst{4}; 26068let DecoderNamespace = "SUBINSN_L2"; 26069} 26070def SS1_storeb_io : HInst< 26071(outs), 26072(ins GeneralSubRegs:$Rs16, u4_0Imm:$Ii, GeneralSubRegs:$Rt16), 26073"memb($Rs16+#$Ii) = $Rt16", 26074tc_30b9bb4a, TypeSUBINSN>, Enc_b38ffc { 26075let Inst{12-12} = 0b1; 26076let addrMode = BaseImmOffset; 26077let accessSize = ByteAccess; 26078let AsmVariantName = "NonParsable"; 26079let mayStore = 1; 26080let DecoderNamespace = "SUBINSN_S1"; 26081} 26082def SS1_storew_io : HInst< 26083(outs), 26084(ins GeneralSubRegs:$Rs16, u4_2Imm:$Ii, GeneralSubRegs:$Rt16), 26085"memw($Rs16+#$Ii) = $Rt16", 26086tc_30b9bb4a, TypeSUBINSN>, Enc_f55a0c { 26087let Inst{12-12} = 0b0; 26088let addrMode = BaseImmOffset; 26089let accessSize = WordAccess; 26090let AsmVariantName = "NonParsable"; 26091let mayStore = 1; 26092let DecoderNamespace = "SUBINSN_S1"; 26093} 26094def SS2_allocframe : HInst< 26095(outs), 26096(ins u5_3Imm:$Ii), 26097"allocframe(#$Ii)", 26098tc_49a8207d, TypeSUBINSN>, Enc_6f70ca { 26099let Inst{3-0} = 0b0000; 26100let Inst{12-9} = 0b1110; 26101let addrMode = BaseImmOffset; 26102let accessSize = DoubleWordAccess; 26103let AsmVariantName = "NonParsable"; 26104let mayStore = 1; 26105let Uses = [FRAMEKEY, FRAMELIMIT, R30, R29, R31]; 26106let Defs = [R30, R29]; 26107let DecoderNamespace = "SUBINSN_S2"; 26108} 26109def SS2_storebi0 : HInst< 26110(outs), 26111(ins GeneralSubRegs:$Rs16, u4_0Imm:$Ii), 26112"memb($Rs16+#$Ii) = #0", 26113tc_89e94ad3, TypeSUBINSN>, Enc_84d359 { 26114let Inst{12-8} = 0b10010; 26115let addrMode = BaseImmOffset; 26116let accessSize = ByteAccess; 26117let AsmVariantName = "NonParsable"; 26118let mayStore = 1; 26119let DecoderNamespace = "SUBINSN_S2"; 26120} 26121def SS2_storebi1 : HInst< 26122(outs), 26123(ins GeneralSubRegs:$Rs16, u4_0Imm:$Ii), 26124"memb($Rs16+#$Ii) = #1", 26125tc_89e94ad3, TypeSUBINSN>, Enc_84d359 { 26126let Inst{12-8} = 0b10011; 26127let addrMode = BaseImmOffset; 26128let accessSize = ByteAccess; 26129let AsmVariantName = "NonParsable"; 26130let mayStore = 1; 26131let DecoderNamespace = "SUBINSN_S2"; 26132} 26133def SS2_stored_sp : HInst< 26134(outs), 26135(ins s6_3Imm:$Ii, GeneralDoubleLow8Regs:$Rtt8), 26136"memd(r29+#$Ii) = $Rtt8", 26137tc_0371abea, TypeSUBINSN>, Enc_b8309d { 26138let Inst{12-9} = 0b0101; 26139let addrMode = BaseImmOffset; 26140let accessSize = DoubleWordAccess; 26141let AsmVariantName = "NonParsable"; 26142let mayStore = 1; 26143let Uses = [R29]; 26144let DecoderNamespace = "SUBINSN_S2"; 26145} 26146def SS2_storeh_io : HInst< 26147(outs), 26148(ins GeneralSubRegs:$Rs16, u3_1Imm:$Ii, GeneralSubRegs:$Rt16), 26149"memh($Rs16+#$Ii) = $Rt16", 26150tc_30b9bb4a, TypeSUBINSN>, Enc_625deb { 26151let Inst{12-11} = 0b00; 26152let addrMode = BaseImmOffset; 26153let accessSize = HalfWordAccess; 26154let AsmVariantName = "NonParsable"; 26155let mayStore = 1; 26156let DecoderNamespace = "SUBINSN_S2"; 26157} 26158def SS2_storew_sp : HInst< 26159(outs), 26160(ins u5_2Imm:$Ii, GeneralSubRegs:$Rt16), 26161"memw(r29+#$Ii) = $Rt16", 26162tc_0371abea, TypeSUBINSN>, Enc_87c142 { 26163let Inst{12-9} = 0b0100; 26164let addrMode = BaseImmOffset; 26165let accessSize = WordAccess; 26166let AsmVariantName = "NonParsable"; 26167let mayStore = 1; 26168let Uses = [R29]; 26169let DecoderNamespace = "SUBINSN_S2"; 26170} 26171def SS2_storewi0 : HInst< 26172(outs), 26173(ins GeneralSubRegs:$Rs16, u4_2Imm:$Ii), 26174"memw($Rs16+#$Ii) = #0", 26175tc_89e94ad3, TypeSUBINSN>, Enc_a6ce9c { 26176let Inst{12-8} = 0b10000; 26177let addrMode = BaseImmOffset; 26178let accessSize = WordAccess; 26179let AsmVariantName = "NonParsable"; 26180let mayStore = 1; 26181let DecoderNamespace = "SUBINSN_S2"; 26182} 26183def SS2_storewi1 : HInst< 26184(outs), 26185(ins GeneralSubRegs:$Rs16, u4_2Imm:$Ii), 26186"memw($Rs16+#$Ii) = #1", 26187tc_89e94ad3, TypeSUBINSN>, Enc_a6ce9c { 26188let Inst{12-8} = 0b10001; 26189let addrMode = BaseImmOffset; 26190let accessSize = WordAccess; 26191let AsmVariantName = "NonParsable"; 26192let mayStore = 1; 26193let DecoderNamespace = "SUBINSN_S2"; 26194} 26195def V6_MAP_equb : HInst< 26196(outs HvxQR:$Qd4), 26197(ins HvxVR:$Vu32, HvxVR:$Vv32), 26198"$Qd4 = vcmp.eq($Vu32.ub,$Vv32.ub)", 26199PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 26200let hasNewValue = 1; 26201let opNewValue = 0; 26202let isPseudo = 1; 26203let isCodeGenOnly = 1; 26204let DecoderNamespace = "EXT_mmvec"; 26205} 26206def V6_MAP_equb_and : HInst< 26207(outs HvxQR:$Qx4), 26208(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), 26209"$Qx4 &= vcmp.eq($Vu32.ub,$Vv32.ub)", 26210PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 26211let isPseudo = 1; 26212let isCodeGenOnly = 1; 26213let DecoderNamespace = "EXT_mmvec"; 26214let Constraints = "$Qx4 = $Qx4in"; 26215} 26216def V6_MAP_equb_ior : HInst< 26217(outs HvxQR:$Qx4), 26218(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), 26219"$Qx4 |= vcmp.eq($Vu32.ub,$Vv32.ub)", 26220PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 26221let isAccumulator = 1; 26222let isPseudo = 1; 26223let isCodeGenOnly = 1; 26224let DecoderNamespace = "EXT_mmvec"; 26225let Constraints = "$Qx4 = $Qx4in"; 26226} 26227def V6_MAP_equb_xor : HInst< 26228(outs HvxQR:$Qx4), 26229(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), 26230"$Qx4 ^= vcmp.eq($Vu32.ub,$Vv32.ub)", 26231PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 26232let isPseudo = 1; 26233let isCodeGenOnly = 1; 26234let DecoderNamespace = "EXT_mmvec"; 26235let Constraints = "$Qx4 = $Qx4in"; 26236} 26237def V6_MAP_equh : HInst< 26238(outs HvxQR:$Qd4), 26239(ins HvxVR:$Vu32, HvxVR:$Vv32), 26240"$Qd4 = vcmp.eq($Vu32.uh,$Vv32.uh)", 26241PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 26242let hasNewValue = 1; 26243let opNewValue = 0; 26244let isPseudo = 1; 26245let isCodeGenOnly = 1; 26246let DecoderNamespace = "EXT_mmvec"; 26247} 26248def V6_MAP_equh_and : HInst< 26249(outs HvxQR:$Qx4), 26250(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), 26251"$Qx4 &= vcmp.eq($Vu32.uh,$Vv32.uh)", 26252PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 26253let isPseudo = 1; 26254let isCodeGenOnly = 1; 26255let DecoderNamespace = "EXT_mmvec"; 26256let Constraints = "$Qx4 = $Qx4in"; 26257} 26258def V6_MAP_equh_ior : HInst< 26259(outs HvxQR:$Qx4), 26260(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), 26261"$Qx4 |= vcmp.eq($Vu32.uh,$Vv32.uh)", 26262PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 26263let isAccumulator = 1; 26264let isPseudo = 1; 26265let isCodeGenOnly = 1; 26266let DecoderNamespace = "EXT_mmvec"; 26267let Constraints = "$Qx4 = $Qx4in"; 26268} 26269def V6_MAP_equh_xor : HInst< 26270(outs HvxQR:$Qx4), 26271(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), 26272"$Qx4 ^= vcmp.eq($Vu32.uh,$Vv32.uh)", 26273PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 26274let isPseudo = 1; 26275let isCodeGenOnly = 1; 26276let DecoderNamespace = "EXT_mmvec"; 26277let Constraints = "$Qx4 = $Qx4in"; 26278} 26279def V6_MAP_equw : HInst< 26280(outs HvxQR:$Qd4), 26281(ins HvxVR:$Vu32, HvxVR:$Vv32), 26282"$Qd4 = vcmp.eq($Vu32.uw,$Vv32.uw)", 26283PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 26284let hasNewValue = 1; 26285let opNewValue = 0; 26286let isPseudo = 1; 26287let isCodeGenOnly = 1; 26288let DecoderNamespace = "EXT_mmvec"; 26289} 26290def V6_MAP_equw_and : HInst< 26291(outs HvxQR:$Qx4), 26292(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), 26293"$Qx4 &= vcmp.eq($Vu32.uw,$Vv32.uw)", 26294PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 26295let isPseudo = 1; 26296let isCodeGenOnly = 1; 26297let DecoderNamespace = "EXT_mmvec"; 26298let Constraints = "$Qx4 = $Qx4in"; 26299} 26300def V6_MAP_equw_ior : HInst< 26301(outs HvxQR:$Qx4), 26302(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), 26303"$Qx4 |= vcmp.eq($Vu32.uw,$Vv32.uw)", 26304PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 26305let isAccumulator = 1; 26306let isPseudo = 1; 26307let isCodeGenOnly = 1; 26308let DecoderNamespace = "EXT_mmvec"; 26309let Constraints = "$Qx4 = $Qx4in"; 26310} 26311def V6_MAP_equw_xor : HInst< 26312(outs HvxQR:$Qx4), 26313(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), 26314"$Qx4 ^= vcmp.eq($Vu32.uw,$Vv32.uw)", 26315PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 26316let isPseudo = 1; 26317let isCodeGenOnly = 1; 26318let DecoderNamespace = "EXT_mmvec"; 26319let Constraints = "$Qx4 = $Qx4in"; 26320} 26321def V6_extractw : HInst< 26322(outs IntRegs:$Rd32), 26323(ins HvxVR:$Vu32, IntRegs:$Rs32), 26324"$Rd32 = vextract($Vu32,$Rs32)", 26325tc_540c3da3, TypeLD>, Enc_50e578, Requires<[UseHVXV60]> { 26326let Inst{7-5} = 0b001; 26327let Inst{13-13} = 0b0; 26328let Inst{31-21} = 0b10010010000; 26329let hasNewValue = 1; 26330let opNewValue = 0; 26331let isSolo = 1; 26332let mayLoad = 1; 26333let DecoderNamespace = "EXT_mmvec"; 26334} 26335def V6_extractw_alt : HInst< 26336(outs IntRegs:$Rd32), 26337(ins HvxVR:$Vu32, IntRegs:$Rs32), 26338"$Rd32.w = vextract($Vu32,$Rs32)", 26339PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 26340let hasNewValue = 1; 26341let opNewValue = 0; 26342let isPseudo = 1; 26343let isCodeGenOnly = 1; 26344let DecoderNamespace = "EXT_mmvec"; 26345} 26346def V6_hi : HInst< 26347(outs HvxVR:$Vd32), 26348(ins HvxWR:$Vss32), 26349"$Vd32 = hi($Vss32)", 26350CVI_VA, TypeCVI_VA>, Requires<[UseHVXV60]> { 26351let hasNewValue = 1; 26352let opNewValue = 0; 26353let isPseudo = 1; 26354let DecoderNamespace = "EXT_mmvec"; 26355} 26356def V6_ld0 : HInst< 26357(outs HvxVR:$Vd32), 26358(ins IntRegs:$Rt32), 26359"$Vd32 = vmem($Rt32)", 26360PSEUDO, TypeCVI_VM_LD>, Requires<[UseHVXV60]> { 26361let hasNewValue = 1; 26362let opNewValue = 0; 26363let isPseudo = 1; 26364let isCodeGenOnly = 1; 26365let DecoderNamespace = "EXT_mmvec"; 26366} 26367def V6_ldcnp0 : HInst< 26368(outs HvxVR:$Vd32), 26369(ins PredRegs:$Pv4, IntRegs:$Rt32), 26370"if (!$Pv4) $Vd32.cur = vmem($Rt32)", 26371PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> { 26372let hasNewValue = 1; 26373let opNewValue = 0; 26374let isPseudo = 1; 26375let isCodeGenOnly = 1; 26376let DecoderNamespace = "EXT_mmvec"; 26377} 26378def V6_ldcnpnt0 : HInst< 26379(outs HvxVR:$Vd32), 26380(ins PredRegs:$Pv4, IntRegs:$Rt32), 26381"if (!$Pv4) $Vd32.cur = vmem($Rt32):nt", 26382PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> { 26383let hasNewValue = 1; 26384let opNewValue = 0; 26385let isPseudo = 1; 26386let isCodeGenOnly = 1; 26387let DecoderNamespace = "EXT_mmvec"; 26388} 26389def V6_ldcp0 : HInst< 26390(outs HvxVR:$Vd32), 26391(ins PredRegs:$Pv4, IntRegs:$Rt32), 26392"if ($Pv4) $Vd32.cur = vmem($Rt32)", 26393PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> { 26394let hasNewValue = 1; 26395let opNewValue = 0; 26396let isPseudo = 1; 26397let isCodeGenOnly = 1; 26398let DecoderNamespace = "EXT_mmvec"; 26399} 26400def V6_ldcpnt0 : HInst< 26401(outs HvxVR:$Vd32), 26402(ins PredRegs:$Pv4, IntRegs:$Rt32), 26403"if ($Pv4) $Vd32.cur = vmem($Rt32):nt", 26404PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> { 26405let hasNewValue = 1; 26406let opNewValue = 0; 26407let isPseudo = 1; 26408let isCodeGenOnly = 1; 26409let DecoderNamespace = "EXT_mmvec"; 26410} 26411def V6_ldnp0 : HInst< 26412(outs HvxVR:$Vd32), 26413(ins PredRegs:$Pv4, IntRegs:$Rt32), 26414"if (!$Pv4) $Vd32 = vmem($Rt32)", 26415PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> { 26416let hasNewValue = 1; 26417let opNewValue = 0; 26418let isPseudo = 1; 26419let isCodeGenOnly = 1; 26420let DecoderNamespace = "EXT_mmvec"; 26421} 26422def V6_ldnpnt0 : HInst< 26423(outs HvxVR:$Vd32), 26424(ins PredRegs:$Pv4, IntRegs:$Rt32), 26425"if (!$Pv4) $Vd32 = vmem($Rt32):nt", 26426PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> { 26427let hasNewValue = 1; 26428let opNewValue = 0; 26429let isPseudo = 1; 26430let isCodeGenOnly = 1; 26431let DecoderNamespace = "EXT_mmvec"; 26432} 26433def V6_ldnt0 : HInst< 26434(outs HvxVR:$Vd32), 26435(ins IntRegs:$Rt32), 26436"$Vd32 = vmem($Rt32):nt", 26437PSEUDO, TypeCVI_VM_LD>, Requires<[UseHVXV60]> { 26438let hasNewValue = 1; 26439let opNewValue = 0; 26440let isPseudo = 1; 26441let isCodeGenOnly = 1; 26442let DecoderNamespace = "EXT_mmvec"; 26443} 26444def V6_ldntnt0 : HInst< 26445(outs HvxVR:$Vd32), 26446(ins IntRegs:$Rt32), 26447"$Vd32 = vmem($Rt32):nt", 26448PSEUDO, TypeMAPPING>, Requires<[HasV62]> { 26449let hasNewValue = 1; 26450let opNewValue = 0; 26451let isPseudo = 1; 26452let isCodeGenOnly = 1; 26453let DecoderNamespace = "EXT_mmvec"; 26454} 26455def V6_ldp0 : HInst< 26456(outs HvxVR:$Vd32), 26457(ins PredRegs:$Pv4, IntRegs:$Rt32), 26458"if ($Pv4) $Vd32 = vmem($Rt32)", 26459PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> { 26460let hasNewValue = 1; 26461let opNewValue = 0; 26462let isPseudo = 1; 26463let isCodeGenOnly = 1; 26464let DecoderNamespace = "EXT_mmvec"; 26465} 26466def V6_ldpnt0 : HInst< 26467(outs HvxVR:$Vd32), 26468(ins PredRegs:$Pv4, IntRegs:$Rt32), 26469"if ($Pv4) $Vd32 = vmem($Rt32):nt", 26470PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> { 26471let hasNewValue = 1; 26472let opNewValue = 0; 26473let isPseudo = 1; 26474let isCodeGenOnly = 1; 26475let DecoderNamespace = "EXT_mmvec"; 26476} 26477def V6_ldtnp0 : HInst< 26478(outs HvxVR:$Vd32), 26479(ins PredRegs:$Pv4, IntRegs:$Rt32), 26480"if (!$Pv4) $Vd32.tmp = vmem($Rt32)", 26481PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> { 26482let hasNewValue = 1; 26483let opNewValue = 0; 26484let isPseudo = 1; 26485let isCodeGenOnly = 1; 26486let DecoderNamespace = "EXT_mmvec"; 26487} 26488def V6_ldtnpnt0 : HInst< 26489(outs HvxVR:$Vd32), 26490(ins PredRegs:$Pv4, IntRegs:$Rt32), 26491"if (!$Pv4) $Vd32.tmp = vmem($Rt32):nt", 26492PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> { 26493let hasNewValue = 1; 26494let opNewValue = 0; 26495let isPseudo = 1; 26496let isCodeGenOnly = 1; 26497let DecoderNamespace = "EXT_mmvec"; 26498} 26499def V6_ldtp0 : HInst< 26500(outs HvxVR:$Vd32), 26501(ins PredRegs:$Pv4, IntRegs:$Rt32), 26502"if ($Pv4) $Vd32.tmp = vmem($Rt32)", 26503PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> { 26504let hasNewValue = 1; 26505let opNewValue = 0; 26506let isPseudo = 1; 26507let isCodeGenOnly = 1; 26508let DecoderNamespace = "EXT_mmvec"; 26509} 26510def V6_ldtpnt0 : HInst< 26511(outs HvxVR:$Vd32), 26512(ins PredRegs:$Pv4, IntRegs:$Rt32), 26513"if ($Pv4) $Vd32.tmp = vmem($Rt32):nt", 26514PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> { 26515let hasNewValue = 1; 26516let opNewValue = 0; 26517let isPseudo = 1; 26518let isCodeGenOnly = 1; 26519let DecoderNamespace = "EXT_mmvec"; 26520} 26521def V6_ldu0 : HInst< 26522(outs HvxVR:$Vd32), 26523(ins IntRegs:$Rt32), 26524"$Vd32 = vmemu($Rt32)", 26525PSEUDO, TypeCVI_VM_LD>, Requires<[UseHVXV60]> { 26526let hasNewValue = 1; 26527let opNewValue = 0; 26528let isPseudo = 1; 26529let isCodeGenOnly = 1; 26530let DecoderNamespace = "EXT_mmvec"; 26531} 26532def V6_lo : HInst< 26533(outs HvxVR:$Vd32), 26534(ins HvxWR:$Vss32), 26535"$Vd32 = lo($Vss32)", 26536CVI_VA, TypeCVI_VA>, Requires<[UseHVXV60]> { 26537let hasNewValue = 1; 26538let opNewValue = 0; 26539let isPseudo = 1; 26540let DecoderNamespace = "EXT_mmvec"; 26541} 26542def V6_lvsplatb : HInst< 26543(outs HvxVR:$Vd32), 26544(ins IntRegs:$Rt32), 26545"$Vd32.b = vsplat($Rt32)", 26546tc_c4edf264, TypeCVI_VX>, Enc_a5ed8a, Requires<[UseHVXV62]> { 26547let Inst{13-5} = 0b000000010; 26548let Inst{31-21} = 0b00011001110; 26549let hasNewValue = 1; 26550let opNewValue = 0; 26551let DecoderNamespace = "EXT_mmvec"; 26552} 26553def V6_lvsplath : HInst< 26554(outs HvxVR:$Vd32), 26555(ins IntRegs:$Rt32), 26556"$Vd32.h = vsplat($Rt32)", 26557tc_c4edf264, TypeCVI_VX>, Enc_a5ed8a, Requires<[UseHVXV62]> { 26558let Inst{13-5} = 0b000000001; 26559let Inst{31-21} = 0b00011001110; 26560let hasNewValue = 1; 26561let opNewValue = 0; 26562let DecoderNamespace = "EXT_mmvec"; 26563} 26564def V6_lvsplatw : HInst< 26565(outs HvxVR:$Vd32), 26566(ins IntRegs:$Rt32), 26567"$Vd32 = vsplat($Rt32)", 26568tc_c4edf264, TypeCVI_VX_LATE>, Enc_a5ed8a, Requires<[UseHVXV60]> { 26569let Inst{13-5} = 0b000000001; 26570let Inst{31-21} = 0b00011001101; 26571let hasNewValue = 1; 26572let opNewValue = 0; 26573let DecoderNamespace = "EXT_mmvec"; 26574} 26575def V6_pred_and : HInst< 26576(outs HvxQR:$Qd4), 26577(ins HvxQR:$Qs4, HvxQR:$Qt4), 26578"$Qd4 = and($Qs4,$Qt4)", 26579tc_db5555f3, TypeCVI_VA_DV>, Enc_134437, Requires<[UseHVXV60]> { 26580let Inst{7-2} = 0b000000; 26581let Inst{13-10} = 0b0000; 26582let Inst{21-16} = 0b000011; 26583let Inst{31-24} = 0b00011110; 26584let hasNewValue = 1; 26585let opNewValue = 0; 26586let DecoderNamespace = "EXT_mmvec"; 26587} 26588def V6_pred_and_n : HInst< 26589(outs HvxQR:$Qd4), 26590(ins HvxQR:$Qs4, HvxQR:$Qt4), 26591"$Qd4 = and($Qs4,!$Qt4)", 26592tc_db5555f3, TypeCVI_VA_DV>, Enc_134437, Requires<[UseHVXV60]> { 26593let Inst{7-2} = 0b000101; 26594let Inst{13-10} = 0b0000; 26595let Inst{21-16} = 0b000011; 26596let Inst{31-24} = 0b00011110; 26597let hasNewValue = 1; 26598let opNewValue = 0; 26599let DecoderNamespace = "EXT_mmvec"; 26600} 26601def V6_pred_not : HInst< 26602(outs HvxQR:$Qd4), 26603(ins HvxQR:$Qs4), 26604"$Qd4 = not($Qs4)", 26605tc_0ec46cf9, TypeCVI_VA>, Enc_bfbf03, Requires<[UseHVXV60]> { 26606let Inst{7-2} = 0b000010; 26607let Inst{13-10} = 0b0000; 26608let Inst{31-16} = 0b0001111000000011; 26609let hasNewValue = 1; 26610let opNewValue = 0; 26611let DecoderNamespace = "EXT_mmvec"; 26612} 26613def V6_pred_or : HInst< 26614(outs HvxQR:$Qd4), 26615(ins HvxQR:$Qs4, HvxQR:$Qt4), 26616"$Qd4 = or($Qs4,$Qt4)", 26617tc_db5555f3, TypeCVI_VA_DV>, Enc_134437, Requires<[UseHVXV60]> { 26618let Inst{7-2} = 0b000001; 26619let Inst{13-10} = 0b0000; 26620let Inst{21-16} = 0b000011; 26621let Inst{31-24} = 0b00011110; 26622let hasNewValue = 1; 26623let opNewValue = 0; 26624let DecoderNamespace = "EXT_mmvec"; 26625} 26626def V6_pred_or_n : HInst< 26627(outs HvxQR:$Qd4), 26628(ins HvxQR:$Qs4, HvxQR:$Qt4), 26629"$Qd4 = or($Qs4,!$Qt4)", 26630tc_db5555f3, TypeCVI_VA_DV>, Enc_134437, Requires<[UseHVXV60]> { 26631let Inst{7-2} = 0b000100; 26632let Inst{13-10} = 0b0000; 26633let Inst{21-16} = 0b000011; 26634let Inst{31-24} = 0b00011110; 26635let hasNewValue = 1; 26636let opNewValue = 0; 26637let DecoderNamespace = "EXT_mmvec"; 26638} 26639def V6_pred_scalar2 : HInst< 26640(outs HvxQR:$Qd4), 26641(ins IntRegs:$Rt32), 26642"$Qd4 = vsetq($Rt32)", 26643tc_5bf8afbb, TypeCVI_VP>, Enc_7222b7, Requires<[UseHVXV60]> { 26644let Inst{13-2} = 0b000000010001; 26645let Inst{31-21} = 0b00011001101; 26646let hasNewValue = 1; 26647let opNewValue = 0; 26648let DecoderNamespace = "EXT_mmvec"; 26649} 26650def V6_pred_scalar2v2 : HInst< 26651(outs HvxQR:$Qd4), 26652(ins IntRegs:$Rt32), 26653"$Qd4 = vsetq2($Rt32)", 26654tc_5bf8afbb, TypeCVI_VP>, Enc_7222b7, Requires<[UseHVXV62]> { 26655let Inst{13-2} = 0b000000010011; 26656let Inst{31-21} = 0b00011001101; 26657let hasNewValue = 1; 26658let opNewValue = 0; 26659let DecoderNamespace = "EXT_mmvec"; 26660} 26661def V6_pred_xor : HInst< 26662(outs HvxQR:$Qd4), 26663(ins HvxQR:$Qs4, HvxQR:$Qt4), 26664"$Qd4 = xor($Qs4,$Qt4)", 26665tc_db5555f3, TypeCVI_VA_DV>, Enc_134437, Requires<[UseHVXV60]> { 26666let Inst{7-2} = 0b000011; 26667let Inst{13-10} = 0b0000; 26668let Inst{21-16} = 0b000011; 26669let Inst{31-24} = 0b00011110; 26670let hasNewValue = 1; 26671let opNewValue = 0; 26672let DecoderNamespace = "EXT_mmvec"; 26673} 26674def V6_shuffeqh : HInst< 26675(outs HvxQR:$Qd4), 26676(ins HvxQR:$Qs4, HvxQR:$Qt4), 26677"$Qd4.b = vshuffe($Qs4.h,$Qt4.h)", 26678tc_db5555f3, TypeCVI_VA_DV>, Enc_134437, Requires<[UseHVXV62]> { 26679let Inst{7-2} = 0b000110; 26680let Inst{13-10} = 0b0000; 26681let Inst{21-16} = 0b000011; 26682let Inst{31-24} = 0b00011110; 26683let hasNewValue = 1; 26684let opNewValue = 0; 26685let DecoderNamespace = "EXT_mmvec"; 26686} 26687def V6_shuffeqw : HInst< 26688(outs HvxQR:$Qd4), 26689(ins HvxQR:$Qs4, HvxQR:$Qt4), 26690"$Qd4.h = vshuffe($Qs4.w,$Qt4.w)", 26691tc_db5555f3, TypeCVI_VA_DV>, Enc_134437, Requires<[UseHVXV62]> { 26692let Inst{7-2} = 0b000111; 26693let Inst{13-10} = 0b0000; 26694let Inst{21-16} = 0b000011; 26695let Inst{31-24} = 0b00011110; 26696let hasNewValue = 1; 26697let opNewValue = 0; 26698let DecoderNamespace = "EXT_mmvec"; 26699} 26700def V6_st0 : HInst< 26701(outs), 26702(ins IntRegs:$Rt32, HvxVR:$Vs32), 26703"vmem($Rt32) = $Vs32", 26704PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> { 26705let isPseudo = 1; 26706let isCodeGenOnly = 1; 26707let DecoderNamespace = "EXT_mmvec"; 26708} 26709def V6_stn0 : HInst< 26710(outs), 26711(ins IntRegs:$Rt32, HvxVR:$Os8), 26712"vmem($Rt32) = $Os8.new", 26713PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> { 26714let isPseudo = 1; 26715let isCodeGenOnly = 1; 26716let DecoderNamespace = "EXT_mmvec"; 26717let opNewValue = 1; 26718} 26719def V6_stnnt0 : HInst< 26720(outs), 26721(ins IntRegs:$Rt32, HvxVR:$Os8), 26722"vmem($Rt32):nt = $Os8.new", 26723PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> { 26724let isPseudo = 1; 26725let isCodeGenOnly = 1; 26726let DecoderNamespace = "EXT_mmvec"; 26727let opNewValue = 1; 26728} 26729def V6_stnp0 : HInst< 26730(outs), 26731(ins PredRegs:$Pv4, IntRegs:$Rt32, HvxVR:$Vs32), 26732"if (!$Pv4) vmem($Rt32) = $Vs32", 26733PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> { 26734let isPseudo = 1; 26735let isCodeGenOnly = 1; 26736let DecoderNamespace = "EXT_mmvec"; 26737} 26738def V6_stnpnt0 : HInst< 26739(outs), 26740(ins PredRegs:$Pv4, IntRegs:$Rt32, HvxVR:$Vs32), 26741"if (!$Pv4) vmem($Rt32):nt = $Vs32", 26742PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> { 26743let isPseudo = 1; 26744let isCodeGenOnly = 1; 26745let DecoderNamespace = "EXT_mmvec"; 26746} 26747def V6_stnq0 : HInst< 26748(outs), 26749(ins HvxQR:$Qv4, IntRegs:$Rt32, HvxVR:$Vs32), 26750"if (!$Qv4) vmem($Rt32) = $Vs32", 26751PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> { 26752let isPseudo = 1; 26753let isCodeGenOnly = 1; 26754let DecoderNamespace = "EXT_mmvec"; 26755} 26756def V6_stnqnt0 : HInst< 26757(outs), 26758(ins HvxQR:$Qv4, IntRegs:$Rt32, HvxVR:$Vs32), 26759"if (!$Qv4) vmem($Rt32):nt = $Vs32", 26760PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> { 26761let isPseudo = 1; 26762let isCodeGenOnly = 1; 26763let DecoderNamespace = "EXT_mmvec"; 26764} 26765def V6_stnt0 : HInst< 26766(outs), 26767(ins IntRegs:$Rt32, HvxVR:$Vs32), 26768"vmem($Rt32):nt = $Vs32", 26769PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> { 26770let isPseudo = 1; 26771let isCodeGenOnly = 1; 26772let DecoderNamespace = "EXT_mmvec"; 26773} 26774def V6_stp0 : HInst< 26775(outs), 26776(ins PredRegs:$Pv4, IntRegs:$Rt32, HvxVR:$Vs32), 26777"if ($Pv4) vmem($Rt32) = $Vs32", 26778PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> { 26779let isPseudo = 1; 26780let isCodeGenOnly = 1; 26781let DecoderNamespace = "EXT_mmvec"; 26782} 26783def V6_stpnt0 : HInst< 26784(outs), 26785(ins PredRegs:$Pv4, IntRegs:$Rt32, HvxVR:$Vs32), 26786"if ($Pv4) vmem($Rt32):nt = $Vs32", 26787PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> { 26788let isPseudo = 1; 26789let isCodeGenOnly = 1; 26790let DecoderNamespace = "EXT_mmvec"; 26791} 26792def V6_stq0 : HInst< 26793(outs), 26794(ins HvxQR:$Qv4, IntRegs:$Rt32, HvxVR:$Vs32), 26795"if ($Qv4) vmem($Rt32) = $Vs32", 26796PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> { 26797let isPseudo = 1; 26798let isCodeGenOnly = 1; 26799let DecoderNamespace = "EXT_mmvec"; 26800} 26801def V6_stqnt0 : HInst< 26802(outs), 26803(ins HvxQR:$Qv4, IntRegs:$Rt32, HvxVR:$Vs32), 26804"if ($Qv4) vmem($Rt32):nt = $Vs32", 26805PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> { 26806let isPseudo = 1; 26807let isCodeGenOnly = 1; 26808let DecoderNamespace = "EXT_mmvec"; 26809} 26810def V6_stu0 : HInst< 26811(outs), 26812(ins IntRegs:$Rt32, HvxVR:$Vs32), 26813"vmemu($Rt32) = $Vs32", 26814PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> { 26815let isPseudo = 1; 26816let isCodeGenOnly = 1; 26817let DecoderNamespace = "EXT_mmvec"; 26818} 26819def V6_stunp0 : HInst< 26820(outs), 26821(ins PredRegs:$Pv4, IntRegs:$Rt32, HvxVR:$Vs32), 26822"if (!$Pv4) vmemu($Rt32) = $Vs32", 26823PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> { 26824let isPseudo = 1; 26825let isCodeGenOnly = 1; 26826let DecoderNamespace = "EXT_mmvec"; 26827} 26828def V6_stup0 : HInst< 26829(outs), 26830(ins PredRegs:$Pv4, IntRegs:$Rt32, HvxVR:$Vs32), 26831"if ($Pv4) vmemu($Rt32) = $Vs32", 26832PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> { 26833let isPseudo = 1; 26834let isCodeGenOnly = 1; 26835let DecoderNamespace = "EXT_mmvec"; 26836} 26837def V6_vL32Ub_ai : HInst< 26838(outs HvxVR:$Vd32), 26839(ins IntRegs:$Rt32, s4_0Imm:$Ii), 26840"$Vd32 = vmemu($Rt32+#$Ii)", 26841tc_a7e6707d, TypeCVI_VM_VP_LDU>, Enc_f3f408, Requires<[UseHVXV60]> { 26842let Inst{7-5} = 0b111; 26843let Inst{12-11} = 0b00; 26844let Inst{31-21} = 0b00101000000; 26845let hasNewValue = 1; 26846let opNewValue = 0; 26847let addrMode = BaseImmOffset; 26848let accessSize = HVXVectorAccess; 26849let isCVLoad = 1; 26850let mayLoad = 1; 26851let isRestrictNoSlot1Store = 1; 26852let DecoderNamespace = "EXT_mmvec"; 26853} 26854def V6_vL32Ub_pi : HInst< 26855(outs HvxVR:$Vd32, IntRegs:$Rx32), 26856(ins IntRegs:$Rx32in, s3_0Imm:$Ii), 26857"$Vd32 = vmemu($Rx32++#$Ii)", 26858tc_3c56e5ce, TypeCVI_VM_VP_LDU>, Enc_a255dc, Requires<[UseHVXV60]> { 26859let Inst{7-5} = 0b111; 26860let Inst{13-11} = 0b000; 26861let Inst{31-21} = 0b00101001000; 26862let hasNewValue = 1; 26863let opNewValue = 0; 26864let addrMode = PostInc; 26865let accessSize = HVXVectorAccess; 26866let isCVLoad = 1; 26867let mayLoad = 1; 26868let isRestrictNoSlot1Store = 1; 26869let BaseOpcode = "V6_vL32b_pi"; 26870let DecoderNamespace = "EXT_mmvec"; 26871let Constraints = "$Rx32 = $Rx32in"; 26872} 26873def V6_vL32Ub_ppu : HInst< 26874(outs HvxVR:$Vd32, IntRegs:$Rx32), 26875(ins IntRegs:$Rx32in, ModRegs:$Mu2), 26876"$Vd32 = vmemu($Rx32++$Mu2)", 26877tc_3c56e5ce, TypeCVI_VM_VP_LDU>, Enc_2ebe3b, Requires<[UseHVXV60]> { 26878let Inst{12-5} = 0b00000111; 26879let Inst{31-21} = 0b00101011000; 26880let hasNewValue = 1; 26881let opNewValue = 0; 26882let addrMode = PostInc; 26883let accessSize = HVXVectorAccess; 26884let isCVLoad = 1; 26885let mayLoad = 1; 26886let isRestrictNoSlot1Store = 1; 26887let DecoderNamespace = "EXT_mmvec"; 26888let Constraints = "$Rx32 = $Rx32in"; 26889} 26890def V6_vL32b_ai : HInst< 26891(outs HvxVR:$Vd32), 26892(ins IntRegs:$Rt32, s4_0Imm:$Ii), 26893"$Vd32 = vmem($Rt32+#$Ii)", 26894tc_c0749f3c, TypeCVI_VM_LD>, Enc_f3f408, Requires<[UseHVXV60]>, PredRel { 26895let Inst{7-5} = 0b000; 26896let Inst{12-11} = 0b00; 26897let Inst{31-21} = 0b00101000000; 26898let hasNewValue = 1; 26899let opNewValue = 0; 26900let addrMode = BaseImmOffset; 26901let accessSize = HVXVectorAccess; 26902let isCVLoad = 1; 26903let mayLoad = 1; 26904let isRestrictNoSlot1Store = 1; 26905let BaseOpcode = "V6_vL32b_ai"; 26906let isCVLoadable = 1; 26907let isPredicable = 1; 26908let DecoderNamespace = "EXT_mmvec"; 26909} 26910def V6_vL32b_cur_ai : HInst< 26911(outs HvxVR:$Vd32), 26912(ins IntRegs:$Rt32, s4_0Imm:$Ii), 26913"$Vd32.cur = vmem($Rt32+#$Ii)", 26914tc_c0749f3c, TypeCVI_VM_LD>, Enc_f3f408, Requires<[UseHVXV60]>, PredRel { 26915let Inst{7-5} = 0b001; 26916let Inst{12-11} = 0b00; 26917let Inst{31-21} = 0b00101000000; 26918let hasNewValue = 1; 26919let opNewValue = 0; 26920let addrMode = BaseImmOffset; 26921let accessSize = HVXVectorAccess; 26922let isCVLoad = 1; 26923let CVINew = 1; 26924let mayLoad = 1; 26925let isRestrictNoSlot1Store = 1; 26926let BaseOpcode = "V6_vL32b_cur_ai"; 26927let isPredicable = 1; 26928let DecoderNamespace = "EXT_mmvec"; 26929} 26930def V6_vL32b_cur_npred_ai : HInst< 26931(outs HvxVR:$Vd32), 26932(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii), 26933"if (!$Pv4) $Vd32.cur = vmem($Rt32+#$Ii)", 26934tc_abe8c3b2, TypeCVI_VM_LD>, Enc_8d8a30, Requires<[UseHVXV62]>, PredRel { 26935let Inst{7-5} = 0b101; 26936let Inst{31-21} = 0b00101000100; 26937let isPredicated = 1; 26938let isPredicatedFalse = 1; 26939let hasNewValue = 1; 26940let opNewValue = 0; 26941let addrMode = BaseImmOffset; 26942let accessSize = HVXVectorAccess; 26943let isCVLoad = 1; 26944let CVINew = 1; 26945let mayLoad = 1; 26946let isRestrictNoSlot1Store = 1; 26947let BaseOpcode = "V6_vL32b_cur_ai"; 26948let DecoderNamespace = "EXT_mmvec"; 26949} 26950def V6_vL32b_cur_npred_pi : HInst< 26951(outs HvxVR:$Vd32, IntRegs:$Rx32), 26952(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii), 26953"if (!$Pv4) $Vd32.cur = vmem($Rx32++#$Ii)", 26954tc_453fe68d, TypeCVI_VM_LD>, Enc_58a8bf, Requires<[UseHVXV62]>, PredRel { 26955let Inst{7-5} = 0b101; 26956let Inst{13-13} = 0b0; 26957let Inst{31-21} = 0b00101001100; 26958let isPredicated = 1; 26959let isPredicatedFalse = 1; 26960let hasNewValue = 1; 26961let opNewValue = 0; 26962let addrMode = PostInc; 26963let accessSize = HVXVectorAccess; 26964let isCVLoad = 1; 26965let CVINew = 1; 26966let mayLoad = 1; 26967let isRestrictNoSlot1Store = 1; 26968let BaseOpcode = "V6_vL32b_cur_pi"; 26969let DecoderNamespace = "EXT_mmvec"; 26970let Constraints = "$Rx32 = $Rx32in"; 26971} 26972def V6_vL32b_cur_npred_ppu : HInst< 26973(outs HvxVR:$Vd32, IntRegs:$Rx32), 26974(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2), 26975"if (!$Pv4) $Vd32.cur = vmem($Rx32++$Mu2)", 26976tc_453fe68d, TypeCVI_VM_LD>, Enc_f8c1c4, Requires<[UseHVXV62]>, PredRel { 26977let Inst{10-5} = 0b000101; 26978let Inst{31-21} = 0b00101011100; 26979let isPredicated = 1; 26980let isPredicatedFalse = 1; 26981let hasNewValue = 1; 26982let opNewValue = 0; 26983let addrMode = PostInc; 26984let accessSize = HVXVectorAccess; 26985let isCVLoad = 1; 26986let CVINew = 1; 26987let mayLoad = 1; 26988let isRestrictNoSlot1Store = 1; 26989let BaseOpcode = "V6_vL32b_cur_ppu"; 26990let DecoderNamespace = "EXT_mmvec"; 26991let Constraints = "$Rx32 = $Rx32in"; 26992} 26993def V6_vL32b_cur_pi : HInst< 26994(outs HvxVR:$Vd32, IntRegs:$Rx32), 26995(ins IntRegs:$Rx32in, s3_0Imm:$Ii), 26996"$Vd32.cur = vmem($Rx32++#$Ii)", 26997tc_1ba8a0cd, TypeCVI_VM_LD>, Enc_a255dc, Requires<[UseHVXV60]>, PredRel { 26998let Inst{7-5} = 0b001; 26999let Inst{13-11} = 0b000; 27000let Inst{31-21} = 0b00101001000; 27001let hasNewValue = 1; 27002let opNewValue = 0; 27003let addrMode = PostInc; 27004let accessSize = HVXVectorAccess; 27005let isCVLoad = 1; 27006let CVINew = 1; 27007let mayLoad = 1; 27008let isRestrictNoSlot1Store = 1; 27009let BaseOpcode = "V6_vL32b_cur_pi"; 27010let isPredicable = 1; 27011let DecoderNamespace = "EXT_mmvec"; 27012let Constraints = "$Rx32 = $Rx32in"; 27013} 27014def V6_vL32b_cur_ppu : HInst< 27015(outs HvxVR:$Vd32, IntRegs:$Rx32), 27016(ins IntRegs:$Rx32in, ModRegs:$Mu2), 27017"$Vd32.cur = vmem($Rx32++$Mu2)", 27018tc_1ba8a0cd, TypeCVI_VM_LD>, Enc_2ebe3b, Requires<[UseHVXV60]>, PredRel { 27019let Inst{12-5} = 0b00000001; 27020let Inst{31-21} = 0b00101011000; 27021let hasNewValue = 1; 27022let opNewValue = 0; 27023let addrMode = PostInc; 27024let accessSize = HVXVectorAccess; 27025let isCVLoad = 1; 27026let CVINew = 1; 27027let mayLoad = 1; 27028let isRestrictNoSlot1Store = 1; 27029let BaseOpcode = "V6_vL32b_cur_ppu"; 27030let isPredicable = 1; 27031let DecoderNamespace = "EXT_mmvec"; 27032let Constraints = "$Rx32 = $Rx32in"; 27033} 27034def V6_vL32b_cur_pred_ai : HInst< 27035(outs HvxVR:$Vd32), 27036(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii), 27037"if ($Pv4) $Vd32.cur = vmem($Rt32+#$Ii)", 27038tc_abe8c3b2, TypeCVI_VM_LD>, Enc_8d8a30, Requires<[UseHVXV62]>, PredRel { 27039let Inst{7-5} = 0b100; 27040let Inst{31-21} = 0b00101000100; 27041let isPredicated = 1; 27042let hasNewValue = 1; 27043let opNewValue = 0; 27044let addrMode = BaseImmOffset; 27045let accessSize = HVXVectorAccess; 27046let isCVLoad = 1; 27047let CVINew = 1; 27048let mayLoad = 1; 27049let isRestrictNoSlot1Store = 1; 27050let BaseOpcode = "V6_vL32b_cur_ai"; 27051let DecoderNamespace = "EXT_mmvec"; 27052} 27053def V6_vL32b_cur_pred_pi : HInst< 27054(outs HvxVR:$Vd32, IntRegs:$Rx32), 27055(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii), 27056"if ($Pv4) $Vd32.cur = vmem($Rx32++#$Ii)", 27057tc_453fe68d, TypeCVI_VM_LD>, Enc_58a8bf, Requires<[UseHVXV62]>, PredRel { 27058let Inst{7-5} = 0b100; 27059let Inst{13-13} = 0b0; 27060let Inst{31-21} = 0b00101001100; 27061let isPredicated = 1; 27062let hasNewValue = 1; 27063let opNewValue = 0; 27064let addrMode = PostInc; 27065let accessSize = HVXVectorAccess; 27066let isCVLoad = 1; 27067let CVINew = 1; 27068let mayLoad = 1; 27069let isRestrictNoSlot1Store = 1; 27070let BaseOpcode = "V6_vL32b_cur_pi"; 27071let DecoderNamespace = "EXT_mmvec"; 27072let Constraints = "$Rx32 = $Rx32in"; 27073} 27074def V6_vL32b_cur_pred_ppu : HInst< 27075(outs HvxVR:$Vd32, IntRegs:$Rx32), 27076(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2), 27077"if ($Pv4) $Vd32.cur = vmem($Rx32++$Mu2)", 27078tc_453fe68d, TypeCVI_VM_LD>, Enc_f8c1c4, Requires<[UseHVXV62]>, PredRel { 27079let Inst{10-5} = 0b000100; 27080let Inst{31-21} = 0b00101011100; 27081let isPredicated = 1; 27082let hasNewValue = 1; 27083let opNewValue = 0; 27084let addrMode = PostInc; 27085let accessSize = HVXVectorAccess; 27086let isCVLoad = 1; 27087let CVINew = 1; 27088let mayLoad = 1; 27089let isRestrictNoSlot1Store = 1; 27090let BaseOpcode = "V6_vL32b_cur_ppu"; 27091let DecoderNamespace = "EXT_mmvec"; 27092let Constraints = "$Rx32 = $Rx32in"; 27093} 27094def V6_vL32b_npred_ai : HInst< 27095(outs HvxVR:$Vd32), 27096(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii), 27097"if (!$Pv4) $Vd32 = vmem($Rt32+#$Ii)", 27098tc_abe8c3b2, TypeCVI_VM_LD>, Enc_8d8a30, Requires<[UseHVXV62]>, PredRel { 27099let Inst{7-5} = 0b011; 27100let Inst{31-21} = 0b00101000100; 27101let isPredicated = 1; 27102let isPredicatedFalse = 1; 27103let hasNewValue = 1; 27104let opNewValue = 0; 27105let addrMode = BaseImmOffset; 27106let accessSize = HVXVectorAccess; 27107let isCVLoad = 1; 27108let mayLoad = 1; 27109let isRestrictNoSlot1Store = 1; 27110let BaseOpcode = "V6_vL32b_ai"; 27111let DecoderNamespace = "EXT_mmvec"; 27112} 27113def V6_vL32b_npred_pi : HInst< 27114(outs HvxVR:$Vd32, IntRegs:$Rx32), 27115(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii), 27116"if (!$Pv4) $Vd32 = vmem($Rx32++#$Ii)", 27117tc_453fe68d, TypeCVI_VM_LD>, Enc_58a8bf, Requires<[UseHVXV62]>, PredRel { 27118let Inst{7-5} = 0b011; 27119let Inst{13-13} = 0b0; 27120let Inst{31-21} = 0b00101001100; 27121let isPredicated = 1; 27122let isPredicatedFalse = 1; 27123let hasNewValue = 1; 27124let opNewValue = 0; 27125let addrMode = PostInc; 27126let accessSize = HVXVectorAccess; 27127let isCVLoad = 1; 27128let mayLoad = 1; 27129let isRestrictNoSlot1Store = 1; 27130let BaseOpcode = "V6_vL32b_pi"; 27131let DecoderNamespace = "EXT_mmvec"; 27132let Constraints = "$Rx32 = $Rx32in"; 27133} 27134def V6_vL32b_npred_ppu : HInst< 27135(outs HvxVR:$Vd32, IntRegs:$Rx32), 27136(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2), 27137"if (!$Pv4) $Vd32 = vmem($Rx32++$Mu2)", 27138tc_453fe68d, TypeCVI_VM_LD>, Enc_f8c1c4, Requires<[UseHVXV62]>, PredRel { 27139let Inst{10-5} = 0b000011; 27140let Inst{31-21} = 0b00101011100; 27141let isPredicated = 1; 27142let isPredicatedFalse = 1; 27143let hasNewValue = 1; 27144let opNewValue = 0; 27145let addrMode = PostInc; 27146let accessSize = HVXVectorAccess; 27147let isCVLoad = 1; 27148let mayLoad = 1; 27149let isRestrictNoSlot1Store = 1; 27150let BaseOpcode = "V6_vL32b_ppu"; 27151let DecoderNamespace = "EXT_mmvec"; 27152let Constraints = "$Rx32 = $Rx32in"; 27153} 27154def V6_vL32b_nt_ai : HInst< 27155(outs HvxVR:$Vd32), 27156(ins IntRegs:$Rt32, s4_0Imm:$Ii), 27157"$Vd32 = vmem($Rt32+#$Ii):nt", 27158tc_c0749f3c, TypeCVI_VM_LD>, Enc_f3f408, Requires<[UseHVXV60]>, PredRel { 27159let Inst{7-5} = 0b000; 27160let Inst{12-11} = 0b00; 27161let Inst{31-21} = 0b00101000010; 27162let hasNewValue = 1; 27163let opNewValue = 0; 27164let addrMode = BaseImmOffset; 27165let accessSize = HVXVectorAccess; 27166let isCVLoad = 1; 27167let mayLoad = 1; 27168let isNonTemporal = 1; 27169let isRestrictNoSlot1Store = 1; 27170let BaseOpcode = "V6_vL32b_nt_ai"; 27171let isCVLoadable = 1; 27172let isPredicable = 1; 27173let DecoderNamespace = "EXT_mmvec"; 27174} 27175def V6_vL32b_nt_cur_ai : HInst< 27176(outs HvxVR:$Vd32), 27177(ins IntRegs:$Rt32, s4_0Imm:$Ii), 27178"$Vd32.cur = vmem($Rt32+#$Ii):nt", 27179tc_c0749f3c, TypeCVI_VM_LD>, Enc_f3f408, Requires<[UseHVXV60]>, PredRel { 27180let Inst{7-5} = 0b001; 27181let Inst{12-11} = 0b00; 27182let Inst{31-21} = 0b00101000010; 27183let hasNewValue = 1; 27184let opNewValue = 0; 27185let addrMode = BaseImmOffset; 27186let accessSize = HVXVectorAccess; 27187let isCVLoad = 1; 27188let CVINew = 1; 27189let mayLoad = 1; 27190let isNonTemporal = 1; 27191let isRestrictNoSlot1Store = 1; 27192let BaseOpcode = "V6_vL32b_nt_cur_ai"; 27193let isPredicable = 1; 27194let DecoderNamespace = "EXT_mmvec"; 27195} 27196def V6_vL32b_nt_cur_npred_ai : HInst< 27197(outs HvxVR:$Vd32), 27198(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii), 27199"if (!$Pv4) $Vd32.cur = vmem($Rt32+#$Ii):nt", 27200tc_abe8c3b2, TypeCVI_VM_LD>, Enc_8d8a30, Requires<[UseHVXV62]>, PredRel { 27201let Inst{7-5} = 0b101; 27202let Inst{31-21} = 0b00101000110; 27203let isPredicated = 1; 27204let isPredicatedFalse = 1; 27205let hasNewValue = 1; 27206let opNewValue = 0; 27207let addrMode = BaseImmOffset; 27208let accessSize = HVXVectorAccess; 27209let isCVLoad = 1; 27210let CVINew = 1; 27211let mayLoad = 1; 27212let isNonTemporal = 1; 27213let isRestrictNoSlot1Store = 1; 27214let BaseOpcode = "V6_vL32b_nt_cur_ai"; 27215let DecoderNamespace = "EXT_mmvec"; 27216} 27217def V6_vL32b_nt_cur_npred_pi : HInst< 27218(outs HvxVR:$Vd32, IntRegs:$Rx32), 27219(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii), 27220"if (!$Pv4) $Vd32.cur = vmem($Rx32++#$Ii):nt", 27221tc_453fe68d, TypeCVI_VM_LD>, Enc_58a8bf, Requires<[UseHVXV62]>, PredRel { 27222let Inst{7-5} = 0b101; 27223let Inst{13-13} = 0b0; 27224let Inst{31-21} = 0b00101001110; 27225let isPredicated = 1; 27226let isPredicatedFalse = 1; 27227let hasNewValue = 1; 27228let opNewValue = 0; 27229let addrMode = PostInc; 27230let accessSize = HVXVectorAccess; 27231let isCVLoad = 1; 27232let CVINew = 1; 27233let mayLoad = 1; 27234let isNonTemporal = 1; 27235let isRestrictNoSlot1Store = 1; 27236let BaseOpcode = "V6_vL32b_nt_cur_pi"; 27237let DecoderNamespace = "EXT_mmvec"; 27238let Constraints = "$Rx32 = $Rx32in"; 27239} 27240def V6_vL32b_nt_cur_npred_ppu : HInst< 27241(outs HvxVR:$Vd32, IntRegs:$Rx32), 27242(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2), 27243"if (!$Pv4) $Vd32.cur = vmem($Rx32++$Mu2):nt", 27244tc_453fe68d, TypeCVI_VM_LD>, Enc_f8c1c4, Requires<[UseHVXV62]>, PredRel { 27245let Inst{10-5} = 0b000101; 27246let Inst{31-21} = 0b00101011110; 27247let isPredicated = 1; 27248let isPredicatedFalse = 1; 27249let hasNewValue = 1; 27250let opNewValue = 0; 27251let addrMode = PostInc; 27252let accessSize = HVXVectorAccess; 27253let isCVLoad = 1; 27254let CVINew = 1; 27255let mayLoad = 1; 27256let isNonTemporal = 1; 27257let isRestrictNoSlot1Store = 1; 27258let BaseOpcode = "V6_vL32b_nt_cur_ppu"; 27259let DecoderNamespace = "EXT_mmvec"; 27260let Constraints = "$Rx32 = $Rx32in"; 27261} 27262def V6_vL32b_nt_cur_pi : HInst< 27263(outs HvxVR:$Vd32, IntRegs:$Rx32), 27264(ins IntRegs:$Rx32in, s3_0Imm:$Ii), 27265"$Vd32.cur = vmem($Rx32++#$Ii):nt", 27266tc_1ba8a0cd, TypeCVI_VM_LD>, Enc_a255dc, Requires<[UseHVXV60]>, PredRel { 27267let Inst{7-5} = 0b001; 27268let Inst{13-11} = 0b000; 27269let Inst{31-21} = 0b00101001010; 27270let hasNewValue = 1; 27271let opNewValue = 0; 27272let addrMode = PostInc; 27273let accessSize = HVXVectorAccess; 27274let isCVLoad = 1; 27275let CVINew = 1; 27276let mayLoad = 1; 27277let isNonTemporal = 1; 27278let isRestrictNoSlot1Store = 1; 27279let BaseOpcode = "V6_vL32b_nt_cur_pi"; 27280let isPredicable = 1; 27281let DecoderNamespace = "EXT_mmvec"; 27282let Constraints = "$Rx32 = $Rx32in"; 27283} 27284def V6_vL32b_nt_cur_ppu : HInst< 27285(outs HvxVR:$Vd32, IntRegs:$Rx32), 27286(ins IntRegs:$Rx32in, ModRegs:$Mu2), 27287"$Vd32.cur = vmem($Rx32++$Mu2):nt", 27288tc_1ba8a0cd, TypeCVI_VM_LD>, Enc_2ebe3b, Requires<[UseHVXV60]>, PredRel { 27289let Inst{12-5} = 0b00000001; 27290let Inst{31-21} = 0b00101011010; 27291let hasNewValue = 1; 27292let opNewValue = 0; 27293let addrMode = PostInc; 27294let accessSize = HVXVectorAccess; 27295let isCVLoad = 1; 27296let CVINew = 1; 27297let mayLoad = 1; 27298let isNonTemporal = 1; 27299let isRestrictNoSlot1Store = 1; 27300let BaseOpcode = "V6_vL32b_nt_cur_ppu"; 27301let isPredicable = 1; 27302let DecoderNamespace = "EXT_mmvec"; 27303let Constraints = "$Rx32 = $Rx32in"; 27304} 27305def V6_vL32b_nt_cur_pred_ai : HInst< 27306(outs HvxVR:$Vd32), 27307(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii), 27308"if ($Pv4) $Vd32.cur = vmem($Rt32+#$Ii):nt", 27309tc_abe8c3b2, TypeCVI_VM_LD>, Enc_8d8a30, Requires<[UseHVXV62]>, PredRel { 27310let Inst{7-5} = 0b100; 27311let Inst{31-21} = 0b00101000110; 27312let isPredicated = 1; 27313let hasNewValue = 1; 27314let opNewValue = 0; 27315let addrMode = BaseImmOffset; 27316let accessSize = HVXVectorAccess; 27317let isCVLoad = 1; 27318let CVINew = 1; 27319let mayLoad = 1; 27320let isNonTemporal = 1; 27321let isRestrictNoSlot1Store = 1; 27322let BaseOpcode = "V6_vL32b_nt_cur_ai"; 27323let DecoderNamespace = "EXT_mmvec"; 27324} 27325def V6_vL32b_nt_cur_pred_pi : HInst< 27326(outs HvxVR:$Vd32, IntRegs:$Rx32), 27327(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii), 27328"if ($Pv4) $Vd32.cur = vmem($Rx32++#$Ii):nt", 27329tc_453fe68d, TypeCVI_VM_LD>, Enc_58a8bf, Requires<[UseHVXV62]>, PredRel { 27330let Inst{7-5} = 0b100; 27331let Inst{13-13} = 0b0; 27332let Inst{31-21} = 0b00101001110; 27333let isPredicated = 1; 27334let hasNewValue = 1; 27335let opNewValue = 0; 27336let addrMode = PostInc; 27337let accessSize = HVXVectorAccess; 27338let isCVLoad = 1; 27339let CVINew = 1; 27340let mayLoad = 1; 27341let isNonTemporal = 1; 27342let isRestrictNoSlot1Store = 1; 27343let BaseOpcode = "V6_vL32b_nt_cur_pi"; 27344let DecoderNamespace = "EXT_mmvec"; 27345let Constraints = "$Rx32 = $Rx32in"; 27346} 27347def V6_vL32b_nt_cur_pred_ppu : HInst< 27348(outs HvxVR:$Vd32, IntRegs:$Rx32), 27349(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2), 27350"if ($Pv4) $Vd32.cur = vmem($Rx32++$Mu2):nt", 27351tc_453fe68d, TypeCVI_VM_LD>, Enc_f8c1c4, Requires<[UseHVXV62]>, PredRel { 27352let Inst{10-5} = 0b000100; 27353let Inst{31-21} = 0b00101011110; 27354let isPredicated = 1; 27355let hasNewValue = 1; 27356let opNewValue = 0; 27357let addrMode = PostInc; 27358let accessSize = HVXVectorAccess; 27359let isCVLoad = 1; 27360let CVINew = 1; 27361let mayLoad = 1; 27362let isNonTemporal = 1; 27363let isRestrictNoSlot1Store = 1; 27364let BaseOpcode = "V6_vL32b_nt_cur_ppu"; 27365let DecoderNamespace = "EXT_mmvec"; 27366let Constraints = "$Rx32 = $Rx32in"; 27367} 27368def V6_vL32b_nt_npred_ai : HInst< 27369(outs HvxVR:$Vd32), 27370(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii), 27371"if (!$Pv4) $Vd32 = vmem($Rt32+#$Ii):nt", 27372tc_abe8c3b2, TypeCVI_VM_LD>, Enc_8d8a30, Requires<[UseHVXV62]>, PredRel { 27373let Inst{7-5} = 0b011; 27374let Inst{31-21} = 0b00101000110; 27375let isPredicated = 1; 27376let isPredicatedFalse = 1; 27377let hasNewValue = 1; 27378let opNewValue = 0; 27379let addrMode = BaseImmOffset; 27380let accessSize = HVXVectorAccess; 27381let isCVLoad = 1; 27382let mayLoad = 1; 27383let isNonTemporal = 1; 27384let isRestrictNoSlot1Store = 1; 27385let BaseOpcode = "V6_vL32b_nt_ai"; 27386let DecoderNamespace = "EXT_mmvec"; 27387} 27388def V6_vL32b_nt_npred_pi : HInst< 27389(outs HvxVR:$Vd32, IntRegs:$Rx32), 27390(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii), 27391"if (!$Pv4) $Vd32 = vmem($Rx32++#$Ii):nt", 27392tc_453fe68d, TypeCVI_VM_LD>, Enc_58a8bf, Requires<[UseHVXV62]>, PredRel { 27393let Inst{7-5} = 0b011; 27394let Inst{13-13} = 0b0; 27395let Inst{31-21} = 0b00101001110; 27396let isPredicated = 1; 27397let isPredicatedFalse = 1; 27398let hasNewValue = 1; 27399let opNewValue = 0; 27400let addrMode = PostInc; 27401let accessSize = HVXVectorAccess; 27402let isCVLoad = 1; 27403let mayLoad = 1; 27404let isNonTemporal = 1; 27405let isRestrictNoSlot1Store = 1; 27406let BaseOpcode = "V6_vL32b_nt_pi"; 27407let DecoderNamespace = "EXT_mmvec"; 27408let Constraints = "$Rx32 = $Rx32in"; 27409} 27410def V6_vL32b_nt_npred_ppu : HInst< 27411(outs HvxVR:$Vd32, IntRegs:$Rx32), 27412(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2), 27413"if (!$Pv4) $Vd32 = vmem($Rx32++$Mu2):nt", 27414tc_453fe68d, TypeCVI_VM_LD>, Enc_f8c1c4, Requires<[UseHVXV62]>, PredRel { 27415let Inst{10-5} = 0b000011; 27416let Inst{31-21} = 0b00101011110; 27417let isPredicated = 1; 27418let isPredicatedFalse = 1; 27419let hasNewValue = 1; 27420let opNewValue = 0; 27421let addrMode = PostInc; 27422let accessSize = HVXVectorAccess; 27423let isCVLoad = 1; 27424let mayLoad = 1; 27425let isNonTemporal = 1; 27426let isRestrictNoSlot1Store = 1; 27427let BaseOpcode = "V6_vL32b_nt_ppu"; 27428let DecoderNamespace = "EXT_mmvec"; 27429let Constraints = "$Rx32 = $Rx32in"; 27430} 27431def V6_vL32b_nt_pi : HInst< 27432(outs HvxVR:$Vd32, IntRegs:$Rx32), 27433(ins IntRegs:$Rx32in, s3_0Imm:$Ii), 27434"$Vd32 = vmem($Rx32++#$Ii):nt", 27435tc_1ba8a0cd, TypeCVI_VM_LD>, Enc_a255dc, Requires<[UseHVXV60]>, PredRel { 27436let Inst{7-5} = 0b000; 27437let Inst{13-11} = 0b000; 27438let Inst{31-21} = 0b00101001010; 27439let hasNewValue = 1; 27440let opNewValue = 0; 27441let addrMode = PostInc; 27442let accessSize = HVXVectorAccess; 27443let isCVLoad = 1; 27444let mayLoad = 1; 27445let isNonTemporal = 1; 27446let isRestrictNoSlot1Store = 1; 27447let BaseOpcode = "V6_vL32b_nt_pi"; 27448let isCVLoadable = 1; 27449let isPredicable = 1; 27450let DecoderNamespace = "EXT_mmvec"; 27451let Constraints = "$Rx32 = $Rx32in"; 27452} 27453def V6_vL32b_nt_ppu : HInst< 27454(outs HvxVR:$Vd32, IntRegs:$Rx32), 27455(ins IntRegs:$Rx32in, ModRegs:$Mu2), 27456"$Vd32 = vmem($Rx32++$Mu2):nt", 27457tc_1ba8a0cd, TypeCVI_VM_LD>, Enc_2ebe3b, Requires<[UseHVXV60]>, PredRel { 27458let Inst{12-5} = 0b00000000; 27459let Inst{31-21} = 0b00101011010; 27460let hasNewValue = 1; 27461let opNewValue = 0; 27462let addrMode = PostInc; 27463let accessSize = HVXVectorAccess; 27464let isCVLoad = 1; 27465let mayLoad = 1; 27466let isNonTemporal = 1; 27467let isRestrictNoSlot1Store = 1; 27468let BaseOpcode = "V6_vL32b_nt_ppu"; 27469let isCVLoadable = 1; 27470let isPredicable = 1; 27471let DecoderNamespace = "EXT_mmvec"; 27472let Constraints = "$Rx32 = $Rx32in"; 27473} 27474def V6_vL32b_nt_pred_ai : HInst< 27475(outs HvxVR:$Vd32), 27476(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii), 27477"if ($Pv4) $Vd32 = vmem($Rt32+#$Ii):nt", 27478tc_abe8c3b2, TypeCVI_VM_LD>, Enc_8d8a30, Requires<[UseHVXV62]>, PredRel { 27479let Inst{7-5} = 0b010; 27480let Inst{31-21} = 0b00101000110; 27481let isPredicated = 1; 27482let hasNewValue = 1; 27483let opNewValue = 0; 27484let addrMode = BaseImmOffset; 27485let accessSize = HVXVectorAccess; 27486let isCVLoad = 1; 27487let mayLoad = 1; 27488let isNonTemporal = 1; 27489let isRestrictNoSlot1Store = 1; 27490let BaseOpcode = "V6_vL32b_nt_ai"; 27491let DecoderNamespace = "EXT_mmvec"; 27492} 27493def V6_vL32b_nt_pred_pi : HInst< 27494(outs HvxVR:$Vd32, IntRegs:$Rx32), 27495(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii), 27496"if ($Pv4) $Vd32 = vmem($Rx32++#$Ii):nt", 27497tc_453fe68d, TypeCVI_VM_LD>, Enc_58a8bf, Requires<[UseHVXV62]>, PredRel { 27498let Inst{7-5} = 0b010; 27499let Inst{13-13} = 0b0; 27500let Inst{31-21} = 0b00101001110; 27501let isPredicated = 1; 27502let hasNewValue = 1; 27503let opNewValue = 0; 27504let addrMode = PostInc; 27505let accessSize = HVXVectorAccess; 27506let isCVLoad = 1; 27507let mayLoad = 1; 27508let isNonTemporal = 1; 27509let isRestrictNoSlot1Store = 1; 27510let BaseOpcode = "V6_vL32b_nt_pi"; 27511let DecoderNamespace = "EXT_mmvec"; 27512let Constraints = "$Rx32 = $Rx32in"; 27513} 27514def V6_vL32b_nt_pred_ppu : HInst< 27515(outs HvxVR:$Vd32, IntRegs:$Rx32), 27516(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2), 27517"if ($Pv4) $Vd32 = vmem($Rx32++$Mu2):nt", 27518tc_453fe68d, TypeCVI_VM_LD>, Enc_f8c1c4, Requires<[UseHVXV62]>, PredRel { 27519let Inst{10-5} = 0b000010; 27520let Inst{31-21} = 0b00101011110; 27521let isPredicated = 1; 27522let hasNewValue = 1; 27523let opNewValue = 0; 27524let addrMode = PostInc; 27525let accessSize = HVXVectorAccess; 27526let isCVLoad = 1; 27527let mayLoad = 1; 27528let isNonTemporal = 1; 27529let isRestrictNoSlot1Store = 1; 27530let BaseOpcode = "V6_vL32b_nt_ppu"; 27531let DecoderNamespace = "EXT_mmvec"; 27532let Constraints = "$Rx32 = $Rx32in"; 27533} 27534def V6_vL32b_nt_tmp_ai : HInst< 27535(outs HvxVR:$Vd32), 27536(ins IntRegs:$Rt32, s4_0Imm:$Ii), 27537"$Vd32.tmp = vmem($Rt32+#$Ii):nt", 27538tc_52447ecc, TypeCVI_VM_TMP_LD>, Enc_f3f408, Requires<[UseHVXV60]>, PredRel { 27539let Inst{7-5} = 0b010; 27540let Inst{12-11} = 0b00; 27541let Inst{31-21} = 0b00101000010; 27542let hasNewValue = 1; 27543let opNewValue = 0; 27544let addrMode = BaseImmOffset; 27545let accessSize = HVXVectorAccess; 27546let isCVLoad = 1; 27547let mayLoad = 1; 27548let isNonTemporal = 1; 27549let isRestrictNoSlot1Store = 1; 27550let BaseOpcode = "V6_vL32b_nt_tmp_ai"; 27551let isPredicable = 1; 27552let DecoderNamespace = "EXT_mmvec"; 27553} 27554def V6_vL32b_nt_tmp_npred_ai : HInst< 27555(outs HvxVR:$Vd32), 27556(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii), 27557"if (!$Pv4) $Vd32.tmp = vmem($Rt32+#$Ii):nt", 27558tc_3904b926, TypeCVI_VM_TMP_LD>, Enc_8d8a30, Requires<[UseHVXV62]>, PredRel { 27559let Inst{7-5} = 0b111; 27560let Inst{31-21} = 0b00101000110; 27561let isPredicated = 1; 27562let isPredicatedFalse = 1; 27563let hasNewValue = 1; 27564let opNewValue = 0; 27565let addrMode = BaseImmOffset; 27566let accessSize = HVXVectorAccess; 27567let isCVLoad = 1; 27568let mayLoad = 1; 27569let isNonTemporal = 1; 27570let isRestrictNoSlot1Store = 1; 27571let BaseOpcode = "V6_vL32b_nt_tmp_ai"; 27572let DecoderNamespace = "EXT_mmvec"; 27573} 27574def V6_vL32b_nt_tmp_npred_pi : HInst< 27575(outs HvxVR:$Vd32, IntRegs:$Rx32), 27576(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii), 27577"if (!$Pv4) $Vd32.tmp = vmem($Rx32++#$Ii):nt", 27578tc_b9db8205, TypeCVI_VM_TMP_LD>, Enc_58a8bf, Requires<[UseHVXV62]>, PredRel { 27579let Inst{7-5} = 0b111; 27580let Inst{13-13} = 0b0; 27581let Inst{31-21} = 0b00101001110; 27582let isPredicated = 1; 27583let isPredicatedFalse = 1; 27584let hasNewValue = 1; 27585let opNewValue = 0; 27586let addrMode = PostInc; 27587let accessSize = HVXVectorAccess; 27588let isCVLoad = 1; 27589let mayLoad = 1; 27590let isNonTemporal = 1; 27591let isRestrictNoSlot1Store = 1; 27592let BaseOpcode = "V6_vL32b_nt_tmp_pi"; 27593let DecoderNamespace = "EXT_mmvec"; 27594let Constraints = "$Rx32 = $Rx32in"; 27595} 27596def V6_vL32b_nt_tmp_npred_ppu : HInst< 27597(outs HvxVR:$Vd32, IntRegs:$Rx32), 27598(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2), 27599"if (!$Pv4) $Vd32.tmp = vmem($Rx32++$Mu2):nt", 27600tc_b9db8205, TypeCVI_VM_TMP_LD>, Enc_f8c1c4, Requires<[UseHVXV62]>, PredRel { 27601let Inst{10-5} = 0b000111; 27602let Inst{31-21} = 0b00101011110; 27603let isPredicated = 1; 27604let isPredicatedFalse = 1; 27605let hasNewValue = 1; 27606let opNewValue = 0; 27607let addrMode = PostInc; 27608let accessSize = HVXVectorAccess; 27609let isCVLoad = 1; 27610let mayLoad = 1; 27611let isNonTemporal = 1; 27612let isRestrictNoSlot1Store = 1; 27613let BaseOpcode = "V6_vL32b_nt_tmp_ppu"; 27614let DecoderNamespace = "EXT_mmvec"; 27615let Constraints = "$Rx32 = $Rx32in"; 27616} 27617def V6_vL32b_nt_tmp_pi : HInst< 27618(outs HvxVR:$Vd32, IntRegs:$Rx32), 27619(ins IntRegs:$Rx32in, s3_0Imm:$Ii), 27620"$Vd32.tmp = vmem($Rx32++#$Ii):nt", 27621tc_663c80a7, TypeCVI_VM_TMP_LD>, Enc_a255dc, Requires<[UseHVXV60]>, PredRel { 27622let Inst{7-5} = 0b010; 27623let Inst{13-11} = 0b000; 27624let Inst{31-21} = 0b00101001010; 27625let hasNewValue = 1; 27626let opNewValue = 0; 27627let addrMode = PostInc; 27628let accessSize = HVXVectorAccess; 27629let isCVLoad = 1; 27630let mayLoad = 1; 27631let isNonTemporal = 1; 27632let isRestrictNoSlot1Store = 1; 27633let BaseOpcode = "V6_vL32b_nt_tmp_pi"; 27634let isPredicable = 1; 27635let DecoderNamespace = "EXT_mmvec"; 27636let Constraints = "$Rx32 = $Rx32in"; 27637} 27638def V6_vL32b_nt_tmp_ppu : HInst< 27639(outs HvxVR:$Vd32, IntRegs:$Rx32), 27640(ins IntRegs:$Rx32in, ModRegs:$Mu2), 27641"$Vd32.tmp = vmem($Rx32++$Mu2):nt", 27642tc_663c80a7, TypeCVI_VM_TMP_LD>, Enc_2ebe3b, Requires<[UseHVXV60]>, PredRel { 27643let Inst{12-5} = 0b00000010; 27644let Inst{31-21} = 0b00101011010; 27645let hasNewValue = 1; 27646let opNewValue = 0; 27647let addrMode = PostInc; 27648let accessSize = HVXVectorAccess; 27649let isCVLoad = 1; 27650let mayLoad = 1; 27651let isNonTemporal = 1; 27652let isRestrictNoSlot1Store = 1; 27653let BaseOpcode = "V6_vL32b_nt_tmp_ppu"; 27654let isPredicable = 1; 27655let DecoderNamespace = "EXT_mmvec"; 27656let Constraints = "$Rx32 = $Rx32in"; 27657} 27658def V6_vL32b_nt_tmp_pred_ai : HInst< 27659(outs HvxVR:$Vd32), 27660(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii), 27661"if ($Pv4) $Vd32.tmp = vmem($Rt32+#$Ii):nt", 27662tc_3904b926, TypeCVI_VM_TMP_LD>, Enc_8d8a30, Requires<[UseHVXV62]>, PredRel { 27663let Inst{7-5} = 0b110; 27664let Inst{31-21} = 0b00101000110; 27665let isPredicated = 1; 27666let hasNewValue = 1; 27667let opNewValue = 0; 27668let addrMode = BaseImmOffset; 27669let accessSize = HVXVectorAccess; 27670let isCVLoad = 1; 27671let mayLoad = 1; 27672let isNonTemporal = 1; 27673let isRestrictNoSlot1Store = 1; 27674let BaseOpcode = "V6_vL32b_nt_tmp_ai"; 27675let DecoderNamespace = "EXT_mmvec"; 27676} 27677def V6_vL32b_nt_tmp_pred_pi : HInst< 27678(outs HvxVR:$Vd32, IntRegs:$Rx32), 27679(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii), 27680"if ($Pv4) $Vd32.tmp = vmem($Rx32++#$Ii):nt", 27681tc_b9db8205, TypeCVI_VM_TMP_LD>, Enc_58a8bf, Requires<[UseHVXV62]>, PredRel { 27682let Inst{7-5} = 0b110; 27683let Inst{13-13} = 0b0; 27684let Inst{31-21} = 0b00101001110; 27685let isPredicated = 1; 27686let hasNewValue = 1; 27687let opNewValue = 0; 27688let addrMode = PostInc; 27689let accessSize = HVXVectorAccess; 27690let isCVLoad = 1; 27691let mayLoad = 1; 27692let isNonTemporal = 1; 27693let isRestrictNoSlot1Store = 1; 27694let BaseOpcode = "V6_vL32b_nt_tmp_pi"; 27695let DecoderNamespace = "EXT_mmvec"; 27696let Constraints = "$Rx32 = $Rx32in"; 27697} 27698def V6_vL32b_nt_tmp_pred_ppu : HInst< 27699(outs HvxVR:$Vd32, IntRegs:$Rx32), 27700(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2), 27701"if ($Pv4) $Vd32.tmp = vmem($Rx32++$Mu2):nt", 27702tc_b9db8205, TypeCVI_VM_TMP_LD>, Enc_f8c1c4, Requires<[UseHVXV62]>, PredRel { 27703let Inst{10-5} = 0b000110; 27704let Inst{31-21} = 0b00101011110; 27705let isPredicated = 1; 27706let hasNewValue = 1; 27707let opNewValue = 0; 27708let addrMode = PostInc; 27709let accessSize = HVXVectorAccess; 27710let isCVLoad = 1; 27711let mayLoad = 1; 27712let isNonTemporal = 1; 27713let isRestrictNoSlot1Store = 1; 27714let BaseOpcode = "V6_vL32b_nt_tmp_ppu"; 27715let DecoderNamespace = "EXT_mmvec"; 27716let Constraints = "$Rx32 = $Rx32in"; 27717} 27718def V6_vL32b_pi : HInst< 27719(outs HvxVR:$Vd32, IntRegs:$Rx32), 27720(ins IntRegs:$Rx32in, s3_0Imm:$Ii), 27721"$Vd32 = vmem($Rx32++#$Ii)", 27722tc_1ba8a0cd, TypeCVI_VM_LD>, Enc_a255dc, Requires<[UseHVXV60]>, PredRel { 27723let Inst{7-5} = 0b000; 27724let Inst{13-11} = 0b000; 27725let Inst{31-21} = 0b00101001000; 27726let hasNewValue = 1; 27727let opNewValue = 0; 27728let addrMode = PostInc; 27729let accessSize = HVXVectorAccess; 27730let isCVLoad = 1; 27731let mayLoad = 1; 27732let isRestrictNoSlot1Store = 1; 27733let BaseOpcode = "V6_vL32b_pi"; 27734let isCVLoadable = 1; 27735let isPredicable = 1; 27736let DecoderNamespace = "EXT_mmvec"; 27737let Constraints = "$Rx32 = $Rx32in"; 27738} 27739def V6_vL32b_ppu : HInst< 27740(outs HvxVR:$Vd32, IntRegs:$Rx32), 27741(ins IntRegs:$Rx32in, ModRegs:$Mu2), 27742"$Vd32 = vmem($Rx32++$Mu2)", 27743tc_1ba8a0cd, TypeCVI_VM_LD>, Enc_2ebe3b, Requires<[UseHVXV60]>, PredRel { 27744let Inst{12-5} = 0b00000000; 27745let Inst{31-21} = 0b00101011000; 27746let hasNewValue = 1; 27747let opNewValue = 0; 27748let addrMode = PostInc; 27749let accessSize = HVXVectorAccess; 27750let isCVLoad = 1; 27751let mayLoad = 1; 27752let isRestrictNoSlot1Store = 1; 27753let BaseOpcode = "V6_vL32b_ppu"; 27754let isCVLoadable = 1; 27755let isPredicable = 1; 27756let DecoderNamespace = "EXT_mmvec"; 27757let Constraints = "$Rx32 = $Rx32in"; 27758} 27759def V6_vL32b_pred_ai : HInst< 27760(outs HvxVR:$Vd32), 27761(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii), 27762"if ($Pv4) $Vd32 = vmem($Rt32+#$Ii)", 27763tc_abe8c3b2, TypeCVI_VM_LD>, Enc_8d8a30, Requires<[UseHVXV62]>, PredRel { 27764let Inst{7-5} = 0b010; 27765let Inst{31-21} = 0b00101000100; 27766let isPredicated = 1; 27767let hasNewValue = 1; 27768let opNewValue = 0; 27769let addrMode = BaseImmOffset; 27770let accessSize = HVXVectorAccess; 27771let isCVLoad = 1; 27772let mayLoad = 1; 27773let isRestrictNoSlot1Store = 1; 27774let BaseOpcode = "V6_vL32b_ai"; 27775let DecoderNamespace = "EXT_mmvec"; 27776} 27777def V6_vL32b_pred_pi : HInst< 27778(outs HvxVR:$Vd32, IntRegs:$Rx32), 27779(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii), 27780"if ($Pv4) $Vd32 = vmem($Rx32++#$Ii)", 27781tc_453fe68d, TypeCVI_VM_LD>, Enc_58a8bf, Requires<[UseHVXV62]>, PredRel { 27782let Inst{7-5} = 0b010; 27783let Inst{13-13} = 0b0; 27784let Inst{31-21} = 0b00101001100; 27785let isPredicated = 1; 27786let hasNewValue = 1; 27787let opNewValue = 0; 27788let addrMode = PostInc; 27789let accessSize = HVXVectorAccess; 27790let isCVLoad = 1; 27791let mayLoad = 1; 27792let isRestrictNoSlot1Store = 1; 27793let BaseOpcode = "V6_vL32b_pi"; 27794let DecoderNamespace = "EXT_mmvec"; 27795let Constraints = "$Rx32 = $Rx32in"; 27796} 27797def V6_vL32b_pred_ppu : HInst< 27798(outs HvxVR:$Vd32, IntRegs:$Rx32), 27799(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2), 27800"if ($Pv4) $Vd32 = vmem($Rx32++$Mu2)", 27801tc_453fe68d, TypeCVI_VM_LD>, Enc_f8c1c4, Requires<[UseHVXV62]>, PredRel { 27802let Inst{10-5} = 0b000010; 27803let Inst{31-21} = 0b00101011100; 27804let isPredicated = 1; 27805let hasNewValue = 1; 27806let opNewValue = 0; 27807let addrMode = PostInc; 27808let accessSize = HVXVectorAccess; 27809let isCVLoad = 1; 27810let mayLoad = 1; 27811let isRestrictNoSlot1Store = 1; 27812let BaseOpcode = "V6_vL32b_ppu"; 27813let DecoderNamespace = "EXT_mmvec"; 27814let Constraints = "$Rx32 = $Rx32in"; 27815} 27816def V6_vL32b_tmp_ai : HInst< 27817(outs HvxVR:$Vd32), 27818(ins IntRegs:$Rt32, s4_0Imm:$Ii), 27819"$Vd32.tmp = vmem($Rt32+#$Ii)", 27820tc_52447ecc, TypeCVI_VM_TMP_LD>, Enc_f3f408, Requires<[UseHVXV60]>, PredRel { 27821let Inst{7-5} = 0b010; 27822let Inst{12-11} = 0b00; 27823let Inst{31-21} = 0b00101000000; 27824let hasNewValue = 1; 27825let opNewValue = 0; 27826let addrMode = BaseImmOffset; 27827let accessSize = HVXVectorAccess; 27828let isCVLoad = 1; 27829let mayLoad = 1; 27830let isRestrictNoSlot1Store = 1; 27831let BaseOpcode = "V6_vL32b_tmp_ai"; 27832let isPredicable = 1; 27833let DecoderNamespace = "EXT_mmvec"; 27834} 27835def V6_vL32b_tmp_npred_ai : HInst< 27836(outs HvxVR:$Vd32), 27837(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii), 27838"if (!$Pv4) $Vd32.tmp = vmem($Rt32+#$Ii)", 27839tc_3904b926, TypeCVI_VM_TMP_LD>, Enc_8d8a30, Requires<[UseHVXV62]>, PredRel { 27840let Inst{7-5} = 0b111; 27841let Inst{31-21} = 0b00101000100; 27842let isPredicated = 1; 27843let isPredicatedFalse = 1; 27844let hasNewValue = 1; 27845let opNewValue = 0; 27846let addrMode = BaseImmOffset; 27847let accessSize = HVXVectorAccess; 27848let isCVLoad = 1; 27849let mayLoad = 1; 27850let isRestrictNoSlot1Store = 1; 27851let BaseOpcode = "V6_vL32b_tmp_ai"; 27852let DecoderNamespace = "EXT_mmvec"; 27853} 27854def V6_vL32b_tmp_npred_pi : HInst< 27855(outs HvxVR:$Vd32, IntRegs:$Rx32), 27856(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii), 27857"if (!$Pv4) $Vd32.tmp = vmem($Rx32++#$Ii)", 27858tc_b9db8205, TypeCVI_VM_TMP_LD>, Enc_58a8bf, Requires<[UseHVXV62]>, PredRel { 27859let Inst{7-5} = 0b111; 27860let Inst{13-13} = 0b0; 27861let Inst{31-21} = 0b00101001100; 27862let isPredicated = 1; 27863let isPredicatedFalse = 1; 27864let hasNewValue = 1; 27865let opNewValue = 0; 27866let addrMode = PostInc; 27867let accessSize = HVXVectorAccess; 27868let isCVLoad = 1; 27869let mayLoad = 1; 27870let isRestrictNoSlot1Store = 1; 27871let BaseOpcode = "V6_vL32b_tmp_pi"; 27872let DecoderNamespace = "EXT_mmvec"; 27873let Constraints = "$Rx32 = $Rx32in"; 27874} 27875def V6_vL32b_tmp_npred_ppu : HInst< 27876(outs HvxVR:$Vd32, IntRegs:$Rx32), 27877(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2), 27878"if (!$Pv4) $Vd32.tmp = vmem($Rx32++$Mu2)", 27879tc_b9db8205, TypeCVI_VM_TMP_LD>, Enc_f8c1c4, Requires<[UseHVXV62]>, PredRel { 27880let Inst{10-5} = 0b000111; 27881let Inst{31-21} = 0b00101011100; 27882let isPredicated = 1; 27883let isPredicatedFalse = 1; 27884let hasNewValue = 1; 27885let opNewValue = 0; 27886let addrMode = PostInc; 27887let accessSize = HVXVectorAccess; 27888let isCVLoad = 1; 27889let mayLoad = 1; 27890let isRestrictNoSlot1Store = 1; 27891let BaseOpcode = "V6_vL32b_tmp_ppu"; 27892let DecoderNamespace = "EXT_mmvec"; 27893let Constraints = "$Rx32 = $Rx32in"; 27894} 27895def V6_vL32b_tmp_pi : HInst< 27896(outs HvxVR:$Vd32, IntRegs:$Rx32), 27897(ins IntRegs:$Rx32in, s3_0Imm:$Ii), 27898"$Vd32.tmp = vmem($Rx32++#$Ii)", 27899tc_663c80a7, TypeCVI_VM_TMP_LD>, Enc_a255dc, Requires<[UseHVXV60]>, PredRel { 27900let Inst{7-5} = 0b010; 27901let Inst{13-11} = 0b000; 27902let Inst{31-21} = 0b00101001000; 27903let hasNewValue = 1; 27904let opNewValue = 0; 27905let addrMode = PostInc; 27906let accessSize = HVXVectorAccess; 27907let isCVLoad = 1; 27908let mayLoad = 1; 27909let isRestrictNoSlot1Store = 1; 27910let BaseOpcode = "V6_vL32b_tmp_pi"; 27911let isPredicable = 1; 27912let DecoderNamespace = "EXT_mmvec"; 27913let Constraints = "$Rx32 = $Rx32in"; 27914} 27915def V6_vL32b_tmp_ppu : HInst< 27916(outs HvxVR:$Vd32, IntRegs:$Rx32), 27917(ins IntRegs:$Rx32in, ModRegs:$Mu2), 27918"$Vd32.tmp = vmem($Rx32++$Mu2)", 27919tc_663c80a7, TypeCVI_VM_TMP_LD>, Enc_2ebe3b, Requires<[UseHVXV60]>, PredRel { 27920let Inst{12-5} = 0b00000010; 27921let Inst{31-21} = 0b00101011000; 27922let hasNewValue = 1; 27923let opNewValue = 0; 27924let addrMode = PostInc; 27925let accessSize = HVXVectorAccess; 27926let isCVLoad = 1; 27927let mayLoad = 1; 27928let isRestrictNoSlot1Store = 1; 27929let BaseOpcode = "V6_vL32b_tmp_ppu"; 27930let isPredicable = 1; 27931let DecoderNamespace = "EXT_mmvec"; 27932let Constraints = "$Rx32 = $Rx32in"; 27933} 27934def V6_vL32b_tmp_pred_ai : HInst< 27935(outs HvxVR:$Vd32), 27936(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii), 27937"if ($Pv4) $Vd32.tmp = vmem($Rt32+#$Ii)", 27938tc_3904b926, TypeCVI_VM_TMP_LD>, Enc_8d8a30, Requires<[UseHVXV62]>, PredRel { 27939let Inst{7-5} = 0b110; 27940let Inst{31-21} = 0b00101000100; 27941let isPredicated = 1; 27942let hasNewValue = 1; 27943let opNewValue = 0; 27944let addrMode = BaseImmOffset; 27945let accessSize = HVXVectorAccess; 27946let isCVLoad = 1; 27947let mayLoad = 1; 27948let isRestrictNoSlot1Store = 1; 27949let BaseOpcode = "V6_vL32b_tmp_ai"; 27950let DecoderNamespace = "EXT_mmvec"; 27951} 27952def V6_vL32b_tmp_pred_pi : HInst< 27953(outs HvxVR:$Vd32, IntRegs:$Rx32), 27954(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii), 27955"if ($Pv4) $Vd32.tmp = vmem($Rx32++#$Ii)", 27956tc_b9db8205, TypeCVI_VM_TMP_LD>, Enc_58a8bf, Requires<[UseHVXV62]>, PredRel { 27957let Inst{7-5} = 0b110; 27958let Inst{13-13} = 0b0; 27959let Inst{31-21} = 0b00101001100; 27960let isPredicated = 1; 27961let hasNewValue = 1; 27962let opNewValue = 0; 27963let addrMode = PostInc; 27964let accessSize = HVXVectorAccess; 27965let isCVLoad = 1; 27966let mayLoad = 1; 27967let isRestrictNoSlot1Store = 1; 27968let BaseOpcode = "V6_vL32b_tmp_pi"; 27969let DecoderNamespace = "EXT_mmvec"; 27970let Constraints = "$Rx32 = $Rx32in"; 27971} 27972def V6_vL32b_tmp_pred_ppu : HInst< 27973(outs HvxVR:$Vd32, IntRegs:$Rx32), 27974(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2), 27975"if ($Pv4) $Vd32.tmp = vmem($Rx32++$Mu2)", 27976tc_b9db8205, TypeCVI_VM_TMP_LD>, Enc_f8c1c4, Requires<[UseHVXV62]>, PredRel { 27977let Inst{10-5} = 0b000110; 27978let Inst{31-21} = 0b00101011100; 27979let isPredicated = 1; 27980let hasNewValue = 1; 27981let opNewValue = 0; 27982let addrMode = PostInc; 27983let accessSize = HVXVectorAccess; 27984let isCVLoad = 1; 27985let mayLoad = 1; 27986let isRestrictNoSlot1Store = 1; 27987let BaseOpcode = "V6_vL32b_tmp_ppu"; 27988let DecoderNamespace = "EXT_mmvec"; 27989let Constraints = "$Rx32 = $Rx32in"; 27990} 27991def V6_vS32Ub_ai : HInst< 27992(outs), 27993(ins IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32), 27994"vmemu($Rt32+#$Ii) = $Vs32", 27995tc_f21e8abb, TypeCVI_VM_STU>, Enc_c9e3bc, Requires<[UseHVXV60]>, NewValueRel { 27996let Inst{7-5} = 0b111; 27997let Inst{12-11} = 0b00; 27998let Inst{31-21} = 0b00101000001; 27999let addrMode = BaseImmOffset; 28000let accessSize = HVXVectorAccess; 28001let mayStore = 1; 28002let BaseOpcode = "V6_vS32Ub_ai"; 28003let isPredicable = 1; 28004let DecoderNamespace = "EXT_mmvec"; 28005} 28006def V6_vS32Ub_npred_ai : HInst< 28007(outs), 28008(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32), 28009"if (!$Pv4) vmemu($Rt32+#$Ii) = $Vs32", 28010tc_131f1c81, TypeCVI_VM_STU>, Enc_27b757, Requires<[UseHVXV60]>, NewValueRel { 28011let Inst{7-5} = 0b111; 28012let Inst{31-21} = 0b00101000101; 28013let isPredicated = 1; 28014let isPredicatedFalse = 1; 28015let addrMode = BaseImmOffset; 28016let accessSize = HVXVectorAccess; 28017let mayStore = 1; 28018let BaseOpcode = "V6_vS32Ub_ai"; 28019let DecoderNamespace = "EXT_mmvec"; 28020} 28021def V6_vS32Ub_npred_pi : HInst< 28022(outs IntRegs:$Rx32), 28023(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32), 28024"if (!$Pv4) vmemu($Rx32++#$Ii) = $Vs32", 28025tc_c7039829, TypeCVI_VM_STU>, Enc_865390, Requires<[UseHVXV60]>, NewValueRel { 28026let Inst{7-5} = 0b111; 28027let Inst{13-13} = 0b0; 28028let Inst{31-21} = 0b00101001101; 28029let isPredicated = 1; 28030let isPredicatedFalse = 1; 28031let addrMode = PostInc; 28032let accessSize = HVXVectorAccess; 28033let mayStore = 1; 28034let BaseOpcode = "V6_vS32Ub_pi"; 28035let DecoderNamespace = "EXT_mmvec"; 28036let Constraints = "$Rx32 = $Rx32in"; 28037} 28038def V6_vS32Ub_npred_ppu : HInst< 28039(outs IntRegs:$Rx32), 28040(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32), 28041"if (!$Pv4) vmemu($Rx32++$Mu2) = $Vs32", 28042tc_c7039829, TypeCVI_VM_STU>, Enc_1ef990, Requires<[UseHVXV60]>, NewValueRel { 28043let Inst{10-5} = 0b000111; 28044let Inst{31-21} = 0b00101011101; 28045let isPredicated = 1; 28046let isPredicatedFalse = 1; 28047let addrMode = PostInc; 28048let accessSize = HVXVectorAccess; 28049let mayStore = 1; 28050let BaseOpcode = "V6_vS32Ub_ppu"; 28051let DecoderNamespace = "EXT_mmvec"; 28052let Constraints = "$Rx32 = $Rx32in"; 28053} 28054def V6_vS32Ub_pi : HInst< 28055(outs IntRegs:$Rx32), 28056(ins IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32), 28057"vmemu($Rx32++#$Ii) = $Vs32", 28058tc_e2d2e9e5, TypeCVI_VM_STU>, Enc_b62ef7, Requires<[UseHVXV60]>, NewValueRel { 28059let Inst{7-5} = 0b111; 28060let Inst{13-11} = 0b000; 28061let Inst{31-21} = 0b00101001001; 28062let addrMode = PostInc; 28063let accessSize = HVXVectorAccess; 28064let mayStore = 1; 28065let BaseOpcode = "V6_vS32Ub_pi"; 28066let isPredicable = 1; 28067let DecoderNamespace = "EXT_mmvec"; 28068let Constraints = "$Rx32 = $Rx32in"; 28069} 28070def V6_vS32Ub_ppu : HInst< 28071(outs IntRegs:$Rx32), 28072(ins IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32), 28073"vmemu($Rx32++$Mu2) = $Vs32", 28074tc_e2d2e9e5, TypeCVI_VM_STU>, Enc_d15d19, Requires<[UseHVXV60]>, NewValueRel { 28075let Inst{12-5} = 0b00000111; 28076let Inst{31-21} = 0b00101011001; 28077let addrMode = PostInc; 28078let accessSize = HVXVectorAccess; 28079let mayStore = 1; 28080let BaseOpcode = "V6_vS32Ub_ppu"; 28081let isPredicable = 1; 28082let DecoderNamespace = "EXT_mmvec"; 28083let Constraints = "$Rx32 = $Rx32in"; 28084} 28085def V6_vS32Ub_pred_ai : HInst< 28086(outs), 28087(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32), 28088"if ($Pv4) vmemu($Rt32+#$Ii) = $Vs32", 28089tc_131f1c81, TypeCVI_VM_STU>, Enc_27b757, Requires<[UseHVXV60]>, NewValueRel { 28090let Inst{7-5} = 0b110; 28091let Inst{31-21} = 0b00101000101; 28092let isPredicated = 1; 28093let addrMode = BaseImmOffset; 28094let accessSize = HVXVectorAccess; 28095let mayStore = 1; 28096let BaseOpcode = "V6_vS32Ub_ai"; 28097let DecoderNamespace = "EXT_mmvec"; 28098} 28099def V6_vS32Ub_pred_pi : HInst< 28100(outs IntRegs:$Rx32), 28101(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32), 28102"if ($Pv4) vmemu($Rx32++#$Ii) = $Vs32", 28103tc_c7039829, TypeCVI_VM_STU>, Enc_865390, Requires<[UseHVXV60]>, NewValueRel { 28104let Inst{7-5} = 0b110; 28105let Inst{13-13} = 0b0; 28106let Inst{31-21} = 0b00101001101; 28107let isPredicated = 1; 28108let addrMode = PostInc; 28109let accessSize = HVXVectorAccess; 28110let mayStore = 1; 28111let BaseOpcode = "V6_vS32Ub_pi"; 28112let DecoderNamespace = "EXT_mmvec"; 28113let Constraints = "$Rx32 = $Rx32in"; 28114} 28115def V6_vS32Ub_pred_ppu : HInst< 28116(outs IntRegs:$Rx32), 28117(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32), 28118"if ($Pv4) vmemu($Rx32++$Mu2) = $Vs32", 28119tc_c7039829, TypeCVI_VM_STU>, Enc_1ef990, Requires<[UseHVXV60]>, NewValueRel { 28120let Inst{10-5} = 0b000110; 28121let Inst{31-21} = 0b00101011101; 28122let isPredicated = 1; 28123let addrMode = PostInc; 28124let accessSize = HVXVectorAccess; 28125let mayStore = 1; 28126let BaseOpcode = "V6_vS32Ub_ppu"; 28127let DecoderNamespace = "EXT_mmvec"; 28128let Constraints = "$Rx32 = $Rx32in"; 28129} 28130def V6_vS32b_ai : HInst< 28131(outs), 28132(ins IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32), 28133"vmem($Rt32+#$Ii) = $Vs32", 28134tc_c5dba46e, TypeCVI_VM_ST>, Enc_c9e3bc, Requires<[UseHVXV60]>, NewValueRel { 28135let Inst{7-5} = 0b000; 28136let Inst{12-11} = 0b00; 28137let Inst{31-21} = 0b00101000001; 28138let addrMode = BaseImmOffset; 28139let accessSize = HVXVectorAccess; 28140let mayStore = 1; 28141let BaseOpcode = "V6_vS32b_ai"; 28142let isNVStorable = 1; 28143let isPredicable = 1; 28144let DecoderNamespace = "EXT_mmvec"; 28145} 28146def V6_vS32b_new_ai : HInst< 28147(outs), 28148(ins IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Os8), 28149"vmem($Rt32+#$Ii) = $Os8.new", 28150tc_ab23f776, TypeCVI_VM_NEW_ST>, Enc_f77fbc, Requires<[UseHVXV60]>, NewValueRel { 28151let Inst{7-3} = 0b00100; 28152let Inst{12-11} = 0b00; 28153let Inst{31-21} = 0b00101000001; 28154let addrMode = BaseImmOffset; 28155let accessSize = HVXVectorAccess; 28156let isNVStore = 1; 28157let CVINew = 1; 28158let isNewValue = 1; 28159let mayStore = 1; 28160let BaseOpcode = "V6_vS32b_ai"; 28161let isPredicable = 1; 28162let DecoderNamespace = "EXT_mmvec"; 28163let opNewValue = 2; 28164} 28165def V6_vS32b_new_npred_ai : HInst< 28166(outs), 28167(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Os8), 28168"if (!$Pv4) vmem($Rt32+#$Ii) = $Os8.new", 28169tc_7177e272, TypeCVI_VM_NEW_ST>, Enc_f7430e, Requires<[UseHVXV60]>, NewValueRel { 28170let Inst{7-3} = 0b01101; 28171let Inst{31-21} = 0b00101000101; 28172let isPredicated = 1; 28173let isPredicatedFalse = 1; 28174let addrMode = BaseImmOffset; 28175let accessSize = HVXVectorAccess; 28176let isNVStore = 1; 28177let CVINew = 1; 28178let isNewValue = 1; 28179let mayStore = 1; 28180let BaseOpcode = "V6_vS32b_ai"; 28181let DecoderNamespace = "EXT_mmvec"; 28182let opNewValue = 3; 28183} 28184def V6_vS32b_new_npred_pi : HInst< 28185(outs IntRegs:$Rx32), 28186(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Os8), 28187"if (!$Pv4) vmem($Rx32++#$Ii) = $Os8.new", 28188tc_e99d4c2e, TypeCVI_VM_NEW_ST>, Enc_784502, Requires<[UseHVXV60]>, NewValueRel { 28189let Inst{7-3} = 0b01101; 28190let Inst{13-13} = 0b0; 28191let Inst{31-21} = 0b00101001101; 28192let isPredicated = 1; 28193let isPredicatedFalse = 1; 28194let addrMode = PostInc; 28195let accessSize = HVXVectorAccess; 28196let isNVStore = 1; 28197let CVINew = 1; 28198let isNewValue = 1; 28199let mayStore = 1; 28200let BaseOpcode = "V6_vS32b_pi"; 28201let DecoderNamespace = "EXT_mmvec"; 28202let opNewValue = 4; 28203let Constraints = "$Rx32 = $Rx32in"; 28204} 28205def V6_vS32b_new_npred_ppu : HInst< 28206(outs IntRegs:$Rx32), 28207(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Os8), 28208"if (!$Pv4) vmem($Rx32++$Mu2) = $Os8.new", 28209tc_e99d4c2e, TypeCVI_VM_NEW_ST>, Enc_372c9d, Requires<[UseHVXV60]>, NewValueRel { 28210let Inst{10-3} = 0b00001101; 28211let Inst{31-21} = 0b00101011101; 28212let isPredicated = 1; 28213let isPredicatedFalse = 1; 28214let addrMode = PostInc; 28215let accessSize = HVXVectorAccess; 28216let isNVStore = 1; 28217let CVINew = 1; 28218let isNewValue = 1; 28219let mayStore = 1; 28220let BaseOpcode = "V6_vS32b_ppu"; 28221let DecoderNamespace = "EXT_mmvec"; 28222let opNewValue = 4; 28223let Constraints = "$Rx32 = $Rx32in"; 28224} 28225def V6_vS32b_new_pi : HInst< 28226(outs IntRegs:$Rx32), 28227(ins IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Os8), 28228"vmem($Rx32++#$Ii) = $Os8.new", 28229tc_6942b6e0, TypeCVI_VM_NEW_ST>, Enc_1aaec1, Requires<[UseHVXV60]>, NewValueRel { 28230let Inst{7-3} = 0b00100; 28231let Inst{13-11} = 0b000; 28232let Inst{31-21} = 0b00101001001; 28233let addrMode = PostInc; 28234let accessSize = HVXVectorAccess; 28235let isNVStore = 1; 28236let CVINew = 1; 28237let isNewValue = 1; 28238let mayStore = 1; 28239let BaseOpcode = "V6_vS32b_pi"; 28240let isPredicable = 1; 28241let DecoderNamespace = "EXT_mmvec"; 28242let opNewValue = 3; 28243let Constraints = "$Rx32 = $Rx32in"; 28244} 28245def V6_vS32b_new_ppu : HInst< 28246(outs IntRegs:$Rx32), 28247(ins IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Os8), 28248"vmem($Rx32++$Mu2) = $Os8.new", 28249tc_6942b6e0, TypeCVI_VM_NEW_ST>, Enc_cf1927, Requires<[UseHVXV60]>, NewValueRel { 28250let Inst{12-3} = 0b0000000100; 28251let Inst{31-21} = 0b00101011001; 28252let addrMode = PostInc; 28253let accessSize = HVXVectorAccess; 28254let isNVStore = 1; 28255let CVINew = 1; 28256let isNewValue = 1; 28257let mayStore = 1; 28258let BaseOpcode = "V6_vS32b_ppu"; 28259let isPredicable = 1; 28260let DecoderNamespace = "EXT_mmvec"; 28261let opNewValue = 3; 28262let Constraints = "$Rx32 = $Rx32in"; 28263} 28264def V6_vS32b_new_pred_ai : HInst< 28265(outs), 28266(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Os8), 28267"if ($Pv4) vmem($Rt32+#$Ii) = $Os8.new", 28268tc_7177e272, TypeCVI_VM_NEW_ST>, Enc_f7430e, Requires<[UseHVXV60]>, NewValueRel { 28269let Inst{7-3} = 0b01000; 28270let Inst{31-21} = 0b00101000101; 28271let isPredicated = 1; 28272let addrMode = BaseImmOffset; 28273let accessSize = HVXVectorAccess; 28274let isNVStore = 1; 28275let CVINew = 1; 28276let isNewValue = 1; 28277let mayStore = 1; 28278let BaseOpcode = "V6_vS32b_ai"; 28279let DecoderNamespace = "EXT_mmvec"; 28280let opNewValue = 3; 28281} 28282def V6_vS32b_new_pred_pi : HInst< 28283(outs IntRegs:$Rx32), 28284(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Os8), 28285"if ($Pv4) vmem($Rx32++#$Ii) = $Os8.new", 28286tc_e99d4c2e, TypeCVI_VM_NEW_ST>, Enc_784502, Requires<[UseHVXV60]>, NewValueRel { 28287let Inst{7-3} = 0b01000; 28288let Inst{13-13} = 0b0; 28289let Inst{31-21} = 0b00101001101; 28290let isPredicated = 1; 28291let addrMode = PostInc; 28292let accessSize = HVXVectorAccess; 28293let isNVStore = 1; 28294let CVINew = 1; 28295let isNewValue = 1; 28296let mayStore = 1; 28297let BaseOpcode = "V6_vS32b_pi"; 28298let DecoderNamespace = "EXT_mmvec"; 28299let opNewValue = 4; 28300let Constraints = "$Rx32 = $Rx32in"; 28301} 28302def V6_vS32b_new_pred_ppu : HInst< 28303(outs IntRegs:$Rx32), 28304(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Os8), 28305"if ($Pv4) vmem($Rx32++$Mu2) = $Os8.new", 28306tc_e99d4c2e, TypeCVI_VM_NEW_ST>, Enc_372c9d, Requires<[UseHVXV60]>, NewValueRel { 28307let Inst{10-3} = 0b00001000; 28308let Inst{31-21} = 0b00101011101; 28309let isPredicated = 1; 28310let addrMode = PostInc; 28311let accessSize = HVXVectorAccess; 28312let isNVStore = 1; 28313let CVINew = 1; 28314let isNewValue = 1; 28315let mayStore = 1; 28316let BaseOpcode = "V6_vS32b_ppu"; 28317let DecoderNamespace = "EXT_mmvec"; 28318let opNewValue = 4; 28319let Constraints = "$Rx32 = $Rx32in"; 28320} 28321def V6_vS32b_npred_ai : HInst< 28322(outs), 28323(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32), 28324"if (!$Pv4) vmem($Rt32+#$Ii) = $Vs32", 28325tc_a02a10a8, TypeCVI_VM_ST>, Enc_27b757, Requires<[UseHVXV60]>, NewValueRel { 28326let Inst{7-5} = 0b001; 28327let Inst{31-21} = 0b00101000101; 28328let isPredicated = 1; 28329let isPredicatedFalse = 1; 28330let addrMode = BaseImmOffset; 28331let accessSize = HVXVectorAccess; 28332let mayStore = 1; 28333let BaseOpcode = "V6_vS32b_ai"; 28334let isNVStorable = 1; 28335let DecoderNamespace = "EXT_mmvec"; 28336} 28337def V6_vS32b_npred_pi : HInst< 28338(outs IntRegs:$Rx32), 28339(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32), 28340"if (!$Pv4) vmem($Rx32++#$Ii) = $Vs32", 28341tc_54a0dc47, TypeCVI_VM_ST>, Enc_865390, Requires<[UseHVXV60]>, NewValueRel { 28342let Inst{7-5} = 0b001; 28343let Inst{13-13} = 0b0; 28344let Inst{31-21} = 0b00101001101; 28345let isPredicated = 1; 28346let isPredicatedFalse = 1; 28347let addrMode = PostInc; 28348let accessSize = HVXVectorAccess; 28349let mayStore = 1; 28350let BaseOpcode = "V6_vS32b_pi"; 28351let isNVStorable = 1; 28352let DecoderNamespace = "EXT_mmvec"; 28353let Constraints = "$Rx32 = $Rx32in"; 28354} 28355def V6_vS32b_npred_ppu : HInst< 28356(outs IntRegs:$Rx32), 28357(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32), 28358"if (!$Pv4) vmem($Rx32++$Mu2) = $Vs32", 28359tc_54a0dc47, TypeCVI_VM_ST>, Enc_1ef990, Requires<[UseHVXV60]>, NewValueRel { 28360let Inst{10-5} = 0b000001; 28361let Inst{31-21} = 0b00101011101; 28362let isPredicated = 1; 28363let isPredicatedFalse = 1; 28364let addrMode = PostInc; 28365let accessSize = HVXVectorAccess; 28366let mayStore = 1; 28367let BaseOpcode = "V6_vS32b_ppu"; 28368let isNVStorable = 1; 28369let DecoderNamespace = "EXT_mmvec"; 28370let Constraints = "$Rx32 = $Rx32in"; 28371} 28372def V6_vS32b_nqpred_ai : HInst< 28373(outs), 28374(ins HvxQR:$Qv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32), 28375"if (!$Qv4) vmem($Rt32+#$Ii) = $Vs32", 28376tc_447d9895, TypeCVI_VM_ST>, Enc_2ea740, Requires<[UseHVXV60]> { 28377let Inst{7-5} = 0b001; 28378let Inst{31-21} = 0b00101000100; 28379let addrMode = BaseImmOffset; 28380let accessSize = HVXVectorAccess; 28381let mayStore = 1; 28382let DecoderNamespace = "EXT_mmvec"; 28383} 28384def V6_vS32b_nqpred_pi : HInst< 28385(outs IntRegs:$Rx32), 28386(ins HvxQR:$Qv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32), 28387"if (!$Qv4) vmem($Rx32++#$Ii) = $Vs32", 28388tc_191381c1, TypeCVI_VM_ST>, Enc_0b51ce, Requires<[UseHVXV60]> { 28389let Inst{7-5} = 0b001; 28390let Inst{13-13} = 0b0; 28391let Inst{31-21} = 0b00101001100; 28392let addrMode = PostInc; 28393let accessSize = HVXVectorAccess; 28394let mayStore = 1; 28395let DecoderNamespace = "EXT_mmvec"; 28396let Constraints = "$Rx32 = $Rx32in"; 28397} 28398def V6_vS32b_nqpred_ppu : HInst< 28399(outs IntRegs:$Rx32), 28400(ins HvxQR:$Qv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32), 28401"if (!$Qv4) vmem($Rx32++$Mu2) = $Vs32", 28402tc_191381c1, TypeCVI_VM_ST>, Enc_4dff07, Requires<[UseHVXV60]> { 28403let Inst{10-5} = 0b000001; 28404let Inst{31-21} = 0b00101011100; 28405let addrMode = PostInc; 28406let accessSize = HVXVectorAccess; 28407let mayStore = 1; 28408let DecoderNamespace = "EXT_mmvec"; 28409let Constraints = "$Rx32 = $Rx32in"; 28410} 28411def V6_vS32b_nt_ai : HInst< 28412(outs), 28413(ins IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32), 28414"vmem($Rt32+#$Ii):nt = $Vs32", 28415tc_c5dba46e, TypeCVI_VM_ST>, Enc_c9e3bc, Requires<[UseHVXV60]>, NewValueRel { 28416let Inst{7-5} = 0b000; 28417let Inst{12-11} = 0b00; 28418let Inst{31-21} = 0b00101000011; 28419let addrMode = BaseImmOffset; 28420let accessSize = HVXVectorAccess; 28421let isNonTemporal = 1; 28422let mayStore = 1; 28423let BaseOpcode = "V6_vS32b_ai"; 28424let isNVStorable = 1; 28425let isPredicable = 1; 28426let DecoderNamespace = "EXT_mmvec"; 28427} 28428def V6_vS32b_nt_new_ai : HInst< 28429(outs), 28430(ins IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Os8), 28431"vmem($Rt32+#$Ii):nt = $Os8.new", 28432tc_ab23f776, TypeCVI_VM_NEW_ST>, Enc_f77fbc, Requires<[UseHVXV60]>, NewValueRel { 28433let Inst{7-3} = 0b00100; 28434let Inst{12-11} = 0b00; 28435let Inst{31-21} = 0b00101000011; 28436let addrMode = BaseImmOffset; 28437let accessSize = HVXVectorAccess; 28438let isNVStore = 1; 28439let CVINew = 1; 28440let isNewValue = 1; 28441let isNonTemporal = 1; 28442let mayStore = 1; 28443let BaseOpcode = "V6_vS32b_ai"; 28444let isPredicable = 1; 28445let DecoderNamespace = "EXT_mmvec"; 28446let opNewValue = 2; 28447} 28448def V6_vS32b_nt_new_npred_ai : HInst< 28449(outs), 28450(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Os8), 28451"if (!$Pv4) vmem($Rt32+#$Ii):nt = $Os8.new", 28452tc_7177e272, TypeCVI_VM_NEW_ST>, Enc_f7430e, Requires<[UseHVXV60]>, NewValueRel { 28453let Inst{7-3} = 0b01111; 28454let Inst{31-21} = 0b00101000111; 28455let isPredicated = 1; 28456let isPredicatedFalse = 1; 28457let addrMode = BaseImmOffset; 28458let accessSize = HVXVectorAccess; 28459let isNVStore = 1; 28460let CVINew = 1; 28461let isNewValue = 1; 28462let isNonTemporal = 1; 28463let mayStore = 1; 28464let BaseOpcode = "V6_vS32b_ai"; 28465let DecoderNamespace = "EXT_mmvec"; 28466let opNewValue = 3; 28467} 28468def V6_vS32b_nt_new_npred_pi : HInst< 28469(outs IntRegs:$Rx32), 28470(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Os8), 28471"if (!$Pv4) vmem($Rx32++#$Ii):nt = $Os8.new", 28472tc_e99d4c2e, TypeCVI_VM_NEW_ST>, Enc_784502, Requires<[UseHVXV60]>, NewValueRel { 28473let Inst{7-3} = 0b01111; 28474let Inst{13-13} = 0b0; 28475let Inst{31-21} = 0b00101001111; 28476let isPredicated = 1; 28477let isPredicatedFalse = 1; 28478let addrMode = PostInc; 28479let accessSize = HVXVectorAccess; 28480let isNVStore = 1; 28481let CVINew = 1; 28482let isNewValue = 1; 28483let isNonTemporal = 1; 28484let mayStore = 1; 28485let BaseOpcode = "V6_vS32b_pi"; 28486let DecoderNamespace = "EXT_mmvec"; 28487let opNewValue = 4; 28488let Constraints = "$Rx32 = $Rx32in"; 28489} 28490def V6_vS32b_nt_new_npred_ppu : HInst< 28491(outs IntRegs:$Rx32), 28492(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Os8), 28493"if (!$Pv4) vmem($Rx32++$Mu2):nt = $Os8.new", 28494tc_e99d4c2e, TypeCVI_VM_NEW_ST>, Enc_372c9d, Requires<[UseHVXV60]>, NewValueRel { 28495let Inst{10-3} = 0b00001111; 28496let Inst{31-21} = 0b00101011111; 28497let isPredicated = 1; 28498let isPredicatedFalse = 1; 28499let addrMode = PostInc; 28500let accessSize = HVXVectorAccess; 28501let isNVStore = 1; 28502let CVINew = 1; 28503let isNewValue = 1; 28504let isNonTemporal = 1; 28505let mayStore = 1; 28506let BaseOpcode = "V6_vS32b_ppu"; 28507let DecoderNamespace = "EXT_mmvec"; 28508let opNewValue = 4; 28509let Constraints = "$Rx32 = $Rx32in"; 28510} 28511def V6_vS32b_nt_new_pi : HInst< 28512(outs IntRegs:$Rx32), 28513(ins IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Os8), 28514"vmem($Rx32++#$Ii):nt = $Os8.new", 28515tc_6942b6e0, TypeCVI_VM_NEW_ST>, Enc_1aaec1, Requires<[UseHVXV60]>, NewValueRel { 28516let Inst{7-3} = 0b00100; 28517let Inst{13-11} = 0b000; 28518let Inst{31-21} = 0b00101001011; 28519let addrMode = PostInc; 28520let accessSize = HVXVectorAccess; 28521let isNVStore = 1; 28522let CVINew = 1; 28523let isNewValue = 1; 28524let isNonTemporal = 1; 28525let mayStore = 1; 28526let BaseOpcode = "V6_vS32b_pi"; 28527let isPredicable = 1; 28528let DecoderNamespace = "EXT_mmvec"; 28529let opNewValue = 3; 28530let Constraints = "$Rx32 = $Rx32in"; 28531} 28532def V6_vS32b_nt_new_ppu : HInst< 28533(outs IntRegs:$Rx32), 28534(ins IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Os8), 28535"vmem($Rx32++$Mu2):nt = $Os8.new", 28536tc_6942b6e0, TypeCVI_VM_NEW_ST>, Enc_cf1927, Requires<[UseHVXV60]>, NewValueRel { 28537let Inst{12-3} = 0b0000000100; 28538let Inst{31-21} = 0b00101011011; 28539let addrMode = PostInc; 28540let accessSize = HVXVectorAccess; 28541let isNVStore = 1; 28542let CVINew = 1; 28543let isNewValue = 1; 28544let isNonTemporal = 1; 28545let mayStore = 1; 28546let BaseOpcode = "V6_vS32b_ppu"; 28547let isPredicable = 1; 28548let DecoderNamespace = "EXT_mmvec"; 28549let opNewValue = 3; 28550let Constraints = "$Rx32 = $Rx32in"; 28551} 28552def V6_vS32b_nt_new_pred_ai : HInst< 28553(outs), 28554(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Os8), 28555"if ($Pv4) vmem($Rt32+#$Ii):nt = $Os8.new", 28556tc_7177e272, TypeCVI_VM_NEW_ST>, Enc_f7430e, Requires<[UseHVXV60]>, NewValueRel { 28557let Inst{7-3} = 0b01010; 28558let Inst{31-21} = 0b00101000111; 28559let isPredicated = 1; 28560let addrMode = BaseImmOffset; 28561let accessSize = HVXVectorAccess; 28562let isNVStore = 1; 28563let CVINew = 1; 28564let isNewValue = 1; 28565let isNonTemporal = 1; 28566let mayStore = 1; 28567let BaseOpcode = "V6_vS32b_ai"; 28568let DecoderNamespace = "EXT_mmvec"; 28569let opNewValue = 3; 28570} 28571def V6_vS32b_nt_new_pred_pi : HInst< 28572(outs IntRegs:$Rx32), 28573(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Os8), 28574"if ($Pv4) vmem($Rx32++#$Ii):nt = $Os8.new", 28575tc_e99d4c2e, TypeCVI_VM_NEW_ST>, Enc_784502, Requires<[UseHVXV60]>, NewValueRel { 28576let Inst{7-3} = 0b01010; 28577let Inst{13-13} = 0b0; 28578let Inst{31-21} = 0b00101001111; 28579let isPredicated = 1; 28580let addrMode = PostInc; 28581let accessSize = HVXVectorAccess; 28582let isNVStore = 1; 28583let CVINew = 1; 28584let isNewValue = 1; 28585let isNonTemporal = 1; 28586let mayStore = 1; 28587let BaseOpcode = "V6_vS32b_pi"; 28588let DecoderNamespace = "EXT_mmvec"; 28589let opNewValue = 4; 28590let Constraints = "$Rx32 = $Rx32in"; 28591} 28592def V6_vS32b_nt_new_pred_ppu : HInst< 28593(outs IntRegs:$Rx32), 28594(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Os8), 28595"if ($Pv4) vmem($Rx32++$Mu2):nt = $Os8.new", 28596tc_e99d4c2e, TypeCVI_VM_NEW_ST>, Enc_372c9d, Requires<[UseHVXV60]>, NewValueRel { 28597let Inst{10-3} = 0b00001010; 28598let Inst{31-21} = 0b00101011111; 28599let isPredicated = 1; 28600let addrMode = PostInc; 28601let accessSize = HVXVectorAccess; 28602let isNVStore = 1; 28603let CVINew = 1; 28604let isNewValue = 1; 28605let isNonTemporal = 1; 28606let mayStore = 1; 28607let BaseOpcode = "V6_vS32b_ppu"; 28608let DecoderNamespace = "EXT_mmvec"; 28609let opNewValue = 4; 28610let Constraints = "$Rx32 = $Rx32in"; 28611} 28612def V6_vS32b_nt_npred_ai : HInst< 28613(outs), 28614(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32), 28615"if (!$Pv4) vmem($Rt32+#$Ii):nt = $Vs32", 28616tc_a02a10a8, TypeCVI_VM_ST>, Enc_27b757, Requires<[UseHVXV60]>, NewValueRel { 28617let Inst{7-5} = 0b001; 28618let Inst{31-21} = 0b00101000111; 28619let isPredicated = 1; 28620let isPredicatedFalse = 1; 28621let addrMode = BaseImmOffset; 28622let accessSize = HVXVectorAccess; 28623let isNonTemporal = 1; 28624let mayStore = 1; 28625let BaseOpcode = "V6_vS32b_ai"; 28626let isNVStorable = 1; 28627let DecoderNamespace = "EXT_mmvec"; 28628} 28629def V6_vS32b_nt_npred_pi : HInst< 28630(outs IntRegs:$Rx32), 28631(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32), 28632"if (!$Pv4) vmem($Rx32++#$Ii):nt = $Vs32", 28633tc_54a0dc47, TypeCVI_VM_ST>, Enc_865390, Requires<[UseHVXV60]>, NewValueRel { 28634let Inst{7-5} = 0b001; 28635let Inst{13-13} = 0b0; 28636let Inst{31-21} = 0b00101001111; 28637let isPredicated = 1; 28638let isPredicatedFalse = 1; 28639let addrMode = PostInc; 28640let accessSize = HVXVectorAccess; 28641let isNonTemporal = 1; 28642let mayStore = 1; 28643let BaseOpcode = "V6_vS32b_pi"; 28644let isNVStorable = 1; 28645let DecoderNamespace = "EXT_mmvec"; 28646let Constraints = "$Rx32 = $Rx32in"; 28647} 28648def V6_vS32b_nt_npred_ppu : HInst< 28649(outs IntRegs:$Rx32), 28650(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32), 28651"if (!$Pv4) vmem($Rx32++$Mu2):nt = $Vs32", 28652tc_54a0dc47, TypeCVI_VM_ST>, Enc_1ef990, Requires<[UseHVXV60]>, NewValueRel { 28653let Inst{10-5} = 0b000001; 28654let Inst{31-21} = 0b00101011111; 28655let isPredicated = 1; 28656let isPredicatedFalse = 1; 28657let addrMode = PostInc; 28658let accessSize = HVXVectorAccess; 28659let isNonTemporal = 1; 28660let mayStore = 1; 28661let BaseOpcode = "V6_vS32b_ppu"; 28662let isNVStorable = 1; 28663let DecoderNamespace = "EXT_mmvec"; 28664let Constraints = "$Rx32 = $Rx32in"; 28665} 28666def V6_vS32b_nt_nqpred_ai : HInst< 28667(outs), 28668(ins HvxQR:$Qv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32), 28669"if (!$Qv4) vmem($Rt32+#$Ii):nt = $Vs32", 28670tc_447d9895, TypeCVI_VM_ST>, Enc_2ea740, Requires<[UseHVXV60]> { 28671let Inst{7-5} = 0b001; 28672let Inst{31-21} = 0b00101000110; 28673let addrMode = BaseImmOffset; 28674let accessSize = HVXVectorAccess; 28675let isNonTemporal = 1; 28676let mayStore = 1; 28677let DecoderNamespace = "EXT_mmvec"; 28678} 28679def V6_vS32b_nt_nqpred_pi : HInst< 28680(outs IntRegs:$Rx32), 28681(ins HvxQR:$Qv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32), 28682"if (!$Qv4) vmem($Rx32++#$Ii):nt = $Vs32", 28683tc_191381c1, TypeCVI_VM_ST>, Enc_0b51ce, Requires<[UseHVXV60]> { 28684let Inst{7-5} = 0b001; 28685let Inst{13-13} = 0b0; 28686let Inst{31-21} = 0b00101001110; 28687let addrMode = PostInc; 28688let accessSize = HVXVectorAccess; 28689let isNonTemporal = 1; 28690let mayStore = 1; 28691let DecoderNamespace = "EXT_mmvec"; 28692let Constraints = "$Rx32 = $Rx32in"; 28693} 28694def V6_vS32b_nt_nqpred_ppu : HInst< 28695(outs IntRegs:$Rx32), 28696(ins HvxQR:$Qv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32), 28697"if (!$Qv4) vmem($Rx32++$Mu2):nt = $Vs32", 28698tc_191381c1, TypeCVI_VM_ST>, Enc_4dff07, Requires<[UseHVXV60]> { 28699let Inst{10-5} = 0b000001; 28700let Inst{31-21} = 0b00101011110; 28701let addrMode = PostInc; 28702let accessSize = HVXVectorAccess; 28703let isNonTemporal = 1; 28704let mayStore = 1; 28705let DecoderNamespace = "EXT_mmvec"; 28706let Constraints = "$Rx32 = $Rx32in"; 28707} 28708def V6_vS32b_nt_pi : HInst< 28709(outs IntRegs:$Rx32), 28710(ins IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32), 28711"vmem($Rx32++#$Ii):nt = $Vs32", 28712tc_3e2aaafc, TypeCVI_VM_ST>, Enc_b62ef7, Requires<[UseHVXV60]>, NewValueRel { 28713let Inst{7-5} = 0b000; 28714let Inst{13-11} = 0b000; 28715let Inst{31-21} = 0b00101001011; 28716let addrMode = PostInc; 28717let accessSize = HVXVectorAccess; 28718let isNonTemporal = 1; 28719let mayStore = 1; 28720let BaseOpcode = "V6_vS32b_pi"; 28721let isNVStorable = 1; 28722let isPredicable = 1; 28723let DecoderNamespace = "EXT_mmvec"; 28724let Constraints = "$Rx32 = $Rx32in"; 28725} 28726def V6_vS32b_nt_ppu : HInst< 28727(outs IntRegs:$Rx32), 28728(ins IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32), 28729"vmem($Rx32++$Mu2):nt = $Vs32", 28730tc_3e2aaafc, TypeCVI_VM_ST>, Enc_d15d19, Requires<[UseHVXV60]>, NewValueRel { 28731let Inst{12-5} = 0b00000000; 28732let Inst{31-21} = 0b00101011011; 28733let addrMode = PostInc; 28734let accessSize = HVXVectorAccess; 28735let isNonTemporal = 1; 28736let mayStore = 1; 28737let BaseOpcode = "V6_vS32b_ppu"; 28738let isNVStorable = 1; 28739let isPredicable = 1; 28740let DecoderNamespace = "EXT_mmvec"; 28741let Constraints = "$Rx32 = $Rx32in"; 28742} 28743def V6_vS32b_nt_pred_ai : HInst< 28744(outs), 28745(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32), 28746"if ($Pv4) vmem($Rt32+#$Ii):nt = $Vs32", 28747tc_a02a10a8, TypeCVI_VM_ST>, Enc_27b757, Requires<[UseHVXV60]>, NewValueRel { 28748let Inst{7-5} = 0b000; 28749let Inst{31-21} = 0b00101000111; 28750let isPredicated = 1; 28751let addrMode = BaseImmOffset; 28752let accessSize = HVXVectorAccess; 28753let isNonTemporal = 1; 28754let mayStore = 1; 28755let BaseOpcode = "V6_vS32b_ai"; 28756let isNVStorable = 1; 28757let DecoderNamespace = "EXT_mmvec"; 28758} 28759def V6_vS32b_nt_pred_pi : HInst< 28760(outs IntRegs:$Rx32), 28761(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32), 28762"if ($Pv4) vmem($Rx32++#$Ii):nt = $Vs32", 28763tc_54a0dc47, TypeCVI_VM_ST>, Enc_865390, Requires<[UseHVXV60]>, NewValueRel { 28764let Inst{7-5} = 0b000; 28765let Inst{13-13} = 0b0; 28766let Inst{31-21} = 0b00101001111; 28767let isPredicated = 1; 28768let addrMode = PostInc; 28769let accessSize = HVXVectorAccess; 28770let isNonTemporal = 1; 28771let mayStore = 1; 28772let BaseOpcode = "V6_vS32b_pi"; 28773let isNVStorable = 1; 28774let DecoderNamespace = "EXT_mmvec"; 28775let Constraints = "$Rx32 = $Rx32in"; 28776} 28777def V6_vS32b_nt_pred_ppu : HInst< 28778(outs IntRegs:$Rx32), 28779(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32), 28780"if ($Pv4) vmem($Rx32++$Mu2):nt = $Vs32", 28781tc_54a0dc47, TypeCVI_VM_ST>, Enc_1ef990, Requires<[UseHVXV60]>, NewValueRel { 28782let Inst{10-5} = 0b000000; 28783let Inst{31-21} = 0b00101011111; 28784let isPredicated = 1; 28785let addrMode = PostInc; 28786let accessSize = HVXVectorAccess; 28787let isNonTemporal = 1; 28788let mayStore = 1; 28789let BaseOpcode = "V6_vS32b_ppu"; 28790let isNVStorable = 1; 28791let DecoderNamespace = "EXT_mmvec"; 28792let Constraints = "$Rx32 = $Rx32in"; 28793} 28794def V6_vS32b_nt_qpred_ai : HInst< 28795(outs), 28796(ins HvxQR:$Qv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32), 28797"if ($Qv4) vmem($Rt32+#$Ii):nt = $Vs32", 28798tc_447d9895, TypeCVI_VM_ST>, Enc_2ea740, Requires<[UseHVXV60]> { 28799let Inst{7-5} = 0b000; 28800let Inst{31-21} = 0b00101000110; 28801let addrMode = BaseImmOffset; 28802let accessSize = HVXVectorAccess; 28803let isNonTemporal = 1; 28804let mayStore = 1; 28805let DecoderNamespace = "EXT_mmvec"; 28806} 28807def V6_vS32b_nt_qpred_pi : HInst< 28808(outs IntRegs:$Rx32), 28809(ins HvxQR:$Qv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32), 28810"if ($Qv4) vmem($Rx32++#$Ii):nt = $Vs32", 28811tc_191381c1, TypeCVI_VM_ST>, Enc_0b51ce, Requires<[UseHVXV60]> { 28812let Inst{7-5} = 0b000; 28813let Inst{13-13} = 0b0; 28814let Inst{31-21} = 0b00101001110; 28815let addrMode = PostInc; 28816let accessSize = HVXVectorAccess; 28817let isNonTemporal = 1; 28818let mayStore = 1; 28819let DecoderNamespace = "EXT_mmvec"; 28820let Constraints = "$Rx32 = $Rx32in"; 28821} 28822def V6_vS32b_nt_qpred_ppu : HInst< 28823(outs IntRegs:$Rx32), 28824(ins HvxQR:$Qv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32), 28825"if ($Qv4) vmem($Rx32++$Mu2):nt = $Vs32", 28826tc_191381c1, TypeCVI_VM_ST>, Enc_4dff07, Requires<[UseHVXV60]> { 28827let Inst{10-5} = 0b000000; 28828let Inst{31-21} = 0b00101011110; 28829let addrMode = PostInc; 28830let accessSize = HVXVectorAccess; 28831let isNonTemporal = 1; 28832let mayStore = 1; 28833let DecoderNamespace = "EXT_mmvec"; 28834let Constraints = "$Rx32 = $Rx32in"; 28835} 28836def V6_vS32b_pi : HInst< 28837(outs IntRegs:$Rx32), 28838(ins IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32), 28839"vmem($Rx32++#$Ii) = $Vs32", 28840tc_3e2aaafc, TypeCVI_VM_ST>, Enc_b62ef7, Requires<[UseHVXV60]>, NewValueRel { 28841let Inst{7-5} = 0b000; 28842let Inst{13-11} = 0b000; 28843let Inst{31-21} = 0b00101001001; 28844let addrMode = PostInc; 28845let accessSize = HVXVectorAccess; 28846let mayStore = 1; 28847let BaseOpcode = "V6_vS32b_pi"; 28848let isNVStorable = 1; 28849let isPredicable = 1; 28850let DecoderNamespace = "EXT_mmvec"; 28851let Constraints = "$Rx32 = $Rx32in"; 28852} 28853def V6_vS32b_ppu : HInst< 28854(outs IntRegs:$Rx32), 28855(ins IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32), 28856"vmem($Rx32++$Mu2) = $Vs32", 28857tc_3e2aaafc, TypeCVI_VM_ST>, Enc_d15d19, Requires<[UseHVXV60]>, NewValueRel { 28858let Inst{12-5} = 0b00000000; 28859let Inst{31-21} = 0b00101011001; 28860let addrMode = PostInc; 28861let accessSize = HVXVectorAccess; 28862let mayStore = 1; 28863let isNVStorable = 1; 28864let isPredicable = 1; 28865let DecoderNamespace = "EXT_mmvec"; 28866let Constraints = "$Rx32 = $Rx32in"; 28867} 28868def V6_vS32b_pred_ai : HInst< 28869(outs), 28870(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32), 28871"if ($Pv4) vmem($Rt32+#$Ii) = $Vs32", 28872tc_a02a10a8, TypeCVI_VM_ST>, Enc_27b757, Requires<[UseHVXV60]>, NewValueRel { 28873let Inst{7-5} = 0b000; 28874let Inst{31-21} = 0b00101000101; 28875let isPredicated = 1; 28876let addrMode = BaseImmOffset; 28877let accessSize = HVXVectorAccess; 28878let mayStore = 1; 28879let BaseOpcode = "V6_vS32b_ai"; 28880let isNVStorable = 1; 28881let DecoderNamespace = "EXT_mmvec"; 28882} 28883def V6_vS32b_pred_pi : HInst< 28884(outs IntRegs:$Rx32), 28885(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32), 28886"if ($Pv4) vmem($Rx32++#$Ii) = $Vs32", 28887tc_54a0dc47, TypeCVI_VM_ST>, Enc_865390, Requires<[UseHVXV60]>, NewValueRel { 28888let Inst{7-5} = 0b000; 28889let Inst{13-13} = 0b0; 28890let Inst{31-21} = 0b00101001101; 28891let isPredicated = 1; 28892let addrMode = PostInc; 28893let accessSize = HVXVectorAccess; 28894let mayStore = 1; 28895let BaseOpcode = "V6_vS32b_pi"; 28896let isNVStorable = 1; 28897let DecoderNamespace = "EXT_mmvec"; 28898let Constraints = "$Rx32 = $Rx32in"; 28899} 28900def V6_vS32b_pred_ppu : HInst< 28901(outs IntRegs:$Rx32), 28902(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32), 28903"if ($Pv4) vmem($Rx32++$Mu2) = $Vs32", 28904tc_54a0dc47, TypeCVI_VM_ST>, Enc_1ef990, Requires<[UseHVXV60]>, NewValueRel { 28905let Inst{10-5} = 0b000000; 28906let Inst{31-21} = 0b00101011101; 28907let isPredicated = 1; 28908let addrMode = PostInc; 28909let accessSize = HVXVectorAccess; 28910let mayStore = 1; 28911let BaseOpcode = "V6_vS32b_ppu"; 28912let isNVStorable = 1; 28913let DecoderNamespace = "EXT_mmvec"; 28914let Constraints = "$Rx32 = $Rx32in"; 28915} 28916def V6_vS32b_qpred_ai : HInst< 28917(outs), 28918(ins HvxQR:$Qv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32), 28919"if ($Qv4) vmem($Rt32+#$Ii) = $Vs32", 28920tc_447d9895, TypeCVI_VM_ST>, Enc_2ea740, Requires<[UseHVXV60]> { 28921let Inst{7-5} = 0b000; 28922let Inst{31-21} = 0b00101000100; 28923let addrMode = BaseImmOffset; 28924let accessSize = HVXVectorAccess; 28925let mayStore = 1; 28926let DecoderNamespace = "EXT_mmvec"; 28927} 28928def V6_vS32b_qpred_pi : HInst< 28929(outs IntRegs:$Rx32), 28930(ins HvxQR:$Qv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32), 28931"if ($Qv4) vmem($Rx32++#$Ii) = $Vs32", 28932tc_191381c1, TypeCVI_VM_ST>, Enc_0b51ce, Requires<[UseHVXV60]> { 28933let Inst{7-5} = 0b000; 28934let Inst{13-13} = 0b0; 28935let Inst{31-21} = 0b00101001100; 28936let addrMode = PostInc; 28937let accessSize = HVXVectorAccess; 28938let mayStore = 1; 28939let DecoderNamespace = "EXT_mmvec"; 28940let Constraints = "$Rx32 = $Rx32in"; 28941} 28942def V6_vS32b_qpred_ppu : HInst< 28943(outs IntRegs:$Rx32), 28944(ins HvxQR:$Qv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32), 28945"if ($Qv4) vmem($Rx32++$Mu2) = $Vs32", 28946tc_191381c1, TypeCVI_VM_ST>, Enc_4dff07, Requires<[UseHVXV60]> { 28947let Inst{10-5} = 0b000000; 28948let Inst{31-21} = 0b00101011100; 28949let addrMode = PostInc; 28950let accessSize = HVXVectorAccess; 28951let mayStore = 1; 28952let DecoderNamespace = "EXT_mmvec"; 28953let Constraints = "$Rx32 = $Rx32in"; 28954} 28955def V6_vS32b_srls_ai : HInst< 28956(outs), 28957(ins IntRegs:$Rt32, s4_0Imm:$Ii), 28958"vmem($Rt32+#$Ii):scatter_release", 28959tc_3ce09744, TypeCVI_SCATTER_NEW_RST>, Enc_ff3442, Requires<[UseHVXV65]> { 28960let Inst{7-0} = 0b00101000; 28961let Inst{12-11} = 0b00; 28962let Inst{31-21} = 0b00101000001; 28963let addrMode = BaseImmOffset; 28964let accessSize = HVXVectorAccess; 28965let CVINew = 1; 28966let mayStore = 1; 28967let DecoderNamespace = "EXT_mmvec"; 28968} 28969def V6_vS32b_srls_pi : HInst< 28970(outs IntRegs:$Rx32), 28971(ins IntRegs:$Rx32in, s3_0Imm:$Ii), 28972"vmem($Rx32++#$Ii):scatter_release", 28973tc_20a4bbec, TypeCVI_SCATTER_NEW_RST>, Enc_6c9ee0, Requires<[UseHVXV65]> { 28974let Inst{7-0} = 0b00101000; 28975let Inst{13-11} = 0b000; 28976let Inst{31-21} = 0b00101001001; 28977let addrMode = PostInc; 28978let accessSize = HVXVectorAccess; 28979let CVINew = 1; 28980let mayStore = 1; 28981let DecoderNamespace = "EXT_mmvec"; 28982let Constraints = "$Rx32 = $Rx32in"; 28983} 28984def V6_vS32b_srls_ppu : HInst< 28985(outs IntRegs:$Rx32), 28986(ins IntRegs:$Rx32in, ModRegs:$Mu2), 28987"vmem($Rx32++$Mu2):scatter_release", 28988tc_20a4bbec, TypeCVI_SCATTER_NEW_RST>, Enc_44661f, Requires<[UseHVXV65]> { 28989let Inst{12-0} = 0b0000000101000; 28990let Inst{31-21} = 0b00101011001; 28991let addrMode = PostInc; 28992let accessSize = HVXVectorAccess; 28993let CVINew = 1; 28994let mayStore = 1; 28995let DecoderNamespace = "EXT_mmvec"; 28996let Constraints = "$Rx32 = $Rx32in"; 28997} 28998def V6_vabsb : HInst< 28999(outs HvxVR:$Vd32), 29000(ins HvxVR:$Vu32), 29001"$Vd32.b = vabs($Vu32.b)", 29002tc_0ec46cf9, TypeCVI_VA>, Enc_e7581c, Requires<[UseHVXV65]> { 29003let Inst{7-5} = 0b100; 29004let Inst{13-13} = 0b0; 29005let Inst{31-16} = 0b0001111000000001; 29006let hasNewValue = 1; 29007let opNewValue = 0; 29008let DecoderNamespace = "EXT_mmvec"; 29009} 29010def V6_vabsb_alt : HInst< 29011(outs HvxVR:$Vd32), 29012(ins HvxVR:$Vu32), 29013"$Vd32 = vabsb($Vu32)", 29014PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> { 29015let hasNewValue = 1; 29016let opNewValue = 0; 29017let isPseudo = 1; 29018let isCodeGenOnly = 1; 29019let DecoderNamespace = "EXT_mmvec"; 29020} 29021def V6_vabsb_sat : HInst< 29022(outs HvxVR:$Vd32), 29023(ins HvxVR:$Vu32), 29024"$Vd32.b = vabs($Vu32.b):sat", 29025tc_0ec46cf9, TypeCVI_VA>, Enc_e7581c, Requires<[UseHVXV65]> { 29026let Inst{7-5} = 0b101; 29027let Inst{13-13} = 0b0; 29028let Inst{31-16} = 0b0001111000000001; 29029let hasNewValue = 1; 29030let opNewValue = 0; 29031let DecoderNamespace = "EXT_mmvec"; 29032} 29033def V6_vabsb_sat_alt : HInst< 29034(outs HvxVR:$Vd32), 29035(ins HvxVR:$Vu32), 29036"$Vd32 = vabsb($Vu32):sat", 29037PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> { 29038let hasNewValue = 1; 29039let opNewValue = 0; 29040let isPseudo = 1; 29041let isCodeGenOnly = 1; 29042let DecoderNamespace = "EXT_mmvec"; 29043} 29044def V6_vabsdiffh : HInst< 29045(outs HvxVR:$Vd32), 29046(ins HvxVR:$Vu32, HvxVR:$Vv32), 29047"$Vd32.uh = vabsdiff($Vu32.h,$Vv32.h)", 29048tc_c127de3a, TypeCVI_VX>, Enc_45364e, Requires<[UseHVXV60]> { 29049let Inst{7-5} = 0b001; 29050let Inst{13-13} = 0b0; 29051let Inst{31-21} = 0b00011100110; 29052let hasNewValue = 1; 29053let opNewValue = 0; 29054let DecoderNamespace = "EXT_mmvec"; 29055} 29056def V6_vabsdiffh_alt : HInst< 29057(outs HvxVR:$Vd32), 29058(ins HvxVR:$Vu32, HvxVR:$Vv32), 29059"$Vd32 = vabsdiffh($Vu32,$Vv32)", 29060PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 29061let hasNewValue = 1; 29062let opNewValue = 0; 29063let isPseudo = 1; 29064let isCodeGenOnly = 1; 29065let DecoderNamespace = "EXT_mmvec"; 29066} 29067def V6_vabsdiffub : HInst< 29068(outs HvxVR:$Vd32), 29069(ins HvxVR:$Vu32, HvxVR:$Vv32), 29070"$Vd32.ub = vabsdiff($Vu32.ub,$Vv32.ub)", 29071tc_c127de3a, TypeCVI_VX>, Enc_45364e, Requires<[UseHVXV60]> { 29072let Inst{7-5} = 0b000; 29073let Inst{13-13} = 0b0; 29074let Inst{31-21} = 0b00011100110; 29075let hasNewValue = 1; 29076let opNewValue = 0; 29077let DecoderNamespace = "EXT_mmvec"; 29078} 29079def V6_vabsdiffub_alt : HInst< 29080(outs HvxVR:$Vd32), 29081(ins HvxVR:$Vu32, HvxVR:$Vv32), 29082"$Vd32 = vabsdiffub($Vu32,$Vv32)", 29083PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 29084let hasNewValue = 1; 29085let opNewValue = 0; 29086let isPseudo = 1; 29087let isCodeGenOnly = 1; 29088let DecoderNamespace = "EXT_mmvec"; 29089} 29090def V6_vabsdiffuh : HInst< 29091(outs HvxVR:$Vd32), 29092(ins HvxVR:$Vu32, HvxVR:$Vv32), 29093"$Vd32.uh = vabsdiff($Vu32.uh,$Vv32.uh)", 29094tc_c127de3a, TypeCVI_VX>, Enc_45364e, Requires<[UseHVXV60]> { 29095let Inst{7-5} = 0b010; 29096let Inst{13-13} = 0b0; 29097let Inst{31-21} = 0b00011100110; 29098let hasNewValue = 1; 29099let opNewValue = 0; 29100let DecoderNamespace = "EXT_mmvec"; 29101} 29102def V6_vabsdiffuh_alt : HInst< 29103(outs HvxVR:$Vd32), 29104(ins HvxVR:$Vu32, HvxVR:$Vv32), 29105"$Vd32 = vabsdiffuh($Vu32,$Vv32)", 29106PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 29107let hasNewValue = 1; 29108let opNewValue = 0; 29109let isPseudo = 1; 29110let isCodeGenOnly = 1; 29111let DecoderNamespace = "EXT_mmvec"; 29112} 29113def V6_vabsdiffw : HInst< 29114(outs HvxVR:$Vd32), 29115(ins HvxVR:$Vu32, HvxVR:$Vv32), 29116"$Vd32.uw = vabsdiff($Vu32.w,$Vv32.w)", 29117tc_c127de3a, TypeCVI_VX>, Enc_45364e, Requires<[UseHVXV60]> { 29118let Inst{7-5} = 0b011; 29119let Inst{13-13} = 0b0; 29120let Inst{31-21} = 0b00011100110; 29121let hasNewValue = 1; 29122let opNewValue = 0; 29123let DecoderNamespace = "EXT_mmvec"; 29124} 29125def V6_vabsdiffw_alt : HInst< 29126(outs HvxVR:$Vd32), 29127(ins HvxVR:$Vu32, HvxVR:$Vv32), 29128"$Vd32 = vabsdiffw($Vu32,$Vv32)", 29129PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 29130let hasNewValue = 1; 29131let opNewValue = 0; 29132let isPseudo = 1; 29133let isCodeGenOnly = 1; 29134let DecoderNamespace = "EXT_mmvec"; 29135} 29136def V6_vabsh : HInst< 29137(outs HvxVR:$Vd32), 29138(ins HvxVR:$Vu32), 29139"$Vd32.h = vabs($Vu32.h)", 29140tc_0ec46cf9, TypeCVI_VA>, Enc_e7581c, Requires<[UseHVXV60]> { 29141let Inst{7-5} = 0b000; 29142let Inst{13-13} = 0b0; 29143let Inst{31-16} = 0b0001111000000000; 29144let hasNewValue = 1; 29145let opNewValue = 0; 29146let DecoderNamespace = "EXT_mmvec"; 29147} 29148def V6_vabsh_alt : HInst< 29149(outs HvxVR:$Vd32), 29150(ins HvxVR:$Vu32), 29151"$Vd32 = vabsh($Vu32)", 29152PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 29153let hasNewValue = 1; 29154let opNewValue = 0; 29155let isPseudo = 1; 29156let isCodeGenOnly = 1; 29157let DecoderNamespace = "EXT_mmvec"; 29158} 29159def V6_vabsh_sat : HInst< 29160(outs HvxVR:$Vd32), 29161(ins HvxVR:$Vu32), 29162"$Vd32.h = vabs($Vu32.h):sat", 29163tc_0ec46cf9, TypeCVI_VA>, Enc_e7581c, Requires<[UseHVXV60]> { 29164let Inst{7-5} = 0b001; 29165let Inst{13-13} = 0b0; 29166let Inst{31-16} = 0b0001111000000000; 29167let hasNewValue = 1; 29168let opNewValue = 0; 29169let DecoderNamespace = "EXT_mmvec"; 29170} 29171def V6_vabsh_sat_alt : HInst< 29172(outs HvxVR:$Vd32), 29173(ins HvxVR:$Vu32), 29174"$Vd32 = vabsh($Vu32):sat", 29175PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 29176let hasNewValue = 1; 29177let opNewValue = 0; 29178let isPseudo = 1; 29179let isCodeGenOnly = 1; 29180let DecoderNamespace = "EXT_mmvec"; 29181} 29182def V6_vabsub_alt : HInst< 29183(outs HvxVR:$Vd32), 29184(ins HvxVR:$Vu32), 29185"$Vd32.ub = vabs($Vu32.b)", 29186tc_0ec46cf9, TypeMAPPING>, Requires<[UseHVXV65]> { 29187let hasNewValue = 1; 29188let opNewValue = 0; 29189let isPseudo = 1; 29190let isCodeGenOnly = 1; 29191let DecoderNamespace = "EXT_mmvec"; 29192} 29193def V6_vabsuh_alt : HInst< 29194(outs HvxVR:$Vd32), 29195(ins HvxVR:$Vu32), 29196"$Vd32.uh = vabs($Vu32.h)", 29197tc_0ec46cf9, TypeMAPPING>, Requires<[UseHVXV65]> { 29198let hasNewValue = 1; 29199let opNewValue = 0; 29200let isPseudo = 1; 29201let isCodeGenOnly = 1; 29202let DecoderNamespace = "EXT_mmvec"; 29203} 29204def V6_vabsuw_alt : HInst< 29205(outs HvxVR:$Vd32), 29206(ins HvxVR:$Vu32), 29207"$Vd32.uw = vabs($Vu32.w)", 29208tc_0ec46cf9, TypeMAPPING>, Requires<[UseHVXV65]> { 29209let hasNewValue = 1; 29210let opNewValue = 0; 29211let isPseudo = 1; 29212let isCodeGenOnly = 1; 29213let DecoderNamespace = "EXT_mmvec"; 29214} 29215def V6_vabsw : HInst< 29216(outs HvxVR:$Vd32), 29217(ins HvxVR:$Vu32), 29218"$Vd32.w = vabs($Vu32.w)", 29219tc_0ec46cf9, TypeCVI_VA>, Enc_e7581c, Requires<[UseHVXV60]> { 29220let Inst{7-5} = 0b010; 29221let Inst{13-13} = 0b0; 29222let Inst{31-16} = 0b0001111000000000; 29223let hasNewValue = 1; 29224let opNewValue = 0; 29225let DecoderNamespace = "EXT_mmvec"; 29226} 29227def V6_vabsw_alt : HInst< 29228(outs HvxVR:$Vd32), 29229(ins HvxVR:$Vu32), 29230"$Vd32 = vabsw($Vu32)", 29231PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 29232let hasNewValue = 1; 29233let opNewValue = 0; 29234let isPseudo = 1; 29235let isCodeGenOnly = 1; 29236let DecoderNamespace = "EXT_mmvec"; 29237} 29238def V6_vabsw_sat : HInst< 29239(outs HvxVR:$Vd32), 29240(ins HvxVR:$Vu32), 29241"$Vd32.w = vabs($Vu32.w):sat", 29242tc_0ec46cf9, TypeCVI_VA>, Enc_e7581c, Requires<[UseHVXV60]> { 29243let Inst{7-5} = 0b011; 29244let Inst{13-13} = 0b0; 29245let Inst{31-16} = 0b0001111000000000; 29246let hasNewValue = 1; 29247let opNewValue = 0; 29248let DecoderNamespace = "EXT_mmvec"; 29249} 29250def V6_vabsw_sat_alt : HInst< 29251(outs HvxVR:$Vd32), 29252(ins HvxVR:$Vu32), 29253"$Vd32 = vabsw($Vu32):sat", 29254PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 29255let hasNewValue = 1; 29256let opNewValue = 0; 29257let isPseudo = 1; 29258let isCodeGenOnly = 1; 29259let DecoderNamespace = "EXT_mmvec"; 29260} 29261def V6_vaddb : HInst< 29262(outs HvxVR:$Vd32), 29263(ins HvxVR:$Vu32, HvxVR:$Vv32), 29264"$Vd32.b = vadd($Vu32.b,$Vv32.b)", 29265tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> { 29266let Inst{7-5} = 0b110; 29267let Inst{13-13} = 0b0; 29268let Inst{31-21} = 0b00011111101; 29269let hasNewValue = 1; 29270let opNewValue = 0; 29271let DecoderNamespace = "EXT_mmvec"; 29272} 29273def V6_vaddb_alt : HInst< 29274(outs HvxVR:$Vd32), 29275(ins HvxVR:$Vu32, HvxVR:$Vv32), 29276"$Vd32 = vaddb($Vu32,$Vv32)", 29277PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 29278let hasNewValue = 1; 29279let opNewValue = 0; 29280let isPseudo = 1; 29281let isCodeGenOnly = 1; 29282let DecoderNamespace = "EXT_mmvec"; 29283} 29284def V6_vaddb_dv : HInst< 29285(outs HvxWR:$Vdd32), 29286(ins HvxWR:$Vuu32, HvxWR:$Vvv32), 29287"$Vdd32.b = vadd($Vuu32.b,$Vvv32.b)", 29288tc_db5555f3, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> { 29289let Inst{7-5} = 0b100; 29290let Inst{13-13} = 0b0; 29291let Inst{31-21} = 0b00011100011; 29292let hasNewValue = 1; 29293let opNewValue = 0; 29294let DecoderNamespace = "EXT_mmvec"; 29295} 29296def V6_vaddb_dv_alt : HInst< 29297(outs HvxWR:$Vdd32), 29298(ins HvxWR:$Vuu32, HvxWR:$Vvv32), 29299"$Vdd32 = vaddb($Vuu32,$Vvv32)", 29300PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 29301let hasNewValue = 1; 29302let opNewValue = 0; 29303let isPseudo = 1; 29304let isCodeGenOnly = 1; 29305let DecoderNamespace = "EXT_mmvec"; 29306} 29307def V6_vaddbnq : HInst< 29308(outs HvxVR:$Vx32), 29309(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32), 29310"if (!$Qv4) $Vx32.b += $Vu32.b", 29311tc_257f6f7c, TypeCVI_VA>, Enc_a90628, Requires<[UseHVXV60]> { 29312let Inst{7-5} = 0b011; 29313let Inst{13-13} = 0b1; 29314let Inst{21-16} = 0b000001; 29315let Inst{31-24} = 0b00011110; 29316let hasNewValue = 1; 29317let opNewValue = 0; 29318let isAccumulator = 1; 29319let DecoderNamespace = "EXT_mmvec"; 29320let Constraints = "$Vx32 = $Vx32in"; 29321} 29322def V6_vaddbnq_alt : HInst< 29323(outs HvxVR:$Vx32), 29324(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32), 29325"if (!$Qv4.b) $Vx32.b += $Vu32.b", 29326PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 29327let hasNewValue = 1; 29328let opNewValue = 0; 29329let isAccumulator = 1; 29330let isPseudo = 1; 29331let isCodeGenOnly = 1; 29332let DecoderNamespace = "EXT_mmvec"; 29333let Constraints = "$Vx32 = $Vx32in"; 29334} 29335def V6_vaddbq : HInst< 29336(outs HvxVR:$Vx32), 29337(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32), 29338"if ($Qv4) $Vx32.b += $Vu32.b", 29339tc_257f6f7c, TypeCVI_VA>, Enc_a90628, Requires<[UseHVXV60]> { 29340let Inst{7-5} = 0b000; 29341let Inst{13-13} = 0b1; 29342let Inst{21-16} = 0b000001; 29343let Inst{31-24} = 0b00011110; 29344let hasNewValue = 1; 29345let opNewValue = 0; 29346let isAccumulator = 1; 29347let DecoderNamespace = "EXT_mmvec"; 29348let Constraints = "$Vx32 = $Vx32in"; 29349} 29350def V6_vaddbq_alt : HInst< 29351(outs HvxVR:$Vx32), 29352(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32), 29353"if ($Qv4.b) $Vx32.b += $Vu32.b", 29354PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 29355let hasNewValue = 1; 29356let opNewValue = 0; 29357let isAccumulator = 1; 29358let isPseudo = 1; 29359let isCodeGenOnly = 1; 29360let DecoderNamespace = "EXT_mmvec"; 29361let Constraints = "$Vx32 = $Vx32in"; 29362} 29363def V6_vaddbsat : HInst< 29364(outs HvxVR:$Vd32), 29365(ins HvxVR:$Vu32, HvxVR:$Vv32), 29366"$Vd32.b = vadd($Vu32.b,$Vv32.b):sat", 29367tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV62]> { 29368let Inst{7-5} = 0b000; 29369let Inst{13-13} = 0b0; 29370let Inst{31-21} = 0b00011111000; 29371let hasNewValue = 1; 29372let opNewValue = 0; 29373let DecoderNamespace = "EXT_mmvec"; 29374} 29375def V6_vaddbsat_alt : HInst< 29376(outs HvxVR:$Vd32), 29377(ins HvxVR:$Vu32, HvxVR:$Vv32), 29378"$Vd32 = vaddb($Vu32,$Vv32):sat", 29379PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> { 29380let hasNewValue = 1; 29381let opNewValue = 0; 29382let isPseudo = 1; 29383let isCodeGenOnly = 1; 29384let DecoderNamespace = "EXT_mmvec"; 29385} 29386def V6_vaddbsat_dv : HInst< 29387(outs HvxWR:$Vdd32), 29388(ins HvxWR:$Vuu32, HvxWR:$Vvv32), 29389"$Vdd32.b = vadd($Vuu32.b,$Vvv32.b):sat", 29390tc_db5555f3, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV62]> { 29391let Inst{7-5} = 0b000; 29392let Inst{13-13} = 0b0; 29393let Inst{31-21} = 0b00011110101; 29394let hasNewValue = 1; 29395let opNewValue = 0; 29396let DecoderNamespace = "EXT_mmvec"; 29397} 29398def V6_vaddbsat_dv_alt : HInst< 29399(outs HvxWR:$Vdd32), 29400(ins HvxWR:$Vuu32, HvxWR:$Vvv32), 29401"$Vdd32 = vaddb($Vuu32,$Vvv32):sat", 29402PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> { 29403let hasNewValue = 1; 29404let opNewValue = 0; 29405let isPseudo = 1; 29406let isCodeGenOnly = 1; 29407let DecoderNamespace = "EXT_mmvec"; 29408} 29409def V6_vaddcarry : HInst< 29410(outs HvxVR:$Vd32, HvxQR:$Qx4), 29411(ins HvxVR:$Vu32, HvxVR:$Vv32, HvxQR:$Qx4in), 29412"$Vd32.w = vadd($Vu32.w,$Vv32.w,$Qx4):carry", 29413tc_7e6a3e89, TypeCVI_VA>, Enc_b43b67, Requires<[UseHVXV62]> { 29414let Inst{7-7} = 0b0; 29415let Inst{13-13} = 0b1; 29416let Inst{31-21} = 0b00011100101; 29417let hasNewValue = 1; 29418let opNewValue = 0; 29419let DecoderNamespace = "EXT_mmvec"; 29420let Constraints = "$Qx4 = $Qx4in"; 29421} 29422def V6_vaddcarryo : HInst< 29423(outs HvxVR:$Vd32, HvxQR:$Qe4), 29424(ins HvxVR:$Vu32, HvxVR:$Vv32), 29425"$Vd32.w,$Qe4 = vadd($Vu32.w,$Vv32.w):carry", 29426tc_e35c1e93, TypeCOPROC_VX>, Enc_c1d806, Requires<[UseHVXV66]> { 29427let Inst{7-7} = 0b0; 29428let Inst{13-13} = 0b1; 29429let Inst{31-21} = 0b00011101101; 29430let hasNewValue = 1; 29431let opNewValue = 0; 29432let hasNewValue2 = 1; 29433let opNewValue2 = 1; 29434let DecoderNamespace = "EXT_mmvec"; 29435} 29436def V6_vaddcarrysat : HInst< 29437(outs HvxVR:$Vd32), 29438(ins HvxVR:$Vu32, HvxVR:$Vv32, HvxQR:$Qs4), 29439"$Vd32.w = vadd($Vu32.w,$Vv32.w,$Qs4):carry:sat", 29440tc_257f6f7c, TypeCVI_VA>, Enc_e0820b, Requires<[UseHVXV66]> { 29441let Inst{7-7} = 0b0; 29442let Inst{13-13} = 0b1; 29443let Inst{31-21} = 0b00011101100; 29444let hasNewValue = 1; 29445let opNewValue = 0; 29446let DecoderNamespace = "EXT_mmvec"; 29447} 29448def V6_vaddclbh : HInst< 29449(outs HvxVR:$Vd32), 29450(ins HvxVR:$Vu32, HvxVR:$Vv32), 29451"$Vd32.h = vadd(vclb($Vu32.h),$Vv32.h)", 29452tc_05ca8cfd, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV62]> { 29453let Inst{7-5} = 0b000; 29454let Inst{13-13} = 0b1; 29455let Inst{31-21} = 0b00011111000; 29456let hasNewValue = 1; 29457let opNewValue = 0; 29458let DecoderNamespace = "EXT_mmvec"; 29459} 29460def V6_vaddclbw : HInst< 29461(outs HvxVR:$Vd32), 29462(ins HvxVR:$Vu32, HvxVR:$Vv32), 29463"$Vd32.w = vadd(vclb($Vu32.w),$Vv32.w)", 29464tc_05ca8cfd, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV62]> { 29465let Inst{7-5} = 0b001; 29466let Inst{13-13} = 0b1; 29467let Inst{31-21} = 0b00011111000; 29468let hasNewValue = 1; 29469let opNewValue = 0; 29470let DecoderNamespace = "EXT_mmvec"; 29471} 29472def V6_vaddh : HInst< 29473(outs HvxVR:$Vd32), 29474(ins HvxVR:$Vu32, HvxVR:$Vv32), 29475"$Vd32.h = vadd($Vu32.h,$Vv32.h)", 29476tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> { 29477let Inst{7-5} = 0b111; 29478let Inst{13-13} = 0b0; 29479let Inst{31-21} = 0b00011111101; 29480let hasNewValue = 1; 29481let opNewValue = 0; 29482let DecoderNamespace = "EXT_mmvec"; 29483} 29484def V6_vaddh_alt : HInst< 29485(outs HvxVR:$Vd32), 29486(ins HvxVR:$Vu32, HvxVR:$Vv32), 29487"$Vd32 = vaddh($Vu32,$Vv32)", 29488PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 29489let hasNewValue = 1; 29490let opNewValue = 0; 29491let isPseudo = 1; 29492let isCodeGenOnly = 1; 29493let DecoderNamespace = "EXT_mmvec"; 29494} 29495def V6_vaddh_dv : HInst< 29496(outs HvxWR:$Vdd32), 29497(ins HvxWR:$Vuu32, HvxWR:$Vvv32), 29498"$Vdd32.h = vadd($Vuu32.h,$Vvv32.h)", 29499tc_db5555f3, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> { 29500let Inst{7-5} = 0b101; 29501let Inst{13-13} = 0b0; 29502let Inst{31-21} = 0b00011100011; 29503let hasNewValue = 1; 29504let opNewValue = 0; 29505let DecoderNamespace = "EXT_mmvec"; 29506} 29507def V6_vaddh_dv_alt : HInst< 29508(outs HvxWR:$Vdd32), 29509(ins HvxWR:$Vuu32, HvxWR:$Vvv32), 29510"$Vdd32 = vaddh($Vuu32,$Vvv32)", 29511PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 29512let hasNewValue = 1; 29513let opNewValue = 0; 29514let isPseudo = 1; 29515let isCodeGenOnly = 1; 29516let DecoderNamespace = "EXT_mmvec"; 29517} 29518def V6_vaddhnq : HInst< 29519(outs HvxVR:$Vx32), 29520(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32), 29521"if (!$Qv4) $Vx32.h += $Vu32.h", 29522tc_257f6f7c, TypeCVI_VA>, Enc_a90628, Requires<[UseHVXV60]> { 29523let Inst{7-5} = 0b100; 29524let Inst{13-13} = 0b1; 29525let Inst{21-16} = 0b000001; 29526let Inst{31-24} = 0b00011110; 29527let hasNewValue = 1; 29528let opNewValue = 0; 29529let isAccumulator = 1; 29530let DecoderNamespace = "EXT_mmvec"; 29531let Constraints = "$Vx32 = $Vx32in"; 29532} 29533def V6_vaddhnq_alt : HInst< 29534(outs HvxVR:$Vx32), 29535(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32), 29536"if (!$Qv4.h) $Vx32.h += $Vu32.h", 29537PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 29538let hasNewValue = 1; 29539let opNewValue = 0; 29540let isAccumulator = 1; 29541let isPseudo = 1; 29542let isCodeGenOnly = 1; 29543let DecoderNamespace = "EXT_mmvec"; 29544let Constraints = "$Vx32 = $Vx32in"; 29545} 29546def V6_vaddhq : HInst< 29547(outs HvxVR:$Vx32), 29548(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32), 29549"if ($Qv4) $Vx32.h += $Vu32.h", 29550tc_257f6f7c, TypeCVI_VA>, Enc_a90628, Requires<[UseHVXV60]> { 29551let Inst{7-5} = 0b001; 29552let Inst{13-13} = 0b1; 29553let Inst{21-16} = 0b000001; 29554let Inst{31-24} = 0b00011110; 29555let hasNewValue = 1; 29556let opNewValue = 0; 29557let isAccumulator = 1; 29558let DecoderNamespace = "EXT_mmvec"; 29559let Constraints = "$Vx32 = $Vx32in"; 29560} 29561def V6_vaddhq_alt : HInst< 29562(outs HvxVR:$Vx32), 29563(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32), 29564"if ($Qv4.h) $Vx32.h += $Vu32.h", 29565PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 29566let hasNewValue = 1; 29567let opNewValue = 0; 29568let isAccumulator = 1; 29569let isPseudo = 1; 29570let isCodeGenOnly = 1; 29571let DecoderNamespace = "EXT_mmvec"; 29572let Constraints = "$Vx32 = $Vx32in"; 29573} 29574def V6_vaddhsat : HInst< 29575(outs HvxVR:$Vd32), 29576(ins HvxVR:$Vu32, HvxVR:$Vv32), 29577"$Vd32.h = vadd($Vu32.h,$Vv32.h):sat", 29578tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> { 29579let Inst{7-5} = 0b011; 29580let Inst{13-13} = 0b0; 29581let Inst{31-21} = 0b00011100010; 29582let hasNewValue = 1; 29583let opNewValue = 0; 29584let DecoderNamespace = "EXT_mmvec"; 29585} 29586def V6_vaddhsat_alt : HInst< 29587(outs HvxVR:$Vd32), 29588(ins HvxVR:$Vu32, HvxVR:$Vv32), 29589"$Vd32 = vaddh($Vu32,$Vv32):sat", 29590PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 29591let hasNewValue = 1; 29592let opNewValue = 0; 29593let isPseudo = 1; 29594let isCodeGenOnly = 1; 29595let DecoderNamespace = "EXT_mmvec"; 29596} 29597def V6_vaddhsat_dv : HInst< 29598(outs HvxWR:$Vdd32), 29599(ins HvxWR:$Vuu32, HvxWR:$Vvv32), 29600"$Vdd32.h = vadd($Vuu32.h,$Vvv32.h):sat", 29601tc_db5555f3, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> { 29602let Inst{7-5} = 0b001; 29603let Inst{13-13} = 0b0; 29604let Inst{31-21} = 0b00011100100; 29605let hasNewValue = 1; 29606let opNewValue = 0; 29607let DecoderNamespace = "EXT_mmvec"; 29608} 29609def V6_vaddhsat_dv_alt : HInst< 29610(outs HvxWR:$Vdd32), 29611(ins HvxWR:$Vuu32, HvxWR:$Vvv32), 29612"$Vdd32 = vaddh($Vuu32,$Vvv32):sat", 29613PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 29614let hasNewValue = 1; 29615let opNewValue = 0; 29616let isPseudo = 1; 29617let isCodeGenOnly = 1; 29618let DecoderNamespace = "EXT_mmvec"; 29619} 29620def V6_vaddhw : HInst< 29621(outs HvxWR:$Vdd32), 29622(ins HvxVR:$Vu32, HvxVR:$Vv32), 29623"$Vdd32.w = vadd($Vu32.h,$Vv32.h)", 29624tc_d8287c14, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV60]> { 29625let Inst{7-5} = 0b100; 29626let Inst{13-13} = 0b0; 29627let Inst{31-21} = 0b00011100101; 29628let hasNewValue = 1; 29629let opNewValue = 0; 29630let DecoderNamespace = "EXT_mmvec"; 29631} 29632def V6_vaddhw_acc : HInst< 29633(outs HvxWR:$Vxx32), 29634(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32), 29635"$Vxx32.w += vadd($Vu32.h,$Vv32.h)", 29636tc_08a4f1b6, TypeCVI_VX_DV>, Enc_3fc427, Requires<[UseHVXV62]> { 29637let Inst{7-5} = 0b010; 29638let Inst{13-13} = 0b1; 29639let Inst{31-21} = 0b00011100001; 29640let hasNewValue = 1; 29641let opNewValue = 0; 29642let isAccumulator = 1; 29643let DecoderNamespace = "EXT_mmvec"; 29644let Constraints = "$Vxx32 = $Vxx32in"; 29645} 29646def V6_vaddhw_acc_alt : HInst< 29647(outs HvxWR:$Vxx32), 29648(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32), 29649"$Vxx32 += vaddh($Vu32,$Vv32)", 29650PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> { 29651let hasNewValue = 1; 29652let opNewValue = 0; 29653let isAccumulator = 1; 29654let isPseudo = 1; 29655let isCodeGenOnly = 1; 29656let DecoderNamespace = "EXT_mmvec"; 29657let Constraints = "$Vxx32 = $Vxx32in"; 29658} 29659def V6_vaddhw_alt : HInst< 29660(outs HvxWR:$Vdd32), 29661(ins HvxVR:$Vu32, HvxVR:$Vv32), 29662"$Vdd32 = vaddh($Vu32,$Vv32)", 29663PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 29664let hasNewValue = 1; 29665let opNewValue = 0; 29666let isPseudo = 1; 29667let isCodeGenOnly = 1; 29668let DecoderNamespace = "EXT_mmvec"; 29669} 29670def V6_vaddubh : HInst< 29671(outs HvxWR:$Vdd32), 29672(ins HvxVR:$Vu32, HvxVR:$Vv32), 29673"$Vdd32.h = vadd($Vu32.ub,$Vv32.ub)", 29674tc_d8287c14, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV60]> { 29675let Inst{7-5} = 0b010; 29676let Inst{13-13} = 0b0; 29677let Inst{31-21} = 0b00011100101; 29678let hasNewValue = 1; 29679let opNewValue = 0; 29680let DecoderNamespace = "EXT_mmvec"; 29681} 29682def V6_vaddubh_acc : HInst< 29683(outs HvxWR:$Vxx32), 29684(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32), 29685"$Vxx32.h += vadd($Vu32.ub,$Vv32.ub)", 29686tc_08a4f1b6, TypeCVI_VX_DV>, Enc_3fc427, Requires<[UseHVXV62]> { 29687let Inst{7-5} = 0b101; 29688let Inst{13-13} = 0b1; 29689let Inst{31-21} = 0b00011100010; 29690let hasNewValue = 1; 29691let opNewValue = 0; 29692let isAccumulator = 1; 29693let DecoderNamespace = "EXT_mmvec"; 29694let Constraints = "$Vxx32 = $Vxx32in"; 29695} 29696def V6_vaddubh_acc_alt : HInst< 29697(outs HvxWR:$Vxx32), 29698(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32), 29699"$Vxx32 += vaddub($Vu32,$Vv32)", 29700PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> { 29701let hasNewValue = 1; 29702let opNewValue = 0; 29703let isAccumulator = 1; 29704let isPseudo = 1; 29705let isCodeGenOnly = 1; 29706let DecoderNamespace = "EXT_mmvec"; 29707let Constraints = "$Vxx32 = $Vxx32in"; 29708} 29709def V6_vaddubh_alt : HInst< 29710(outs HvxWR:$Vdd32), 29711(ins HvxVR:$Vu32, HvxVR:$Vv32), 29712"$Vdd32 = vaddub($Vu32,$Vv32)", 29713PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 29714let hasNewValue = 1; 29715let opNewValue = 0; 29716let isPseudo = 1; 29717let isCodeGenOnly = 1; 29718let DecoderNamespace = "EXT_mmvec"; 29719} 29720def V6_vaddubsat : HInst< 29721(outs HvxVR:$Vd32), 29722(ins HvxVR:$Vu32, HvxVR:$Vv32), 29723"$Vd32.ub = vadd($Vu32.ub,$Vv32.ub):sat", 29724tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> { 29725let Inst{7-5} = 0b001; 29726let Inst{13-13} = 0b0; 29727let Inst{31-21} = 0b00011100010; 29728let hasNewValue = 1; 29729let opNewValue = 0; 29730let DecoderNamespace = "EXT_mmvec"; 29731} 29732def V6_vaddubsat_alt : HInst< 29733(outs HvxVR:$Vd32), 29734(ins HvxVR:$Vu32, HvxVR:$Vv32), 29735"$Vd32 = vaddub($Vu32,$Vv32):sat", 29736PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 29737let hasNewValue = 1; 29738let opNewValue = 0; 29739let isPseudo = 1; 29740let isCodeGenOnly = 1; 29741let DecoderNamespace = "EXT_mmvec"; 29742} 29743def V6_vaddubsat_dv : HInst< 29744(outs HvxWR:$Vdd32), 29745(ins HvxWR:$Vuu32, HvxWR:$Vvv32), 29746"$Vdd32.ub = vadd($Vuu32.ub,$Vvv32.ub):sat", 29747tc_db5555f3, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> { 29748let Inst{7-5} = 0b111; 29749let Inst{13-13} = 0b0; 29750let Inst{31-21} = 0b00011100011; 29751let hasNewValue = 1; 29752let opNewValue = 0; 29753let DecoderNamespace = "EXT_mmvec"; 29754} 29755def V6_vaddubsat_dv_alt : HInst< 29756(outs HvxWR:$Vdd32), 29757(ins HvxWR:$Vuu32, HvxWR:$Vvv32), 29758"$Vdd32 = vaddub($Vuu32,$Vvv32):sat", 29759PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 29760let hasNewValue = 1; 29761let opNewValue = 0; 29762let isPseudo = 1; 29763let isCodeGenOnly = 1; 29764let DecoderNamespace = "EXT_mmvec"; 29765} 29766def V6_vaddububb_sat : HInst< 29767(outs HvxVR:$Vd32), 29768(ins HvxVR:$Vu32, HvxVR:$Vv32), 29769"$Vd32.ub = vadd($Vu32.ub,$Vv32.b):sat", 29770tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV62]> { 29771let Inst{7-5} = 0b100; 29772let Inst{13-13} = 0b0; 29773let Inst{31-21} = 0b00011110101; 29774let hasNewValue = 1; 29775let opNewValue = 0; 29776let DecoderNamespace = "EXT_mmvec"; 29777} 29778def V6_vadduhsat : HInst< 29779(outs HvxVR:$Vd32), 29780(ins HvxVR:$Vu32, HvxVR:$Vv32), 29781"$Vd32.uh = vadd($Vu32.uh,$Vv32.uh):sat", 29782tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> { 29783let Inst{7-5} = 0b010; 29784let Inst{13-13} = 0b0; 29785let Inst{31-21} = 0b00011100010; 29786let hasNewValue = 1; 29787let opNewValue = 0; 29788let DecoderNamespace = "EXT_mmvec"; 29789} 29790def V6_vadduhsat_alt : HInst< 29791(outs HvxVR:$Vd32), 29792(ins HvxVR:$Vu32, HvxVR:$Vv32), 29793"$Vd32 = vadduh($Vu32,$Vv32):sat", 29794PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 29795let hasNewValue = 1; 29796let opNewValue = 0; 29797let isPseudo = 1; 29798let isCodeGenOnly = 1; 29799let DecoderNamespace = "EXT_mmvec"; 29800} 29801def V6_vadduhsat_dv : HInst< 29802(outs HvxWR:$Vdd32), 29803(ins HvxWR:$Vuu32, HvxWR:$Vvv32), 29804"$Vdd32.uh = vadd($Vuu32.uh,$Vvv32.uh):sat", 29805tc_db5555f3, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> { 29806let Inst{7-5} = 0b000; 29807let Inst{13-13} = 0b0; 29808let Inst{31-21} = 0b00011100100; 29809let hasNewValue = 1; 29810let opNewValue = 0; 29811let DecoderNamespace = "EXT_mmvec"; 29812} 29813def V6_vadduhsat_dv_alt : HInst< 29814(outs HvxWR:$Vdd32), 29815(ins HvxWR:$Vuu32, HvxWR:$Vvv32), 29816"$Vdd32 = vadduh($Vuu32,$Vvv32):sat", 29817PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 29818let hasNewValue = 1; 29819let opNewValue = 0; 29820let isPseudo = 1; 29821let isCodeGenOnly = 1; 29822let DecoderNamespace = "EXT_mmvec"; 29823} 29824def V6_vadduhw : HInst< 29825(outs HvxWR:$Vdd32), 29826(ins HvxVR:$Vu32, HvxVR:$Vv32), 29827"$Vdd32.w = vadd($Vu32.uh,$Vv32.uh)", 29828tc_d8287c14, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV60]> { 29829let Inst{7-5} = 0b011; 29830let Inst{13-13} = 0b0; 29831let Inst{31-21} = 0b00011100101; 29832let hasNewValue = 1; 29833let opNewValue = 0; 29834let DecoderNamespace = "EXT_mmvec"; 29835} 29836def V6_vadduhw_acc : HInst< 29837(outs HvxWR:$Vxx32), 29838(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32), 29839"$Vxx32.w += vadd($Vu32.uh,$Vv32.uh)", 29840tc_08a4f1b6, TypeCVI_VX_DV>, Enc_3fc427, Requires<[UseHVXV62]> { 29841let Inst{7-5} = 0b100; 29842let Inst{13-13} = 0b1; 29843let Inst{31-21} = 0b00011100010; 29844let hasNewValue = 1; 29845let opNewValue = 0; 29846let isAccumulator = 1; 29847let DecoderNamespace = "EXT_mmvec"; 29848let Constraints = "$Vxx32 = $Vxx32in"; 29849} 29850def V6_vadduhw_acc_alt : HInst< 29851(outs HvxWR:$Vxx32), 29852(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32), 29853"$Vxx32 += vadduh($Vu32,$Vv32)", 29854PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> { 29855let hasNewValue = 1; 29856let opNewValue = 0; 29857let isAccumulator = 1; 29858let isPseudo = 1; 29859let isCodeGenOnly = 1; 29860let DecoderNamespace = "EXT_mmvec"; 29861let Constraints = "$Vxx32 = $Vxx32in"; 29862} 29863def V6_vadduhw_alt : HInst< 29864(outs HvxWR:$Vdd32), 29865(ins HvxVR:$Vu32, HvxVR:$Vv32), 29866"$Vdd32 = vadduh($Vu32,$Vv32)", 29867PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 29868let hasNewValue = 1; 29869let opNewValue = 0; 29870let isPseudo = 1; 29871let isCodeGenOnly = 1; 29872let DecoderNamespace = "EXT_mmvec"; 29873} 29874def V6_vadduwsat : HInst< 29875(outs HvxVR:$Vd32), 29876(ins HvxVR:$Vu32, HvxVR:$Vv32), 29877"$Vd32.uw = vadd($Vu32.uw,$Vv32.uw):sat", 29878tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV62]> { 29879let Inst{7-5} = 0b001; 29880let Inst{13-13} = 0b0; 29881let Inst{31-21} = 0b00011111011; 29882let hasNewValue = 1; 29883let opNewValue = 0; 29884let DecoderNamespace = "EXT_mmvec"; 29885} 29886def V6_vadduwsat_alt : HInst< 29887(outs HvxVR:$Vd32), 29888(ins HvxVR:$Vu32, HvxVR:$Vv32), 29889"$Vd32 = vadduw($Vu32,$Vv32):sat", 29890PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> { 29891let hasNewValue = 1; 29892let opNewValue = 0; 29893let isPseudo = 1; 29894let isCodeGenOnly = 1; 29895let DecoderNamespace = "EXT_mmvec"; 29896} 29897def V6_vadduwsat_dv : HInst< 29898(outs HvxWR:$Vdd32), 29899(ins HvxWR:$Vuu32, HvxWR:$Vvv32), 29900"$Vdd32.uw = vadd($Vuu32.uw,$Vvv32.uw):sat", 29901tc_db5555f3, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV62]> { 29902let Inst{7-5} = 0b010; 29903let Inst{13-13} = 0b0; 29904let Inst{31-21} = 0b00011110101; 29905let hasNewValue = 1; 29906let opNewValue = 0; 29907let DecoderNamespace = "EXT_mmvec"; 29908} 29909def V6_vadduwsat_dv_alt : HInst< 29910(outs HvxWR:$Vdd32), 29911(ins HvxWR:$Vuu32, HvxWR:$Vvv32), 29912"$Vdd32 = vadduw($Vuu32,$Vvv32):sat", 29913PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> { 29914let hasNewValue = 1; 29915let opNewValue = 0; 29916let isPseudo = 1; 29917let isCodeGenOnly = 1; 29918let DecoderNamespace = "EXT_mmvec"; 29919} 29920def V6_vaddw : HInst< 29921(outs HvxVR:$Vd32), 29922(ins HvxVR:$Vu32, HvxVR:$Vv32), 29923"$Vd32.w = vadd($Vu32.w,$Vv32.w)", 29924tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> { 29925let Inst{7-5} = 0b000; 29926let Inst{13-13} = 0b0; 29927let Inst{31-21} = 0b00011100010; 29928let hasNewValue = 1; 29929let opNewValue = 0; 29930let DecoderNamespace = "EXT_mmvec"; 29931} 29932def V6_vaddw_alt : HInst< 29933(outs HvxVR:$Vd32), 29934(ins HvxVR:$Vu32, HvxVR:$Vv32), 29935"$Vd32 = vaddw($Vu32,$Vv32)", 29936PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 29937let hasNewValue = 1; 29938let opNewValue = 0; 29939let isPseudo = 1; 29940let isCodeGenOnly = 1; 29941let DecoderNamespace = "EXT_mmvec"; 29942} 29943def V6_vaddw_dv : HInst< 29944(outs HvxWR:$Vdd32), 29945(ins HvxWR:$Vuu32, HvxWR:$Vvv32), 29946"$Vdd32.w = vadd($Vuu32.w,$Vvv32.w)", 29947tc_db5555f3, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> { 29948let Inst{7-5} = 0b110; 29949let Inst{13-13} = 0b0; 29950let Inst{31-21} = 0b00011100011; 29951let hasNewValue = 1; 29952let opNewValue = 0; 29953let DecoderNamespace = "EXT_mmvec"; 29954} 29955def V6_vaddw_dv_alt : HInst< 29956(outs HvxWR:$Vdd32), 29957(ins HvxWR:$Vuu32, HvxWR:$Vvv32), 29958"$Vdd32 = vaddw($Vuu32,$Vvv32)", 29959PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 29960let hasNewValue = 1; 29961let opNewValue = 0; 29962let isPseudo = 1; 29963let isCodeGenOnly = 1; 29964let DecoderNamespace = "EXT_mmvec"; 29965} 29966def V6_vaddwnq : HInst< 29967(outs HvxVR:$Vx32), 29968(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32), 29969"if (!$Qv4) $Vx32.w += $Vu32.w", 29970tc_257f6f7c, TypeCVI_VA>, Enc_a90628, Requires<[UseHVXV60]> { 29971let Inst{7-5} = 0b101; 29972let Inst{13-13} = 0b1; 29973let Inst{21-16} = 0b000001; 29974let Inst{31-24} = 0b00011110; 29975let hasNewValue = 1; 29976let opNewValue = 0; 29977let isAccumulator = 1; 29978let DecoderNamespace = "EXT_mmvec"; 29979let Constraints = "$Vx32 = $Vx32in"; 29980} 29981def V6_vaddwnq_alt : HInst< 29982(outs HvxVR:$Vx32), 29983(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32), 29984"if (!$Qv4.w) $Vx32.w += $Vu32.w", 29985PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 29986let hasNewValue = 1; 29987let opNewValue = 0; 29988let isAccumulator = 1; 29989let isPseudo = 1; 29990let isCodeGenOnly = 1; 29991let DecoderNamespace = "EXT_mmvec"; 29992let Constraints = "$Vx32 = $Vx32in"; 29993} 29994def V6_vaddwq : HInst< 29995(outs HvxVR:$Vx32), 29996(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32), 29997"if ($Qv4) $Vx32.w += $Vu32.w", 29998tc_257f6f7c, TypeCVI_VA>, Enc_a90628, Requires<[UseHVXV60]> { 29999let Inst{7-5} = 0b010; 30000let Inst{13-13} = 0b1; 30001let Inst{21-16} = 0b000001; 30002let Inst{31-24} = 0b00011110; 30003let hasNewValue = 1; 30004let opNewValue = 0; 30005let isAccumulator = 1; 30006let DecoderNamespace = "EXT_mmvec"; 30007let Constraints = "$Vx32 = $Vx32in"; 30008} 30009def V6_vaddwq_alt : HInst< 30010(outs HvxVR:$Vx32), 30011(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32), 30012"if ($Qv4.w) $Vx32.w += $Vu32.w", 30013PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 30014let hasNewValue = 1; 30015let opNewValue = 0; 30016let isAccumulator = 1; 30017let isPseudo = 1; 30018let isCodeGenOnly = 1; 30019let DecoderNamespace = "EXT_mmvec"; 30020let Constraints = "$Vx32 = $Vx32in"; 30021} 30022def V6_vaddwsat : HInst< 30023(outs HvxVR:$Vd32), 30024(ins HvxVR:$Vu32, HvxVR:$Vv32), 30025"$Vd32.w = vadd($Vu32.w,$Vv32.w):sat", 30026tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> { 30027let Inst{7-5} = 0b100; 30028let Inst{13-13} = 0b0; 30029let Inst{31-21} = 0b00011100010; 30030let hasNewValue = 1; 30031let opNewValue = 0; 30032let DecoderNamespace = "EXT_mmvec"; 30033} 30034def V6_vaddwsat_alt : HInst< 30035(outs HvxVR:$Vd32), 30036(ins HvxVR:$Vu32, HvxVR:$Vv32), 30037"$Vd32 = vaddw($Vu32,$Vv32):sat", 30038PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 30039let hasNewValue = 1; 30040let opNewValue = 0; 30041let isPseudo = 1; 30042let isCodeGenOnly = 1; 30043let DecoderNamespace = "EXT_mmvec"; 30044} 30045def V6_vaddwsat_dv : HInst< 30046(outs HvxWR:$Vdd32), 30047(ins HvxWR:$Vuu32, HvxWR:$Vvv32), 30048"$Vdd32.w = vadd($Vuu32.w,$Vvv32.w):sat", 30049tc_db5555f3, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> { 30050let Inst{7-5} = 0b010; 30051let Inst{13-13} = 0b0; 30052let Inst{31-21} = 0b00011100100; 30053let hasNewValue = 1; 30054let opNewValue = 0; 30055let DecoderNamespace = "EXT_mmvec"; 30056} 30057def V6_vaddwsat_dv_alt : HInst< 30058(outs HvxWR:$Vdd32), 30059(ins HvxWR:$Vuu32, HvxWR:$Vvv32), 30060"$Vdd32 = vaddw($Vuu32,$Vvv32):sat", 30061PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 30062let hasNewValue = 1; 30063let opNewValue = 0; 30064let isPseudo = 1; 30065let isCodeGenOnly = 1; 30066let DecoderNamespace = "EXT_mmvec"; 30067} 30068def V6_valignb : HInst< 30069(outs HvxVR:$Vd32), 30070(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8), 30071"$Vd32 = valign($Vu32,$Vv32,$Rt8)", 30072tc_56e64202, TypeCVI_VP>, Enc_a30110, Requires<[UseHVXV60]> { 30073let Inst{7-5} = 0b000; 30074let Inst{13-13} = 0b0; 30075let Inst{31-24} = 0b00011011; 30076let hasNewValue = 1; 30077let opNewValue = 0; 30078let DecoderNamespace = "EXT_mmvec"; 30079} 30080def V6_valignbi : HInst< 30081(outs HvxVR:$Vd32), 30082(ins HvxVR:$Vu32, HvxVR:$Vv32, u3_0Imm:$Ii), 30083"$Vd32 = valign($Vu32,$Vv32,#$Ii)", 30084tc_56e64202, TypeCVI_VP>, Enc_0b2e5b, Requires<[UseHVXV60]> { 30085let Inst{13-13} = 0b1; 30086let Inst{31-21} = 0b00011110001; 30087let hasNewValue = 1; 30088let opNewValue = 0; 30089let DecoderNamespace = "EXT_mmvec"; 30090} 30091def V6_vand : HInst< 30092(outs HvxVR:$Vd32), 30093(ins HvxVR:$Vu32, HvxVR:$Vv32), 30094"$Vd32 = vand($Vu32,$Vv32)", 30095tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> { 30096let Inst{7-5} = 0b101; 30097let Inst{13-13} = 0b0; 30098let Inst{31-21} = 0b00011100001; 30099let hasNewValue = 1; 30100let opNewValue = 0; 30101let DecoderNamespace = "EXT_mmvec"; 30102} 30103def V6_vandnqrt : HInst< 30104(outs HvxVR:$Vd32), 30105(ins HvxQR:$Qu4, IntRegs:$Rt32), 30106"$Vd32 = vand(!$Qu4,$Rt32)", 30107tc_ac4046bc, TypeCVI_VX>, Enc_7b7ba8, Requires<[UseHVXV62]> { 30108let Inst{7-5} = 0b101; 30109let Inst{13-10} = 0b0001; 30110let Inst{31-21} = 0b00011001101; 30111let hasNewValue = 1; 30112let opNewValue = 0; 30113let DecoderNamespace = "EXT_mmvec"; 30114} 30115def V6_vandnqrt_acc : HInst< 30116(outs HvxVR:$Vx32), 30117(ins HvxVR:$Vx32in, HvxQR:$Qu4, IntRegs:$Rt32), 30118"$Vx32 |= vand(!$Qu4,$Rt32)", 30119tc_2e8f5f6e, TypeCVI_VX>, Enc_895bd9, Requires<[UseHVXV62]> { 30120let Inst{7-5} = 0b011; 30121let Inst{13-10} = 0b1001; 30122let Inst{31-21} = 0b00011001011; 30123let hasNewValue = 1; 30124let opNewValue = 0; 30125let isAccumulator = 1; 30126let DecoderNamespace = "EXT_mmvec"; 30127let Constraints = "$Vx32 = $Vx32in"; 30128} 30129def V6_vandnqrt_acc_alt : HInst< 30130(outs HvxVR:$Vx32), 30131(ins HvxVR:$Vx32in, HvxQR:$Qu4, IntRegs:$Rt32), 30132"$Vx32.ub |= vand(!$Qu4.ub,$Rt32.ub)", 30133PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> { 30134let hasNewValue = 1; 30135let opNewValue = 0; 30136let isAccumulator = 1; 30137let isPseudo = 1; 30138let isCodeGenOnly = 1; 30139let DecoderNamespace = "EXT_mmvec"; 30140let Constraints = "$Vx32 = $Vx32in"; 30141} 30142def V6_vandnqrt_alt : HInst< 30143(outs HvxVR:$Vd32), 30144(ins HvxQR:$Qu4, IntRegs:$Rt32), 30145"$Vd32.ub = vand(!$Qu4.ub,$Rt32.ub)", 30146PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> { 30147let hasNewValue = 1; 30148let opNewValue = 0; 30149let isPseudo = 1; 30150let isCodeGenOnly = 1; 30151let DecoderNamespace = "EXT_mmvec"; 30152} 30153def V6_vandqrt : HInst< 30154(outs HvxVR:$Vd32), 30155(ins HvxQR:$Qu4, IntRegs:$Rt32), 30156"$Vd32 = vand($Qu4,$Rt32)", 30157tc_ac4046bc, TypeCVI_VX_LATE>, Enc_7b7ba8, Requires<[UseHVXV60]> { 30158let Inst{7-5} = 0b101; 30159let Inst{13-10} = 0b0000; 30160let Inst{31-21} = 0b00011001101; 30161let hasNewValue = 1; 30162let opNewValue = 0; 30163let DecoderNamespace = "EXT_mmvec"; 30164} 30165def V6_vandqrt_acc : HInst< 30166(outs HvxVR:$Vx32), 30167(ins HvxVR:$Vx32in, HvxQR:$Qu4, IntRegs:$Rt32), 30168"$Vx32 |= vand($Qu4,$Rt32)", 30169tc_2e8f5f6e, TypeCVI_VX_LATE>, Enc_895bd9, Requires<[UseHVXV60]> { 30170let Inst{7-5} = 0b011; 30171let Inst{13-10} = 0b1000; 30172let Inst{31-21} = 0b00011001011; 30173let hasNewValue = 1; 30174let opNewValue = 0; 30175let isAccumulator = 1; 30176let DecoderNamespace = "EXT_mmvec"; 30177let Constraints = "$Vx32 = $Vx32in"; 30178} 30179def V6_vandqrt_acc_alt : HInst< 30180(outs HvxVR:$Vx32), 30181(ins HvxVR:$Vx32in, HvxQR:$Qu4, IntRegs:$Rt32), 30182"$Vx32.ub |= vand($Qu4.ub,$Rt32.ub)", 30183PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 30184let hasNewValue = 1; 30185let opNewValue = 0; 30186let isAccumulator = 1; 30187let isPseudo = 1; 30188let isCodeGenOnly = 1; 30189let DecoderNamespace = "EXT_mmvec"; 30190let Constraints = "$Vx32 = $Vx32in"; 30191} 30192def V6_vandqrt_alt : HInst< 30193(outs HvxVR:$Vd32), 30194(ins HvxQR:$Qu4, IntRegs:$Rt32), 30195"$Vd32.ub = vand($Qu4.ub,$Rt32.ub)", 30196PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 30197let hasNewValue = 1; 30198let opNewValue = 0; 30199let isPseudo = 1; 30200let isCodeGenOnly = 1; 30201let DecoderNamespace = "EXT_mmvec"; 30202} 30203def V6_vandvnqv : HInst< 30204(outs HvxVR:$Vd32), 30205(ins HvxQR:$Qv4, HvxVR:$Vu32), 30206"$Vd32 = vand(!$Qv4,$Vu32)", 30207tc_56c4f9fe, TypeCVI_VA>, Enc_c4dc92, Requires<[UseHVXV62]> { 30208let Inst{7-5} = 0b001; 30209let Inst{13-13} = 0b1; 30210let Inst{21-16} = 0b000011; 30211let Inst{31-24} = 0b00011110; 30212let hasNewValue = 1; 30213let opNewValue = 0; 30214let DecoderNamespace = "EXT_mmvec"; 30215} 30216def V6_vandvqv : HInst< 30217(outs HvxVR:$Vd32), 30218(ins HvxQR:$Qv4, HvxVR:$Vu32), 30219"$Vd32 = vand($Qv4,$Vu32)", 30220tc_56c4f9fe, TypeCVI_VA>, Enc_c4dc92, Requires<[UseHVXV62]> { 30221let Inst{7-5} = 0b000; 30222let Inst{13-13} = 0b1; 30223let Inst{21-16} = 0b000011; 30224let Inst{31-24} = 0b00011110; 30225let hasNewValue = 1; 30226let opNewValue = 0; 30227let DecoderNamespace = "EXT_mmvec"; 30228} 30229def V6_vandvrt : HInst< 30230(outs HvxQR:$Qd4), 30231(ins HvxVR:$Vu32, IntRegs:$Rt32), 30232"$Qd4 = vand($Vu32,$Rt32)", 30233tc_ac4046bc, TypeCVI_VX_LATE>, Enc_0f8bab, Requires<[UseHVXV60]> { 30234let Inst{7-2} = 0b010010; 30235let Inst{13-13} = 0b0; 30236let Inst{31-21} = 0b00011001101; 30237let hasNewValue = 1; 30238let opNewValue = 0; 30239let DecoderNamespace = "EXT_mmvec"; 30240} 30241def V6_vandvrt_acc : HInst< 30242(outs HvxQR:$Qx4), 30243(ins HvxQR:$Qx4in, HvxVR:$Vu32, IntRegs:$Rt32), 30244"$Qx4 |= vand($Vu32,$Rt32)", 30245tc_2e8f5f6e, TypeCVI_VX_LATE>, Enc_adf111, Requires<[UseHVXV60]> { 30246let Inst{7-2} = 0b100000; 30247let Inst{13-13} = 0b1; 30248let Inst{31-21} = 0b00011001011; 30249let isAccumulator = 1; 30250let DecoderNamespace = "EXT_mmvec"; 30251let Constraints = "$Qx4 = $Qx4in"; 30252} 30253def V6_vandvrt_acc_alt : HInst< 30254(outs HvxQR:$Qx4), 30255(ins HvxQR:$Qx4in, HvxVR:$Vu32, IntRegs:$Rt32), 30256"$Qx4.ub |= vand($Vu32.ub,$Rt32.ub)", 30257PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 30258let isAccumulator = 1; 30259let isPseudo = 1; 30260let isCodeGenOnly = 1; 30261let DecoderNamespace = "EXT_mmvec"; 30262let Constraints = "$Qx4 = $Qx4in"; 30263} 30264def V6_vandvrt_alt : HInst< 30265(outs HvxQR:$Qd4), 30266(ins HvxVR:$Vu32, IntRegs:$Rt32), 30267"$Qd4.ub = vand($Vu32.ub,$Rt32.ub)", 30268PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 30269let hasNewValue = 1; 30270let opNewValue = 0; 30271let isPseudo = 1; 30272let isCodeGenOnly = 1; 30273let DecoderNamespace = "EXT_mmvec"; 30274} 30275def V6_vaslh : HInst< 30276(outs HvxVR:$Vd32), 30277(ins HvxVR:$Vu32, IntRegs:$Rt32), 30278"$Vd32.h = vasl($Vu32.h,$Rt32)", 30279tc_7417e785, TypeCVI_VS>, Enc_b087ac, Requires<[UseHVXV60]> { 30280let Inst{7-5} = 0b000; 30281let Inst{13-13} = 0b0; 30282let Inst{31-21} = 0b00011001100; 30283let hasNewValue = 1; 30284let opNewValue = 0; 30285let DecoderNamespace = "EXT_mmvec"; 30286} 30287def V6_vaslh_acc : HInst< 30288(outs HvxVR:$Vx32), 30289(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32), 30290"$Vx32.h += vasl($Vu32.h,$Rt32)", 30291tc_309dbb4f, TypeCVI_VS>, Enc_5138b3, Requires<[UseHVXV65]> { 30292let Inst{7-5} = 0b101; 30293let Inst{13-13} = 0b1; 30294let Inst{31-21} = 0b00011001101; 30295let hasNewValue = 1; 30296let opNewValue = 0; 30297let isAccumulator = 1; 30298let DecoderNamespace = "EXT_mmvec"; 30299let Constraints = "$Vx32 = $Vx32in"; 30300} 30301def V6_vaslh_acc_alt : HInst< 30302(outs HvxVR:$Vx32), 30303(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32), 30304"$Vx32 += vaslh($Vu32,$Rt32)", 30305PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> { 30306let hasNewValue = 1; 30307let opNewValue = 0; 30308let isAccumulator = 1; 30309let isPseudo = 1; 30310let isCodeGenOnly = 1; 30311let DecoderNamespace = "EXT_mmvec"; 30312let Constraints = "$Vx32 = $Vx32in"; 30313} 30314def V6_vaslh_alt : HInst< 30315(outs HvxVR:$Vd32), 30316(ins HvxVR:$Vu32, IntRegs:$Rt32), 30317"$Vd32 = vaslh($Vu32,$Rt32)", 30318PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 30319let hasNewValue = 1; 30320let opNewValue = 0; 30321let isPseudo = 1; 30322let isCodeGenOnly = 1; 30323let DecoderNamespace = "EXT_mmvec"; 30324} 30325def V6_vaslhv : HInst< 30326(outs HvxVR:$Vd32), 30327(ins HvxVR:$Vu32, HvxVR:$Vv32), 30328"$Vd32.h = vasl($Vu32.h,$Vv32.h)", 30329tc_05ca8cfd, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV60]> { 30330let Inst{7-5} = 0b101; 30331let Inst{13-13} = 0b0; 30332let Inst{31-21} = 0b00011111101; 30333let hasNewValue = 1; 30334let opNewValue = 0; 30335let DecoderNamespace = "EXT_mmvec"; 30336} 30337def V6_vaslhv_alt : HInst< 30338(outs HvxVR:$Vd32), 30339(ins HvxVR:$Vu32, HvxVR:$Vv32), 30340"$Vd32 = vaslh($Vu32,$Vv32)", 30341PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 30342let hasNewValue = 1; 30343let opNewValue = 0; 30344let isPseudo = 1; 30345let isCodeGenOnly = 1; 30346let DecoderNamespace = "EXT_mmvec"; 30347} 30348def V6_vaslw : HInst< 30349(outs HvxVR:$Vd32), 30350(ins HvxVR:$Vu32, IntRegs:$Rt32), 30351"$Vd32.w = vasl($Vu32.w,$Rt32)", 30352tc_7417e785, TypeCVI_VS>, Enc_b087ac, Requires<[UseHVXV60]> { 30353let Inst{7-5} = 0b111; 30354let Inst{13-13} = 0b0; 30355let Inst{31-21} = 0b00011001011; 30356let hasNewValue = 1; 30357let opNewValue = 0; 30358let DecoderNamespace = "EXT_mmvec"; 30359} 30360def V6_vaslw_acc : HInst< 30361(outs HvxVR:$Vx32), 30362(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32), 30363"$Vx32.w += vasl($Vu32.w,$Rt32)", 30364tc_309dbb4f, TypeCVI_VS>, Enc_5138b3, Requires<[UseHVXV60]> { 30365let Inst{7-5} = 0b010; 30366let Inst{13-13} = 0b1; 30367let Inst{31-21} = 0b00011001011; 30368let hasNewValue = 1; 30369let opNewValue = 0; 30370let isAccumulator = 1; 30371let DecoderNamespace = "EXT_mmvec"; 30372let Constraints = "$Vx32 = $Vx32in"; 30373} 30374def V6_vaslw_acc_alt : HInst< 30375(outs HvxVR:$Vx32), 30376(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32), 30377"$Vx32 += vaslw($Vu32,$Rt32)", 30378PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 30379let hasNewValue = 1; 30380let opNewValue = 0; 30381let isAccumulator = 1; 30382let isPseudo = 1; 30383let isCodeGenOnly = 1; 30384let DecoderNamespace = "EXT_mmvec"; 30385let Constraints = "$Vx32 = $Vx32in"; 30386} 30387def V6_vaslw_alt : HInst< 30388(outs HvxVR:$Vd32), 30389(ins HvxVR:$Vu32, IntRegs:$Rt32), 30390"$Vd32 = vaslw($Vu32,$Rt32)", 30391PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 30392let hasNewValue = 1; 30393let opNewValue = 0; 30394let isPseudo = 1; 30395let isCodeGenOnly = 1; 30396let DecoderNamespace = "EXT_mmvec"; 30397} 30398def V6_vaslwv : HInst< 30399(outs HvxVR:$Vd32), 30400(ins HvxVR:$Vu32, HvxVR:$Vv32), 30401"$Vd32.w = vasl($Vu32.w,$Vv32.w)", 30402tc_05ca8cfd, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV60]> { 30403let Inst{7-5} = 0b100; 30404let Inst{13-13} = 0b0; 30405let Inst{31-21} = 0b00011111101; 30406let hasNewValue = 1; 30407let opNewValue = 0; 30408let DecoderNamespace = "EXT_mmvec"; 30409} 30410def V6_vaslwv_alt : HInst< 30411(outs HvxVR:$Vd32), 30412(ins HvxVR:$Vu32, HvxVR:$Vv32), 30413"$Vd32 = vaslw($Vu32,$Vv32)", 30414PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 30415let hasNewValue = 1; 30416let opNewValue = 0; 30417let isPseudo = 1; 30418let isCodeGenOnly = 1; 30419let DecoderNamespace = "EXT_mmvec"; 30420} 30421def V6_vasr_into : HInst< 30422(outs HvxWR:$Vxx32), 30423(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32), 30424"$Vxx32.w = vasrinto($Vu32.w,$Vv32.w)", 30425tc_df80eeb0, TypeCVI_VP_VS>, Enc_3fc427, Requires<[UseHVXV66]> { 30426let Inst{7-5} = 0b111; 30427let Inst{13-13} = 0b1; 30428let Inst{31-21} = 0b00011010101; 30429let hasNewValue = 1; 30430let opNewValue = 0; 30431let DecoderNamespace = "EXT_mmvec"; 30432let Constraints = "$Vxx32 = $Vxx32in"; 30433} 30434def V6_vasr_into_alt : HInst< 30435(outs HvxWR:$Vxx32), 30436(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32), 30437"$Vxx32 = vasrinto($Vu32,$Vv32)", 30438PSEUDO, TypeMAPPING>, Requires<[UseHVXV66]> { 30439let hasNewValue = 1; 30440let opNewValue = 0; 30441let isPseudo = 1; 30442let isCodeGenOnly = 1; 30443let DecoderNamespace = "EXT_mmvec"; 30444let Constraints = "$Vxx32 = $Vxx32in"; 30445} 30446def V6_vasrh : HInst< 30447(outs HvxVR:$Vd32), 30448(ins HvxVR:$Vu32, IntRegs:$Rt32), 30449"$Vd32.h = vasr($Vu32.h,$Rt32)", 30450tc_7417e785, TypeCVI_VS>, Enc_b087ac, Requires<[UseHVXV60]> { 30451let Inst{7-5} = 0b110; 30452let Inst{13-13} = 0b0; 30453let Inst{31-21} = 0b00011001011; 30454let hasNewValue = 1; 30455let opNewValue = 0; 30456let DecoderNamespace = "EXT_mmvec"; 30457} 30458def V6_vasrh_acc : HInst< 30459(outs HvxVR:$Vx32), 30460(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32), 30461"$Vx32.h += vasr($Vu32.h,$Rt32)", 30462tc_309dbb4f, TypeCVI_VS>, Enc_5138b3, Requires<[UseHVXV65]> { 30463let Inst{7-5} = 0b111; 30464let Inst{13-13} = 0b1; 30465let Inst{31-21} = 0b00011001100; 30466let hasNewValue = 1; 30467let opNewValue = 0; 30468let isAccumulator = 1; 30469let DecoderNamespace = "EXT_mmvec"; 30470let Constraints = "$Vx32 = $Vx32in"; 30471} 30472def V6_vasrh_acc_alt : HInst< 30473(outs HvxVR:$Vx32), 30474(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32), 30475"$Vx32 += vasrh($Vu32,$Rt32)", 30476PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> { 30477let hasNewValue = 1; 30478let opNewValue = 0; 30479let isAccumulator = 1; 30480let isPseudo = 1; 30481let isCodeGenOnly = 1; 30482let DecoderNamespace = "EXT_mmvec"; 30483let Constraints = "$Vx32 = $Vx32in"; 30484} 30485def V6_vasrh_alt : HInst< 30486(outs HvxVR:$Vd32), 30487(ins HvxVR:$Vu32, IntRegs:$Rt32), 30488"$Vd32 = vasrh($Vu32,$Rt32)", 30489PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 30490let hasNewValue = 1; 30491let opNewValue = 0; 30492let isPseudo = 1; 30493let isCodeGenOnly = 1; 30494let DecoderNamespace = "EXT_mmvec"; 30495} 30496def V6_vasrhbrndsat : HInst< 30497(outs HvxVR:$Vd32), 30498(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8), 30499"$Vd32.b = vasr($Vu32.h,$Vv32.h,$Rt8):rnd:sat", 30500tc_16ff9ef8, TypeCVI_VS>, Enc_a30110, Requires<[UseHVXV60]> { 30501let Inst{7-5} = 0b000; 30502let Inst{13-13} = 0b1; 30503let Inst{31-24} = 0b00011011; 30504let hasNewValue = 1; 30505let opNewValue = 0; 30506let DecoderNamespace = "EXT_mmvec"; 30507} 30508def V6_vasrhbrndsat_alt : HInst< 30509(outs HvxVR:$Vd32), 30510(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8), 30511"$Vd32 = vasrhb($Vu32,$Vv32,$Rt8):rnd:sat", 30512tc_16ff9ef8, TypeMAPPING>, Requires<[HasV60]> { 30513let hasNewValue = 1; 30514let opNewValue = 0; 30515let isPseudo = 1; 30516let isCodeGenOnly = 1; 30517} 30518def V6_vasrhbsat : HInst< 30519(outs HvxVR:$Vd32), 30520(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8), 30521"$Vd32.b = vasr($Vu32.h,$Vv32.h,$Rt8):sat", 30522tc_16ff9ef8, TypeCVI_VS>, Enc_a30110, Requires<[UseHVXV62]> { 30523let Inst{7-5} = 0b000; 30524let Inst{13-13} = 0b0; 30525let Inst{31-24} = 0b00011000; 30526let hasNewValue = 1; 30527let opNewValue = 0; 30528let DecoderNamespace = "EXT_mmvec"; 30529} 30530def V6_vasrhubrndsat : HInst< 30531(outs HvxVR:$Vd32), 30532(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8), 30533"$Vd32.ub = vasr($Vu32.h,$Vv32.h,$Rt8):rnd:sat", 30534tc_16ff9ef8, TypeCVI_VS>, Enc_a30110, Requires<[UseHVXV60]> { 30535let Inst{7-5} = 0b111; 30536let Inst{13-13} = 0b0; 30537let Inst{31-24} = 0b00011011; 30538let hasNewValue = 1; 30539let opNewValue = 0; 30540let DecoderNamespace = "EXT_mmvec"; 30541} 30542def V6_vasrhubrndsat_alt : HInst< 30543(outs HvxVR:$Vd32), 30544(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8), 30545"$Vd32 = vasrhub($Vu32,$Vv32,$Rt8):rnd:sat", 30546tc_16ff9ef8, TypeMAPPING>, Requires<[HasV60]> { 30547let hasNewValue = 1; 30548let opNewValue = 0; 30549let isPseudo = 1; 30550let isCodeGenOnly = 1; 30551} 30552def V6_vasrhubsat : HInst< 30553(outs HvxVR:$Vd32), 30554(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8), 30555"$Vd32.ub = vasr($Vu32.h,$Vv32.h,$Rt8):sat", 30556tc_16ff9ef8, TypeCVI_VS>, Enc_a30110, Requires<[UseHVXV60]> { 30557let Inst{7-5} = 0b110; 30558let Inst{13-13} = 0b0; 30559let Inst{31-24} = 0b00011011; 30560let hasNewValue = 1; 30561let opNewValue = 0; 30562let DecoderNamespace = "EXT_mmvec"; 30563} 30564def V6_vasrhubsat_alt : HInst< 30565(outs HvxVR:$Vd32), 30566(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8), 30567"$Vd32 = vasrhub($Vu32,$Vv32,$Rt8):sat", 30568tc_16ff9ef8, TypeMAPPING>, Requires<[HasV60]> { 30569let hasNewValue = 1; 30570let opNewValue = 0; 30571let isPseudo = 1; 30572let isCodeGenOnly = 1; 30573} 30574def V6_vasrhv : HInst< 30575(outs HvxVR:$Vd32), 30576(ins HvxVR:$Vu32, HvxVR:$Vv32), 30577"$Vd32.h = vasr($Vu32.h,$Vv32.h)", 30578tc_05ca8cfd, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV60]> { 30579let Inst{7-5} = 0b011; 30580let Inst{13-13} = 0b0; 30581let Inst{31-21} = 0b00011111101; 30582let hasNewValue = 1; 30583let opNewValue = 0; 30584let DecoderNamespace = "EXT_mmvec"; 30585} 30586def V6_vasrhv_alt : HInst< 30587(outs HvxVR:$Vd32), 30588(ins HvxVR:$Vu32, HvxVR:$Vv32), 30589"$Vd32 = vasrh($Vu32,$Vv32)", 30590PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 30591let hasNewValue = 1; 30592let opNewValue = 0; 30593let isPseudo = 1; 30594let isCodeGenOnly = 1; 30595let DecoderNamespace = "EXT_mmvec"; 30596} 30597def V6_vasruhubrndsat : HInst< 30598(outs HvxVR:$Vd32), 30599(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8), 30600"$Vd32.ub = vasr($Vu32.uh,$Vv32.uh,$Rt8):rnd:sat", 30601tc_16ff9ef8, TypeCVI_VS>, Enc_a30110, Requires<[UseHVXV65]> { 30602let Inst{7-5} = 0b111; 30603let Inst{13-13} = 0b0; 30604let Inst{31-24} = 0b00011000; 30605let hasNewValue = 1; 30606let opNewValue = 0; 30607let DecoderNamespace = "EXT_mmvec"; 30608} 30609def V6_vasruhubsat : HInst< 30610(outs HvxVR:$Vd32), 30611(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8), 30612"$Vd32.ub = vasr($Vu32.uh,$Vv32.uh,$Rt8):sat", 30613tc_16ff9ef8, TypeCVI_VS>, Enc_a30110, Requires<[UseHVXV65]> { 30614let Inst{7-5} = 0b101; 30615let Inst{13-13} = 0b1; 30616let Inst{31-24} = 0b00011000; 30617let hasNewValue = 1; 30618let opNewValue = 0; 30619let DecoderNamespace = "EXT_mmvec"; 30620} 30621def V6_vasruwuhrndsat : HInst< 30622(outs HvxVR:$Vd32), 30623(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8), 30624"$Vd32.uh = vasr($Vu32.uw,$Vv32.uw,$Rt8):rnd:sat", 30625tc_16ff9ef8, TypeCVI_VS>, Enc_a30110, Requires<[UseHVXV62]> { 30626let Inst{7-5} = 0b001; 30627let Inst{13-13} = 0b0; 30628let Inst{31-24} = 0b00011000; 30629let hasNewValue = 1; 30630let opNewValue = 0; 30631let DecoderNamespace = "EXT_mmvec"; 30632} 30633def V6_vasruwuhsat : HInst< 30634(outs HvxVR:$Vd32), 30635(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8), 30636"$Vd32.uh = vasr($Vu32.uw,$Vv32.uw,$Rt8):sat", 30637tc_16ff9ef8, TypeCVI_VS>, Enc_a30110, Requires<[UseHVXV65]> { 30638let Inst{7-5} = 0b100; 30639let Inst{13-13} = 0b1; 30640let Inst{31-24} = 0b00011000; 30641let hasNewValue = 1; 30642let opNewValue = 0; 30643let DecoderNamespace = "EXT_mmvec"; 30644} 30645def V6_vasrw : HInst< 30646(outs HvxVR:$Vd32), 30647(ins HvxVR:$Vu32, IntRegs:$Rt32), 30648"$Vd32.w = vasr($Vu32.w,$Rt32)", 30649tc_7417e785, TypeCVI_VS>, Enc_b087ac, Requires<[UseHVXV60]> { 30650let Inst{7-5} = 0b101; 30651let Inst{13-13} = 0b0; 30652let Inst{31-21} = 0b00011001011; 30653let hasNewValue = 1; 30654let opNewValue = 0; 30655let DecoderNamespace = "EXT_mmvec"; 30656} 30657def V6_vasrw_acc : HInst< 30658(outs HvxVR:$Vx32), 30659(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32), 30660"$Vx32.w += vasr($Vu32.w,$Rt32)", 30661tc_309dbb4f, TypeCVI_VS>, Enc_5138b3, Requires<[UseHVXV60]> { 30662let Inst{7-5} = 0b101; 30663let Inst{13-13} = 0b1; 30664let Inst{31-21} = 0b00011001011; 30665let hasNewValue = 1; 30666let opNewValue = 0; 30667let isAccumulator = 1; 30668let DecoderNamespace = "EXT_mmvec"; 30669let Constraints = "$Vx32 = $Vx32in"; 30670} 30671def V6_vasrw_acc_alt : HInst< 30672(outs HvxVR:$Vx32), 30673(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32), 30674"$Vx32 += vasrw($Vu32,$Rt32)", 30675PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 30676let hasNewValue = 1; 30677let opNewValue = 0; 30678let isAccumulator = 1; 30679let isPseudo = 1; 30680let isCodeGenOnly = 1; 30681let DecoderNamespace = "EXT_mmvec"; 30682let Constraints = "$Vx32 = $Vx32in"; 30683} 30684def V6_vasrw_alt : HInst< 30685(outs HvxVR:$Vd32), 30686(ins HvxVR:$Vu32, IntRegs:$Rt32), 30687"$Vd32 = vasrw($Vu32,$Rt32)", 30688PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 30689let hasNewValue = 1; 30690let opNewValue = 0; 30691let isPseudo = 1; 30692let isCodeGenOnly = 1; 30693let DecoderNamespace = "EXT_mmvec"; 30694} 30695def V6_vasrwh : HInst< 30696(outs HvxVR:$Vd32), 30697(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8), 30698"$Vd32.h = vasr($Vu32.w,$Vv32.w,$Rt8)", 30699tc_16ff9ef8, TypeCVI_VS>, Enc_a30110, Requires<[UseHVXV60]> { 30700let Inst{7-5} = 0b010; 30701let Inst{13-13} = 0b0; 30702let Inst{31-24} = 0b00011011; 30703let hasNewValue = 1; 30704let opNewValue = 0; 30705let DecoderNamespace = "EXT_mmvec"; 30706} 30707def V6_vasrwh_alt : HInst< 30708(outs HvxVR:$Vd32), 30709(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8), 30710"$Vd32 = vasrwh($Vu32,$Vv32,$Rt8)", 30711tc_16ff9ef8, TypeMAPPING>, Requires<[HasV60]> { 30712let hasNewValue = 1; 30713let opNewValue = 0; 30714let isPseudo = 1; 30715let isCodeGenOnly = 1; 30716} 30717def V6_vasrwhrndsat : HInst< 30718(outs HvxVR:$Vd32), 30719(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8), 30720"$Vd32.h = vasr($Vu32.w,$Vv32.w,$Rt8):rnd:sat", 30721tc_16ff9ef8, TypeCVI_VS>, Enc_a30110, Requires<[UseHVXV60]> { 30722let Inst{7-5} = 0b100; 30723let Inst{13-13} = 0b0; 30724let Inst{31-24} = 0b00011011; 30725let hasNewValue = 1; 30726let opNewValue = 0; 30727let DecoderNamespace = "EXT_mmvec"; 30728} 30729def V6_vasrwhrndsat_alt : HInst< 30730(outs HvxVR:$Vd32), 30731(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8), 30732"$Vd32 = vasrwh($Vu32,$Vv32,$Rt8):rnd:sat", 30733tc_16ff9ef8, TypeMAPPING>, Requires<[HasV60]> { 30734let hasNewValue = 1; 30735let opNewValue = 0; 30736let isPseudo = 1; 30737let isCodeGenOnly = 1; 30738} 30739def V6_vasrwhsat : HInst< 30740(outs HvxVR:$Vd32), 30741(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8), 30742"$Vd32.h = vasr($Vu32.w,$Vv32.w,$Rt8):sat", 30743tc_16ff9ef8, TypeCVI_VS>, Enc_a30110, Requires<[UseHVXV60]> { 30744let Inst{7-5} = 0b011; 30745let Inst{13-13} = 0b0; 30746let Inst{31-24} = 0b00011011; 30747let hasNewValue = 1; 30748let opNewValue = 0; 30749let DecoderNamespace = "EXT_mmvec"; 30750} 30751def V6_vasrwhsat_alt : HInst< 30752(outs HvxVR:$Vd32), 30753(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8), 30754"$Vd32 = vasrwh($Vu32,$Vv32,$Rt8):sat", 30755tc_16ff9ef8, TypeMAPPING>, Requires<[HasV60]> { 30756let hasNewValue = 1; 30757let opNewValue = 0; 30758let isPseudo = 1; 30759let isCodeGenOnly = 1; 30760} 30761def V6_vasrwuhrndsat : HInst< 30762(outs HvxVR:$Vd32), 30763(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8), 30764"$Vd32.uh = vasr($Vu32.w,$Vv32.w,$Rt8):rnd:sat", 30765tc_16ff9ef8, TypeCVI_VS>, Enc_a30110, Requires<[UseHVXV62]> { 30766let Inst{7-5} = 0b010; 30767let Inst{13-13} = 0b0; 30768let Inst{31-24} = 0b00011000; 30769let hasNewValue = 1; 30770let opNewValue = 0; 30771let DecoderNamespace = "EXT_mmvec"; 30772} 30773def V6_vasrwuhsat : HInst< 30774(outs HvxVR:$Vd32), 30775(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8), 30776"$Vd32.uh = vasr($Vu32.w,$Vv32.w,$Rt8):sat", 30777tc_16ff9ef8, TypeCVI_VS>, Enc_a30110, Requires<[UseHVXV60]> { 30778let Inst{7-5} = 0b101; 30779let Inst{13-13} = 0b0; 30780let Inst{31-24} = 0b00011011; 30781let hasNewValue = 1; 30782let opNewValue = 0; 30783let DecoderNamespace = "EXT_mmvec"; 30784} 30785def V6_vasrwuhsat_alt : HInst< 30786(outs HvxVR:$Vd32), 30787(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8), 30788"$Vd32 = vasrwuh($Vu32,$Vv32,$Rt8):sat", 30789tc_16ff9ef8, TypeMAPPING>, Requires<[HasV60]> { 30790let hasNewValue = 1; 30791let opNewValue = 0; 30792let isPseudo = 1; 30793let isCodeGenOnly = 1; 30794} 30795def V6_vasrwv : HInst< 30796(outs HvxVR:$Vd32), 30797(ins HvxVR:$Vu32, HvxVR:$Vv32), 30798"$Vd32.w = vasr($Vu32.w,$Vv32.w)", 30799tc_05ca8cfd, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV60]> { 30800let Inst{7-5} = 0b000; 30801let Inst{13-13} = 0b0; 30802let Inst{31-21} = 0b00011111101; 30803let hasNewValue = 1; 30804let opNewValue = 0; 30805let DecoderNamespace = "EXT_mmvec"; 30806} 30807def V6_vasrwv_alt : HInst< 30808(outs HvxVR:$Vd32), 30809(ins HvxVR:$Vu32, HvxVR:$Vv32), 30810"$Vd32 = vasrw($Vu32,$Vv32)", 30811PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 30812let hasNewValue = 1; 30813let opNewValue = 0; 30814let isPseudo = 1; 30815let isCodeGenOnly = 1; 30816let DecoderNamespace = "EXT_mmvec"; 30817} 30818def V6_vassign : HInst< 30819(outs HvxVR:$Vd32), 30820(ins HvxVR:$Vu32), 30821"$Vd32 = $Vu32", 30822tc_0ec46cf9, TypeCVI_VA>, Enc_e7581c, Requires<[UseHVXV60]> { 30823let Inst{7-5} = 0b111; 30824let Inst{13-13} = 0b1; 30825let Inst{31-16} = 0b0001111000000011; 30826let hasNewValue = 1; 30827let opNewValue = 0; 30828let DecoderNamespace = "EXT_mmvec"; 30829} 30830def V6_vassignp : HInst< 30831(outs HvxWR:$Vdd32), 30832(ins HvxWR:$Vuu32), 30833"$Vdd32 = $Vuu32", 30834CVI_VA, TypeCVI_VA_DV>, Requires<[UseHVXV60]> { 30835let hasNewValue = 1; 30836let opNewValue = 0; 30837let isPseudo = 1; 30838let DecoderNamespace = "EXT_mmvec"; 30839} 30840def V6_vavgb : HInst< 30841(outs HvxVR:$Vd32), 30842(ins HvxVR:$Vu32, HvxVR:$Vv32), 30843"$Vd32.b = vavg($Vu32.b,$Vv32.b)", 30844tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV65]> { 30845let Inst{7-5} = 0b100; 30846let Inst{13-13} = 0b1; 30847let Inst{31-21} = 0b00011111000; 30848let hasNewValue = 1; 30849let opNewValue = 0; 30850let DecoderNamespace = "EXT_mmvec"; 30851} 30852def V6_vavgb_alt : HInst< 30853(outs HvxVR:$Vd32), 30854(ins HvxVR:$Vu32, HvxVR:$Vv32), 30855"$Vd32 = vavgb($Vu32,$Vv32)", 30856PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> { 30857let hasNewValue = 1; 30858let opNewValue = 0; 30859let isPseudo = 1; 30860let isCodeGenOnly = 1; 30861let DecoderNamespace = "EXT_mmvec"; 30862} 30863def V6_vavgbrnd : HInst< 30864(outs HvxVR:$Vd32), 30865(ins HvxVR:$Vu32, HvxVR:$Vv32), 30866"$Vd32.b = vavg($Vu32.b,$Vv32.b):rnd", 30867tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV65]> { 30868let Inst{7-5} = 0b101; 30869let Inst{13-13} = 0b1; 30870let Inst{31-21} = 0b00011111000; 30871let hasNewValue = 1; 30872let opNewValue = 0; 30873let DecoderNamespace = "EXT_mmvec"; 30874} 30875def V6_vavgbrnd_alt : HInst< 30876(outs HvxVR:$Vd32), 30877(ins HvxVR:$Vu32, HvxVR:$Vv32), 30878"$Vd32 = vavgb($Vu32,$Vv32):rnd", 30879PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> { 30880let hasNewValue = 1; 30881let opNewValue = 0; 30882let isPseudo = 1; 30883let isCodeGenOnly = 1; 30884let DecoderNamespace = "EXT_mmvec"; 30885} 30886def V6_vavgh : HInst< 30887(outs HvxVR:$Vd32), 30888(ins HvxVR:$Vu32, HvxVR:$Vv32), 30889"$Vd32.h = vavg($Vu32.h,$Vv32.h)", 30890tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> { 30891let Inst{7-5} = 0b110; 30892let Inst{13-13} = 0b0; 30893let Inst{31-21} = 0b00011100110; 30894let hasNewValue = 1; 30895let opNewValue = 0; 30896let DecoderNamespace = "EXT_mmvec"; 30897} 30898def V6_vavgh_alt : HInst< 30899(outs HvxVR:$Vd32), 30900(ins HvxVR:$Vu32, HvxVR:$Vv32), 30901"$Vd32 = vavgh($Vu32,$Vv32)", 30902PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 30903let hasNewValue = 1; 30904let opNewValue = 0; 30905let isPseudo = 1; 30906let isCodeGenOnly = 1; 30907let DecoderNamespace = "EXT_mmvec"; 30908} 30909def V6_vavghrnd : HInst< 30910(outs HvxVR:$Vd32), 30911(ins HvxVR:$Vu32, HvxVR:$Vv32), 30912"$Vd32.h = vavg($Vu32.h,$Vv32.h):rnd", 30913tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> { 30914let Inst{7-5} = 0b101; 30915let Inst{13-13} = 0b0; 30916let Inst{31-21} = 0b00011100111; 30917let hasNewValue = 1; 30918let opNewValue = 0; 30919let DecoderNamespace = "EXT_mmvec"; 30920} 30921def V6_vavghrnd_alt : HInst< 30922(outs HvxVR:$Vd32), 30923(ins HvxVR:$Vu32, HvxVR:$Vv32), 30924"$Vd32 = vavgh($Vu32,$Vv32):rnd", 30925PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 30926let hasNewValue = 1; 30927let opNewValue = 0; 30928let isPseudo = 1; 30929let isCodeGenOnly = 1; 30930let DecoderNamespace = "EXT_mmvec"; 30931} 30932def V6_vavgub : HInst< 30933(outs HvxVR:$Vd32), 30934(ins HvxVR:$Vu32, HvxVR:$Vv32), 30935"$Vd32.ub = vavg($Vu32.ub,$Vv32.ub)", 30936tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> { 30937let Inst{7-5} = 0b100; 30938let Inst{13-13} = 0b0; 30939let Inst{31-21} = 0b00011100110; 30940let hasNewValue = 1; 30941let opNewValue = 0; 30942let DecoderNamespace = "EXT_mmvec"; 30943} 30944def V6_vavgub_alt : HInst< 30945(outs HvxVR:$Vd32), 30946(ins HvxVR:$Vu32, HvxVR:$Vv32), 30947"$Vd32 = vavgub($Vu32,$Vv32)", 30948PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 30949let hasNewValue = 1; 30950let opNewValue = 0; 30951let isPseudo = 1; 30952let isCodeGenOnly = 1; 30953let DecoderNamespace = "EXT_mmvec"; 30954} 30955def V6_vavgubrnd : HInst< 30956(outs HvxVR:$Vd32), 30957(ins HvxVR:$Vu32, HvxVR:$Vv32), 30958"$Vd32.ub = vavg($Vu32.ub,$Vv32.ub):rnd", 30959tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> { 30960let Inst{7-5} = 0b011; 30961let Inst{13-13} = 0b0; 30962let Inst{31-21} = 0b00011100111; 30963let hasNewValue = 1; 30964let opNewValue = 0; 30965let DecoderNamespace = "EXT_mmvec"; 30966} 30967def V6_vavgubrnd_alt : HInst< 30968(outs HvxVR:$Vd32), 30969(ins HvxVR:$Vu32, HvxVR:$Vv32), 30970"$Vd32 = vavgub($Vu32,$Vv32):rnd", 30971PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 30972let hasNewValue = 1; 30973let opNewValue = 0; 30974let isPseudo = 1; 30975let isCodeGenOnly = 1; 30976let DecoderNamespace = "EXT_mmvec"; 30977} 30978def V6_vavguh : HInst< 30979(outs HvxVR:$Vd32), 30980(ins HvxVR:$Vu32, HvxVR:$Vv32), 30981"$Vd32.uh = vavg($Vu32.uh,$Vv32.uh)", 30982tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> { 30983let Inst{7-5} = 0b101; 30984let Inst{13-13} = 0b0; 30985let Inst{31-21} = 0b00011100110; 30986let hasNewValue = 1; 30987let opNewValue = 0; 30988let DecoderNamespace = "EXT_mmvec"; 30989} 30990def V6_vavguh_alt : HInst< 30991(outs HvxVR:$Vd32), 30992(ins HvxVR:$Vu32, HvxVR:$Vv32), 30993"$Vd32 = vavguh($Vu32,$Vv32)", 30994PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 30995let hasNewValue = 1; 30996let opNewValue = 0; 30997let isPseudo = 1; 30998let isCodeGenOnly = 1; 30999let DecoderNamespace = "EXT_mmvec"; 31000} 31001def V6_vavguhrnd : HInst< 31002(outs HvxVR:$Vd32), 31003(ins HvxVR:$Vu32, HvxVR:$Vv32), 31004"$Vd32.uh = vavg($Vu32.uh,$Vv32.uh):rnd", 31005tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> { 31006let Inst{7-5} = 0b100; 31007let Inst{13-13} = 0b0; 31008let Inst{31-21} = 0b00011100111; 31009let hasNewValue = 1; 31010let opNewValue = 0; 31011let DecoderNamespace = "EXT_mmvec"; 31012} 31013def V6_vavguhrnd_alt : HInst< 31014(outs HvxVR:$Vd32), 31015(ins HvxVR:$Vu32, HvxVR:$Vv32), 31016"$Vd32 = vavguh($Vu32,$Vv32):rnd", 31017PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 31018let hasNewValue = 1; 31019let opNewValue = 0; 31020let isPseudo = 1; 31021let isCodeGenOnly = 1; 31022let DecoderNamespace = "EXT_mmvec"; 31023} 31024def V6_vavguw : HInst< 31025(outs HvxVR:$Vd32), 31026(ins HvxVR:$Vu32, HvxVR:$Vv32), 31027"$Vd32.uw = vavg($Vu32.uw,$Vv32.uw)", 31028tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV65]> { 31029let Inst{7-5} = 0b010; 31030let Inst{13-13} = 0b1; 31031let Inst{31-21} = 0b00011111000; 31032let hasNewValue = 1; 31033let opNewValue = 0; 31034let DecoderNamespace = "EXT_mmvec"; 31035} 31036def V6_vavguw_alt : HInst< 31037(outs HvxVR:$Vd32), 31038(ins HvxVR:$Vu32, HvxVR:$Vv32), 31039"$Vd32 = vavguw($Vu32,$Vv32)", 31040PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> { 31041let hasNewValue = 1; 31042let opNewValue = 0; 31043let isPseudo = 1; 31044let isCodeGenOnly = 1; 31045let DecoderNamespace = "EXT_mmvec"; 31046} 31047def V6_vavguwrnd : HInst< 31048(outs HvxVR:$Vd32), 31049(ins HvxVR:$Vu32, HvxVR:$Vv32), 31050"$Vd32.uw = vavg($Vu32.uw,$Vv32.uw):rnd", 31051tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV65]> { 31052let Inst{7-5} = 0b011; 31053let Inst{13-13} = 0b1; 31054let Inst{31-21} = 0b00011111000; 31055let hasNewValue = 1; 31056let opNewValue = 0; 31057let DecoderNamespace = "EXT_mmvec"; 31058} 31059def V6_vavguwrnd_alt : HInst< 31060(outs HvxVR:$Vd32), 31061(ins HvxVR:$Vu32, HvxVR:$Vv32), 31062"$Vd32 = vavguw($Vu32,$Vv32):rnd", 31063PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> { 31064let hasNewValue = 1; 31065let opNewValue = 0; 31066let isPseudo = 1; 31067let isCodeGenOnly = 1; 31068let DecoderNamespace = "EXT_mmvec"; 31069} 31070def V6_vavgw : HInst< 31071(outs HvxVR:$Vd32), 31072(ins HvxVR:$Vu32, HvxVR:$Vv32), 31073"$Vd32.w = vavg($Vu32.w,$Vv32.w)", 31074tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> { 31075let Inst{7-5} = 0b111; 31076let Inst{13-13} = 0b0; 31077let Inst{31-21} = 0b00011100110; 31078let hasNewValue = 1; 31079let opNewValue = 0; 31080let DecoderNamespace = "EXT_mmvec"; 31081} 31082def V6_vavgw_alt : HInst< 31083(outs HvxVR:$Vd32), 31084(ins HvxVR:$Vu32, HvxVR:$Vv32), 31085"$Vd32 = vavgw($Vu32,$Vv32)", 31086PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 31087let hasNewValue = 1; 31088let opNewValue = 0; 31089let isPseudo = 1; 31090let isCodeGenOnly = 1; 31091let DecoderNamespace = "EXT_mmvec"; 31092} 31093def V6_vavgwrnd : HInst< 31094(outs HvxVR:$Vd32), 31095(ins HvxVR:$Vu32, HvxVR:$Vv32), 31096"$Vd32.w = vavg($Vu32.w,$Vv32.w):rnd", 31097tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> { 31098let Inst{7-5} = 0b110; 31099let Inst{13-13} = 0b0; 31100let Inst{31-21} = 0b00011100111; 31101let hasNewValue = 1; 31102let opNewValue = 0; 31103let DecoderNamespace = "EXT_mmvec"; 31104} 31105def V6_vavgwrnd_alt : HInst< 31106(outs HvxVR:$Vd32), 31107(ins HvxVR:$Vu32, HvxVR:$Vv32), 31108"$Vd32 = vavgw($Vu32,$Vv32):rnd", 31109PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 31110let hasNewValue = 1; 31111let opNewValue = 0; 31112let isPseudo = 1; 31113let isCodeGenOnly = 1; 31114let DecoderNamespace = "EXT_mmvec"; 31115} 31116def V6_vccombine : HInst< 31117(outs HvxWR:$Vdd32), 31118(ins PredRegs:$Ps4, HvxVR:$Vu32, HvxVR:$Vv32), 31119"if ($Ps4) $Vdd32 = vcombine($Vu32,$Vv32)", 31120tc_af25efd9, TypeCVI_VA_DV>, Enc_8c2412, Requires<[UseHVXV60]> { 31121let Inst{7-7} = 0b0; 31122let Inst{13-13} = 0b0; 31123let Inst{31-21} = 0b00011010011; 31124let isPredicated = 1; 31125let hasNewValue = 1; 31126let opNewValue = 0; 31127let DecoderNamespace = "EXT_mmvec"; 31128} 31129def V6_vcl0h : HInst< 31130(outs HvxVR:$Vd32), 31131(ins HvxVR:$Vu32), 31132"$Vd32.uh = vcl0($Vu32.uh)", 31133tc_51d0ecc3, TypeCVI_VS>, Enc_e7581c, Requires<[UseHVXV60]> { 31134let Inst{7-5} = 0b111; 31135let Inst{13-13} = 0b0; 31136let Inst{31-16} = 0b0001111000000010; 31137let hasNewValue = 1; 31138let opNewValue = 0; 31139let DecoderNamespace = "EXT_mmvec"; 31140} 31141def V6_vcl0h_alt : HInst< 31142(outs HvxVR:$Vd32), 31143(ins HvxVR:$Vu32), 31144"$Vd32 = vcl0h($Vu32)", 31145PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 31146let hasNewValue = 1; 31147let opNewValue = 0; 31148let isPseudo = 1; 31149let isCodeGenOnly = 1; 31150let DecoderNamespace = "EXT_mmvec"; 31151} 31152def V6_vcl0w : HInst< 31153(outs HvxVR:$Vd32), 31154(ins HvxVR:$Vu32), 31155"$Vd32.uw = vcl0($Vu32.uw)", 31156tc_51d0ecc3, TypeCVI_VS>, Enc_e7581c, Requires<[UseHVXV60]> { 31157let Inst{7-5} = 0b101; 31158let Inst{13-13} = 0b0; 31159let Inst{31-16} = 0b0001111000000010; 31160let hasNewValue = 1; 31161let opNewValue = 0; 31162let DecoderNamespace = "EXT_mmvec"; 31163} 31164def V6_vcl0w_alt : HInst< 31165(outs HvxVR:$Vd32), 31166(ins HvxVR:$Vu32), 31167"$Vd32 = vcl0w($Vu32)", 31168PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 31169let hasNewValue = 1; 31170let opNewValue = 0; 31171let isPseudo = 1; 31172let isCodeGenOnly = 1; 31173let DecoderNamespace = "EXT_mmvec"; 31174} 31175def V6_vcmov : HInst< 31176(outs HvxVR:$Vd32), 31177(ins PredRegs:$Ps4, HvxVR:$Vu32), 31178"if ($Ps4) $Vd32 = $Vu32", 31179tc_3aacf4a8, TypeCVI_VA>, Enc_770858, Requires<[UseHVXV60]> { 31180let Inst{7-7} = 0b0; 31181let Inst{13-13} = 0b0; 31182let Inst{31-16} = 0b0001101000000000; 31183let isPredicated = 1; 31184let hasNewValue = 1; 31185let opNewValue = 0; 31186let DecoderNamespace = "EXT_mmvec"; 31187} 31188def V6_vcombine : HInst< 31189(outs HvxWR:$Vdd32), 31190(ins HvxVR:$Vu32, HvxVR:$Vv32), 31191"$Vdd32 = vcombine($Vu32,$Vv32)", 31192tc_db5555f3, TypeCVI_VA_DV>, Enc_71bb9b, Requires<[UseHVXV60]> { 31193let Inst{7-5} = 0b111; 31194let Inst{13-13} = 0b0; 31195let Inst{31-21} = 0b00011111010; 31196let hasNewValue = 1; 31197let opNewValue = 0; 31198let isRegSequence = 1; 31199let DecoderNamespace = "EXT_mmvec"; 31200} 31201def V6_vd0 : HInst< 31202(outs HvxVR:$Vd32), 31203(ins), 31204"$Vd32 = #0", 31205CVI_VA, TypeCVI_VA>, Requires<[UseHVXV60]> { 31206let hasNewValue = 1; 31207let opNewValue = 0; 31208let isPseudo = 1; 31209let isCodeGenOnly = 1; 31210let DecoderNamespace = "EXT_mmvec"; 31211} 31212def V6_vdd0 : HInst< 31213(outs HvxWR:$Vdd32), 31214(ins), 31215"$Vdd32 = #0", 31216tc_718b5c53, TypeMAPPING>, Requires<[UseHVXV65]> { 31217let hasNewValue = 1; 31218let opNewValue = 0; 31219let isPseudo = 1; 31220let isCodeGenOnly = 1; 31221let DecoderNamespace = "EXT_mmvec"; 31222} 31223def V6_vdeal : HInst< 31224(outs HvxVR:$Vy32, HvxVR:$Vx32), 31225(ins HvxVR:$Vy32in, HvxVR:$Vx32in, IntRegs:$Rt32), 31226"vdeal($Vy32,$Vx32,$Rt32)", 31227tc_561aaa58, TypeCVI_VP_VS>, Enc_989021, Requires<[UseHVXV60]> { 31228let Inst{7-5} = 0b010; 31229let Inst{13-13} = 0b1; 31230let Inst{31-21} = 0b00011001111; 31231let hasNewValue = 1; 31232let opNewValue = 0; 31233let hasNewValue2 = 1; 31234let opNewValue2 = 1; 31235let DecoderNamespace = "EXT_mmvec"; 31236let Constraints = "$Vy32 = $Vy32in, $Vx32 = $Vx32in"; 31237} 31238def V6_vdealb : HInst< 31239(outs HvxVR:$Vd32), 31240(ins HvxVR:$Vu32), 31241"$Vd32.b = vdeal($Vu32.b)", 31242tc_946013d8, TypeCVI_VP>, Enc_e7581c, Requires<[UseHVXV60]> { 31243let Inst{7-5} = 0b111; 31244let Inst{13-13} = 0b0; 31245let Inst{31-16} = 0b0001111000000000; 31246let hasNewValue = 1; 31247let opNewValue = 0; 31248let DecoderNamespace = "EXT_mmvec"; 31249} 31250def V6_vdealb4w : HInst< 31251(outs HvxVR:$Vd32), 31252(ins HvxVR:$Vu32, HvxVR:$Vv32), 31253"$Vd32.b = vdeale($Vu32.b,$Vv32.b)", 31254tc_46d6c3e0, TypeCVI_VP>, Enc_45364e, Requires<[UseHVXV60]> { 31255let Inst{7-5} = 0b111; 31256let Inst{13-13} = 0b0; 31257let Inst{31-21} = 0b00011111001; 31258let hasNewValue = 1; 31259let opNewValue = 0; 31260let DecoderNamespace = "EXT_mmvec"; 31261} 31262def V6_vdealb4w_alt : HInst< 31263(outs HvxVR:$Vd32), 31264(ins HvxVR:$Vu32, HvxVR:$Vv32), 31265"$Vd32 = vdealb4w($Vu32,$Vv32)", 31266PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 31267let hasNewValue = 1; 31268let opNewValue = 0; 31269let isPseudo = 1; 31270let isCodeGenOnly = 1; 31271let DecoderNamespace = "EXT_mmvec"; 31272} 31273def V6_vdealb_alt : HInst< 31274(outs HvxVR:$Vd32), 31275(ins HvxVR:$Vu32), 31276"$Vd32 = vdealb($Vu32)", 31277PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 31278let hasNewValue = 1; 31279let opNewValue = 0; 31280let isPseudo = 1; 31281let isCodeGenOnly = 1; 31282let DecoderNamespace = "EXT_mmvec"; 31283} 31284def V6_vdealh : HInst< 31285(outs HvxVR:$Vd32), 31286(ins HvxVR:$Vu32), 31287"$Vd32.h = vdeal($Vu32.h)", 31288tc_946013d8, TypeCVI_VP>, Enc_e7581c, Requires<[UseHVXV60]> { 31289let Inst{7-5} = 0b110; 31290let Inst{13-13} = 0b0; 31291let Inst{31-16} = 0b0001111000000000; 31292let hasNewValue = 1; 31293let opNewValue = 0; 31294let DecoderNamespace = "EXT_mmvec"; 31295} 31296def V6_vdealh_alt : HInst< 31297(outs HvxVR:$Vd32), 31298(ins HvxVR:$Vu32), 31299"$Vd32 = vdealh($Vu32)", 31300PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 31301let hasNewValue = 1; 31302let opNewValue = 0; 31303let isPseudo = 1; 31304let isCodeGenOnly = 1; 31305let DecoderNamespace = "EXT_mmvec"; 31306} 31307def V6_vdealvdd : HInst< 31308(outs HvxWR:$Vdd32), 31309(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8), 31310"$Vdd32 = vdeal($Vu32,$Vv32,$Rt8)", 31311tc_87adc037, TypeCVI_VP_VS>, Enc_24a7dc, Requires<[UseHVXV60]> { 31312let Inst{7-5} = 0b100; 31313let Inst{13-13} = 0b1; 31314let Inst{31-24} = 0b00011011; 31315let hasNewValue = 1; 31316let opNewValue = 0; 31317let DecoderNamespace = "EXT_mmvec"; 31318} 31319def V6_vdelta : HInst< 31320(outs HvxVR:$Vd32), 31321(ins HvxVR:$Vu32, HvxVR:$Vv32), 31322"$Vd32 = vdelta($Vu32,$Vv32)", 31323tc_46d6c3e0, TypeCVI_VP>, Enc_45364e, Requires<[UseHVXV60]> { 31324let Inst{7-5} = 0b001; 31325let Inst{13-13} = 0b0; 31326let Inst{31-21} = 0b00011111001; 31327let hasNewValue = 1; 31328let opNewValue = 0; 31329let DecoderNamespace = "EXT_mmvec"; 31330} 31331def V6_vdmpybus : HInst< 31332(outs HvxVR:$Vd32), 31333(ins HvxVR:$Vu32, IntRegs:$Rt32), 31334"$Vd32.h = vdmpy($Vu32.ub,$Rt32.b)", 31335tc_649072c2, TypeCVI_VX>, Enc_b087ac, Requires<[UseHVXV60]> { 31336let Inst{7-5} = 0b110; 31337let Inst{13-13} = 0b0; 31338let Inst{31-21} = 0b00011001000; 31339let hasNewValue = 1; 31340let opNewValue = 0; 31341let DecoderNamespace = "EXT_mmvec"; 31342} 31343def V6_vdmpybus_acc : HInst< 31344(outs HvxVR:$Vx32), 31345(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32), 31346"$Vx32.h += vdmpy($Vu32.ub,$Rt32.b)", 31347tc_b091f1c6, TypeCVI_VX>, Enc_5138b3, Requires<[UseHVXV60]> { 31348let Inst{7-5} = 0b110; 31349let Inst{13-13} = 0b1; 31350let Inst{31-21} = 0b00011001000; 31351let hasNewValue = 1; 31352let opNewValue = 0; 31353let isAccumulator = 1; 31354let DecoderNamespace = "EXT_mmvec"; 31355let Constraints = "$Vx32 = $Vx32in"; 31356} 31357def V6_vdmpybus_acc_alt : HInst< 31358(outs HvxVR:$Vx32), 31359(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32), 31360"$Vx32 += vdmpybus($Vu32,$Rt32)", 31361PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 31362let hasNewValue = 1; 31363let opNewValue = 0; 31364let isAccumulator = 1; 31365let isPseudo = 1; 31366let isCodeGenOnly = 1; 31367let DecoderNamespace = "EXT_mmvec"; 31368let Constraints = "$Vx32 = $Vx32in"; 31369} 31370def V6_vdmpybus_alt : HInst< 31371(outs HvxVR:$Vd32), 31372(ins HvxVR:$Vu32, IntRegs:$Rt32), 31373"$Vd32 = vdmpybus($Vu32,$Rt32)", 31374PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 31375let hasNewValue = 1; 31376let opNewValue = 0; 31377let isPseudo = 1; 31378let isCodeGenOnly = 1; 31379let DecoderNamespace = "EXT_mmvec"; 31380} 31381def V6_vdmpybus_dv : HInst< 31382(outs HvxWR:$Vdd32), 31383(ins HvxWR:$Vuu32, IntRegs:$Rt32), 31384"$Vdd32.h = vdmpy($Vuu32.ub,$Rt32.b)", 31385tc_0b04c6c7, TypeCVI_VX_DV>, Enc_aad80c, Requires<[UseHVXV60]> { 31386let Inst{7-5} = 0b111; 31387let Inst{13-13} = 0b0; 31388let Inst{31-21} = 0b00011001000; 31389let hasNewValue = 1; 31390let opNewValue = 0; 31391let DecoderNamespace = "EXT_mmvec"; 31392} 31393def V6_vdmpybus_dv_acc : HInst< 31394(outs HvxWR:$Vxx32), 31395(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32), 31396"$Vxx32.h += vdmpy($Vuu32.ub,$Rt32.b)", 31397tc_660769f1, TypeCVI_VX_DV>, Enc_d6990d, Requires<[UseHVXV60]> { 31398let Inst{7-5} = 0b111; 31399let Inst{13-13} = 0b1; 31400let Inst{31-21} = 0b00011001000; 31401let hasNewValue = 1; 31402let opNewValue = 0; 31403let isAccumulator = 1; 31404let DecoderNamespace = "EXT_mmvec"; 31405let Constraints = "$Vxx32 = $Vxx32in"; 31406} 31407def V6_vdmpybus_dv_acc_alt : HInst< 31408(outs HvxWR:$Vxx32), 31409(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32), 31410"$Vxx32 += vdmpybus($Vuu32,$Rt32)", 31411PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 31412let hasNewValue = 1; 31413let opNewValue = 0; 31414let isAccumulator = 1; 31415let isPseudo = 1; 31416let isCodeGenOnly = 1; 31417let DecoderNamespace = "EXT_mmvec"; 31418let Constraints = "$Vxx32 = $Vxx32in"; 31419} 31420def V6_vdmpybus_dv_alt : HInst< 31421(outs HvxWR:$Vdd32), 31422(ins HvxWR:$Vuu32, IntRegs:$Rt32), 31423"$Vdd32 = vdmpybus($Vuu32,$Rt32)", 31424PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 31425let hasNewValue = 1; 31426let opNewValue = 0; 31427let isPseudo = 1; 31428let isCodeGenOnly = 1; 31429let DecoderNamespace = "EXT_mmvec"; 31430} 31431def V6_vdmpyhb : HInst< 31432(outs HvxVR:$Vd32), 31433(ins HvxVR:$Vu32, IntRegs:$Rt32), 31434"$Vd32.w = vdmpy($Vu32.h,$Rt32.b)", 31435tc_649072c2, TypeCVI_VX>, Enc_b087ac, Requires<[UseHVXV60]> { 31436let Inst{7-5} = 0b010; 31437let Inst{13-13} = 0b0; 31438let Inst{31-21} = 0b00011001000; 31439let hasNewValue = 1; 31440let opNewValue = 0; 31441let DecoderNamespace = "EXT_mmvec"; 31442} 31443def V6_vdmpyhb_acc : HInst< 31444(outs HvxVR:$Vx32), 31445(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32), 31446"$Vx32.w += vdmpy($Vu32.h,$Rt32.b)", 31447tc_b091f1c6, TypeCVI_VX>, Enc_5138b3, Requires<[UseHVXV60]> { 31448let Inst{7-5} = 0b011; 31449let Inst{13-13} = 0b1; 31450let Inst{31-21} = 0b00011001000; 31451let hasNewValue = 1; 31452let opNewValue = 0; 31453let isAccumulator = 1; 31454let DecoderNamespace = "EXT_mmvec"; 31455let Constraints = "$Vx32 = $Vx32in"; 31456} 31457def V6_vdmpyhb_acc_alt : HInst< 31458(outs HvxVR:$Vx32), 31459(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32), 31460"$Vx32 += vdmpyhb($Vu32,$Rt32)", 31461PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 31462let hasNewValue = 1; 31463let opNewValue = 0; 31464let isAccumulator = 1; 31465let isPseudo = 1; 31466let isCodeGenOnly = 1; 31467let DecoderNamespace = "EXT_mmvec"; 31468let Constraints = "$Vx32 = $Vx32in"; 31469} 31470def V6_vdmpyhb_alt : HInst< 31471(outs HvxVR:$Vd32), 31472(ins HvxVR:$Vu32, IntRegs:$Rt32), 31473"$Vd32 = vdmpyhb($Vu32,$Rt32)", 31474PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 31475let hasNewValue = 1; 31476let opNewValue = 0; 31477let isPseudo = 1; 31478let isCodeGenOnly = 1; 31479let DecoderNamespace = "EXT_mmvec"; 31480} 31481def V6_vdmpyhb_dv : HInst< 31482(outs HvxWR:$Vdd32), 31483(ins HvxWR:$Vuu32, IntRegs:$Rt32), 31484"$Vdd32.w = vdmpy($Vuu32.h,$Rt32.b)", 31485tc_0b04c6c7, TypeCVI_VX_DV>, Enc_aad80c, Requires<[UseHVXV60]> { 31486let Inst{7-5} = 0b100; 31487let Inst{13-13} = 0b0; 31488let Inst{31-21} = 0b00011001001; 31489let hasNewValue = 1; 31490let opNewValue = 0; 31491let DecoderNamespace = "EXT_mmvec"; 31492} 31493def V6_vdmpyhb_dv_acc : HInst< 31494(outs HvxWR:$Vxx32), 31495(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32), 31496"$Vxx32.w += vdmpy($Vuu32.h,$Rt32.b)", 31497tc_660769f1, TypeCVI_VX_DV>, Enc_d6990d, Requires<[UseHVXV60]> { 31498let Inst{7-5} = 0b100; 31499let Inst{13-13} = 0b1; 31500let Inst{31-21} = 0b00011001001; 31501let hasNewValue = 1; 31502let opNewValue = 0; 31503let isAccumulator = 1; 31504let DecoderNamespace = "EXT_mmvec"; 31505let Constraints = "$Vxx32 = $Vxx32in"; 31506} 31507def V6_vdmpyhb_dv_acc_alt : HInst< 31508(outs HvxWR:$Vxx32), 31509(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32), 31510"$Vxx32 += vdmpyhb($Vuu32,$Rt32)", 31511PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 31512let hasNewValue = 1; 31513let opNewValue = 0; 31514let isAccumulator = 1; 31515let isPseudo = 1; 31516let isCodeGenOnly = 1; 31517let DecoderNamespace = "EXT_mmvec"; 31518let Constraints = "$Vxx32 = $Vxx32in"; 31519} 31520def V6_vdmpyhb_dv_alt : HInst< 31521(outs HvxWR:$Vdd32), 31522(ins HvxWR:$Vuu32, IntRegs:$Rt32), 31523"$Vdd32 = vdmpyhb($Vuu32,$Rt32)", 31524PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 31525let hasNewValue = 1; 31526let opNewValue = 0; 31527let isPseudo = 1; 31528let isCodeGenOnly = 1; 31529let DecoderNamespace = "EXT_mmvec"; 31530} 31531def V6_vdmpyhisat : HInst< 31532(outs HvxVR:$Vd32), 31533(ins HvxWR:$Vuu32, IntRegs:$Rt32), 31534"$Vd32.w = vdmpy($Vuu32.h,$Rt32.h):sat", 31535tc_0b04c6c7, TypeCVI_VX_DV>, Enc_0e41fa, Requires<[UseHVXV60]> { 31536let Inst{7-5} = 0b011; 31537let Inst{13-13} = 0b0; 31538let Inst{31-21} = 0b00011001001; 31539let hasNewValue = 1; 31540let opNewValue = 0; 31541let DecoderNamespace = "EXT_mmvec"; 31542} 31543def V6_vdmpyhisat_acc : HInst< 31544(outs HvxVR:$Vx32), 31545(ins HvxVR:$Vx32in, HvxWR:$Vuu32, IntRegs:$Rt32), 31546"$Vx32.w += vdmpy($Vuu32.h,$Rt32.h):sat", 31547tc_660769f1, TypeCVI_VX_DV>, Enc_cc857d, Requires<[UseHVXV60]> { 31548let Inst{7-5} = 0b010; 31549let Inst{13-13} = 0b1; 31550let Inst{31-21} = 0b00011001001; 31551let hasNewValue = 1; 31552let opNewValue = 0; 31553let isAccumulator = 1; 31554let DecoderNamespace = "EXT_mmvec"; 31555let Constraints = "$Vx32 = $Vx32in"; 31556} 31557def V6_vdmpyhisat_acc_alt : HInst< 31558(outs HvxVR:$Vx32), 31559(ins HvxVR:$Vx32in, HvxWR:$Vuu32, IntRegs:$Rt32), 31560"$Vx32 += vdmpyh($Vuu32,$Rt32):sat", 31561PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 31562let hasNewValue = 1; 31563let opNewValue = 0; 31564let isAccumulator = 1; 31565let isPseudo = 1; 31566let isCodeGenOnly = 1; 31567let DecoderNamespace = "EXT_mmvec"; 31568let Constraints = "$Vx32 = $Vx32in"; 31569} 31570def V6_vdmpyhisat_alt : HInst< 31571(outs HvxVR:$Vd32), 31572(ins HvxWR:$Vuu32, IntRegs:$Rt32), 31573"$Vd32 = vdmpyh($Vuu32,$Rt32):sat", 31574PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 31575let hasNewValue = 1; 31576let opNewValue = 0; 31577let isPseudo = 1; 31578let isCodeGenOnly = 1; 31579let DecoderNamespace = "EXT_mmvec"; 31580} 31581def V6_vdmpyhsat : HInst< 31582(outs HvxVR:$Vd32), 31583(ins HvxVR:$Vu32, IntRegs:$Rt32), 31584"$Vd32.w = vdmpy($Vu32.h,$Rt32.h):sat", 31585tc_0b04c6c7, TypeCVI_VX_DV>, Enc_b087ac, Requires<[UseHVXV60]> { 31586let Inst{7-5} = 0b010; 31587let Inst{13-13} = 0b0; 31588let Inst{31-21} = 0b00011001001; 31589let hasNewValue = 1; 31590let opNewValue = 0; 31591let DecoderNamespace = "EXT_mmvec"; 31592} 31593def V6_vdmpyhsat_acc : HInst< 31594(outs HvxVR:$Vx32), 31595(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32), 31596"$Vx32.w += vdmpy($Vu32.h,$Rt32.h):sat", 31597tc_660769f1, TypeCVI_VX_DV>, Enc_5138b3, Requires<[UseHVXV60]> { 31598let Inst{7-5} = 0b011; 31599let Inst{13-13} = 0b1; 31600let Inst{31-21} = 0b00011001001; 31601let hasNewValue = 1; 31602let opNewValue = 0; 31603let isAccumulator = 1; 31604let DecoderNamespace = "EXT_mmvec"; 31605let Constraints = "$Vx32 = $Vx32in"; 31606} 31607def V6_vdmpyhsat_acc_alt : HInst< 31608(outs HvxVR:$Vx32), 31609(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32), 31610"$Vx32 += vdmpyh($Vu32,$Rt32):sat", 31611PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 31612let hasNewValue = 1; 31613let opNewValue = 0; 31614let isAccumulator = 1; 31615let isPseudo = 1; 31616let isCodeGenOnly = 1; 31617let DecoderNamespace = "EXT_mmvec"; 31618let Constraints = "$Vx32 = $Vx32in"; 31619} 31620def V6_vdmpyhsat_alt : HInst< 31621(outs HvxVR:$Vd32), 31622(ins HvxVR:$Vu32, IntRegs:$Rt32), 31623"$Vd32 = vdmpyh($Vu32,$Rt32):sat", 31624PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 31625let hasNewValue = 1; 31626let opNewValue = 0; 31627let isPseudo = 1; 31628let isCodeGenOnly = 1; 31629let DecoderNamespace = "EXT_mmvec"; 31630} 31631def V6_vdmpyhsuisat : HInst< 31632(outs HvxVR:$Vd32), 31633(ins HvxWR:$Vuu32, IntRegs:$Rt32), 31634"$Vd32.w = vdmpy($Vuu32.h,$Rt32.uh,#1):sat", 31635tc_0b04c6c7, TypeCVI_VX_DV>, Enc_0e41fa, Requires<[UseHVXV60]> { 31636let Inst{7-5} = 0b001; 31637let Inst{13-13} = 0b0; 31638let Inst{31-21} = 0b00011001001; 31639let hasNewValue = 1; 31640let opNewValue = 0; 31641let DecoderNamespace = "EXT_mmvec"; 31642} 31643def V6_vdmpyhsuisat_acc : HInst< 31644(outs HvxVR:$Vx32), 31645(ins HvxVR:$Vx32in, HvxWR:$Vuu32, IntRegs:$Rt32), 31646"$Vx32.w += vdmpy($Vuu32.h,$Rt32.uh,#1):sat", 31647tc_660769f1, TypeCVI_VX_DV>, Enc_cc857d, Requires<[UseHVXV60]> { 31648let Inst{7-5} = 0b001; 31649let Inst{13-13} = 0b1; 31650let Inst{31-21} = 0b00011001001; 31651let hasNewValue = 1; 31652let opNewValue = 0; 31653let isAccumulator = 1; 31654let DecoderNamespace = "EXT_mmvec"; 31655let Constraints = "$Vx32 = $Vx32in"; 31656} 31657def V6_vdmpyhsuisat_acc_alt : HInst< 31658(outs HvxVR:$Vx32), 31659(ins HvxVR:$Vx32in, HvxWR:$Vuu32, IntRegs:$Rt32), 31660"$Vx32 += vdmpyhsu($Vuu32,$Rt32,#1):sat", 31661PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 31662let hasNewValue = 1; 31663let opNewValue = 0; 31664let isAccumulator = 1; 31665let isPseudo = 1; 31666let isCodeGenOnly = 1; 31667let DecoderNamespace = "EXT_mmvec"; 31668let Constraints = "$Vx32 = $Vx32in"; 31669} 31670def V6_vdmpyhsuisat_alt : HInst< 31671(outs HvxVR:$Vd32), 31672(ins HvxWR:$Vuu32, IntRegs:$Rt32), 31673"$Vd32 = vdmpyhsu($Vuu32,$Rt32,#1):sat", 31674PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 31675let hasNewValue = 1; 31676let opNewValue = 0; 31677let isPseudo = 1; 31678let isCodeGenOnly = 1; 31679let DecoderNamespace = "EXT_mmvec"; 31680} 31681def V6_vdmpyhsusat : HInst< 31682(outs HvxVR:$Vd32), 31683(ins HvxVR:$Vu32, IntRegs:$Rt32), 31684"$Vd32.w = vdmpy($Vu32.h,$Rt32.uh):sat", 31685tc_0b04c6c7, TypeCVI_VX_DV>, Enc_b087ac, Requires<[UseHVXV60]> { 31686let Inst{7-5} = 0b000; 31687let Inst{13-13} = 0b0; 31688let Inst{31-21} = 0b00011001001; 31689let hasNewValue = 1; 31690let opNewValue = 0; 31691let DecoderNamespace = "EXT_mmvec"; 31692} 31693def V6_vdmpyhsusat_acc : HInst< 31694(outs HvxVR:$Vx32), 31695(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32), 31696"$Vx32.w += vdmpy($Vu32.h,$Rt32.uh):sat", 31697tc_660769f1, TypeCVI_VX_DV>, Enc_5138b3, Requires<[UseHVXV60]> { 31698let Inst{7-5} = 0b000; 31699let Inst{13-13} = 0b1; 31700let Inst{31-21} = 0b00011001001; 31701let hasNewValue = 1; 31702let opNewValue = 0; 31703let isAccumulator = 1; 31704let DecoderNamespace = "EXT_mmvec"; 31705let Constraints = "$Vx32 = $Vx32in"; 31706} 31707def V6_vdmpyhsusat_acc_alt : HInst< 31708(outs HvxVR:$Vx32), 31709(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32), 31710"$Vx32 += vdmpyhsu($Vu32,$Rt32):sat", 31711PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 31712let hasNewValue = 1; 31713let opNewValue = 0; 31714let isAccumulator = 1; 31715let isPseudo = 1; 31716let isCodeGenOnly = 1; 31717let DecoderNamespace = "EXT_mmvec"; 31718let Constraints = "$Vx32 = $Vx32in"; 31719} 31720def V6_vdmpyhsusat_alt : HInst< 31721(outs HvxVR:$Vd32), 31722(ins HvxVR:$Vu32, IntRegs:$Rt32), 31723"$Vd32 = vdmpyhsu($Vu32,$Rt32):sat", 31724PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 31725let hasNewValue = 1; 31726let opNewValue = 0; 31727let isPseudo = 1; 31728let isCodeGenOnly = 1; 31729let DecoderNamespace = "EXT_mmvec"; 31730} 31731def V6_vdmpyhvsat : HInst< 31732(outs HvxVR:$Vd32), 31733(ins HvxVR:$Vu32, HvxVR:$Vv32), 31734"$Vd32.w = vdmpy($Vu32.h,$Vv32.h):sat", 31735tc_d8287c14, TypeCVI_VX_DV>, Enc_45364e, Requires<[UseHVXV60]> { 31736let Inst{7-5} = 0b011; 31737let Inst{13-13} = 0b0; 31738let Inst{31-21} = 0b00011100000; 31739let hasNewValue = 1; 31740let opNewValue = 0; 31741let DecoderNamespace = "EXT_mmvec"; 31742} 31743def V6_vdmpyhvsat_acc : HInst< 31744(outs HvxVR:$Vx32), 31745(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32), 31746"$Vx32.w += vdmpy($Vu32.h,$Vv32.h):sat", 31747tc_08a4f1b6, TypeCVI_VX_DV>, Enc_a7341a, Requires<[UseHVXV60]> { 31748let Inst{7-5} = 0b011; 31749let Inst{13-13} = 0b1; 31750let Inst{31-21} = 0b00011100000; 31751let hasNewValue = 1; 31752let opNewValue = 0; 31753let isAccumulator = 1; 31754let DecoderNamespace = "EXT_mmvec"; 31755let Constraints = "$Vx32 = $Vx32in"; 31756} 31757def V6_vdmpyhvsat_acc_alt : HInst< 31758(outs HvxVR:$Vx32), 31759(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32), 31760"$Vx32 += vdmpyh($Vu32,$Vv32):sat", 31761PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 31762let hasNewValue = 1; 31763let opNewValue = 0; 31764let isAccumulator = 1; 31765let isPseudo = 1; 31766let isCodeGenOnly = 1; 31767let DecoderNamespace = "EXT_mmvec"; 31768let Constraints = "$Vx32 = $Vx32in"; 31769} 31770def V6_vdmpyhvsat_alt : HInst< 31771(outs HvxVR:$Vd32), 31772(ins HvxVR:$Vu32, HvxVR:$Vv32), 31773"$Vd32 = vdmpyh($Vu32,$Vv32):sat", 31774PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 31775let hasNewValue = 1; 31776let opNewValue = 0; 31777let isPseudo = 1; 31778let isCodeGenOnly = 1; 31779let DecoderNamespace = "EXT_mmvec"; 31780} 31781def V6_vdsaduh : HInst< 31782(outs HvxWR:$Vdd32), 31783(ins HvxWR:$Vuu32, IntRegs:$Rt32), 31784"$Vdd32.uw = vdsad($Vuu32.uh,$Rt32.uh)", 31785tc_0b04c6c7, TypeCVI_VX_DV>, Enc_aad80c, Requires<[UseHVXV60]> { 31786let Inst{7-5} = 0b101; 31787let Inst{13-13} = 0b0; 31788let Inst{31-21} = 0b00011001000; 31789let hasNewValue = 1; 31790let opNewValue = 0; 31791let DecoderNamespace = "EXT_mmvec"; 31792} 31793def V6_vdsaduh_acc : HInst< 31794(outs HvxWR:$Vxx32), 31795(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32), 31796"$Vxx32.uw += vdsad($Vuu32.uh,$Rt32.uh)", 31797tc_660769f1, TypeCVI_VX_DV>, Enc_d6990d, Requires<[UseHVXV60]> { 31798let Inst{7-5} = 0b000; 31799let Inst{13-13} = 0b1; 31800let Inst{31-21} = 0b00011001011; 31801let hasNewValue = 1; 31802let opNewValue = 0; 31803let isAccumulator = 1; 31804let DecoderNamespace = "EXT_mmvec"; 31805let Constraints = "$Vxx32 = $Vxx32in"; 31806} 31807def V6_vdsaduh_acc_alt : HInst< 31808(outs HvxWR:$Vxx32), 31809(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32), 31810"$Vxx32 += vdsaduh($Vuu32,$Rt32)", 31811PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 31812let hasNewValue = 1; 31813let opNewValue = 0; 31814let isAccumulator = 1; 31815let isPseudo = 1; 31816let isCodeGenOnly = 1; 31817let DecoderNamespace = "EXT_mmvec"; 31818let Constraints = "$Vxx32 = $Vxx32in"; 31819} 31820def V6_vdsaduh_alt : HInst< 31821(outs HvxWR:$Vdd32), 31822(ins HvxWR:$Vuu32, IntRegs:$Rt32), 31823"$Vdd32 = vdsaduh($Vuu32,$Rt32)", 31824PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 31825let hasNewValue = 1; 31826let opNewValue = 0; 31827let isPseudo = 1; 31828let isCodeGenOnly = 1; 31829let DecoderNamespace = "EXT_mmvec"; 31830} 31831def V6_veqb : HInst< 31832(outs HvxQR:$Qd4), 31833(ins HvxVR:$Vu32, HvxVR:$Vv32), 31834"$Qd4 = vcmp.eq($Vu32.b,$Vv32.b)", 31835tc_56c4f9fe, TypeCVI_VA>, Enc_95441f, Requires<[UseHVXV60]> { 31836let Inst{7-2} = 0b000000; 31837let Inst{13-13} = 0b0; 31838let Inst{31-21} = 0b00011111100; 31839let hasNewValue = 1; 31840let opNewValue = 0; 31841let DecoderNamespace = "EXT_mmvec"; 31842} 31843def V6_veqb_and : HInst< 31844(outs HvxQR:$Qx4), 31845(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), 31846"$Qx4 &= vcmp.eq($Vu32.b,$Vv32.b)", 31847tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> { 31848let Inst{7-2} = 0b000000; 31849let Inst{13-13} = 0b1; 31850let Inst{31-21} = 0b00011100100; 31851let DecoderNamespace = "EXT_mmvec"; 31852let Constraints = "$Qx4 = $Qx4in"; 31853} 31854def V6_veqb_or : HInst< 31855(outs HvxQR:$Qx4), 31856(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), 31857"$Qx4 |= vcmp.eq($Vu32.b,$Vv32.b)", 31858tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> { 31859let Inst{7-2} = 0b010000; 31860let Inst{13-13} = 0b1; 31861let Inst{31-21} = 0b00011100100; 31862let isAccumulator = 1; 31863let DecoderNamespace = "EXT_mmvec"; 31864let Constraints = "$Qx4 = $Qx4in"; 31865} 31866def V6_veqb_xor : HInst< 31867(outs HvxQR:$Qx4), 31868(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), 31869"$Qx4 ^= vcmp.eq($Vu32.b,$Vv32.b)", 31870tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> { 31871let Inst{7-2} = 0b100000; 31872let Inst{13-13} = 0b1; 31873let Inst{31-21} = 0b00011100100; 31874let DecoderNamespace = "EXT_mmvec"; 31875let Constraints = "$Qx4 = $Qx4in"; 31876} 31877def V6_veqh : HInst< 31878(outs HvxQR:$Qd4), 31879(ins HvxVR:$Vu32, HvxVR:$Vv32), 31880"$Qd4 = vcmp.eq($Vu32.h,$Vv32.h)", 31881tc_56c4f9fe, TypeCVI_VA>, Enc_95441f, Requires<[UseHVXV60]> { 31882let Inst{7-2} = 0b000001; 31883let Inst{13-13} = 0b0; 31884let Inst{31-21} = 0b00011111100; 31885let hasNewValue = 1; 31886let opNewValue = 0; 31887let DecoderNamespace = "EXT_mmvec"; 31888} 31889def V6_veqh_and : HInst< 31890(outs HvxQR:$Qx4), 31891(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), 31892"$Qx4 &= vcmp.eq($Vu32.h,$Vv32.h)", 31893tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> { 31894let Inst{7-2} = 0b000001; 31895let Inst{13-13} = 0b1; 31896let Inst{31-21} = 0b00011100100; 31897let DecoderNamespace = "EXT_mmvec"; 31898let Constraints = "$Qx4 = $Qx4in"; 31899} 31900def V6_veqh_or : HInst< 31901(outs HvxQR:$Qx4), 31902(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), 31903"$Qx4 |= vcmp.eq($Vu32.h,$Vv32.h)", 31904tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> { 31905let Inst{7-2} = 0b010001; 31906let Inst{13-13} = 0b1; 31907let Inst{31-21} = 0b00011100100; 31908let isAccumulator = 1; 31909let DecoderNamespace = "EXT_mmvec"; 31910let Constraints = "$Qx4 = $Qx4in"; 31911} 31912def V6_veqh_xor : HInst< 31913(outs HvxQR:$Qx4), 31914(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), 31915"$Qx4 ^= vcmp.eq($Vu32.h,$Vv32.h)", 31916tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> { 31917let Inst{7-2} = 0b100001; 31918let Inst{13-13} = 0b1; 31919let Inst{31-21} = 0b00011100100; 31920let DecoderNamespace = "EXT_mmvec"; 31921let Constraints = "$Qx4 = $Qx4in"; 31922} 31923def V6_veqw : HInst< 31924(outs HvxQR:$Qd4), 31925(ins HvxVR:$Vu32, HvxVR:$Vv32), 31926"$Qd4 = vcmp.eq($Vu32.w,$Vv32.w)", 31927tc_56c4f9fe, TypeCVI_VA>, Enc_95441f, Requires<[UseHVXV60]> { 31928let Inst{7-2} = 0b000010; 31929let Inst{13-13} = 0b0; 31930let Inst{31-21} = 0b00011111100; 31931let hasNewValue = 1; 31932let opNewValue = 0; 31933let DecoderNamespace = "EXT_mmvec"; 31934} 31935def V6_veqw_and : HInst< 31936(outs HvxQR:$Qx4), 31937(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), 31938"$Qx4 &= vcmp.eq($Vu32.w,$Vv32.w)", 31939tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> { 31940let Inst{7-2} = 0b000010; 31941let Inst{13-13} = 0b1; 31942let Inst{31-21} = 0b00011100100; 31943let DecoderNamespace = "EXT_mmvec"; 31944let Constraints = "$Qx4 = $Qx4in"; 31945} 31946def V6_veqw_or : HInst< 31947(outs HvxQR:$Qx4), 31948(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), 31949"$Qx4 |= vcmp.eq($Vu32.w,$Vv32.w)", 31950tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> { 31951let Inst{7-2} = 0b010010; 31952let Inst{13-13} = 0b1; 31953let Inst{31-21} = 0b00011100100; 31954let isAccumulator = 1; 31955let DecoderNamespace = "EXT_mmvec"; 31956let Constraints = "$Qx4 = $Qx4in"; 31957} 31958def V6_veqw_xor : HInst< 31959(outs HvxQR:$Qx4), 31960(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), 31961"$Qx4 ^= vcmp.eq($Vu32.w,$Vv32.w)", 31962tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> { 31963let Inst{7-2} = 0b100010; 31964let Inst{13-13} = 0b1; 31965let Inst{31-21} = 0b00011100100; 31966let DecoderNamespace = "EXT_mmvec"; 31967let Constraints = "$Qx4 = $Qx4in"; 31968} 31969def V6_vgathermh : HInst< 31970(outs), 31971(ins IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32), 31972"vtmp.h = vgather($Rt32,$Mu2,$Vv32.h).h", 31973tc_e8797b98, TypeCVI_GATHER>, Enc_8b8927, Requires<[UseHVXV65]> { 31974let Inst{12-5} = 0b00001000; 31975let Inst{31-21} = 0b00101111000; 31976let hasNewValue = 1; 31977let opNewValue = 0; 31978let accessSize = HalfWordAccess; 31979let isCVLoad = 1; 31980let hasTmpDst = 1; 31981let mayLoad = 1; 31982let Defs = [VTMP]; 31983let DecoderNamespace = "EXT_mmvec"; 31984} 31985def V6_vgathermhq : HInst< 31986(outs), 31987(ins HvxQR:$Qs4, IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32), 31988"if ($Qs4) vtmp.h = vgather($Rt32,$Mu2,$Vv32.h).h", 31989tc_05ac6f98, TypeCVI_GATHER>, Enc_158beb, Requires<[UseHVXV65]> { 31990let Inst{12-7} = 0b001010; 31991let Inst{31-21} = 0b00101111000; 31992let hasNewValue = 1; 31993let opNewValue = 0; 31994let accessSize = HalfWordAccess; 31995let isCVLoad = 1; 31996let hasTmpDst = 1; 31997let mayLoad = 1; 31998let Defs = [VTMP]; 31999let DecoderNamespace = "EXT_mmvec"; 32000} 32001def V6_vgathermhw : HInst< 32002(outs), 32003(ins IntRegs:$Rt32, ModRegs:$Mu2, HvxWR:$Vvv32), 32004"vtmp.h = vgather($Rt32,$Mu2,$Vvv32.w).h", 32005tc_05058f6f, TypeCVI_GATHER>, Enc_28dcbb, Requires<[UseHVXV65]> { 32006let Inst{12-5} = 0b00010000; 32007let Inst{31-21} = 0b00101111000; 32008let hasNewValue = 1; 32009let opNewValue = 0; 32010let accessSize = HalfWordAccess; 32011let isCVLoad = 1; 32012let hasTmpDst = 1; 32013let mayLoad = 1; 32014let Defs = [VTMP]; 32015let DecoderNamespace = "EXT_mmvec"; 32016} 32017def V6_vgathermhwq : HInst< 32018(outs), 32019(ins HvxQR:$Qs4, IntRegs:$Rt32, ModRegs:$Mu2, HvxWR:$Vvv32), 32020"if ($Qs4) vtmp.h = vgather($Rt32,$Mu2,$Vvv32.w).h", 32021tc_fd7610da, TypeCVI_GATHER>, Enc_4e4a80, Requires<[UseHVXV65]> { 32022let Inst{12-7} = 0b001100; 32023let Inst{31-21} = 0b00101111000; 32024let hasNewValue = 1; 32025let opNewValue = 0; 32026let accessSize = HalfWordAccess; 32027let isCVLoad = 1; 32028let hasTmpDst = 1; 32029let mayLoad = 1; 32030let Defs = [VTMP]; 32031let DecoderNamespace = "EXT_mmvec"; 32032} 32033def V6_vgathermw : HInst< 32034(outs), 32035(ins IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32), 32036"vtmp.w = vgather($Rt32,$Mu2,$Vv32.w).w", 32037tc_e8797b98, TypeCVI_GATHER>, Enc_8b8927, Requires<[UseHVXV65]> { 32038let Inst{12-5} = 0b00000000; 32039let Inst{31-21} = 0b00101111000; 32040let hasNewValue = 1; 32041let opNewValue = 0; 32042let accessSize = WordAccess; 32043let isCVLoad = 1; 32044let hasTmpDst = 1; 32045let mayLoad = 1; 32046let Defs = [VTMP]; 32047let DecoderNamespace = "EXT_mmvec"; 32048} 32049def V6_vgathermwq : HInst< 32050(outs), 32051(ins HvxQR:$Qs4, IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32), 32052"if ($Qs4) vtmp.w = vgather($Rt32,$Mu2,$Vv32.w).w", 32053tc_05ac6f98, TypeCVI_GATHER>, Enc_158beb, Requires<[UseHVXV65]> { 32054let Inst{12-7} = 0b001000; 32055let Inst{31-21} = 0b00101111000; 32056let hasNewValue = 1; 32057let opNewValue = 0; 32058let accessSize = WordAccess; 32059let isCVLoad = 1; 32060let hasTmpDst = 1; 32061let mayLoad = 1; 32062let Defs = [VTMP]; 32063let DecoderNamespace = "EXT_mmvec"; 32064} 32065def V6_vgtb : HInst< 32066(outs HvxQR:$Qd4), 32067(ins HvxVR:$Vu32, HvxVR:$Vv32), 32068"$Qd4 = vcmp.gt($Vu32.b,$Vv32.b)", 32069tc_56c4f9fe, TypeCVI_VA>, Enc_95441f, Requires<[UseHVXV60]> { 32070let Inst{7-2} = 0b000100; 32071let Inst{13-13} = 0b0; 32072let Inst{31-21} = 0b00011111100; 32073let hasNewValue = 1; 32074let opNewValue = 0; 32075let DecoderNamespace = "EXT_mmvec"; 32076} 32077def V6_vgtb_and : HInst< 32078(outs HvxQR:$Qx4), 32079(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), 32080"$Qx4 &= vcmp.gt($Vu32.b,$Vv32.b)", 32081tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> { 32082let Inst{7-2} = 0b000100; 32083let Inst{13-13} = 0b1; 32084let Inst{31-21} = 0b00011100100; 32085let DecoderNamespace = "EXT_mmvec"; 32086let Constraints = "$Qx4 = $Qx4in"; 32087} 32088def V6_vgtb_or : HInst< 32089(outs HvxQR:$Qx4), 32090(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), 32091"$Qx4 |= vcmp.gt($Vu32.b,$Vv32.b)", 32092tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> { 32093let Inst{7-2} = 0b010100; 32094let Inst{13-13} = 0b1; 32095let Inst{31-21} = 0b00011100100; 32096let isAccumulator = 1; 32097let DecoderNamespace = "EXT_mmvec"; 32098let Constraints = "$Qx4 = $Qx4in"; 32099} 32100def V6_vgtb_xor : HInst< 32101(outs HvxQR:$Qx4), 32102(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), 32103"$Qx4 ^= vcmp.gt($Vu32.b,$Vv32.b)", 32104tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> { 32105let Inst{7-2} = 0b100100; 32106let Inst{13-13} = 0b1; 32107let Inst{31-21} = 0b00011100100; 32108let DecoderNamespace = "EXT_mmvec"; 32109let Constraints = "$Qx4 = $Qx4in"; 32110} 32111def V6_vgth : HInst< 32112(outs HvxQR:$Qd4), 32113(ins HvxVR:$Vu32, HvxVR:$Vv32), 32114"$Qd4 = vcmp.gt($Vu32.h,$Vv32.h)", 32115tc_56c4f9fe, TypeCVI_VA>, Enc_95441f, Requires<[UseHVXV60]> { 32116let Inst{7-2} = 0b000101; 32117let Inst{13-13} = 0b0; 32118let Inst{31-21} = 0b00011111100; 32119let hasNewValue = 1; 32120let opNewValue = 0; 32121let DecoderNamespace = "EXT_mmvec"; 32122} 32123def V6_vgth_and : HInst< 32124(outs HvxQR:$Qx4), 32125(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), 32126"$Qx4 &= vcmp.gt($Vu32.h,$Vv32.h)", 32127tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> { 32128let Inst{7-2} = 0b000101; 32129let Inst{13-13} = 0b1; 32130let Inst{31-21} = 0b00011100100; 32131let DecoderNamespace = "EXT_mmvec"; 32132let Constraints = "$Qx4 = $Qx4in"; 32133} 32134def V6_vgth_or : HInst< 32135(outs HvxQR:$Qx4), 32136(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), 32137"$Qx4 |= vcmp.gt($Vu32.h,$Vv32.h)", 32138tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> { 32139let Inst{7-2} = 0b010101; 32140let Inst{13-13} = 0b1; 32141let Inst{31-21} = 0b00011100100; 32142let isAccumulator = 1; 32143let DecoderNamespace = "EXT_mmvec"; 32144let Constraints = "$Qx4 = $Qx4in"; 32145} 32146def V6_vgth_xor : HInst< 32147(outs HvxQR:$Qx4), 32148(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), 32149"$Qx4 ^= vcmp.gt($Vu32.h,$Vv32.h)", 32150tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> { 32151let Inst{7-2} = 0b100101; 32152let Inst{13-13} = 0b1; 32153let Inst{31-21} = 0b00011100100; 32154let DecoderNamespace = "EXT_mmvec"; 32155let Constraints = "$Qx4 = $Qx4in"; 32156} 32157def V6_vgtub : HInst< 32158(outs HvxQR:$Qd4), 32159(ins HvxVR:$Vu32, HvxVR:$Vv32), 32160"$Qd4 = vcmp.gt($Vu32.ub,$Vv32.ub)", 32161tc_56c4f9fe, TypeCVI_VA>, Enc_95441f, Requires<[UseHVXV60]> { 32162let Inst{7-2} = 0b001000; 32163let Inst{13-13} = 0b0; 32164let Inst{31-21} = 0b00011111100; 32165let hasNewValue = 1; 32166let opNewValue = 0; 32167let DecoderNamespace = "EXT_mmvec"; 32168} 32169def V6_vgtub_and : HInst< 32170(outs HvxQR:$Qx4), 32171(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), 32172"$Qx4 &= vcmp.gt($Vu32.ub,$Vv32.ub)", 32173tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> { 32174let Inst{7-2} = 0b001000; 32175let Inst{13-13} = 0b1; 32176let Inst{31-21} = 0b00011100100; 32177let DecoderNamespace = "EXT_mmvec"; 32178let Constraints = "$Qx4 = $Qx4in"; 32179} 32180def V6_vgtub_or : HInst< 32181(outs HvxQR:$Qx4), 32182(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), 32183"$Qx4 |= vcmp.gt($Vu32.ub,$Vv32.ub)", 32184tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> { 32185let Inst{7-2} = 0b011000; 32186let Inst{13-13} = 0b1; 32187let Inst{31-21} = 0b00011100100; 32188let isAccumulator = 1; 32189let DecoderNamespace = "EXT_mmvec"; 32190let Constraints = "$Qx4 = $Qx4in"; 32191} 32192def V6_vgtub_xor : HInst< 32193(outs HvxQR:$Qx4), 32194(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), 32195"$Qx4 ^= vcmp.gt($Vu32.ub,$Vv32.ub)", 32196tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> { 32197let Inst{7-2} = 0b101000; 32198let Inst{13-13} = 0b1; 32199let Inst{31-21} = 0b00011100100; 32200let DecoderNamespace = "EXT_mmvec"; 32201let Constraints = "$Qx4 = $Qx4in"; 32202} 32203def V6_vgtuh : HInst< 32204(outs HvxQR:$Qd4), 32205(ins HvxVR:$Vu32, HvxVR:$Vv32), 32206"$Qd4 = vcmp.gt($Vu32.uh,$Vv32.uh)", 32207tc_56c4f9fe, TypeCVI_VA>, Enc_95441f, Requires<[UseHVXV60]> { 32208let Inst{7-2} = 0b001001; 32209let Inst{13-13} = 0b0; 32210let Inst{31-21} = 0b00011111100; 32211let hasNewValue = 1; 32212let opNewValue = 0; 32213let DecoderNamespace = "EXT_mmvec"; 32214} 32215def V6_vgtuh_and : HInst< 32216(outs HvxQR:$Qx4), 32217(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), 32218"$Qx4 &= vcmp.gt($Vu32.uh,$Vv32.uh)", 32219tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> { 32220let Inst{7-2} = 0b001001; 32221let Inst{13-13} = 0b1; 32222let Inst{31-21} = 0b00011100100; 32223let DecoderNamespace = "EXT_mmvec"; 32224let Constraints = "$Qx4 = $Qx4in"; 32225} 32226def V6_vgtuh_or : HInst< 32227(outs HvxQR:$Qx4), 32228(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), 32229"$Qx4 |= vcmp.gt($Vu32.uh,$Vv32.uh)", 32230tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> { 32231let Inst{7-2} = 0b011001; 32232let Inst{13-13} = 0b1; 32233let Inst{31-21} = 0b00011100100; 32234let isAccumulator = 1; 32235let DecoderNamespace = "EXT_mmvec"; 32236let Constraints = "$Qx4 = $Qx4in"; 32237} 32238def V6_vgtuh_xor : HInst< 32239(outs HvxQR:$Qx4), 32240(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), 32241"$Qx4 ^= vcmp.gt($Vu32.uh,$Vv32.uh)", 32242tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> { 32243let Inst{7-2} = 0b101001; 32244let Inst{13-13} = 0b1; 32245let Inst{31-21} = 0b00011100100; 32246let DecoderNamespace = "EXT_mmvec"; 32247let Constraints = "$Qx4 = $Qx4in"; 32248} 32249def V6_vgtuw : HInst< 32250(outs HvxQR:$Qd4), 32251(ins HvxVR:$Vu32, HvxVR:$Vv32), 32252"$Qd4 = vcmp.gt($Vu32.uw,$Vv32.uw)", 32253tc_56c4f9fe, TypeCVI_VA>, Enc_95441f, Requires<[UseHVXV60]> { 32254let Inst{7-2} = 0b001010; 32255let Inst{13-13} = 0b0; 32256let Inst{31-21} = 0b00011111100; 32257let hasNewValue = 1; 32258let opNewValue = 0; 32259let DecoderNamespace = "EXT_mmvec"; 32260} 32261def V6_vgtuw_and : HInst< 32262(outs HvxQR:$Qx4), 32263(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), 32264"$Qx4 &= vcmp.gt($Vu32.uw,$Vv32.uw)", 32265tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> { 32266let Inst{7-2} = 0b001010; 32267let Inst{13-13} = 0b1; 32268let Inst{31-21} = 0b00011100100; 32269let DecoderNamespace = "EXT_mmvec"; 32270let Constraints = "$Qx4 = $Qx4in"; 32271} 32272def V6_vgtuw_or : HInst< 32273(outs HvxQR:$Qx4), 32274(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), 32275"$Qx4 |= vcmp.gt($Vu32.uw,$Vv32.uw)", 32276tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> { 32277let Inst{7-2} = 0b011010; 32278let Inst{13-13} = 0b1; 32279let Inst{31-21} = 0b00011100100; 32280let isAccumulator = 1; 32281let DecoderNamespace = "EXT_mmvec"; 32282let Constraints = "$Qx4 = $Qx4in"; 32283} 32284def V6_vgtuw_xor : HInst< 32285(outs HvxQR:$Qx4), 32286(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), 32287"$Qx4 ^= vcmp.gt($Vu32.uw,$Vv32.uw)", 32288tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> { 32289let Inst{7-2} = 0b101010; 32290let Inst{13-13} = 0b1; 32291let Inst{31-21} = 0b00011100100; 32292let DecoderNamespace = "EXT_mmvec"; 32293let Constraints = "$Qx4 = $Qx4in"; 32294} 32295def V6_vgtw : HInst< 32296(outs HvxQR:$Qd4), 32297(ins HvxVR:$Vu32, HvxVR:$Vv32), 32298"$Qd4 = vcmp.gt($Vu32.w,$Vv32.w)", 32299tc_56c4f9fe, TypeCVI_VA>, Enc_95441f, Requires<[UseHVXV60]> { 32300let Inst{7-2} = 0b000110; 32301let Inst{13-13} = 0b0; 32302let Inst{31-21} = 0b00011111100; 32303let hasNewValue = 1; 32304let opNewValue = 0; 32305let DecoderNamespace = "EXT_mmvec"; 32306} 32307def V6_vgtw_and : HInst< 32308(outs HvxQR:$Qx4), 32309(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), 32310"$Qx4 &= vcmp.gt($Vu32.w,$Vv32.w)", 32311tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> { 32312let Inst{7-2} = 0b000110; 32313let Inst{13-13} = 0b1; 32314let Inst{31-21} = 0b00011100100; 32315let DecoderNamespace = "EXT_mmvec"; 32316let Constraints = "$Qx4 = $Qx4in"; 32317} 32318def V6_vgtw_or : HInst< 32319(outs HvxQR:$Qx4), 32320(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), 32321"$Qx4 |= vcmp.gt($Vu32.w,$Vv32.w)", 32322tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> { 32323let Inst{7-2} = 0b010110; 32324let Inst{13-13} = 0b1; 32325let Inst{31-21} = 0b00011100100; 32326let isAccumulator = 1; 32327let DecoderNamespace = "EXT_mmvec"; 32328let Constraints = "$Qx4 = $Qx4in"; 32329} 32330def V6_vgtw_xor : HInst< 32331(outs HvxQR:$Qx4), 32332(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), 32333"$Qx4 ^= vcmp.gt($Vu32.w,$Vv32.w)", 32334tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> { 32335let Inst{7-2} = 0b100110; 32336let Inst{13-13} = 0b1; 32337let Inst{31-21} = 0b00011100100; 32338let DecoderNamespace = "EXT_mmvec"; 32339let Constraints = "$Qx4 = $Qx4in"; 32340} 32341def V6_vhist : HInst< 32342(outs), 32343(ins), 32344"vhist", 32345tc_1381a97c, TypeCVI_HIST>, Enc_e3b0c4, Requires<[UseHVXV60]> { 32346let Inst{13-0} = 0b10000010000000; 32347let Inst{31-16} = 0b0001111000000000; 32348let DecoderNamespace = "EXT_mmvec"; 32349} 32350def V6_vhistq : HInst< 32351(outs), 32352(ins HvxQR:$Qv4), 32353"vhist($Qv4)", 32354tc_e3f68a46, TypeCVI_HIST>, Enc_217147, Requires<[UseHVXV60]> { 32355let Inst{13-0} = 0b10000010000000; 32356let Inst{21-16} = 0b000010; 32357let Inst{31-24} = 0b00011110; 32358let DecoderNamespace = "EXT_mmvec"; 32359} 32360def V6_vinsertwr : HInst< 32361(outs HvxVR:$Vx32), 32362(ins HvxVR:$Vx32in, IntRegs:$Rt32), 32363"$Vx32.w = vinsert($Rt32)", 32364tc_ac4046bc, TypeCVI_VX_LATE>, Enc_569cfe, Requires<[UseHVXV60]> { 32365let Inst{13-5} = 0b100000001; 32366let Inst{31-21} = 0b00011001101; 32367let hasNewValue = 1; 32368let opNewValue = 0; 32369let DecoderNamespace = "EXT_mmvec"; 32370let Constraints = "$Vx32 = $Vx32in"; 32371} 32372def V6_vlalignb : HInst< 32373(outs HvxVR:$Vd32), 32374(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8), 32375"$Vd32 = vlalign($Vu32,$Vv32,$Rt8)", 32376tc_56e64202, TypeCVI_VP>, Enc_a30110, Requires<[UseHVXV60]> { 32377let Inst{7-5} = 0b001; 32378let Inst{13-13} = 0b0; 32379let Inst{31-24} = 0b00011011; 32380let hasNewValue = 1; 32381let opNewValue = 0; 32382let DecoderNamespace = "EXT_mmvec"; 32383} 32384def V6_vlalignbi : HInst< 32385(outs HvxVR:$Vd32), 32386(ins HvxVR:$Vu32, HvxVR:$Vv32, u3_0Imm:$Ii), 32387"$Vd32 = vlalign($Vu32,$Vv32,#$Ii)", 32388tc_56e64202, TypeCVI_VP>, Enc_0b2e5b, Requires<[UseHVXV60]> { 32389let Inst{13-13} = 0b1; 32390let Inst{31-21} = 0b00011110011; 32391let hasNewValue = 1; 32392let opNewValue = 0; 32393let DecoderNamespace = "EXT_mmvec"; 32394} 32395def V6_vlsrb : HInst< 32396(outs HvxVR:$Vd32), 32397(ins HvxVR:$Vu32, IntRegs:$Rt32), 32398"$Vd32.ub = vlsr($Vu32.ub,$Rt32)", 32399tc_7417e785, TypeCVI_VS>, Enc_b087ac, Requires<[UseHVXV62]> { 32400let Inst{7-5} = 0b011; 32401let Inst{13-13} = 0b0; 32402let Inst{31-21} = 0b00011001100; 32403let hasNewValue = 1; 32404let opNewValue = 0; 32405let DecoderNamespace = "EXT_mmvec"; 32406} 32407def V6_vlsrh : HInst< 32408(outs HvxVR:$Vd32), 32409(ins HvxVR:$Vu32, IntRegs:$Rt32), 32410"$Vd32.uh = vlsr($Vu32.uh,$Rt32)", 32411tc_7417e785, TypeCVI_VS>, Enc_b087ac, Requires<[UseHVXV60]> { 32412let Inst{7-5} = 0b010; 32413let Inst{13-13} = 0b0; 32414let Inst{31-21} = 0b00011001100; 32415let hasNewValue = 1; 32416let opNewValue = 0; 32417let DecoderNamespace = "EXT_mmvec"; 32418} 32419def V6_vlsrh_alt : HInst< 32420(outs HvxVR:$Vd32), 32421(ins HvxVR:$Vu32, IntRegs:$Rt32), 32422"$Vd32 = vlsrh($Vu32,$Rt32)", 32423PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 32424let hasNewValue = 1; 32425let opNewValue = 0; 32426let isPseudo = 1; 32427let isCodeGenOnly = 1; 32428let DecoderNamespace = "EXT_mmvec"; 32429} 32430def V6_vlsrhv : HInst< 32431(outs HvxVR:$Vd32), 32432(ins HvxVR:$Vu32, HvxVR:$Vv32), 32433"$Vd32.h = vlsr($Vu32.h,$Vv32.h)", 32434tc_05ca8cfd, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV60]> { 32435let Inst{7-5} = 0b010; 32436let Inst{13-13} = 0b0; 32437let Inst{31-21} = 0b00011111101; 32438let hasNewValue = 1; 32439let opNewValue = 0; 32440let DecoderNamespace = "EXT_mmvec"; 32441} 32442def V6_vlsrhv_alt : HInst< 32443(outs HvxVR:$Vd32), 32444(ins HvxVR:$Vu32, HvxVR:$Vv32), 32445"$Vd32 = vlsrh($Vu32,$Vv32)", 32446PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 32447let hasNewValue = 1; 32448let opNewValue = 0; 32449let isPseudo = 1; 32450let isCodeGenOnly = 1; 32451let DecoderNamespace = "EXT_mmvec"; 32452} 32453def V6_vlsrw : HInst< 32454(outs HvxVR:$Vd32), 32455(ins HvxVR:$Vu32, IntRegs:$Rt32), 32456"$Vd32.uw = vlsr($Vu32.uw,$Rt32)", 32457tc_7417e785, TypeCVI_VS>, Enc_b087ac, Requires<[UseHVXV60]> { 32458let Inst{7-5} = 0b001; 32459let Inst{13-13} = 0b0; 32460let Inst{31-21} = 0b00011001100; 32461let hasNewValue = 1; 32462let opNewValue = 0; 32463let DecoderNamespace = "EXT_mmvec"; 32464} 32465def V6_vlsrw_alt : HInst< 32466(outs HvxVR:$Vd32), 32467(ins HvxVR:$Vu32, IntRegs:$Rt32), 32468"$Vd32 = vlsrw($Vu32,$Rt32)", 32469PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 32470let hasNewValue = 1; 32471let opNewValue = 0; 32472let isPseudo = 1; 32473let isCodeGenOnly = 1; 32474let DecoderNamespace = "EXT_mmvec"; 32475} 32476def V6_vlsrwv : HInst< 32477(outs HvxVR:$Vd32), 32478(ins HvxVR:$Vu32, HvxVR:$Vv32), 32479"$Vd32.w = vlsr($Vu32.w,$Vv32.w)", 32480tc_05ca8cfd, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV60]> { 32481let Inst{7-5} = 0b001; 32482let Inst{13-13} = 0b0; 32483let Inst{31-21} = 0b00011111101; 32484let hasNewValue = 1; 32485let opNewValue = 0; 32486let DecoderNamespace = "EXT_mmvec"; 32487} 32488def V6_vlsrwv_alt : HInst< 32489(outs HvxVR:$Vd32), 32490(ins HvxVR:$Vu32, HvxVR:$Vv32), 32491"$Vd32 = vlsrw($Vu32,$Vv32)", 32492PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 32493let hasNewValue = 1; 32494let opNewValue = 0; 32495let isPseudo = 1; 32496let isCodeGenOnly = 1; 32497let DecoderNamespace = "EXT_mmvec"; 32498} 32499def V6_vlut4 : HInst< 32500(outs HvxVR:$Vd32), 32501(ins HvxVR:$Vu32, DoubleRegs:$Rtt32), 32502"$Vd32.h = vlut4($Vu32.uh,$Rtt32.h)", 32503tc_f1de44ef, TypeCVI_VX_DV>, Enc_263841, Requires<[UseHVXV65]> { 32504let Inst{7-5} = 0b100; 32505let Inst{13-13} = 0b0; 32506let Inst{31-21} = 0b00011001011; 32507let hasNewValue = 1; 32508let opNewValue = 0; 32509let DecoderNamespace = "EXT_mmvec"; 32510} 32511def V6_vlutvvb : HInst< 32512(outs HvxVR:$Vd32), 32513(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8), 32514"$Vd32.b = vlut32($Vu32.b,$Vv32.b,$Rt8)", 32515tc_56e64202, TypeCVI_VP>, Enc_a30110, Requires<[UseHVXV60]> { 32516let Inst{7-5} = 0b001; 32517let Inst{13-13} = 0b1; 32518let Inst{31-24} = 0b00011011; 32519let hasNewValue = 1; 32520let opNewValue = 0; 32521let DecoderNamespace = "EXT_mmvec"; 32522} 32523def V6_vlutvvb_nm : HInst< 32524(outs HvxVR:$Vd32), 32525(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8), 32526"$Vd32.b = vlut32($Vu32.b,$Vv32.b,$Rt8):nomatch", 32527tc_56e64202, TypeCVI_VP>, Enc_a30110, Requires<[UseHVXV62]> { 32528let Inst{7-5} = 0b011; 32529let Inst{13-13} = 0b0; 32530let Inst{31-24} = 0b00011000; 32531let hasNewValue = 1; 32532let opNewValue = 0; 32533let DecoderNamespace = "EXT_mmvec"; 32534} 32535def V6_vlutvvb_oracc : HInst< 32536(outs HvxVR:$Vx32), 32537(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8), 32538"$Vx32.b |= vlut32($Vu32.b,$Vv32.b,$Rt8)", 32539tc_9d1dc972, TypeCVI_VP_VS>, Enc_245865, Requires<[UseHVXV60]> { 32540let Inst{7-5} = 0b101; 32541let Inst{13-13} = 0b1; 32542let Inst{31-24} = 0b00011011; 32543let hasNewValue = 1; 32544let opNewValue = 0; 32545let isAccumulator = 1; 32546let DecoderNamespace = "EXT_mmvec"; 32547let Constraints = "$Vx32 = $Vx32in"; 32548} 32549def V6_vlutvvb_oracci : HInst< 32550(outs HvxVR:$Vx32), 32551(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32, u3_0Imm:$Ii), 32552"$Vx32.b |= vlut32($Vu32.b,$Vv32.b,#$Ii)", 32553tc_9d1dc972, TypeCVI_VP_VS>, Enc_cd4705, Requires<[UseHVXV62]> { 32554let Inst{13-13} = 0b1; 32555let Inst{31-21} = 0b00011100110; 32556let hasNewValue = 1; 32557let opNewValue = 0; 32558let isAccumulator = 1; 32559let DecoderNamespace = "EXT_mmvec"; 32560let Constraints = "$Vx32 = $Vx32in"; 32561} 32562def V6_vlutvvbi : HInst< 32563(outs HvxVR:$Vd32), 32564(ins HvxVR:$Vu32, HvxVR:$Vv32, u3_0Imm:$Ii), 32565"$Vd32.b = vlut32($Vu32.b,$Vv32.b,#$Ii)", 32566tc_56e64202, TypeCVI_VP>, Enc_0b2e5b, Requires<[UseHVXV62]> { 32567let Inst{13-13} = 0b0; 32568let Inst{31-21} = 0b00011110001; 32569let hasNewValue = 1; 32570let opNewValue = 0; 32571let DecoderNamespace = "EXT_mmvec"; 32572} 32573def V6_vlutvwh : HInst< 32574(outs HvxWR:$Vdd32), 32575(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8), 32576"$Vdd32.h = vlut16($Vu32.b,$Vv32.h,$Rt8)", 32577tc_87adc037, TypeCVI_VP_VS>, Enc_24a7dc, Requires<[UseHVXV60]> { 32578let Inst{7-5} = 0b110; 32579let Inst{13-13} = 0b1; 32580let Inst{31-24} = 0b00011011; 32581let hasNewValue = 1; 32582let opNewValue = 0; 32583let DecoderNamespace = "EXT_mmvec"; 32584} 32585def V6_vlutvwh_nm : HInst< 32586(outs HvxWR:$Vdd32), 32587(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8), 32588"$Vdd32.h = vlut16($Vu32.b,$Vv32.h,$Rt8):nomatch", 32589tc_87adc037, TypeCVI_VP_VS>, Enc_24a7dc, Requires<[UseHVXV62]> { 32590let Inst{7-5} = 0b100; 32591let Inst{13-13} = 0b0; 32592let Inst{31-24} = 0b00011000; 32593let hasNewValue = 1; 32594let opNewValue = 0; 32595let DecoderNamespace = "EXT_mmvec"; 32596} 32597def V6_vlutvwh_oracc : HInst< 32598(outs HvxWR:$Vxx32), 32599(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8), 32600"$Vxx32.h |= vlut16($Vu32.b,$Vv32.h,$Rt8)", 32601tc_9d1dc972, TypeCVI_VP_VS>, Enc_7b523d, Requires<[UseHVXV60]> { 32602let Inst{7-5} = 0b111; 32603let Inst{13-13} = 0b1; 32604let Inst{31-24} = 0b00011011; 32605let hasNewValue = 1; 32606let opNewValue = 0; 32607let isAccumulator = 1; 32608let DecoderNamespace = "EXT_mmvec"; 32609let Constraints = "$Vxx32 = $Vxx32in"; 32610} 32611def V6_vlutvwh_oracci : HInst< 32612(outs HvxWR:$Vxx32), 32613(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32, u3_0Imm:$Ii), 32614"$Vxx32.h |= vlut16($Vu32.b,$Vv32.h,#$Ii)", 32615tc_9d1dc972, TypeCVI_VP_VS>, Enc_1178da, Requires<[UseHVXV62]> { 32616let Inst{13-13} = 0b1; 32617let Inst{31-21} = 0b00011100111; 32618let hasNewValue = 1; 32619let opNewValue = 0; 32620let isAccumulator = 1; 32621let DecoderNamespace = "EXT_mmvec"; 32622let Constraints = "$Vxx32 = $Vxx32in"; 32623} 32624def V6_vlutvwhi : HInst< 32625(outs HvxWR:$Vdd32), 32626(ins HvxVR:$Vu32, HvxVR:$Vv32, u3_0Imm:$Ii), 32627"$Vdd32.h = vlut16($Vu32.b,$Vv32.h,#$Ii)", 32628tc_87adc037, TypeCVI_VP_VS>, Enc_4b39e4, Requires<[UseHVXV62]> { 32629let Inst{13-13} = 0b0; 32630let Inst{31-21} = 0b00011110011; 32631let hasNewValue = 1; 32632let opNewValue = 0; 32633let DecoderNamespace = "EXT_mmvec"; 32634} 32635def V6_vmaxb : HInst< 32636(outs HvxVR:$Vd32), 32637(ins HvxVR:$Vu32, HvxVR:$Vv32), 32638"$Vd32.b = vmax($Vu32.b,$Vv32.b)", 32639tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV62]> { 32640let Inst{7-5} = 0b101; 32641let Inst{13-13} = 0b0; 32642let Inst{31-21} = 0b00011111001; 32643let hasNewValue = 1; 32644let opNewValue = 0; 32645let DecoderNamespace = "EXT_mmvec"; 32646} 32647def V6_vmaxb_alt : HInst< 32648(outs HvxVR:$Vd32), 32649(ins HvxVR:$Vu32, HvxVR:$Vv32), 32650"$Vd32 = vmaxb($Vu32,$Vv32)", 32651PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> { 32652let hasNewValue = 1; 32653let opNewValue = 0; 32654let isPseudo = 1; 32655let isCodeGenOnly = 1; 32656let DecoderNamespace = "EXT_mmvec"; 32657} 32658def V6_vmaxh : HInst< 32659(outs HvxVR:$Vd32), 32660(ins HvxVR:$Vu32, HvxVR:$Vv32), 32661"$Vd32.h = vmax($Vu32.h,$Vv32.h)", 32662tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> { 32663let Inst{7-5} = 0b111; 32664let Inst{13-13} = 0b0; 32665let Inst{31-21} = 0b00011111000; 32666let hasNewValue = 1; 32667let opNewValue = 0; 32668let DecoderNamespace = "EXT_mmvec"; 32669} 32670def V6_vmaxh_alt : HInst< 32671(outs HvxVR:$Vd32), 32672(ins HvxVR:$Vu32, HvxVR:$Vv32), 32673"$Vd32 = vmaxh($Vu32,$Vv32)", 32674PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 32675let hasNewValue = 1; 32676let opNewValue = 0; 32677let isPseudo = 1; 32678let isCodeGenOnly = 1; 32679let DecoderNamespace = "EXT_mmvec"; 32680} 32681def V6_vmaxub : HInst< 32682(outs HvxVR:$Vd32), 32683(ins HvxVR:$Vu32, HvxVR:$Vv32), 32684"$Vd32.ub = vmax($Vu32.ub,$Vv32.ub)", 32685tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> { 32686let Inst{7-5} = 0b101; 32687let Inst{13-13} = 0b0; 32688let Inst{31-21} = 0b00011111000; 32689let hasNewValue = 1; 32690let opNewValue = 0; 32691let DecoderNamespace = "EXT_mmvec"; 32692} 32693def V6_vmaxub_alt : HInst< 32694(outs HvxVR:$Vd32), 32695(ins HvxVR:$Vu32, HvxVR:$Vv32), 32696"$Vd32 = vmaxub($Vu32,$Vv32)", 32697PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 32698let hasNewValue = 1; 32699let opNewValue = 0; 32700let isPseudo = 1; 32701let isCodeGenOnly = 1; 32702let DecoderNamespace = "EXT_mmvec"; 32703} 32704def V6_vmaxuh : HInst< 32705(outs HvxVR:$Vd32), 32706(ins HvxVR:$Vu32, HvxVR:$Vv32), 32707"$Vd32.uh = vmax($Vu32.uh,$Vv32.uh)", 32708tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> { 32709let Inst{7-5} = 0b110; 32710let Inst{13-13} = 0b0; 32711let Inst{31-21} = 0b00011111000; 32712let hasNewValue = 1; 32713let opNewValue = 0; 32714let DecoderNamespace = "EXT_mmvec"; 32715} 32716def V6_vmaxuh_alt : HInst< 32717(outs HvxVR:$Vd32), 32718(ins HvxVR:$Vu32, HvxVR:$Vv32), 32719"$Vd32 = vmaxuh($Vu32,$Vv32)", 32720PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 32721let hasNewValue = 1; 32722let opNewValue = 0; 32723let isPseudo = 1; 32724let isCodeGenOnly = 1; 32725let DecoderNamespace = "EXT_mmvec"; 32726} 32727def V6_vmaxw : HInst< 32728(outs HvxVR:$Vd32), 32729(ins HvxVR:$Vu32, HvxVR:$Vv32), 32730"$Vd32.w = vmax($Vu32.w,$Vv32.w)", 32731tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> { 32732let Inst{7-5} = 0b000; 32733let Inst{13-13} = 0b0; 32734let Inst{31-21} = 0b00011111001; 32735let hasNewValue = 1; 32736let opNewValue = 0; 32737let DecoderNamespace = "EXT_mmvec"; 32738} 32739def V6_vmaxw_alt : HInst< 32740(outs HvxVR:$Vd32), 32741(ins HvxVR:$Vu32, HvxVR:$Vv32), 32742"$Vd32 = vmaxw($Vu32,$Vv32)", 32743PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 32744let hasNewValue = 1; 32745let opNewValue = 0; 32746let isPseudo = 1; 32747let isCodeGenOnly = 1; 32748let DecoderNamespace = "EXT_mmvec"; 32749} 32750def V6_vminb : HInst< 32751(outs HvxVR:$Vd32), 32752(ins HvxVR:$Vu32, HvxVR:$Vv32), 32753"$Vd32.b = vmin($Vu32.b,$Vv32.b)", 32754tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV62]> { 32755let Inst{7-5} = 0b100; 32756let Inst{13-13} = 0b0; 32757let Inst{31-21} = 0b00011111001; 32758let hasNewValue = 1; 32759let opNewValue = 0; 32760let DecoderNamespace = "EXT_mmvec"; 32761} 32762def V6_vminb_alt : HInst< 32763(outs HvxVR:$Vd32), 32764(ins HvxVR:$Vu32, HvxVR:$Vv32), 32765"$Vd32 = vminb($Vu32,$Vv32)", 32766PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> { 32767let hasNewValue = 1; 32768let opNewValue = 0; 32769let isPseudo = 1; 32770let isCodeGenOnly = 1; 32771let DecoderNamespace = "EXT_mmvec"; 32772} 32773def V6_vminh : HInst< 32774(outs HvxVR:$Vd32), 32775(ins HvxVR:$Vu32, HvxVR:$Vv32), 32776"$Vd32.h = vmin($Vu32.h,$Vv32.h)", 32777tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> { 32778let Inst{7-5} = 0b011; 32779let Inst{13-13} = 0b0; 32780let Inst{31-21} = 0b00011111000; 32781let hasNewValue = 1; 32782let opNewValue = 0; 32783let DecoderNamespace = "EXT_mmvec"; 32784} 32785def V6_vminh_alt : HInst< 32786(outs HvxVR:$Vd32), 32787(ins HvxVR:$Vu32, HvxVR:$Vv32), 32788"$Vd32 = vminh($Vu32,$Vv32)", 32789PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 32790let hasNewValue = 1; 32791let opNewValue = 0; 32792let isPseudo = 1; 32793let isCodeGenOnly = 1; 32794let DecoderNamespace = "EXT_mmvec"; 32795} 32796def V6_vminub : HInst< 32797(outs HvxVR:$Vd32), 32798(ins HvxVR:$Vu32, HvxVR:$Vv32), 32799"$Vd32.ub = vmin($Vu32.ub,$Vv32.ub)", 32800tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> { 32801let Inst{7-5} = 0b001; 32802let Inst{13-13} = 0b0; 32803let Inst{31-21} = 0b00011111000; 32804let hasNewValue = 1; 32805let opNewValue = 0; 32806let DecoderNamespace = "EXT_mmvec"; 32807} 32808def V6_vminub_alt : HInst< 32809(outs HvxVR:$Vd32), 32810(ins HvxVR:$Vu32, HvxVR:$Vv32), 32811"$Vd32 = vminub($Vu32,$Vv32)", 32812PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 32813let hasNewValue = 1; 32814let opNewValue = 0; 32815let isPseudo = 1; 32816let isCodeGenOnly = 1; 32817let DecoderNamespace = "EXT_mmvec"; 32818} 32819def V6_vminuh : HInst< 32820(outs HvxVR:$Vd32), 32821(ins HvxVR:$Vu32, HvxVR:$Vv32), 32822"$Vd32.uh = vmin($Vu32.uh,$Vv32.uh)", 32823tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> { 32824let Inst{7-5} = 0b010; 32825let Inst{13-13} = 0b0; 32826let Inst{31-21} = 0b00011111000; 32827let hasNewValue = 1; 32828let opNewValue = 0; 32829let DecoderNamespace = "EXT_mmvec"; 32830} 32831def V6_vminuh_alt : HInst< 32832(outs HvxVR:$Vd32), 32833(ins HvxVR:$Vu32, HvxVR:$Vv32), 32834"$Vd32 = vminuh($Vu32,$Vv32)", 32835PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 32836let hasNewValue = 1; 32837let opNewValue = 0; 32838let isPseudo = 1; 32839let isCodeGenOnly = 1; 32840let DecoderNamespace = "EXT_mmvec"; 32841} 32842def V6_vminw : HInst< 32843(outs HvxVR:$Vd32), 32844(ins HvxVR:$Vu32, HvxVR:$Vv32), 32845"$Vd32.w = vmin($Vu32.w,$Vv32.w)", 32846tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> { 32847let Inst{7-5} = 0b100; 32848let Inst{13-13} = 0b0; 32849let Inst{31-21} = 0b00011111000; 32850let hasNewValue = 1; 32851let opNewValue = 0; 32852let DecoderNamespace = "EXT_mmvec"; 32853} 32854def V6_vminw_alt : HInst< 32855(outs HvxVR:$Vd32), 32856(ins HvxVR:$Vu32, HvxVR:$Vv32), 32857"$Vd32 = vminw($Vu32,$Vv32)", 32858PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 32859let hasNewValue = 1; 32860let opNewValue = 0; 32861let isPseudo = 1; 32862let isCodeGenOnly = 1; 32863let DecoderNamespace = "EXT_mmvec"; 32864} 32865def V6_vmpabus : HInst< 32866(outs HvxWR:$Vdd32), 32867(ins HvxWR:$Vuu32, IntRegs:$Rt32), 32868"$Vdd32.h = vmpa($Vuu32.ub,$Rt32.b)", 32869tc_0b04c6c7, TypeCVI_VX_DV>, Enc_aad80c, Requires<[UseHVXV60]> { 32870let Inst{7-5} = 0b110; 32871let Inst{13-13} = 0b0; 32872let Inst{31-21} = 0b00011001001; 32873let hasNewValue = 1; 32874let opNewValue = 0; 32875let DecoderNamespace = "EXT_mmvec"; 32876} 32877def V6_vmpabus_acc : HInst< 32878(outs HvxWR:$Vxx32), 32879(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32), 32880"$Vxx32.h += vmpa($Vuu32.ub,$Rt32.b)", 32881tc_660769f1, TypeCVI_VX_DV>, Enc_d6990d, Requires<[UseHVXV60]> { 32882let Inst{7-5} = 0b110; 32883let Inst{13-13} = 0b1; 32884let Inst{31-21} = 0b00011001001; 32885let hasNewValue = 1; 32886let opNewValue = 0; 32887let isAccumulator = 1; 32888let DecoderNamespace = "EXT_mmvec"; 32889let Constraints = "$Vxx32 = $Vxx32in"; 32890} 32891def V6_vmpabus_acc_alt : HInst< 32892(outs HvxWR:$Vxx32), 32893(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32), 32894"$Vxx32 += vmpabus($Vuu32,$Rt32)", 32895PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 32896let hasNewValue = 1; 32897let opNewValue = 0; 32898let isAccumulator = 1; 32899let isPseudo = 1; 32900let isCodeGenOnly = 1; 32901let DecoderNamespace = "EXT_mmvec"; 32902let Constraints = "$Vxx32 = $Vxx32in"; 32903} 32904def V6_vmpabus_alt : HInst< 32905(outs HvxWR:$Vdd32), 32906(ins HvxWR:$Vuu32, IntRegs:$Rt32), 32907"$Vdd32 = vmpabus($Vuu32,$Rt32)", 32908PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 32909let hasNewValue = 1; 32910let opNewValue = 0; 32911let isPseudo = 1; 32912let isCodeGenOnly = 1; 32913let DecoderNamespace = "EXT_mmvec"; 32914} 32915def V6_vmpabusv : HInst< 32916(outs HvxWR:$Vdd32), 32917(ins HvxWR:$Vuu32, HvxWR:$Vvv32), 32918"$Vdd32.h = vmpa($Vuu32.ub,$Vvv32.b)", 32919tc_d8287c14, TypeCVI_VX_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> { 32920let Inst{7-5} = 0b011; 32921let Inst{13-13} = 0b0; 32922let Inst{31-21} = 0b00011100001; 32923let hasNewValue = 1; 32924let opNewValue = 0; 32925let DecoderNamespace = "EXT_mmvec"; 32926} 32927def V6_vmpabusv_alt : HInst< 32928(outs HvxWR:$Vdd32), 32929(ins HvxWR:$Vuu32, HvxWR:$Vvv32), 32930"$Vdd32 = vmpabus($Vuu32,$Vvv32)", 32931PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 32932let hasNewValue = 1; 32933let opNewValue = 0; 32934let isPseudo = 1; 32935let isCodeGenOnly = 1; 32936let DecoderNamespace = "EXT_mmvec"; 32937} 32938def V6_vmpabuu : HInst< 32939(outs HvxWR:$Vdd32), 32940(ins HvxWR:$Vuu32, IntRegs:$Rt32), 32941"$Vdd32.h = vmpa($Vuu32.ub,$Rt32.ub)", 32942tc_0b04c6c7, TypeCVI_VX_DV>, Enc_aad80c, Requires<[UseHVXV65]> { 32943let Inst{7-5} = 0b011; 32944let Inst{13-13} = 0b0; 32945let Inst{31-21} = 0b00011001011; 32946let hasNewValue = 1; 32947let opNewValue = 0; 32948let DecoderNamespace = "EXT_mmvec"; 32949} 32950def V6_vmpabuu_acc : HInst< 32951(outs HvxWR:$Vxx32), 32952(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32), 32953"$Vxx32.h += vmpa($Vuu32.ub,$Rt32.ub)", 32954tc_660769f1, TypeCVI_VX_DV>, Enc_d6990d, Requires<[UseHVXV65]> { 32955let Inst{7-5} = 0b100; 32956let Inst{13-13} = 0b1; 32957let Inst{31-21} = 0b00011001101; 32958let hasNewValue = 1; 32959let opNewValue = 0; 32960let isAccumulator = 1; 32961let DecoderNamespace = "EXT_mmvec"; 32962let Constraints = "$Vxx32 = $Vxx32in"; 32963} 32964def V6_vmpabuu_acc_alt : HInst< 32965(outs HvxWR:$Vxx32), 32966(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32), 32967"$Vxx32 += vmpabuu($Vuu32,$Rt32)", 32968PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> { 32969let hasNewValue = 1; 32970let opNewValue = 0; 32971let isAccumulator = 1; 32972let isPseudo = 1; 32973let isCodeGenOnly = 1; 32974let DecoderNamespace = "EXT_mmvec"; 32975let Constraints = "$Vxx32 = $Vxx32in"; 32976} 32977def V6_vmpabuu_alt : HInst< 32978(outs HvxWR:$Vdd32), 32979(ins HvxWR:$Vuu32, IntRegs:$Rt32), 32980"$Vdd32 = vmpabuu($Vuu32,$Rt32)", 32981PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> { 32982let hasNewValue = 1; 32983let opNewValue = 0; 32984let isPseudo = 1; 32985let isCodeGenOnly = 1; 32986let DecoderNamespace = "EXT_mmvec"; 32987} 32988def V6_vmpabuuv : HInst< 32989(outs HvxWR:$Vdd32), 32990(ins HvxWR:$Vuu32, HvxWR:$Vvv32), 32991"$Vdd32.h = vmpa($Vuu32.ub,$Vvv32.ub)", 32992tc_d8287c14, TypeCVI_VX_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> { 32993let Inst{7-5} = 0b111; 32994let Inst{13-13} = 0b0; 32995let Inst{31-21} = 0b00011100111; 32996let hasNewValue = 1; 32997let opNewValue = 0; 32998let DecoderNamespace = "EXT_mmvec"; 32999} 33000def V6_vmpabuuv_alt : HInst< 33001(outs HvxWR:$Vdd32), 33002(ins HvxWR:$Vuu32, HvxWR:$Vvv32), 33003"$Vdd32 = vmpabuu($Vuu32,$Vvv32)", 33004PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 33005let hasNewValue = 1; 33006let opNewValue = 0; 33007let isPseudo = 1; 33008let isCodeGenOnly = 1; 33009let DecoderNamespace = "EXT_mmvec"; 33010} 33011def V6_vmpahb : HInst< 33012(outs HvxWR:$Vdd32), 33013(ins HvxWR:$Vuu32, IntRegs:$Rt32), 33014"$Vdd32.w = vmpa($Vuu32.h,$Rt32.b)", 33015tc_0b04c6c7, TypeCVI_VX_DV>, Enc_aad80c, Requires<[UseHVXV60]> { 33016let Inst{7-5} = 0b111; 33017let Inst{13-13} = 0b0; 33018let Inst{31-21} = 0b00011001001; 33019let hasNewValue = 1; 33020let opNewValue = 0; 33021let DecoderNamespace = "EXT_mmvec"; 33022} 33023def V6_vmpahb_acc : HInst< 33024(outs HvxWR:$Vxx32), 33025(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32), 33026"$Vxx32.w += vmpa($Vuu32.h,$Rt32.b)", 33027tc_660769f1, TypeCVI_VX_DV>, Enc_d6990d, Requires<[UseHVXV60]> { 33028let Inst{7-5} = 0b111; 33029let Inst{13-13} = 0b1; 33030let Inst{31-21} = 0b00011001001; 33031let hasNewValue = 1; 33032let opNewValue = 0; 33033let isAccumulator = 1; 33034let DecoderNamespace = "EXT_mmvec"; 33035let Constraints = "$Vxx32 = $Vxx32in"; 33036} 33037def V6_vmpahb_acc_alt : HInst< 33038(outs HvxWR:$Vxx32), 33039(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32), 33040"$Vxx32 += vmpahb($Vuu32,$Rt32)", 33041PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 33042let hasNewValue = 1; 33043let opNewValue = 0; 33044let isAccumulator = 1; 33045let isPseudo = 1; 33046let isCodeGenOnly = 1; 33047let DecoderNamespace = "EXT_mmvec"; 33048let Constraints = "$Vxx32 = $Vxx32in"; 33049} 33050def V6_vmpahb_alt : HInst< 33051(outs HvxWR:$Vdd32), 33052(ins HvxWR:$Vuu32, IntRegs:$Rt32), 33053"$Vdd32 = vmpahb($Vuu32,$Rt32)", 33054PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 33055let hasNewValue = 1; 33056let opNewValue = 0; 33057let isPseudo = 1; 33058let isCodeGenOnly = 1; 33059let DecoderNamespace = "EXT_mmvec"; 33060} 33061def V6_vmpahhsat : HInst< 33062(outs HvxVR:$Vx32), 33063(ins HvxVR:$Vx32in, HvxVR:$Vu32, DoubleRegs:$Rtt32), 33064"$Vx32.h = vmpa($Vx32in.h,$Vu32.h,$Rtt32.h):sat", 33065tc_90bcc1db, TypeCVI_VX_DV>, Enc_310ba1, Requires<[UseHVXV65]> { 33066let Inst{7-5} = 0b100; 33067let Inst{13-13} = 0b1; 33068let Inst{31-21} = 0b00011001100; 33069let hasNewValue = 1; 33070let opNewValue = 0; 33071let DecoderNamespace = "EXT_mmvec"; 33072let Constraints = "$Vx32 = $Vx32in"; 33073} 33074def V6_vmpauhb : HInst< 33075(outs HvxWR:$Vdd32), 33076(ins HvxWR:$Vuu32, IntRegs:$Rt32), 33077"$Vdd32.w = vmpa($Vuu32.uh,$Rt32.b)", 33078tc_0b04c6c7, TypeCVI_VX_DV>, Enc_aad80c, Requires<[UseHVXV62]> { 33079let Inst{7-5} = 0b101; 33080let Inst{13-13} = 0b0; 33081let Inst{31-21} = 0b00011001100; 33082let hasNewValue = 1; 33083let opNewValue = 0; 33084let DecoderNamespace = "EXT_mmvec"; 33085} 33086def V6_vmpauhb_acc : HInst< 33087(outs HvxWR:$Vxx32), 33088(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32), 33089"$Vxx32.w += vmpa($Vuu32.uh,$Rt32.b)", 33090tc_660769f1, TypeCVI_VX_DV>, Enc_d6990d, Requires<[UseHVXV62]> { 33091let Inst{7-5} = 0b010; 33092let Inst{13-13} = 0b1; 33093let Inst{31-21} = 0b00011001100; 33094let hasNewValue = 1; 33095let opNewValue = 0; 33096let isAccumulator = 1; 33097let DecoderNamespace = "EXT_mmvec"; 33098let Constraints = "$Vxx32 = $Vxx32in"; 33099} 33100def V6_vmpauhb_acc_alt : HInst< 33101(outs HvxWR:$Vxx32), 33102(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32), 33103"$Vxx32 += vmpauhb($Vuu32,$Rt32)", 33104PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> { 33105let hasNewValue = 1; 33106let opNewValue = 0; 33107let isAccumulator = 1; 33108let isPseudo = 1; 33109let isCodeGenOnly = 1; 33110let DecoderNamespace = "EXT_mmvec"; 33111let Constraints = "$Vxx32 = $Vxx32in"; 33112} 33113def V6_vmpauhb_alt : HInst< 33114(outs HvxWR:$Vdd32), 33115(ins HvxWR:$Vuu32, IntRegs:$Rt32), 33116"$Vdd32 = vmpauhb($Vuu32,$Rt32)", 33117PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> { 33118let hasNewValue = 1; 33119let opNewValue = 0; 33120let isPseudo = 1; 33121let isCodeGenOnly = 1; 33122let DecoderNamespace = "EXT_mmvec"; 33123} 33124def V6_vmpauhuhsat : HInst< 33125(outs HvxVR:$Vx32), 33126(ins HvxVR:$Vx32in, HvxVR:$Vu32, DoubleRegs:$Rtt32), 33127"$Vx32.h = vmpa($Vx32in.h,$Vu32.uh,$Rtt32.uh):sat", 33128tc_90bcc1db, TypeCVI_VX_DV>, Enc_310ba1, Requires<[UseHVXV65]> { 33129let Inst{7-5} = 0b101; 33130let Inst{13-13} = 0b1; 33131let Inst{31-21} = 0b00011001100; 33132let hasNewValue = 1; 33133let opNewValue = 0; 33134let DecoderNamespace = "EXT_mmvec"; 33135let Constraints = "$Vx32 = $Vx32in"; 33136} 33137def V6_vmpsuhuhsat : HInst< 33138(outs HvxVR:$Vx32), 33139(ins HvxVR:$Vx32in, HvxVR:$Vu32, DoubleRegs:$Rtt32), 33140"$Vx32.h = vmps($Vx32in.h,$Vu32.uh,$Rtt32.uh):sat", 33141tc_90bcc1db, TypeCVI_VX_DV>, Enc_310ba1, Requires<[UseHVXV65]> { 33142let Inst{7-5} = 0b110; 33143let Inst{13-13} = 0b1; 33144let Inst{31-21} = 0b00011001100; 33145let hasNewValue = 1; 33146let opNewValue = 0; 33147let DecoderNamespace = "EXT_mmvec"; 33148let Constraints = "$Vx32 = $Vx32in"; 33149} 33150def V6_vmpybus : HInst< 33151(outs HvxWR:$Vdd32), 33152(ins HvxVR:$Vu32, IntRegs:$Rt32), 33153"$Vdd32.h = vmpy($Vu32.ub,$Rt32.b)", 33154tc_0b04c6c7, TypeCVI_VX_DV>, Enc_01d3d0, Requires<[UseHVXV60]> { 33155let Inst{7-5} = 0b101; 33156let Inst{13-13} = 0b0; 33157let Inst{31-21} = 0b00011001001; 33158let hasNewValue = 1; 33159let opNewValue = 0; 33160let DecoderNamespace = "EXT_mmvec"; 33161} 33162def V6_vmpybus_acc : HInst< 33163(outs HvxWR:$Vxx32), 33164(ins HvxWR:$Vxx32in, HvxVR:$Vu32, IntRegs:$Rt32), 33165"$Vxx32.h += vmpy($Vu32.ub,$Rt32.b)", 33166tc_660769f1, TypeCVI_VX_DV>, Enc_5e8512, Requires<[UseHVXV60]> { 33167let Inst{7-5} = 0b101; 33168let Inst{13-13} = 0b1; 33169let Inst{31-21} = 0b00011001001; 33170let hasNewValue = 1; 33171let opNewValue = 0; 33172let isAccumulator = 1; 33173let DecoderNamespace = "EXT_mmvec"; 33174let Constraints = "$Vxx32 = $Vxx32in"; 33175} 33176def V6_vmpybus_acc_alt : HInst< 33177(outs HvxWR:$Vxx32), 33178(ins HvxWR:$Vxx32in, HvxVR:$Vu32, IntRegs:$Rt32), 33179"$Vxx32 += vmpybus($Vu32,$Rt32)", 33180PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 33181let hasNewValue = 1; 33182let opNewValue = 0; 33183let isAccumulator = 1; 33184let isPseudo = 1; 33185let isCodeGenOnly = 1; 33186let DecoderNamespace = "EXT_mmvec"; 33187let Constraints = "$Vxx32 = $Vxx32in"; 33188} 33189def V6_vmpybus_alt : HInst< 33190(outs HvxWR:$Vdd32), 33191(ins HvxVR:$Vu32, IntRegs:$Rt32), 33192"$Vdd32 = vmpybus($Vu32,$Rt32)", 33193PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 33194let hasNewValue = 1; 33195let opNewValue = 0; 33196let isPseudo = 1; 33197let isCodeGenOnly = 1; 33198let DecoderNamespace = "EXT_mmvec"; 33199} 33200def V6_vmpybusv : HInst< 33201(outs HvxWR:$Vdd32), 33202(ins HvxVR:$Vu32, HvxVR:$Vv32), 33203"$Vdd32.h = vmpy($Vu32.ub,$Vv32.b)", 33204tc_d8287c14, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV60]> { 33205let Inst{7-5} = 0b110; 33206let Inst{13-13} = 0b0; 33207let Inst{31-21} = 0b00011100000; 33208let hasNewValue = 1; 33209let opNewValue = 0; 33210let DecoderNamespace = "EXT_mmvec"; 33211} 33212def V6_vmpybusv_acc : HInst< 33213(outs HvxWR:$Vxx32), 33214(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32), 33215"$Vxx32.h += vmpy($Vu32.ub,$Vv32.b)", 33216tc_08a4f1b6, TypeCVI_VX_DV>, Enc_3fc427, Requires<[UseHVXV60]> { 33217let Inst{7-5} = 0b110; 33218let Inst{13-13} = 0b1; 33219let Inst{31-21} = 0b00011100000; 33220let hasNewValue = 1; 33221let opNewValue = 0; 33222let isAccumulator = 1; 33223let DecoderNamespace = "EXT_mmvec"; 33224let Constraints = "$Vxx32 = $Vxx32in"; 33225} 33226def V6_vmpybusv_acc_alt : HInst< 33227(outs HvxWR:$Vxx32), 33228(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32), 33229"$Vxx32 += vmpybus($Vu32,$Vv32)", 33230PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 33231let hasNewValue = 1; 33232let opNewValue = 0; 33233let isAccumulator = 1; 33234let isPseudo = 1; 33235let isCodeGenOnly = 1; 33236let DecoderNamespace = "EXT_mmvec"; 33237let Constraints = "$Vxx32 = $Vxx32in"; 33238} 33239def V6_vmpybusv_alt : HInst< 33240(outs HvxWR:$Vdd32), 33241(ins HvxVR:$Vu32, HvxVR:$Vv32), 33242"$Vdd32 = vmpybus($Vu32,$Vv32)", 33243PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 33244let hasNewValue = 1; 33245let opNewValue = 0; 33246let isPseudo = 1; 33247let isCodeGenOnly = 1; 33248let DecoderNamespace = "EXT_mmvec"; 33249} 33250def V6_vmpybv : HInst< 33251(outs HvxWR:$Vdd32), 33252(ins HvxVR:$Vu32, HvxVR:$Vv32), 33253"$Vdd32.h = vmpy($Vu32.b,$Vv32.b)", 33254tc_d8287c14, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV60]> { 33255let Inst{7-5} = 0b100; 33256let Inst{13-13} = 0b0; 33257let Inst{31-21} = 0b00011100000; 33258let hasNewValue = 1; 33259let opNewValue = 0; 33260let DecoderNamespace = "EXT_mmvec"; 33261} 33262def V6_vmpybv_acc : HInst< 33263(outs HvxWR:$Vxx32), 33264(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32), 33265"$Vxx32.h += vmpy($Vu32.b,$Vv32.b)", 33266tc_08a4f1b6, TypeCVI_VX_DV>, Enc_3fc427, Requires<[UseHVXV60]> { 33267let Inst{7-5} = 0b100; 33268let Inst{13-13} = 0b1; 33269let Inst{31-21} = 0b00011100000; 33270let hasNewValue = 1; 33271let opNewValue = 0; 33272let isAccumulator = 1; 33273let DecoderNamespace = "EXT_mmvec"; 33274let Constraints = "$Vxx32 = $Vxx32in"; 33275} 33276def V6_vmpybv_acc_alt : HInst< 33277(outs HvxWR:$Vxx32), 33278(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32), 33279"$Vxx32 += vmpyb($Vu32,$Vv32)", 33280PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 33281let hasNewValue = 1; 33282let opNewValue = 0; 33283let isAccumulator = 1; 33284let isPseudo = 1; 33285let isCodeGenOnly = 1; 33286let DecoderNamespace = "EXT_mmvec"; 33287let Constraints = "$Vxx32 = $Vxx32in"; 33288} 33289def V6_vmpybv_alt : HInst< 33290(outs HvxWR:$Vdd32), 33291(ins HvxVR:$Vu32, HvxVR:$Vv32), 33292"$Vdd32 = vmpyb($Vu32,$Vv32)", 33293PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 33294let hasNewValue = 1; 33295let opNewValue = 0; 33296let isPseudo = 1; 33297let isCodeGenOnly = 1; 33298let DecoderNamespace = "EXT_mmvec"; 33299} 33300def V6_vmpyewuh : HInst< 33301(outs HvxVR:$Vd32), 33302(ins HvxVR:$Vu32, HvxVR:$Vv32), 33303"$Vd32.w = vmpye($Vu32.w,$Vv32.uh)", 33304tc_d8287c14, TypeCVI_VX_DV>, Enc_45364e, Requires<[UseHVXV60]> { 33305let Inst{7-5} = 0b101; 33306let Inst{13-13} = 0b0; 33307let Inst{31-21} = 0b00011111111; 33308let hasNewValue = 1; 33309let opNewValue = 0; 33310let DecoderNamespace = "EXT_mmvec"; 33311} 33312def V6_vmpyewuh_64 : HInst< 33313(outs HvxWR:$Vdd32), 33314(ins HvxVR:$Vu32, HvxVR:$Vv32), 33315"$Vdd32 = vmpye($Vu32.w,$Vv32.uh)", 33316tc_d8287c14, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV62]> { 33317let Inst{7-5} = 0b110; 33318let Inst{13-13} = 0b0; 33319let Inst{31-21} = 0b00011110101; 33320let hasNewValue = 1; 33321let opNewValue = 0; 33322let DecoderNamespace = "EXT_mmvec"; 33323} 33324def V6_vmpyewuh_alt : HInst< 33325(outs HvxVR:$Vd32), 33326(ins HvxVR:$Vu32, HvxVR:$Vv32), 33327"$Vd32 = vmpyewuh($Vu32,$Vv32)", 33328PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 33329let hasNewValue = 1; 33330let opNewValue = 0; 33331let isPseudo = 1; 33332let isCodeGenOnly = 1; 33333let DecoderNamespace = "EXT_mmvec"; 33334} 33335def V6_vmpyh : HInst< 33336(outs HvxWR:$Vdd32), 33337(ins HvxVR:$Vu32, IntRegs:$Rt32), 33338"$Vdd32.w = vmpy($Vu32.h,$Rt32.h)", 33339tc_0b04c6c7, TypeCVI_VX_DV>, Enc_01d3d0, Requires<[UseHVXV60]> { 33340let Inst{7-5} = 0b000; 33341let Inst{13-13} = 0b0; 33342let Inst{31-21} = 0b00011001010; 33343let hasNewValue = 1; 33344let opNewValue = 0; 33345let DecoderNamespace = "EXT_mmvec"; 33346} 33347def V6_vmpyh_acc : HInst< 33348(outs HvxWR:$Vxx32), 33349(ins HvxWR:$Vxx32in, HvxVR:$Vu32, IntRegs:$Rt32), 33350"$Vxx32.w += vmpy($Vu32.h,$Rt32.h)", 33351tc_660769f1, TypeCVI_VX_DV>, Enc_5e8512, Requires<[UseHVXV65]> { 33352let Inst{7-5} = 0b110; 33353let Inst{13-13} = 0b1; 33354let Inst{31-21} = 0b00011001101; 33355let hasNewValue = 1; 33356let opNewValue = 0; 33357let isAccumulator = 1; 33358let DecoderNamespace = "EXT_mmvec"; 33359let Constraints = "$Vxx32 = $Vxx32in"; 33360} 33361def V6_vmpyh_acc_alt : HInst< 33362(outs HvxWR:$Vxx32), 33363(ins HvxWR:$Vxx32in, HvxVR:$Vu32, IntRegs:$Rt32), 33364"$Vxx32 += vmpyh($Vu32,$Rt32)", 33365PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> { 33366let hasNewValue = 1; 33367let opNewValue = 0; 33368let isAccumulator = 1; 33369let isPseudo = 1; 33370let isCodeGenOnly = 1; 33371let DecoderNamespace = "EXT_mmvec"; 33372let Constraints = "$Vxx32 = $Vxx32in"; 33373} 33374def V6_vmpyh_alt : HInst< 33375(outs HvxWR:$Vdd32), 33376(ins HvxVR:$Vu32, IntRegs:$Rt32), 33377"$Vdd32 = vmpyh($Vu32,$Rt32)", 33378PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 33379let hasNewValue = 1; 33380let opNewValue = 0; 33381let isPseudo = 1; 33382let isCodeGenOnly = 1; 33383let DecoderNamespace = "EXT_mmvec"; 33384} 33385def V6_vmpyhsat_acc : HInst< 33386(outs HvxWR:$Vxx32), 33387(ins HvxWR:$Vxx32in, HvxVR:$Vu32, IntRegs:$Rt32), 33388"$Vxx32.w += vmpy($Vu32.h,$Rt32.h):sat", 33389tc_660769f1, TypeCVI_VX_DV>, Enc_5e8512, Requires<[UseHVXV60]> { 33390let Inst{7-5} = 0b000; 33391let Inst{13-13} = 0b1; 33392let Inst{31-21} = 0b00011001010; 33393let hasNewValue = 1; 33394let opNewValue = 0; 33395let isAccumulator = 1; 33396let DecoderNamespace = "EXT_mmvec"; 33397let Constraints = "$Vxx32 = $Vxx32in"; 33398} 33399def V6_vmpyhsat_acc_alt : HInst< 33400(outs HvxWR:$Vxx32), 33401(ins HvxWR:$Vxx32in, HvxVR:$Vu32, IntRegs:$Rt32), 33402"$Vxx32 += vmpyh($Vu32,$Rt32):sat", 33403PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 33404let hasNewValue = 1; 33405let opNewValue = 0; 33406let isAccumulator = 1; 33407let isPseudo = 1; 33408let isCodeGenOnly = 1; 33409let DecoderNamespace = "EXT_mmvec"; 33410let Constraints = "$Vxx32 = $Vxx32in"; 33411} 33412def V6_vmpyhsrs : HInst< 33413(outs HvxVR:$Vd32), 33414(ins HvxVR:$Vu32, IntRegs:$Rt32), 33415"$Vd32.h = vmpy($Vu32.h,$Rt32.h):<<1:rnd:sat", 33416tc_0b04c6c7, TypeCVI_VX_DV>, Enc_b087ac, Requires<[UseHVXV60]> { 33417let Inst{7-5} = 0b010; 33418let Inst{13-13} = 0b0; 33419let Inst{31-21} = 0b00011001010; 33420let hasNewValue = 1; 33421let opNewValue = 0; 33422let DecoderNamespace = "EXT_mmvec"; 33423} 33424def V6_vmpyhsrs_alt : HInst< 33425(outs HvxVR:$Vd32), 33426(ins HvxVR:$Vu32, IntRegs:$Rt32), 33427"$Vd32 = vmpyh($Vu32,$Rt32):<<1:rnd:sat", 33428PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 33429let hasNewValue = 1; 33430let opNewValue = 0; 33431let isPseudo = 1; 33432let isCodeGenOnly = 1; 33433let DecoderNamespace = "EXT_mmvec"; 33434} 33435def V6_vmpyhss : HInst< 33436(outs HvxVR:$Vd32), 33437(ins HvxVR:$Vu32, IntRegs:$Rt32), 33438"$Vd32.h = vmpy($Vu32.h,$Rt32.h):<<1:sat", 33439tc_0b04c6c7, TypeCVI_VX_DV>, Enc_b087ac, Requires<[UseHVXV60]> { 33440let Inst{7-5} = 0b001; 33441let Inst{13-13} = 0b0; 33442let Inst{31-21} = 0b00011001010; 33443let hasNewValue = 1; 33444let opNewValue = 0; 33445let DecoderNamespace = "EXT_mmvec"; 33446} 33447def V6_vmpyhss_alt : HInst< 33448(outs HvxVR:$Vd32), 33449(ins HvxVR:$Vu32, IntRegs:$Rt32), 33450"$Vd32 = vmpyh($Vu32,$Rt32):<<1:sat", 33451PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 33452let hasNewValue = 1; 33453let opNewValue = 0; 33454let isPseudo = 1; 33455let isCodeGenOnly = 1; 33456let DecoderNamespace = "EXT_mmvec"; 33457} 33458def V6_vmpyhus : HInst< 33459(outs HvxWR:$Vdd32), 33460(ins HvxVR:$Vu32, HvxVR:$Vv32), 33461"$Vdd32.w = vmpy($Vu32.h,$Vv32.uh)", 33462tc_d8287c14, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV60]> { 33463let Inst{7-5} = 0b010; 33464let Inst{13-13} = 0b0; 33465let Inst{31-21} = 0b00011100001; 33466let hasNewValue = 1; 33467let opNewValue = 0; 33468let DecoderNamespace = "EXT_mmvec"; 33469} 33470def V6_vmpyhus_acc : HInst< 33471(outs HvxWR:$Vxx32), 33472(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32), 33473"$Vxx32.w += vmpy($Vu32.h,$Vv32.uh)", 33474tc_08a4f1b6, TypeCVI_VX_DV>, Enc_3fc427, Requires<[UseHVXV60]> { 33475let Inst{7-5} = 0b001; 33476let Inst{13-13} = 0b1; 33477let Inst{31-21} = 0b00011100001; 33478let hasNewValue = 1; 33479let opNewValue = 0; 33480let isAccumulator = 1; 33481let DecoderNamespace = "EXT_mmvec"; 33482let Constraints = "$Vxx32 = $Vxx32in"; 33483} 33484def V6_vmpyhus_acc_alt : HInst< 33485(outs HvxWR:$Vxx32), 33486(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32), 33487"$Vxx32 += vmpyhus($Vu32,$Vv32)", 33488PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 33489let hasNewValue = 1; 33490let opNewValue = 0; 33491let isAccumulator = 1; 33492let isPseudo = 1; 33493let isCodeGenOnly = 1; 33494let DecoderNamespace = "EXT_mmvec"; 33495let Constraints = "$Vxx32 = $Vxx32in"; 33496} 33497def V6_vmpyhus_alt : HInst< 33498(outs HvxWR:$Vdd32), 33499(ins HvxVR:$Vu32, HvxVR:$Vv32), 33500"$Vdd32 = vmpyhus($Vu32,$Vv32)", 33501PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 33502let hasNewValue = 1; 33503let opNewValue = 0; 33504let isPseudo = 1; 33505let isCodeGenOnly = 1; 33506let DecoderNamespace = "EXT_mmvec"; 33507} 33508def V6_vmpyhv : HInst< 33509(outs HvxWR:$Vdd32), 33510(ins HvxVR:$Vu32, HvxVR:$Vv32), 33511"$Vdd32.w = vmpy($Vu32.h,$Vv32.h)", 33512tc_d8287c14, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV60]> { 33513let Inst{7-5} = 0b111; 33514let Inst{13-13} = 0b0; 33515let Inst{31-21} = 0b00011100000; 33516let hasNewValue = 1; 33517let opNewValue = 0; 33518let DecoderNamespace = "EXT_mmvec"; 33519} 33520def V6_vmpyhv_acc : HInst< 33521(outs HvxWR:$Vxx32), 33522(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32), 33523"$Vxx32.w += vmpy($Vu32.h,$Vv32.h)", 33524tc_08a4f1b6, TypeCVI_VX_DV>, Enc_3fc427, Requires<[UseHVXV60]> { 33525let Inst{7-5} = 0b111; 33526let Inst{13-13} = 0b1; 33527let Inst{31-21} = 0b00011100000; 33528let hasNewValue = 1; 33529let opNewValue = 0; 33530let isAccumulator = 1; 33531let DecoderNamespace = "EXT_mmvec"; 33532let Constraints = "$Vxx32 = $Vxx32in"; 33533} 33534def V6_vmpyhv_acc_alt : HInst< 33535(outs HvxWR:$Vxx32), 33536(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32), 33537"$Vxx32 += vmpyh($Vu32,$Vv32)", 33538PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 33539let hasNewValue = 1; 33540let opNewValue = 0; 33541let isAccumulator = 1; 33542let isPseudo = 1; 33543let isCodeGenOnly = 1; 33544let DecoderNamespace = "EXT_mmvec"; 33545let Constraints = "$Vxx32 = $Vxx32in"; 33546} 33547def V6_vmpyhv_alt : HInst< 33548(outs HvxWR:$Vdd32), 33549(ins HvxVR:$Vu32, HvxVR:$Vv32), 33550"$Vdd32 = vmpyh($Vu32,$Vv32)", 33551PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 33552let hasNewValue = 1; 33553let opNewValue = 0; 33554let isPseudo = 1; 33555let isCodeGenOnly = 1; 33556let DecoderNamespace = "EXT_mmvec"; 33557} 33558def V6_vmpyhvsrs : HInst< 33559(outs HvxVR:$Vd32), 33560(ins HvxVR:$Vu32, HvxVR:$Vv32), 33561"$Vd32.h = vmpy($Vu32.h,$Vv32.h):<<1:rnd:sat", 33562tc_d8287c14, TypeCVI_VX_DV>, Enc_45364e, Requires<[UseHVXV60]> { 33563let Inst{7-5} = 0b001; 33564let Inst{13-13} = 0b0; 33565let Inst{31-21} = 0b00011100001; 33566let hasNewValue = 1; 33567let opNewValue = 0; 33568let DecoderNamespace = "EXT_mmvec"; 33569} 33570def V6_vmpyhvsrs_alt : HInst< 33571(outs HvxVR:$Vd32), 33572(ins HvxVR:$Vu32, HvxVR:$Vv32), 33573"$Vd32 = vmpyh($Vu32,$Vv32):<<1:rnd:sat", 33574PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 33575let hasNewValue = 1; 33576let opNewValue = 0; 33577let isPseudo = 1; 33578let isCodeGenOnly = 1; 33579let DecoderNamespace = "EXT_mmvec"; 33580} 33581def V6_vmpyieoh : HInst< 33582(outs HvxVR:$Vd32), 33583(ins HvxVR:$Vu32, HvxVR:$Vv32), 33584"$Vd32.w = vmpyieo($Vu32.h,$Vv32.h)", 33585tc_c127de3a, TypeCVI_VX>, Enc_45364e, Requires<[UseHVXV60]> { 33586let Inst{7-5} = 0b000; 33587let Inst{13-13} = 0b0; 33588let Inst{31-21} = 0b00011111011; 33589let hasNewValue = 1; 33590let opNewValue = 0; 33591let DecoderNamespace = "EXT_mmvec"; 33592} 33593def V6_vmpyiewh_acc : HInst< 33594(outs HvxVR:$Vx32), 33595(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32), 33596"$Vx32.w += vmpyie($Vu32.w,$Vv32.h)", 33597tc_08a4f1b6, TypeCVI_VX_DV>, Enc_a7341a, Requires<[UseHVXV60]> { 33598let Inst{7-5} = 0b000; 33599let Inst{13-13} = 0b1; 33600let Inst{31-21} = 0b00011100010; 33601let hasNewValue = 1; 33602let opNewValue = 0; 33603let isAccumulator = 1; 33604let DecoderNamespace = "EXT_mmvec"; 33605let Constraints = "$Vx32 = $Vx32in"; 33606} 33607def V6_vmpyiewh_acc_alt : HInst< 33608(outs HvxVR:$Vx32), 33609(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32), 33610"$Vx32 += vmpyiewh($Vu32,$Vv32)", 33611PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 33612let hasNewValue = 1; 33613let opNewValue = 0; 33614let isAccumulator = 1; 33615let isPseudo = 1; 33616let isCodeGenOnly = 1; 33617let DecoderNamespace = "EXT_mmvec"; 33618let Constraints = "$Vx32 = $Vx32in"; 33619} 33620def V6_vmpyiewuh : HInst< 33621(outs HvxVR:$Vd32), 33622(ins HvxVR:$Vu32, HvxVR:$Vv32), 33623"$Vd32.w = vmpyie($Vu32.w,$Vv32.uh)", 33624tc_d8287c14, TypeCVI_VX_DV>, Enc_45364e, Requires<[UseHVXV60]> { 33625let Inst{7-5} = 0b000; 33626let Inst{13-13} = 0b0; 33627let Inst{31-21} = 0b00011111110; 33628let hasNewValue = 1; 33629let opNewValue = 0; 33630let DecoderNamespace = "EXT_mmvec"; 33631} 33632def V6_vmpyiewuh_acc : HInst< 33633(outs HvxVR:$Vx32), 33634(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32), 33635"$Vx32.w += vmpyie($Vu32.w,$Vv32.uh)", 33636tc_08a4f1b6, TypeCVI_VX_DV>, Enc_a7341a, Requires<[UseHVXV60]> { 33637let Inst{7-5} = 0b101; 33638let Inst{13-13} = 0b1; 33639let Inst{31-21} = 0b00011100001; 33640let hasNewValue = 1; 33641let opNewValue = 0; 33642let isAccumulator = 1; 33643let DecoderNamespace = "EXT_mmvec"; 33644let Constraints = "$Vx32 = $Vx32in"; 33645} 33646def V6_vmpyiewuh_acc_alt : HInst< 33647(outs HvxVR:$Vx32), 33648(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32), 33649"$Vx32 += vmpyiewuh($Vu32,$Vv32)", 33650PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 33651let hasNewValue = 1; 33652let opNewValue = 0; 33653let isAccumulator = 1; 33654let isPseudo = 1; 33655let isCodeGenOnly = 1; 33656let DecoderNamespace = "EXT_mmvec"; 33657let Constraints = "$Vx32 = $Vx32in"; 33658} 33659def V6_vmpyiewuh_alt : HInst< 33660(outs HvxVR:$Vd32), 33661(ins HvxVR:$Vu32, HvxVR:$Vv32), 33662"$Vd32 = vmpyiewuh($Vu32,$Vv32)", 33663PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 33664let hasNewValue = 1; 33665let opNewValue = 0; 33666let isPseudo = 1; 33667let isCodeGenOnly = 1; 33668let DecoderNamespace = "EXT_mmvec"; 33669} 33670def V6_vmpyih : HInst< 33671(outs HvxVR:$Vd32), 33672(ins HvxVR:$Vu32, HvxVR:$Vv32), 33673"$Vd32.h = vmpyi($Vu32.h,$Vv32.h)", 33674tc_d8287c14, TypeCVI_VX_DV>, Enc_45364e, Requires<[UseHVXV60]> { 33675let Inst{7-5} = 0b100; 33676let Inst{13-13} = 0b0; 33677let Inst{31-21} = 0b00011100001; 33678let hasNewValue = 1; 33679let opNewValue = 0; 33680let DecoderNamespace = "EXT_mmvec"; 33681} 33682def V6_vmpyih_acc : HInst< 33683(outs HvxVR:$Vx32), 33684(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32), 33685"$Vx32.h += vmpyi($Vu32.h,$Vv32.h)", 33686tc_08a4f1b6, TypeCVI_VX_DV>, Enc_a7341a, Requires<[UseHVXV60]> { 33687let Inst{7-5} = 0b100; 33688let Inst{13-13} = 0b1; 33689let Inst{31-21} = 0b00011100001; 33690let hasNewValue = 1; 33691let opNewValue = 0; 33692let isAccumulator = 1; 33693let DecoderNamespace = "EXT_mmvec"; 33694let Constraints = "$Vx32 = $Vx32in"; 33695} 33696def V6_vmpyih_acc_alt : HInst< 33697(outs HvxVR:$Vx32), 33698(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32), 33699"$Vx32 += vmpyih($Vu32,$Vv32)", 33700PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 33701let hasNewValue = 1; 33702let opNewValue = 0; 33703let isAccumulator = 1; 33704let isPseudo = 1; 33705let isCodeGenOnly = 1; 33706let DecoderNamespace = "EXT_mmvec"; 33707let Constraints = "$Vx32 = $Vx32in"; 33708} 33709def V6_vmpyih_alt : HInst< 33710(outs HvxVR:$Vd32), 33711(ins HvxVR:$Vu32, HvxVR:$Vv32), 33712"$Vd32 = vmpyih($Vu32,$Vv32)", 33713PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 33714let hasNewValue = 1; 33715let opNewValue = 0; 33716let isPseudo = 1; 33717let isCodeGenOnly = 1; 33718let DecoderNamespace = "EXT_mmvec"; 33719} 33720def V6_vmpyihb : HInst< 33721(outs HvxVR:$Vd32), 33722(ins HvxVR:$Vu32, IntRegs:$Rt32), 33723"$Vd32.h = vmpyi($Vu32.h,$Rt32.b)", 33724tc_649072c2, TypeCVI_VX>, Enc_b087ac, Requires<[UseHVXV60]> { 33725let Inst{7-5} = 0b000; 33726let Inst{13-13} = 0b0; 33727let Inst{31-21} = 0b00011001011; 33728let hasNewValue = 1; 33729let opNewValue = 0; 33730let DecoderNamespace = "EXT_mmvec"; 33731} 33732def V6_vmpyihb_acc : HInst< 33733(outs HvxVR:$Vx32), 33734(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32), 33735"$Vx32.h += vmpyi($Vu32.h,$Rt32.b)", 33736tc_b091f1c6, TypeCVI_VX>, Enc_5138b3, Requires<[UseHVXV60]> { 33737let Inst{7-5} = 0b001; 33738let Inst{13-13} = 0b1; 33739let Inst{31-21} = 0b00011001011; 33740let hasNewValue = 1; 33741let opNewValue = 0; 33742let isAccumulator = 1; 33743let DecoderNamespace = "EXT_mmvec"; 33744let Constraints = "$Vx32 = $Vx32in"; 33745} 33746def V6_vmpyihb_acc_alt : HInst< 33747(outs HvxVR:$Vx32), 33748(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32), 33749"$Vx32 += vmpyihb($Vu32,$Rt32)", 33750PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 33751let hasNewValue = 1; 33752let opNewValue = 0; 33753let isAccumulator = 1; 33754let isPseudo = 1; 33755let isCodeGenOnly = 1; 33756let DecoderNamespace = "EXT_mmvec"; 33757let Constraints = "$Vx32 = $Vx32in"; 33758} 33759def V6_vmpyihb_alt : HInst< 33760(outs HvxVR:$Vd32), 33761(ins HvxVR:$Vu32, IntRegs:$Rt32), 33762"$Vd32 = vmpyihb($Vu32,$Rt32)", 33763PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 33764let hasNewValue = 1; 33765let opNewValue = 0; 33766let isPseudo = 1; 33767let isCodeGenOnly = 1; 33768let DecoderNamespace = "EXT_mmvec"; 33769} 33770def V6_vmpyiowh : HInst< 33771(outs HvxVR:$Vd32), 33772(ins HvxVR:$Vu32, HvxVR:$Vv32), 33773"$Vd32.w = vmpyio($Vu32.w,$Vv32.h)", 33774tc_d8287c14, TypeCVI_VX_DV>, Enc_45364e, Requires<[UseHVXV60]> { 33775let Inst{7-5} = 0b001; 33776let Inst{13-13} = 0b0; 33777let Inst{31-21} = 0b00011111110; 33778let hasNewValue = 1; 33779let opNewValue = 0; 33780let DecoderNamespace = "EXT_mmvec"; 33781} 33782def V6_vmpyiowh_alt : HInst< 33783(outs HvxVR:$Vd32), 33784(ins HvxVR:$Vu32, HvxVR:$Vv32), 33785"$Vd32 = vmpyiowh($Vu32,$Vv32)", 33786PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 33787let hasNewValue = 1; 33788let opNewValue = 0; 33789let isPseudo = 1; 33790let isCodeGenOnly = 1; 33791let DecoderNamespace = "EXT_mmvec"; 33792} 33793def V6_vmpyiwb : HInst< 33794(outs HvxVR:$Vd32), 33795(ins HvxVR:$Vu32, IntRegs:$Rt32), 33796"$Vd32.w = vmpyi($Vu32.w,$Rt32.b)", 33797tc_649072c2, TypeCVI_VX>, Enc_b087ac, Requires<[UseHVXV60]> { 33798let Inst{7-5} = 0b000; 33799let Inst{13-13} = 0b0; 33800let Inst{31-21} = 0b00011001101; 33801let hasNewValue = 1; 33802let opNewValue = 0; 33803let DecoderNamespace = "EXT_mmvec"; 33804} 33805def V6_vmpyiwb_acc : HInst< 33806(outs HvxVR:$Vx32), 33807(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32), 33808"$Vx32.w += vmpyi($Vu32.w,$Rt32.b)", 33809tc_b091f1c6, TypeCVI_VX>, Enc_5138b3, Requires<[UseHVXV60]> { 33810let Inst{7-5} = 0b010; 33811let Inst{13-13} = 0b1; 33812let Inst{31-21} = 0b00011001010; 33813let hasNewValue = 1; 33814let opNewValue = 0; 33815let isAccumulator = 1; 33816let DecoderNamespace = "EXT_mmvec"; 33817let Constraints = "$Vx32 = $Vx32in"; 33818} 33819def V6_vmpyiwb_acc_alt : HInst< 33820(outs HvxVR:$Vx32), 33821(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32), 33822"$Vx32 += vmpyiwb($Vu32,$Rt32)", 33823PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 33824let hasNewValue = 1; 33825let opNewValue = 0; 33826let isAccumulator = 1; 33827let isPseudo = 1; 33828let isCodeGenOnly = 1; 33829let DecoderNamespace = "EXT_mmvec"; 33830let Constraints = "$Vx32 = $Vx32in"; 33831} 33832def V6_vmpyiwb_alt : HInst< 33833(outs HvxVR:$Vd32), 33834(ins HvxVR:$Vu32, IntRegs:$Rt32), 33835"$Vd32 = vmpyiwb($Vu32,$Rt32)", 33836PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 33837let hasNewValue = 1; 33838let opNewValue = 0; 33839let isPseudo = 1; 33840let isCodeGenOnly = 1; 33841let DecoderNamespace = "EXT_mmvec"; 33842} 33843def V6_vmpyiwh : HInst< 33844(outs HvxVR:$Vd32), 33845(ins HvxVR:$Vu32, IntRegs:$Rt32), 33846"$Vd32.w = vmpyi($Vu32.w,$Rt32.h)", 33847tc_0b04c6c7, TypeCVI_VX_DV>, Enc_b087ac, Requires<[UseHVXV60]> { 33848let Inst{7-5} = 0b111; 33849let Inst{13-13} = 0b0; 33850let Inst{31-21} = 0b00011001100; 33851let hasNewValue = 1; 33852let opNewValue = 0; 33853let DecoderNamespace = "EXT_mmvec"; 33854} 33855def V6_vmpyiwh_acc : HInst< 33856(outs HvxVR:$Vx32), 33857(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32), 33858"$Vx32.w += vmpyi($Vu32.w,$Rt32.h)", 33859tc_660769f1, TypeCVI_VX_DV>, Enc_5138b3, Requires<[UseHVXV60]> { 33860let Inst{7-5} = 0b011; 33861let Inst{13-13} = 0b1; 33862let Inst{31-21} = 0b00011001010; 33863let hasNewValue = 1; 33864let opNewValue = 0; 33865let isAccumulator = 1; 33866let DecoderNamespace = "EXT_mmvec"; 33867let Constraints = "$Vx32 = $Vx32in"; 33868} 33869def V6_vmpyiwh_acc_alt : HInst< 33870(outs HvxVR:$Vx32), 33871(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32), 33872"$Vx32 += vmpyiwh($Vu32,$Rt32)", 33873PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 33874let hasNewValue = 1; 33875let opNewValue = 0; 33876let isAccumulator = 1; 33877let isPseudo = 1; 33878let isCodeGenOnly = 1; 33879let DecoderNamespace = "EXT_mmvec"; 33880let Constraints = "$Vx32 = $Vx32in"; 33881} 33882def V6_vmpyiwh_alt : HInst< 33883(outs HvxVR:$Vd32), 33884(ins HvxVR:$Vu32, IntRegs:$Rt32), 33885"$Vd32 = vmpyiwh($Vu32,$Rt32)", 33886PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 33887let hasNewValue = 1; 33888let opNewValue = 0; 33889let isPseudo = 1; 33890let isCodeGenOnly = 1; 33891let DecoderNamespace = "EXT_mmvec"; 33892} 33893def V6_vmpyiwub : HInst< 33894(outs HvxVR:$Vd32), 33895(ins HvxVR:$Vu32, IntRegs:$Rt32), 33896"$Vd32.w = vmpyi($Vu32.w,$Rt32.ub)", 33897tc_649072c2, TypeCVI_VX>, Enc_b087ac, Requires<[UseHVXV62]> { 33898let Inst{7-5} = 0b110; 33899let Inst{13-13} = 0b0; 33900let Inst{31-21} = 0b00011001100; 33901let hasNewValue = 1; 33902let opNewValue = 0; 33903let DecoderNamespace = "EXT_mmvec"; 33904} 33905def V6_vmpyiwub_acc : HInst< 33906(outs HvxVR:$Vx32), 33907(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32), 33908"$Vx32.w += vmpyi($Vu32.w,$Rt32.ub)", 33909tc_b091f1c6, TypeCVI_VX>, Enc_5138b3, Requires<[UseHVXV62]> { 33910let Inst{7-5} = 0b001; 33911let Inst{13-13} = 0b1; 33912let Inst{31-21} = 0b00011001100; 33913let hasNewValue = 1; 33914let opNewValue = 0; 33915let isAccumulator = 1; 33916let DecoderNamespace = "EXT_mmvec"; 33917let Constraints = "$Vx32 = $Vx32in"; 33918} 33919def V6_vmpyiwub_acc_alt : HInst< 33920(outs HvxVR:$Vx32), 33921(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32), 33922"$Vx32 += vmpyiwub($Vu32,$Rt32)", 33923PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> { 33924let hasNewValue = 1; 33925let opNewValue = 0; 33926let isAccumulator = 1; 33927let isPseudo = 1; 33928let isCodeGenOnly = 1; 33929let DecoderNamespace = "EXT_mmvec"; 33930let Constraints = "$Vx32 = $Vx32in"; 33931} 33932def V6_vmpyiwub_alt : HInst< 33933(outs HvxVR:$Vd32), 33934(ins HvxVR:$Vu32, IntRegs:$Rt32), 33935"$Vd32 = vmpyiwub($Vu32,$Rt32)", 33936PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> { 33937let hasNewValue = 1; 33938let opNewValue = 0; 33939let isPseudo = 1; 33940let isCodeGenOnly = 1; 33941let DecoderNamespace = "EXT_mmvec"; 33942} 33943def V6_vmpyowh : HInst< 33944(outs HvxVR:$Vd32), 33945(ins HvxVR:$Vu32, HvxVR:$Vv32), 33946"$Vd32.w = vmpyo($Vu32.w,$Vv32.h):<<1:sat", 33947tc_d8287c14, TypeCVI_VX_DV>, Enc_45364e, Requires<[UseHVXV60]> { 33948let Inst{7-5} = 0b111; 33949let Inst{13-13} = 0b0; 33950let Inst{31-21} = 0b00011111111; 33951let hasNewValue = 1; 33952let opNewValue = 0; 33953let DecoderNamespace = "EXT_mmvec"; 33954} 33955def V6_vmpyowh_64_acc : HInst< 33956(outs HvxWR:$Vxx32), 33957(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32), 33958"$Vxx32 += vmpyo($Vu32.w,$Vv32.h)", 33959tc_08a4f1b6, TypeCVI_VX_DV>, Enc_3fc427, Requires<[UseHVXV62]> { 33960let Inst{7-5} = 0b011; 33961let Inst{13-13} = 0b1; 33962let Inst{31-21} = 0b00011100001; 33963let hasNewValue = 1; 33964let opNewValue = 0; 33965let isAccumulator = 1; 33966let DecoderNamespace = "EXT_mmvec"; 33967let Constraints = "$Vxx32 = $Vxx32in"; 33968} 33969def V6_vmpyowh_alt : HInst< 33970(outs HvxVR:$Vd32), 33971(ins HvxVR:$Vu32, HvxVR:$Vv32), 33972"$Vd32 = vmpyowh($Vu32,$Vv32):<<1:sat", 33973PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 33974let hasNewValue = 1; 33975let opNewValue = 0; 33976let isPseudo = 1; 33977let isCodeGenOnly = 1; 33978let DecoderNamespace = "EXT_mmvec"; 33979} 33980def V6_vmpyowh_rnd : HInst< 33981(outs HvxVR:$Vd32), 33982(ins HvxVR:$Vu32, HvxVR:$Vv32), 33983"$Vd32.w = vmpyo($Vu32.w,$Vv32.h):<<1:rnd:sat", 33984tc_d8287c14, TypeCVI_VX_DV>, Enc_45364e, Requires<[UseHVXV60]> { 33985let Inst{7-5} = 0b000; 33986let Inst{13-13} = 0b0; 33987let Inst{31-21} = 0b00011111010; 33988let hasNewValue = 1; 33989let opNewValue = 0; 33990let DecoderNamespace = "EXT_mmvec"; 33991} 33992def V6_vmpyowh_rnd_alt : HInst< 33993(outs HvxVR:$Vd32), 33994(ins HvxVR:$Vu32, HvxVR:$Vv32), 33995"$Vd32 = vmpyowh($Vu32,$Vv32):<<1:rnd:sat", 33996PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 33997let hasNewValue = 1; 33998let opNewValue = 0; 33999let isPseudo = 1; 34000let isCodeGenOnly = 1; 34001let DecoderNamespace = "EXT_mmvec"; 34002} 34003def V6_vmpyowh_rnd_sacc : HInst< 34004(outs HvxVR:$Vx32), 34005(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32), 34006"$Vx32.w += vmpyo($Vu32.w,$Vv32.h):<<1:rnd:sat:shift", 34007tc_08a4f1b6, TypeCVI_VX_DV>, Enc_a7341a, Requires<[UseHVXV60]> { 34008let Inst{7-5} = 0b111; 34009let Inst{13-13} = 0b1; 34010let Inst{31-21} = 0b00011100001; 34011let hasNewValue = 1; 34012let opNewValue = 0; 34013let isAccumulator = 1; 34014let DecoderNamespace = "EXT_mmvec"; 34015let Constraints = "$Vx32 = $Vx32in"; 34016} 34017def V6_vmpyowh_rnd_sacc_alt : HInst< 34018(outs HvxVR:$Vx32), 34019(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32), 34020"$Vx32 += vmpyowh($Vu32,$Vv32):<<1:rnd:sat:shift", 34021PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 34022let hasNewValue = 1; 34023let opNewValue = 0; 34024let isAccumulator = 1; 34025let isPseudo = 1; 34026let DecoderNamespace = "EXT_mmvec"; 34027let Constraints = "$Vx32 = $Vx32in"; 34028} 34029def V6_vmpyowh_sacc : HInst< 34030(outs HvxVR:$Vx32), 34031(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32), 34032"$Vx32.w += vmpyo($Vu32.w,$Vv32.h):<<1:sat:shift", 34033tc_08a4f1b6, TypeCVI_VX_DV>, Enc_a7341a, Requires<[UseHVXV60]> { 34034let Inst{7-5} = 0b110; 34035let Inst{13-13} = 0b1; 34036let Inst{31-21} = 0b00011100001; 34037let hasNewValue = 1; 34038let opNewValue = 0; 34039let isAccumulator = 1; 34040let DecoderNamespace = "EXT_mmvec"; 34041let Constraints = "$Vx32 = $Vx32in"; 34042} 34043def V6_vmpyowh_sacc_alt : HInst< 34044(outs HvxVR:$Vx32), 34045(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32), 34046"$Vx32 += vmpyowh($Vu32,$Vv32):<<1:sat:shift", 34047PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 34048let hasNewValue = 1; 34049let opNewValue = 0; 34050let isAccumulator = 1; 34051let isPseudo = 1; 34052let DecoderNamespace = "EXT_mmvec"; 34053let Constraints = "$Vx32 = $Vx32in"; 34054} 34055def V6_vmpyub : HInst< 34056(outs HvxWR:$Vdd32), 34057(ins HvxVR:$Vu32, IntRegs:$Rt32), 34058"$Vdd32.uh = vmpy($Vu32.ub,$Rt32.ub)", 34059tc_0b04c6c7, TypeCVI_VX_DV>, Enc_01d3d0, Requires<[UseHVXV60]> { 34060let Inst{7-5} = 0b000; 34061let Inst{13-13} = 0b0; 34062let Inst{31-21} = 0b00011001110; 34063let hasNewValue = 1; 34064let opNewValue = 0; 34065let DecoderNamespace = "EXT_mmvec"; 34066} 34067def V6_vmpyub_acc : HInst< 34068(outs HvxWR:$Vxx32), 34069(ins HvxWR:$Vxx32in, HvxVR:$Vu32, IntRegs:$Rt32), 34070"$Vxx32.uh += vmpy($Vu32.ub,$Rt32.ub)", 34071tc_660769f1, TypeCVI_VX_DV>, Enc_5e8512, Requires<[UseHVXV60]> { 34072let Inst{7-5} = 0b000; 34073let Inst{13-13} = 0b1; 34074let Inst{31-21} = 0b00011001100; 34075let hasNewValue = 1; 34076let opNewValue = 0; 34077let isAccumulator = 1; 34078let DecoderNamespace = "EXT_mmvec"; 34079let Constraints = "$Vxx32 = $Vxx32in"; 34080} 34081def V6_vmpyub_acc_alt : HInst< 34082(outs HvxWR:$Vxx32), 34083(ins HvxWR:$Vxx32in, HvxVR:$Vu32, IntRegs:$Rt32), 34084"$Vxx32 += vmpyub($Vu32,$Rt32)", 34085PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 34086let hasNewValue = 1; 34087let opNewValue = 0; 34088let isAccumulator = 1; 34089let isPseudo = 1; 34090let isCodeGenOnly = 1; 34091let DecoderNamespace = "EXT_mmvec"; 34092let Constraints = "$Vxx32 = $Vxx32in"; 34093} 34094def V6_vmpyub_alt : HInst< 34095(outs HvxWR:$Vdd32), 34096(ins HvxVR:$Vu32, IntRegs:$Rt32), 34097"$Vdd32 = vmpyub($Vu32,$Rt32)", 34098PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 34099let hasNewValue = 1; 34100let opNewValue = 0; 34101let isPseudo = 1; 34102let isCodeGenOnly = 1; 34103let DecoderNamespace = "EXT_mmvec"; 34104} 34105def V6_vmpyubv : HInst< 34106(outs HvxWR:$Vdd32), 34107(ins HvxVR:$Vu32, HvxVR:$Vv32), 34108"$Vdd32.uh = vmpy($Vu32.ub,$Vv32.ub)", 34109tc_d8287c14, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV60]> { 34110let Inst{7-5} = 0b101; 34111let Inst{13-13} = 0b0; 34112let Inst{31-21} = 0b00011100000; 34113let hasNewValue = 1; 34114let opNewValue = 0; 34115let DecoderNamespace = "EXT_mmvec"; 34116} 34117def V6_vmpyubv_acc : HInst< 34118(outs HvxWR:$Vxx32), 34119(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32), 34120"$Vxx32.uh += vmpy($Vu32.ub,$Vv32.ub)", 34121tc_08a4f1b6, TypeCVI_VX_DV>, Enc_3fc427, Requires<[UseHVXV60]> { 34122let Inst{7-5} = 0b101; 34123let Inst{13-13} = 0b1; 34124let Inst{31-21} = 0b00011100000; 34125let hasNewValue = 1; 34126let opNewValue = 0; 34127let isAccumulator = 1; 34128let DecoderNamespace = "EXT_mmvec"; 34129let Constraints = "$Vxx32 = $Vxx32in"; 34130} 34131def V6_vmpyubv_acc_alt : HInst< 34132(outs HvxWR:$Vxx32), 34133(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32), 34134"$Vxx32 += vmpyub($Vu32,$Vv32)", 34135PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 34136let hasNewValue = 1; 34137let opNewValue = 0; 34138let isAccumulator = 1; 34139let isPseudo = 1; 34140let isCodeGenOnly = 1; 34141let DecoderNamespace = "EXT_mmvec"; 34142let Constraints = "$Vxx32 = $Vxx32in"; 34143} 34144def V6_vmpyubv_alt : HInst< 34145(outs HvxWR:$Vdd32), 34146(ins HvxVR:$Vu32, HvxVR:$Vv32), 34147"$Vdd32 = vmpyub($Vu32,$Vv32)", 34148PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 34149let hasNewValue = 1; 34150let opNewValue = 0; 34151let isPseudo = 1; 34152let isCodeGenOnly = 1; 34153let DecoderNamespace = "EXT_mmvec"; 34154} 34155def V6_vmpyuh : HInst< 34156(outs HvxWR:$Vdd32), 34157(ins HvxVR:$Vu32, IntRegs:$Rt32), 34158"$Vdd32.uw = vmpy($Vu32.uh,$Rt32.uh)", 34159tc_0b04c6c7, TypeCVI_VX_DV>, Enc_01d3d0, Requires<[UseHVXV60]> { 34160let Inst{7-5} = 0b011; 34161let Inst{13-13} = 0b0; 34162let Inst{31-21} = 0b00011001010; 34163let hasNewValue = 1; 34164let opNewValue = 0; 34165let DecoderNamespace = "EXT_mmvec"; 34166} 34167def V6_vmpyuh_acc : HInst< 34168(outs HvxWR:$Vxx32), 34169(ins HvxWR:$Vxx32in, HvxVR:$Vu32, IntRegs:$Rt32), 34170"$Vxx32.uw += vmpy($Vu32.uh,$Rt32.uh)", 34171tc_660769f1, TypeCVI_VX_DV>, Enc_5e8512, Requires<[UseHVXV60]> { 34172let Inst{7-5} = 0b001; 34173let Inst{13-13} = 0b1; 34174let Inst{31-21} = 0b00011001010; 34175let hasNewValue = 1; 34176let opNewValue = 0; 34177let isAccumulator = 1; 34178let DecoderNamespace = "EXT_mmvec"; 34179let Constraints = "$Vxx32 = $Vxx32in"; 34180} 34181def V6_vmpyuh_acc_alt : HInst< 34182(outs HvxWR:$Vxx32), 34183(ins HvxWR:$Vxx32in, HvxVR:$Vu32, IntRegs:$Rt32), 34184"$Vxx32 += vmpyuh($Vu32,$Rt32)", 34185PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 34186let hasNewValue = 1; 34187let opNewValue = 0; 34188let isAccumulator = 1; 34189let isPseudo = 1; 34190let isCodeGenOnly = 1; 34191let DecoderNamespace = "EXT_mmvec"; 34192let Constraints = "$Vxx32 = $Vxx32in"; 34193} 34194def V6_vmpyuh_alt : HInst< 34195(outs HvxWR:$Vdd32), 34196(ins HvxVR:$Vu32, IntRegs:$Rt32), 34197"$Vdd32 = vmpyuh($Vu32,$Rt32)", 34198PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 34199let hasNewValue = 1; 34200let opNewValue = 0; 34201let isPseudo = 1; 34202let isCodeGenOnly = 1; 34203let DecoderNamespace = "EXT_mmvec"; 34204} 34205def V6_vmpyuhe : HInst< 34206(outs HvxVR:$Vd32), 34207(ins HvxVR:$Vu32, IntRegs:$Rt32), 34208"$Vd32.uw = vmpye($Vu32.uh,$Rt32.uh)", 34209tc_649072c2, TypeCVI_VX>, Enc_b087ac, Requires<[UseHVXV65]> { 34210let Inst{7-5} = 0b010; 34211let Inst{13-13} = 0b0; 34212let Inst{31-21} = 0b00011001011; 34213let hasNewValue = 1; 34214let opNewValue = 0; 34215let DecoderNamespace = "EXT_mmvec"; 34216} 34217def V6_vmpyuhe_acc : HInst< 34218(outs HvxVR:$Vx32), 34219(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32), 34220"$Vx32.uw += vmpye($Vu32.uh,$Rt32.uh)", 34221tc_b091f1c6, TypeCVI_VX>, Enc_5138b3, Requires<[UseHVXV65]> { 34222let Inst{7-5} = 0b011; 34223let Inst{13-13} = 0b1; 34224let Inst{31-21} = 0b00011001100; 34225let hasNewValue = 1; 34226let opNewValue = 0; 34227let isAccumulator = 1; 34228let DecoderNamespace = "EXT_mmvec"; 34229let Constraints = "$Vx32 = $Vx32in"; 34230} 34231def V6_vmpyuhv : HInst< 34232(outs HvxWR:$Vdd32), 34233(ins HvxVR:$Vu32, HvxVR:$Vv32), 34234"$Vdd32.uw = vmpy($Vu32.uh,$Vv32.uh)", 34235tc_d8287c14, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV60]> { 34236let Inst{7-5} = 0b000; 34237let Inst{13-13} = 0b0; 34238let Inst{31-21} = 0b00011100001; 34239let hasNewValue = 1; 34240let opNewValue = 0; 34241let DecoderNamespace = "EXT_mmvec"; 34242} 34243def V6_vmpyuhv_acc : HInst< 34244(outs HvxWR:$Vxx32), 34245(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32), 34246"$Vxx32.uw += vmpy($Vu32.uh,$Vv32.uh)", 34247tc_08a4f1b6, TypeCVI_VX_DV>, Enc_3fc427, Requires<[UseHVXV60]> { 34248let Inst{7-5} = 0b000; 34249let Inst{13-13} = 0b1; 34250let Inst{31-21} = 0b00011100001; 34251let hasNewValue = 1; 34252let opNewValue = 0; 34253let isAccumulator = 1; 34254let DecoderNamespace = "EXT_mmvec"; 34255let Constraints = "$Vxx32 = $Vxx32in"; 34256} 34257def V6_vmpyuhv_acc_alt : HInst< 34258(outs HvxWR:$Vxx32), 34259(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32), 34260"$Vxx32 += vmpyuh($Vu32,$Vv32)", 34261PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 34262let hasNewValue = 1; 34263let opNewValue = 0; 34264let isAccumulator = 1; 34265let isPseudo = 1; 34266let isCodeGenOnly = 1; 34267let DecoderNamespace = "EXT_mmvec"; 34268let Constraints = "$Vxx32 = $Vxx32in"; 34269} 34270def V6_vmpyuhv_alt : HInst< 34271(outs HvxWR:$Vdd32), 34272(ins HvxVR:$Vu32, HvxVR:$Vv32), 34273"$Vdd32 = vmpyuh($Vu32,$Vv32)", 34274PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 34275let hasNewValue = 1; 34276let opNewValue = 0; 34277let isPseudo = 1; 34278let isCodeGenOnly = 1; 34279let DecoderNamespace = "EXT_mmvec"; 34280} 34281def V6_vmux : HInst< 34282(outs HvxVR:$Vd32), 34283(ins HvxQR:$Qt4, HvxVR:$Vu32, HvxVR:$Vv32), 34284"$Vd32 = vmux($Qt4,$Vu32,$Vv32)", 34285tc_257f6f7c, TypeCVI_VA>, Enc_31db33, Requires<[UseHVXV60]> { 34286let Inst{7-7} = 0b0; 34287let Inst{13-13} = 0b1; 34288let Inst{31-21} = 0b00011110111; 34289let hasNewValue = 1; 34290let opNewValue = 0; 34291let DecoderNamespace = "EXT_mmvec"; 34292} 34293def V6_vnavgb : HInst< 34294(outs HvxVR:$Vd32), 34295(ins HvxVR:$Vu32, HvxVR:$Vv32), 34296"$Vd32.b = vnavg($Vu32.b,$Vv32.b)", 34297tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV65]> { 34298let Inst{7-5} = 0b110; 34299let Inst{13-13} = 0b1; 34300let Inst{31-21} = 0b00011111000; 34301let hasNewValue = 1; 34302let opNewValue = 0; 34303let DecoderNamespace = "EXT_mmvec"; 34304} 34305def V6_vnavgb_alt : HInst< 34306(outs HvxVR:$Vd32), 34307(ins HvxVR:$Vu32, HvxVR:$Vv32), 34308"$Vd32 = vnavgb($Vu32,$Vv32)", 34309PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> { 34310let hasNewValue = 1; 34311let opNewValue = 0; 34312let isPseudo = 1; 34313let isCodeGenOnly = 1; 34314let DecoderNamespace = "EXT_mmvec"; 34315} 34316def V6_vnavgh : HInst< 34317(outs HvxVR:$Vd32), 34318(ins HvxVR:$Vu32, HvxVR:$Vv32), 34319"$Vd32.h = vnavg($Vu32.h,$Vv32.h)", 34320tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> { 34321let Inst{7-5} = 0b001; 34322let Inst{13-13} = 0b0; 34323let Inst{31-21} = 0b00011100111; 34324let hasNewValue = 1; 34325let opNewValue = 0; 34326let DecoderNamespace = "EXT_mmvec"; 34327} 34328def V6_vnavgh_alt : HInst< 34329(outs HvxVR:$Vd32), 34330(ins HvxVR:$Vu32, HvxVR:$Vv32), 34331"$Vd32 = vnavgh($Vu32,$Vv32)", 34332PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 34333let hasNewValue = 1; 34334let opNewValue = 0; 34335let isPseudo = 1; 34336let isCodeGenOnly = 1; 34337let DecoderNamespace = "EXT_mmvec"; 34338} 34339def V6_vnavgub : HInst< 34340(outs HvxVR:$Vd32), 34341(ins HvxVR:$Vu32, HvxVR:$Vv32), 34342"$Vd32.b = vnavg($Vu32.ub,$Vv32.ub)", 34343tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> { 34344let Inst{7-5} = 0b000; 34345let Inst{13-13} = 0b0; 34346let Inst{31-21} = 0b00011100111; 34347let hasNewValue = 1; 34348let opNewValue = 0; 34349let DecoderNamespace = "EXT_mmvec"; 34350} 34351def V6_vnavgub_alt : HInst< 34352(outs HvxVR:$Vd32), 34353(ins HvxVR:$Vu32, HvxVR:$Vv32), 34354"$Vd32 = vnavgub($Vu32,$Vv32)", 34355PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 34356let hasNewValue = 1; 34357let opNewValue = 0; 34358let isPseudo = 1; 34359let isCodeGenOnly = 1; 34360let DecoderNamespace = "EXT_mmvec"; 34361} 34362def V6_vnavgw : HInst< 34363(outs HvxVR:$Vd32), 34364(ins HvxVR:$Vu32, HvxVR:$Vv32), 34365"$Vd32.w = vnavg($Vu32.w,$Vv32.w)", 34366tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> { 34367let Inst{7-5} = 0b010; 34368let Inst{13-13} = 0b0; 34369let Inst{31-21} = 0b00011100111; 34370let hasNewValue = 1; 34371let opNewValue = 0; 34372let DecoderNamespace = "EXT_mmvec"; 34373} 34374def V6_vnavgw_alt : HInst< 34375(outs HvxVR:$Vd32), 34376(ins HvxVR:$Vu32, HvxVR:$Vv32), 34377"$Vd32 = vnavgw($Vu32,$Vv32)", 34378PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 34379let hasNewValue = 1; 34380let opNewValue = 0; 34381let isPseudo = 1; 34382let isCodeGenOnly = 1; 34383let DecoderNamespace = "EXT_mmvec"; 34384} 34385def V6_vnccombine : HInst< 34386(outs HvxWR:$Vdd32), 34387(ins PredRegs:$Ps4, HvxVR:$Vu32, HvxVR:$Vv32), 34388"if (!$Ps4) $Vdd32 = vcombine($Vu32,$Vv32)", 34389tc_af25efd9, TypeCVI_VA_DV>, Enc_8c2412, Requires<[UseHVXV60]> { 34390let Inst{7-7} = 0b0; 34391let Inst{13-13} = 0b0; 34392let Inst{31-21} = 0b00011010010; 34393let isPredicated = 1; 34394let isPredicatedFalse = 1; 34395let hasNewValue = 1; 34396let opNewValue = 0; 34397let DecoderNamespace = "EXT_mmvec"; 34398} 34399def V6_vncmov : HInst< 34400(outs HvxVR:$Vd32), 34401(ins PredRegs:$Ps4, HvxVR:$Vu32), 34402"if (!$Ps4) $Vd32 = $Vu32", 34403tc_3aacf4a8, TypeCVI_VA>, Enc_770858, Requires<[UseHVXV60]> { 34404let Inst{7-7} = 0b0; 34405let Inst{13-13} = 0b0; 34406let Inst{31-16} = 0b0001101000100000; 34407let isPredicated = 1; 34408let isPredicatedFalse = 1; 34409let hasNewValue = 1; 34410let opNewValue = 0; 34411let DecoderNamespace = "EXT_mmvec"; 34412} 34413def V6_vnormamth : HInst< 34414(outs HvxVR:$Vd32), 34415(ins HvxVR:$Vu32), 34416"$Vd32.h = vnormamt($Vu32.h)", 34417tc_51d0ecc3, TypeCVI_VS>, Enc_e7581c, Requires<[UseHVXV60]> { 34418let Inst{7-5} = 0b101; 34419let Inst{13-13} = 0b0; 34420let Inst{31-16} = 0b0001111000000011; 34421let hasNewValue = 1; 34422let opNewValue = 0; 34423let DecoderNamespace = "EXT_mmvec"; 34424} 34425def V6_vnormamth_alt : HInst< 34426(outs HvxVR:$Vd32), 34427(ins HvxVR:$Vu32), 34428"$Vd32 = vnormamth($Vu32)", 34429PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 34430let hasNewValue = 1; 34431let opNewValue = 0; 34432let isPseudo = 1; 34433let isCodeGenOnly = 1; 34434let DecoderNamespace = "EXT_mmvec"; 34435} 34436def V6_vnormamtw : HInst< 34437(outs HvxVR:$Vd32), 34438(ins HvxVR:$Vu32), 34439"$Vd32.w = vnormamt($Vu32.w)", 34440tc_51d0ecc3, TypeCVI_VS>, Enc_e7581c, Requires<[UseHVXV60]> { 34441let Inst{7-5} = 0b100; 34442let Inst{13-13} = 0b0; 34443let Inst{31-16} = 0b0001111000000011; 34444let hasNewValue = 1; 34445let opNewValue = 0; 34446let DecoderNamespace = "EXT_mmvec"; 34447} 34448def V6_vnormamtw_alt : HInst< 34449(outs HvxVR:$Vd32), 34450(ins HvxVR:$Vu32), 34451"$Vd32 = vnormamtw($Vu32)", 34452PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 34453let hasNewValue = 1; 34454let opNewValue = 0; 34455let isPseudo = 1; 34456let isCodeGenOnly = 1; 34457let DecoderNamespace = "EXT_mmvec"; 34458} 34459def V6_vnot : HInst< 34460(outs HvxVR:$Vd32), 34461(ins HvxVR:$Vu32), 34462"$Vd32 = vnot($Vu32)", 34463tc_0ec46cf9, TypeCVI_VA>, Enc_e7581c, Requires<[UseHVXV60]> { 34464let Inst{7-5} = 0b100; 34465let Inst{13-13} = 0b0; 34466let Inst{31-16} = 0b0001111000000000; 34467let hasNewValue = 1; 34468let opNewValue = 0; 34469let DecoderNamespace = "EXT_mmvec"; 34470} 34471def V6_vor : HInst< 34472(outs HvxVR:$Vd32), 34473(ins HvxVR:$Vu32, HvxVR:$Vv32), 34474"$Vd32 = vor($Vu32,$Vv32)", 34475tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> { 34476let Inst{7-5} = 0b110; 34477let Inst{13-13} = 0b0; 34478let Inst{31-21} = 0b00011100001; 34479let hasNewValue = 1; 34480let opNewValue = 0; 34481let DecoderNamespace = "EXT_mmvec"; 34482} 34483def V6_vpackeb : HInst< 34484(outs HvxVR:$Vd32), 34485(ins HvxVR:$Vu32, HvxVR:$Vv32), 34486"$Vd32.b = vpacke($Vu32.h,$Vv32.h)", 34487tc_46d6c3e0, TypeCVI_VP>, Enc_45364e, Requires<[UseHVXV60]> { 34488let Inst{7-5} = 0b010; 34489let Inst{13-13} = 0b0; 34490let Inst{31-21} = 0b00011111110; 34491let hasNewValue = 1; 34492let opNewValue = 0; 34493let DecoderNamespace = "EXT_mmvec"; 34494} 34495def V6_vpackeb_alt : HInst< 34496(outs HvxVR:$Vd32), 34497(ins HvxVR:$Vu32, HvxVR:$Vv32), 34498"$Vd32 = vpackeb($Vu32,$Vv32)", 34499PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 34500let hasNewValue = 1; 34501let opNewValue = 0; 34502let isPseudo = 1; 34503let isCodeGenOnly = 1; 34504let DecoderNamespace = "EXT_mmvec"; 34505} 34506def V6_vpackeh : HInst< 34507(outs HvxVR:$Vd32), 34508(ins HvxVR:$Vu32, HvxVR:$Vv32), 34509"$Vd32.h = vpacke($Vu32.w,$Vv32.w)", 34510tc_46d6c3e0, TypeCVI_VP>, Enc_45364e, Requires<[UseHVXV60]> { 34511let Inst{7-5} = 0b011; 34512let Inst{13-13} = 0b0; 34513let Inst{31-21} = 0b00011111110; 34514let hasNewValue = 1; 34515let opNewValue = 0; 34516let DecoderNamespace = "EXT_mmvec"; 34517} 34518def V6_vpackeh_alt : HInst< 34519(outs HvxVR:$Vd32), 34520(ins HvxVR:$Vu32, HvxVR:$Vv32), 34521"$Vd32 = vpackeh($Vu32,$Vv32)", 34522PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 34523let hasNewValue = 1; 34524let opNewValue = 0; 34525let isPseudo = 1; 34526let isCodeGenOnly = 1; 34527let DecoderNamespace = "EXT_mmvec"; 34528} 34529def V6_vpackhb_sat : HInst< 34530(outs HvxVR:$Vd32), 34531(ins HvxVR:$Vu32, HvxVR:$Vv32), 34532"$Vd32.b = vpack($Vu32.h,$Vv32.h):sat", 34533tc_46d6c3e0, TypeCVI_VP>, Enc_45364e, Requires<[UseHVXV60]> { 34534let Inst{7-5} = 0b110; 34535let Inst{13-13} = 0b0; 34536let Inst{31-21} = 0b00011111110; 34537let hasNewValue = 1; 34538let opNewValue = 0; 34539let DecoderNamespace = "EXT_mmvec"; 34540} 34541def V6_vpackhb_sat_alt : HInst< 34542(outs HvxVR:$Vd32), 34543(ins HvxVR:$Vu32, HvxVR:$Vv32), 34544"$Vd32 = vpackhb($Vu32,$Vv32):sat", 34545PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 34546let hasNewValue = 1; 34547let opNewValue = 0; 34548let isPseudo = 1; 34549let isCodeGenOnly = 1; 34550let DecoderNamespace = "EXT_mmvec"; 34551} 34552def V6_vpackhub_sat : HInst< 34553(outs HvxVR:$Vd32), 34554(ins HvxVR:$Vu32, HvxVR:$Vv32), 34555"$Vd32.ub = vpack($Vu32.h,$Vv32.h):sat", 34556tc_46d6c3e0, TypeCVI_VP>, Enc_45364e, Requires<[UseHVXV60]> { 34557let Inst{7-5} = 0b101; 34558let Inst{13-13} = 0b0; 34559let Inst{31-21} = 0b00011111110; 34560let hasNewValue = 1; 34561let opNewValue = 0; 34562let DecoderNamespace = "EXT_mmvec"; 34563} 34564def V6_vpackhub_sat_alt : HInst< 34565(outs HvxVR:$Vd32), 34566(ins HvxVR:$Vu32, HvxVR:$Vv32), 34567"$Vd32 = vpackhub($Vu32,$Vv32):sat", 34568PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 34569let hasNewValue = 1; 34570let opNewValue = 0; 34571let isPseudo = 1; 34572let isCodeGenOnly = 1; 34573let DecoderNamespace = "EXT_mmvec"; 34574} 34575def V6_vpackob : HInst< 34576(outs HvxVR:$Vd32), 34577(ins HvxVR:$Vu32, HvxVR:$Vv32), 34578"$Vd32.b = vpacko($Vu32.h,$Vv32.h)", 34579tc_46d6c3e0, TypeCVI_VP>, Enc_45364e, Requires<[UseHVXV60]> { 34580let Inst{7-5} = 0b001; 34581let Inst{13-13} = 0b0; 34582let Inst{31-21} = 0b00011111111; 34583let hasNewValue = 1; 34584let opNewValue = 0; 34585let DecoderNamespace = "EXT_mmvec"; 34586} 34587def V6_vpackob_alt : HInst< 34588(outs HvxVR:$Vd32), 34589(ins HvxVR:$Vu32, HvxVR:$Vv32), 34590"$Vd32 = vpackob($Vu32,$Vv32)", 34591PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 34592let hasNewValue = 1; 34593let opNewValue = 0; 34594let isPseudo = 1; 34595let isCodeGenOnly = 1; 34596let DecoderNamespace = "EXT_mmvec"; 34597} 34598def V6_vpackoh : HInst< 34599(outs HvxVR:$Vd32), 34600(ins HvxVR:$Vu32, HvxVR:$Vv32), 34601"$Vd32.h = vpacko($Vu32.w,$Vv32.w)", 34602tc_46d6c3e0, TypeCVI_VP>, Enc_45364e, Requires<[UseHVXV60]> { 34603let Inst{7-5} = 0b010; 34604let Inst{13-13} = 0b0; 34605let Inst{31-21} = 0b00011111111; 34606let hasNewValue = 1; 34607let opNewValue = 0; 34608let DecoderNamespace = "EXT_mmvec"; 34609} 34610def V6_vpackoh_alt : HInst< 34611(outs HvxVR:$Vd32), 34612(ins HvxVR:$Vu32, HvxVR:$Vv32), 34613"$Vd32 = vpackoh($Vu32,$Vv32)", 34614PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 34615let hasNewValue = 1; 34616let opNewValue = 0; 34617let isPseudo = 1; 34618let isCodeGenOnly = 1; 34619let DecoderNamespace = "EXT_mmvec"; 34620} 34621def V6_vpackwh_sat : HInst< 34622(outs HvxVR:$Vd32), 34623(ins HvxVR:$Vu32, HvxVR:$Vv32), 34624"$Vd32.h = vpack($Vu32.w,$Vv32.w):sat", 34625tc_46d6c3e0, TypeCVI_VP>, Enc_45364e, Requires<[UseHVXV60]> { 34626let Inst{7-5} = 0b000; 34627let Inst{13-13} = 0b0; 34628let Inst{31-21} = 0b00011111111; 34629let hasNewValue = 1; 34630let opNewValue = 0; 34631let DecoderNamespace = "EXT_mmvec"; 34632} 34633def V6_vpackwh_sat_alt : HInst< 34634(outs HvxVR:$Vd32), 34635(ins HvxVR:$Vu32, HvxVR:$Vv32), 34636"$Vd32 = vpackwh($Vu32,$Vv32):sat", 34637PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 34638let hasNewValue = 1; 34639let opNewValue = 0; 34640let isPseudo = 1; 34641let isCodeGenOnly = 1; 34642let DecoderNamespace = "EXT_mmvec"; 34643} 34644def V6_vpackwuh_sat : HInst< 34645(outs HvxVR:$Vd32), 34646(ins HvxVR:$Vu32, HvxVR:$Vv32), 34647"$Vd32.uh = vpack($Vu32.w,$Vv32.w):sat", 34648tc_46d6c3e0, TypeCVI_VP>, Enc_45364e, Requires<[UseHVXV60]> { 34649let Inst{7-5} = 0b111; 34650let Inst{13-13} = 0b0; 34651let Inst{31-21} = 0b00011111110; 34652let hasNewValue = 1; 34653let opNewValue = 0; 34654let DecoderNamespace = "EXT_mmvec"; 34655} 34656def V6_vpackwuh_sat_alt : HInst< 34657(outs HvxVR:$Vd32), 34658(ins HvxVR:$Vu32, HvxVR:$Vv32), 34659"$Vd32 = vpackwuh($Vu32,$Vv32):sat", 34660PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 34661let hasNewValue = 1; 34662let opNewValue = 0; 34663let isPseudo = 1; 34664let isCodeGenOnly = 1; 34665let DecoderNamespace = "EXT_mmvec"; 34666} 34667def V6_vpopcounth : HInst< 34668(outs HvxVR:$Vd32), 34669(ins HvxVR:$Vu32), 34670"$Vd32.h = vpopcount($Vu32.h)", 34671tc_51d0ecc3, TypeCVI_VS>, Enc_e7581c, Requires<[UseHVXV60]> { 34672let Inst{7-5} = 0b110; 34673let Inst{13-13} = 0b0; 34674let Inst{31-16} = 0b0001111000000010; 34675let hasNewValue = 1; 34676let opNewValue = 0; 34677let DecoderNamespace = "EXT_mmvec"; 34678} 34679def V6_vpopcounth_alt : HInst< 34680(outs HvxVR:$Vd32), 34681(ins HvxVR:$Vu32), 34682"$Vd32 = vpopcounth($Vu32)", 34683PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 34684let hasNewValue = 1; 34685let opNewValue = 0; 34686let isPseudo = 1; 34687let isCodeGenOnly = 1; 34688let DecoderNamespace = "EXT_mmvec"; 34689} 34690def V6_vprefixqb : HInst< 34691(outs HvxVR:$Vd32), 34692(ins HvxQR:$Qv4), 34693"$Vd32.b = prefixsum($Qv4)", 34694tc_51d0ecc3, TypeCVI_VS>, Enc_6f83e7, Requires<[UseHVXV65]> { 34695let Inst{13-5} = 0b100000010; 34696let Inst{21-16} = 0b000011; 34697let Inst{31-24} = 0b00011110; 34698let hasNewValue = 1; 34699let opNewValue = 0; 34700let DecoderNamespace = "EXT_mmvec"; 34701} 34702def V6_vprefixqh : HInst< 34703(outs HvxVR:$Vd32), 34704(ins HvxQR:$Qv4), 34705"$Vd32.h = prefixsum($Qv4)", 34706tc_51d0ecc3, TypeCVI_VS>, Enc_6f83e7, Requires<[UseHVXV65]> { 34707let Inst{13-5} = 0b100001010; 34708let Inst{21-16} = 0b000011; 34709let Inst{31-24} = 0b00011110; 34710let hasNewValue = 1; 34711let opNewValue = 0; 34712let DecoderNamespace = "EXT_mmvec"; 34713} 34714def V6_vprefixqw : HInst< 34715(outs HvxVR:$Vd32), 34716(ins HvxQR:$Qv4), 34717"$Vd32.w = prefixsum($Qv4)", 34718tc_51d0ecc3, TypeCVI_VS>, Enc_6f83e7, Requires<[UseHVXV65]> { 34719let Inst{13-5} = 0b100010010; 34720let Inst{21-16} = 0b000011; 34721let Inst{31-24} = 0b00011110; 34722let hasNewValue = 1; 34723let opNewValue = 0; 34724let DecoderNamespace = "EXT_mmvec"; 34725} 34726def V6_vrdelta : HInst< 34727(outs HvxVR:$Vd32), 34728(ins HvxVR:$Vu32, HvxVR:$Vv32), 34729"$Vd32 = vrdelta($Vu32,$Vv32)", 34730tc_46d6c3e0, TypeCVI_VP>, Enc_45364e, Requires<[UseHVXV60]> { 34731let Inst{7-5} = 0b011; 34732let Inst{13-13} = 0b0; 34733let Inst{31-21} = 0b00011111001; 34734let hasNewValue = 1; 34735let opNewValue = 0; 34736let DecoderNamespace = "EXT_mmvec"; 34737} 34738def V6_vrmpybub_rtt : HInst< 34739(outs HvxWR:$Vdd32), 34740(ins HvxVR:$Vu32, DoubleRegs:$Rtt32), 34741"$Vdd32.w = vrmpy($Vu32.b,$Rtt32.ub)", 34742tc_cd94bfe0, TypeCVI_VS_VX>, Enc_cb785b, Requires<[UseHVXV65]> { 34743let Inst{7-5} = 0b101; 34744let Inst{13-13} = 0b0; 34745let Inst{31-21} = 0b00011001110; 34746let hasNewValue = 1; 34747let opNewValue = 0; 34748let DecoderNamespace = "EXT_mmvec"; 34749} 34750def V6_vrmpybub_rtt_acc : HInst< 34751(outs HvxWR:$Vxx32), 34752(ins HvxWR:$Vxx32in, HvxVR:$Vu32, DoubleRegs:$Rtt32), 34753"$Vxx32.w += vrmpy($Vu32.b,$Rtt32.ub)", 34754tc_15fdf750, TypeCVI_VS_VX>, Enc_ad9bef, Requires<[UseHVXV65]> { 34755let Inst{7-5} = 0b000; 34756let Inst{13-13} = 0b1; 34757let Inst{31-21} = 0b00011001101; 34758let hasNewValue = 1; 34759let opNewValue = 0; 34760let isAccumulator = 1; 34761let DecoderNamespace = "EXT_mmvec"; 34762let Constraints = "$Vxx32 = $Vxx32in"; 34763} 34764def V6_vrmpybub_rtt_acc_alt : HInst< 34765(outs HvxWR:$Vxx32), 34766(ins HvxWR:$Vxx32in, HvxVR:$Vu32, DoubleRegs:$Rtt32), 34767"$Vxx32.w += vrmpy($Vu32.b,$Rtt32.ub)", 34768PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> { 34769let hasNewValue = 1; 34770let opNewValue = 0; 34771let isAccumulator = 1; 34772let isPseudo = 1; 34773let isCodeGenOnly = 1; 34774let DecoderNamespace = "EXT_mmvec"; 34775let Constraints = "$Vxx32 = $Vxx32in"; 34776} 34777def V6_vrmpybub_rtt_alt : HInst< 34778(outs HvxWR:$Vdd32), 34779(ins HvxVR:$Vu32, DoubleRegs:$Rtt32), 34780"$Vdd32.w = vrmpy($Vu32.b,$Rtt32.ub)", 34781PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> { 34782let hasNewValue = 1; 34783let opNewValue = 0; 34784let isPseudo = 1; 34785let isCodeGenOnly = 1; 34786let DecoderNamespace = "EXT_mmvec"; 34787} 34788def V6_vrmpybus : HInst< 34789(outs HvxVR:$Vd32), 34790(ins HvxVR:$Vu32, IntRegs:$Rt32), 34791"$Vd32.w = vrmpy($Vu32.ub,$Rt32.b)", 34792tc_649072c2, TypeCVI_VX>, Enc_b087ac, Requires<[UseHVXV60]> { 34793let Inst{7-5} = 0b100; 34794let Inst{13-13} = 0b0; 34795let Inst{31-21} = 0b00011001000; 34796let hasNewValue = 1; 34797let opNewValue = 0; 34798let DecoderNamespace = "EXT_mmvec"; 34799} 34800def V6_vrmpybus_acc : HInst< 34801(outs HvxVR:$Vx32), 34802(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32), 34803"$Vx32.w += vrmpy($Vu32.ub,$Rt32.b)", 34804tc_b091f1c6, TypeCVI_VX>, Enc_5138b3, Requires<[UseHVXV60]> { 34805let Inst{7-5} = 0b101; 34806let Inst{13-13} = 0b1; 34807let Inst{31-21} = 0b00011001000; 34808let hasNewValue = 1; 34809let opNewValue = 0; 34810let isAccumulator = 1; 34811let DecoderNamespace = "EXT_mmvec"; 34812let Constraints = "$Vx32 = $Vx32in"; 34813} 34814def V6_vrmpybus_acc_alt : HInst< 34815(outs HvxVR:$Vx32), 34816(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32), 34817"$Vx32 += vrmpybus($Vu32,$Rt32)", 34818PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 34819let hasNewValue = 1; 34820let opNewValue = 0; 34821let isAccumulator = 1; 34822let isPseudo = 1; 34823let isCodeGenOnly = 1; 34824let DecoderNamespace = "EXT_mmvec"; 34825let Constraints = "$Vx32 = $Vx32in"; 34826} 34827def V6_vrmpybus_alt : HInst< 34828(outs HvxVR:$Vd32), 34829(ins HvxVR:$Vu32, IntRegs:$Rt32), 34830"$Vd32 = vrmpybus($Vu32,$Rt32)", 34831PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 34832let hasNewValue = 1; 34833let opNewValue = 0; 34834let isPseudo = 1; 34835let isCodeGenOnly = 1; 34836let DecoderNamespace = "EXT_mmvec"; 34837} 34838def V6_vrmpybusi : HInst< 34839(outs HvxWR:$Vdd32), 34840(ins HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii), 34841"$Vdd32.w = vrmpy($Vuu32.ub,$Rt32.b,#$Ii)", 34842tc_1ad8a370, TypeCVI_VX_DV>, Enc_2f2f04, Requires<[UseHVXV60]> { 34843let Inst{7-6} = 0b10; 34844let Inst{13-13} = 0b0; 34845let Inst{31-21} = 0b00011001010; 34846let hasNewValue = 1; 34847let opNewValue = 0; 34848let DecoderNamespace = "EXT_mmvec"; 34849} 34850def V6_vrmpybusi_acc : HInst< 34851(outs HvxWR:$Vxx32), 34852(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii), 34853"$Vxx32.w += vrmpy($Vuu32.ub,$Rt32.b,#$Ii)", 34854tc_e675c45a, TypeCVI_VX_DV>, Enc_d483b9, Requires<[UseHVXV60]> { 34855let Inst{7-6} = 0b10; 34856let Inst{13-13} = 0b1; 34857let Inst{31-21} = 0b00011001010; 34858let hasNewValue = 1; 34859let opNewValue = 0; 34860let isAccumulator = 1; 34861let DecoderNamespace = "EXT_mmvec"; 34862let Constraints = "$Vxx32 = $Vxx32in"; 34863} 34864def V6_vrmpybusi_acc_alt : HInst< 34865(outs HvxWR:$Vxx32), 34866(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii), 34867"$Vxx32 += vrmpybus($Vuu32,$Rt32,#$Ii)", 34868PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 34869let hasNewValue = 1; 34870let opNewValue = 0; 34871let isAccumulator = 1; 34872let isPseudo = 1; 34873let isCodeGenOnly = 1; 34874let DecoderNamespace = "EXT_mmvec"; 34875let Constraints = "$Vxx32 = $Vxx32in"; 34876} 34877def V6_vrmpybusi_alt : HInst< 34878(outs HvxWR:$Vdd32), 34879(ins HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii), 34880"$Vdd32 = vrmpybus($Vuu32,$Rt32,#$Ii)", 34881PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 34882let hasNewValue = 1; 34883let opNewValue = 0; 34884let isPseudo = 1; 34885let isCodeGenOnly = 1; 34886let DecoderNamespace = "EXT_mmvec"; 34887} 34888def V6_vrmpybusv : HInst< 34889(outs HvxVR:$Vd32), 34890(ins HvxVR:$Vu32, HvxVR:$Vv32), 34891"$Vd32.w = vrmpy($Vu32.ub,$Vv32.b)", 34892tc_c127de3a, TypeCVI_VX>, Enc_45364e, Requires<[UseHVXV60]> { 34893let Inst{7-5} = 0b010; 34894let Inst{13-13} = 0b0; 34895let Inst{31-21} = 0b00011100000; 34896let hasNewValue = 1; 34897let opNewValue = 0; 34898let DecoderNamespace = "EXT_mmvec"; 34899} 34900def V6_vrmpybusv_acc : HInst< 34901(outs HvxVR:$Vx32), 34902(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32), 34903"$Vx32.w += vrmpy($Vu32.ub,$Vv32.b)", 34904tc_08a4f1b6, TypeCVI_VX_DV>, Enc_a7341a, Requires<[UseHVXV60]> { 34905let Inst{7-5} = 0b010; 34906let Inst{13-13} = 0b1; 34907let Inst{31-21} = 0b00011100000; 34908let hasNewValue = 1; 34909let opNewValue = 0; 34910let isAccumulator = 1; 34911let DecoderNamespace = "EXT_mmvec"; 34912let Constraints = "$Vx32 = $Vx32in"; 34913} 34914def V6_vrmpybusv_acc_alt : HInst< 34915(outs HvxVR:$Vx32), 34916(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32), 34917"$Vx32 += vrmpybus($Vu32,$Vv32)", 34918PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 34919let hasNewValue = 1; 34920let opNewValue = 0; 34921let isAccumulator = 1; 34922let isPseudo = 1; 34923let isCodeGenOnly = 1; 34924let DecoderNamespace = "EXT_mmvec"; 34925let Constraints = "$Vx32 = $Vx32in"; 34926} 34927def V6_vrmpybusv_alt : HInst< 34928(outs HvxVR:$Vd32), 34929(ins HvxVR:$Vu32, HvxVR:$Vv32), 34930"$Vd32 = vrmpybus($Vu32,$Vv32)", 34931PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 34932let hasNewValue = 1; 34933let opNewValue = 0; 34934let isPseudo = 1; 34935let isCodeGenOnly = 1; 34936let DecoderNamespace = "EXT_mmvec"; 34937} 34938def V6_vrmpybv : HInst< 34939(outs HvxVR:$Vd32), 34940(ins HvxVR:$Vu32, HvxVR:$Vv32), 34941"$Vd32.w = vrmpy($Vu32.b,$Vv32.b)", 34942tc_c127de3a, TypeCVI_VX>, Enc_45364e, Requires<[UseHVXV60]> { 34943let Inst{7-5} = 0b001; 34944let Inst{13-13} = 0b0; 34945let Inst{31-21} = 0b00011100000; 34946let hasNewValue = 1; 34947let opNewValue = 0; 34948let DecoderNamespace = "EXT_mmvec"; 34949} 34950def V6_vrmpybv_acc : HInst< 34951(outs HvxVR:$Vx32), 34952(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32), 34953"$Vx32.w += vrmpy($Vu32.b,$Vv32.b)", 34954tc_08a4f1b6, TypeCVI_VX_DV>, Enc_a7341a, Requires<[UseHVXV60]> { 34955let Inst{7-5} = 0b001; 34956let Inst{13-13} = 0b1; 34957let Inst{31-21} = 0b00011100000; 34958let hasNewValue = 1; 34959let opNewValue = 0; 34960let isAccumulator = 1; 34961let DecoderNamespace = "EXT_mmvec"; 34962let Constraints = "$Vx32 = $Vx32in"; 34963} 34964def V6_vrmpybv_acc_alt : HInst< 34965(outs HvxVR:$Vx32), 34966(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32), 34967"$Vx32 += vrmpyb($Vu32,$Vv32)", 34968PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 34969let hasNewValue = 1; 34970let opNewValue = 0; 34971let isAccumulator = 1; 34972let isPseudo = 1; 34973let isCodeGenOnly = 1; 34974let DecoderNamespace = "EXT_mmvec"; 34975let Constraints = "$Vx32 = $Vx32in"; 34976} 34977def V6_vrmpybv_alt : HInst< 34978(outs HvxVR:$Vd32), 34979(ins HvxVR:$Vu32, HvxVR:$Vv32), 34980"$Vd32 = vrmpyb($Vu32,$Vv32)", 34981PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 34982let hasNewValue = 1; 34983let opNewValue = 0; 34984let isPseudo = 1; 34985let isCodeGenOnly = 1; 34986let DecoderNamespace = "EXT_mmvec"; 34987} 34988def V6_vrmpyub : HInst< 34989(outs HvxVR:$Vd32), 34990(ins HvxVR:$Vu32, IntRegs:$Rt32), 34991"$Vd32.uw = vrmpy($Vu32.ub,$Rt32.ub)", 34992tc_649072c2, TypeCVI_VX>, Enc_b087ac, Requires<[UseHVXV60]> { 34993let Inst{7-5} = 0b011; 34994let Inst{13-13} = 0b0; 34995let Inst{31-21} = 0b00011001000; 34996let hasNewValue = 1; 34997let opNewValue = 0; 34998let DecoderNamespace = "EXT_mmvec"; 34999} 35000def V6_vrmpyub_acc : HInst< 35001(outs HvxVR:$Vx32), 35002(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32), 35003"$Vx32.uw += vrmpy($Vu32.ub,$Rt32.ub)", 35004tc_b091f1c6, TypeCVI_VX>, Enc_5138b3, Requires<[UseHVXV60]> { 35005let Inst{7-5} = 0b100; 35006let Inst{13-13} = 0b1; 35007let Inst{31-21} = 0b00011001000; 35008let hasNewValue = 1; 35009let opNewValue = 0; 35010let isAccumulator = 1; 35011let DecoderNamespace = "EXT_mmvec"; 35012let Constraints = "$Vx32 = $Vx32in"; 35013} 35014def V6_vrmpyub_acc_alt : HInst< 35015(outs HvxVR:$Vx32), 35016(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32), 35017"$Vx32 += vrmpyub($Vu32,$Rt32)", 35018PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 35019let hasNewValue = 1; 35020let opNewValue = 0; 35021let isAccumulator = 1; 35022let isPseudo = 1; 35023let isCodeGenOnly = 1; 35024let DecoderNamespace = "EXT_mmvec"; 35025let Constraints = "$Vx32 = $Vx32in"; 35026} 35027def V6_vrmpyub_alt : HInst< 35028(outs HvxVR:$Vd32), 35029(ins HvxVR:$Vu32, IntRegs:$Rt32), 35030"$Vd32 = vrmpyub($Vu32,$Rt32)", 35031PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 35032let hasNewValue = 1; 35033let opNewValue = 0; 35034let isPseudo = 1; 35035let isCodeGenOnly = 1; 35036let DecoderNamespace = "EXT_mmvec"; 35037} 35038def V6_vrmpyub_rtt : HInst< 35039(outs HvxWR:$Vdd32), 35040(ins HvxVR:$Vu32, DoubleRegs:$Rtt32), 35041"$Vdd32.uw = vrmpy($Vu32.ub,$Rtt32.ub)", 35042tc_cd94bfe0, TypeCVI_VS_VX>, Enc_cb785b, Requires<[UseHVXV65]> { 35043let Inst{7-5} = 0b100; 35044let Inst{13-13} = 0b0; 35045let Inst{31-21} = 0b00011001110; 35046let hasNewValue = 1; 35047let opNewValue = 0; 35048let DecoderNamespace = "EXT_mmvec"; 35049} 35050def V6_vrmpyub_rtt_acc : HInst< 35051(outs HvxWR:$Vxx32), 35052(ins HvxWR:$Vxx32in, HvxVR:$Vu32, DoubleRegs:$Rtt32), 35053"$Vxx32.uw += vrmpy($Vu32.ub,$Rtt32.ub)", 35054tc_15fdf750, TypeCVI_VS_VX>, Enc_ad9bef, Requires<[UseHVXV65]> { 35055let Inst{7-5} = 0b111; 35056let Inst{13-13} = 0b1; 35057let Inst{31-21} = 0b00011001101; 35058let hasNewValue = 1; 35059let opNewValue = 0; 35060let isAccumulator = 1; 35061let DecoderNamespace = "EXT_mmvec"; 35062let Constraints = "$Vxx32 = $Vxx32in"; 35063} 35064def V6_vrmpyub_rtt_acc_alt : HInst< 35065(outs HvxWR:$Vxx32), 35066(ins HvxWR:$Vxx32in, HvxVR:$Vu32, DoubleRegs:$Rtt32), 35067"$Vxx32.uw += vrmpy($Vu32.ub,$Rtt32.ub)", 35068PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> { 35069let hasNewValue = 1; 35070let opNewValue = 0; 35071let isAccumulator = 1; 35072let isPseudo = 1; 35073let isCodeGenOnly = 1; 35074let DecoderNamespace = "EXT_mmvec"; 35075let Constraints = "$Vxx32 = $Vxx32in"; 35076} 35077def V6_vrmpyub_rtt_alt : HInst< 35078(outs HvxWR:$Vdd32), 35079(ins HvxVR:$Vu32, DoubleRegs:$Rtt32), 35080"$Vdd32.uw = vrmpy($Vu32.ub,$Rtt32.ub)", 35081PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> { 35082let hasNewValue = 1; 35083let opNewValue = 0; 35084let isPseudo = 1; 35085let isCodeGenOnly = 1; 35086let DecoderNamespace = "EXT_mmvec"; 35087} 35088def V6_vrmpyubi : HInst< 35089(outs HvxWR:$Vdd32), 35090(ins HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii), 35091"$Vdd32.uw = vrmpy($Vuu32.ub,$Rt32.ub,#$Ii)", 35092tc_1ad8a370, TypeCVI_VX_DV>, Enc_2f2f04, Requires<[UseHVXV60]> { 35093let Inst{7-6} = 0b11; 35094let Inst{13-13} = 0b0; 35095let Inst{31-21} = 0b00011001101; 35096let hasNewValue = 1; 35097let opNewValue = 0; 35098let DecoderNamespace = "EXT_mmvec"; 35099} 35100def V6_vrmpyubi_acc : HInst< 35101(outs HvxWR:$Vxx32), 35102(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii), 35103"$Vxx32.uw += vrmpy($Vuu32.ub,$Rt32.ub,#$Ii)", 35104tc_e675c45a, TypeCVI_VX_DV>, Enc_d483b9, Requires<[UseHVXV60]> { 35105let Inst{7-6} = 0b11; 35106let Inst{13-13} = 0b1; 35107let Inst{31-21} = 0b00011001011; 35108let hasNewValue = 1; 35109let opNewValue = 0; 35110let isAccumulator = 1; 35111let DecoderNamespace = "EXT_mmvec"; 35112let Constraints = "$Vxx32 = $Vxx32in"; 35113} 35114def V6_vrmpyubi_acc_alt : HInst< 35115(outs HvxWR:$Vxx32), 35116(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii), 35117"$Vxx32 += vrmpyub($Vuu32,$Rt32,#$Ii)", 35118PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 35119let hasNewValue = 1; 35120let opNewValue = 0; 35121let isAccumulator = 1; 35122let isPseudo = 1; 35123let isCodeGenOnly = 1; 35124let DecoderNamespace = "EXT_mmvec"; 35125let Constraints = "$Vxx32 = $Vxx32in"; 35126} 35127def V6_vrmpyubi_alt : HInst< 35128(outs HvxWR:$Vdd32), 35129(ins HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii), 35130"$Vdd32 = vrmpyub($Vuu32,$Rt32,#$Ii)", 35131PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 35132let hasNewValue = 1; 35133let opNewValue = 0; 35134let isPseudo = 1; 35135let isCodeGenOnly = 1; 35136let DecoderNamespace = "EXT_mmvec"; 35137} 35138def V6_vrmpyubv : HInst< 35139(outs HvxVR:$Vd32), 35140(ins HvxVR:$Vu32, HvxVR:$Vv32), 35141"$Vd32.uw = vrmpy($Vu32.ub,$Vv32.ub)", 35142tc_c127de3a, TypeCVI_VX>, Enc_45364e, Requires<[UseHVXV60]> { 35143let Inst{7-5} = 0b000; 35144let Inst{13-13} = 0b0; 35145let Inst{31-21} = 0b00011100000; 35146let hasNewValue = 1; 35147let opNewValue = 0; 35148let DecoderNamespace = "EXT_mmvec"; 35149} 35150def V6_vrmpyubv_acc : HInst< 35151(outs HvxVR:$Vx32), 35152(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32), 35153"$Vx32.uw += vrmpy($Vu32.ub,$Vv32.ub)", 35154tc_08a4f1b6, TypeCVI_VX_DV>, Enc_a7341a, Requires<[UseHVXV60]> { 35155let Inst{7-5} = 0b000; 35156let Inst{13-13} = 0b1; 35157let Inst{31-21} = 0b00011100000; 35158let hasNewValue = 1; 35159let opNewValue = 0; 35160let isAccumulator = 1; 35161let DecoderNamespace = "EXT_mmvec"; 35162let Constraints = "$Vx32 = $Vx32in"; 35163} 35164def V6_vrmpyubv_acc_alt : HInst< 35165(outs HvxVR:$Vx32), 35166(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32), 35167"$Vx32 += vrmpyub($Vu32,$Vv32)", 35168PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 35169let hasNewValue = 1; 35170let opNewValue = 0; 35171let isAccumulator = 1; 35172let isPseudo = 1; 35173let isCodeGenOnly = 1; 35174let DecoderNamespace = "EXT_mmvec"; 35175let Constraints = "$Vx32 = $Vx32in"; 35176} 35177def V6_vrmpyubv_alt : HInst< 35178(outs HvxVR:$Vd32), 35179(ins HvxVR:$Vu32, HvxVR:$Vv32), 35180"$Vd32 = vrmpyub($Vu32,$Vv32)", 35181PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 35182let hasNewValue = 1; 35183let opNewValue = 0; 35184let isPseudo = 1; 35185let isCodeGenOnly = 1; 35186let DecoderNamespace = "EXT_mmvec"; 35187} 35188def V6_vrmpyzbb_rt : HInst< 35189(outs HvxVQR:$Vdddd32), 35190(ins HvxVR:$Vu32, IntRegsLow8:$Rt8), 35191"$Vdddd32.w = vrmpyz($Vu32.b,$Rt8.b)", 35192tc_61bf7c03, TypeCVI_4SLOT_MPY>, Enc_1bd127, Requires<[UseHVXV66,UseZReg]> { 35193let Inst{7-5} = 0b000; 35194let Inst{13-13} = 0b0; 35195let Inst{31-19} = 0b0001100111101; 35196let hasNewValue = 1; 35197let opNewValue = 0; 35198let DecoderNamespace = "EXT_mmvec"; 35199} 35200def V6_vrmpyzbb_rt_acc : HInst< 35201(outs HvxVQR:$Vyyyy32), 35202(ins HvxVQR:$Vyyyy32in, HvxVR:$Vu32, IntRegsLow8:$Rt8), 35203"$Vyyyy32.w += vrmpyz($Vu32.b,$Rt8.b)", 35204tc_933f2b39, TypeCVI_4SLOT_MPY>, Enc_d7bc34, Requires<[UseHVXV66,UseZReg]> { 35205let Inst{7-5} = 0b010; 35206let Inst{13-13} = 0b1; 35207let Inst{31-19} = 0b0001100111000; 35208let hasNewValue = 1; 35209let opNewValue = 0; 35210let isAccumulator = 1; 35211let DecoderNamespace = "EXT_mmvec"; 35212let Constraints = "$Vyyyy32 = $Vyyyy32in"; 35213} 35214def V6_vrmpyzbb_rx : HInst< 35215(outs HvxVQR:$Vdddd32, IntRegsLow8:$Rx8), 35216(ins HvxVR:$Vu32, IntRegs:$Rx8in), 35217"$Vdddd32.w = vrmpyz($Vu32.b,$Rx8.b++)", 35218tc_26a377fe, TypeCVI_4SLOT_MPY>, Enc_3b7631, Requires<[UseHVXV66,UseZReg]> { 35219let Inst{7-5} = 0b000; 35220let Inst{13-13} = 0b0; 35221let Inst{31-19} = 0b0001100111100; 35222let hasNewValue = 1; 35223let opNewValue = 0; 35224let DecoderNamespace = "EXT_mmvec"; 35225let Constraints = "$Rx8 = $Rx8in"; 35226} 35227def V6_vrmpyzbb_rx_acc : HInst< 35228(outs HvxVQR:$Vyyyy32, IntRegsLow8:$Rx8), 35229(ins HvxVQR:$Vyyyy32in, HvxVR:$Vu32, IntRegs:$Rx8in), 35230"$Vyyyy32.w += vrmpyz($Vu32.b,$Rx8.b++)", 35231tc_2d4051cd, TypeCVI_4SLOT_MPY>, Enc_bddee3, Requires<[UseHVXV66,UseZReg]> { 35232let Inst{7-5} = 0b010; 35233let Inst{13-13} = 0b1; 35234let Inst{31-19} = 0b0001100111001; 35235let hasNewValue = 1; 35236let opNewValue = 0; 35237let isAccumulator = 1; 35238let DecoderNamespace = "EXT_mmvec"; 35239let Constraints = "$Vyyyy32 = $Vyyyy32in, $Rx8 = $Rx8in"; 35240} 35241def V6_vrmpyzbub_rt : HInst< 35242(outs HvxVQR:$Vdddd32), 35243(ins HvxVR:$Vu32, IntRegsLow8:$Rt8), 35244"$Vdddd32.w = vrmpyz($Vu32.b,$Rt8.ub)", 35245tc_61bf7c03, TypeCVI_4SLOT_MPY>, Enc_1bd127, Requires<[UseHVXV66,UseZReg]> { 35246let Inst{7-5} = 0b010; 35247let Inst{13-13} = 0b0; 35248let Inst{31-19} = 0b0001100111111; 35249let hasNewValue = 1; 35250let opNewValue = 0; 35251let DecoderNamespace = "EXT_mmvec"; 35252} 35253def V6_vrmpyzbub_rt_acc : HInst< 35254(outs HvxVQR:$Vyyyy32), 35255(ins HvxVQR:$Vyyyy32in, HvxVR:$Vu32, IntRegsLow8:$Rt8), 35256"$Vyyyy32.w += vrmpyz($Vu32.b,$Rt8.ub)", 35257tc_933f2b39, TypeCVI_4SLOT_MPY>, Enc_d7bc34, Requires<[UseHVXV66,UseZReg]> { 35258let Inst{7-5} = 0b001; 35259let Inst{13-13} = 0b1; 35260let Inst{31-19} = 0b0001100111010; 35261let hasNewValue = 1; 35262let opNewValue = 0; 35263let isAccumulator = 1; 35264let DecoderNamespace = "EXT_mmvec"; 35265let Constraints = "$Vyyyy32 = $Vyyyy32in"; 35266} 35267def V6_vrmpyzbub_rx : HInst< 35268(outs HvxVQR:$Vdddd32, IntRegsLow8:$Rx8), 35269(ins HvxVR:$Vu32, IntRegs:$Rx8in), 35270"$Vdddd32.w = vrmpyz($Vu32.b,$Rx8.ub++)", 35271tc_26a377fe, TypeCVI_4SLOT_MPY>, Enc_3b7631, Requires<[UseHVXV66,UseZReg]> { 35272let Inst{7-5} = 0b010; 35273let Inst{13-13} = 0b0; 35274let Inst{31-19} = 0b0001100111110; 35275let hasNewValue = 1; 35276let opNewValue = 0; 35277let DecoderNamespace = "EXT_mmvec"; 35278let Constraints = "$Rx8 = $Rx8in"; 35279} 35280def V6_vrmpyzbub_rx_acc : HInst< 35281(outs HvxVQR:$Vyyyy32, IntRegsLow8:$Rx8), 35282(ins HvxVQR:$Vyyyy32in, HvxVR:$Vu32, IntRegs:$Rx8in), 35283"$Vyyyy32.w += vrmpyz($Vu32.b,$Rx8.ub++)", 35284tc_2d4051cd, TypeCVI_4SLOT_MPY>, Enc_bddee3, Requires<[UseHVXV66,UseZReg]> { 35285let Inst{7-5} = 0b001; 35286let Inst{13-13} = 0b1; 35287let Inst{31-19} = 0b0001100111011; 35288let hasNewValue = 1; 35289let opNewValue = 0; 35290let isAccumulator = 1; 35291let DecoderNamespace = "EXT_mmvec"; 35292let Constraints = "$Vyyyy32 = $Vyyyy32in, $Rx8 = $Rx8in"; 35293} 35294def V6_vrmpyzcb_rt : HInst< 35295(outs HvxVQR:$Vdddd32), 35296(ins HvxVR:$Vu32, IntRegsLow8:$Rt8), 35297"$Vdddd32.w = vr16mpyz($Vu32.c,$Rt8.b)", 35298tc_61bf7c03, TypeCVI_4SLOT_MPY>, Enc_1bd127, Requires<[UseHVXV66,UseZReg]> { 35299let Inst{7-5} = 0b001; 35300let Inst{13-13} = 0b0; 35301let Inst{31-19} = 0b0001100111101; 35302let hasNewValue = 1; 35303let opNewValue = 0; 35304let DecoderNamespace = "EXT_mmvec"; 35305} 35306def V6_vrmpyzcb_rt_acc : HInst< 35307(outs HvxVQR:$Vyyyy32), 35308(ins HvxVQR:$Vyyyy32in, HvxVR:$Vu32, IntRegsLow8:$Rt8), 35309"$Vyyyy32.w += vr16mpyz($Vu32.c,$Rt8.b)", 35310tc_933f2b39, TypeCVI_4SLOT_MPY>, Enc_d7bc34, Requires<[UseHVXV66,UseZReg]> { 35311let Inst{7-5} = 0b011; 35312let Inst{13-13} = 0b1; 35313let Inst{31-19} = 0b0001100111000; 35314let hasNewValue = 1; 35315let opNewValue = 0; 35316let isAccumulator = 1; 35317let DecoderNamespace = "EXT_mmvec"; 35318let Constraints = "$Vyyyy32 = $Vyyyy32in"; 35319} 35320def V6_vrmpyzcb_rx : HInst< 35321(outs HvxVQR:$Vdddd32, IntRegsLow8:$Rx8), 35322(ins HvxVR:$Vu32, IntRegs:$Rx8in), 35323"$Vdddd32.w = vr16mpyz($Vu32.c,$Rx8.b++)", 35324tc_26a377fe, TypeCVI_4SLOT_MPY>, Enc_3b7631, Requires<[UseHVXV66,UseZReg]> { 35325let Inst{7-5} = 0b001; 35326let Inst{13-13} = 0b0; 35327let Inst{31-19} = 0b0001100111100; 35328let hasNewValue = 1; 35329let opNewValue = 0; 35330let DecoderNamespace = "EXT_mmvec"; 35331let Constraints = "$Rx8 = $Rx8in"; 35332} 35333def V6_vrmpyzcb_rx_acc : HInst< 35334(outs HvxVQR:$Vyyyy32, IntRegsLow8:$Rx8), 35335(ins HvxVQR:$Vyyyy32in, HvxVR:$Vu32, IntRegs:$Rx8in), 35336"$Vyyyy32.w += vr16mpyz($Vu32.c,$Rx8.b++)", 35337tc_2d4051cd, TypeCVI_4SLOT_MPY>, Enc_bddee3, Requires<[UseHVXV66,UseZReg]> { 35338let Inst{7-5} = 0b011; 35339let Inst{13-13} = 0b1; 35340let Inst{31-19} = 0b0001100111001; 35341let hasNewValue = 1; 35342let opNewValue = 0; 35343let isAccumulator = 1; 35344let DecoderNamespace = "EXT_mmvec"; 35345let Constraints = "$Vyyyy32 = $Vyyyy32in, $Rx8 = $Rx8in"; 35346} 35347def V6_vrmpyzcbs_rt : HInst< 35348(outs HvxVQR:$Vdddd32), 35349(ins HvxVR:$Vu32, IntRegsLow8:$Rt8), 35350"$Vdddd32.w = vr16mpyzs($Vu32.c,$Rt8.b)", 35351tc_61bf7c03, TypeCVI_4SLOT_MPY>, Enc_1bd127, Requires<[UseHVXV66,UseZReg]> { 35352let Inst{7-5} = 0b010; 35353let Inst{13-13} = 0b0; 35354let Inst{31-19} = 0b0001100111101; 35355let hasNewValue = 1; 35356let opNewValue = 0; 35357let DecoderNamespace = "EXT_mmvec"; 35358} 35359def V6_vrmpyzcbs_rt_acc : HInst< 35360(outs HvxVQR:$Vyyyy32), 35361(ins HvxVQR:$Vyyyy32in, HvxVR:$Vu32, IntRegsLow8:$Rt8), 35362"$Vyyyy32.w += vr16mpyzs($Vu32.c,$Rt8.b)", 35363tc_933f2b39, TypeCVI_4SLOT_MPY>, Enc_d7bc34, Requires<[UseHVXV66,UseZReg]> { 35364let Inst{7-5} = 0b001; 35365let Inst{13-13} = 0b1; 35366let Inst{31-19} = 0b0001100111000; 35367let hasNewValue = 1; 35368let opNewValue = 0; 35369let isAccumulator = 1; 35370let DecoderNamespace = "EXT_mmvec"; 35371let Constraints = "$Vyyyy32 = $Vyyyy32in"; 35372} 35373def V6_vrmpyzcbs_rx : HInst< 35374(outs HvxVQR:$Vdddd32, IntRegsLow8:$Rx8), 35375(ins HvxVR:$Vu32, IntRegs:$Rx8in), 35376"$Vdddd32.w = vr16mpyzs($Vu32.c,$Rx8.b++)", 35377tc_26a377fe, TypeCVI_4SLOT_MPY>, Enc_3b7631, Requires<[UseHVXV66,UseZReg]> { 35378let Inst{7-5} = 0b010; 35379let Inst{13-13} = 0b0; 35380let Inst{31-19} = 0b0001100111100; 35381let hasNewValue = 1; 35382let opNewValue = 0; 35383let DecoderNamespace = "EXT_mmvec"; 35384let Constraints = "$Rx8 = $Rx8in"; 35385} 35386def V6_vrmpyzcbs_rx_acc : HInst< 35387(outs HvxVQR:$Vyyyy32, IntRegsLow8:$Rx8), 35388(ins HvxVQR:$Vyyyy32in, HvxVR:$Vu32, IntRegs:$Rx8in), 35389"$Vyyyy32.w += vr16mpyzs($Vu32.c,$Rx8.b++)", 35390tc_2d4051cd, TypeCVI_4SLOT_MPY>, Enc_bddee3, Requires<[UseHVXV66,UseZReg]> { 35391let Inst{7-5} = 0b001; 35392let Inst{13-13} = 0b1; 35393let Inst{31-19} = 0b0001100111001; 35394let hasNewValue = 1; 35395let opNewValue = 0; 35396let isAccumulator = 1; 35397let DecoderNamespace = "EXT_mmvec"; 35398let Constraints = "$Vyyyy32 = $Vyyyy32in, $Rx8 = $Rx8in"; 35399} 35400def V6_vrmpyznb_rt : HInst< 35401(outs HvxVQR:$Vdddd32), 35402(ins HvxVR:$Vu32, IntRegsLow8:$Rt8), 35403"$Vdddd32.w = vr8mpyz($Vu32.n,$Rt8.b)", 35404tc_61bf7c03, TypeCVI_4SLOT_MPY>, Enc_1bd127, Requires<[UseHVXV66,UseZReg]> { 35405let Inst{7-5} = 0b000; 35406let Inst{13-13} = 0b0; 35407let Inst{31-19} = 0b0001100111111; 35408let hasNewValue = 1; 35409let opNewValue = 0; 35410let DecoderNamespace = "EXT_mmvec"; 35411} 35412def V6_vrmpyznb_rt_acc : HInst< 35413(outs HvxVQR:$Vyyyy32), 35414(ins HvxVQR:$Vyyyy32in, HvxVR:$Vu32, IntRegsLow8:$Rt8), 35415"$Vyyyy32.w += vr8mpyz($Vu32.n,$Rt8.b)", 35416tc_933f2b39, TypeCVI_4SLOT_MPY>, Enc_d7bc34, Requires<[UseHVXV66,UseZReg]> { 35417let Inst{7-5} = 0b010; 35418let Inst{13-13} = 0b1; 35419let Inst{31-19} = 0b0001100111010; 35420let hasNewValue = 1; 35421let opNewValue = 0; 35422let isAccumulator = 1; 35423let DecoderNamespace = "EXT_mmvec"; 35424let Constraints = "$Vyyyy32 = $Vyyyy32in"; 35425} 35426def V6_vrmpyznb_rx : HInst< 35427(outs HvxVQR:$Vdddd32, IntRegsLow8:$Rx8), 35428(ins HvxVR:$Vu32, IntRegs:$Rx8in), 35429"$Vdddd32.w = vr8mpyz($Vu32.n,$Rx8.b++)", 35430tc_26a377fe, TypeCVI_4SLOT_MPY>, Enc_3b7631, Requires<[UseHVXV66,UseZReg]> { 35431let Inst{7-5} = 0b000; 35432let Inst{13-13} = 0b0; 35433let Inst{31-19} = 0b0001100111110; 35434let hasNewValue = 1; 35435let opNewValue = 0; 35436let DecoderNamespace = "EXT_mmvec"; 35437let Constraints = "$Rx8 = $Rx8in"; 35438} 35439def V6_vrmpyznb_rx_acc : HInst< 35440(outs HvxVQR:$Vyyyy32, IntRegsLow8:$Rx8), 35441(ins HvxVQR:$Vyyyy32in, HvxVR:$Vu32, IntRegs:$Rx8in), 35442"$Vyyyy32.w += vr8mpyz($Vu32.n,$Rx8.b++)", 35443tc_2d4051cd, TypeCVI_4SLOT_MPY>, Enc_bddee3, Requires<[UseHVXV66,UseZReg]> { 35444let Inst{7-5} = 0b010; 35445let Inst{13-13} = 0b1; 35446let Inst{31-19} = 0b0001100111011; 35447let hasNewValue = 1; 35448let opNewValue = 0; 35449let isAccumulator = 1; 35450let DecoderNamespace = "EXT_mmvec"; 35451let Constraints = "$Vyyyy32 = $Vyyyy32in, $Rx8 = $Rx8in"; 35452} 35453def V6_vror : HInst< 35454(outs HvxVR:$Vd32), 35455(ins HvxVR:$Vu32, IntRegs:$Rt32), 35456"$Vd32 = vror($Vu32,$Rt32)", 35457tc_6e7fa133, TypeCVI_VP>, Enc_b087ac, Requires<[UseHVXV60]> { 35458let Inst{7-5} = 0b001; 35459let Inst{13-13} = 0b0; 35460let Inst{31-21} = 0b00011001011; 35461let hasNewValue = 1; 35462let opNewValue = 0; 35463let DecoderNamespace = "EXT_mmvec"; 35464} 35465def V6_vrotr : HInst< 35466(outs HvxVR:$Vd32), 35467(ins HvxVR:$Vu32, HvxVR:$Vv32), 35468"$Vd32.uw = vrotr($Vu32.uw,$Vv32.uw)", 35469tc_05ca8cfd, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV66]> { 35470let Inst{7-5} = 0b111; 35471let Inst{13-13} = 0b1; 35472let Inst{31-21} = 0b00011010100; 35473let hasNewValue = 1; 35474let opNewValue = 0; 35475let DecoderNamespace = "EXT_mmvec"; 35476} 35477def V6_vrotr_alt : HInst< 35478(outs HvxVR:$Vd32), 35479(ins HvxVR:$Vu32, HvxVR:$Vv32), 35480"$Vd32 = vrotr($Vu32,$Vv32)", 35481PSEUDO, TypeMAPPING>, Requires<[UseHVXV66]> { 35482let hasNewValue = 1; 35483let opNewValue = 0; 35484let isPseudo = 1; 35485let isCodeGenOnly = 1; 35486let DecoderNamespace = "EXT_mmvec"; 35487} 35488def V6_vroundhb : HInst< 35489(outs HvxVR:$Vd32), 35490(ins HvxVR:$Vu32, HvxVR:$Vv32), 35491"$Vd32.b = vround($Vu32.h,$Vv32.h):sat", 35492tc_05ca8cfd, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV60]> { 35493let Inst{7-5} = 0b110; 35494let Inst{13-13} = 0b0; 35495let Inst{31-21} = 0b00011111011; 35496let hasNewValue = 1; 35497let opNewValue = 0; 35498let DecoderNamespace = "EXT_mmvec"; 35499} 35500def V6_vroundhb_alt : HInst< 35501(outs HvxVR:$Vd32), 35502(ins HvxVR:$Vu32, HvxVR:$Vv32), 35503"$Vd32 = vroundhb($Vu32,$Vv32):sat", 35504PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 35505let hasNewValue = 1; 35506let opNewValue = 0; 35507let isPseudo = 1; 35508let isCodeGenOnly = 1; 35509let DecoderNamespace = "EXT_mmvec"; 35510} 35511def V6_vroundhub : HInst< 35512(outs HvxVR:$Vd32), 35513(ins HvxVR:$Vu32, HvxVR:$Vv32), 35514"$Vd32.ub = vround($Vu32.h,$Vv32.h):sat", 35515tc_05ca8cfd, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV60]> { 35516let Inst{7-5} = 0b111; 35517let Inst{13-13} = 0b0; 35518let Inst{31-21} = 0b00011111011; 35519let hasNewValue = 1; 35520let opNewValue = 0; 35521let DecoderNamespace = "EXT_mmvec"; 35522} 35523def V6_vroundhub_alt : HInst< 35524(outs HvxVR:$Vd32), 35525(ins HvxVR:$Vu32, HvxVR:$Vv32), 35526"$Vd32 = vroundhub($Vu32,$Vv32):sat", 35527PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 35528let hasNewValue = 1; 35529let opNewValue = 0; 35530let isPseudo = 1; 35531let isCodeGenOnly = 1; 35532let DecoderNamespace = "EXT_mmvec"; 35533} 35534def V6_vrounduhub : HInst< 35535(outs HvxVR:$Vd32), 35536(ins HvxVR:$Vu32, HvxVR:$Vv32), 35537"$Vd32.ub = vround($Vu32.uh,$Vv32.uh):sat", 35538tc_05ca8cfd, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV62]> { 35539let Inst{7-5} = 0b011; 35540let Inst{13-13} = 0b0; 35541let Inst{31-21} = 0b00011111111; 35542let hasNewValue = 1; 35543let opNewValue = 0; 35544let DecoderNamespace = "EXT_mmvec"; 35545} 35546def V6_vrounduhub_alt : HInst< 35547(outs HvxVR:$Vd32), 35548(ins HvxVR:$Vu32, HvxVR:$Vv32), 35549"$Vd32 = vrounduhub($Vu32,$Vv32):sat", 35550PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> { 35551let hasNewValue = 1; 35552let opNewValue = 0; 35553let isPseudo = 1; 35554let isCodeGenOnly = 1; 35555let DecoderNamespace = "EXT_mmvec"; 35556} 35557def V6_vrounduwuh : HInst< 35558(outs HvxVR:$Vd32), 35559(ins HvxVR:$Vu32, HvxVR:$Vv32), 35560"$Vd32.uh = vround($Vu32.uw,$Vv32.uw):sat", 35561tc_05ca8cfd, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV62]> { 35562let Inst{7-5} = 0b100; 35563let Inst{13-13} = 0b0; 35564let Inst{31-21} = 0b00011111111; 35565let hasNewValue = 1; 35566let opNewValue = 0; 35567let DecoderNamespace = "EXT_mmvec"; 35568} 35569def V6_vrounduwuh_alt : HInst< 35570(outs HvxVR:$Vd32), 35571(ins HvxVR:$Vu32, HvxVR:$Vv32), 35572"$Vd32 = vrounduwuh($Vu32,$Vv32):sat", 35573PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> { 35574let hasNewValue = 1; 35575let opNewValue = 0; 35576let isPseudo = 1; 35577let isCodeGenOnly = 1; 35578let DecoderNamespace = "EXT_mmvec"; 35579} 35580def V6_vroundwh : HInst< 35581(outs HvxVR:$Vd32), 35582(ins HvxVR:$Vu32, HvxVR:$Vv32), 35583"$Vd32.h = vround($Vu32.w,$Vv32.w):sat", 35584tc_05ca8cfd, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV60]> { 35585let Inst{7-5} = 0b100; 35586let Inst{13-13} = 0b0; 35587let Inst{31-21} = 0b00011111011; 35588let hasNewValue = 1; 35589let opNewValue = 0; 35590let DecoderNamespace = "EXT_mmvec"; 35591} 35592def V6_vroundwh_alt : HInst< 35593(outs HvxVR:$Vd32), 35594(ins HvxVR:$Vu32, HvxVR:$Vv32), 35595"$Vd32 = vroundwh($Vu32,$Vv32):sat", 35596PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 35597let hasNewValue = 1; 35598let opNewValue = 0; 35599let isPseudo = 1; 35600let isCodeGenOnly = 1; 35601let DecoderNamespace = "EXT_mmvec"; 35602} 35603def V6_vroundwuh : HInst< 35604(outs HvxVR:$Vd32), 35605(ins HvxVR:$Vu32, HvxVR:$Vv32), 35606"$Vd32.uh = vround($Vu32.w,$Vv32.w):sat", 35607tc_05ca8cfd, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV60]> { 35608let Inst{7-5} = 0b101; 35609let Inst{13-13} = 0b0; 35610let Inst{31-21} = 0b00011111011; 35611let hasNewValue = 1; 35612let opNewValue = 0; 35613let DecoderNamespace = "EXT_mmvec"; 35614} 35615def V6_vroundwuh_alt : HInst< 35616(outs HvxVR:$Vd32), 35617(ins HvxVR:$Vu32, HvxVR:$Vv32), 35618"$Vd32 = vroundwuh($Vu32,$Vv32):sat", 35619PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 35620let hasNewValue = 1; 35621let opNewValue = 0; 35622let isPseudo = 1; 35623let isCodeGenOnly = 1; 35624let DecoderNamespace = "EXT_mmvec"; 35625} 35626def V6_vrsadubi : HInst< 35627(outs HvxWR:$Vdd32), 35628(ins HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii), 35629"$Vdd32.uw = vrsad($Vuu32.ub,$Rt32.ub,#$Ii)", 35630tc_1ad8a370, TypeCVI_VX_DV>, Enc_2f2f04, Requires<[UseHVXV60]> { 35631let Inst{7-6} = 0b11; 35632let Inst{13-13} = 0b0; 35633let Inst{31-21} = 0b00011001010; 35634let hasNewValue = 1; 35635let opNewValue = 0; 35636let DecoderNamespace = "EXT_mmvec"; 35637} 35638def V6_vrsadubi_acc : HInst< 35639(outs HvxWR:$Vxx32), 35640(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii), 35641"$Vxx32.uw += vrsad($Vuu32.ub,$Rt32.ub,#$Ii)", 35642tc_e675c45a, TypeCVI_VX_DV>, Enc_d483b9, Requires<[UseHVXV60]> { 35643let Inst{7-6} = 0b11; 35644let Inst{13-13} = 0b1; 35645let Inst{31-21} = 0b00011001010; 35646let hasNewValue = 1; 35647let opNewValue = 0; 35648let isAccumulator = 1; 35649let DecoderNamespace = "EXT_mmvec"; 35650let Constraints = "$Vxx32 = $Vxx32in"; 35651} 35652def V6_vrsadubi_acc_alt : HInst< 35653(outs HvxWR:$Vxx32), 35654(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii), 35655"$Vxx32 += vrsadub($Vuu32,$Rt32,#$Ii)", 35656PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 35657let hasNewValue = 1; 35658let opNewValue = 0; 35659let isAccumulator = 1; 35660let isPseudo = 1; 35661let isCodeGenOnly = 1; 35662let DecoderNamespace = "EXT_mmvec"; 35663let Constraints = "$Vxx32 = $Vxx32in"; 35664} 35665def V6_vrsadubi_alt : HInst< 35666(outs HvxWR:$Vdd32), 35667(ins HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii), 35668"$Vdd32 = vrsadub($Vuu32,$Rt32,#$Ii)", 35669PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 35670let hasNewValue = 1; 35671let opNewValue = 0; 35672let isPseudo = 1; 35673let isCodeGenOnly = 1; 35674let DecoderNamespace = "EXT_mmvec"; 35675} 35676def V6_vsatdw : HInst< 35677(outs HvxVR:$Vd32), 35678(ins HvxVR:$Vu32, HvxVR:$Vv32), 35679"$Vd32.w = vsatdw($Vu32.w,$Vv32.w)", 35680tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV66]> { 35681let Inst{7-5} = 0b111; 35682let Inst{13-13} = 0b1; 35683let Inst{31-21} = 0b00011101100; 35684let hasNewValue = 1; 35685let opNewValue = 0; 35686let DecoderNamespace = "EXT_mmvec"; 35687} 35688def V6_vsathub : HInst< 35689(outs HvxVR:$Vd32), 35690(ins HvxVR:$Vu32, HvxVR:$Vv32), 35691"$Vd32.ub = vsat($Vu32.h,$Vv32.h)", 35692tc_8772086c, TypeCVI_VINLANESAT>, Enc_45364e, Requires<[UseHVXV60]> { 35693let Inst{7-5} = 0b010; 35694let Inst{13-13} = 0b0; 35695let Inst{31-21} = 0b00011111011; 35696let hasNewValue = 1; 35697let opNewValue = 0; 35698let DecoderNamespace = "EXT_mmvec"; 35699} 35700def V6_vsathub_alt : HInst< 35701(outs HvxVR:$Vd32), 35702(ins HvxVR:$Vu32, HvxVR:$Vv32), 35703"$Vd32 = vsathub($Vu32,$Vv32)", 35704PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 35705let hasNewValue = 1; 35706let opNewValue = 0; 35707let isPseudo = 1; 35708let isCodeGenOnly = 1; 35709let DecoderNamespace = "EXT_mmvec"; 35710} 35711def V6_vsatuwuh : HInst< 35712(outs HvxVR:$Vd32), 35713(ins HvxVR:$Vu32, HvxVR:$Vv32), 35714"$Vd32.uh = vsat($Vu32.uw,$Vv32.uw)", 35715tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV62]> { 35716let Inst{7-5} = 0b110; 35717let Inst{13-13} = 0b0; 35718let Inst{31-21} = 0b00011111001; 35719let hasNewValue = 1; 35720let opNewValue = 0; 35721let DecoderNamespace = "EXT_mmvec"; 35722} 35723def V6_vsatuwuh_alt : HInst< 35724(outs HvxVR:$Vd32), 35725(ins HvxVR:$Vu32, HvxVR:$Vv32), 35726"$Vd32 = vsatuwuh($Vu32,$Vv32)", 35727PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> { 35728let hasNewValue = 1; 35729let opNewValue = 0; 35730let isPseudo = 1; 35731let isCodeGenOnly = 1; 35732let DecoderNamespace = "EXT_mmvec"; 35733} 35734def V6_vsatwh : HInst< 35735(outs HvxVR:$Vd32), 35736(ins HvxVR:$Vu32, HvxVR:$Vv32), 35737"$Vd32.h = vsat($Vu32.w,$Vv32.w)", 35738tc_8772086c, TypeCVI_VINLANESAT>, Enc_45364e, Requires<[UseHVXV60]> { 35739let Inst{7-5} = 0b011; 35740let Inst{13-13} = 0b0; 35741let Inst{31-21} = 0b00011111011; 35742let hasNewValue = 1; 35743let opNewValue = 0; 35744let DecoderNamespace = "EXT_mmvec"; 35745} 35746def V6_vsatwh_alt : HInst< 35747(outs HvxVR:$Vd32), 35748(ins HvxVR:$Vu32, HvxVR:$Vv32), 35749"$Vd32 = vsatwh($Vu32,$Vv32)", 35750PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 35751let hasNewValue = 1; 35752let opNewValue = 0; 35753let isPseudo = 1; 35754let isCodeGenOnly = 1; 35755let DecoderNamespace = "EXT_mmvec"; 35756} 35757def V6_vsb : HInst< 35758(outs HvxWR:$Vdd32), 35759(ins HvxVR:$Vu32), 35760"$Vdd32.h = vsxt($Vu32.b)", 35761tc_b4416217, TypeCVI_VA_DV>, Enc_dd766a, Requires<[UseHVXV60]> { 35762let Inst{7-5} = 0b011; 35763let Inst{13-13} = 0b0; 35764let Inst{31-16} = 0b0001111000000010; 35765let hasNewValue = 1; 35766let opNewValue = 0; 35767let DecoderNamespace = "EXT_mmvec"; 35768} 35769def V6_vsb_alt : HInst< 35770(outs HvxWR:$Vdd32), 35771(ins HvxVR:$Vu32), 35772"$Vdd32 = vsxtb($Vu32)", 35773PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 35774let hasNewValue = 1; 35775let opNewValue = 0; 35776let isPseudo = 1; 35777let isCodeGenOnly = 1; 35778let DecoderNamespace = "EXT_mmvec"; 35779} 35780def V6_vscattermh : HInst< 35781(outs), 35782(ins IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32), 35783"vscatter($Rt32,$Mu2,$Vv32.h).h = $Vw32", 35784tc_9f363d21, TypeCVI_SCATTER>, Enc_16c48b, Requires<[UseHVXV65]> { 35785let Inst{7-5} = 0b001; 35786let Inst{31-21} = 0b00101111001; 35787let accessSize = HalfWordAccess; 35788let mayStore = 1; 35789let DecoderNamespace = "EXT_mmvec"; 35790} 35791def V6_vscattermh_add : HInst< 35792(outs), 35793(ins IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32), 35794"vscatter($Rt32,$Mu2,$Vv32.h).h += $Vw32", 35795tc_9f363d21, TypeCVI_SCATTER>, Enc_16c48b, Requires<[UseHVXV65]> { 35796let Inst{7-5} = 0b101; 35797let Inst{31-21} = 0b00101111001; 35798let accessSize = HalfWordAccess; 35799let isAccumulator = 1; 35800let mayStore = 1; 35801let DecoderNamespace = "EXT_mmvec"; 35802} 35803def V6_vscattermh_add_alt : HInst< 35804(outs), 35805(ins IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32), 35806"vscatter($Rt32,$Mu2,$Vv32.h) += $Vw32.h", 35807PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> { 35808let isAccumulator = 1; 35809let isPseudo = 1; 35810let isCodeGenOnly = 1; 35811let DecoderNamespace = "EXT_mmvec"; 35812} 35813def V6_vscattermh_alt : HInst< 35814(outs), 35815(ins IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32), 35816"vscatter($Rt32,$Mu2,$Vv32.h) = $Vw32.h", 35817PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> { 35818let isPseudo = 1; 35819let isCodeGenOnly = 1; 35820let DecoderNamespace = "EXT_mmvec"; 35821} 35822def V6_vscattermhq : HInst< 35823(outs), 35824(ins HvxQR:$Qs4, IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32), 35825"if ($Qs4) vscatter($Rt32,$Mu2,$Vv32.h).h = $Vw32", 35826tc_8e420e4d, TypeCVI_SCATTER>, Enc_9be1de, Requires<[UseHVXV65]> { 35827let Inst{7-7} = 0b1; 35828let Inst{31-21} = 0b00101111100; 35829let accessSize = HalfWordAccess; 35830let mayStore = 1; 35831let DecoderNamespace = "EXT_mmvec"; 35832} 35833def V6_vscattermhq_alt : HInst< 35834(outs), 35835(ins HvxQR:$Qs4, IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32), 35836"if ($Qs4) vscatter($Rt32,$Mu2,$Vv32.h) = $Vw32.h", 35837PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> { 35838let isPseudo = 1; 35839let isCodeGenOnly = 1; 35840let DecoderNamespace = "EXT_mmvec"; 35841} 35842def V6_vscattermhw : HInst< 35843(outs), 35844(ins IntRegs:$Rt32, ModRegs:$Mu2, HvxWR:$Vvv32, HvxVR:$Vw32), 35845"vscatter($Rt32,$Mu2,$Vvv32.w).h = $Vw32", 35846tc_7273323b, TypeCVI_SCATTER_DV>, Enc_a641d0, Requires<[UseHVXV65]> { 35847let Inst{7-5} = 0b010; 35848let Inst{31-21} = 0b00101111001; 35849let accessSize = HalfWordAccess; 35850let mayStore = 1; 35851let DecoderNamespace = "EXT_mmvec"; 35852} 35853def V6_vscattermhw_add : HInst< 35854(outs), 35855(ins IntRegs:$Rt32, ModRegs:$Mu2, HvxWR:$Vvv32, HvxVR:$Vw32), 35856"vscatter($Rt32,$Mu2,$Vvv32.w).h += $Vw32", 35857tc_7273323b, TypeCVI_SCATTER_DV>, Enc_a641d0, Requires<[UseHVXV65]> { 35858let Inst{7-5} = 0b110; 35859let Inst{31-21} = 0b00101111001; 35860let accessSize = HalfWordAccess; 35861let isAccumulator = 1; 35862let mayStore = 1; 35863let DecoderNamespace = "EXT_mmvec"; 35864} 35865def V6_vscattermhwq : HInst< 35866(outs), 35867(ins HvxQR:$Qs4, IntRegs:$Rt32, ModRegs:$Mu2, HvxWR:$Vvv32, HvxVR:$Vw32), 35868"if ($Qs4) vscatter($Rt32,$Mu2,$Vvv32.w).h = $Vw32", 35869tc_58d21193, TypeCVI_SCATTER_DV>, Enc_3d6d37, Requires<[UseHVXV65]> { 35870let Inst{7-7} = 0b0; 35871let Inst{31-21} = 0b00101111101; 35872let accessSize = HalfWordAccess; 35873let mayStore = 1; 35874let DecoderNamespace = "EXT_mmvec"; 35875} 35876def V6_vscattermw : HInst< 35877(outs), 35878(ins IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32), 35879"vscatter($Rt32,$Mu2,$Vv32.w).w = $Vw32", 35880tc_9f363d21, TypeCVI_SCATTER>, Enc_16c48b, Requires<[UseHVXV65]> { 35881let Inst{7-5} = 0b000; 35882let Inst{31-21} = 0b00101111001; 35883let accessSize = WordAccess; 35884let mayStore = 1; 35885let DecoderNamespace = "EXT_mmvec"; 35886} 35887def V6_vscattermw_add : HInst< 35888(outs), 35889(ins IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32), 35890"vscatter($Rt32,$Mu2,$Vv32.w).w += $Vw32", 35891tc_9f363d21, TypeCVI_SCATTER>, Enc_16c48b, Requires<[UseHVXV65]> { 35892let Inst{7-5} = 0b100; 35893let Inst{31-21} = 0b00101111001; 35894let accessSize = WordAccess; 35895let isAccumulator = 1; 35896let mayStore = 1; 35897let DecoderNamespace = "EXT_mmvec"; 35898} 35899def V6_vscattermw_add_alt : HInst< 35900(outs), 35901(ins IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32), 35902"vscatter($Rt32,$Mu2,$Vv32.w) += $Vw32.w", 35903PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> { 35904let isAccumulator = 1; 35905let isPseudo = 1; 35906let isCodeGenOnly = 1; 35907let DecoderNamespace = "EXT_mmvec"; 35908} 35909def V6_vscattermw_alt : HInst< 35910(outs), 35911(ins IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32), 35912"vscatter($Rt32,$Mu2,$Vv32.w) = $Vw32.w", 35913PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> { 35914let isPseudo = 1; 35915let isCodeGenOnly = 1; 35916let DecoderNamespace = "EXT_mmvec"; 35917} 35918def V6_vscattermwh_add_alt : HInst< 35919(outs), 35920(ins IntRegs:$Rt32, ModRegs:$Mu2, HvxWR:$Vvv32, HvxVR:$Vw32), 35921"vscatter($Rt32,$Mu2,$Vvv32.w) += $Vw32.h", 35922PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> { 35923let isAccumulator = 1; 35924let isPseudo = 1; 35925let isCodeGenOnly = 1; 35926let DecoderNamespace = "EXT_mmvec"; 35927} 35928def V6_vscattermwh_alt : HInst< 35929(outs), 35930(ins IntRegs:$Rt32, ModRegs:$Mu2, HvxWR:$Vvv32, HvxVR:$Vw32), 35931"vscatter($Rt32,$Mu2,$Vvv32.w) = $Vw32.h", 35932PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> { 35933let isPseudo = 1; 35934let isCodeGenOnly = 1; 35935let DecoderNamespace = "EXT_mmvec"; 35936} 35937def V6_vscattermwhq_alt : HInst< 35938(outs), 35939(ins HvxQR:$Qs4, IntRegs:$Rt32, ModRegs:$Mu2, HvxWR:$Vvv32, HvxVR:$Vw32), 35940"if ($Qs4) vscatter($Rt32,$Mu2,$Vvv32.w) = $Vw32.h", 35941PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> { 35942let isPseudo = 1; 35943let isCodeGenOnly = 1; 35944let DecoderNamespace = "EXT_mmvec"; 35945} 35946def V6_vscattermwq : HInst< 35947(outs), 35948(ins HvxQR:$Qs4, IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32), 35949"if ($Qs4) vscatter($Rt32,$Mu2,$Vv32.w).w = $Vw32", 35950tc_8e420e4d, TypeCVI_SCATTER>, Enc_9be1de, Requires<[UseHVXV65]> { 35951let Inst{7-7} = 0b0; 35952let Inst{31-21} = 0b00101111100; 35953let accessSize = WordAccess; 35954let mayStore = 1; 35955let DecoderNamespace = "EXT_mmvec"; 35956} 35957def V6_vscattermwq_alt : HInst< 35958(outs), 35959(ins HvxQR:$Qs4, IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32), 35960"if ($Qs4) vscatter($Rt32,$Mu2,$Vv32.w) = $Vw32.w", 35961PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> { 35962let isPseudo = 1; 35963let isCodeGenOnly = 1; 35964let DecoderNamespace = "EXT_mmvec"; 35965} 35966def V6_vsh : HInst< 35967(outs HvxWR:$Vdd32), 35968(ins HvxVR:$Vu32), 35969"$Vdd32.w = vsxt($Vu32.h)", 35970tc_b4416217, TypeCVI_VA_DV>, Enc_dd766a, Requires<[UseHVXV60]> { 35971let Inst{7-5} = 0b100; 35972let Inst{13-13} = 0b0; 35973let Inst{31-16} = 0b0001111000000010; 35974let hasNewValue = 1; 35975let opNewValue = 0; 35976let DecoderNamespace = "EXT_mmvec"; 35977} 35978def V6_vsh_alt : HInst< 35979(outs HvxWR:$Vdd32), 35980(ins HvxVR:$Vu32), 35981"$Vdd32 = vsxth($Vu32)", 35982PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 35983let hasNewValue = 1; 35984let opNewValue = 0; 35985let isPseudo = 1; 35986let isCodeGenOnly = 1; 35987let DecoderNamespace = "EXT_mmvec"; 35988} 35989def V6_vshufeh : HInst< 35990(outs HvxVR:$Vd32), 35991(ins HvxVR:$Vu32, HvxVR:$Vv32), 35992"$Vd32.h = vshuffe($Vu32.h,$Vv32.h)", 35993tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> { 35994let Inst{7-5} = 0b011; 35995let Inst{13-13} = 0b0; 35996let Inst{31-21} = 0b00011111010; 35997let hasNewValue = 1; 35998let opNewValue = 0; 35999let DecoderNamespace = "EXT_mmvec"; 36000} 36001def V6_vshufeh_alt : HInst< 36002(outs HvxVR:$Vd32), 36003(ins HvxVR:$Vu32, HvxVR:$Vv32), 36004"$Vd32 = vshuffeh($Vu32,$Vv32)", 36005PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 36006let hasNewValue = 1; 36007let opNewValue = 0; 36008let isPseudo = 1; 36009let isCodeGenOnly = 1; 36010let DecoderNamespace = "EXT_mmvec"; 36011} 36012def V6_vshuff : HInst< 36013(outs HvxVR:$Vy32, HvxVR:$Vx32), 36014(ins HvxVR:$Vy32in, HvxVR:$Vx32in, IntRegs:$Rt32), 36015"vshuff($Vy32,$Vx32,$Rt32)", 36016tc_561aaa58, TypeCVI_VP_VS>, Enc_989021, Requires<[UseHVXV60]> { 36017let Inst{7-5} = 0b001; 36018let Inst{13-13} = 0b1; 36019let Inst{31-21} = 0b00011001111; 36020let hasNewValue = 1; 36021let opNewValue = 0; 36022let hasNewValue2 = 1; 36023let opNewValue2 = 1; 36024let DecoderNamespace = "EXT_mmvec"; 36025let Constraints = "$Vy32 = $Vy32in, $Vx32 = $Vx32in"; 36026} 36027def V6_vshuffb : HInst< 36028(outs HvxVR:$Vd32), 36029(ins HvxVR:$Vu32), 36030"$Vd32.b = vshuff($Vu32.b)", 36031tc_946013d8, TypeCVI_VP>, Enc_e7581c, Requires<[UseHVXV60]> { 36032let Inst{7-5} = 0b000; 36033let Inst{13-13} = 0b0; 36034let Inst{31-16} = 0b0001111000000010; 36035let hasNewValue = 1; 36036let opNewValue = 0; 36037let DecoderNamespace = "EXT_mmvec"; 36038} 36039def V6_vshuffb_alt : HInst< 36040(outs HvxVR:$Vd32), 36041(ins HvxVR:$Vu32), 36042"$Vd32 = vshuffb($Vu32)", 36043PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 36044let hasNewValue = 1; 36045let opNewValue = 0; 36046let isPseudo = 1; 36047let isCodeGenOnly = 1; 36048let DecoderNamespace = "EXT_mmvec"; 36049} 36050def V6_vshuffeb : HInst< 36051(outs HvxVR:$Vd32), 36052(ins HvxVR:$Vu32, HvxVR:$Vv32), 36053"$Vd32.b = vshuffe($Vu32.b,$Vv32.b)", 36054tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> { 36055let Inst{7-5} = 0b001; 36056let Inst{13-13} = 0b0; 36057let Inst{31-21} = 0b00011111010; 36058let hasNewValue = 1; 36059let opNewValue = 0; 36060let DecoderNamespace = "EXT_mmvec"; 36061} 36062def V6_vshuffeb_alt : HInst< 36063(outs HvxVR:$Vd32), 36064(ins HvxVR:$Vu32, HvxVR:$Vv32), 36065"$Vd32 = vshuffeb($Vu32,$Vv32)", 36066PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 36067let hasNewValue = 1; 36068let opNewValue = 0; 36069let isPseudo = 1; 36070let isCodeGenOnly = 1; 36071let DecoderNamespace = "EXT_mmvec"; 36072} 36073def V6_vshuffh : HInst< 36074(outs HvxVR:$Vd32), 36075(ins HvxVR:$Vu32), 36076"$Vd32.h = vshuff($Vu32.h)", 36077tc_946013d8, TypeCVI_VP>, Enc_e7581c, Requires<[UseHVXV60]> { 36078let Inst{7-5} = 0b111; 36079let Inst{13-13} = 0b0; 36080let Inst{31-16} = 0b0001111000000001; 36081let hasNewValue = 1; 36082let opNewValue = 0; 36083let DecoderNamespace = "EXT_mmvec"; 36084} 36085def V6_vshuffh_alt : HInst< 36086(outs HvxVR:$Vd32), 36087(ins HvxVR:$Vu32), 36088"$Vd32 = vshuffh($Vu32)", 36089PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 36090let hasNewValue = 1; 36091let opNewValue = 0; 36092let isPseudo = 1; 36093let isCodeGenOnly = 1; 36094let DecoderNamespace = "EXT_mmvec"; 36095} 36096def V6_vshuffob : HInst< 36097(outs HvxVR:$Vd32), 36098(ins HvxVR:$Vu32, HvxVR:$Vv32), 36099"$Vd32.b = vshuffo($Vu32.b,$Vv32.b)", 36100tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> { 36101let Inst{7-5} = 0b010; 36102let Inst{13-13} = 0b0; 36103let Inst{31-21} = 0b00011111010; 36104let hasNewValue = 1; 36105let opNewValue = 0; 36106let DecoderNamespace = "EXT_mmvec"; 36107} 36108def V6_vshuffob_alt : HInst< 36109(outs HvxVR:$Vd32), 36110(ins HvxVR:$Vu32, HvxVR:$Vv32), 36111"$Vd32 = vshuffob($Vu32,$Vv32)", 36112PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 36113let hasNewValue = 1; 36114let opNewValue = 0; 36115let isPseudo = 1; 36116let isCodeGenOnly = 1; 36117let DecoderNamespace = "EXT_mmvec"; 36118} 36119def V6_vshuffvdd : HInst< 36120(outs HvxWR:$Vdd32), 36121(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8), 36122"$Vdd32 = vshuff($Vu32,$Vv32,$Rt8)", 36123tc_87adc037, TypeCVI_VP_VS>, Enc_24a7dc, Requires<[UseHVXV60]> { 36124let Inst{7-5} = 0b011; 36125let Inst{13-13} = 0b1; 36126let Inst{31-24} = 0b00011011; 36127let hasNewValue = 1; 36128let opNewValue = 0; 36129let DecoderNamespace = "EXT_mmvec"; 36130} 36131def V6_vshufoeb : HInst< 36132(outs HvxWR:$Vdd32), 36133(ins HvxVR:$Vu32, HvxVR:$Vv32), 36134"$Vdd32.b = vshuffoe($Vu32.b,$Vv32.b)", 36135tc_db5555f3, TypeCVI_VA_DV>, Enc_71bb9b, Requires<[UseHVXV60]> { 36136let Inst{7-5} = 0b110; 36137let Inst{13-13} = 0b0; 36138let Inst{31-21} = 0b00011111010; 36139let hasNewValue = 1; 36140let opNewValue = 0; 36141let DecoderNamespace = "EXT_mmvec"; 36142} 36143def V6_vshufoeb_alt : HInst< 36144(outs HvxWR:$Vdd32), 36145(ins HvxVR:$Vu32, HvxVR:$Vv32), 36146"$Vdd32 = vshuffoeb($Vu32,$Vv32)", 36147PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 36148let hasNewValue = 1; 36149let opNewValue = 0; 36150let isPseudo = 1; 36151let isCodeGenOnly = 1; 36152let DecoderNamespace = "EXT_mmvec"; 36153} 36154def V6_vshufoeh : HInst< 36155(outs HvxWR:$Vdd32), 36156(ins HvxVR:$Vu32, HvxVR:$Vv32), 36157"$Vdd32.h = vshuffoe($Vu32.h,$Vv32.h)", 36158tc_db5555f3, TypeCVI_VA_DV>, Enc_71bb9b, Requires<[UseHVXV60]> { 36159let Inst{7-5} = 0b101; 36160let Inst{13-13} = 0b0; 36161let Inst{31-21} = 0b00011111010; 36162let hasNewValue = 1; 36163let opNewValue = 0; 36164let DecoderNamespace = "EXT_mmvec"; 36165} 36166def V6_vshufoeh_alt : HInst< 36167(outs HvxWR:$Vdd32), 36168(ins HvxVR:$Vu32, HvxVR:$Vv32), 36169"$Vdd32 = vshuffoeh($Vu32,$Vv32)", 36170PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 36171let hasNewValue = 1; 36172let opNewValue = 0; 36173let isPseudo = 1; 36174let isCodeGenOnly = 1; 36175let DecoderNamespace = "EXT_mmvec"; 36176} 36177def V6_vshufoh : HInst< 36178(outs HvxVR:$Vd32), 36179(ins HvxVR:$Vu32, HvxVR:$Vv32), 36180"$Vd32.h = vshuffo($Vu32.h,$Vv32.h)", 36181tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> { 36182let Inst{7-5} = 0b100; 36183let Inst{13-13} = 0b0; 36184let Inst{31-21} = 0b00011111010; 36185let hasNewValue = 1; 36186let opNewValue = 0; 36187let DecoderNamespace = "EXT_mmvec"; 36188} 36189def V6_vshufoh_alt : HInst< 36190(outs HvxVR:$Vd32), 36191(ins HvxVR:$Vu32, HvxVR:$Vv32), 36192"$Vd32 = vshuffoh($Vu32,$Vv32)", 36193PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 36194let hasNewValue = 1; 36195let opNewValue = 0; 36196let isPseudo = 1; 36197let isCodeGenOnly = 1; 36198let DecoderNamespace = "EXT_mmvec"; 36199} 36200def V6_vsubb : HInst< 36201(outs HvxVR:$Vd32), 36202(ins HvxVR:$Vu32, HvxVR:$Vv32), 36203"$Vd32.b = vsub($Vu32.b,$Vv32.b)", 36204tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> { 36205let Inst{7-5} = 0b101; 36206let Inst{13-13} = 0b0; 36207let Inst{31-21} = 0b00011100010; 36208let hasNewValue = 1; 36209let opNewValue = 0; 36210let DecoderNamespace = "EXT_mmvec"; 36211} 36212def V6_vsubb_alt : HInst< 36213(outs HvxVR:$Vd32), 36214(ins HvxVR:$Vu32, HvxVR:$Vv32), 36215"$Vd32 = vsubb($Vu32,$Vv32)", 36216PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 36217let hasNewValue = 1; 36218let opNewValue = 0; 36219let isPseudo = 1; 36220let isCodeGenOnly = 1; 36221let DecoderNamespace = "EXT_mmvec"; 36222} 36223def V6_vsubb_dv : HInst< 36224(outs HvxWR:$Vdd32), 36225(ins HvxWR:$Vuu32, HvxWR:$Vvv32), 36226"$Vdd32.b = vsub($Vuu32.b,$Vvv32.b)", 36227tc_db5555f3, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> { 36228let Inst{7-5} = 0b011; 36229let Inst{13-13} = 0b0; 36230let Inst{31-21} = 0b00011100100; 36231let hasNewValue = 1; 36232let opNewValue = 0; 36233let DecoderNamespace = "EXT_mmvec"; 36234} 36235def V6_vsubb_dv_alt : HInst< 36236(outs HvxWR:$Vdd32), 36237(ins HvxWR:$Vuu32, HvxWR:$Vvv32), 36238"$Vdd32 = vsubb($Vuu32,$Vvv32)", 36239PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 36240let hasNewValue = 1; 36241let opNewValue = 0; 36242let isPseudo = 1; 36243let isCodeGenOnly = 1; 36244let DecoderNamespace = "EXT_mmvec"; 36245} 36246def V6_vsubbnq : HInst< 36247(outs HvxVR:$Vx32), 36248(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32), 36249"if (!$Qv4) $Vx32.b -= $Vu32.b", 36250tc_257f6f7c, TypeCVI_VA>, Enc_a90628, Requires<[UseHVXV60]> { 36251let Inst{7-5} = 0b001; 36252let Inst{13-13} = 0b1; 36253let Inst{21-16} = 0b000010; 36254let Inst{31-24} = 0b00011110; 36255let hasNewValue = 1; 36256let opNewValue = 0; 36257let DecoderNamespace = "EXT_mmvec"; 36258let Constraints = "$Vx32 = $Vx32in"; 36259} 36260def V6_vsubbnq_alt : HInst< 36261(outs HvxVR:$Vx32), 36262(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32), 36263"if (!$Qv4.b) $Vx32.b -= $Vu32.b", 36264PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 36265let hasNewValue = 1; 36266let opNewValue = 0; 36267let isPseudo = 1; 36268let isCodeGenOnly = 1; 36269let DecoderNamespace = "EXT_mmvec"; 36270let Constraints = "$Vx32 = $Vx32in"; 36271} 36272def V6_vsubbq : HInst< 36273(outs HvxVR:$Vx32), 36274(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32), 36275"if ($Qv4) $Vx32.b -= $Vu32.b", 36276tc_257f6f7c, TypeCVI_VA>, Enc_a90628, Requires<[UseHVXV60]> { 36277let Inst{7-5} = 0b110; 36278let Inst{13-13} = 0b1; 36279let Inst{21-16} = 0b000001; 36280let Inst{31-24} = 0b00011110; 36281let hasNewValue = 1; 36282let opNewValue = 0; 36283let DecoderNamespace = "EXT_mmvec"; 36284let Constraints = "$Vx32 = $Vx32in"; 36285} 36286def V6_vsubbq_alt : HInst< 36287(outs HvxVR:$Vx32), 36288(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32), 36289"if ($Qv4.b) $Vx32.b -= $Vu32.b", 36290PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 36291let hasNewValue = 1; 36292let opNewValue = 0; 36293let isPseudo = 1; 36294let isCodeGenOnly = 1; 36295let DecoderNamespace = "EXT_mmvec"; 36296let Constraints = "$Vx32 = $Vx32in"; 36297} 36298def V6_vsubbsat : HInst< 36299(outs HvxVR:$Vd32), 36300(ins HvxVR:$Vu32, HvxVR:$Vv32), 36301"$Vd32.b = vsub($Vu32.b,$Vv32.b):sat", 36302tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV62]> { 36303let Inst{7-5} = 0b010; 36304let Inst{13-13} = 0b0; 36305let Inst{31-21} = 0b00011111001; 36306let hasNewValue = 1; 36307let opNewValue = 0; 36308let DecoderNamespace = "EXT_mmvec"; 36309} 36310def V6_vsubbsat_alt : HInst< 36311(outs HvxVR:$Vd32), 36312(ins HvxVR:$Vu32, HvxVR:$Vv32), 36313"$Vd32 = vsubb($Vu32,$Vv32):sat", 36314PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> { 36315let hasNewValue = 1; 36316let opNewValue = 0; 36317let isPseudo = 1; 36318let isCodeGenOnly = 1; 36319let DecoderNamespace = "EXT_mmvec"; 36320} 36321def V6_vsubbsat_dv : HInst< 36322(outs HvxWR:$Vdd32), 36323(ins HvxWR:$Vuu32, HvxWR:$Vvv32), 36324"$Vdd32.b = vsub($Vuu32.b,$Vvv32.b):sat", 36325tc_db5555f3, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV62]> { 36326let Inst{7-5} = 0b001; 36327let Inst{13-13} = 0b0; 36328let Inst{31-21} = 0b00011110101; 36329let hasNewValue = 1; 36330let opNewValue = 0; 36331let DecoderNamespace = "EXT_mmvec"; 36332} 36333def V6_vsubbsat_dv_alt : HInst< 36334(outs HvxWR:$Vdd32), 36335(ins HvxWR:$Vuu32, HvxWR:$Vvv32), 36336"$Vdd32 = vsubb($Vuu32,$Vvv32):sat", 36337PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> { 36338let hasNewValue = 1; 36339let opNewValue = 0; 36340let isPseudo = 1; 36341let isCodeGenOnly = 1; 36342let DecoderNamespace = "EXT_mmvec"; 36343} 36344def V6_vsubcarry : HInst< 36345(outs HvxVR:$Vd32, HvxQR:$Qx4), 36346(ins HvxVR:$Vu32, HvxVR:$Vv32, HvxQR:$Qx4in), 36347"$Vd32.w = vsub($Vu32.w,$Vv32.w,$Qx4):carry", 36348tc_7e6a3e89, TypeCVI_VA>, Enc_b43b67, Requires<[UseHVXV62]> { 36349let Inst{7-7} = 0b1; 36350let Inst{13-13} = 0b1; 36351let Inst{31-21} = 0b00011100101; 36352let hasNewValue = 1; 36353let opNewValue = 0; 36354let DecoderNamespace = "EXT_mmvec"; 36355let Constraints = "$Qx4 = $Qx4in"; 36356} 36357def V6_vsubcarryo : HInst< 36358(outs HvxVR:$Vd32, HvxQR:$Qe4), 36359(ins HvxVR:$Vu32, HvxVR:$Vv32), 36360"$Vd32.w,$Qe4 = vsub($Vu32.w,$Vv32.w):carry", 36361tc_e35c1e93, TypeCOPROC_VX>, Enc_c1d806, Requires<[UseHVXV66]> { 36362let Inst{7-7} = 0b1; 36363let Inst{13-13} = 0b1; 36364let Inst{31-21} = 0b00011101101; 36365let hasNewValue = 1; 36366let opNewValue = 0; 36367let hasNewValue2 = 1; 36368let opNewValue2 = 1; 36369let DecoderNamespace = "EXT_mmvec"; 36370} 36371def V6_vsubh : HInst< 36372(outs HvxVR:$Vd32), 36373(ins HvxVR:$Vu32, HvxVR:$Vv32), 36374"$Vd32.h = vsub($Vu32.h,$Vv32.h)", 36375tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> { 36376let Inst{7-5} = 0b110; 36377let Inst{13-13} = 0b0; 36378let Inst{31-21} = 0b00011100010; 36379let hasNewValue = 1; 36380let opNewValue = 0; 36381let DecoderNamespace = "EXT_mmvec"; 36382} 36383def V6_vsubh_alt : HInst< 36384(outs HvxVR:$Vd32), 36385(ins HvxVR:$Vu32, HvxVR:$Vv32), 36386"$Vd32 = vsubh($Vu32,$Vv32)", 36387PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 36388let hasNewValue = 1; 36389let opNewValue = 0; 36390let isPseudo = 1; 36391let isCodeGenOnly = 1; 36392let DecoderNamespace = "EXT_mmvec"; 36393} 36394def V6_vsubh_dv : HInst< 36395(outs HvxWR:$Vdd32), 36396(ins HvxWR:$Vuu32, HvxWR:$Vvv32), 36397"$Vdd32.h = vsub($Vuu32.h,$Vvv32.h)", 36398tc_db5555f3, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> { 36399let Inst{7-5} = 0b100; 36400let Inst{13-13} = 0b0; 36401let Inst{31-21} = 0b00011100100; 36402let hasNewValue = 1; 36403let opNewValue = 0; 36404let DecoderNamespace = "EXT_mmvec"; 36405} 36406def V6_vsubh_dv_alt : HInst< 36407(outs HvxWR:$Vdd32), 36408(ins HvxWR:$Vuu32, HvxWR:$Vvv32), 36409"$Vdd32 = vsubh($Vuu32,$Vvv32)", 36410PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 36411let hasNewValue = 1; 36412let opNewValue = 0; 36413let isPseudo = 1; 36414let isCodeGenOnly = 1; 36415let DecoderNamespace = "EXT_mmvec"; 36416} 36417def V6_vsubhnq : HInst< 36418(outs HvxVR:$Vx32), 36419(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32), 36420"if (!$Qv4) $Vx32.h -= $Vu32.h", 36421tc_257f6f7c, TypeCVI_VA>, Enc_a90628, Requires<[UseHVXV60]> { 36422let Inst{7-5} = 0b010; 36423let Inst{13-13} = 0b1; 36424let Inst{21-16} = 0b000010; 36425let Inst{31-24} = 0b00011110; 36426let hasNewValue = 1; 36427let opNewValue = 0; 36428let DecoderNamespace = "EXT_mmvec"; 36429let Constraints = "$Vx32 = $Vx32in"; 36430} 36431def V6_vsubhnq_alt : HInst< 36432(outs HvxVR:$Vx32), 36433(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32), 36434"if (!$Qv4.h) $Vx32.h -= $Vu32.h", 36435PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 36436let hasNewValue = 1; 36437let opNewValue = 0; 36438let isPseudo = 1; 36439let isCodeGenOnly = 1; 36440let DecoderNamespace = "EXT_mmvec"; 36441let Constraints = "$Vx32 = $Vx32in"; 36442} 36443def V6_vsubhq : HInst< 36444(outs HvxVR:$Vx32), 36445(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32), 36446"if ($Qv4) $Vx32.h -= $Vu32.h", 36447tc_257f6f7c, TypeCVI_VA>, Enc_a90628, Requires<[UseHVXV60]> { 36448let Inst{7-5} = 0b111; 36449let Inst{13-13} = 0b1; 36450let Inst{21-16} = 0b000001; 36451let Inst{31-24} = 0b00011110; 36452let hasNewValue = 1; 36453let opNewValue = 0; 36454let DecoderNamespace = "EXT_mmvec"; 36455let Constraints = "$Vx32 = $Vx32in"; 36456} 36457def V6_vsubhq_alt : HInst< 36458(outs HvxVR:$Vx32), 36459(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32), 36460"if ($Qv4.h) $Vx32.h -= $Vu32.h", 36461PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 36462let hasNewValue = 1; 36463let opNewValue = 0; 36464let isPseudo = 1; 36465let isCodeGenOnly = 1; 36466let DecoderNamespace = "EXT_mmvec"; 36467let Constraints = "$Vx32 = $Vx32in"; 36468} 36469def V6_vsubhsat : HInst< 36470(outs HvxVR:$Vd32), 36471(ins HvxVR:$Vu32, HvxVR:$Vv32), 36472"$Vd32.h = vsub($Vu32.h,$Vv32.h):sat", 36473tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> { 36474let Inst{7-5} = 0b010; 36475let Inst{13-13} = 0b0; 36476let Inst{31-21} = 0b00011100011; 36477let hasNewValue = 1; 36478let opNewValue = 0; 36479let DecoderNamespace = "EXT_mmvec"; 36480} 36481def V6_vsubhsat_alt : HInst< 36482(outs HvxVR:$Vd32), 36483(ins HvxVR:$Vu32, HvxVR:$Vv32), 36484"$Vd32 = vsubh($Vu32,$Vv32):sat", 36485PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 36486let hasNewValue = 1; 36487let opNewValue = 0; 36488let isPseudo = 1; 36489let isCodeGenOnly = 1; 36490let DecoderNamespace = "EXT_mmvec"; 36491} 36492def V6_vsubhsat_dv : HInst< 36493(outs HvxWR:$Vdd32), 36494(ins HvxWR:$Vuu32, HvxWR:$Vvv32), 36495"$Vdd32.h = vsub($Vuu32.h,$Vvv32.h):sat", 36496tc_db5555f3, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> { 36497let Inst{7-5} = 0b000; 36498let Inst{13-13} = 0b0; 36499let Inst{31-21} = 0b00011100101; 36500let hasNewValue = 1; 36501let opNewValue = 0; 36502let DecoderNamespace = "EXT_mmvec"; 36503} 36504def V6_vsubhsat_dv_alt : HInst< 36505(outs HvxWR:$Vdd32), 36506(ins HvxWR:$Vuu32, HvxWR:$Vvv32), 36507"$Vdd32 = vsubh($Vuu32,$Vvv32):sat", 36508PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 36509let hasNewValue = 1; 36510let opNewValue = 0; 36511let isPseudo = 1; 36512let isCodeGenOnly = 1; 36513let DecoderNamespace = "EXT_mmvec"; 36514} 36515def V6_vsubhw : HInst< 36516(outs HvxWR:$Vdd32), 36517(ins HvxVR:$Vu32, HvxVR:$Vv32), 36518"$Vdd32.w = vsub($Vu32.h,$Vv32.h)", 36519tc_d8287c14, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV60]> { 36520let Inst{7-5} = 0b111; 36521let Inst{13-13} = 0b0; 36522let Inst{31-21} = 0b00011100101; 36523let hasNewValue = 1; 36524let opNewValue = 0; 36525let DecoderNamespace = "EXT_mmvec"; 36526} 36527def V6_vsubhw_alt : HInst< 36528(outs HvxWR:$Vdd32), 36529(ins HvxVR:$Vu32, HvxVR:$Vv32), 36530"$Vdd32 = vsubh($Vu32,$Vv32)", 36531PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 36532let hasNewValue = 1; 36533let opNewValue = 0; 36534let isPseudo = 1; 36535let isCodeGenOnly = 1; 36536let DecoderNamespace = "EXT_mmvec"; 36537} 36538def V6_vsububh : HInst< 36539(outs HvxWR:$Vdd32), 36540(ins HvxVR:$Vu32, HvxVR:$Vv32), 36541"$Vdd32.h = vsub($Vu32.ub,$Vv32.ub)", 36542tc_d8287c14, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV60]> { 36543let Inst{7-5} = 0b101; 36544let Inst{13-13} = 0b0; 36545let Inst{31-21} = 0b00011100101; 36546let hasNewValue = 1; 36547let opNewValue = 0; 36548let DecoderNamespace = "EXT_mmvec"; 36549} 36550def V6_vsububh_alt : HInst< 36551(outs HvxWR:$Vdd32), 36552(ins HvxVR:$Vu32, HvxVR:$Vv32), 36553"$Vdd32 = vsubub($Vu32,$Vv32)", 36554PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 36555let hasNewValue = 1; 36556let opNewValue = 0; 36557let isPseudo = 1; 36558let isCodeGenOnly = 1; 36559let DecoderNamespace = "EXT_mmvec"; 36560} 36561def V6_vsububsat : HInst< 36562(outs HvxVR:$Vd32), 36563(ins HvxVR:$Vu32, HvxVR:$Vv32), 36564"$Vd32.ub = vsub($Vu32.ub,$Vv32.ub):sat", 36565tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> { 36566let Inst{7-5} = 0b000; 36567let Inst{13-13} = 0b0; 36568let Inst{31-21} = 0b00011100011; 36569let hasNewValue = 1; 36570let opNewValue = 0; 36571let DecoderNamespace = "EXT_mmvec"; 36572} 36573def V6_vsububsat_alt : HInst< 36574(outs HvxVR:$Vd32), 36575(ins HvxVR:$Vu32, HvxVR:$Vv32), 36576"$Vd32 = vsubub($Vu32,$Vv32):sat", 36577PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 36578let hasNewValue = 1; 36579let opNewValue = 0; 36580let isPseudo = 1; 36581let isCodeGenOnly = 1; 36582let DecoderNamespace = "EXT_mmvec"; 36583} 36584def V6_vsububsat_dv : HInst< 36585(outs HvxWR:$Vdd32), 36586(ins HvxWR:$Vuu32, HvxWR:$Vvv32), 36587"$Vdd32.ub = vsub($Vuu32.ub,$Vvv32.ub):sat", 36588tc_db5555f3, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> { 36589let Inst{7-5} = 0b110; 36590let Inst{13-13} = 0b0; 36591let Inst{31-21} = 0b00011100100; 36592let hasNewValue = 1; 36593let opNewValue = 0; 36594let DecoderNamespace = "EXT_mmvec"; 36595} 36596def V6_vsububsat_dv_alt : HInst< 36597(outs HvxWR:$Vdd32), 36598(ins HvxWR:$Vuu32, HvxWR:$Vvv32), 36599"$Vdd32 = vsubub($Vuu32,$Vvv32):sat", 36600PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 36601let hasNewValue = 1; 36602let opNewValue = 0; 36603let isPseudo = 1; 36604let isCodeGenOnly = 1; 36605let DecoderNamespace = "EXT_mmvec"; 36606} 36607def V6_vsubububb_sat : HInst< 36608(outs HvxVR:$Vd32), 36609(ins HvxVR:$Vu32, HvxVR:$Vv32), 36610"$Vd32.ub = vsub($Vu32.ub,$Vv32.b):sat", 36611tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV62]> { 36612let Inst{7-5} = 0b101; 36613let Inst{13-13} = 0b0; 36614let Inst{31-21} = 0b00011110101; 36615let hasNewValue = 1; 36616let opNewValue = 0; 36617let DecoderNamespace = "EXT_mmvec"; 36618} 36619def V6_vsubuhsat : HInst< 36620(outs HvxVR:$Vd32), 36621(ins HvxVR:$Vu32, HvxVR:$Vv32), 36622"$Vd32.uh = vsub($Vu32.uh,$Vv32.uh):sat", 36623tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> { 36624let Inst{7-5} = 0b001; 36625let Inst{13-13} = 0b0; 36626let Inst{31-21} = 0b00011100011; 36627let hasNewValue = 1; 36628let opNewValue = 0; 36629let DecoderNamespace = "EXT_mmvec"; 36630} 36631def V6_vsubuhsat_alt : HInst< 36632(outs HvxVR:$Vd32), 36633(ins HvxVR:$Vu32, HvxVR:$Vv32), 36634"$Vd32 = vsubuh($Vu32,$Vv32):sat", 36635PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 36636let hasNewValue = 1; 36637let opNewValue = 0; 36638let isPseudo = 1; 36639let isCodeGenOnly = 1; 36640let DecoderNamespace = "EXT_mmvec"; 36641} 36642def V6_vsubuhsat_dv : HInst< 36643(outs HvxWR:$Vdd32), 36644(ins HvxWR:$Vuu32, HvxWR:$Vvv32), 36645"$Vdd32.uh = vsub($Vuu32.uh,$Vvv32.uh):sat", 36646tc_db5555f3, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> { 36647let Inst{7-5} = 0b111; 36648let Inst{13-13} = 0b0; 36649let Inst{31-21} = 0b00011100100; 36650let hasNewValue = 1; 36651let opNewValue = 0; 36652let DecoderNamespace = "EXT_mmvec"; 36653} 36654def V6_vsubuhsat_dv_alt : HInst< 36655(outs HvxWR:$Vdd32), 36656(ins HvxWR:$Vuu32, HvxWR:$Vvv32), 36657"$Vdd32 = vsubuh($Vuu32,$Vvv32):sat", 36658PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 36659let hasNewValue = 1; 36660let opNewValue = 0; 36661let isPseudo = 1; 36662let isCodeGenOnly = 1; 36663let DecoderNamespace = "EXT_mmvec"; 36664} 36665def V6_vsubuhw : HInst< 36666(outs HvxWR:$Vdd32), 36667(ins HvxVR:$Vu32, HvxVR:$Vv32), 36668"$Vdd32.w = vsub($Vu32.uh,$Vv32.uh)", 36669tc_d8287c14, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV60]> { 36670let Inst{7-5} = 0b110; 36671let Inst{13-13} = 0b0; 36672let Inst{31-21} = 0b00011100101; 36673let hasNewValue = 1; 36674let opNewValue = 0; 36675let DecoderNamespace = "EXT_mmvec"; 36676} 36677def V6_vsubuhw_alt : HInst< 36678(outs HvxWR:$Vdd32), 36679(ins HvxVR:$Vu32, HvxVR:$Vv32), 36680"$Vdd32 = vsubuh($Vu32,$Vv32)", 36681PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 36682let hasNewValue = 1; 36683let opNewValue = 0; 36684let isPseudo = 1; 36685let isCodeGenOnly = 1; 36686let DecoderNamespace = "EXT_mmvec"; 36687} 36688def V6_vsubuwsat : HInst< 36689(outs HvxVR:$Vd32), 36690(ins HvxVR:$Vu32, HvxVR:$Vv32), 36691"$Vd32.uw = vsub($Vu32.uw,$Vv32.uw):sat", 36692tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV62]> { 36693let Inst{7-5} = 0b100; 36694let Inst{13-13} = 0b0; 36695let Inst{31-21} = 0b00011111110; 36696let hasNewValue = 1; 36697let opNewValue = 0; 36698let DecoderNamespace = "EXT_mmvec"; 36699} 36700def V6_vsubuwsat_alt : HInst< 36701(outs HvxVR:$Vd32), 36702(ins HvxVR:$Vu32, HvxVR:$Vv32), 36703"$Vd32 = vsubuw($Vu32,$Vv32):sat", 36704PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> { 36705let hasNewValue = 1; 36706let opNewValue = 0; 36707let isPseudo = 1; 36708let isCodeGenOnly = 1; 36709let DecoderNamespace = "EXT_mmvec"; 36710} 36711def V6_vsubuwsat_dv : HInst< 36712(outs HvxWR:$Vdd32), 36713(ins HvxWR:$Vuu32, HvxWR:$Vvv32), 36714"$Vdd32.uw = vsub($Vuu32.uw,$Vvv32.uw):sat", 36715tc_db5555f3, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV62]> { 36716let Inst{7-5} = 0b011; 36717let Inst{13-13} = 0b0; 36718let Inst{31-21} = 0b00011110101; 36719let hasNewValue = 1; 36720let opNewValue = 0; 36721let DecoderNamespace = "EXT_mmvec"; 36722} 36723def V6_vsubuwsat_dv_alt : HInst< 36724(outs HvxWR:$Vdd32), 36725(ins HvxWR:$Vuu32, HvxWR:$Vvv32), 36726"$Vdd32 = vsubuw($Vuu32,$Vvv32):sat", 36727PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> { 36728let hasNewValue = 1; 36729let opNewValue = 0; 36730let isPseudo = 1; 36731let isCodeGenOnly = 1; 36732let DecoderNamespace = "EXT_mmvec"; 36733} 36734def V6_vsubw : HInst< 36735(outs HvxVR:$Vd32), 36736(ins HvxVR:$Vu32, HvxVR:$Vv32), 36737"$Vd32.w = vsub($Vu32.w,$Vv32.w)", 36738tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> { 36739let Inst{7-5} = 0b111; 36740let Inst{13-13} = 0b0; 36741let Inst{31-21} = 0b00011100010; 36742let hasNewValue = 1; 36743let opNewValue = 0; 36744let DecoderNamespace = "EXT_mmvec"; 36745} 36746def V6_vsubw_alt : HInst< 36747(outs HvxVR:$Vd32), 36748(ins HvxVR:$Vu32, HvxVR:$Vv32), 36749"$Vd32 = vsubw($Vu32,$Vv32)", 36750PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 36751let hasNewValue = 1; 36752let opNewValue = 0; 36753let isPseudo = 1; 36754let isCodeGenOnly = 1; 36755let DecoderNamespace = "EXT_mmvec"; 36756} 36757def V6_vsubw_dv : HInst< 36758(outs HvxWR:$Vdd32), 36759(ins HvxWR:$Vuu32, HvxWR:$Vvv32), 36760"$Vdd32.w = vsub($Vuu32.w,$Vvv32.w)", 36761tc_db5555f3, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> { 36762let Inst{7-5} = 0b101; 36763let Inst{13-13} = 0b0; 36764let Inst{31-21} = 0b00011100100; 36765let hasNewValue = 1; 36766let opNewValue = 0; 36767let DecoderNamespace = "EXT_mmvec"; 36768} 36769def V6_vsubw_dv_alt : HInst< 36770(outs HvxWR:$Vdd32), 36771(ins HvxWR:$Vuu32, HvxWR:$Vvv32), 36772"$Vdd32 = vsubw($Vuu32,$Vvv32)", 36773PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 36774let hasNewValue = 1; 36775let opNewValue = 0; 36776let isPseudo = 1; 36777let isCodeGenOnly = 1; 36778let DecoderNamespace = "EXT_mmvec"; 36779} 36780def V6_vsubwnq : HInst< 36781(outs HvxVR:$Vx32), 36782(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32), 36783"if (!$Qv4) $Vx32.w -= $Vu32.w", 36784tc_257f6f7c, TypeCVI_VA>, Enc_a90628, Requires<[UseHVXV60]> { 36785let Inst{7-5} = 0b011; 36786let Inst{13-13} = 0b1; 36787let Inst{21-16} = 0b000010; 36788let Inst{31-24} = 0b00011110; 36789let hasNewValue = 1; 36790let opNewValue = 0; 36791let DecoderNamespace = "EXT_mmvec"; 36792let Constraints = "$Vx32 = $Vx32in"; 36793} 36794def V6_vsubwnq_alt : HInst< 36795(outs HvxVR:$Vx32), 36796(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32), 36797"if (!$Qv4.w) $Vx32.w -= $Vu32.w", 36798PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 36799let hasNewValue = 1; 36800let opNewValue = 0; 36801let isPseudo = 1; 36802let isCodeGenOnly = 1; 36803let DecoderNamespace = "EXT_mmvec"; 36804let Constraints = "$Vx32 = $Vx32in"; 36805} 36806def V6_vsubwq : HInst< 36807(outs HvxVR:$Vx32), 36808(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32), 36809"if ($Qv4) $Vx32.w -= $Vu32.w", 36810tc_257f6f7c, TypeCVI_VA>, Enc_a90628, Requires<[UseHVXV60]> { 36811let Inst{7-5} = 0b000; 36812let Inst{13-13} = 0b1; 36813let Inst{21-16} = 0b000010; 36814let Inst{31-24} = 0b00011110; 36815let hasNewValue = 1; 36816let opNewValue = 0; 36817let DecoderNamespace = "EXT_mmvec"; 36818let Constraints = "$Vx32 = $Vx32in"; 36819} 36820def V6_vsubwq_alt : HInst< 36821(outs HvxVR:$Vx32), 36822(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32), 36823"if ($Qv4.w) $Vx32.w -= $Vu32.w", 36824PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 36825let hasNewValue = 1; 36826let opNewValue = 0; 36827let isPseudo = 1; 36828let isCodeGenOnly = 1; 36829let DecoderNamespace = "EXT_mmvec"; 36830let Constraints = "$Vx32 = $Vx32in"; 36831} 36832def V6_vsubwsat : HInst< 36833(outs HvxVR:$Vd32), 36834(ins HvxVR:$Vu32, HvxVR:$Vv32), 36835"$Vd32.w = vsub($Vu32.w,$Vv32.w):sat", 36836tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> { 36837let Inst{7-5} = 0b011; 36838let Inst{13-13} = 0b0; 36839let Inst{31-21} = 0b00011100011; 36840let hasNewValue = 1; 36841let opNewValue = 0; 36842let DecoderNamespace = "EXT_mmvec"; 36843} 36844def V6_vsubwsat_alt : HInst< 36845(outs HvxVR:$Vd32), 36846(ins HvxVR:$Vu32, HvxVR:$Vv32), 36847"$Vd32 = vsubw($Vu32,$Vv32):sat", 36848PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 36849let hasNewValue = 1; 36850let opNewValue = 0; 36851let isPseudo = 1; 36852let isCodeGenOnly = 1; 36853let DecoderNamespace = "EXT_mmvec"; 36854} 36855def V6_vsubwsat_dv : HInst< 36856(outs HvxWR:$Vdd32), 36857(ins HvxWR:$Vuu32, HvxWR:$Vvv32), 36858"$Vdd32.w = vsub($Vuu32.w,$Vvv32.w):sat", 36859tc_db5555f3, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> { 36860let Inst{7-5} = 0b001; 36861let Inst{13-13} = 0b0; 36862let Inst{31-21} = 0b00011100101; 36863let hasNewValue = 1; 36864let opNewValue = 0; 36865let DecoderNamespace = "EXT_mmvec"; 36866} 36867def V6_vsubwsat_dv_alt : HInst< 36868(outs HvxWR:$Vdd32), 36869(ins HvxWR:$Vuu32, HvxWR:$Vvv32), 36870"$Vdd32 = vsubw($Vuu32,$Vvv32):sat", 36871PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 36872let hasNewValue = 1; 36873let opNewValue = 0; 36874let isPseudo = 1; 36875let isCodeGenOnly = 1; 36876let DecoderNamespace = "EXT_mmvec"; 36877} 36878def V6_vswap : HInst< 36879(outs HvxWR:$Vdd32), 36880(ins HvxQR:$Qt4, HvxVR:$Vu32, HvxVR:$Vv32), 36881"$Vdd32 = vswap($Qt4,$Vu32,$Vv32)", 36882tc_71646d06, TypeCVI_VA_DV>, Enc_3dac0b, Requires<[UseHVXV60]> { 36883let Inst{7-7} = 0b0; 36884let Inst{13-13} = 0b1; 36885let Inst{31-21} = 0b00011110101; 36886let hasNewValue = 1; 36887let opNewValue = 0; 36888let DecoderNamespace = "EXT_mmvec"; 36889} 36890def V6_vtmpyb : HInst< 36891(outs HvxWR:$Vdd32), 36892(ins HvxWR:$Vuu32, IntRegs:$Rt32), 36893"$Vdd32.h = vtmpy($Vuu32.b,$Rt32.b)", 36894tc_0b04c6c7, TypeCVI_VX_DV>, Enc_aad80c, Requires<[UseHVXV60]> { 36895let Inst{7-5} = 0b000; 36896let Inst{13-13} = 0b0; 36897let Inst{31-21} = 0b00011001000; 36898let hasNewValue = 1; 36899let opNewValue = 0; 36900let DecoderNamespace = "EXT_mmvec"; 36901} 36902def V6_vtmpyb_acc : HInst< 36903(outs HvxWR:$Vxx32), 36904(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32), 36905"$Vxx32.h += vtmpy($Vuu32.b,$Rt32.b)", 36906tc_660769f1, TypeCVI_VX_DV>, Enc_d6990d, Requires<[UseHVXV60]> { 36907let Inst{7-5} = 0b000; 36908let Inst{13-13} = 0b1; 36909let Inst{31-21} = 0b00011001000; 36910let hasNewValue = 1; 36911let opNewValue = 0; 36912let isAccumulator = 1; 36913let DecoderNamespace = "EXT_mmvec"; 36914let Constraints = "$Vxx32 = $Vxx32in"; 36915} 36916def V6_vtmpyb_acc_alt : HInst< 36917(outs HvxWR:$Vxx32), 36918(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32), 36919"$Vxx32 += vtmpyb($Vuu32,$Rt32)", 36920PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 36921let hasNewValue = 1; 36922let opNewValue = 0; 36923let isAccumulator = 1; 36924let isPseudo = 1; 36925let isCodeGenOnly = 1; 36926let DecoderNamespace = "EXT_mmvec"; 36927let Constraints = "$Vxx32 = $Vxx32in"; 36928} 36929def V6_vtmpyb_alt : HInst< 36930(outs HvxWR:$Vdd32), 36931(ins HvxWR:$Vuu32, IntRegs:$Rt32), 36932"$Vdd32 = vtmpyb($Vuu32,$Rt32)", 36933PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 36934let hasNewValue = 1; 36935let opNewValue = 0; 36936let isPseudo = 1; 36937let isCodeGenOnly = 1; 36938let DecoderNamespace = "EXT_mmvec"; 36939} 36940def V6_vtmpybus : HInst< 36941(outs HvxWR:$Vdd32), 36942(ins HvxWR:$Vuu32, IntRegs:$Rt32), 36943"$Vdd32.h = vtmpy($Vuu32.ub,$Rt32.b)", 36944tc_0b04c6c7, TypeCVI_VX_DV>, Enc_aad80c, Requires<[UseHVXV60]> { 36945let Inst{7-5} = 0b001; 36946let Inst{13-13} = 0b0; 36947let Inst{31-21} = 0b00011001000; 36948let hasNewValue = 1; 36949let opNewValue = 0; 36950let DecoderNamespace = "EXT_mmvec"; 36951} 36952def V6_vtmpybus_acc : HInst< 36953(outs HvxWR:$Vxx32), 36954(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32), 36955"$Vxx32.h += vtmpy($Vuu32.ub,$Rt32.b)", 36956tc_660769f1, TypeCVI_VX_DV>, Enc_d6990d, Requires<[UseHVXV60]> { 36957let Inst{7-5} = 0b001; 36958let Inst{13-13} = 0b1; 36959let Inst{31-21} = 0b00011001000; 36960let hasNewValue = 1; 36961let opNewValue = 0; 36962let isAccumulator = 1; 36963let DecoderNamespace = "EXT_mmvec"; 36964let Constraints = "$Vxx32 = $Vxx32in"; 36965} 36966def V6_vtmpybus_acc_alt : HInst< 36967(outs HvxWR:$Vxx32), 36968(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32), 36969"$Vxx32 += vtmpybus($Vuu32,$Rt32)", 36970PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 36971let hasNewValue = 1; 36972let opNewValue = 0; 36973let isAccumulator = 1; 36974let isPseudo = 1; 36975let isCodeGenOnly = 1; 36976let DecoderNamespace = "EXT_mmvec"; 36977let Constraints = "$Vxx32 = $Vxx32in"; 36978} 36979def V6_vtmpybus_alt : HInst< 36980(outs HvxWR:$Vdd32), 36981(ins HvxWR:$Vuu32, IntRegs:$Rt32), 36982"$Vdd32 = vtmpybus($Vuu32,$Rt32)", 36983PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 36984let hasNewValue = 1; 36985let opNewValue = 0; 36986let isPseudo = 1; 36987let isCodeGenOnly = 1; 36988let DecoderNamespace = "EXT_mmvec"; 36989} 36990def V6_vtmpyhb : HInst< 36991(outs HvxWR:$Vdd32), 36992(ins HvxWR:$Vuu32, IntRegs:$Rt32), 36993"$Vdd32.w = vtmpy($Vuu32.h,$Rt32.b)", 36994tc_0b04c6c7, TypeCVI_VX_DV>, Enc_aad80c, Requires<[UseHVXV60]> { 36995let Inst{7-5} = 0b100; 36996let Inst{13-13} = 0b0; 36997let Inst{31-21} = 0b00011001101; 36998let hasNewValue = 1; 36999let opNewValue = 0; 37000let DecoderNamespace = "EXT_mmvec"; 37001} 37002def V6_vtmpyhb_acc : HInst< 37003(outs HvxWR:$Vxx32), 37004(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32), 37005"$Vxx32.w += vtmpy($Vuu32.h,$Rt32.b)", 37006tc_660769f1, TypeCVI_VX_DV>, Enc_d6990d, Requires<[UseHVXV60]> { 37007let Inst{7-5} = 0b010; 37008let Inst{13-13} = 0b1; 37009let Inst{31-21} = 0b00011001000; 37010let hasNewValue = 1; 37011let opNewValue = 0; 37012let isAccumulator = 1; 37013let DecoderNamespace = "EXT_mmvec"; 37014let Constraints = "$Vxx32 = $Vxx32in"; 37015} 37016def V6_vtmpyhb_acc_alt : HInst< 37017(outs HvxWR:$Vxx32), 37018(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32), 37019"$Vxx32 += vtmpyhb($Vuu32,$Rt32)", 37020PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 37021let hasNewValue = 1; 37022let opNewValue = 0; 37023let isAccumulator = 1; 37024let isPseudo = 1; 37025let isCodeGenOnly = 1; 37026let DecoderNamespace = "EXT_mmvec"; 37027let Constraints = "$Vxx32 = $Vxx32in"; 37028} 37029def V6_vtmpyhb_alt : HInst< 37030(outs HvxWR:$Vdd32), 37031(ins HvxWR:$Vuu32, IntRegs:$Rt32), 37032"$Vdd32 = vtmpyhb($Vuu32,$Rt32)", 37033PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 37034let hasNewValue = 1; 37035let opNewValue = 0; 37036let isPseudo = 1; 37037let isCodeGenOnly = 1; 37038let DecoderNamespace = "EXT_mmvec"; 37039} 37040def V6_vtran2x2_map : HInst< 37041(outs HvxVR:$Vy32, HvxVR:$Vx32), 37042(ins HvxVR:$Vy32in, HvxVR:$Vx32in, IntRegs:$Rt32), 37043"vtrans2x2($Vy32,$Vx32,$Rt32)", 37044PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 37045let hasNewValue = 1; 37046let opNewValue = 0; 37047let hasNewValue2 = 1; 37048let opNewValue2 = 1; 37049let isPseudo = 1; 37050let isCodeGenOnly = 1; 37051let DecoderNamespace = "EXT_mmvec"; 37052let Constraints = "$Vy32 = $Vy32in, $Vx32 = $Vx32in"; 37053} 37054def V6_vunpackb : HInst< 37055(outs HvxWR:$Vdd32), 37056(ins HvxVR:$Vu32), 37057"$Vdd32.h = vunpack($Vu32.b)", 37058tc_04da405a, TypeCVI_VP_VS>, Enc_dd766a, Requires<[UseHVXV60]> { 37059let Inst{7-5} = 0b010; 37060let Inst{13-13} = 0b0; 37061let Inst{31-16} = 0b0001111000000001; 37062let hasNewValue = 1; 37063let opNewValue = 0; 37064let DecoderNamespace = "EXT_mmvec"; 37065} 37066def V6_vunpackb_alt : HInst< 37067(outs HvxWR:$Vdd32), 37068(ins HvxVR:$Vu32), 37069"$Vdd32 = vunpackb($Vu32)", 37070PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 37071let hasNewValue = 1; 37072let opNewValue = 0; 37073let isPseudo = 1; 37074let isCodeGenOnly = 1; 37075let DecoderNamespace = "EXT_mmvec"; 37076} 37077def V6_vunpackh : HInst< 37078(outs HvxWR:$Vdd32), 37079(ins HvxVR:$Vu32), 37080"$Vdd32.w = vunpack($Vu32.h)", 37081tc_04da405a, TypeCVI_VP_VS>, Enc_dd766a, Requires<[UseHVXV60]> { 37082let Inst{7-5} = 0b011; 37083let Inst{13-13} = 0b0; 37084let Inst{31-16} = 0b0001111000000001; 37085let hasNewValue = 1; 37086let opNewValue = 0; 37087let DecoderNamespace = "EXT_mmvec"; 37088} 37089def V6_vunpackh_alt : HInst< 37090(outs HvxWR:$Vdd32), 37091(ins HvxVR:$Vu32), 37092"$Vdd32 = vunpackh($Vu32)", 37093PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 37094let hasNewValue = 1; 37095let opNewValue = 0; 37096let isPseudo = 1; 37097let isCodeGenOnly = 1; 37098let DecoderNamespace = "EXT_mmvec"; 37099} 37100def V6_vunpackob : HInst< 37101(outs HvxWR:$Vxx32), 37102(ins HvxWR:$Vxx32in, HvxVR:$Vu32), 37103"$Vxx32.h |= vunpacko($Vu32.b)", 37104tc_2c745bb8, TypeCVI_VP_VS>, Enc_500cb0, Requires<[UseHVXV60]> { 37105let Inst{7-5} = 0b000; 37106let Inst{13-13} = 0b1; 37107let Inst{31-16} = 0b0001111000000000; 37108let hasNewValue = 1; 37109let opNewValue = 0; 37110let isAccumulator = 1; 37111let DecoderNamespace = "EXT_mmvec"; 37112let Constraints = "$Vxx32 = $Vxx32in"; 37113} 37114def V6_vunpackob_alt : HInst< 37115(outs HvxWR:$Vxx32), 37116(ins HvxWR:$Vxx32in, HvxVR:$Vu32), 37117"$Vxx32 |= vunpackob($Vu32)", 37118PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 37119let hasNewValue = 1; 37120let opNewValue = 0; 37121let isAccumulator = 1; 37122let isPseudo = 1; 37123let DecoderNamespace = "EXT_mmvec"; 37124let Constraints = "$Vxx32 = $Vxx32in"; 37125} 37126def V6_vunpackoh : HInst< 37127(outs HvxWR:$Vxx32), 37128(ins HvxWR:$Vxx32in, HvxVR:$Vu32), 37129"$Vxx32.w |= vunpacko($Vu32.h)", 37130tc_2c745bb8, TypeCVI_VP_VS>, Enc_500cb0, Requires<[UseHVXV60]> { 37131let Inst{7-5} = 0b001; 37132let Inst{13-13} = 0b1; 37133let Inst{31-16} = 0b0001111000000000; 37134let hasNewValue = 1; 37135let opNewValue = 0; 37136let isAccumulator = 1; 37137let DecoderNamespace = "EXT_mmvec"; 37138let Constraints = "$Vxx32 = $Vxx32in"; 37139} 37140def V6_vunpackoh_alt : HInst< 37141(outs HvxWR:$Vxx32), 37142(ins HvxWR:$Vxx32in, HvxVR:$Vu32), 37143"$Vxx32 |= vunpackoh($Vu32)", 37144PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 37145let hasNewValue = 1; 37146let opNewValue = 0; 37147let isAccumulator = 1; 37148let isPseudo = 1; 37149let isCodeGenOnly = 1; 37150let DecoderNamespace = "EXT_mmvec"; 37151let Constraints = "$Vxx32 = $Vxx32in"; 37152} 37153def V6_vunpackub : HInst< 37154(outs HvxWR:$Vdd32), 37155(ins HvxVR:$Vu32), 37156"$Vdd32.uh = vunpack($Vu32.ub)", 37157tc_04da405a, TypeCVI_VP_VS>, Enc_dd766a, Requires<[UseHVXV60]> { 37158let Inst{7-5} = 0b000; 37159let Inst{13-13} = 0b0; 37160let Inst{31-16} = 0b0001111000000001; 37161let hasNewValue = 1; 37162let opNewValue = 0; 37163let DecoderNamespace = "EXT_mmvec"; 37164} 37165def V6_vunpackub_alt : HInst< 37166(outs HvxWR:$Vdd32), 37167(ins HvxVR:$Vu32), 37168"$Vdd32 = vunpackub($Vu32)", 37169PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 37170let hasNewValue = 1; 37171let opNewValue = 0; 37172let isPseudo = 1; 37173let isCodeGenOnly = 1; 37174let DecoderNamespace = "EXT_mmvec"; 37175} 37176def V6_vunpackuh : HInst< 37177(outs HvxWR:$Vdd32), 37178(ins HvxVR:$Vu32), 37179"$Vdd32.uw = vunpack($Vu32.uh)", 37180tc_04da405a, TypeCVI_VP_VS>, Enc_dd766a, Requires<[UseHVXV60]> { 37181let Inst{7-5} = 0b001; 37182let Inst{13-13} = 0b0; 37183let Inst{31-16} = 0b0001111000000001; 37184let hasNewValue = 1; 37185let opNewValue = 0; 37186let DecoderNamespace = "EXT_mmvec"; 37187} 37188def V6_vunpackuh_alt : HInst< 37189(outs HvxWR:$Vdd32), 37190(ins HvxVR:$Vu32), 37191"$Vdd32 = vunpackuh($Vu32)", 37192PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 37193let hasNewValue = 1; 37194let opNewValue = 0; 37195let isPseudo = 1; 37196let isCodeGenOnly = 1; 37197let DecoderNamespace = "EXT_mmvec"; 37198} 37199def V6_vwhist128 : HInst< 37200(outs), 37201(ins), 37202"vwhist128", 37203tc_1381a97c, TypeCVI_HIST>, Enc_e3b0c4, Requires<[UseHVXV62]> { 37204let Inst{13-0} = 0b10010010000000; 37205let Inst{31-16} = 0b0001111000000000; 37206let DecoderNamespace = "EXT_mmvec"; 37207} 37208def V6_vwhist128m : HInst< 37209(outs), 37210(ins u1_0Imm:$Ii), 37211"vwhist128(#$Ii)", 37212tc_b28e51aa, TypeCVI_HIST>, Enc_efaed8, Requires<[UseHVXV62]> { 37213let Inst{7-0} = 0b10000000; 37214let Inst{13-9} = 0b10011; 37215let Inst{31-16} = 0b0001111000000000; 37216let DecoderNamespace = "EXT_mmvec"; 37217} 37218def V6_vwhist128q : HInst< 37219(outs), 37220(ins HvxQR:$Qv4), 37221"vwhist128($Qv4)", 37222tc_e3f68a46, TypeCVI_HIST>, Enc_217147, Requires<[UseHVXV62]> { 37223let Inst{13-0} = 0b10010010000000; 37224let Inst{21-16} = 0b000010; 37225let Inst{31-24} = 0b00011110; 37226let DecoderNamespace = "EXT_mmvec"; 37227} 37228def V6_vwhist128qm : HInst< 37229(outs), 37230(ins HvxQR:$Qv4, u1_0Imm:$Ii), 37231"vwhist128($Qv4,#$Ii)", 37232tc_767c4e9d, TypeCVI_HIST>, Enc_802dc0, Requires<[UseHVXV62]> { 37233let Inst{7-0} = 0b10000000; 37234let Inst{13-9} = 0b10011; 37235let Inst{21-16} = 0b000010; 37236let Inst{31-24} = 0b00011110; 37237let DecoderNamespace = "EXT_mmvec"; 37238} 37239def V6_vwhist256 : HInst< 37240(outs), 37241(ins), 37242"vwhist256", 37243tc_1381a97c, TypeCVI_HIST>, Enc_e3b0c4, Requires<[UseHVXV62]> { 37244let Inst{13-0} = 0b10001010000000; 37245let Inst{31-16} = 0b0001111000000000; 37246let DecoderNamespace = "EXT_mmvec"; 37247} 37248def V6_vwhist256_sat : HInst< 37249(outs), 37250(ins), 37251"vwhist256:sat", 37252tc_1381a97c, TypeCVI_HIST>, Enc_e3b0c4, Requires<[UseHVXV62]> { 37253let Inst{13-0} = 0b10001110000000; 37254let Inst{31-16} = 0b0001111000000000; 37255let DecoderNamespace = "EXT_mmvec"; 37256} 37257def V6_vwhist256q : HInst< 37258(outs), 37259(ins HvxQR:$Qv4), 37260"vwhist256($Qv4)", 37261tc_e3f68a46, TypeCVI_HIST>, Enc_217147, Requires<[UseHVXV62]> { 37262let Inst{13-0} = 0b10001010000000; 37263let Inst{21-16} = 0b000010; 37264let Inst{31-24} = 0b00011110; 37265let DecoderNamespace = "EXT_mmvec"; 37266} 37267def V6_vwhist256q_sat : HInst< 37268(outs), 37269(ins HvxQR:$Qv4), 37270"vwhist256($Qv4):sat", 37271tc_e3f68a46, TypeCVI_HIST>, Enc_217147, Requires<[UseHVXV62]> { 37272let Inst{13-0} = 0b10001110000000; 37273let Inst{21-16} = 0b000010; 37274let Inst{31-24} = 0b00011110; 37275let DecoderNamespace = "EXT_mmvec"; 37276} 37277def V6_vxor : HInst< 37278(outs HvxVR:$Vd32), 37279(ins HvxVR:$Vu32, HvxVR:$Vv32), 37280"$Vd32 = vxor($Vu32,$Vv32)", 37281tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> { 37282let Inst{7-5} = 0b111; 37283let Inst{13-13} = 0b0; 37284let Inst{31-21} = 0b00011100001; 37285let hasNewValue = 1; 37286let opNewValue = 0; 37287let DecoderNamespace = "EXT_mmvec"; 37288} 37289def V6_vzb : HInst< 37290(outs HvxWR:$Vdd32), 37291(ins HvxVR:$Vu32), 37292"$Vdd32.uh = vzxt($Vu32.ub)", 37293tc_b4416217, TypeCVI_VA_DV>, Enc_dd766a, Requires<[UseHVXV60]> { 37294let Inst{7-5} = 0b001; 37295let Inst{13-13} = 0b0; 37296let Inst{31-16} = 0b0001111000000010; 37297let hasNewValue = 1; 37298let opNewValue = 0; 37299let DecoderNamespace = "EXT_mmvec"; 37300} 37301def V6_vzb_alt : HInst< 37302(outs HvxWR:$Vdd32), 37303(ins HvxVR:$Vu32), 37304"$Vdd32 = vzxtb($Vu32)", 37305PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 37306let hasNewValue = 1; 37307let opNewValue = 0; 37308let isPseudo = 1; 37309let isCodeGenOnly = 1; 37310let DecoderNamespace = "EXT_mmvec"; 37311} 37312def V6_vzh : HInst< 37313(outs HvxWR:$Vdd32), 37314(ins HvxVR:$Vu32), 37315"$Vdd32.uw = vzxt($Vu32.uh)", 37316tc_b4416217, TypeCVI_VA_DV>, Enc_dd766a, Requires<[UseHVXV60]> { 37317let Inst{7-5} = 0b010; 37318let Inst{13-13} = 0b0; 37319let Inst{31-16} = 0b0001111000000010; 37320let hasNewValue = 1; 37321let opNewValue = 0; 37322let DecoderNamespace = "EXT_mmvec"; 37323} 37324def V6_vzh_alt : HInst< 37325(outs HvxWR:$Vdd32), 37326(ins HvxVR:$Vu32), 37327"$Vdd32 = vzxth($Vu32)", 37328PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { 37329let hasNewValue = 1; 37330let opNewValue = 0; 37331let isPseudo = 1; 37332let isCodeGenOnly = 1; 37333let DecoderNamespace = "EXT_mmvec"; 37334} 37335def V6_zLd_ai : HInst< 37336(outs), 37337(ins IntRegs:$Rt32, s4_0Imm:$Ii), 37338"z = vmem($Rt32+#$Ii)", 37339tc_e699ae41, TypeCVI_ZW>, Enc_ff3442, Requires<[UseHVXV66,UseZReg]> { 37340let Inst{7-0} = 0b00000000; 37341let Inst{12-11} = 0b00; 37342let Inst{31-21} = 0b00101100000; 37343let addrMode = BaseImmOffset; 37344let mayLoad = 1; 37345let isRestrictNoSlot1Store = 1; 37346let DecoderNamespace = "EXT_mmvec"; 37347} 37348def V6_zLd_pi : HInst< 37349(outs IntRegs:$Rx32), 37350(ins IntRegs:$Rx32in, s3_0Imm:$Ii), 37351"z = vmem($Rx32++#$Ii)", 37352tc_a0dbea28, TypeCVI_ZW>, Enc_6c9ee0, Requires<[UseHVXV66,UseZReg]> { 37353let Inst{7-0} = 0b00000000; 37354let Inst{13-11} = 0b000; 37355let Inst{31-21} = 0b00101101000; 37356let addrMode = PostInc; 37357let mayLoad = 1; 37358let isRestrictNoSlot1Store = 1; 37359let DecoderNamespace = "EXT_mmvec"; 37360let Constraints = "$Rx32 = $Rx32in"; 37361} 37362def V6_zLd_ppu : HInst< 37363(outs IntRegs:$Rx32), 37364(ins IntRegs:$Rx32in, ModRegs:$Mu2), 37365"z = vmem($Rx32++$Mu2)", 37366tc_a0dbea28, TypeCVI_ZW>, Enc_44661f, Requires<[UseHVXV66,UseZReg]> { 37367let Inst{12-0} = 0b0000000000001; 37368let Inst{31-21} = 0b00101101000; 37369let addrMode = PostInc; 37370let mayLoad = 1; 37371let isRestrictNoSlot1Store = 1; 37372let DecoderNamespace = "EXT_mmvec"; 37373let Constraints = "$Rx32 = $Rx32in"; 37374} 37375def V6_zLd_pred_ai : HInst< 37376(outs), 37377(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii), 37378"if ($Pv4) z = vmem($Rt32+#$Ii)", 37379tc_dd5b0695, TypeCVI_ZW>, Enc_ef601b, Requires<[UseHVXV66,UseZReg]> { 37380let Inst{7-0} = 0b00000000; 37381let Inst{31-21} = 0b00101100100; 37382let isPredicated = 1; 37383let addrMode = BaseImmOffset; 37384let mayLoad = 1; 37385let isRestrictNoSlot1Store = 1; 37386let DecoderNamespace = "EXT_mmvec"; 37387} 37388def V6_zLd_pred_pi : HInst< 37389(outs IntRegs:$Rx32), 37390(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii), 37391"if ($Pv4) z = vmem($Rx32++#$Ii)", 37392tc_3ad719fb, TypeCVI_ZW>, Enc_6baed4, Requires<[UseHVXV66,UseZReg]> { 37393let Inst{7-0} = 0b00000000; 37394let Inst{13-13} = 0b0; 37395let Inst{31-21} = 0b00101101100; 37396let isPredicated = 1; 37397let addrMode = PostInc; 37398let mayLoad = 1; 37399let isRestrictNoSlot1Store = 1; 37400let DecoderNamespace = "EXT_mmvec"; 37401let Constraints = "$Rx32 = $Rx32in"; 37402} 37403def V6_zLd_pred_ppu : HInst< 37404(outs IntRegs:$Rx32), 37405(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2), 37406"if ($Pv4) z = vmem($Rx32++$Mu2)", 37407tc_3ad719fb, TypeCVI_ZW>, Enc_691712, Requires<[UseHVXV66,UseZReg]> { 37408let Inst{10-0} = 0b00000000001; 37409let Inst{31-21} = 0b00101101100; 37410let isPredicated = 1; 37411let addrMode = PostInc; 37412let mayLoad = 1; 37413let isRestrictNoSlot1Store = 1; 37414let DecoderNamespace = "EXT_mmvec"; 37415let Constraints = "$Rx32 = $Rx32in"; 37416} 37417def V6_zextract : HInst< 37418(outs HvxVR:$Vd32), 37419(ins IntRegs:$Rt32), 37420"$Vd32 = zextract($Rt32)", 37421tc_5bf8afbb, TypeCVI_VP>, Enc_a5ed8a, Requires<[UseHVXV66,UseZReg]> { 37422let Inst{13-5} = 0b000001001; 37423let Inst{31-21} = 0b00011001101; 37424let hasNewValue = 1; 37425let opNewValue = 0; 37426let DecoderNamespace = "EXT_mmvec"; 37427} 37428def V6_zld0 : HInst< 37429(outs), 37430(ins IntRegs:$Rt32), 37431"z = vmem($Rt32)", 37432PSEUDO, TypeMAPPING>, Requires<[UseHVXV66]> { 37433let isPseudo = 1; 37434let isCodeGenOnly = 1; 37435let DecoderNamespace = "EXT_mmvec"; 37436} 37437def V6_zldp0 : HInst< 37438(outs), 37439(ins PredRegs:$Pv4, IntRegs:$Rt32), 37440"if ($Pv4) z = vmem($Rt32)", 37441PSEUDO, TypeMAPPING>, Requires<[UseHVXV66]> { 37442let isPseudo = 1; 37443let isCodeGenOnly = 1; 37444let DecoderNamespace = "EXT_mmvec"; 37445} 37446def Y2_barrier : HInst< 37447(outs), 37448(ins), 37449"barrier", 37450tc_8c99de45, TypeST>, Enc_e3b0c4 { 37451let Inst{13-0} = 0b00000000000000; 37452let Inst{31-16} = 0b1010100000000000; 37453let isSoloAX = 1; 37454let hasSideEffects = 1; 37455} 37456def Y2_break : HInst< 37457(outs), 37458(ins), 37459"brkpt", 37460tc_9ad9998f, TypeCR>, Enc_e3b0c4 { 37461let Inst{13-0} = 0b00000000000000; 37462let Inst{31-16} = 0b0110110000100000; 37463let isSolo = 1; 37464} 37465def Y2_dccleana : HInst< 37466(outs), 37467(ins IntRegs:$Rs32), 37468"dccleana($Rs32)", 37469tc_b857bf4e, TypeST>, Enc_ecbcc8 { 37470let Inst{13-0} = 0b00000000000000; 37471let Inst{31-21} = 0b10100000000; 37472let isRestrictSlot1AOK = 1; 37473let hasSideEffects = 1; 37474} 37475def Y2_dccleaninva : HInst< 37476(outs), 37477(ins IntRegs:$Rs32), 37478"dccleaninva($Rs32)", 37479tc_b857bf4e, TypeST>, Enc_ecbcc8 { 37480let Inst{13-0} = 0b00000000000000; 37481let Inst{31-21} = 0b10100000010; 37482let isRestrictSlot1AOK = 1; 37483let hasSideEffects = 1; 37484} 37485def Y2_dcfetch : HInst< 37486(outs), 37487(ins IntRegs:$Rs32), 37488"dcfetch($Rs32)", 37489tc_d63f638c, TypeMAPPING> { 37490let hasSideEffects = 1; 37491let isPseudo = 1; 37492let isCodeGenOnly = 1; 37493} 37494def Y2_dcfetchbo : HInst< 37495(outs), 37496(ins IntRegs:$Rs32, u11_3Imm:$Ii), 37497"dcfetch($Rs32+#$Ii)", 37498tc_9ca930f7, TypeLD>, Enc_2d829e { 37499let Inst{13-11} = 0b000; 37500let Inst{31-21} = 0b10010100000; 37501let addrMode = BaseImmOffset; 37502let isRestrictNoSlot1Store = 1; 37503let hasSideEffects = 1; 37504} 37505def Y2_dcinva : HInst< 37506(outs), 37507(ins IntRegs:$Rs32), 37508"dcinva($Rs32)", 37509tc_b857bf4e, TypeST>, Enc_ecbcc8 { 37510let Inst{13-0} = 0b00000000000000; 37511let Inst{31-21} = 0b10100000001; 37512let isRestrictSlot1AOK = 1; 37513let hasSideEffects = 1; 37514} 37515def Y2_dczeroa : HInst< 37516(outs), 37517(ins IntRegs:$Rs32), 37518"dczeroa($Rs32)", 37519tc_b857bf4e, TypeST>, Enc_ecbcc8 { 37520let Inst{13-0} = 0b00000000000000; 37521let Inst{31-21} = 0b10100000110; 37522let isRestrictSlot1AOK = 1; 37523let mayStore = 1; 37524let hasSideEffects = 1; 37525} 37526def Y2_icinva : HInst< 37527(outs), 37528(ins IntRegs:$Rs32), 37529"icinva($Rs32)", 37530tc_5d7f5414, TypeJ>, Enc_ecbcc8 { 37531let Inst{13-0} = 0b00000000000000; 37532let Inst{31-21} = 0b01010110110; 37533let isSolo = 1; 37534} 37535def Y2_isync : HInst< 37536(outs), 37537(ins), 37538"isync", 37539tc_8b121f4a, TypeJ>, Enc_e3b0c4 { 37540let Inst{13-0} = 0b00000000000010; 37541let Inst{31-16} = 0b0101011111000000; 37542let isSolo = 1; 37543} 37544def Y2_syncht : HInst< 37545(outs), 37546(ins), 37547"syncht", 37548tc_8c99de45, TypeST>, Enc_e3b0c4 { 37549let Inst{13-0} = 0b00000000000000; 37550let Inst{31-16} = 0b1010100001000000; 37551let isSolo = 1; 37552} 37553def Y2_wait : HInst< 37554(outs), 37555(ins IntRegs:$Rs32), 37556"wait($Rs32)", 37557tc_174516e8, TypeCR>, Enc_ecbcc8, Requires<[HasV65]> { 37558let Inst{13-0} = 0b00000000000000; 37559let Inst{31-21} = 0b01100100010; 37560let isSolo = 1; 37561} 37562def Y4_l2fetch : HInst< 37563(outs), 37564(ins IntRegs:$Rs32, IntRegs:$Rt32), 37565"l2fetch($Rs32,$Rt32)", 37566tc_fe211424, TypeST>, Enc_ca3887 { 37567let Inst{7-0} = 0b00000000; 37568let Inst{13-13} = 0b0; 37569let Inst{31-21} = 0b10100110000; 37570let isSoloAX = 1; 37571let mayStore = 1; 37572let hasSideEffects = 1; 37573} 37574def Y4_trace : HInst< 37575(outs), 37576(ins IntRegs:$Rs32), 37577"trace($Rs32)", 37578tc_6b25e783, TypeCR>, Enc_ecbcc8 { 37579let Inst{13-0} = 0b00000000000000; 37580let Inst{31-21} = 0b01100010010; 37581let isSoloAX = 1; 37582} 37583def Y5_l2fetch : HInst< 37584(outs), 37585(ins IntRegs:$Rs32, DoubleRegs:$Rtt32), 37586"l2fetch($Rs32,$Rtt32)", 37587tc_fe211424, TypeST>, Enc_e6abcf { 37588let Inst{7-0} = 0b00000000; 37589let Inst{13-13} = 0b0; 37590let Inst{31-21} = 0b10100110100; 37591let isSoloAX = 1; 37592let mayStore = 1; 37593let hasSideEffects = 1; 37594} 37595def dep_A2_addsat : HInst< 37596(outs IntRegs:$Rd32), 37597(ins IntRegs:$Rs32, IntRegs:$Rt32), 37598"$Rd32 = add($Rs32,$Rt32):sat:deprecated", 37599tc_779080bf, TypeALU64>, Enc_5ab2be { 37600let Inst{7-5} = 0b000; 37601let Inst{13-13} = 0b0; 37602let Inst{31-21} = 0b11010101100; 37603let hasNewValue = 1; 37604let opNewValue = 0; 37605let prefersSlot3 = 1; 37606let Defs = [USR_OVF]; 37607} 37608def dep_A2_subsat : HInst< 37609(outs IntRegs:$Rd32), 37610(ins IntRegs:$Rt32, IntRegs:$Rs32), 37611"$Rd32 = sub($Rt32,$Rs32):sat:deprecated", 37612tc_779080bf, TypeALU64>, Enc_bd6011 { 37613let Inst{7-5} = 0b100; 37614let Inst{13-13} = 0b0; 37615let Inst{31-21} = 0b11010101100; 37616let hasNewValue = 1; 37617let opNewValue = 0; 37618let prefersSlot3 = 1; 37619let Defs = [USR_OVF]; 37620} 37621def dep_S2_packhl : HInst< 37622(outs DoubleRegs:$Rdd32), 37623(ins IntRegs:$Rs32, IntRegs:$Rt32), 37624"$Rdd32 = packhl($Rs32,$Rt32):deprecated", 37625tc_946df596, TypeALU64>, Enc_be32a5 { 37626let Inst{7-5} = 0b000; 37627let Inst{13-13} = 0b0; 37628let Inst{31-21} = 0b11010100000; 37629} 37630