1; RUN: llc < %s -mtriple=thumbv7-apple-ios -mcpu=cortex-a8 -regalloc=fast -optimize-regalloc=0 -verify-machineinstrs | FileCheck %s -check-prefix=A8 -check-prefix=CHECK -check-prefix=NORMAL 2; RUN: llc < %s -mtriple=thumbv7-apple-ios -mcpu=cortex-m3 -regalloc=fast -optimize-regalloc=0 | FileCheck %s -check-prefix=M3 -check-prefix=CHECK -check-prefix=NORMAL 3; rdar://6949835 4; RUN: llc < %s -mtriple=thumbv7-apple-ios -mcpu=cortex-a8 -regalloc=basic | FileCheck %s -check-prefix=BASIC -check-prefix=CHECK -check-prefix=NORMAL 5; RUN: llc < %s -mtriple=thumbv7-apple-ios -mcpu=cortex-a8 -regalloc=greedy | FileCheck %s -check-prefix=GREEDY -check-prefix=CHECK -check-prefix=NORMAL 6; RUN: llc < %s -mtriple=thumbv7-apple-ios -mcpu=swift | FileCheck %s -check-prefix=CHECK -check-prefix=NORMAL 7 8; RUN: llc < %s -mtriple=thumbv7-apple-ios -arm-assume-misaligned-load-store | FileCheck %s -check-prefix=CHECK -check-prefix=CONSERVATIVE 9 10; Magic ARM pair hints works best with linearscan / fast. 11 12@b = external global i64* 13 14; We use the following two to force values into specific registers. 15declare i64* @get_ptr() 16declare void @use_i64(i64 %v) 17 18define void @test_ldrd(i64 %a) nounwind readonly "no-frame-pointer-elim"="true" { 19; CHECK-LABEL: test_ldrd: 20; NORMAL: bl{{x?}} _get_ptr 21; A8: ldrd r0, r1, [r0] 22; Cortex-M3 errata 602117: LDRD with base in list may result in incorrect base 23; register when interrupted or faulted. 24; M3-NOT: ldrd r[[REGNUM:[0-9]+]], {{r[0-9]+}}, [r[[REGNUM]]] 25; CONSERVATIVE-NOT: ldrd 26; NORMAL: bl{{x?}} _use_i64 27 %ptr = call i64* @get_ptr() 28 %v = load i64, i64* %ptr, align 8 29 call void @use_i64(i64 %v) 30 ret void 31} 32 33; rdar://10435045 mixed LDRi8/LDRi12 34; 35; In this case, LSR generate a sequence of LDRi8/LDRi12. We should be 36; able to generate an LDRD pair here, but this is highly sensitive to 37; regalloc hinting. So, this doubles as a register allocation 38; test. RABasic currently does a better job within the inner loop 39; because of its *lack* of hinting ability. Whereas RAGreedy keeps 40; R0/R1/R2 live as the three arguments, forcing the LDRD's odd 41; destination into R3. We then sensibly split LDRD again rather then 42; evict another live range or use callee saved regs. Sorry if the test 43; is sensitive to Regalloc changes, but it is an interesting case. 44; 45; CHECK-LABEL: f: 46; BASIC: %bb 47; BASIC: ldrd 48; BASIC: str 49; GREEDY: %bb 50; GREEDY: ldrd 51; GREEDY: str 52define void @f(i32* nocapture %a, i32* nocapture %b, i32 %n) nounwind "no-frame-pointer-elim"="true" { 53entry: 54 %0 = add nsw i32 %n, -1 ; <i32> [#uses=2] 55 %1 = icmp sgt i32 %0, 0 ; <i1> [#uses=1] 56 br i1 %1, label %bb, label %return 57 58bb: ; preds = %bb, %entry 59 %i.03 = phi i32 [ %tmp, %bb ], [ 0, %entry ] ; <i32> [#uses=3] 60 %scevgep = getelementptr i32, i32* %a, i32 %i.03 ; <i32*> [#uses=1] 61 %scevgep4 = getelementptr i32, i32* %b, i32 %i.03 ; <i32*> [#uses=1] 62 %tmp = add i32 %i.03, 1 ; <i32> [#uses=3] 63 %scevgep5 = getelementptr i32, i32* %a, i32 %tmp ; <i32*> [#uses=1] 64 %2 = load i32, i32* %scevgep, align 4 ; <i32> [#uses=1] 65 %3 = load i32, i32* %scevgep5, align 4 ; <i32> [#uses=1] 66 %4 = add nsw i32 %3, %2 ; <i32> [#uses=1] 67 store i32 %4, i32* %scevgep4, align 4 68 %exitcond = icmp eq i32 %tmp, %0 ; <i1> [#uses=1] 69 br i1 %exitcond, label %return, label %bb 70 71return: ; preds = %bb, %entry 72 ret void 73} 74 75; rdar://13978317 76; Pair of loads not formed when lifetime markers are set. 77%struct.Test = type { i32, i32, i32 } 78 79@TestVar = external global %struct.Test 80 81; CHECK-LABEL: Func1: 82define void @Func1() nounwind ssp "no-frame-pointer-elim"="true" { 83entry: 84; A8: movw [[BASE:r[0-9]+]], :lower16:{{.*}}TestVar{{.*}} 85; A8: movt [[BASE]], :upper16:{{.*}}TestVar{{.*}} 86; A8: ldrd [[FIELD1:r[0-9]+]], [[FIELD2:r[0-9]+]], {{\[}}[[BASE]], #4] 87; A8-NEXT: add [[FIELD1]], [[FIELD2]] 88; A8-NEXT: str [[FIELD1]], {{\[}}[[BASE]]{{\]}} 89; CONSERVATIVE-NOT: ldrd 90 %orig_blocks = alloca [256 x i16], align 2 91 %0 = bitcast [256 x i16]* %orig_blocks to i8*call void @llvm.lifetime.start.p0i8(i64 512, i8* %0) nounwind 92 %tmp1 = load i32, i32* getelementptr inbounds (%struct.Test, %struct.Test* @TestVar, i32 0, i32 1), align 4 93 %tmp2 = load i32, i32* getelementptr inbounds (%struct.Test, %struct.Test* @TestVar, i32 0, i32 2), align 4 94 %add = add nsw i32 %tmp2, %tmp1 95 store i32 %add, i32* getelementptr inbounds (%struct.Test, %struct.Test* @TestVar, i32 0, i32 0), align 4 96 call void @llvm.lifetime.end.p0i8(i64 512, i8* %0) nounwind 97 ret void 98} 99 100declare void @extfunc(i32, i32, i32, i32) 101 102; CHECK-LABEL: Func2: 103; CONSERVATIVE-NOT: ldrd 104; A8: ldrd 105; CHECK: bl{{x?}} _extfunc 106; A8: pop 107define void @Func2(i32* %p) "no-frame-pointer-elim"="true" { 108entry: 109 %addr0 = getelementptr i32, i32* %p, i32 0 110 %addr1 = getelementptr i32, i32* %p, i32 1 111 %v0 = load i32, i32* %addr0 112 %v1 = load i32, i32* %addr1 113 ; try to force %v0/%v1 into non-adjacent registers 114 call void @extfunc(i32 %v0, i32 0, i32 0, i32 %v1) 115 ret void 116} 117 118; CHECK-LABEL: strd_spill_ldrd_reload: 119; A8: strd r1, r0, [sp, #-8]! 120; M3: strd r1, r0, [sp, #-8]! 121; BASIC: strd r1, r0, [sp, #-8]! 122; GREEDY: strd r0, r1, [sp, #-8]! 123; CONSERVATIVE: strd r0, r1, [sp, #-8]! 124; NORMAL: @ InlineAsm Start 125; NORMAL: @ InlineAsm End 126; A8: ldrd r2, r1, [sp] 127; M3: ldrd r2, r1, [sp] 128; BASIC: ldrd r2, r1, [sp] 129; GREEDY: ldrd r1, r2, [sp] 130; CONSERVATIVE: ldrd r1, r2, [sp] 131; CHECK: bl{{x?}} _extfunc 132define void @strd_spill_ldrd_reload(i32 %v0, i32 %v1) "no-frame-pointer-elim"="true" { 133 ; force %v0 and %v1 to be spilled 134 call void asm sideeffect "", "~{r0},~{r1},~{r2},~{r3},~{r4},~{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11},~{r12},~{lr}"() 135 ; force the reloaded %v0, %v1 into different registers 136 call void @extfunc(i32 0, i32 %v0, i32 %v1, i32 7) 137 ret void 138} 139 140declare void @extfunc2(i32*, i32, i32) 141 142; CHECK-LABEL: ldrd_postupdate_dec: 143; NORMAL: ldrd r1, r2, [r0], #-8 144; CONSERVATIVE-NOT: ldrd 145; CHECK: bl{{x?}} _extfunc 146define void @ldrd_postupdate_dec(i32* %p0) "no-frame-pointer-elim"="true" { 147 %p0.1 = getelementptr i32, i32* %p0, i32 1 148 %v0 = load i32, i32* %p0 149 %v1 = load i32, i32* %p0.1 150 %p1 = getelementptr i32, i32* %p0, i32 -2 151 call void @extfunc2(i32* %p1, i32 %v0, i32 %v1) 152 ret void 153} 154 155; CHECK-LABEL: ldrd_postupdate_inc: 156; NORMAL: ldrd r1, r2, [r0], #8 157; CONSERVATIVE-NOT: ldrd 158; CHECK: bl{{x?}} _extfunc 159define void @ldrd_postupdate_inc(i32* %p0) "no-frame-pointer-elim"="true" { 160 %p0.1 = getelementptr i32, i32* %p0, i32 1 161 %v0 = load i32, i32* %p0 162 %v1 = load i32, i32* %p0.1 163 %p1 = getelementptr i32, i32* %p0, i32 2 164 call void @extfunc2(i32* %p1, i32 %v0, i32 %v1) 165 ret void 166} 167 168; CHECK-LABEL: strd_postupdate_dec: 169; NORMAL: strd r1, r2, [r0], #-8 170; CONSERVATIVE-NOT: strd 171; CHECK: bx lr 172define i32* @strd_postupdate_dec(i32* %p0, i32 %v0, i32 %v1) "no-frame-pointer-elim"="true" { 173 %p0.1 = getelementptr i32, i32* %p0, i32 1 174 store i32 %v0, i32* %p0 175 store i32 %v1, i32* %p0.1 176 %p1 = getelementptr i32, i32* %p0, i32 -2 177 ret i32* %p1 178} 179 180; CHECK-LABEL: strd_postupdate_inc: 181; NORMAL: strd r1, r2, [r0], #8 182; CONSERVATIVE-NOT: strd 183; CHECK: bx lr 184define i32* @strd_postupdate_inc(i32* %p0, i32 %v0, i32 %v1) "no-frame-pointer-elim"="true" { 185 %p0.1 = getelementptr i32, i32* %p0, i32 1 186 store i32 %v0, i32* %p0 187 store i32 %v1, i32* %p0.1 188 %p1 = getelementptr i32, i32* %p0, i32 2 189 ret i32* %p1 190} 191 192; CHECK-LABEL: ldrd_strd_aa: 193; NORMAL: ldrd [[TMP1:r[0-9]]], [[TMP2:r[0-9]]], 194; NORMAL: strd [[TMP1]], [[TMP2]], 195; CONSERVATIVE-NOT: ldrd 196; CONSERVATIVE-NOT: strd 197; CHECK: bx lr 198 199define void @ldrd_strd_aa(i32* noalias nocapture %x, i32* noalias nocapture readonly %y) { 200entry: 201 %0 = load i32, i32* %y, align 4 202 store i32 %0, i32* %x, align 4 203 %arrayidx2 = getelementptr inbounds i32, i32* %y, i32 1 204 %1 = load i32, i32* %arrayidx2, align 4 205 %arrayidx3 = getelementptr inbounds i32, i32* %x, i32 1 206 store i32 %1, i32* %arrayidx3, align 4 207 ret void 208} 209 210; CHECK-LABEL: bitcast_ptr_ldr 211; CHECK-NOT: ldrd 212define i32 @bitcast_ptr_ldr(i16* %In) { 213entry: 214 %0 = bitcast i16* %In to i32* 215 %in.addr.0 = getelementptr inbounds i32, i32* %0, i32 0 216 %in.addr.1 = getelementptr inbounds i32, i32* %0, i32 1 217 %1 = load i32, i32* %in.addr.0, align 2 218 %2 = load i32, i32* %in.addr.1, align 2 219 %mul = mul i32 %1, %2 220 ret i32 %mul 221} 222 223; CHECK-LABEL: bitcast_gep_ldr 224; CHECK-NOT: ldrd 225define i32 @bitcast_gep_ldr(i16* %In) { 226entry: 227 %in.addr.0 = getelementptr inbounds i16, i16* %In, i32 0 228 %in.addr.1 = getelementptr inbounds i16, i16* %In, i32 2 229 %cast.0 = bitcast i16* %in.addr.0 to i32* 230 %cast.1 = bitcast i16* %in.addr.1 to i32* 231 %0 = load i32, i32* %cast.0, align 2 232 %1 = load i32, i32* %cast.1, align 2 233 %mul = mul i32 %0, %1 234 ret i32 %mul 235} 236 237; CHECK-LABEL: bitcast_ptr_str 238; CHECK-NOT: strd 239define void @bitcast_ptr_str(i32 %arg0, i32 %arg1, i16* %out) { 240entry: 241 %0 = bitcast i16* %out to i32* 242 %out.addr.0 = getelementptr inbounds i32, i32* %0, i32 0 243 %out.addr.1 = getelementptr inbounds i32, i32* %0, i32 1 244 store i32 %arg0, i32* %out.addr.0, align 2 245 store i32 %arg1, i32* %out.addr.1, align 2 246 ret void 247} 248 249; CHECK-LABEL: bitcast_gep_str 250; CHECK-NOT: strd 251define void @bitcast_gep_str(i32 %arg0, i32 %arg1, i16* %out) { 252entry: 253 %out.addr.0 = getelementptr inbounds i16, i16* %out, i32 0 254 %out.addr.1 = getelementptr inbounds i16, i16* %out, i32 2 255 %cast.0 = bitcast i16* %out.addr.0 to i32* 256 %cast.1 = bitcast i16* %out.addr.1 to i32* 257 store i32 %arg0, i32* %cast.0, align 2 258 store i32 %arg1, i32* %cast.1, align 2 259 ret void 260} 261 262declare void @llvm.lifetime.start.p0i8(i64, i8* nocapture) nounwind 263declare void @llvm.lifetime.end.p0i8(i64, i8* nocapture) nounwind 264