1 /* 2 * $Id: pmrc.h,v 1.9 2005/09/29 08:51:07 telka Exp $ 3 * 4 * XScale PXA26x/PXA255/PXA250/PXA210 Power Manager and Reset Control Registers 5 * Copyright (C) 2002, 2003 ETC s.r.o. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. Neither the name of the ETC s.r.o. nor the names of its contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE 24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 26 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 27 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 28 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 29 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 * 31 * Written by Marcel Telka <marcel@telka.sk>, 2002, 2003. 32 * 33 * Documentation: 34 * [1] Intel Corporation, "Intel PXA250 and PXA210 Application Processors 35 * Developer's Manual", February 2002, Order Number: 278522-001 36 * [2] Intel Corporation, "Intel PXA26x Processor Family Developer's Manual", 37 * March 2003, Order Number: 278638-002 38 * [3] Intel Corporation, "Intel PXA255 Processor Developer's Manual" 39 * March 2003, Order Number: 278693-001 40 * 41 */ 42 43 #ifndef PXA2X0_PMRC_H 44 #define PXA2X0_PMRC_H 45 46 #include <openwince.h> 47 48 #if LANGUAGE == C 49 #include <stdint.h> 50 #endif 51 52 #if defined(PXA2X0_NOPXA250) && !defined(PXA2X0_NOPXA255) 53 #define PXA2X0_NOPXA255 54 #endif 55 56 #if defined(PXA2X0_NOPXA255) && !defined(PXA2X0_NOPXA260) 57 #define PXA2X0_NOPXA260 58 #endif 59 60 /* Power Manager and Reset Control Registers */ 61 62 #define PMRC_BASE 0x40F00000 63 64 #if LANGUAGE == C 65 typedef volatile struct PMRC_registers { 66 uint32_t pmcr; 67 uint32_t pssr; 68 uint32_t pspr; 69 uint32_t pwer; 70 uint32_t prer; 71 uint32_t pfer; 72 uint32_t pedr; 73 uint32_t pcfr; 74 uint32_t pgsr0; 75 uint32_t pgsr1; 76 uint32_t pgsr2; 77 uint32_t __reserved; 78 uint32_t rcsr; 79 } PMRC_registers_t; 80 81 #ifdef PXA2X0_UNMAPPED 82 #define PMRC_pointer ((PMRC_registers_t*) PMRC_BASE) 83 #endif 84 85 #define PMCR PMRC_pointer->pmcr 86 #define PSSR PMRC_pointer->pssr 87 #define PSPR PMRC_pointer->pspr 88 #define PWER PMRC_pointer->pwer 89 #define PRER PMRC_pointer->prer 90 #define PFER PMRC_pointer->pfer 91 #define PEDR PMRC_pointer->pedr 92 #define PCFR PMRC_pointer->pcfr 93 #define PGSR0 PMRC_pointer->pgsr0 94 #define PGSR1 PMRC_pointer->pgsr1 95 #define PGSR2 PMRC_pointer->pgsr2 96 #define RCSR PMRC_pointer->rcsr 97 #endif /* LANGUAGE == C */ 98 99 #define PMCR_OFFSET 0x00 100 #define PSSR_OFFSET 0x04 101 #define PSPR_OFFSET 0x08 102 #define PWER_OFFSET 0x0C 103 #define PRER_OFFSET 0x10 104 #define PFER_OFFSET 0x14 105 #define PEDR_OFFSET 0x18 106 #define PCFR_OFFSET 0x1C 107 #define PGSR0_OFFSET 0x20 108 #define PGSR1_OFFSET 0x24 109 #define PGSR2_OFFSET 0x28 110 #define RCSR_OFFSET 0x30 111 112 /* PMCR bits - see Table 3-7 in [1], Table 3-7 in [2], Table 3-7 in [3] */ 113 114 #define PMCR_IDAE bit(0) 115 116 /* PSSR bits - see Table 3-13 in [1], Table 3-13 in [2], Table 3-13 in [3] */ 117 118 #define PSSR_RDH bit(5) 119 #define PSSR_PH bit(4) 120 #define PSSR_VFS bit(2) 121 #define PSSR_BFS bit(1) 122 #define PSSR_SSS bit(0) 123 124 /* PWER bits - see Table 3-9 in [1], Table 3-9 in [2], Table 3-9 in [3] */ 125 126 #define PWER_WERTC bit(31) 127 #define PWER_WE15 bit(15) 128 #define PWER_WE14 bit(14) 129 #define PWER_WE13 bit(13) 130 #define PWER_WE12 bit(12) 131 #define PWER_WE11 bit(11) 132 #define PWER_WE10 bit(10) 133 #define PWER_WE9 bit(9) 134 #define PWER_WE8 bit(8) 135 #define PWER_WE7 bit(7) 136 #define PWER_WE6 bit(6) 137 #define PWER_WE5 bit(5) 138 #define PWER_WE4 bit(4) 139 #define PWER_WE3 bit(3) 140 #define PWER_WE2 bit(2) 141 #define PWER_WE1 bit(1) 142 #define PWER_WE0 bit(0) 143 144 /* PCFR bits - see Table 3-8 in [1], Table 3-8 in [2], Table 3-8 in [3] */ 145 146 #define PCFR_FS bit(2) 147 #define PCFR_FP bit(1) 148 #define PCFR_OPDE bit(0) 149 150 /* RCSR bits - see Table 3-18 in [1], Table 3-18 in [2], Table 3-19 in [3] */ 151 152 #define RCSR_GPR bit(3) 153 #define RCSR_SMR bit(2) 154 #define RCSR_WDR bit(1) 155 #define RCSR_HWR bit(0) 156 157 #endif /* PXA2X0_PMRC_H */ 158