1 /**
2 ******************************************************************************
3 * @file stm32l1xx_hal_cortex.h
4 * @author MCD Application Team
5 * @version V1.2.0
6 * @date 01-July-2016
7 * @brief Header file of CORTEX HAL module.
8 ******************************************************************************
9 * @attention
10 *
11 * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
12 *
13 * Redistribution and use in source and binary forms, with or without modification,
14 * are permitted provided that the following conditions are met:
15 * 1. Redistributions of source code must retain the above copyright notice,
16 * this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright notice,
18 * this list of conditions and the following disclaimer in the documentation
19 * and/or other materials provided with the distribution.
20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 *
35 ******************************************************************************
36 */
37
38 /* Define to prevent recursive inclusion -------------------------------------*/
39 #ifndef __STM32L1xx_HAL_CORTEX_H
40 #define __STM32L1xx_HAL_CORTEX_H
41
42 #ifdef __cplusplus
43 extern "C" {
44 #endif
45
46 /* Includes ------------------------------------------------------------------*/
47 #include "stm32l1xx_hal_def.h"
48
49 /** @addtogroup STM32L1xx_HAL_Driver
50 * @{
51 */
52
53 /** @addtogroup CORTEX
54 * @{
55 */
56
57 /* Exported types ------------------------------------------------------------*/
58 /** @defgroup CORTEX_Exported_Types Cortex Exported Types
59 * @{
60 */
61
62 #if (__MPU_PRESENT == 1)
63 /** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition
64 * @brief MPU Region initialization structure
65 * @{
66 */
67 typedef struct
68 {
69 uint8_t Enable; /*!< Specifies the status of the region.
70 This parameter can be a value of @ref CORTEX_MPU_Region_Enable */
71 uint8_t Number; /*!< Specifies the number of the region to protect.
72 This parameter can be a value of @ref CORTEX_MPU_Region_Number */
73 uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. */
74 uint8_t Size; /*!< Specifies the size of the region to protect.
75 This parameter can be a value of @ref CORTEX_MPU_Region_Size */
76 uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable.
77 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */
78 uint8_t TypeExtField; /*!< Specifies the TEX field level.
79 This parameter can be a value of @ref CORTEX_MPU_TEX_Levels */
80 uint8_t AccessPermission; /*!< Specifies the region access permission type.
81 This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */
82 uint8_t DisableExec; /*!< Specifies the instruction access status.
83 This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */
84 uint8_t IsShareable; /*!< Specifies the shareability status of the protected region.
85 This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */
86 uint8_t IsCacheable; /*!< Specifies the cacheable status of the region protected.
87 This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable */
88 uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region.
89 This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable */
90 }MPU_Region_InitTypeDef;
91 /**
92 * @}
93 */
94 #endif /* __MPU_PRESENT */
95
96 /**
97 * @}
98 */
99
100 /* Exported constants --------------------------------------------------------*/
101
102 /** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants
103 * @{
104 */
105
106
107 /** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group
108 * @{
109 */
110
111 #define NVIC_PRIORITYGROUP_0 ((uint32_t)0x00000007) /*!< 0 bits for pre-emption priority
112 4 bits for subpriority */
113 #define NVIC_PRIORITYGROUP_1 ((uint32_t)0x00000006) /*!< 1 bits for pre-emption priority
114 3 bits for subpriority */
115 #define NVIC_PRIORITYGROUP_2 ((uint32_t)0x00000005) /*!< 2 bits for pre-emption priority
116 2 bits for subpriority */
117 #define NVIC_PRIORITYGROUP_3 ((uint32_t)0x00000004) /*!< 3 bits for pre-emption priority
118 1 bits for subpriority */
119 #define NVIC_PRIORITYGROUP_4 ((uint32_t)0x00000003) /*!< 4 bits for pre-emption priority
120 0 bits for subpriority */
121 /**
122 * @}
123 */
124
125 /** @defgroup CORTEX_SysTick_clock_source CORTEX SysTick clock source
126 * @{
127 */
128 #define SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0x00000000)
129 #define SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004)
130
131 /**
132 * @}
133 */
134
135 #if (__MPU_PRESENT == 1)
136 /** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control MPU HFNMI and PRIVILEGED Access control
137 * @{
138 */
139 #define MPU_HFNMI_PRIVDEF_NONE ((uint32_t)0x00000000)
140 #define MPU_HARDFAULT_NMI ((uint32_t)0x00000002)
141 #define MPU_PRIVILEGED_DEFAULT ((uint32_t)0x00000004)
142 #define MPU_HFNMI_PRIVDEF ((uint32_t)0x00000006)
143 /**
144 * @}
145 */
146
147 /** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable
148 * @{
149 */
150 #define MPU_REGION_ENABLE ((uint8_t)0x01)
151 #define MPU_REGION_DISABLE ((uint8_t)0x00)
152 /**
153 * @}
154 */
155
156 /** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access
157 * @{
158 */
159 #define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00)
160 #define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01)
161 /**
162 * @}
163 */
164
165 /** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable
166 * @{
167 */
168 #define MPU_ACCESS_SHAREABLE ((uint8_t)0x01)
169 #define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00)
170 /**
171 * @}
172 */
173
174 /** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable
175 * @{
176 */
177 #define MPU_ACCESS_CACHEABLE ((uint8_t)0x01)
178 #define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00)
179 /**
180 * @}
181 */
182
183 /** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable
184 * @{
185 */
186 #define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01)
187 #define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00)
188 /**
189 * @}
190 */
191
192 /** @defgroup CORTEX_MPU_TEX_Levels MPU TEX Levels
193 * @{
194 */
195 #define MPU_TEX_LEVEL0 ((uint8_t)0x00)
196 #define MPU_TEX_LEVEL1 ((uint8_t)0x01)
197 #define MPU_TEX_LEVEL2 ((uint8_t)0x02)
198 /**
199 * @}
200 */
201
202 /** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size
203 * @{
204 */
205 #define MPU_REGION_SIZE_32B ((uint8_t)0x04)
206 #define MPU_REGION_SIZE_64B ((uint8_t)0x05)
207 #define MPU_REGION_SIZE_128B ((uint8_t)0x06)
208 #define MPU_REGION_SIZE_256B ((uint8_t)0x07)
209 #define MPU_REGION_SIZE_512B ((uint8_t)0x08)
210 #define MPU_REGION_SIZE_1KB ((uint8_t)0x09)
211 #define MPU_REGION_SIZE_2KB ((uint8_t)0x0A)
212 #define MPU_REGION_SIZE_4KB ((uint8_t)0x0B)
213 #define MPU_REGION_SIZE_8KB ((uint8_t)0x0C)
214 #define MPU_REGION_SIZE_16KB ((uint8_t)0x0D)
215 #define MPU_REGION_SIZE_32KB ((uint8_t)0x0E)
216 #define MPU_REGION_SIZE_64KB ((uint8_t)0x0F)
217 #define MPU_REGION_SIZE_128KB ((uint8_t)0x10)
218 #define MPU_REGION_SIZE_256KB ((uint8_t)0x11)
219 #define MPU_REGION_SIZE_512KB ((uint8_t)0x12)
220 #define MPU_REGION_SIZE_1MB ((uint8_t)0x13)
221 #define MPU_REGION_SIZE_2MB ((uint8_t)0x14)
222 #define MPU_REGION_SIZE_4MB ((uint8_t)0x15)
223 #define MPU_REGION_SIZE_8MB ((uint8_t)0x16)
224 #define MPU_REGION_SIZE_16MB ((uint8_t)0x17)
225 #define MPU_REGION_SIZE_32MB ((uint8_t)0x18)
226 #define MPU_REGION_SIZE_64MB ((uint8_t)0x19)
227 #define MPU_REGION_SIZE_128MB ((uint8_t)0x1A)
228 #define MPU_REGION_SIZE_256MB ((uint8_t)0x1B)
229 #define MPU_REGION_SIZE_512MB ((uint8_t)0x1C)
230 #define MPU_REGION_SIZE_1GB ((uint8_t)0x1D)
231 #define MPU_REGION_SIZE_2GB ((uint8_t)0x1E)
232 #define MPU_REGION_SIZE_4GB ((uint8_t)0x1F)
233 /**
234 * @}
235 */
236
237 /** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes
238 * @{
239 */
240 #define MPU_REGION_NO_ACCESS ((uint8_t)0x00)
241 #define MPU_REGION_PRIV_RW ((uint8_t)0x01)
242 #define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02)
243 #define MPU_REGION_FULL_ACCESS ((uint8_t)0x03)
244 #define MPU_REGION_PRIV_RO ((uint8_t)0x05)
245 #define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06)
246 /**
247 * @}
248 */
249
250 /** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number
251 * @{
252 */
253 #define MPU_REGION_NUMBER0 ((uint8_t)0x00)
254 #define MPU_REGION_NUMBER1 ((uint8_t)0x01)
255 #define MPU_REGION_NUMBER2 ((uint8_t)0x02)
256 #define MPU_REGION_NUMBER3 ((uint8_t)0x03)
257 #define MPU_REGION_NUMBER4 ((uint8_t)0x04)
258 #define MPU_REGION_NUMBER5 ((uint8_t)0x05)
259 #define MPU_REGION_NUMBER6 ((uint8_t)0x06)
260 #define MPU_REGION_NUMBER7 ((uint8_t)0x07)
261 /**
262 * @}
263 */
264 #endif /* __MPU_PRESENT */
265 /**
266 * @}
267 */
268
269 /* Exported Macros -----------------------------------------------------------*/
270 /** @defgroup CORTEX_Exported_Macros CORTEX Exported Macros
271 * @{
272 */
273
274 /** @defgroup CORTEX_Preemption_Priority_Group_Macro CORTEX Preemption Priority Group
275 * @{
276 */
277 #define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \
278 ((GROUP) == NVIC_PRIORITYGROUP_1) || \
279 ((GROUP) == NVIC_PRIORITYGROUP_2) || \
280 ((GROUP) == NVIC_PRIORITYGROUP_3) || \
281 ((GROUP) == NVIC_PRIORITYGROUP_4))
282
283 #define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
284
285 #define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
286
287 #define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= 0x00)
288
289 /**
290 * @}
291 */
292
293 /**
294 * @}
295 */
296
297 /* Private macro -------------------------------------------------------------*/
298 /** @defgroup CORTEX_Private_Macros CORTEX Private Macros
299 * @{
300 */
301
302 /** @defgroup CORTEX_SysTick_clock_source_Macro_Private CORTEX SysTick clock source
303 * @{
304 */
305 #define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \
306 ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))
307 /**
308 * @}
309 */
310
311 #if (__MPU_PRESENT == 1)
312 #define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \
313 ((STATE) == MPU_REGION_DISABLE))
314
315 #define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \
316 ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))
317
318 #define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || \
319 ((STATE) == MPU_ACCESS_NOT_SHAREABLE))
320
321 #define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || \
322 ((STATE) == MPU_ACCESS_NOT_CACHEABLE))
323
324 #define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || \
325 ((STATE) == MPU_ACCESS_NOT_BUFFERABLE))
326
327 #define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || \
328 ((TYPE) == MPU_TEX_LEVEL1) || \
329 ((TYPE) == MPU_TEX_LEVEL2))
330
331 #define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || \
332 ((TYPE) == MPU_REGION_PRIV_RW) || \
333 ((TYPE) == MPU_REGION_PRIV_RW_URO) || \
334 ((TYPE) == MPU_REGION_FULL_ACCESS) || \
335 ((TYPE) == MPU_REGION_PRIV_RO) || \
336 ((TYPE) == MPU_REGION_PRIV_RO_URO))
337
338 #define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \
339 ((NUMBER) == MPU_REGION_NUMBER1) || \
340 ((NUMBER) == MPU_REGION_NUMBER2) || \
341 ((NUMBER) == MPU_REGION_NUMBER3) || \
342 ((NUMBER) == MPU_REGION_NUMBER4) || \
343 ((NUMBER) == MPU_REGION_NUMBER5) || \
344 ((NUMBER) == MPU_REGION_NUMBER6) || \
345 ((NUMBER) == MPU_REGION_NUMBER7))
346
347 #define IS_MPU_REGION_SIZE(SIZE) (((SIZE) == MPU_REGION_SIZE_32B) || \
348 ((SIZE) == MPU_REGION_SIZE_64B) || \
349 ((SIZE) == MPU_REGION_SIZE_128B) || \
350 ((SIZE) == MPU_REGION_SIZE_256B) || \
351 ((SIZE) == MPU_REGION_SIZE_512B) || \
352 ((SIZE) == MPU_REGION_SIZE_1KB) || \
353 ((SIZE) == MPU_REGION_SIZE_2KB) || \
354 ((SIZE) == MPU_REGION_SIZE_4KB) || \
355 ((SIZE) == MPU_REGION_SIZE_8KB) || \
356 ((SIZE) == MPU_REGION_SIZE_16KB) || \
357 ((SIZE) == MPU_REGION_SIZE_32KB) || \
358 ((SIZE) == MPU_REGION_SIZE_64KB) || \
359 ((SIZE) == MPU_REGION_SIZE_128KB) || \
360 ((SIZE) == MPU_REGION_SIZE_256KB) || \
361 ((SIZE) == MPU_REGION_SIZE_512KB) || \
362 ((SIZE) == MPU_REGION_SIZE_1MB) || \
363 ((SIZE) == MPU_REGION_SIZE_2MB) || \
364 ((SIZE) == MPU_REGION_SIZE_4MB) || \
365 ((SIZE) == MPU_REGION_SIZE_8MB) || \
366 ((SIZE) == MPU_REGION_SIZE_16MB) || \
367 ((SIZE) == MPU_REGION_SIZE_32MB) || \
368 ((SIZE) == MPU_REGION_SIZE_64MB) || \
369 ((SIZE) == MPU_REGION_SIZE_128MB) || \
370 ((SIZE) == MPU_REGION_SIZE_256MB) || \
371 ((SIZE) == MPU_REGION_SIZE_512MB) || \
372 ((SIZE) == MPU_REGION_SIZE_1GB) || \
373 ((SIZE) == MPU_REGION_SIZE_2GB) || \
374 ((SIZE) == MPU_REGION_SIZE_4GB))
375
376 #define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FF)
377 #endif /* __MPU_PRESENT */
378
379 /**
380 * @}
381 */
382
383 /* Private functions ---------------------------------------------------------*/
384 /** @defgroup CORTEX_Private_Functions CORTEX Private Functions
385 * @brief CORTEX private functions
386 * @{
387 */
388
389 #if (__MPU_PRESENT == 1)
390 /**
391 * @brief Disables the MPU
392 * @retval None
393 */
HAL_MPU_Disable(void)394 __STATIC_INLINE void HAL_MPU_Disable(void)
395 {
396 /* Disable fault exceptions */
397 SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
398
399 /* Disable the MPU */
400 MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
401 }
402
403 /**
404 * @brief Enables the MPU
405 * @param MPU_Control: Specifies the control mode of the MPU during hard fault,
406 * NMI, FAULTMASK and privileged accessto the default memory
407 * This parameter can be one of the following values:
408 * @arg MPU_HFNMI_PRIVDEF_NONE
409 * @arg MPU_HARDFAULT_NMI
410 * @arg MPU_PRIVILEGED_DEFAULT
411 * @arg MPU_HFNMI_PRIVDEF
412 * @retval None
413 */
HAL_MPU_Enable(uint32_t MPU_Control)414 __STATIC_INLINE void HAL_MPU_Enable(uint32_t MPU_Control)
415 {
416 /* Enable the MPU */
417 MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
418
419 /* Enable fault exceptions */
420 SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
421 }
422 #endif /* __MPU_PRESENT */
423
424 /**
425 * @}
426 */
427
428 /* Exported functions --------------------------------------------------------*/
429 /** @addtogroup CORTEX_Exported_Functions
430 * @{
431 */
432
433 /** @addtogroup CORTEX_Exported_Functions_Group1
434 * @{
435 */
436 /* Initialization and de-initialization functions *****************************/
437 void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup);
438 void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority);
439 void HAL_NVIC_EnableIRQ(IRQn_Type IRQn);
440 void HAL_NVIC_DisableIRQ(IRQn_Type IRQn);
441 void HAL_NVIC_SystemReset(void);
442 uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);
443 /**
444 * @}
445 */
446
447 /** @addtogroup CORTEX_Exported_Functions_Group2
448 * @{
449 */
450 /* Peripheral Control functions ***********************************************/
451 #if (__MPU_PRESENT == 1)
452 void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
453 #endif /* __MPU_PRESENT */
454 uint32_t HAL_NVIC_GetPriorityGrouping(void);
455 void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority);
456 uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn);
457 void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn);
458 void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn);
459 uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn);
460 void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource);
461 void HAL_SYSTICK_IRQHandler(void);
462 void HAL_SYSTICK_Callback(void);
463 /**
464 * @}
465 */
466
467 /**
468 * @}
469 */
470
471 /**
472 * @}
473 */
474
475 /**
476 * @}
477 */
478
479 #ifdef __cplusplus
480 }
481 #endif
482
483 #endif /* __STM32L1xx_HAL_CORTEX_H */
484
485
486 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
487