1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ 2|* *| 3|* Target Register Enum Values *| 4|* *| 5|* Automatically generated file, do not edit! *| 6|* *| 7\*===----------------------------------------------------------------------===*/ 8 9 10#ifdef GET_REGINFO_ENUM 11#undef GET_REGINFO_ENUM 12namespace llvm { 13 14class MCRegisterClass; 15extern const MCRegisterClass SystemZMCRegisterClasses[]; 16 17namespace SystemZ { 18enum { 19 NoRegister, 20 CC = 1, 21 V0 = 2, 22 V1 = 3, 23 V2 = 4, 24 V3 = 5, 25 V4 = 6, 26 V5 = 7, 27 V6 = 8, 28 V7 = 9, 29 V8 = 10, 30 V9 = 11, 31 V10 = 12, 32 V11 = 13, 33 V12 = 14, 34 V13 = 15, 35 V14 = 16, 36 V15 = 17, 37 V16 = 18, 38 V17 = 19, 39 V18 = 20, 40 V19 = 21, 41 V20 = 22, 42 V21 = 23, 43 V22 = 24, 44 V23 = 25, 45 V24 = 26, 46 V25 = 27, 47 V26 = 28, 48 V27 = 29, 49 V28 = 30, 50 V29 = 31, 51 V30 = 32, 52 V31 = 33, 53 F0D = 34, 54 F1D = 35, 55 F2D = 36, 56 F3D = 37, 57 F4D = 38, 58 F5D = 39, 59 F6D = 40, 60 F7D = 41, 61 F8D = 42, 62 F9D = 43, 63 F10D = 44, 64 F11D = 45, 65 F12D = 46, 66 F13D = 47, 67 F14D = 48, 68 F15D = 49, 69 F16D = 50, 70 F17D = 51, 71 F18D = 52, 72 F19D = 53, 73 F20D = 54, 74 F21D = 55, 75 F22D = 56, 76 F23D = 57, 77 F24D = 58, 78 F25D = 59, 79 F26D = 60, 80 F27D = 61, 81 F28D = 62, 82 F29D = 63, 83 F30D = 64, 84 F31D = 65, 85 F0Q = 66, 86 F1Q = 67, 87 F4Q = 68, 88 F5Q = 69, 89 F8Q = 70, 90 F9Q = 71, 91 F12Q = 72, 92 F13Q = 73, 93 F0S = 74, 94 F1S = 75, 95 F2S = 76, 96 F3S = 77, 97 F4S = 78, 98 F5S = 79, 99 F6S = 80, 100 F7S = 81, 101 F8S = 82, 102 F9S = 83, 103 F10S = 84, 104 F11S = 85, 105 F12S = 86, 106 F13S = 87, 107 F14S = 88, 108 F15S = 89, 109 F16S = 90, 110 F17S = 91, 111 F18S = 92, 112 F19S = 93, 113 F20S = 94, 114 F21S = 95, 115 F22S = 96, 116 F23S = 97, 117 F24S = 98, 118 F25S = 99, 119 F26S = 100, 120 F27S = 101, 121 F28S = 102, 122 F29S = 103, 123 F30S = 104, 124 F31S = 105, 125 R0D = 106, 126 R1D = 107, 127 R2D = 108, 128 R3D = 109, 129 R4D = 110, 130 R5D = 111, 131 R6D = 112, 132 R7D = 113, 133 R8D = 114, 134 R9D = 115, 135 R10D = 116, 136 R11D = 117, 137 R12D = 118, 138 R13D = 119, 139 R14D = 120, 140 R15D = 121, 141 R0H = 122, 142 R1H = 123, 143 R2H = 124, 144 R3H = 125, 145 R4H = 126, 146 R5H = 127, 147 R6H = 128, 148 R7H = 129, 149 R8H = 130, 150 R9H = 131, 151 R10H = 132, 152 R11H = 133, 153 R12H = 134, 154 R13H = 135, 155 R14H = 136, 156 R15H = 137, 157 R0L = 138, 158 R1L = 139, 159 R2L = 140, 160 R3L = 141, 161 R4L = 142, 162 R5L = 143, 163 R6L = 144, 164 R7L = 145, 165 R8L = 146, 166 R9L = 147, 167 R10L = 148, 168 R11L = 149, 169 R12L = 150, 170 R13L = 151, 171 R14L = 152, 172 R15L = 153, 173 R0Q = 154, 174 R2Q = 155, 175 R4Q = 156, 176 R6Q = 157, 177 R8Q = 158, 178 R10Q = 159, 179 R12Q = 160, 180 R14Q = 161, 181 NUM_TARGET_REGS // 162 182}; 183} 184 185// Register classes 186namespace SystemZ { 187enum { 188 GRX32BitRegClassID = 0, 189 VR32BitRegClassID = 1, 190 FP32BitRegClassID = 2, 191 GR32BitRegClassID = 3, 192 GRH32BitRegClassID = 4, 193 ADDR32BitRegClassID = 5, 194 CCRegsRegClassID = 6, 195 VR64BitRegClassID = 7, 196 FP64BitRegClassID = 8, 197 GR64BitRegClassID = 9, 198 ADDR64BitRegClassID = 10, 199 VR128BitRegClassID = 11, 200 VF128BitRegClassID = 12, 201 FP128BitRegClassID = 13, 202 GR128BitRegClassID = 14, 203 ADDR128BitRegClassID = 15, 204 205 }; 206} 207 208// Subregister indices 209namespace SystemZ { 210enum { 211 NoSubRegister, 212 subreg_h32, // 1 213 subreg_h64, // 2 214 subreg_hh32, // 3 215 subreg_hl32, // 4 216 subreg_hr32, // 5 217 subreg_l32, // 6 218 subreg_l64, // 7 219 subreg_r32, // 8 220 subreg_r64, // 9 221 NUM_TARGET_SUBREGS 222}; 223} 224} // End llvm namespace 225#endif // GET_REGINFO_ENUM 226 227/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ 228|* *| 229|* MC Register Information *| 230|* *| 231|* Automatically generated file, do not edit! *| 232|* *| 233\*===----------------------------------------------------------------------===*/ 234 235 236#ifdef GET_REGINFO_MC_DESC 237#undef GET_REGINFO_MC_DESC 238namespace llvm { 239 240extern const MCPhysReg SystemZRegDiffLists[] = { 241 /* 0 */ 64953, 1, 1, 1, 0, 242 /* 5 */ 65357, 1, 0, 243 /* 8 */ 65471, 2, 0, 244 /* 11 */ 65473, 2, 0, 245 /* 14 */ 65475, 2, 0, 246 /* 17 */ 65477, 2, 0, 247 /* 20 */ 32, 40, 0, 248 /* 23 */ 65506, 40, 65494, 40, 0, 249 /* 28 */ 65508, 40, 65494, 40, 0, 250 /* 33 */ 65510, 40, 65494, 40, 0, 251 /* 38 */ 65512, 40, 65494, 40, 0, 252 /* 43 */ 65504, 40, 0, 253 /* 46 */ 65520, 40, 0, 254 /* 49 */ 65504, 41, 0, 255 /* 52 */ 65520, 41, 0, 256 /* 55 */ 65504, 42, 0, 257 /* 58 */ 65520, 42, 0, 258 /* 61 */ 65504, 43, 0, 259 /* 64 */ 65520, 43, 0, 260 /* 67 */ 65504, 44, 0, 261 /* 70 */ 65520, 44, 0, 262 /* 73 */ 65504, 45, 0, 263 /* 76 */ 65520, 45, 0, 264 /* 79 */ 65504, 46, 0, 265 /* 82 */ 65520, 46, 0, 266 /* 85 */ 65504, 47, 0, 267 /* 88 */ 65520, 47, 0, 268 /* 91 */ 65504, 48, 0, 269 /* 94 */ 65520, 48, 0, 270 /* 97 */ 65496, 65504, 56, 0, 271 /* 101 */ 65496, 65504, 58, 0, 272 /* 105 */ 65496, 65504, 60, 0, 273 /* 109 */ 65496, 65504, 62, 0, 274 /* 113 */ 65496, 65504, 64, 0, 275 /* 117 */ 65293, 0, 276 /* 119 */ 65326, 0, 277 /* 121 */ 65463, 0, 278 /* 123 */ 65503, 0, 279 /* 125 */ 65496, 65504, 0, 280 /* 128 */ 65489, 32, 65520, 65519, 32, 65520, 0, 281 /* 135 */ 65490, 32, 65520, 65519, 32, 65520, 0, 282 /* 142 */ 65491, 32, 65520, 65519, 32, 65520, 0, 283 /* 149 */ 65492, 32, 65520, 65519, 32, 65520, 0, 284 /* 156 */ 65493, 32, 65520, 65519, 32, 65520, 0, 285 /* 163 */ 65494, 32, 65520, 65519, 32, 65520, 0, 286 /* 170 */ 65495, 32, 65520, 65519, 32, 65520, 0, 287 /* 177 */ 65496, 32, 65520, 65519, 32, 65520, 0, 288 /* 184 */ 65535, 0, 289}; 290 291extern const unsigned SystemZLaneMaskLists[] = { 292 /* 0 */ 0x00000000, ~0u, 293 /* 2 */ 0x00000004, 0x00000002, 0x00000010, 0x00000001, ~0u, 294 /* 7 */ 0x00000008, 0x00000020, ~0u, 295}; 296 297extern const uint16_t SystemZSubRegIdxLists[] = { 298 /* 0 */ 6, 1, 0, 299 /* 3 */ 7, 6, 1, 2, 4, 3, 0, 300 /* 10 */ 7, 8, 2, 5, 0, 301 /* 15 */ 9, 8, 0, 302}; 303 304extern const MCRegisterInfo::SubRegCoveredBits SystemZSubRegIdxRanges[] = { 305 { 65535, 65535 }, 306 { 32, 32 }, // subreg_h32 307 { 64, 64 }, // subreg_h64 308 { 96, 32 }, // subreg_hh32 309 { 64, 32 }, // subreg_hl32 310 { 96, 32 }, // subreg_hr32 311 { 0, 32 }, // subreg_l32 312 { 0, 64 }, // subreg_l64 313 { 32, 32 }, // subreg_r32 314 { 64, 64 }, // subreg_r64 315}; 316 317extern const char SystemZRegStrings[] = { 318 /* 0 */ 'V', '1', '0', 0, 319 /* 4 */ 'V', '2', '0', 0, 320 /* 8 */ 'V', '3', '0', 0, 321 /* 12 */ 'V', '0', 0, 322 /* 15 */ 'V', '1', '1', 0, 323 /* 19 */ 'V', '2', '1', 0, 324 /* 23 */ 'V', '3', '1', 0, 325 /* 27 */ 'V', '1', 0, 326 /* 30 */ 'V', '1', '2', 0, 327 /* 34 */ 'V', '2', '2', 0, 328 /* 38 */ 'V', '2', 0, 329 /* 41 */ 'V', '1', '3', 0, 330 /* 45 */ 'V', '2', '3', 0, 331 /* 49 */ 'V', '3', 0, 332 /* 52 */ 'V', '1', '4', 0, 333 /* 56 */ 'V', '2', '4', 0, 334 /* 60 */ 'V', '4', 0, 335 /* 63 */ 'V', '1', '5', 0, 336 /* 67 */ 'V', '2', '5', 0, 337 /* 71 */ 'V', '5', 0, 338 /* 74 */ 'V', '1', '6', 0, 339 /* 78 */ 'V', '2', '6', 0, 340 /* 82 */ 'V', '6', 0, 341 /* 85 */ 'V', '1', '7', 0, 342 /* 89 */ 'V', '2', '7', 0, 343 /* 93 */ 'V', '7', 0, 344 /* 96 */ 'V', '1', '8', 0, 345 /* 100 */ 'V', '2', '8', 0, 346 /* 104 */ 'V', '8', 0, 347 /* 107 */ 'V', '1', '9', 0, 348 /* 111 */ 'V', '2', '9', 0, 349 /* 115 */ 'V', '9', 0, 350 /* 118 */ 'C', 'C', 0, 351 /* 121 */ 'F', '1', '0', 'D', 0, 352 /* 126 */ 'R', '1', '0', 'D', 0, 353 /* 131 */ 'F', '2', '0', 'D', 0, 354 /* 136 */ 'F', '3', '0', 'D', 0, 355 /* 141 */ 'F', '0', 'D', 0, 356 /* 145 */ 'R', '0', 'D', 0, 357 /* 149 */ 'F', '1', '1', 'D', 0, 358 /* 154 */ 'R', '1', '1', 'D', 0, 359 /* 159 */ 'F', '2', '1', 'D', 0, 360 /* 164 */ 'F', '3', '1', 'D', 0, 361 /* 169 */ 'F', '1', 'D', 0, 362 /* 173 */ 'R', '1', 'D', 0, 363 /* 177 */ 'F', '1', '2', 'D', 0, 364 /* 182 */ 'R', '1', '2', 'D', 0, 365 /* 187 */ 'F', '2', '2', 'D', 0, 366 /* 192 */ 'F', '2', 'D', 0, 367 /* 196 */ 'R', '2', 'D', 0, 368 /* 200 */ 'F', '1', '3', 'D', 0, 369 /* 205 */ 'R', '1', '3', 'D', 0, 370 /* 210 */ 'F', '2', '3', 'D', 0, 371 /* 215 */ 'F', '3', 'D', 0, 372 /* 219 */ 'R', '3', 'D', 0, 373 /* 223 */ 'F', '1', '4', 'D', 0, 374 /* 228 */ 'R', '1', '4', 'D', 0, 375 /* 233 */ 'F', '2', '4', 'D', 0, 376 /* 238 */ 'F', '4', 'D', 0, 377 /* 242 */ 'R', '4', 'D', 0, 378 /* 246 */ 'F', '1', '5', 'D', 0, 379 /* 251 */ 'R', '1', '5', 'D', 0, 380 /* 256 */ 'F', '2', '5', 'D', 0, 381 /* 261 */ 'F', '5', 'D', 0, 382 /* 265 */ 'R', '5', 'D', 0, 383 /* 269 */ 'F', '1', '6', 'D', 0, 384 /* 274 */ 'F', '2', '6', 'D', 0, 385 /* 279 */ 'F', '6', 'D', 0, 386 /* 283 */ 'R', '6', 'D', 0, 387 /* 287 */ 'F', '1', '7', 'D', 0, 388 /* 292 */ 'F', '2', '7', 'D', 0, 389 /* 297 */ 'F', '7', 'D', 0, 390 /* 301 */ 'R', '7', 'D', 0, 391 /* 305 */ 'F', '1', '8', 'D', 0, 392 /* 310 */ 'F', '2', '8', 'D', 0, 393 /* 315 */ 'F', '8', 'D', 0, 394 /* 319 */ 'R', '8', 'D', 0, 395 /* 323 */ 'F', '1', '9', 'D', 0, 396 /* 328 */ 'F', '2', '9', 'D', 0, 397 /* 333 */ 'F', '9', 'D', 0, 398 /* 337 */ 'R', '9', 'D', 0, 399 /* 341 */ 'R', '1', '0', 'H', 0, 400 /* 346 */ 'R', '0', 'H', 0, 401 /* 350 */ 'R', '1', '1', 'H', 0, 402 /* 355 */ 'R', '1', 'H', 0, 403 /* 359 */ 'R', '1', '2', 'H', 0, 404 /* 364 */ 'R', '2', 'H', 0, 405 /* 368 */ 'R', '1', '3', 'H', 0, 406 /* 373 */ 'R', '3', 'H', 0, 407 /* 377 */ 'R', '1', '4', 'H', 0, 408 /* 382 */ 'R', '4', 'H', 0, 409 /* 386 */ 'R', '1', '5', 'H', 0, 410 /* 391 */ 'R', '5', 'H', 0, 411 /* 395 */ 'R', '6', 'H', 0, 412 /* 399 */ 'R', '7', 'H', 0, 413 /* 403 */ 'R', '8', 'H', 0, 414 /* 407 */ 'R', '9', 'H', 0, 415 /* 411 */ 'R', '1', '0', 'L', 0, 416 /* 416 */ 'R', '0', 'L', 0, 417 /* 420 */ 'R', '1', '1', 'L', 0, 418 /* 425 */ 'R', '1', 'L', 0, 419 /* 429 */ 'R', '1', '2', 'L', 0, 420 /* 434 */ 'R', '2', 'L', 0, 421 /* 438 */ 'R', '1', '3', 'L', 0, 422 /* 443 */ 'R', '3', 'L', 0, 423 /* 447 */ 'R', '1', '4', 'L', 0, 424 /* 452 */ 'R', '4', 'L', 0, 425 /* 456 */ 'R', '1', '5', 'L', 0, 426 /* 461 */ 'R', '5', 'L', 0, 427 /* 465 */ 'R', '6', 'L', 0, 428 /* 469 */ 'R', '7', 'L', 0, 429 /* 473 */ 'R', '8', 'L', 0, 430 /* 477 */ 'R', '9', 'L', 0, 431 /* 481 */ 'R', '1', '0', 'Q', 0, 432 /* 486 */ 'F', '0', 'Q', 0, 433 /* 490 */ 'R', '0', 'Q', 0, 434 /* 494 */ 'F', '1', 'Q', 0, 435 /* 498 */ 'F', '1', '2', 'Q', 0, 436 /* 503 */ 'R', '1', '2', 'Q', 0, 437 /* 508 */ 'R', '2', 'Q', 0, 438 /* 512 */ 'F', '1', '3', 'Q', 0, 439 /* 517 */ 'R', '1', '4', 'Q', 0, 440 /* 522 */ 'F', '4', 'Q', 0, 441 /* 526 */ 'R', '4', 'Q', 0, 442 /* 530 */ 'F', '5', 'Q', 0, 443 /* 534 */ 'R', '6', 'Q', 0, 444 /* 538 */ 'F', '8', 'Q', 0, 445 /* 542 */ 'R', '8', 'Q', 0, 446 /* 546 */ 'F', '9', 'Q', 0, 447 /* 550 */ 'F', '1', '0', 'S', 0, 448 /* 555 */ 'F', '2', '0', 'S', 0, 449 /* 560 */ 'F', '3', '0', 'S', 0, 450 /* 565 */ 'F', '0', 'S', 0, 451 /* 569 */ 'F', '1', '1', 'S', 0, 452 /* 574 */ 'F', '2', '1', 'S', 0, 453 /* 579 */ 'F', '3', '1', 'S', 0, 454 /* 584 */ 'F', '1', 'S', 0, 455 /* 588 */ 'F', '1', '2', 'S', 0, 456 /* 593 */ 'F', '2', '2', 'S', 0, 457 /* 598 */ 'F', '2', 'S', 0, 458 /* 602 */ 'F', '1', '3', 'S', 0, 459 /* 607 */ 'F', '2', '3', 'S', 0, 460 /* 612 */ 'F', '3', 'S', 0, 461 /* 616 */ 'F', '1', '4', 'S', 0, 462 /* 621 */ 'F', '2', '4', 'S', 0, 463 /* 626 */ 'F', '4', 'S', 0, 464 /* 630 */ 'F', '1', '5', 'S', 0, 465 /* 635 */ 'F', '2', '5', 'S', 0, 466 /* 640 */ 'F', '5', 'S', 0, 467 /* 644 */ 'F', '1', '6', 'S', 0, 468 /* 649 */ 'F', '2', '6', 'S', 0, 469 /* 654 */ 'F', '6', 'S', 0, 470 /* 658 */ 'F', '1', '7', 'S', 0, 471 /* 663 */ 'F', '2', '7', 'S', 0, 472 /* 668 */ 'F', '7', 'S', 0, 473 /* 672 */ 'F', '1', '8', 'S', 0, 474 /* 677 */ 'F', '2', '8', 'S', 0, 475 /* 682 */ 'F', '8', 'S', 0, 476 /* 686 */ 'F', '1', '9', 'S', 0, 477 /* 691 */ 'F', '2', '9', 'S', 0, 478 /* 696 */ 'F', '9', 'S', 0, 479}; 480 481extern const MCRegisterDesc SystemZRegDesc[] = { // Descriptors 482 { 3, 0, 0, 0, 0, 0 }, 483 { 118, 4, 4, 2, 2945, 0 }, 484 { 12, 20, 4, 15, 2945, 8 }, 485 { 27, 20, 4, 15, 2945, 8 }, 486 { 38, 20, 4, 15, 2945, 8 }, 487 { 49, 20, 4, 15, 2945, 8 }, 488 { 60, 20, 4, 15, 2945, 8 }, 489 { 71, 20, 4, 15, 2945, 8 }, 490 { 82, 20, 4, 15, 2945, 8 }, 491 { 93, 20, 4, 15, 2945, 8 }, 492 { 104, 20, 4, 15, 2945, 8 }, 493 { 115, 20, 4, 15, 2945, 8 }, 494 { 0, 20, 4, 15, 2945, 8 }, 495 { 15, 20, 4, 15, 2945, 8 }, 496 { 30, 20, 4, 15, 2945, 8 }, 497 { 41, 20, 4, 15, 2945, 8 }, 498 { 52, 20, 4, 15, 2945, 8 }, 499 { 63, 20, 4, 15, 2945, 8 }, 500 { 74, 20, 4, 15, 2945, 8 }, 501 { 85, 20, 4, 15, 2945, 8 }, 502 { 96, 20, 4, 15, 2945, 8 }, 503 { 107, 20, 4, 15, 2945, 8 }, 504 { 4, 20, 4, 15, 2945, 8 }, 505 { 19, 20, 4, 15, 2945, 8 }, 506 { 34, 20, 4, 15, 2945, 8 }, 507 { 45, 20, 4, 15, 2945, 8 }, 508 { 56, 20, 4, 15, 2945, 8 }, 509 { 67, 20, 4, 15, 2945, 8 }, 510 { 78, 20, 4, 15, 2945, 8 }, 511 { 89, 20, 4, 15, 2945, 8 }, 512 { 100, 20, 4, 15, 2945, 8 }, 513 { 111, 20, 4, 15, 2945, 8 }, 514 { 8, 20, 4, 15, 2945, 8 }, 515 { 23, 20, 4, 15, 2945, 8 }, 516 { 141, 21, 114, 16, 1969, 8 }, 517 { 169, 21, 114, 16, 1969, 8 }, 518 { 192, 21, 110, 16, 1969, 8 }, 519 { 215, 21, 110, 16, 1969, 8 }, 520 { 238, 21, 110, 16, 1969, 8 }, 521 { 261, 21, 110, 16, 1969, 8 }, 522 { 279, 21, 106, 16, 1969, 8 }, 523 { 297, 21, 106, 16, 1969, 8 }, 524 { 315, 21, 106, 16, 1969, 8 }, 525 { 333, 21, 106, 16, 1969, 8 }, 526 { 121, 21, 102, 16, 1969, 8 }, 527 { 149, 21, 102, 16, 1969, 8 }, 528 { 177, 21, 102, 16, 1969, 8 }, 529 { 200, 21, 102, 16, 1969, 8 }, 530 { 223, 21, 98, 16, 1969, 8 }, 531 { 246, 21, 98, 16, 1969, 8 }, 532 { 269, 21, 126, 16, 1969, 8 }, 533 { 287, 21, 126, 16, 1969, 8 }, 534 { 305, 21, 126, 16, 1969, 8 }, 535 { 323, 21, 126, 16, 1969, 8 }, 536 { 131, 21, 126, 16, 1969, 8 }, 537 { 159, 21, 126, 16, 1969, 8 }, 538 { 187, 21, 126, 16, 1969, 8 }, 539 { 210, 21, 126, 16, 1969, 8 }, 540 { 233, 21, 126, 16, 1969, 8 }, 541 { 256, 21, 126, 16, 1969, 8 }, 542 { 274, 21, 126, 16, 1969, 8 }, 543 { 292, 21, 126, 16, 1969, 8 }, 544 { 310, 21, 126, 16, 1969, 8 }, 545 { 328, 21, 126, 16, 1969, 8 }, 546 { 136, 21, 126, 16, 1969, 8 }, 547 { 164, 21, 126, 16, 1969, 8 }, 548 { 486, 23, 4, 10, 129, 7 }, 549 { 494, 23, 4, 10, 129, 7 }, 550 { 522, 28, 4, 10, 177, 7 }, 551 { 530, 28, 4, 10, 177, 7 }, 552 { 538, 33, 4, 10, 225, 7 }, 553 { 546, 33, 4, 10, 225, 7 }, 554 { 498, 38, 4, 10, 273, 7 }, 555 { 512, 38, 4, 10, 273, 7 }, 556 { 565, 4, 113, 2, 1937, 0 }, 557 { 584, 4, 113, 2, 1937, 0 }, 558 { 598, 4, 109, 2, 1937, 0 }, 559 { 612, 4, 109, 2, 1937, 0 }, 560 { 626, 4, 109, 2, 1937, 0 }, 561 { 640, 4, 109, 2, 1937, 0 }, 562 { 654, 4, 105, 2, 1937, 0 }, 563 { 668, 4, 105, 2, 1937, 0 }, 564 { 682, 4, 105, 2, 1937, 0 }, 565 { 696, 4, 105, 2, 1937, 0 }, 566 { 550, 4, 101, 2, 1937, 0 }, 567 { 569, 4, 101, 2, 1937, 0 }, 568 { 588, 4, 101, 2, 1937, 0 }, 569 { 602, 4, 101, 2, 1937, 0 }, 570 { 616, 4, 97, 2, 1937, 0 }, 571 { 630, 4, 97, 2, 1937, 0 }, 572 { 644, 4, 125, 2, 1937, 0 }, 573 { 658, 4, 125, 2, 1937, 0 }, 574 { 672, 4, 125, 2, 1937, 0 }, 575 { 686, 4, 125, 2, 1937, 0 }, 576 { 555, 4, 125, 2, 1937, 0 }, 577 { 574, 4, 125, 2, 1937, 0 }, 578 { 593, 4, 125, 2, 1937, 0 }, 579 { 607, 4, 125, 2, 1937, 0 }, 580 { 621, 4, 125, 2, 1937, 0 }, 581 { 635, 4, 125, 2, 1937, 0 }, 582 { 649, 4, 125, 2, 1937, 0 }, 583 { 663, 4, 125, 2, 1937, 0 }, 584 { 677, 4, 125, 2, 1937, 0 }, 585 { 691, 4, 125, 2, 1937, 0 }, 586 { 560, 4, 125, 2, 1937, 0 }, 587 { 579, 4, 125, 2, 1937, 0 }, 588 { 145, 132, 92, 0, 82, 4 }, 589 { 173, 132, 86, 0, 82, 4 }, 590 { 196, 132, 86, 0, 82, 4 }, 591 { 219, 132, 80, 0, 82, 4 }, 592 { 242, 132, 80, 0, 82, 4 }, 593 { 265, 132, 74, 0, 82, 4 }, 594 { 283, 132, 74, 0, 82, 4 }, 595 { 301, 132, 68, 0, 82, 4 }, 596 { 319, 132, 68, 0, 82, 4 }, 597 { 337, 132, 62, 0, 82, 4 }, 598 { 126, 132, 62, 0, 82, 4 }, 599 { 154, 132, 56, 0, 82, 4 }, 600 { 182, 132, 56, 0, 82, 4 }, 601 { 205, 132, 50, 0, 82, 4 }, 602 { 228, 132, 50, 0, 82, 4 }, 603 { 251, 132, 21, 0, 82, 4 }, 604 { 346, 4, 94, 2, 1906, 0 }, 605 { 355, 4, 88, 2, 1906, 0 }, 606 { 364, 4, 88, 2, 1906, 0 }, 607 { 373, 4, 82, 2, 1906, 0 }, 608 { 382, 4, 82, 2, 1906, 0 }, 609 { 391, 4, 76, 2, 1906, 0 }, 610 { 395, 4, 76, 2, 1906, 0 }, 611 { 399, 4, 70, 2, 1906, 0 }, 612 { 403, 4, 70, 2, 1906, 0 }, 613 { 407, 4, 64, 2, 1906, 0 }, 614 { 341, 4, 64, 2, 1906, 0 }, 615 { 350, 4, 58, 2, 1906, 0 }, 616 { 359, 4, 58, 2, 1906, 0 }, 617 { 368, 4, 52, 2, 1906, 0 }, 618 { 377, 4, 52, 2, 1906, 0 }, 619 { 386, 4, 46, 2, 1906, 0 }, 620 { 416, 4, 91, 2, 1874, 0 }, 621 { 425, 4, 85, 2, 1874, 0 }, 622 { 434, 4, 85, 2, 1874, 0 }, 623 { 443, 4, 79, 2, 1874, 0 }, 624 { 452, 4, 79, 2, 1874, 0 }, 625 { 461, 4, 73, 2, 1874, 0 }, 626 { 465, 4, 73, 2, 1874, 0 }, 627 { 469, 4, 67, 2, 1874, 0 }, 628 { 473, 4, 67, 2, 1874, 0 }, 629 { 477, 4, 61, 2, 1874, 0 }, 630 { 411, 4, 61, 2, 1874, 0 }, 631 { 420, 4, 55, 2, 1874, 0 }, 632 { 429, 4, 55, 2, 1874, 0 }, 633 { 438, 4, 49, 2, 1874, 0 }, 634 { 447, 4, 49, 2, 1874, 0 }, 635 { 456, 4, 43, 2, 1874, 0 }, 636 { 490, 128, 4, 3, 4, 2 }, 637 { 508, 135, 4, 3, 4, 2 }, 638 { 526, 142, 4, 3, 4, 2 }, 639 { 534, 149, 4, 3, 4, 2 }, 640 { 542, 156, 4, 3, 4, 2 }, 641 { 481, 163, 4, 3, 4, 2 }, 642 { 503, 170, 4, 3, 4, 2 }, 643 { 517, 177, 4, 3, 4, 2 }, 644}; 645 646extern const MCPhysReg SystemZRegUnitRoots[][2] = { 647 { SystemZ::CC }, 648 { SystemZ::F0S }, 649 { SystemZ::F1S }, 650 { SystemZ::F2S }, 651 { SystemZ::F3S }, 652 { SystemZ::F4S }, 653 { SystemZ::F5S }, 654 { SystemZ::F6S }, 655 { SystemZ::F7S }, 656 { SystemZ::F8S }, 657 { SystemZ::F9S }, 658 { SystemZ::F10S }, 659 { SystemZ::F11S }, 660 { SystemZ::F12S }, 661 { SystemZ::F13S }, 662 { SystemZ::F14S }, 663 { SystemZ::F15S }, 664 { SystemZ::F16S }, 665 { SystemZ::F17S }, 666 { SystemZ::F18S }, 667 { SystemZ::F19S }, 668 { SystemZ::F20S }, 669 { SystemZ::F21S }, 670 { SystemZ::F22S }, 671 { SystemZ::F23S }, 672 { SystemZ::F24S }, 673 { SystemZ::F25S }, 674 { SystemZ::F26S }, 675 { SystemZ::F27S }, 676 { SystemZ::F28S }, 677 { SystemZ::F29S }, 678 { SystemZ::F30S }, 679 { SystemZ::F31S }, 680 { SystemZ::R0L }, 681 { SystemZ::R0H }, 682 { SystemZ::R1L }, 683 { SystemZ::R1H }, 684 { SystemZ::R2L }, 685 { SystemZ::R2H }, 686 { SystemZ::R3L }, 687 { SystemZ::R3H }, 688 { SystemZ::R4L }, 689 { SystemZ::R4H }, 690 { SystemZ::R5L }, 691 { SystemZ::R5H }, 692 { SystemZ::R6L }, 693 { SystemZ::R6H }, 694 { SystemZ::R7L }, 695 { SystemZ::R7H }, 696 { SystemZ::R8L }, 697 { SystemZ::R8H }, 698 { SystemZ::R9L }, 699 { SystemZ::R9H }, 700 { SystemZ::R10L }, 701 { SystemZ::R10H }, 702 { SystemZ::R11L }, 703 { SystemZ::R11H }, 704 { SystemZ::R12L }, 705 { SystemZ::R12H }, 706 { SystemZ::R13L }, 707 { SystemZ::R13H }, 708 { SystemZ::R14L }, 709 { SystemZ::R14H }, 710 { SystemZ::R15L }, 711 { SystemZ::R15H }, 712}; 713 714namespace { // Register classes... 715 // GRX32Bit Register Class... 716 const MCPhysReg GRX32Bit[] = { 717 SystemZ::R0L, SystemZ::R1L, SystemZ::R2L, SystemZ::R3L, SystemZ::R4L, SystemZ::R5L, SystemZ::R0H, SystemZ::R1H, SystemZ::R2H, SystemZ::R3H, SystemZ::R4H, SystemZ::R5H, SystemZ::R15L, SystemZ::R15H, SystemZ::R14L, SystemZ::R14H, SystemZ::R13L, SystemZ::R13H, SystemZ::R12L, SystemZ::R12H, SystemZ::R11L, SystemZ::R11H, SystemZ::R10L, SystemZ::R10H, SystemZ::R9L, SystemZ::R9H, SystemZ::R8L, SystemZ::R8H, SystemZ::R7L, SystemZ::R7H, SystemZ::R6L, SystemZ::R6H, 718 }; 719 720 // GRX32Bit Bit set. 721 const uint8_t GRX32BitBits[] = { 722 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0xff, 0xff, 0x03, 723 }; 724 725 // VR32Bit Register Class... 726 const MCPhysReg VR32Bit[] = { 727 SystemZ::F0S, SystemZ::F1S, SystemZ::F2S, SystemZ::F3S, SystemZ::F4S, SystemZ::F5S, SystemZ::F6S, SystemZ::F7S, SystemZ::F16S, SystemZ::F17S, SystemZ::F18S, SystemZ::F19S, SystemZ::F20S, SystemZ::F21S, SystemZ::F22S, SystemZ::F23S, SystemZ::F24S, SystemZ::F25S, SystemZ::F26S, SystemZ::F27S, SystemZ::F28S, SystemZ::F29S, SystemZ::F30S, SystemZ::F31S, SystemZ::F8S, SystemZ::F9S, SystemZ::F10S, SystemZ::F11S, SystemZ::F12S, SystemZ::F13S, SystemZ::F14S, SystemZ::F15S, 728 }; 729 730 // VR32Bit Bit set. 731 const uint8_t VR32BitBits[] = { 732 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0xff, 0xff, 0x03, 733 }; 734 735 // FP32Bit Register Class... 736 const MCPhysReg FP32Bit[] = { 737 SystemZ::F0S, SystemZ::F1S, SystemZ::F2S, SystemZ::F3S, SystemZ::F4S, SystemZ::F5S, SystemZ::F6S, SystemZ::F7S, SystemZ::F8S, SystemZ::F9S, SystemZ::F10S, SystemZ::F11S, SystemZ::F12S, SystemZ::F13S, SystemZ::F14S, SystemZ::F15S, 738 }; 739 740 // FP32Bit Bit set. 741 const uint8_t FP32BitBits[] = { 742 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03, 743 }; 744 745 // GR32Bit Register Class... 746 const MCPhysReg GR32Bit[] = { 747 SystemZ::R0L, SystemZ::R1L, SystemZ::R2L, SystemZ::R3L, SystemZ::R4L, SystemZ::R5L, SystemZ::R15L, SystemZ::R14L, SystemZ::R13L, SystemZ::R12L, SystemZ::R11L, SystemZ::R10L, SystemZ::R9L, SystemZ::R8L, SystemZ::R7L, SystemZ::R6L, 748 }; 749 750 // GR32Bit Bit set. 751 const uint8_t GR32BitBits[] = { 752 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03, 753 }; 754 755 // GRH32Bit Register Class... 756 const MCPhysReg GRH32Bit[] = { 757 SystemZ::R0H, SystemZ::R1H, SystemZ::R2H, SystemZ::R3H, SystemZ::R4H, SystemZ::R5H, SystemZ::R15H, SystemZ::R14H, SystemZ::R13H, SystemZ::R12H, SystemZ::R11H, SystemZ::R10H, SystemZ::R9H, SystemZ::R8H, SystemZ::R7H, SystemZ::R6H, 758 }; 759 760 // GRH32Bit Bit set. 761 const uint8_t GRH32BitBits[] = { 762 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03, 763 }; 764 765 // ADDR32Bit Register Class... 766 const MCPhysReg ADDR32Bit[] = { 767 SystemZ::R1L, SystemZ::R2L, SystemZ::R3L, SystemZ::R4L, SystemZ::R5L, SystemZ::R15L, SystemZ::R14L, SystemZ::R13L, SystemZ::R12L, SystemZ::R11L, SystemZ::R10L, SystemZ::R9L, SystemZ::R8L, SystemZ::R7L, SystemZ::R6L, 768 }; 769 770 // ADDR32Bit Bit set. 771 const uint8_t ADDR32BitBits[] = { 772 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x03, 773 }; 774 775 // CCRegs Register Class... 776 const MCPhysReg CCRegs[] = { 777 SystemZ::CC, 778 }; 779 780 // CCRegs Bit set. 781 const uint8_t CCRegsBits[] = { 782 0x02, 783 }; 784 785 // VR64Bit Register Class... 786 const MCPhysReg VR64Bit[] = { 787 SystemZ::F0D, SystemZ::F1D, SystemZ::F2D, SystemZ::F3D, SystemZ::F4D, SystemZ::F5D, SystemZ::F6D, SystemZ::F7D, SystemZ::F16D, SystemZ::F17D, SystemZ::F18D, SystemZ::F19D, SystemZ::F20D, SystemZ::F21D, SystemZ::F22D, SystemZ::F23D, SystemZ::F24D, SystemZ::F25D, SystemZ::F26D, SystemZ::F27D, SystemZ::F28D, SystemZ::F29D, SystemZ::F30D, SystemZ::F31D, SystemZ::F8D, SystemZ::F9D, SystemZ::F10D, SystemZ::F11D, SystemZ::F12D, SystemZ::F13D, SystemZ::F14D, SystemZ::F15D, 788 }; 789 790 // VR64Bit Bit set. 791 const uint8_t VR64BitBits[] = { 792 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0xff, 0xff, 0x03, 793 }; 794 795 // FP64Bit Register Class... 796 const MCPhysReg FP64Bit[] = { 797 SystemZ::F0D, SystemZ::F1D, SystemZ::F2D, SystemZ::F3D, SystemZ::F4D, SystemZ::F5D, SystemZ::F6D, SystemZ::F7D, SystemZ::F8D, SystemZ::F9D, SystemZ::F10D, SystemZ::F11D, SystemZ::F12D, SystemZ::F13D, SystemZ::F14D, SystemZ::F15D, 798 }; 799 800 // FP64Bit Bit set. 801 const uint8_t FP64BitBits[] = { 802 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03, 803 }; 804 805 // GR64Bit Register Class... 806 const MCPhysReg GR64Bit[] = { 807 SystemZ::R0D, SystemZ::R1D, SystemZ::R2D, SystemZ::R3D, SystemZ::R4D, SystemZ::R5D, SystemZ::R15D, SystemZ::R14D, SystemZ::R13D, SystemZ::R12D, SystemZ::R11D, SystemZ::R10D, SystemZ::R9D, SystemZ::R8D, SystemZ::R7D, SystemZ::R6D, 808 }; 809 810 // GR64Bit Bit set. 811 const uint8_t GR64BitBits[] = { 812 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03, 813 }; 814 815 // ADDR64Bit Register Class... 816 const MCPhysReg ADDR64Bit[] = { 817 SystemZ::R1D, SystemZ::R2D, SystemZ::R3D, SystemZ::R4D, SystemZ::R5D, SystemZ::R15D, SystemZ::R14D, SystemZ::R13D, SystemZ::R12D, SystemZ::R11D, SystemZ::R10D, SystemZ::R9D, SystemZ::R8D, SystemZ::R7D, SystemZ::R6D, 818 }; 819 820 // ADDR64Bit Bit set. 821 const uint8_t ADDR64BitBits[] = { 822 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x03, 823 }; 824 825 // VR128Bit Register Class... 826 const MCPhysReg VR128Bit[] = { 827 SystemZ::V0, SystemZ::V1, SystemZ::V2, SystemZ::V3, SystemZ::V4, SystemZ::V5, SystemZ::V6, SystemZ::V7, SystemZ::V16, SystemZ::V17, SystemZ::V18, SystemZ::V19, SystemZ::V20, SystemZ::V21, SystemZ::V22, SystemZ::V23, SystemZ::V24, SystemZ::V25, SystemZ::V26, SystemZ::V27, SystemZ::V28, SystemZ::V29, SystemZ::V30, SystemZ::V31, SystemZ::V8, SystemZ::V9, SystemZ::V10, SystemZ::V11, SystemZ::V12, SystemZ::V13, SystemZ::V14, SystemZ::V15, 828 }; 829 830 // VR128Bit Bit set. 831 const uint8_t VR128BitBits[] = { 832 0xfc, 0xff, 0xff, 0xff, 0x03, 833 }; 834 835 // VF128Bit Register Class... 836 const MCPhysReg VF128Bit[] = { 837 SystemZ::V0, SystemZ::V1, SystemZ::V2, SystemZ::V3, SystemZ::V4, SystemZ::V5, SystemZ::V6, SystemZ::V7, SystemZ::V8, SystemZ::V9, SystemZ::V10, SystemZ::V11, SystemZ::V12, SystemZ::V13, SystemZ::V14, SystemZ::V15, 838 }; 839 840 // VF128Bit Bit set. 841 const uint8_t VF128BitBits[] = { 842 0xfc, 0xff, 0x03, 843 }; 844 845 // FP128Bit Register Class... 846 const MCPhysReg FP128Bit[] = { 847 SystemZ::F0Q, SystemZ::F1Q, SystemZ::F4Q, SystemZ::F5Q, SystemZ::F8Q, SystemZ::F9Q, SystemZ::F12Q, SystemZ::F13Q, 848 }; 849 850 // FP128Bit Bit set. 851 const uint8_t FP128BitBits[] = { 852 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03, 853 }; 854 855 // GR128Bit Register Class... 856 const MCPhysReg GR128Bit[] = { 857 SystemZ::R0Q, SystemZ::R2Q, SystemZ::R4Q, SystemZ::R12Q, SystemZ::R10Q, SystemZ::R8Q, SystemZ::R6Q, SystemZ::R14Q, 858 }; 859 860 // GR128Bit Bit set. 861 const uint8_t GR128BitBits[] = { 862 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03, 863 }; 864 865 // ADDR128Bit Register Class... 866 const MCPhysReg ADDR128Bit[] = { 867 SystemZ::R2Q, SystemZ::R4Q, SystemZ::R12Q, SystemZ::R10Q, SystemZ::R8Q, SystemZ::R6Q, SystemZ::R14Q, 868 }; 869 870 // ADDR128Bit Bit set. 871 const uint8_t ADDR128BitBits[] = { 872 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x03, 873 }; 874 875} 876 877extern const char SystemZRegClassStrings[] = { 878 /* 0 */ 'C', 'C', 'R', 'e', 'g', 's', 0, 879 /* 7 */ 'G', 'R', 'H', '3', '2', 'B', 'i', 't', 0, 880 /* 16 */ 'F', 'P', '3', '2', 'B', 'i', 't', 0, 881 /* 24 */ 'A', 'D', 'D', 'R', '3', '2', 'B', 'i', 't', 0, 882 /* 34 */ 'G', 'R', '3', '2', 'B', 'i', 't', 0, 883 /* 42 */ 'V', 'R', '3', '2', 'B', 'i', 't', 0, 884 /* 50 */ 'G', 'R', 'X', '3', '2', 'B', 'i', 't', 0, 885 /* 59 */ 'F', 'P', '6', '4', 'B', 'i', 't', 0, 886 /* 67 */ 'A', 'D', 'D', 'R', '6', '4', 'B', 'i', 't', 0, 887 /* 77 */ 'G', 'R', '6', '4', 'B', 'i', 't', 0, 888 /* 85 */ 'V', 'R', '6', '4', 'B', 'i', 't', 0, 889 /* 93 */ 'V', 'F', '1', '2', '8', 'B', 'i', 't', 0, 890 /* 102 */ 'F', 'P', '1', '2', '8', 'B', 'i', 't', 0, 891 /* 111 */ 'A', 'D', 'D', 'R', '1', '2', '8', 'B', 'i', 't', 0, 892 /* 122 */ 'G', 'R', '1', '2', '8', 'B', 'i', 't', 0, 893 /* 131 */ 'V', 'R', '1', '2', '8', 'B', 'i', 't', 0, 894}; 895 896extern const MCRegisterClass SystemZMCRegisterClasses[] = { 897 { GRX32Bit, GRX32BitBits, 50, 32, sizeof(GRX32BitBits), SystemZ::GRX32BitRegClassID, 4, 4, 1, 1 }, 898 { VR32Bit, VR32BitBits, 42, 32, sizeof(VR32BitBits), SystemZ::VR32BitRegClassID, 4, 4, 1, 1 }, 899 { FP32Bit, FP32BitBits, 16, 16, sizeof(FP32BitBits), SystemZ::FP32BitRegClassID, 4, 4, 1, 1 }, 900 { GR32Bit, GR32BitBits, 34, 16, sizeof(GR32BitBits), SystemZ::GR32BitRegClassID, 4, 4, 1, 1 }, 901 { GRH32Bit, GRH32BitBits, 7, 16, sizeof(GRH32BitBits), SystemZ::GRH32BitRegClassID, 4, 4, 1, 1 }, 902 { ADDR32Bit, ADDR32BitBits, 24, 15, sizeof(ADDR32BitBits), SystemZ::ADDR32BitRegClassID, 4, 4, 1, 1 }, 903 { CCRegs, CCRegsBits, 0, 1, sizeof(CCRegsBits), SystemZ::CCRegsRegClassID, 4, 4, 1, 0 }, 904 { VR64Bit, VR64BitBits, 85, 32, sizeof(VR64BitBits), SystemZ::VR64BitRegClassID, 8, 8, 1, 1 }, 905 { FP64Bit, FP64BitBits, 59, 16, sizeof(FP64BitBits), SystemZ::FP64BitRegClassID, 8, 8, 1, 1 }, 906 { GR64Bit, GR64BitBits, 77, 16, sizeof(GR64BitBits), SystemZ::GR64BitRegClassID, 8, 8, 1, 1 }, 907 { ADDR64Bit, ADDR64BitBits, 67, 15, sizeof(ADDR64BitBits), SystemZ::ADDR64BitRegClassID, 8, 8, 1, 1 }, 908 { VR128Bit, VR128BitBits, 131, 32, sizeof(VR128BitBits), SystemZ::VR128BitRegClassID, 16, 16, 1, 1 }, 909 { VF128Bit, VF128BitBits, 93, 16, sizeof(VF128BitBits), SystemZ::VF128BitRegClassID, 16, 16, 1, 1 }, 910 { FP128Bit, FP128BitBits, 102, 8, sizeof(FP128BitBits), SystemZ::FP128BitRegClassID, 16, 16, 1, 1 }, 911 { GR128Bit, GR128BitBits, 122, 8, sizeof(GR128BitBits), SystemZ::GR128BitRegClassID, 16, 16, 1, 1 }, 912 { ADDR128Bit, ADDR128BitBits, 111, 7, sizeof(ADDR128BitBits), SystemZ::ADDR128BitRegClassID, 16, 16, 1, 1 }, 913}; 914 915// SystemZ Dwarf<->LLVM register mappings. 916extern const MCRegisterInfo::DwarfLLVMRegPair SystemZDwarfFlavour0Dwarf2L[] = { 917 { 0U, SystemZ::R0D }, 918 { 1U, SystemZ::R1D }, 919 { 2U, SystemZ::R2D }, 920 { 3U, SystemZ::R3D }, 921 { 4U, SystemZ::R4D }, 922 { 5U, SystemZ::R5D }, 923 { 6U, SystemZ::R6D }, 924 { 7U, SystemZ::R7D }, 925 { 8U, SystemZ::R8D }, 926 { 9U, SystemZ::R9D }, 927 { 10U, SystemZ::R10D }, 928 { 11U, SystemZ::R11D }, 929 { 12U, SystemZ::R12D }, 930 { 13U, SystemZ::R13D }, 931 { 14U, SystemZ::R14D }, 932 { 15U, SystemZ::R15D }, 933 { 16U, SystemZ::F0D }, 934 { 17U, SystemZ::F2D }, 935 { 18U, SystemZ::F4D }, 936 { 19U, SystemZ::F6D }, 937 { 20U, SystemZ::F1D }, 938 { 21U, SystemZ::F3D }, 939 { 22U, SystemZ::F5D }, 940 { 23U, SystemZ::F7D }, 941 { 24U, SystemZ::F8D }, 942 { 25U, SystemZ::F10D }, 943 { 26U, SystemZ::F12D }, 944 { 27U, SystemZ::F14D }, 945 { 28U, SystemZ::F9D }, 946 { 29U, SystemZ::F11D }, 947 { 30U, SystemZ::F13D }, 948 { 31U, SystemZ::F15D }, 949 { 68U, SystemZ::F16D }, 950 { 69U, SystemZ::F18D }, 951 { 70U, SystemZ::F20D }, 952 { 71U, SystemZ::F22D }, 953 { 72U, SystemZ::F17D }, 954 { 73U, SystemZ::F19D }, 955 { 74U, SystemZ::F21D }, 956 { 75U, SystemZ::F23D }, 957 { 76U, SystemZ::F24D }, 958 { 77U, SystemZ::F26D }, 959 { 78U, SystemZ::F28D }, 960 { 79U, SystemZ::F30D }, 961 { 80U, SystemZ::F25D }, 962 { 81U, SystemZ::F27D }, 963 { 82U, SystemZ::F29D }, 964 { 83U, SystemZ::F31D }, 965}; 966extern const unsigned SystemZDwarfFlavour0Dwarf2LSize = array_lengthof(SystemZDwarfFlavour0Dwarf2L); 967 968extern const MCRegisterInfo::DwarfLLVMRegPair SystemZEHFlavour0Dwarf2L[] = { 969 { 0U, SystemZ::R0D }, 970 { 1U, SystemZ::R1D }, 971 { 2U, SystemZ::R2D }, 972 { 3U, SystemZ::R3D }, 973 { 4U, SystemZ::R4D }, 974 { 5U, SystemZ::R5D }, 975 { 6U, SystemZ::R6D }, 976 { 7U, SystemZ::R7D }, 977 { 8U, SystemZ::R8D }, 978 { 9U, SystemZ::R9D }, 979 { 10U, SystemZ::R10D }, 980 { 11U, SystemZ::R11D }, 981 { 12U, SystemZ::R12D }, 982 { 13U, SystemZ::R13D }, 983 { 14U, SystemZ::R14D }, 984 { 15U, SystemZ::R15D }, 985 { 16U, SystemZ::F0D }, 986 { 17U, SystemZ::F2D }, 987 { 18U, SystemZ::F4D }, 988 { 19U, SystemZ::F6D }, 989 { 20U, SystemZ::F1D }, 990 { 21U, SystemZ::F3D }, 991 { 22U, SystemZ::F5D }, 992 { 23U, SystemZ::F7D }, 993 { 24U, SystemZ::F8D }, 994 { 25U, SystemZ::F10D }, 995 { 26U, SystemZ::F12D }, 996 { 27U, SystemZ::F14D }, 997 { 28U, SystemZ::F9D }, 998 { 29U, SystemZ::F11D }, 999 { 30U, SystemZ::F13D }, 1000 { 31U, SystemZ::F15D }, 1001 { 68U, SystemZ::F16D }, 1002 { 69U, SystemZ::F18D }, 1003 { 70U, SystemZ::F20D }, 1004 { 71U, SystemZ::F22D }, 1005 { 72U, SystemZ::F17D }, 1006 { 73U, SystemZ::F19D }, 1007 { 74U, SystemZ::F21D }, 1008 { 75U, SystemZ::F23D }, 1009 { 76U, SystemZ::F24D }, 1010 { 77U, SystemZ::F26D }, 1011 { 78U, SystemZ::F28D }, 1012 { 79U, SystemZ::F30D }, 1013 { 80U, SystemZ::F25D }, 1014 { 81U, SystemZ::F27D }, 1015 { 82U, SystemZ::F29D }, 1016 { 83U, SystemZ::F31D }, 1017}; 1018extern const unsigned SystemZEHFlavour0Dwarf2LSize = array_lengthof(SystemZEHFlavour0Dwarf2L); 1019 1020extern const MCRegisterInfo::DwarfLLVMRegPair SystemZDwarfFlavour0L2Dwarf[] = { 1021 { SystemZ::V0, 16U }, 1022 { SystemZ::V1, 20U }, 1023 { SystemZ::V2, 17U }, 1024 { SystemZ::V3, 21U }, 1025 { SystemZ::V4, 18U }, 1026 { SystemZ::V5, 22U }, 1027 { SystemZ::V6, 19U }, 1028 { SystemZ::V7, 23U }, 1029 { SystemZ::V8, 24U }, 1030 { SystemZ::V9, 28U }, 1031 { SystemZ::V10, 25U }, 1032 { SystemZ::V11, 29U }, 1033 { SystemZ::V12, 26U }, 1034 { SystemZ::V13, 30U }, 1035 { SystemZ::V14, 27U }, 1036 { SystemZ::V15, 31U }, 1037 { SystemZ::V16, 68U }, 1038 { SystemZ::V17, 72U }, 1039 { SystemZ::V18, 69U }, 1040 { SystemZ::V19, 73U }, 1041 { SystemZ::V20, 70U }, 1042 { SystemZ::V21, 74U }, 1043 { SystemZ::V22, 71U }, 1044 { SystemZ::V23, 75U }, 1045 { SystemZ::V24, 76U }, 1046 { SystemZ::V25, 80U }, 1047 { SystemZ::V26, 77U }, 1048 { SystemZ::V27, 81U }, 1049 { SystemZ::V28, 78U }, 1050 { SystemZ::V29, 82U }, 1051 { SystemZ::V30, 79U }, 1052 { SystemZ::V31, 83U }, 1053 { SystemZ::F0D, 16U }, 1054 { SystemZ::F1D, 20U }, 1055 { SystemZ::F2D, 17U }, 1056 { SystemZ::F3D, 21U }, 1057 { SystemZ::F4D, 18U }, 1058 { SystemZ::F5D, 22U }, 1059 { SystemZ::F6D, 19U }, 1060 { SystemZ::F7D, 23U }, 1061 { SystemZ::F8D, 24U }, 1062 { SystemZ::F9D, 28U }, 1063 { SystemZ::F10D, 25U }, 1064 { SystemZ::F11D, 29U }, 1065 { SystemZ::F12D, 26U }, 1066 { SystemZ::F13D, 30U }, 1067 { SystemZ::F14D, 27U }, 1068 { SystemZ::F15D, 31U }, 1069 { SystemZ::F16D, 68U }, 1070 { SystemZ::F17D, 72U }, 1071 { SystemZ::F18D, 69U }, 1072 { SystemZ::F19D, 73U }, 1073 { SystemZ::F20D, 70U }, 1074 { SystemZ::F21D, 74U }, 1075 { SystemZ::F22D, 71U }, 1076 { SystemZ::F23D, 75U }, 1077 { SystemZ::F24D, 76U }, 1078 { SystemZ::F25D, 80U }, 1079 { SystemZ::F26D, 77U }, 1080 { SystemZ::F27D, 81U }, 1081 { SystemZ::F28D, 78U }, 1082 { SystemZ::F29D, 82U }, 1083 { SystemZ::F30D, 79U }, 1084 { SystemZ::F31D, 83U }, 1085 { SystemZ::R0D, 0U }, 1086 { SystemZ::R1D, 1U }, 1087 { SystemZ::R2D, 2U }, 1088 { SystemZ::R3D, 3U }, 1089 { SystemZ::R4D, 4U }, 1090 { SystemZ::R5D, 5U }, 1091 { SystemZ::R6D, 6U }, 1092 { SystemZ::R7D, 7U }, 1093 { SystemZ::R8D, 8U }, 1094 { SystemZ::R9D, 9U }, 1095 { SystemZ::R10D, 10U }, 1096 { SystemZ::R11D, 11U }, 1097 { SystemZ::R12D, 12U }, 1098 { SystemZ::R13D, 13U }, 1099 { SystemZ::R14D, 14U }, 1100 { SystemZ::R15D, 15U }, 1101}; 1102extern const unsigned SystemZDwarfFlavour0L2DwarfSize = array_lengthof(SystemZDwarfFlavour0L2Dwarf); 1103 1104extern const MCRegisterInfo::DwarfLLVMRegPair SystemZEHFlavour0L2Dwarf[] = { 1105 { SystemZ::V0, 16U }, 1106 { SystemZ::V1, 20U }, 1107 { SystemZ::V2, 17U }, 1108 { SystemZ::V3, 21U }, 1109 { SystemZ::V4, 18U }, 1110 { SystemZ::V5, 22U }, 1111 { SystemZ::V6, 19U }, 1112 { SystemZ::V7, 23U }, 1113 { SystemZ::V8, 24U }, 1114 { SystemZ::V9, 28U }, 1115 { SystemZ::V10, 25U }, 1116 { SystemZ::V11, 29U }, 1117 { SystemZ::V12, 26U }, 1118 { SystemZ::V13, 30U }, 1119 { SystemZ::V14, 27U }, 1120 { SystemZ::V15, 31U }, 1121 { SystemZ::V16, 68U }, 1122 { SystemZ::V17, 72U }, 1123 { SystemZ::V18, 69U }, 1124 { SystemZ::V19, 73U }, 1125 { SystemZ::V20, 70U }, 1126 { SystemZ::V21, 74U }, 1127 { SystemZ::V22, 71U }, 1128 { SystemZ::V23, 75U }, 1129 { SystemZ::V24, 76U }, 1130 { SystemZ::V25, 80U }, 1131 { SystemZ::V26, 77U }, 1132 { SystemZ::V27, 81U }, 1133 { SystemZ::V28, 78U }, 1134 { SystemZ::V29, 82U }, 1135 { SystemZ::V30, 79U }, 1136 { SystemZ::V31, 83U }, 1137 { SystemZ::F0D, 16U }, 1138 { SystemZ::F1D, 20U }, 1139 { SystemZ::F2D, 17U }, 1140 { SystemZ::F3D, 21U }, 1141 { SystemZ::F4D, 18U }, 1142 { SystemZ::F5D, 22U }, 1143 { SystemZ::F6D, 19U }, 1144 { SystemZ::F7D, 23U }, 1145 { SystemZ::F8D, 24U }, 1146 { SystemZ::F9D, 28U }, 1147 { SystemZ::F10D, 25U }, 1148 { SystemZ::F11D, 29U }, 1149 { SystemZ::F12D, 26U }, 1150 { SystemZ::F13D, 30U }, 1151 { SystemZ::F14D, 27U }, 1152 { SystemZ::F15D, 31U }, 1153 { SystemZ::F16D, 68U }, 1154 { SystemZ::F17D, 72U }, 1155 { SystemZ::F18D, 69U }, 1156 { SystemZ::F19D, 73U }, 1157 { SystemZ::F20D, 70U }, 1158 { SystemZ::F21D, 74U }, 1159 { SystemZ::F22D, 71U }, 1160 { SystemZ::F23D, 75U }, 1161 { SystemZ::F24D, 76U }, 1162 { SystemZ::F25D, 80U }, 1163 { SystemZ::F26D, 77U }, 1164 { SystemZ::F27D, 81U }, 1165 { SystemZ::F28D, 78U }, 1166 { SystemZ::F29D, 82U }, 1167 { SystemZ::F30D, 79U }, 1168 { SystemZ::F31D, 83U }, 1169 { SystemZ::R0D, 0U }, 1170 { SystemZ::R1D, 1U }, 1171 { SystemZ::R2D, 2U }, 1172 { SystemZ::R3D, 3U }, 1173 { SystemZ::R4D, 4U }, 1174 { SystemZ::R5D, 5U }, 1175 { SystemZ::R6D, 6U }, 1176 { SystemZ::R7D, 7U }, 1177 { SystemZ::R8D, 8U }, 1178 { SystemZ::R9D, 9U }, 1179 { SystemZ::R10D, 10U }, 1180 { SystemZ::R11D, 11U }, 1181 { SystemZ::R12D, 12U }, 1182 { SystemZ::R13D, 13U }, 1183 { SystemZ::R14D, 14U }, 1184 { SystemZ::R15D, 15U }, 1185}; 1186extern const unsigned SystemZEHFlavour0L2DwarfSize = array_lengthof(SystemZEHFlavour0L2Dwarf); 1187 1188extern const uint16_t SystemZRegEncodingTable[] = { 1189 0, 1190 0, 1191 0, 1192 1, 1193 2, 1194 3, 1195 4, 1196 5, 1197 6, 1198 7, 1199 8, 1200 9, 1201 10, 1202 11, 1203 12, 1204 13, 1205 14, 1206 15, 1207 16, 1208 17, 1209 18, 1210 19, 1211 20, 1212 21, 1213 22, 1214 23, 1215 24, 1216 25, 1217 26, 1218 27, 1219 28, 1220 29, 1221 30, 1222 31, 1223 0, 1224 1, 1225 2, 1226 3, 1227 4, 1228 5, 1229 6, 1230 7, 1231 8, 1232 9, 1233 10, 1234 11, 1235 12, 1236 13, 1237 14, 1238 15, 1239 16, 1240 17, 1241 18, 1242 19, 1243 20, 1244 21, 1245 22, 1246 23, 1247 24, 1248 25, 1249 26, 1250 27, 1251 28, 1252 29, 1253 30, 1254 31, 1255 0, 1256 1, 1257 4, 1258 5, 1259 8, 1260 9, 1261 12, 1262 13, 1263 0, 1264 1, 1265 2, 1266 3, 1267 4, 1268 5, 1269 6, 1270 7, 1271 8, 1272 9, 1273 10, 1274 11, 1275 12, 1276 13, 1277 14, 1278 15, 1279 16, 1280 17, 1281 18, 1282 19, 1283 20, 1284 21, 1285 22, 1286 23, 1287 24, 1288 25, 1289 26, 1290 27, 1291 28, 1292 29, 1293 30, 1294 31, 1295 0, 1296 1, 1297 2, 1298 3, 1299 4, 1300 5, 1301 6, 1302 7, 1303 8, 1304 9, 1305 10, 1306 11, 1307 12, 1308 13, 1309 14, 1310 15, 1311 0, 1312 1, 1313 2, 1314 3, 1315 4, 1316 5, 1317 6, 1318 7, 1319 8, 1320 9, 1321 10, 1322 11, 1323 12, 1324 13, 1325 14, 1326 15, 1327 0, 1328 1, 1329 2, 1330 3, 1331 4, 1332 5, 1333 6, 1334 7, 1335 8, 1336 9, 1337 10, 1338 11, 1339 12, 1340 13, 1341 14, 1342 15, 1343 0, 1344 2, 1345 4, 1346 6, 1347 8, 1348 10, 1349 12, 1350 14, 1351}; 1352static inline void InitSystemZMCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) { 1353 RI->InitMCRegisterInfo(SystemZRegDesc, 162, RA, PC, SystemZMCRegisterClasses, 16, SystemZRegUnitRoots, 65, SystemZRegDiffLists, SystemZLaneMaskLists, SystemZRegStrings, SystemZRegClassStrings, SystemZSubRegIdxLists, 10, 1354SystemZSubRegIdxRanges, SystemZRegEncodingTable); 1355 1356 switch (DwarfFlavour) { 1357 default: 1358 llvm_unreachable("Unknown DWARF flavour"); 1359 case 0: 1360 RI->mapDwarfRegsToLLVMRegs(SystemZDwarfFlavour0Dwarf2L, SystemZDwarfFlavour0Dwarf2LSize, false); 1361 break; 1362 } 1363 switch (EHFlavour) { 1364 default: 1365 llvm_unreachable("Unknown DWARF flavour"); 1366 case 0: 1367 RI->mapDwarfRegsToLLVMRegs(SystemZEHFlavour0Dwarf2L, SystemZEHFlavour0Dwarf2LSize, true); 1368 break; 1369 } 1370 switch (DwarfFlavour) { 1371 default: 1372 llvm_unreachable("Unknown DWARF flavour"); 1373 case 0: 1374 RI->mapLLVMRegsToDwarfRegs(SystemZDwarfFlavour0L2Dwarf, SystemZDwarfFlavour0L2DwarfSize, false); 1375 break; 1376 } 1377 switch (EHFlavour) { 1378 default: 1379 llvm_unreachable("Unknown DWARF flavour"); 1380 case 0: 1381 RI->mapLLVMRegsToDwarfRegs(SystemZEHFlavour0L2Dwarf, SystemZEHFlavour0L2DwarfSize, true); 1382 break; 1383 } 1384} 1385 1386} // End llvm namespace 1387#endif // GET_REGINFO_MC_DESC 1388