1/**************************************************************************** 2** 3** Copyright (C) 2019 Denis Shienkov <denis.shienkov@gmail.com> 4** Contact: https://www.qt.io/licensing/ 5** 6** This file is part of the examples of Qbs. 7** 8** $QT_BEGIN_LICENSE:BSD$ 9** Commercial License Usage 10** Licensees holding valid commercial Qt licenses may use this file in 11** accordance with the commercial license agreement provided with the 12** Software or, alternatively, in accordance with the terms contained in 13** a written agreement between you and The Qt Company. For licensing terms 14** and conditions see https://www.qt.io/terms-conditions. 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IN NO EVENT SHALL THE COPYRIGHT 39** OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 40** SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 41** LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 42** DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 43** THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 44** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 45** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE." 46** 47** $QT_END_LICENSE$ 48** 49****************************************************************************/ 50 51 MODULE ?cstartup 52 53 SECTION CSTACK:DATA:NOROOT(3) 54 SECTION .intvec:CODE:NOROOT(2) 55 56 EXTERN __iar_program_start 57 58 PUBLIC _vectors_table 59 DATA 60_vectors_table 61 ;; Generic interrupts offset. 62 DCD sfe(CSTACK) ; Initial stack pointer value. 63 DCD reset_handler ; Reset. 64 DCD 0 ; NMI. 65 DCD 0 ; Hard fault. 66 DCD 0 ; Memory management fault. 67 DCD 0 ; Bus fault. 68 DCD 0 ; Usage fault. 69 DCD 0 ; Reserved. 70 DCD 0 ; Reserved. 71 DCD 0 ; Reserved. 72 DCD 0 ; Reserved. 73 DCD 0 ; SVC. 74 DCD 0 ; Debug monitor. 75 DCD 0 ; Reserved. 76 DCD 0 ; PendSV. 77 DCD 0 ; SysTick. 78 ;; External interrupts offset. 79 DCD 0 ; Window WatchDog. 80 DCD 0 ; PVD through EXTI Line detection. 81 DCD 0 ; Tamper and TimeStamps through the EXTI line. 82 DCD 0 ; RTC Wakeup through the EXTI line. 83 DCD 0 ; FLASH. 84 DCD 0 ; RCC. 85 DCD 0 ; EXTI Line0. 86 DCD 0 ; EXTI Line1. 87 DCD 0 ; EXTI Line2. 88 DCD 0 ; EXTI Line3. 89 DCD 0 ; EXTI Line4. 90 DCD 0 ; DMA1 Stream 0. 91 DCD 0 ; DMA1 Stream 1. 92 DCD 0 ; DMA1 Stream 2. 93 DCD 0 ; DMA1 Stream 3. 94 DCD 0 ; DMA1 Stream 4. 95 DCD 0 ; DMA1 Stream 5. 96 DCD 0 ; DMA1 Stream 6. 97 DCD 0 ; ADC1, ADC2 and ADC3s. 98 DCD 0 ; CAN1 TX. 99 DCD 0 ; CAN1 RX0. 100 DCD 0 ; CAN1 RX1. 101 DCD 0 ; CAN1 SCE. 102 DCD 0 ; External Line[9:5]s. 103 DCD 0 ; TIM1 Break and TIM9. 104 DCD 0 ; TIM1 Update and TIM10. 105 DCD 0 ; TIM1 Trigger and Commutation and TIM11. 106 DCD 0 ; TIM1 Capture Compare. 107 DCD 0 ; TIM2. 108 DCD 0 ; TIM3. 109 DCD 0 ; TIM4. 110 DCD 0 ; I2C1 Event. 111 DCD 0 ; I2C1 Error. 112 DCD 0 ; I2C2 Event. 113 DCD 0 ; I2C2 Error. 114 DCD 0 ; SPI1. 115 DCD 0 ; SPI2. 116 DCD 0 ; USART1. 117 DCD 0 ; USART2. 118 DCD 0 ; USART3. 119 DCD 0 ; External Line[15:10]s. 120 DCD 0 ; RTC Alarm (A and B) through EXTI Line. 121 DCD 0 ; USB OTG FS Wakeup through EXTI line. 122 DCD 0 ; TIM8 Break and TIM12. 123 DCD 0 ; TIM8 Update and TIM13. 124 DCD 0 ; TIM8 Trigger and Commutation and TIM14. 125 DCD 0 ; TIM8 Capture Compare. 126 DCD 0 ; DMA1 Stream7. 127 DCD 0 ; FSMC. 128 DCD 0 ; SDIO. 129 DCD 0 ; TIM5. 130 DCD 0 ; SPI3. 131 DCD 0 ; UART4. 132 DCD 0 ; UART5. 133 DCD 0 ; TIM6 and DAC1&2 underrun errors. 134 DCD 0 ; TIM7. 135 DCD 0 ; DMA2 Stream 0. 136 DCD 0 ; DMA2 Stream 1. 137 DCD 0 ; DMA2 Stream 2. 138 DCD 0 ; DMA2 Stream 3. 139 DCD 0 ; DMA2 Stream 4. 140 DCD 0 ; Ethernet. 141 DCD 0 ; Ethernet Wakeup through EXTI line. 142 DCD 0 ; CAN2 TX. 143 DCD 0 ; CAN2 RX0. 144 DCD 0 ; CAN2 RX1. 145 DCD 0 ; CAN2 SCE. 146 DCD 0 ; USB OTG FS. 147 DCD 0 ; DMA2 Stream 5. 148 DCD 0 ; DMA2 Stream 6. 149 DCD 0 ; DMA2 Stream 7. 150 DCD 0 ; USART6. 151 DCD 0 ; I2C3 event. 152 DCD 0 ; I2C3 error. 153 DCD 0 ; USB OTG HS End Point 1 Out. 154 DCD 0 ; USB OTG HS End Point 1 In. 155 DCD 0 ; USB OTG HS Wakeup through EXTI. 156 DCD 0 ; USB OTG HS. 157 DCD 0 ; DCMI. 158 DCD 0 ; CRYP crypto. 159 DCD 0 ; Hash and RNG. 160 DCD 0 ; FPU. 161 162 ;; Reset handler. 163 THUMB 164 PUBWEAK reset_handler 165 SECTION .text:CODE:REORDER:NOROOT(2) 166reset_handler 167 BLX R0 168 LDR R0, =__iar_program_start 169 BX R0 170 171 END 172