1 /* ppc.h -- Header file for PowerPC opcode table 2 Copyright 1994, 1995, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 3 2007 Free Software Foundation, Inc. 4 Written by Ian Lance Taylor, Cygnus Support 5 6 This file is part of GDB, GAS, and the GNU binutils. 7 8 GDB, GAS, and the GNU binutils are free software; you can redistribute 9 them and/or modify them under the terms of the GNU General Public 10 License as published by the Free Software Foundation; either version 11 1, or (at your option) any later version. 12 13 GDB, GAS, and the GNU binutils are distributed in the hope that they 14 will be useful, but WITHOUT ANY WARRANTY; without even the implied 15 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See 16 the GNU General Public License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with this file; see the file COPYING. If not, write to the Free 20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ 21 22 #ifndef PPC_H 23 #define PPC_H 24 25 typedef unsigned long ppc_cpu_t; 26 27 /* The opcode table is an array of struct powerpc_opcode. */ 28 29 struct powerpc_opcode 30 { 31 /* The opcode name. */ 32 const char *name; 33 34 /* The opcode itself. Those bits which will be filled in with 35 operands are zeroes. */ 36 unsigned long opcode; 37 38 /* The opcode mask. This is used by the disassembler. This is a 39 mask containing ones indicating those bits which must match the 40 opcode field, and zeroes indicating those bits which need not 41 match (and are presumably filled in by operands). */ 42 unsigned long mask; 43 44 /* One bit flags for the opcode. These are used to indicate which 45 specific processors support the instructions. The defined values 46 are listed below. */ 47 ppc_cpu_t flags; 48 49 /* An array of operand codes. Each code is an index into the 50 operand table. They appear in the order which the operands must 51 appear in assembly code, and are terminated by a zero. */ 52 unsigned char operands[8]; 53 }; 54 55 /* The table itself is sorted by major opcode number, and is otherwise 56 in the order in which the disassembler should consider 57 instructions. */ 58 extern const struct powerpc_opcode powerpc_opcodes[]; 59 extern const int powerpc_num_opcodes; 60 61 /* Values defined for the flags field of a struct powerpc_opcode. */ 62 63 /* Opcode is defined for the PowerPC architecture. */ 64 #define PPC_OPCODE_PPC 1 65 66 /* Opcode is defined for the POWER (RS/6000) architecture. */ 67 #define PPC_OPCODE_POWER 2 68 69 /* Opcode is defined for the POWER2 (Rios 2) architecture. */ 70 #define PPC_OPCODE_POWER2 4 71 72 /* Opcode is only defined on 32 bit architectures. */ 73 #define PPC_OPCODE_32 8 74 75 /* Opcode is only defined on 64 bit architectures. */ 76 #define PPC_OPCODE_64 0x10 77 78 /* Opcode is supported by the Motorola PowerPC 601 processor. The 601 79 is assumed to support all PowerPC (PPC_OPCODE_PPC) instructions, 80 but it also supports many additional POWER instructions. */ 81 #define PPC_OPCODE_601 0x20 82 83 /* Opcode is supported in both the Power and PowerPC architectures 84 (ie, compiler's -mcpu=common or assembler's -mcom). */ 85 #define PPC_OPCODE_COMMON 0x40 86 87 /* Opcode is supported for any Power or PowerPC platform (this is 88 for the assembler's -many option, and it eliminates duplicates). */ 89 #define PPC_OPCODE_ANY 0x80 90 91 /* Opcode is supported as part of the 64-bit bridge. */ 92 #define PPC_OPCODE_64_BRIDGE 0x100 93 94 /* Opcode is supported by Altivec Vector Unit */ 95 #define PPC_OPCODE_ALTIVEC 0x200 96 97 /* Opcode is supported by PowerPC 403 processor. */ 98 #define PPC_OPCODE_403 0x400 99 100 /* Opcode is supported by PowerPC BookE processor. */ 101 #define PPC_OPCODE_BOOKE 0x800 102 103 /* Opcode is only supported by 64-bit PowerPC BookE processor. */ 104 #define PPC_OPCODE_BOOKE64 0x1000 105 106 /* Opcode is supported by PowerPC 440 processor. */ 107 #define PPC_OPCODE_440 0x2000 108 109 /* Opcode is only supported by Power4 architecture. */ 110 #define PPC_OPCODE_POWER4 0x4000 111 112 /* Opcode isn't supported by Power4 architecture. */ 113 #define PPC_OPCODE_NOPOWER4 0x8000 114 115 /* Opcode is only supported by POWERPC Classic architecture. */ 116 #define PPC_OPCODE_CLASSIC 0x10000 117 118 /* Opcode is only supported by e500x2 Core. */ 119 #define PPC_OPCODE_SPE 0x20000 120 121 /* Opcode is supported by e500x2 Integer select APU. */ 122 #define PPC_OPCODE_ISEL 0x40000 123 124 /* Opcode is an e500 SPE floating point instruction. */ 125 #define PPC_OPCODE_EFS 0x80000 126 127 /* Opcode is supported by branch locking APU. */ 128 #define PPC_OPCODE_BRLOCK 0x100000 129 130 /* Opcode is supported by performance monitor APU. */ 131 #define PPC_OPCODE_PMR 0x200000 132 133 /* Opcode is supported by cache locking APU. */ 134 #define PPC_OPCODE_CACHELCK 0x400000 135 136 /* Opcode is supported by machine check APU. */ 137 #define PPC_OPCODE_RFMCI 0x800000 138 139 /* Opcode is only supported by Power5 architecture. */ 140 #define PPC_OPCODE_POWER5 0x1000000 141 142 /* Opcode is supported by PowerPC e300 family. */ 143 #define PPC_OPCODE_E300 0x2000000 144 145 /* Opcode is only supported by Power6 architecture. */ 146 #define PPC_OPCODE_POWER6 0x4000000 147 148 /* Opcode is only supported by PowerPC Cell family. */ 149 #define PPC_OPCODE_CELL 0x8000000 150 151 /* Opcode is supported by CPUs with paired singles support. */ 152 #define PPC_OPCODE_PPCPS 0x10000000 153 154 /* Opcode is supported by Power E500MC */ 155 #define PPC_OPCODE_E500MC 0x20000000 156 157 /* Opcode is supported by PowerPC 405 processor. */ 158 #define PPC_OPCODE_405 0x40000000 159 160 /* Opcode is supported by Vector-Scalar (VSX) Unit */ 161 #define PPC_OPCODE_VSX 0x80000000 162 163 /* A macro to extract the major opcode from an instruction. */ 164 #define PPC_OP(i) (((i) >> 26) & 0x3f) 165 166 /* The operands table is an array of struct powerpc_operand. */ 167 168 struct powerpc_operand 169 { 170 /* A bitmask of bits in the operand. */ 171 unsigned int bitm; 172 173 /* How far the operand is left shifted in the instruction. 174 -1 to indicate that BITM and SHIFT cannot be used to determine 175 where the operand goes in the insn. */ 176 int shift; 177 178 /* Insertion function. This is used by the assembler. To insert an 179 operand value into an instruction, check this field. 180 181 If it is NULL, execute 182 i |= (op & o->bitm) << o->shift; 183 (i is the instruction which we are filling in, o is a pointer to 184 this structure, and op is the operand value). 185 186 If this field is not NULL, then simply call it with the 187 instruction and the operand value. It will return the new value 188 of the instruction. If the ERRMSG argument is not NULL, then if 189 the operand value is illegal, *ERRMSG will be set to a warning 190 string (the operand will be inserted in any case). If the 191 operand value is legal, *ERRMSG will be unchanged (most operands 192 can accept any value). */ 193 unsigned long (*insert) 194 (unsigned long instruction, long op, ppc_cpu_t dialect, const char **errmsg); 195 196 /* Extraction function. This is used by the disassembler. To 197 extract this operand type from an instruction, check this field. 198 199 If it is NULL, compute 200 op = (i >> o->shift) & o->bitm; 201 if ((o->flags & PPC_OPERAND_SIGNED) != 0) 202 sign_extend (op); 203 (i is the instruction, o is a pointer to this structure, and op 204 is the result). 205 206 If this field is not NULL, then simply call it with the 207 instruction value. It will return the value of the operand. If 208 the INVALID argument is not NULL, *INVALID will be set to 209 non-zero if this operand type can not actually be extracted from 210 this operand (i.e., the instruction does not match). If the 211 operand is valid, *INVALID will not be changed. */ 212 long (*extract) (unsigned long instruction, ppc_cpu_t dialect, int *invalid); 213 214 /* One bit syntax flags. */ 215 unsigned long flags; 216 }; 217 218 /* Elements in the table are retrieved by indexing with values from 219 the operands field of the powerpc_opcodes table. */ 220 221 extern const struct powerpc_operand powerpc_operands[]; 222 extern const unsigned int num_powerpc_operands; 223 224 /* Values defined for the flags field of a struct powerpc_operand. */ 225 226 /* This operand takes signed values. */ 227 #define PPC_OPERAND_SIGNED (0x1) 228 229 /* This operand takes signed values, but also accepts a full positive 230 range of values when running in 32 bit mode. That is, if bits is 231 16, it takes any value from -0x8000 to 0xffff. In 64 bit mode, 232 this flag is ignored. */ 233 #define PPC_OPERAND_SIGNOPT (0x2) 234 235 /* This operand does not actually exist in the assembler input. This 236 is used to support extended mnemonics such as mr, for which two 237 operands fields are identical. The assembler should call the 238 insert function with any op value. The disassembler should call 239 the extract function, ignore the return value, and check the value 240 placed in the valid argument. */ 241 #define PPC_OPERAND_FAKE (0x4) 242 243 /* The next operand should be wrapped in parentheses rather than 244 separated from this one by a comma. This is used for the load and 245 store instructions which want their operands to look like 246 reg,displacement(reg) 247 */ 248 #define PPC_OPERAND_PARENS (0x8) 249 250 /* This operand may use the symbolic names for the CR fields, which 251 are 252 lt 0 gt 1 eq 2 so 3 un 3 253 cr0 0 cr1 1 cr2 2 cr3 3 254 cr4 4 cr5 5 cr6 6 cr7 7 255 These may be combined arithmetically, as in cr2*4+gt. These are 256 only supported on the PowerPC, not the POWER. */ 257 #define PPC_OPERAND_CR (0x10) 258 259 /* This operand names a register. The disassembler uses this to print 260 register names with a leading 'r'. */ 261 #define PPC_OPERAND_GPR (0x20) 262 263 /* Like PPC_OPERAND_GPR, but don't print a leading 'r' for r0. */ 264 #define PPC_OPERAND_GPR_0 (0x40) 265 266 /* This operand names a floating point register. The disassembler 267 prints these with a leading 'f'. */ 268 #define PPC_OPERAND_FPR (0x80) 269 270 /* This operand is a relative branch displacement. The disassembler 271 prints these symbolically if possible. */ 272 #define PPC_OPERAND_RELATIVE (0x100) 273 274 /* This operand is an absolute branch address. The disassembler 275 prints these symbolically if possible. */ 276 #define PPC_OPERAND_ABSOLUTE (0x200) 277 278 /* This operand is optional, and is zero if omitted. This is used for 279 example, in the optional BF field in the comparison instructions. The 280 assembler must count the number of operands remaining on the line, 281 and the number of operands remaining for the opcode, and decide 282 whether this operand is present or not. The disassembler should 283 print this operand out only if it is not zero. */ 284 #define PPC_OPERAND_OPTIONAL (0x400) 285 286 /* This flag is only used with PPC_OPERAND_OPTIONAL. If this operand 287 is omitted, then for the next operand use this operand value plus 288 1, ignoring the next operand field for the opcode. This wretched 289 hack is needed because the Power rotate instructions can take 290 either 4 or 5 operands. The disassembler should print this operand 291 out regardless of the PPC_OPERAND_OPTIONAL field. */ 292 #define PPC_OPERAND_NEXT (0x800) 293 294 /* This operand should be regarded as a negative number for the 295 purposes of overflow checking (i.e., the normal most negative 296 number is disallowed and one more than the normal most positive 297 number is allowed). This flag will only be set for a signed 298 operand. */ 299 #define PPC_OPERAND_NEGATIVE (0x1000) 300 301 /* This operand names a vector unit register. The disassembler 302 prints these with a leading 'v'. */ 303 #define PPC_OPERAND_VR (0x2000) 304 305 /* This operand is for the DS field in a DS form instruction. */ 306 #define PPC_OPERAND_DS (0x4000) 307 308 /* This operand is for the DQ field in a DQ form instruction. */ 309 #define PPC_OPERAND_DQ (0x8000) 310 311 /* Valid range of operand is 0..n rather than 0..n-1. */ 312 #define PPC_OPERAND_PLUS1 (0x10000) 313 314 /* Xilinx APU and FSL related operands */ 315 #define PPC_OPERAND_FSL (0x20000) 316 #define PPC_OPERAND_FCR (0x40000) 317 #define PPC_OPERAND_UDI (0x80000) 318 319 /* This operand names a vector-scalar unit register. The disassembler 320 prints these with a leading 'vs'. */ 321 #define PPC_OPERAND_VSR (0x100000) 322 323 /* The POWER and PowerPC assemblers use a few macros. We keep them 324 with the operands table for simplicity. The macro table is an 325 array of struct powerpc_macro. */ 326 327 struct powerpc_macro 328 { 329 /* The macro name. */ 330 const char *name; 331 332 /* The number of operands the macro takes. */ 333 unsigned int operands; 334 335 /* One bit flags for the opcode. These are used to indicate which 336 specific processors support the instructions. The values are the 337 same as those for the struct powerpc_opcode flags field. */ 338 ppc_cpu_t flags; 339 340 /* A format string to turn the macro into a normal instruction. 341 Each %N in the string is replaced with operand number N (zero 342 based). */ 343 const char *format; 344 }; 345 346 extern const struct powerpc_macro powerpc_macros[]; 347 extern const int powerpc_num_macros; 348 349 #endif /* PPC_H */ 350