1 /* Print mips instructions for GDB, the GNU debugger, or for objdump.
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2005, 2007
4 Free Software Foundation, Inc.
5 Contributed by Nobuyuki Hikichi(hikichi@sra.co.jp).
6
7 This file is part of the GNU opcodes library.
8
9 This library is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
12 any later version.
13
14 It is distributed in the hope that it will be useful, but WITHOUT
15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17 License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
22 MA 02110-1301, USA. */
23
24 #include <stdio.h>
25 #include <string.h>
26 #include <stdlib.h>
27 #include "ansidecl.h"
28 #include "sysdep.h"
29 #include "disas-asm.h"
30 #include "libiberty.h"
31 #include "elf/mips.h"
32 #include "opintl.h"
33
34 /* FIXME: These are needed to figure out if the code is mips16 or
35 not. The low bit of the address is often a good indicator. No
36 symbol table is available when this code runs out in an embedded
37 system as when it is used for disassembler support in a monitor. */
38
39 #include "opcode/mips.h"
40 #if !defined(EMBEDDED_ENV)
41 #define SYMTAB_AVAILABLE 1
42 #include "elf-bfd.h"
43 #endif
44
45 /* Mips instructions are at maximum this many bytes long. */
46 #define INSNLEN 4
47
48
49 /* FIXME: These should be shared with gdb somehow. */
50
51 struct mips_cp0sel_name
52 {
53 unsigned int cp0reg;
54 unsigned int sel;
55 const char * const name;
56 };
57
58 /* The mips16 registers. */
59 static const unsigned int mips16_to_32_reg_map[] =
60 {
61 16, 17, 2, 3, 4, 5, 6, 7
62 };
63
64 #define mips16_reg_names(rn) mips_gpr_names[mips16_to_32_reg_map[rn]]
65
66
67 static const char * const mips_gpr_names_numeric[32] =
68 {
69 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
70 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
71 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
72 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
73 };
74
75 const char * const mips_gpr_names_oldabi[32] =
76 {
77 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
78 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
79 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
80 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
81 };
82
83 const char * const mips_gpr_names_newabi[32] =
84 {
85 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
86 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
87 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
88 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
89 };
90
91 static const char * const mips_fpr_names_numeric[32] =
92 {
93 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
94 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
95 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
96 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31"
97 };
98
99 static const char * const mips_fpr_names_32[32] =
100 {
101 "fv0", "fv0f", "fv1", "fv1f", "ft0", "ft0f", "ft1", "ft1f",
102 "ft2", "ft2f", "ft3", "ft3f", "fa0", "fa0f", "fa1", "fa1f",
103 "ft4", "ft4f", "ft5", "ft5f", "fs0", "fs0f", "fs1", "fs1f",
104 "fs2", "fs2f", "fs3", "fs3f", "fs4", "fs4f", "fs5", "fs5f"
105 };
106
107 static const char * const mips_fpr_names_n32[32] =
108 {
109 "fv0", "ft14", "fv1", "ft15", "ft0", "ft1", "ft2", "ft3",
110 "ft4", "ft5", "ft6", "ft7", "fa0", "fa1", "fa2", "fa3",
111 "fa4", "fa5", "fa6", "fa7", "fs0", "ft8", "fs1", "ft9",
112 "fs2", "ft10", "fs3", "ft11", "fs4", "ft12", "fs5", "ft13"
113 };
114
115 static const char * const mips_fpr_names_64[32] =
116 {
117 "fv0", "ft12", "fv1", "ft13", "ft0", "ft1", "ft2", "ft3",
118 "ft4", "ft5", "ft6", "ft7", "fa0", "fa1", "fa2", "fa3",
119 "fa4", "fa5", "fa6", "fa7", "ft8", "ft9", "ft10", "ft11",
120 "fs0", "fs1", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7"
121 };
122
123 static const char * const mips_cp0_names_numeric[32] =
124 {
125 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
126 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
127 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
128 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
129 };
130
131 static const char * const mips_cp0_names_mips3264[32] =
132 {
133 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
134 "c0_context", "c0_pagemask", "c0_wired", "$7",
135 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
136 "c0_status", "c0_cause", "c0_epc", "c0_prid",
137 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi",
138 "c0_xcontext", "$21", "$22", "c0_debug",
139 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr",
140 "c0_taglo", "c0_taghi", "c0_errorepc", "c0_desave",
141 };
142
143 static const struct mips_cp0sel_name mips_cp0sel_names_mips3264[] =
144 {
145 { 16, 1, "c0_config1" },
146 { 16, 2, "c0_config2" },
147 { 16, 3, "c0_config3" },
148 { 18, 1, "c0_watchlo,1" },
149 { 18, 2, "c0_watchlo,2" },
150 { 18, 3, "c0_watchlo,3" },
151 { 18, 4, "c0_watchlo,4" },
152 { 18, 5, "c0_watchlo,5" },
153 { 18, 6, "c0_watchlo,6" },
154 { 18, 7, "c0_watchlo,7" },
155 { 19, 1, "c0_watchhi,1" },
156 { 19, 2, "c0_watchhi,2" },
157 { 19, 3, "c0_watchhi,3" },
158 { 19, 4, "c0_watchhi,4" },
159 { 19, 5, "c0_watchhi,5" },
160 { 19, 6, "c0_watchhi,6" },
161 { 19, 7, "c0_watchhi,7" },
162 { 25, 1, "c0_perfcnt,1" },
163 { 25, 2, "c0_perfcnt,2" },
164 { 25, 3, "c0_perfcnt,3" },
165 { 25, 4, "c0_perfcnt,4" },
166 { 25, 5, "c0_perfcnt,5" },
167 { 25, 6, "c0_perfcnt,6" },
168 { 25, 7, "c0_perfcnt,7" },
169 { 27, 1, "c0_cacheerr,1" },
170 { 27, 2, "c0_cacheerr,2" },
171 { 27, 3, "c0_cacheerr,3" },
172 { 28, 1, "c0_datalo" },
173 { 29, 1, "c0_datahi" }
174 };
175
176 static const char * const mips_cp0_names_mips3264r2[32] =
177 {
178 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
179 "c0_context", "c0_pagemask", "c0_wired", "c0_hwrena",
180 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
181 "c0_status", "c0_cause", "c0_epc", "c0_prid",
182 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi",
183 "c0_xcontext", "$21", "$22", "c0_debug",
184 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr",
185 "c0_taglo", "c0_taghi", "c0_errorepc", "c0_desave",
186 };
187
188 static const struct mips_cp0sel_name mips_cp0sel_names_mips3264r2[] =
189 {
190 { 4, 1, "c0_contextconfig" },
191 { 0, 1, "c0_mvpcontrol" },
192 { 0, 2, "c0_mvpconf0" },
193 { 0, 3, "c0_mvpconf1" },
194 { 1, 1, "c0_vpecontrol" },
195 { 1, 2, "c0_vpeconf0" },
196 { 1, 3, "c0_vpeconf1" },
197 { 1, 4, "c0_yqmask" },
198 { 1, 5, "c0_vpeschedule" },
199 { 1, 6, "c0_vpeschefback" },
200 { 2, 1, "c0_tcstatus" },
201 { 2, 2, "c0_tcbind" },
202 { 2, 3, "c0_tcrestart" },
203 { 2, 4, "c0_tchalt" },
204 { 2, 5, "c0_tccontext" },
205 { 2, 6, "c0_tcschedule" },
206 { 2, 7, "c0_tcschefback" },
207 { 5, 1, "c0_pagegrain" },
208 { 6, 1, "c0_srsconf0" },
209 { 6, 2, "c0_srsconf1" },
210 { 6, 3, "c0_srsconf2" },
211 { 6, 4, "c0_srsconf3" },
212 { 6, 5, "c0_srsconf4" },
213 { 12, 1, "c0_intctl" },
214 { 12, 2, "c0_srsctl" },
215 { 12, 3, "c0_srsmap" },
216 { 15, 1, "c0_ebase" },
217 { 16, 1, "c0_config1" },
218 { 16, 2, "c0_config2" },
219 { 16, 3, "c0_config3" },
220 { 18, 1, "c0_watchlo,1" },
221 { 18, 2, "c0_watchlo,2" },
222 { 18, 3, "c0_watchlo,3" },
223 { 18, 4, "c0_watchlo,4" },
224 { 18, 5, "c0_watchlo,5" },
225 { 18, 6, "c0_watchlo,6" },
226 { 18, 7, "c0_watchlo,7" },
227 { 19, 1, "c0_watchhi,1" },
228 { 19, 2, "c0_watchhi,2" },
229 { 19, 3, "c0_watchhi,3" },
230 { 19, 4, "c0_watchhi,4" },
231 { 19, 5, "c0_watchhi,5" },
232 { 19, 6, "c0_watchhi,6" },
233 { 19, 7, "c0_watchhi,7" },
234 { 23, 1, "c0_tracecontrol" },
235 { 23, 2, "c0_tracecontrol2" },
236 { 23, 3, "c0_usertracedata" },
237 { 23, 4, "c0_tracebpc" },
238 { 25, 1, "c0_perfcnt,1" },
239 { 25, 2, "c0_perfcnt,2" },
240 { 25, 3, "c0_perfcnt,3" },
241 { 25, 4, "c0_perfcnt,4" },
242 { 25, 5, "c0_perfcnt,5" },
243 { 25, 6, "c0_perfcnt,6" },
244 { 25, 7, "c0_perfcnt,7" },
245 { 27, 1, "c0_cacheerr,1" },
246 { 27, 2, "c0_cacheerr,2" },
247 { 27, 3, "c0_cacheerr,3" },
248 { 28, 1, "c0_datalo" },
249 { 28, 2, "c0_taglo1" },
250 { 28, 3, "c0_datalo1" },
251 { 28, 4, "c0_taglo2" },
252 { 28, 5, "c0_datalo2" },
253 { 28, 6, "c0_taglo3" },
254 { 28, 7, "c0_datalo3" },
255 { 29, 1, "c0_datahi" },
256 { 29, 2, "c0_taghi1" },
257 { 29, 3, "c0_datahi1" },
258 { 29, 4, "c0_taghi2" },
259 { 29, 5, "c0_datahi2" },
260 { 29, 6, "c0_taghi3" },
261 { 29, 7, "c0_datahi3" },
262 };
263
264 /* SB-1: MIPS64 (mips_cp0_names_mips3264) with minor mods. */
265 static const char * const mips_cp0_names_sb1[32] =
266 {
267 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
268 "c0_context", "c0_pagemask", "c0_wired", "$7",
269 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
270 "c0_status", "c0_cause", "c0_epc", "c0_prid",
271 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi",
272 "c0_xcontext", "$21", "$22", "c0_debug",
273 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr_i",
274 "c0_taglo_i", "c0_taghi_i", "c0_errorepc", "c0_desave",
275 };
276
277 static const struct mips_cp0sel_name mips_cp0sel_names_sb1[] =
278 {
279 { 16, 1, "c0_config1" },
280 { 18, 1, "c0_watchlo,1" },
281 { 19, 1, "c0_watchhi,1" },
282 { 22, 0, "c0_perftrace" },
283 { 23, 3, "c0_edebug" },
284 { 25, 1, "c0_perfcnt,1" },
285 { 25, 2, "c0_perfcnt,2" },
286 { 25, 3, "c0_perfcnt,3" },
287 { 25, 4, "c0_perfcnt,4" },
288 { 25, 5, "c0_perfcnt,5" },
289 { 25, 6, "c0_perfcnt,6" },
290 { 25, 7, "c0_perfcnt,7" },
291 { 26, 1, "c0_buserr_pa" },
292 { 27, 1, "c0_cacheerr_d" },
293 { 27, 3, "c0_cacheerr_d_pa" },
294 { 28, 1, "c0_datalo_i" },
295 { 28, 2, "c0_taglo_d" },
296 { 28, 3, "c0_datalo_d" },
297 { 29, 1, "c0_datahi_i" },
298 { 29, 2, "c0_taghi_d" },
299 { 29, 3, "c0_datahi_d" },
300 };
301
302 static const char * const mips_hwr_names_numeric[32] =
303 {
304 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
305 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
306 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
307 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
308 };
309
310 static const char * const mips_hwr_names_mips3264r2[32] =
311 {
312 "hwr_cpunum", "hwr_synci_step", "hwr_cc", "hwr_ccres",
313 "$4", "$5", "$6", "$7",
314 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
315 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
316 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
317 };
318
319 struct mips_abi_choice
320 {
321 const char * name;
322 const char * const *gpr_names;
323 const char * const *fpr_names;
324 };
325
326 struct mips_abi_choice mips_abi_choices[] =
327 {
328 { "numeric", mips_gpr_names_numeric, mips_fpr_names_numeric },
329 { "o32", mips_gpr_names_oldabi, mips_fpr_names_32 },
330 { "n32", mips_gpr_names_newabi, mips_fpr_names_n32 },
331 { "n64", mips_gpr_names_newabi, mips_fpr_names_64 },
332 };
333
334 struct mips_arch_choice
335 {
336 const char *name;
337 int bfd_mach_valid;
338 unsigned long bfd_mach;
339 int processor;
340 int isa;
341 const char * const *cp0_names;
342 const struct mips_cp0sel_name *cp0sel_names;
343 unsigned int cp0sel_names_len;
344 const char * const *hwr_names;
345 };
346
347 const struct mips_arch_choice mips_arch_choices[] =
348 {
349 { "numeric", 0, 0, 0, 0,
350 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
351
352 { "r3000", 1, bfd_mach_mips3000, CPU_R3000, ISA_MIPS1,
353 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
354 { "r3900", 1, bfd_mach_mips3900, CPU_R3900, ISA_MIPS1,
355 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
356 { "r4000", 1, bfd_mach_mips4000, CPU_R4000, ISA_MIPS3,
357 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
358 { "r4010", 1, bfd_mach_mips4010, CPU_R4010, ISA_MIPS2,
359 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
360 { "vr4100", 1, bfd_mach_mips4100, CPU_VR4100, ISA_MIPS3,
361 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
362 { "vr4111", 1, bfd_mach_mips4111, CPU_R4111, ISA_MIPS3,
363 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
364 { "vr4120", 1, bfd_mach_mips4120, CPU_VR4120, ISA_MIPS3,
365 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
366 { "r4300", 1, bfd_mach_mips4300, CPU_R4300, ISA_MIPS3,
367 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
368 { "r4400", 1, bfd_mach_mips4400, CPU_R4400, ISA_MIPS3,
369 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
370 { "r4600", 1, bfd_mach_mips4600, CPU_R4600, ISA_MIPS3,
371 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
372 { "r4650", 1, bfd_mach_mips4650, CPU_R4650, ISA_MIPS3,
373 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
374 { "r5000", 1, bfd_mach_mips5000, CPU_R5000, ISA_MIPS4,
375 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
376 { "vr5400", 1, bfd_mach_mips5400, CPU_VR5400, ISA_MIPS4,
377 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
378 { "vr5500", 1, bfd_mach_mips5500, CPU_VR5500, ISA_MIPS4,
379 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
380 { "r6000", 1, bfd_mach_mips6000, CPU_R6000, ISA_MIPS2,
381 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
382 { "rm7000", 1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4,
383 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
384 { "rm9000", 1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4,
385 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
386 { "r8000", 1, bfd_mach_mips8000, CPU_R8000, ISA_MIPS4,
387 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
388 { "r10000", 1, bfd_mach_mips10000, CPU_R10000, ISA_MIPS4,
389 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
390 { "r12000", 1, bfd_mach_mips12000, CPU_R12000, ISA_MIPS4,
391 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
392 { "mips5", 1, bfd_mach_mips5, CPU_MIPS5, ISA_MIPS5,
393 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
394
395 /* For stock MIPS32, disassemble all applicable MIPS-specified ASEs.
396 Note that MIPS-3D and MDMX are not applicable to MIPS32. (See
397 _MIPS32 Architecture For Programmers Volume I: Introduction to the
398 MIPS32 Architecture_ (MIPS Document Number MD00082, Revision 0.95),
399 page 1. */
400 { "mips32", 1, bfd_mach_mipsisa32, CPU_MIPS32,
401 ISA_MIPS32 | INSN_MIPS16 | INSN_SMARTMIPS,
402 mips_cp0_names_mips3264,
403 mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264),
404 mips_hwr_names_numeric },
405
406 { "mips32r2", 1, bfd_mach_mipsisa32r2, CPU_MIPS32R2,
407 (ISA_MIPS32R2 | INSN_MIPS16 | INSN_SMARTMIPS | INSN_DSP | INSN_DSPR2
408 | INSN_MIPS3D | INSN_MT),
409 mips_cp0_names_mips3264r2,
410 mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
411 mips_hwr_names_mips3264r2 },
412
413 /* For stock MIPS64, disassemble all applicable MIPS-specified ASEs. */
414 { "mips64", 1, bfd_mach_mipsisa64, CPU_MIPS64,
415 ISA_MIPS64 | INSN_MIPS16 | INSN_MIPS3D | INSN_MDMX,
416 mips_cp0_names_mips3264,
417 mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264),
418 mips_hwr_names_numeric },
419
420 { "mips64r2", 1, bfd_mach_mipsisa64r2, CPU_MIPS64R2,
421 (ISA_MIPS64R2 | INSN_MIPS16 | INSN_MIPS3D | INSN_DSP | INSN_DSPR2
422 | INSN_DSP64 | INSN_MT | INSN_MDMX),
423 mips_cp0_names_mips3264r2,
424 mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
425 mips_hwr_names_mips3264r2 },
426
427 { "sb1", 1, bfd_mach_mips_sb1, CPU_SB1,
428 ISA_MIPS64 | INSN_MIPS3D | INSN_SB1,
429 mips_cp0_names_sb1,
430 mips_cp0sel_names_sb1, ARRAY_SIZE (mips_cp0sel_names_sb1),
431 mips_hwr_names_numeric },
432
433 { "loongson2e", 1, bfd_mach_mips_loongson_2e, CPU_LOONGSON_2E,
434 ISA_MIPS3 | INSN_LOONGSON_2E,
435 mips_cp0_names_numeric,
436 NULL, 0, mips_hwr_names_numeric },
437
438 { "loongson2f", 1, bfd_mach_mips_loongson_2f, CPU_LOONGSON_2F,
439 ISA_MIPS64 | INSN_LOONGSON_2F,
440 mips_cp0_names_numeric,
441 NULL, 0, mips_hwr_names_numeric },
442
443 /* This entry, mips16, is here only for ISA/processor selection; do
444 not print its name. */
445 { "", 1, bfd_mach_mips16, CPU_MIPS16, ISA_MIPS3 | INSN_MIPS16,
446 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
447 };
448
449 /* ISA and processor type to disassemble for, and register names to use.
450 set_default_mips_dis_options and parse_mips_dis_options fill in these
451 values. */
452 static int mips_processor;
453 static int mips_isa;
454 static const char * const *mips_gpr_names;
455 static const char * const *mips_fpr_names;
456 static const char * const *mips_cp0_names;
457 static const struct mips_cp0sel_name *mips_cp0sel_names;
458 static int mips_cp0sel_names_len;
459 static const char * const *mips_hwr_names;
460
461 /* Other options */
462 static int no_aliases; /* If set disassemble as most general inst. */
463
464 static const struct mips_abi_choice *
choose_abi_by_name(const char * name,unsigned int namelen)465 choose_abi_by_name (const char *name, unsigned int namelen)
466 {
467 const struct mips_abi_choice *c;
468 unsigned int i;
469
470 for (i = 0, c = NULL; i < ARRAY_SIZE (mips_abi_choices) && !c; i++) {
471 if (strncmp (mips_abi_choices[i].name, name, namelen) == 0 && strlen (mips_abi_choices[i].name) == namelen) {
472 c = &mips_abi_choices[i];
473 }
474 }
475
476 return c;
477 }
478
479 static const struct mips_arch_choice *
choose_arch_by_name(const char * name,unsigned int namelen)480 choose_arch_by_name (const char *name, unsigned int namelen)
481 {
482 const struct mips_arch_choice *c = NULL;
483 unsigned int i;
484
485 for (i = 0, c = NULL; i < ARRAY_SIZE (mips_arch_choices) && !c; i++) {
486 if (strncmp (mips_arch_choices[i].name, name, namelen) == 0 && strlen (mips_arch_choices[i].name) == namelen) {
487 c = &mips_arch_choices[i];
488 }
489 }
490
491 return c;
492 }
493
494 static const struct mips_arch_choice *
choose_arch_by_number(unsigned long mach)495 choose_arch_by_number (unsigned long mach)
496 {
497 static unsigned long hint_bfd_mach;
498 static const struct mips_arch_choice *hint_arch_choice;
499 const struct mips_arch_choice *c;
500 unsigned int i;
501
502 /* We optimize this because even if the user specifies no
503 flags, this will be done for every instruction! */
504 if (hint_bfd_mach == mach && hint_arch_choice != NULL && hint_arch_choice->bfd_mach == hint_bfd_mach) {
505 return hint_arch_choice;
506 }
507
508 for (i = 0, c = NULL; i < ARRAY_SIZE (mips_arch_choices) && !c; i++)
509 {
510 if (mips_arch_choices[i].bfd_mach_valid
511 && mips_arch_choices[i].bfd_mach == mach)
512 {
513 c = &mips_arch_choices[i];
514 hint_bfd_mach = mach;
515 hint_arch_choice = c;
516 }
517 }
518 return c;
519 }
520
521 /* Check if the object uses NewABI conventions. */
522
523 static int
is_newabi(Elf_Internal_Ehdr * header)524 is_newabi (Elf_Internal_Ehdr *header)
525 {
526 /* There are no old-style ABIs which use 64-bit ELF. */
527 if (header->e_ident[EI_CLASS] == ELFCLASS64) {
528 return 1;
529 }
530
531 /* If a 32-bit ELF file, n32 is a new-style ABI. */
532 if ((header->e_flags & EF_MIPS_ABI2) != 0) {
533 return 1;
534 }
535
536 return 0;
537 }
538
539 static void
set_default_mips_dis_options(struct disassemble_info * info)540 set_default_mips_dis_options (struct disassemble_info *info)
541 {
542 const struct mips_arch_choice *chosen_arch;
543
544 /* Defaults: mipsIII/r3000 (?!), (o)32-style ("oldabi") GPR names,
545 and numeric FPR, CP0 register, and HWR names. */
546 mips_isa = ISA_MIPS3;
547 mips_processor = CPU_LOONGSON_2F; // R3000
548 mips_gpr_names = mips_gpr_names_oldabi;
549 mips_fpr_names = mips_fpr_names_numeric;
550 mips_cp0_names = mips_cp0_names_numeric;
551 mips_cp0sel_names = NULL;
552 mips_cp0sel_names_len = 0;
553 mips_hwr_names = mips_hwr_names_numeric;
554 no_aliases = 0;
555
556 /* If an ELF "newabi" binary, use the n32/(n)64 GPR names. */
557 if (info->flavour == bfd_target_elf_flavour && info->section != NULL)
558 {
559 Elf_Internal_Ehdr *header;
560
561 header = elf_elfheader (info->section->owner);
562 if (is_newabi (header)) {
563 mips_gpr_names = mips_gpr_names_newabi;
564 }
565 }
566
567 /* Set ISA, architecture, and cp0 register names as best we can. */
568 #if ! SYMTAB_AVAILABLE
569 /* This is running out on a target machine, not in a host tool.
570 FIXME: Where does mips_target_info come from? */
571 target_processor = mips_target_info.processor;
572 mips_isa = mips_target_info.isa;
573 #else
574 chosen_arch = choose_arch_by_number (info->mach);
575 if (chosen_arch != NULL)
576 {
577 mips_processor = chosen_arch->processor;
578 mips_isa = chosen_arch->isa;
579 mips_cp0_names = chosen_arch->cp0_names;
580 mips_cp0sel_names = chosen_arch->cp0sel_names;
581 mips_cp0sel_names_len = chosen_arch->cp0sel_names_len;
582 mips_hwr_names = chosen_arch->hwr_names;
583 }
584 #endif
585 }
586
587 static void
parse_mips_dis_option(const char * option,unsigned int len)588 parse_mips_dis_option (const char *option, unsigned int len)
589 {
590 unsigned int i, optionlen, vallen;
591 const char *val;
592 const struct mips_abi_choice *chosen_abi;
593 const struct mips_arch_choice *chosen_arch;
594
595 /* Try to match options that are simple flags
596 if (CONST_STRNEQ (option, "no-aliases"))
597 {
598 no_aliases = 1;
599 return;
600 } */
601
602 /* Look for the = that delimits the end of the option name. */
603 for (i = 0; i < len; i++) {
604 if (option[i] == '=') {
605 break;
606 }
607 }
608
609 if (i == 0) { /* Invalid option: no name before '='. */
610 return;
611 }
612 if (i == len) { /* Invalid option: no '='. */
613 return;
614 }
615 if (i == (len - 1)) { /* Invalid option: no value after '='. */
616 return;
617 }
618
619 optionlen = i;
620 val = option + (optionlen + 1);
621 vallen = len - (optionlen + 1);
622
623 if (strlen ("abi") == optionlen
624 && !strncmp ("abi", option, optionlen)) {
625 chosen_abi = choose_abi_by_name (val, vallen);
626 if (chosen_abi) {
627 mips_gpr_names = chosen_abi->gpr_names;
628 mips_fpr_names = chosen_abi->fpr_names;
629 }
630 return;
631 }
632
633 if (strncmp ("gpr-names", option, optionlen) == 0
634 && strlen ("gpr-names") == optionlen)
635 {
636 chosen_abi = choose_abi_by_name (val, vallen);
637 if (chosen_abi != NULL) {
638 mips_gpr_names = chosen_abi->gpr_names;
639 }
640 return;
641 }
642
643 if (strncmp ("fpr-names", option, optionlen) == 0
644 && strlen ("fpr-names") == optionlen)
645 {
646 chosen_abi = choose_abi_by_name (val, vallen);
647 if (chosen_abi != NULL) {
648 mips_fpr_names = chosen_abi->fpr_names;
649 }
650 return;
651 }
652
653 if (strncmp ("cp0-names", option, optionlen) == 0
654 && strlen ("cp0-names") == optionlen)
655 {
656 chosen_arch = choose_arch_by_name (val, vallen);
657 if (chosen_arch != NULL)
658 {
659 mips_cp0_names = chosen_arch->cp0_names;
660 mips_cp0sel_names = chosen_arch->cp0sel_names;
661 mips_cp0sel_names_len = chosen_arch->cp0sel_names_len;
662 }
663 return;
664 }
665
666 if (strncmp ("hwr-names", option, optionlen) == 0
667 && strlen ("hwr-names") == optionlen)
668 {
669 chosen_arch = choose_arch_by_name (val, vallen);
670 if (chosen_arch != NULL) {
671 mips_hwr_names = chosen_arch->hwr_names;
672 }
673 return;
674 }
675
676 if (strncmp ("reg-names", option, optionlen) == 0
677 && strlen ("reg-names") == optionlen)
678 {
679 /* We check both ABI and ARCH here unconditionally, so
680 that "numeric" will do the desirable thing: select
681 numeric register names for all registers. Other than
682 that, a given name probably won't match both. */
683 chosen_abi = choose_abi_by_name (val, vallen);
684 if (chosen_abi != NULL)
685 {
686 mips_gpr_names = chosen_abi->gpr_names;
687 mips_fpr_names = chosen_abi->fpr_names;
688 }
689 chosen_arch = choose_arch_by_name (val, vallen);
690 if (chosen_arch != NULL)
691 {
692 mips_cp0_names = chosen_arch->cp0_names;
693 mips_cp0sel_names = chosen_arch->cp0sel_names;
694 mips_cp0sel_names_len = chosen_arch->cp0sel_names_len;
695 mips_hwr_names = chosen_arch->hwr_names;
696 }
697 return;
698 }
699
700 /* Invalid option. */
701 }
702
703 void
parse_mips_dis_options(const char * options)704 parse_mips_dis_options (const char *options)
705 {
706 const char *option_end;
707
708 if (!options) {
709 return;
710 }
711
712 while (*options != '\0')
713 {
714 /* Skip empty options. */
715 if (*options == ',')
716 {
717 options++;
718 continue;
719 }
720
721 /* We know that *options is neither NUL or a comma. */
722 option_end = options + 1;
723 while (*option_end != ',' && *option_end != '\0') {
724 option_end++;
725 }
726
727 parse_mips_dis_option (options, option_end - options);
728
729 /* Go on to the next one. If option_end points to a comma, it
730 will be skipped above. */
731 options = option_end;
732 }
733 }
734
735 static const struct mips_cp0sel_name *
lookup_mips_cp0sel_name(const struct mips_cp0sel_name * names,unsigned int len,unsigned int cp0reg,unsigned int sel)736 lookup_mips_cp0sel_name (const struct mips_cp0sel_name *names,
737 unsigned int len,
738 unsigned int cp0reg,
739 unsigned int sel)
740 {
741 unsigned int i;
742
743 for (i = 0; i < len; i++) {
744 if (names[i].cp0reg == cp0reg && names[i].sel == sel) {
745 return &names[i];
746 }
747 }
748 return NULL;
749 }
750
751 /* Print insn arguments for 32/64-bit code. */
752
753 static void
print_insn_args(const char * d,register unsigned long int l,bfd_vma pc,struct disassemble_info * info,const struct mips_opcode * opp)754 print_insn_args (const char *d,
755 register unsigned long int l,
756 bfd_vma pc,
757 struct disassemble_info *info,
758 const struct mips_opcode *opp)
759 {
760 int op, delta;
761 unsigned int lsb, msb, msbd;
762
763 lsb = 0;
764
765 for (; *d != '\0'; d++)
766 {
767 switch (*d)
768 {
769 case ',':
770 (*info->fprintf_func) (info->stream, "%c ", *d);
771 break;
772 case '(':
773 case ')':
774 case '[':
775 case ']':
776 (*info->fprintf_func) (info->stream, "%c", *d);
777 break;
778
779 case '+':
780 /* Extension character; switch for second char. */
781 d++;
782 switch (*d)
783 {
784 case '\0':
785 /* xgettext:c-format */
786 (*info->fprintf_func) (info->stream,
787 _("# internal error, incomplete extension sequence (+)"));
788 return;
789
790 case 'A':
791 lsb = (l >> OP_SH_SHAMT) & OP_MASK_SHAMT;
792 (*info->fprintf_func) (info->stream, "0x%x", lsb);
793 break;
794
795 case 'B':
796 msb = (l >> OP_SH_INSMSB) & OP_MASK_INSMSB;
797 (*info->fprintf_func) (info->stream, "0x%x", msb - lsb + 1);
798 break;
799
800 case '1':
801 (*info->fprintf_func) (info->stream, "0x%lx",
802 (l >> OP_SH_UDI1) & OP_MASK_UDI1);
803 break;
804
805 case '2':
806 (*info->fprintf_func) (info->stream, "0x%lx",
807 (l >> OP_SH_UDI2) & OP_MASK_UDI2);
808 break;
809
810 case '3':
811 (*info->fprintf_func) (info->stream, "0x%lx",
812 (l >> OP_SH_UDI3) & OP_MASK_UDI3);
813 break;
814
815 case '4':
816 (*info->fprintf_func) (info->stream, "0x%lx",
817 (l >> OP_SH_UDI4) & OP_MASK_UDI4);
818 break;
819
820 case 'C':
821 case 'H':
822 msbd = (l >> OP_SH_EXTMSBD) & OP_MASK_EXTMSBD;
823 (*info->fprintf_func) (info->stream, "0x%x", msbd + 1);
824 break;
825
826 case 'D':
827 {
828 const struct mips_cp0sel_name *n;
829 unsigned int cp0reg, sel;
830
831 cp0reg = (l >> OP_SH_RD) & OP_MASK_RD;
832 sel = (l >> OP_SH_SEL) & OP_MASK_SEL;
833
834 /* CP0 register including 'sel' code for mtcN (et al.), to be
835 printed textually if known. If not known, print both
836 CP0 register name and sel numerically since CP0 register
837 with sel 0 may have a name unrelated to register being
838 printed. */
839 n = lookup_mips_cp0sel_name(mips_cp0sel_names,
840 mips_cp0sel_names_len, cp0reg, sel);
841 if (n != NULL) {
842 (*info->fprintf_func) (info->stream, "%s", n->name);
843 } else {
844 (*info->fprintf_func) (info->stream, "$%d,%d", cp0reg, sel);
845 }
846 break;
847 }
848
849 case 'E':
850 lsb = ((l >> OP_SH_SHAMT) & OP_MASK_SHAMT) + 32;
851 (*info->fprintf_func) (info->stream, "0x%x", lsb);
852 break;
853
854 case 'F':
855 msb = ((l >> OP_SH_INSMSB) & OP_MASK_INSMSB) + 32;
856 (*info->fprintf_func) (info->stream, "0x%x", msb - lsb + 1);
857 break;
858
859 case 'G':
860 msbd = ((l >> OP_SH_EXTMSBD) & OP_MASK_EXTMSBD) + 32;
861 (*info->fprintf_func) (info->stream, "0x%x", msbd + 1);
862 break;
863
864 case 't': /* Coprocessor 0 reg name */
865 (*info->fprintf_func) (info->stream, "%s",
866 mips_cp0_names[(l >> OP_SH_RT) &
867 OP_MASK_RT]);
868 break;
869
870 case 'T': /* Coprocessor 0 reg name */
871 {
872 const struct mips_cp0sel_name *n;
873 unsigned int cp0reg, sel;
874
875 cp0reg = (l >> OP_SH_RT) & OP_MASK_RT;
876 sel = (l >> OP_SH_SEL) & OP_MASK_SEL;
877
878 /* CP0 register including 'sel' code for mftc0, to be
879 printed textually if known. If not known, print both
880 CP0 register name and sel numerically since CP0 register
881 with sel 0 may have a name unrelated to register being
882 printed. */
883 n = lookup_mips_cp0sel_name(mips_cp0sel_names,
884 mips_cp0sel_names_len, cp0reg, sel);
885 if (n != NULL) {
886 (*info->fprintf_func) (info->stream, "%s", n->name);
887 } else {
888 (*info->fprintf_func) (info->stream, "$%d,%d", cp0reg, sel);
889 }
890 break;
891 }
892
893 default:
894 /* xgettext:c-format */
895 (*info->fprintf_func) (info->stream,
896 _("# internal error, undefined extension sequence (+%c)"),
897 *d);
898 return;
899 }
900 break;
901
902 case '2':
903 (*info->fprintf_func) (info->stream, "0x%lx",
904 (l >> OP_SH_BP) & OP_MASK_BP);
905 break;
906
907 case '3':
908 (*info->fprintf_func) (info->stream, "0x%lx",
909 (l >> OP_SH_SA3) & OP_MASK_SA3);
910 break;
911
912 case '4':
913 (*info->fprintf_func) (info->stream, "0x%lx",
914 (l >> OP_SH_SA4) & OP_MASK_SA4);
915 break;
916
917 case '5':
918 (*info->fprintf_func) (info->stream, "0x%lx",
919 (l >> OP_SH_IMM8) & OP_MASK_IMM8);
920 break;
921
922 case '6':
923 (*info->fprintf_func) (info->stream, "0x%lx",
924 (l >> OP_SH_RS) & OP_MASK_RS);
925 break;
926
927 case '7':
928 (*info->fprintf_func) (info->stream, "$ac%ld",
929 (l >> OP_SH_DSPACC) & OP_MASK_DSPACC);
930 break;
931
932 case '8':
933 (*info->fprintf_func) (info->stream, "0x%lx",
934 (l >> OP_SH_WRDSP) & OP_MASK_WRDSP);
935 break;
936
937 case '9':
938 (*info->fprintf_func) (info->stream, "$ac%ld",
939 (l >> OP_SH_DSPACC_S) & OP_MASK_DSPACC_S);
940 break;
941
942 case '0': /* dsp 6-bit signed immediate in bit 20 */
943 delta = ((l >> OP_SH_DSPSFT) & OP_MASK_DSPSFT);
944 if (delta & 0x20) { /* test sign bit */
945 delta |= ~OP_MASK_DSPSFT;
946 }
947 (*info->fprintf_func) (info->stream, "%d", delta);
948 break;
949
950 case ':': /* dsp 7-bit signed immediate in bit 19 */
951 delta = ((l >> OP_SH_DSPSFT_7) & OP_MASK_DSPSFT_7);
952 if (delta & 0x40) { /* test sign bit */
953 delta |= ~OP_MASK_DSPSFT_7;
954 }
955 (*info->fprintf_func) (info->stream, "%d", delta);
956 break;
957
958 case '\'':
959 (*info->fprintf_func) (info->stream, "0x%lx",
960 (l >> OP_SH_RDDSP) & OP_MASK_RDDSP);
961 break;
962
963 case '@': /* dsp 10-bit signed immediate in bit 16 */
964 delta = ((l >> OP_SH_IMM10) & OP_MASK_IMM10);
965 if (delta & 0x200) { /* test sign bit */
966 delta |= ~OP_MASK_IMM10;
967 }
968 (*info->fprintf_func) (info->stream, "%d", delta);
969 break;
970
971 case '!':
972 (*info->fprintf_func) (info->stream, "%ld",
973 (l >> OP_SH_MT_U) & OP_MASK_MT_U);
974 break;
975
976 case '$':
977 (*info->fprintf_func) (info->stream, "%ld",
978 (l >> OP_SH_MT_H) & OP_MASK_MT_H);
979 break;
980
981 case '*':
982 (*info->fprintf_func) (info->stream, "$ac%ld",
983 (l >> OP_SH_MTACC_T) & OP_MASK_MTACC_T);
984 break;
985
986 case '&':
987 (*info->fprintf_func) (info->stream, "$ac%ld",
988 (l >> OP_SH_MTACC_D) & OP_MASK_MTACC_D);
989 break;
990
991 case 'g':
992 /* Coprocessor register for CTTC1, MTTC2, MTHC2, CTTC2. */
993 (*info->fprintf_func) (info->stream, "$%ld",
994 (l >> OP_SH_RD) & OP_MASK_RD);
995 break;
996
997 case 's':
998 case 'b':
999 case 'r':
1000 case 'v':
1001 (*info->fprintf_func) (info->stream, "%s",
1002 mips_gpr_names[(l >> OP_SH_RS) & OP_MASK_RS]);
1003 break;
1004
1005 case 't':
1006 case 'w':
1007 (*info->fprintf_func) (info->stream, "%s",
1008 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
1009 break;
1010
1011 case 'i':
1012 case 'u':
1013 (*info->fprintf_func) (info->stream, "0x%lx",
1014 (l >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE);
1015 break;
1016
1017 case 'j': /* Same as i, but sign-extended. */
1018 case 'o':
1019 delta = (l >> OP_SH_DELTA) & OP_MASK_DELTA;
1020 if (delta & 0x8000) {
1021 delta |= ~0xffff;
1022 }
1023 (*info->fprintf_func) (info->stream, "%d",
1024 delta);
1025 break;
1026
1027 case 'h':
1028 (*info->fprintf_func) (info->stream, "0x%x",
1029 (unsigned int) ((l >> OP_SH_PREFX)
1030 & OP_MASK_PREFX));
1031 break;
1032
1033 case 'k':
1034 (*info->fprintf_func) (info->stream, "0x%x",
1035 (unsigned int) ((l >> OP_SH_CACHE)
1036 & OP_MASK_CACHE));
1037 break;
1038
1039 case 'a':
1040 info->target = (((pc + 4) & ~(bfd_vma) 0x0fffffff)
1041 | (((l >> OP_SH_TARGET) & OP_MASK_TARGET) << 2));
1042 /* For gdb disassembler, force odd address on jalx. */
1043 //if (info->flavour == bfd_target_unknown_flavour
1044 // && strcmp (opp->name, "jalx") == 0)
1045 //info->target |= 1;
1046 (*info->print_address_func) (info->target, info);
1047 break;
1048
1049 case 'p':
1050 /* Sign extend the displacement. */
1051 delta = (l >> OP_SH_DELTA) & OP_MASK_DELTA;
1052 if (delta & 0x8000) {
1053 delta |= ~0xffff;
1054 }
1055 info->target = (delta << 2) + pc + INSNLEN;
1056 (*info->print_address_func) (info->target, info);
1057 break;
1058
1059 case 'd':
1060 (*info->fprintf_func) (info->stream, "%s",
1061 mips_gpr_names[(l >> OP_SH_RD) & OP_MASK_RD]);
1062 break;
1063
1064 case 'U':
1065 {
1066 /* First check for both rd and rt being equal. */
1067 unsigned int reg = (l >> OP_SH_RD) & OP_MASK_RD;
1068 if (reg == ((l >> OP_SH_RT) & OP_MASK_RT)) {
1069 (*info->fprintf_func) (info->stream, "%s",
1070 mips_gpr_names[reg]);
1071 } else {
1072 /* If one is zero use the other. */
1073 if (reg == 0) {
1074 (*info->fprintf_func) (info->stream, "%s",
1075 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
1076 } else if (((l >> OP_SH_RT) & OP_MASK_RT) == 0) {
1077 (*info->fprintf_func) (info->stream, "%s",
1078 mips_gpr_names[reg]);
1079 } else { /* Bogus, result depends on processor. */
1080 (*info->fprintf_func) (info->stream, "%s or %s",
1081 mips_gpr_names[reg],
1082 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
1083 }
1084 }
1085 }
1086 break;
1087
1088 case 'z':
1089 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[0]);
1090 break;
1091
1092 case '<':
1093 (*info->fprintf_func) (info->stream, "0x%lx",
1094 (l >> OP_SH_SHAMT) & OP_MASK_SHAMT);
1095 break;
1096
1097 case 'c':
1098 (*info->fprintf_func) (info->stream, "0x%lx",
1099 (l >> OP_SH_CODE) & OP_MASK_CODE);
1100 break;
1101
1102 case 'q':
1103 (*info->fprintf_func) (info->stream, "0x%lx",
1104 (l >> OP_SH_CODE2) & OP_MASK_CODE2);
1105 break;
1106
1107 case 'C':
1108 (*info->fprintf_func) (info->stream, "0x%lx",
1109 (l >> OP_SH_COPZ) & OP_MASK_COPZ);
1110 break;
1111
1112 case 'B':
1113 (*info->fprintf_func) (info->stream, "0x%lx",
1114
1115 (l >> OP_SH_CODE20) & OP_MASK_CODE20);
1116 break;
1117
1118 case 'J':
1119 (*info->fprintf_func) (info->stream, "0x%lx",
1120 (l >> OP_SH_CODE19) & OP_MASK_CODE19);
1121 break;
1122
1123 case 'S':
1124 case 'V':
1125 (*info->fprintf_func) (info->stream, "%s",
1126 mips_fpr_names[(l >> OP_SH_FS) & OP_MASK_FS]);
1127 break;
1128
1129 case 'T':
1130 case 'W':
1131 (*info->fprintf_func) (info->stream, "%s",
1132 mips_fpr_names[(l >> OP_SH_FT) & OP_MASK_FT]);
1133 break;
1134
1135 case 'D':
1136 (*info->fprintf_func) (info->stream, "%s",
1137 mips_fpr_names[(l >> OP_SH_FD) & OP_MASK_FD]);
1138 break;
1139
1140 case 'R':
1141 (*info->fprintf_func) (info->stream, "%s",
1142 mips_fpr_names[(l >> OP_SH_FR) & OP_MASK_FR]);
1143 break;
1144
1145 case 'E':
1146 /* Coprocessor register for lwcN instructions, et al.
1147
1148 Note that there is no load/store cp0 instructions, and
1149 that FPU (cp1) instructions disassemble this field using
1150 'T' format. Therefore, until we gain understanding of
1151 cp2 register names, we can simply print the register
1152 numbers. */
1153 (*info->fprintf_func) (info->stream, "$%ld",
1154 (l >> OP_SH_RT) & OP_MASK_RT);
1155 break;
1156
1157 case 'G':
1158 /* Coprocessor register for mtcN instructions, et al. Note
1159 that FPU (cp1) instructions disassemble this field using
1160 'S' format. Therefore, we only need to worry about cp0,
1161 cp2, and cp3. */
1162 op = (l >> OP_SH_OP) & OP_MASK_OP;
1163 if (op == OP_OP_COP0) {
1164 (*info->fprintf_func) (info->stream, "%s",
1165 mips_cp0_names[(l >> OP_SH_RD) & OP_MASK_RD]);
1166 } else {
1167 (*info->fprintf_func) (info->stream, "$%ld",
1168 (l >> OP_SH_RD) & OP_MASK_RD);
1169 }
1170 break;
1171
1172 case 'K':
1173 (*info->fprintf_func) (info->stream, "%s",
1174 mips_hwr_names[(l >> OP_SH_RD) & OP_MASK_RD]);
1175 break;
1176
1177 case 'N':
1178 (*info->fprintf_func) (info->stream,
1179 ((opp->pinfo & (FP_D | FP_S)) != 0
1180 ? "$fcc%ld" : "$cc%ld"),
1181 (l >> OP_SH_BCC) & OP_MASK_BCC);
1182 break;
1183
1184 case 'M':
1185 (*info->fprintf_func) (info->stream, "$fcc%ld",
1186 (l >> OP_SH_CCC) & OP_MASK_CCC);
1187 break;
1188
1189 case 'P':
1190 (*info->fprintf_func) (info->stream, "%ld",
1191 (l >> OP_SH_PERFREG) & OP_MASK_PERFREG);
1192 break;
1193
1194 case 'e':
1195 (*info->fprintf_func) (info->stream, "%ld",
1196 (l >> OP_SH_VECBYTE) & OP_MASK_VECBYTE);
1197 break;
1198
1199 case '%':
1200 (*info->fprintf_func) (info->stream, "%ld",
1201 (l >> OP_SH_VECALIGN) & OP_MASK_VECALIGN);
1202 break;
1203
1204 case 'H':
1205 (*info->fprintf_func) (info->stream, "%ld",
1206 (l >> OP_SH_SEL) & OP_MASK_SEL);
1207 break;
1208
1209 case 'O':
1210 (*info->fprintf_func) (info->stream, "%ld",
1211 (l >> OP_SH_ALN) & OP_MASK_ALN);
1212 break;
1213
1214 case 'Q':
1215 {
1216 unsigned int vsel = (l >> OP_SH_VSEL) & OP_MASK_VSEL;
1217
1218 if ((vsel & 0x10) == 0)
1219 {
1220 int fmt;
1221
1222 vsel &= 0x0f;
1223 for (fmt = 0; fmt < 3; fmt++, vsel >>= 1) {
1224 if ((vsel & 1) == 0) {
1225 break;
1226 }
1227 }
1228 (*info->fprintf_func) (info->stream, "$v%ld[%d]",
1229 (l >> OP_SH_FT) & OP_MASK_FT,
1230 vsel >> 1);
1231 }
1232 else if ((vsel & 0x08) == 0)
1233 {
1234 (*info->fprintf_func) (info->stream, "$v%ld",
1235 (l >> OP_SH_FT) & OP_MASK_FT);
1236 }
1237 else
1238 {
1239 (*info->fprintf_func) (info->stream, "0x%lx",
1240 (l >> OP_SH_FT) & OP_MASK_FT);
1241 }
1242 }
1243 break;
1244
1245 case 'X':
1246 (*info->fprintf_func) (info->stream, "$v%ld",
1247 (l >> OP_SH_FD) & OP_MASK_FD);
1248 break;
1249
1250 case 'Y':
1251 (*info->fprintf_func) (info->stream, "$v%ld",
1252 (l >> OP_SH_FS) & OP_MASK_FS);
1253 break;
1254
1255 case 'Z':
1256 (*info->fprintf_func) (info->stream, "$v%ld",
1257 (l >> OP_SH_FT) & OP_MASK_FT);
1258 break;
1259
1260 default:
1261 /* xgettext:c-format */
1262 (*info->fprintf_func) (info->stream,
1263 _("# internal error, undefined modifier(%c)"),
1264 *d);
1265 return;
1266 }
1267 }
1268 }
1269
1270 /* Print the mips instruction at address MEMADDR in debugged memory,
1271 on using INFO. Returns length of the instruction, in bytes, which is
1272 always INSNLEN. BIGENDIAN must be 1 if this is big-endian code, 0 if
1273 this is little-endian code. */
1274
1275 static int
print_insn_mips(bfd_vma memaddr,unsigned long int word,struct disassemble_info * info)1276 print_insn_mips (bfd_vma memaddr,
1277 unsigned long int word,
1278 struct disassemble_info *info)
1279 {
1280 const struct mips_opcode *op;
1281 static bfd_boolean init = 0;
1282 static const struct mips_opcode *mips_hash[OP_MASK_OP + 1];
1283
1284 /* Build a hash table to shorten the search time. */
1285 if (! init)
1286 {
1287 unsigned int i;
1288
1289 for (i = 0; i <= OP_MASK_OP; i++)
1290 {
1291 for (op = mips_opcodes; op < &mips_opcodes[NUMOPCODES]; op++)
1292 {
1293 if (op->pinfo == INSN_MACRO || (no_aliases && (op->pinfo2 & INSN2_ALIAS))) {
1294 continue;
1295 }
1296 if (i == ((op->match >> OP_SH_OP) & OP_MASK_OP)) {
1297 mips_hash[i] = op;
1298 break;
1299 }
1300 }
1301 }
1302
1303 init = 1;
1304 }
1305
1306 info->bytes_per_chunk = INSNLEN;
1307 info->display_endian = info->endian;
1308 info->insn_info_valid = 1;
1309 info->branch_delay_insns = 0;
1310 info->data_size = 0;
1311 info->insn_type = dis_nonbranch;
1312 info->target = 0;
1313 info->target2 = 0;
1314
1315 op = mips_hash[(word >> OP_SH_OP) & OP_MASK_OP];
1316 if (op != NULL)
1317 {
1318 for (; op < &mips_opcodes[NUMOPCODES]; op++)
1319 {
1320 if (op->pinfo != INSN_MACRO
1321 && !(no_aliases && (op->pinfo2 & INSN2_ALIAS))
1322 && (word & op->mask) == op->match)
1323 {
1324 const char *d;
1325
1326 /* We always allow to disassemble the jalx instruction. */
1327 if (!OPCODE_IS_MEMBER (op, mips_isa, mips_processor) && strcmp (op->name, "jalx")) {
1328 continue;
1329 }
1330
1331 /* Figure out instruction type and branch delay information. */
1332 if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
1333 {
1334 if ((info->insn_type & INSN_WRITE_GPR_31) != 0) {
1335 info->insn_type = dis_jsr;
1336 } else {
1337 info->insn_type = dis_branch;
1338 }
1339 info->branch_delay_insns = 1;
1340 }
1341 else if ((op->pinfo & (INSN_COND_BRANCH_DELAY
1342 | INSN_COND_BRANCH_LIKELY)) != 0)
1343 {
1344 if ((info->insn_type & INSN_WRITE_GPR_31) != 0) {
1345 info->insn_type = dis_condjsr;
1346 } else {
1347 info->insn_type = dis_condbranch;
1348 }
1349 info->branch_delay_insns = 1;
1350 } else if ((op->pinfo & (INSN_STORE_MEMORY | INSN_LOAD_MEMORY_DELAY)) != 0) {
1351 info->insn_type = dis_dref;
1352 }
1353
1354 (*info->fprintf_func) (info->stream, "%s", op->name);
1355
1356 d = op->args;
1357 if (d != NULL && *d != '\0') {
1358 (*info->fprintf_func) (info->stream, " ");
1359 print_insn_args (d, word, memaddr, info, op);
1360 }
1361
1362 return INSNLEN;
1363 }
1364 }
1365 }
1366
1367 /* Plugin undefined instructions. */
1368 info->insn_type = dis_noninsn;
1369 (*info->fprintf_func) (info->stream, "0x%lx", word);
1370 return INSNLEN;
1371 }
1372
1373 /* Disassemble an operand for a mips16 instruction. */
1374
1375 static void
print_mips16_insn_arg(char type,const struct mips_opcode * op,int l,bfd_boolean use_extend,int extend,bfd_vma memaddr,struct disassemble_info * info)1376 print_mips16_insn_arg (char type,
1377 const struct mips_opcode *op,
1378 int l,
1379 bfd_boolean use_extend,
1380 int extend,
1381 bfd_vma memaddr,
1382 struct disassemble_info *info)
1383 {
1384 switch (type)
1385 {
1386 case ',':
1387 case '(':
1388 case ')':
1389 (*info->fprintf_func) (info->stream, "%c", type);
1390 break;
1391
1392 case 'y':
1393 case 'w':
1394 (*info->fprintf_func) (info->stream, "%s",
1395 mips16_reg_names(((l >> MIPS16OP_SH_RY)
1396 & MIPS16OP_MASK_RY)));
1397 break;
1398
1399 case 'x':
1400 case 'v':
1401 (*info->fprintf_func) (info->stream, "%s",
1402 mips16_reg_names(((l >> MIPS16OP_SH_RX)
1403 & MIPS16OP_MASK_RX)));
1404 break;
1405
1406 case 'z':
1407 (*info->fprintf_func) (info->stream, "%s",
1408 mips16_reg_names(((l >> MIPS16OP_SH_RZ)
1409 & MIPS16OP_MASK_RZ)));
1410 break;
1411
1412 case 'Z':
1413 (*info->fprintf_func) (info->stream, "%s",
1414 mips16_reg_names(((l >> MIPS16OP_SH_MOVE32Z)
1415 & MIPS16OP_MASK_MOVE32Z)));
1416 break;
1417
1418 case '0':
1419 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[0]);
1420 break;
1421
1422 case 'S':
1423 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[29]);
1424 break;
1425
1426 case 'P':
1427 (*info->fprintf_func) (info->stream, "$pc");
1428 break;
1429
1430 case 'R':
1431 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[31]);
1432 break;
1433
1434 case 'X':
1435 (*info->fprintf_func) (info->stream, "%s",
1436 mips_gpr_names[((l >> MIPS16OP_SH_REGR32)
1437 & MIPS16OP_MASK_REGR32)]);
1438 break;
1439
1440 case 'Y':
1441 (*info->fprintf_func) (info->stream, "%s",
1442 mips_gpr_names[MIPS16OP_EXTRACT_REG32R (l)]);
1443 break;
1444
1445 case '<':
1446 case '>':
1447 case '[':
1448 case ']':
1449 case '4':
1450 case '5':
1451 case 'H':
1452 case 'W':
1453 case 'D':
1454 case 'j':
1455 case '6':
1456 case '8':
1457 case 'V':
1458 case 'C':
1459 case 'U':
1460 case 'k':
1461 case 'K':
1462 case 'p':
1463 case 'q':
1464 case 'A':
1465 case 'B':
1466 case 'E':
1467 {
1468 int immed, nbits, shift, signedp, extbits, pcrel, extu, branch;
1469
1470 shift = 0;
1471 signedp = 0;
1472 extbits = 16;
1473 pcrel = 0;
1474 extu = 0;
1475 branch = 0;
1476 switch (type)
1477 {
1478 case '<':
1479 nbits = 3;
1480 immed = (l >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ;
1481 extbits = 5;
1482 extu = 1;
1483 break;
1484 case '>':
1485 nbits = 3;
1486 immed = (l >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX;
1487 extbits = 5;
1488 extu = 1;
1489 break;
1490 case '[':
1491 nbits = 3;
1492 immed = (l >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ;
1493 extbits = 6;
1494 extu = 1;
1495 break;
1496 case ']':
1497 nbits = 3;
1498 immed = (l >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX;
1499 extbits = 6;
1500 extu = 1;
1501 break;
1502 case '4':
1503 nbits = 4;
1504 immed = (l >> MIPS16OP_SH_IMM4) & MIPS16OP_MASK_IMM4;
1505 signedp = 1;
1506 extbits = 15;
1507 break;
1508 case '5':
1509 nbits = 5;
1510 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1511 info->insn_type = dis_dref;
1512 info->data_size = 1;
1513 break;
1514 case 'H':
1515 nbits = 5;
1516 shift = 1;
1517 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1518 info->insn_type = dis_dref;
1519 info->data_size = 2;
1520 break;
1521 case 'W':
1522 nbits = 5;
1523 shift = 2;
1524 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1525 if ((op->pinfo & MIPS16_INSN_READ_PC) == 0
1526 && (op->pinfo & MIPS16_INSN_READ_SP) == 0)
1527 {
1528 info->insn_type = dis_dref;
1529 info->data_size = 4;
1530 }
1531 break;
1532 case 'D':
1533 nbits = 5;
1534 shift = 3;
1535 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1536 info->insn_type = dis_dref;
1537 info->data_size = 8;
1538 break;
1539 case 'j':
1540 nbits = 5;
1541 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1542 signedp = 1;
1543 break;
1544 case '6':
1545 nbits = 6;
1546 immed = (l >> MIPS16OP_SH_IMM6) & MIPS16OP_MASK_IMM6;
1547 break;
1548 case '8':
1549 nbits = 8;
1550 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1551 break;
1552 case 'V':
1553 nbits = 8;
1554 shift = 2;
1555 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1556 /* FIXME: This might be lw, or it might be addiu to $sp or
1557 $pc. We assume it's load. */
1558 info->insn_type = dis_dref;
1559 info->data_size = 4;
1560 break;
1561 case 'C':
1562 nbits = 8;
1563 shift = 3;
1564 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1565 info->insn_type = dis_dref;
1566 info->data_size = 8;
1567 break;
1568 case 'U':
1569 nbits = 8;
1570 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1571 extu = 1;
1572 break;
1573 case 'k':
1574 nbits = 8;
1575 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1576 signedp = 1;
1577 break;
1578 case 'K':
1579 nbits = 8;
1580 shift = 3;
1581 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1582 signedp = 1;
1583 break;
1584 case 'p':
1585 nbits = 8;
1586 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1587 signedp = 1;
1588 pcrel = 1;
1589 branch = 1;
1590 info->insn_type = dis_condbranch;
1591 break;
1592 case 'q':
1593 nbits = 11;
1594 immed = (l >> MIPS16OP_SH_IMM11) & MIPS16OP_MASK_IMM11;
1595 signedp = 1;
1596 pcrel = 1;
1597 branch = 1;
1598 info->insn_type = dis_branch;
1599 break;
1600 case 'A':
1601 nbits = 8;
1602 shift = 2;
1603 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1604 pcrel = 1;
1605 /* FIXME: This can be lw or la. We assume it is lw. */
1606 info->insn_type = dis_dref;
1607 info->data_size = 4;
1608 break;
1609 case 'B':
1610 nbits = 5;
1611 shift = 3;
1612 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1613 pcrel = 1;
1614 info->insn_type = dis_dref;
1615 info->data_size = 8;
1616 break;
1617 case 'E':
1618 nbits = 5;
1619 shift = 2;
1620 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1621 pcrel = 1;
1622 break;
1623 default:
1624 abort ();
1625 }
1626
1627 if (! use_extend)
1628 {
1629 if (signedp && immed >= (1 << (nbits - 1))) {
1630 immed -= 1 << nbits;
1631 }
1632 immed <<= shift;
1633 if ((type == '<' || type == '>' || type == '[' || type == ']') && immed == 0) {
1634 immed = 8;
1635 }
1636 }
1637 else
1638 {
1639 if (extbits == 16) {
1640 immed |= ((extend & 0x1f) << 11) | (extend & 0x7e0);
1641 } else if (extbits == 15) {
1642 immed |= ((extend & 0xf) << 11) | (extend & 0x7f0);
1643 } else {
1644 immed = ((extend >> 6) & 0x1f) | (extend & 0x20);
1645 }
1646 immed &= (1 << extbits) - 1;
1647 if (!extu && immed >= (1 << (extbits - 1))) {
1648 immed -= 1 << extbits;
1649 }
1650 }
1651
1652 if (!pcrel) {
1653 (*info->fprintf_func) (info->stream, "%d", immed);
1654 } else {
1655 bfd_vma baseaddr;
1656
1657 if (branch) {
1658 immed *= 2;
1659 baseaddr = memaddr + 2;
1660 } else if (use_extend) {
1661 baseaddr = memaddr - 2;
1662 } else {
1663 int status;
1664 bfd_byte buffer[2];
1665
1666 baseaddr = memaddr;
1667
1668 /* If this instruction is in the delay slot of a jr
1669 instruction, the base address is the address of the
1670 jr instruction. If it is in the delay slot of jalr
1671 instruction, the base address is the address of the
1672 jalr instruction. This test is unreliable: we have
1673 no way of knowing whether the previous word is
1674 instruction or data. */
1675 status = (*info->read_memory_func) (memaddr - 4, buffer, 2,
1676 info);
1677 if (status == 0 && (((info->endian == BFD_ENDIAN_BIG
1678 ? bfd_getb16 (buffer)
1679 : bfd_getl16 (buffer)) &
1680 0xf800) == 0x1800)) {
1681 baseaddr = memaddr - 4;
1682 } else {
1683 status = (*info->read_memory_func) (memaddr - 2, buffer,
1684 2, info);
1685 if (status == 0 && (((info->endian == BFD_ENDIAN_BIG
1686 ? bfd_getb16 (buffer)
1687 : bfd_getl16 (buffer)) &
1688 0xf81f) == 0xe800)) {
1689 baseaddr = memaddr - 2;
1690 }
1691 }
1692 }
1693 info->target = (baseaddr & ~((1 << shift) - 1)) + immed;
1694 if (pcrel && branch && info->flavour == bfd_target_unknown_flavour) {
1695 /* For gdb disassembler, maintain odd address. */
1696 info->target |= 1;
1697 }
1698 (*info->print_address_func) (info->target, info);
1699 }
1700 }
1701 break;
1702
1703 case 'a':
1704 {
1705 int jalx = l & 0x400;
1706
1707 if (!use_extend) {
1708 extend = 0;
1709 }
1710 l = ((l & 0x1f) << 23) | ((l & 0x3e0) << 13) | (extend << 2);
1711 if (!jalx && info->flavour == bfd_target_unknown_flavour) {
1712 /* For gdb disassembler, maintain odd address. */
1713 l |= 1;
1714 }
1715 }
1716 info->target = ((memaddr + 4) & ~(bfd_vma) 0x0fffffff) | l;
1717 (*info->print_address_func) (info->target, info);
1718 info->insn_type = dis_jsr;
1719 info->branch_delay_insns = 1;
1720 break;
1721
1722 case 'l':
1723 case 'L':
1724 {
1725 int need_comma, amask, smask;
1726
1727 need_comma = 0;
1728
1729 l = (l >> MIPS16OP_SH_IMM6) & MIPS16OP_MASK_IMM6;
1730
1731 amask = (l >> 3) & 7;
1732
1733 if (amask > 0 && amask < 5)
1734 {
1735 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[4]);
1736 if (amask > 1) {
1737 (*info->fprintf_func) (info->stream, "-%s",
1738 mips_gpr_names[amask + 3]);
1739 }
1740 need_comma = 1;
1741 }
1742
1743 smask = (l >> 1) & 3;
1744 if (smask == 3)
1745 {
1746 (*info->fprintf_func) (info->stream, "%s??",
1747 need_comma ? ", " : "");
1748 need_comma = 1;
1749 }
1750 else if (smask > 0)
1751 {
1752 (*info->fprintf_func) (info->stream, "%s%s",
1753 need_comma ? ", " : "",
1754 mips_gpr_names[16]);
1755 if (smask > 1) {
1756 (*info->fprintf_func) (info->stream, "-%s",
1757 mips_gpr_names[smask + 15]);
1758 }
1759 need_comma = 1;
1760 }
1761
1762 if (l & 1)
1763 {
1764 (*info->fprintf_func) (info->stream, "%s%s",
1765 need_comma ? ", " : "",
1766 mips_gpr_names[31]);
1767 need_comma = 1;
1768 }
1769
1770 if (amask == 5 || amask == 6)
1771 {
1772 (*info->fprintf_func) (info->stream, "%s$f0",
1773 need_comma ? ", " : "");
1774 if (amask == 6) {
1775 (*info->fprintf_func) (info->stream, "-$f1");
1776 }
1777 }
1778 }
1779 break;
1780
1781 case 'm':
1782 case 'M':
1783 /* MIPS16e save/restore. */
1784 {
1785 int need_comma = 0;
1786 int amask, args, statics;
1787 int nsreg, smask;
1788 int framesz;
1789 int i, j;
1790
1791 l = l & 0x7f;
1792 if (use_extend) {
1793 l |= extend << 16;
1794 }
1795
1796 amask = (l >> 16) & 0xf;
1797 if (amask == MIPS16_ALL_ARGS)
1798 {
1799 args = 4;
1800 statics = 0;
1801 }
1802 else if (amask == MIPS16_ALL_STATICS)
1803 {
1804 args = 0;
1805 statics = 4;
1806 }
1807 else
1808 {
1809 args = amask >> 2;
1810 statics = amask & 3;
1811 }
1812
1813 if (args > 0) {
1814 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[4]);
1815 if (args > 1) {
1816 (*info->fprintf_func) (info->stream, "-%s",
1817 mips_gpr_names[4 + args - 1]);
1818 }
1819 need_comma = 1;
1820 }
1821
1822 framesz = (((l >> 16) & 0xf0) | (l & 0x0f)) * 8;
1823 if (framesz == 0 && !use_extend) {
1824 framesz = 128;
1825 }
1826
1827 (*info->fprintf_func) (info->stream, "%s%d",
1828 need_comma ? ", " : "",
1829 framesz);
1830
1831 if (l & 0x40) { /* $ra */
1832 (*info->fprintf_func) (info->stream, ", %s", mips_gpr_names[31]);
1833 }
1834
1835 nsreg = (l >> 24) & 0x7;
1836 smask = 0;
1837 if (l & 0x20) { /* $s0 */
1838 smask |= 1 << 0;
1839 }
1840 if (l & 0x10) { /* $s1 */
1841 smask |= 1 << 1;
1842 }
1843 if (nsreg > 0) { /* $s2-$s8 */
1844 smask |= ((1 << nsreg) - 1) << 2;
1845 }
1846
1847 /* Find first set static reg bit. */
1848 for (i = 0; i < 9; i++)
1849 {
1850 if (smask & (1 << i))
1851 {
1852 (*info->fprintf_func) (info->stream, ", %s",
1853 mips_gpr_names[i == 8 ? 30 : (16 + i)]);
1854 /* Skip over string of set bits. */
1855 for (j = i; smask & (2 << j); j++) {}
1856 if (j > i) {
1857 (*info->fprintf_func) (info->stream, "-%s",
1858 mips_gpr_names[j == 8 ? 30 : (16 + j)]);
1859 }
1860 i = j + 1;
1861 }
1862 }
1863
1864 /* Statics $ax - $a3. */
1865 if (statics == 1) {
1866 (*info->fprintf_func) (info->stream, ", %s", mips_gpr_names[7]);
1867 } else if (statics > 0) {
1868 (*info->fprintf_func) (info->stream, ", %s-%s",
1869 mips_gpr_names[7 - statics + 1],
1870 mips_gpr_names[7]);
1871 }
1872 }
1873 break;
1874
1875 default:
1876 /* xgettext:c-format */
1877 (*info->fprintf_func)
1878 (info->stream,
1879 _("# internal disassembler error, unrecognised modifier (%c)"),
1880 type);
1881 abort ();
1882 }
1883 }
1884
1885 /* Disassemble mips16 instructions. */
1886
1887 static int
print_insn_mips16(bfd_vma memaddr,struct disassemble_info * info)1888 print_insn_mips16 (bfd_vma memaddr, struct disassemble_info *info)
1889 {
1890 int status;
1891 bfd_byte buffer[2];
1892 int length;
1893 int insn;
1894 bfd_boolean use_extend;
1895 int extend = 0;
1896 const struct mips_opcode *op, *opend;
1897
1898 info->bytes_per_chunk = 2;
1899 info->display_endian = info->endian;
1900 info->insn_info_valid = 1;
1901 info->branch_delay_insns = 0;
1902 info->data_size = 0;
1903 info->insn_type = dis_nonbranch;
1904 info->target = 0;
1905 info->target2 = 0;
1906
1907 status = (*info->read_memory_func) (memaddr, buffer, 2, info);
1908 if (status != 0)
1909 {
1910 (*info->memory_error_func) (status, memaddr, info);
1911 return -1;
1912 }
1913
1914 length = 2;
1915
1916 if (info->endian == BFD_ENDIAN_BIG) {
1917 insn = bfd_getb16 (buffer);
1918 } else {
1919 insn = bfd_getl16 (buffer);
1920 }
1921
1922 /* Plugin the extend opcode specially. */
1923 use_extend = FALSE;
1924 if ((insn & 0xf800) == 0xf000)
1925 {
1926 use_extend = TRUE;
1927 extend = insn & 0x7ff;
1928
1929 memaddr += 2;
1930
1931 status = (*info->read_memory_func) (memaddr, buffer, 2, info);
1932 if (status != 0)
1933 {
1934 (*info->fprintf_func) (info->stream, "extend 0x%x",
1935 (unsigned int) extend);
1936 (*info->memory_error_func) (status, memaddr, info);
1937 return -1;
1938 }
1939
1940 if (info->endian == BFD_ENDIAN_BIG) {
1941 insn = bfd_getb16 (buffer);
1942 } else {
1943 insn = bfd_getl16 (buffer);
1944 }
1945
1946 /* Check for an extend opcode followed by an extend opcode. */
1947 if ((insn & 0xf800) == 0xf000) {
1948 (*info->fprintf_func) (info->stream, "extend 0x%x",
1949 (unsigned int)extend);
1950 info->insn_type = dis_noninsn;
1951 return length;
1952 }
1953
1954 length += 2;
1955 }
1956
1957 /* FIXME: Should probably use a hash table on the major opcode here. */
1958
1959 opend = mips16_opcodes + bfd_mips16_num_opcodes;
1960 for (op = mips16_opcodes; op < opend; op++)
1961 {
1962 if (op->pinfo != INSN_MACRO
1963 && !(no_aliases && (op->pinfo2 & INSN2_ALIAS))
1964 && (insn & op->mask) == op->match)
1965 {
1966 const char *s;
1967
1968 if (strchr (op->args, 'a') != NULL)
1969 {
1970 if (use_extend)
1971 {
1972 (*info->fprintf_func) (info->stream, "extend 0x%x",
1973 (unsigned int) extend);
1974 info->insn_type = dis_noninsn;
1975 return length - 2;
1976 }
1977
1978 use_extend = FALSE;
1979
1980 memaddr += 2;
1981
1982 status = (*info->read_memory_func) (memaddr, buffer, 2,
1983 info);
1984 if (status == 0)
1985 {
1986 use_extend = TRUE;
1987 if (info->endian == BFD_ENDIAN_BIG) {
1988 extend = bfd_getb16 (buffer);
1989 } else {
1990 extend = bfd_getl16 (buffer);
1991 }
1992 length += 2;
1993 }
1994 }
1995
1996 (*info->fprintf_func) (info->stream, "%s", op->name);
1997 if (op->args[0] != '\0') {
1998 (*info->fprintf_func) (info->stream, " ");
1999 }
2000
2001 for (s = op->args; *s != '\0'; s++)
2002 {
2003 if (*s == ','
2004 && s[1] == 'w'
2005 && (((insn >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX)
2006 == ((insn >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY)))
2007 {
2008 /* Skip the register and the comma. */
2009 ++s;
2010 continue;
2011 }
2012 if (*s == ','
2013 && s[1] == 'v'
2014 && (((insn >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ)
2015 == ((insn >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX)))
2016 {
2017 /* Skip the register and the comma. */
2018 ++s;
2019 continue;
2020 }
2021 print_mips16_insn_arg (*s, op, insn, use_extend, extend, memaddr,
2022 info);
2023 }
2024
2025 if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
2026 {
2027 info->branch_delay_insns = 1;
2028 if (info->insn_type != dis_jsr) {
2029 info->insn_type = dis_branch;
2030 }
2031 }
2032
2033 return length;
2034 }
2035 }
2036
2037 if (use_extend) {
2038 (*info->fprintf_func) (info->stream, "0x%x", extend | 0xf000);
2039 }
2040 (*info->fprintf_func) (info->stream, "0x%x", insn);
2041 info->insn_type = dis_noninsn;
2042
2043 return length;
2044 }
2045
2046 /* In an environment where we do not know the symbol type of the
2047 instruction we are forced to assume that the low order bit of the
2048 instructions' address may mark it as a mips16 instruction. If we
2049 are single stepping, or the pc is within the disassembled function,
2050 this works. Otherwise, we need a clue. Sometimes. */
2051
2052 static int
_print_insn_mips(bfd_vma memaddr,struct disassemble_info * info,enum bfd_endian endianness)2053 _print_insn_mips (bfd_vma memaddr,
2054 struct disassemble_info *info,
2055 enum bfd_endian endianness)
2056 {
2057 bfd_byte buffer[INSNLEN];
2058 int status;
2059
2060 set_default_mips_dis_options (info);
2061 parse_mips_dis_options (info->disassembler_options);
2062
2063 #if 1
2064 /* FIXME: If odd address, this is CLEARLY a mips 16 instruction. */
2065 /* Only a few tools will work this way. */
2066 if (memaddr & 0x01) {
2067 return print_insn_mips16 (memaddr, info);
2068 }
2069 #endif
2070
2071 #if SYMTAB_AVAILABLE
2072 if (info->mach == bfd_mach_mips16 || (info->flavour == bfd_target_elf_flavour && info->symbols != NULL && ((*(elf_symbol_type **)info->symbols)->internal_elf_sym.st_other == STO_MIPS16))) {
2073 return print_insn_mips16 (memaddr, info);
2074 }
2075 #endif
2076
2077 status = (*info->read_memory_func) (memaddr, buffer, INSNLEN, info);
2078 if (status == 0)
2079 {
2080 unsigned long insn;
2081
2082 if (endianness == BFD_ENDIAN_BIG) {
2083 insn = (unsigned long)bfd_getb32 (buffer);
2084 } else {
2085 insn = (unsigned long)bfd_getl32 (buffer);
2086 }
2087
2088 return print_insn_mips (memaddr, insn, info);
2089 }
2090 else
2091 {
2092 (*info->memory_error_func) (status, memaddr, info);
2093 return -1;
2094 }
2095 }
2096
2097 int
print_insn_big_mips(bfd_vma memaddr,struct disassemble_info * info)2098 print_insn_big_mips (bfd_vma memaddr, struct disassemble_info *info)
2099 {
2100 return _print_insn_mips (memaddr, info, BFD_ENDIAN_BIG);
2101 }
2102
2103 int
print_insn_little_mips(bfd_vma memaddr,struct disassemble_info * info)2104 print_insn_little_mips (bfd_vma memaddr, struct disassemble_info *info)
2105 {
2106 return _print_insn_mips (memaddr, info, BFD_ENDIAN_LITTLE);
2107 }
2108
2109 void
print_mips_disassembler_options(FILE * stream)2110 print_mips_disassembler_options (FILE *stream)
2111 {
2112 unsigned int i;
2113
2114 fprintf (stream, _("\n\
2115 The following MIPS specific disassembler options are supported for use\n\
2116 with the -M switch (multiple options should be separated by commas):\n"));
2117
2118 fprintf (stream, _("\n\
2119 gpr-names=ABI Print GPR names according to specified ABI.\n\
2120 Default: based on binary being disassembled.\n"));
2121
2122 fprintf (stream, _("\n\
2123 fpr-names=ABI Print FPR names according to specified ABI.\n\
2124 Default: numeric.\n"));
2125
2126 fprintf (stream, _("\n\
2127 cp0-names=ARCH Print CP0 register names according to\n\
2128 specified architecture.\n\
2129 Default: based on binary being disassembled.\n"));
2130
2131 fprintf (stream, _("\n\
2132 hwr-names=ARCH Print HWR names according to specified \n\
2133 architecture.\n\
2134 Default: based on binary being disassembled.\n"));
2135
2136 fprintf (stream, _("\n\
2137 reg-names=ABI Print GPR and FPR names according to\n\
2138 specified ABI.\n"));
2139
2140 fprintf (stream, _("\n\
2141 reg-names=ARCH Print CP0 register and HWR names according to\n\
2142 specified architecture.\n"));
2143
2144 fprintf (stream, _("\n\
2145 For the options above, the following values are supported for \"ABI\":\n\
2146 "));
2147 for (i = 0; i < ARRAY_SIZE (mips_abi_choices); i++) {
2148 fprintf (stream, " %s", mips_abi_choices[i].name);
2149 }
2150 fprintf (stream, _("\n"));
2151
2152 fprintf (stream, _("\n\
2153 For the options above, The following values are supported for \"ARCH\":\n\
2154 "));
2155 for (i = 0; i < ARRAY_SIZE (mips_arch_choices); i++) {
2156 if (*mips_arch_choices[i].name != '\0') {
2157 fprintf (stream, " %s", mips_arch_choices[i].name);
2158 }
2159 }
2160 fprintf (stream, _("\n"));
2161
2162 fprintf (stream, _("\n"));
2163 }
2164