xref: /dports/devel/radare2/radare2-5.1.1/shlr/arm/omap3430_registers

f OMAP3430_SCM_BASE 0x48002000
f OMAP3430_SCM_END 0x48003FFF
f OMAP3430_CM_REG_A_BASE 0x48004000
f OMAP3430_CM_REG_A_END 0x48005FFF
f OMAP3430_PRM_BASE 0x48306000
f OMAP3430_PRM_END 0x48307FFF
f OMAP3430_L4_AP_BASE 0x48040000
f OMAP3430_L4_AP_END 0x480407FF
f OMAP3430_L4_IP_BASE 0x48040800
f OMAP3430_L4_IP_END 0x48040FFF
f OMAP3430_L4_LA_BASE 0x48041000
f OMAP3430_L4_LA_END 0x48041FFF
f OMAP3430_MLB_BASE 0x48094000
f OMAP3430_MLB_END 0x48094FFF
f OMAP3430_MMU_CAM_BASE 0x480BD400
f OMAP3430_MMU_CAM_END 0x480BD4FF
f OMAP3430_MMU_IVA2_BASE 0x5D00000
f OMAP3430_MMU_IVA2_END 0x5D000FF
f OMAP3430_SDMA_BASE 0x48056000
f OMAP3430_SDMA_END 0x48056FFF
f OMAP3430_MPU_INTC_BASE 0x48200000
f OMAP3430_MPU_INTC_END 0x48200FFF
f OMAP3430_MODEM_INTC_BASE 0x480C7000
f OMAP3430_MODEM_INTC_END 0x480C7FFF
f OMAP3430_GPMC_BASE 0x6E000000
f OMAP3430_GPMC_END 0x6EFFFFFF
f OMAP3430_SMS_BASE 0x6C000000
f OMAP3430_SMS_END 0x6C00FFFF
f OMAP3430_SDRC_BASE 0x6D000000
f OMAP3430_SDRC_END 0x6D00FFFF
f OMAP3430_OCM_ROM_START 0x40014000
f OMAP3430_OCM_ROM_END 0x4001BFFF
f OMAP3430_OCM_RAM_START 0x40200000
f OMAP3430_OCM_RAM_END 0x4020FFFF
f OMAP3430_SGX_BASE 0x50000000
f OMAP3430_SGX_BASE 0x5000FFFF
f OMAP3430_DSS_BASE 0x4804FC00
f OMAP3430_DSS_END 0x48050CFF
f OMAP3430_32kHz_TIMER_BASE 0x48320000
f OMAP3430_32kHz_TIMER_END 0x48320FFF
f OMAP3430_WDTIMER2_BASE 0x48314000
f OMAP3430_WDTIMER2_END 0x48314FFF
f OMAP3430_WDTIMER3_BASE 0x49030000
f OMAP3430_WDTIMER3_END 0x49030FFF
f OMAP3430_GPTIMER1_BASE 0x48318000
f OMAP3430_GPTIMER1_END 0x48318FFF
f OMAP3430_GPTIMER2_BASE 0x49032000
f OMAP3430_GPTIMER2_END 0x49032FFF
f OMAP3430_GPTIMER3_BASE 0x49034000
f OMAP3430_GPTIMER3_END 0x49034FFF
f OMAP3430_GPTIMER4_BASE 0x49036000
f OMAP3430_GPTIMER4_END 0x49036FFF
f OMAP3430_GPTIMER5_BASE 0x49038000
f OMAP3430_GPTIMER5_END 0x49038FFF
f OMAP3430_GPTIMER6_BASE 0x4903A000
f OMAP3430_GPTIMER6_END 0x4903AFFF
f OMAP3430_GPTIMER7_BASE 0x4903C000
f OMAP3430_GPTIMER7_END 0x4903CFFF
f OMAP3430_GPTIMER8_BASE 0x4903E000
f OMAP3430_GPTIMER8_END 0x4903EFFF
f OMAP3430_GPTIMER9_BASE 0x49040000
f OMAP3430_GPTIMER9_END 0x49040FFF
f OMAP3430_GPTIMER10_BASE 0x48086000
f OMAP3430_GPTIMER10_END 0x48086FFF
f OMAP3430_GPTIMER11_BASE 0x48088000
f OMAP3430_GPTIMER11_END 0x48088FFF
f OMAP3430_UART1_BASE 0x4806A000
f OMAP3430_UART1_END 0x4806A3FC
f OMAP3430_UART2_BASE 0x4806C000
f OMAP3430_UART2_END 0x4806C3FC
f OMAP3430_UART3_BASE 0x49020000
f OMAP3430_UART3_END 0x490203FC
f OMAP3430_I2C1_BASE 0x48070000
f OMAP3430_I2C1_END 0x48070078
f OMAP3430_I2C2_BASE 0x48072000
f OMAP3430_I2C2_END 0x48072078
f OMAP3430_I2C3_BASE 0x48060000
f OMAP3430_I2C3_END 0x48060078
f OMAP3430_MCSPI1_BASE 0x48098000
f OMAP3430_MCSPI1_END 0x48098FFF
f OMAP3430_MCSPI2_BASE 0x4809A000
f OMAP3430_MCSPI2_END 0x4809AFFF
f OMAP3430_MCSPI3_BASE 0x480B8000
f OMAP3430_MCSPI3_END 0x480B8FFF
f OMAP3430_MCSPI4_BASE 0x480BA000
f OMAP3430_MCSPI4_END 0x480BAFFF
f OMAP3430_HDQ_BASE 0x480B2000
f OMAP3430_HDQ_END 0x480B2FFF
f OMAP3430_MCBSP1_BASE 0x48074000
f OMAP3430_MCBSP1_END 0x48074FFF
f OMAP3430_MCBSP5_BASE 0x48096000
f OMAP3430_MCBSP5_END 0x48096FFF
f OMAP3430_MCBSP2_BASE 0x49022000
f OMAP3430_MCBSP2_END 0x49022FFF
f OMAP3430_MCBSP3_BASE 0x49024000
f OMAP3430_MCBSP3_END 0x49024FFF
f OMAP3430_MCBSP4_BASE 0x49026000
f OMAP3430_MCBSP4_END 0x49026FFF
f OMAP3430_SLIDETONE_MCBSP2_BASE 0x49028000
f OMAP3430_SLIDETONE_MCBSP2_END 0x49028FFF
f OMAP3430_SLIDETONE_MCBSP3_BASE 0x4902A000
f OMAP3430_SLIDETONE_MCBSP_END 0x4902AFFF
f OMAP3430_GPIO1_BASE 0x48310000
f OMAP3430_GPIO1_END 0x48310FFF
f OMAP3430_GPIO2_BASE 0x49050000
f OMAP3430_GPIO2_END 0x49050FFF
f OMAP3430_GPIO3_BASE 0x49052000
f OMAP3430_GPIO3_END 0x49052FFF
f OMAP3430_GPIO4_BASE 0x49054000
f OMAP3430_GPIO4_END 0x49054FFF
f OMAP3430_GPIO5_BASE 0x49056000
f OMAP3430_GPIO5_END 0x49056FFF
f OMAP3430_GPIO6_BASE 0x49058000
f OMAP3430_GPIO6_END 0x49058FFF
f OMAP3430_reg_CONTROL_REVISION 4 @OMAP3430_SCM_BASE+0x0 Control module revision
f OMAP3430_reg_CONTROL_SYSCONFIG 4 @OMAP3430_SCM_BASE+0x10 Set various parameters relative to the Idle mode of the Control module
f OMAP3430_reg_CONTROL_PADCONF_SDRC_D0 4 @OMAP3430_SCM_BASE+0x30
f OMAP3430_reg_CONTROL_PADCONF_SDRC_D2 4 @OMAP3430_SCM_BASE+0x34
f OMAP3430_reg_CONTROL_PADCONF_SDRC_D4 4 @OMAP3430_SCM_BASE+0x38
f OMAP3430_reg_CONTROL_PADCONF_SDRC_D6 4 @OMAP3430_SCM_BASE+0x3C
f OMAP3430_reg_CONTROL_PADCONF_SDRC_D8 4 @OMAP3430_SCM_BASE+0x40
f OMAP3430_reg_CONTROL_PADCONF_SDRC_D10 4 @OMAP3430_SCM_BASE+0x44
f OMAP3430_reg_CONTROL_PADCONF_SDRC_D12 4 @OMAP3430_SCM_BASE+0x48
f OMAP3430_reg_CONTROL_PADCONF_SDRC_D14 4 @OMAP3430_SCM_BASE+0x4C
f OMAP3430_reg_CONTROL_PADCONF_SDRC_D16 4 @OMAP3430_SCM_BASE+0x50
f OMAP3430_reg_CONTROL_PADCONF_SDRC_D18 4 @OMAP3430_SCM_BASE+0x54
f OMAP3430_reg_CONTROL_PADCONF_SDRC_D20 4 @OMAP3430_SCM_BASE+0x58
f OMAP3430_reg_CONTROL_PADCONF_SDRC_D22 4 @OMAP3430_SCM_BASE+0x5C
f OMAP3430_reg_CONTROL_PADCONF_SDRC_D24 4 @OMAP3430_SCM_BASE+0x60
f OMAP3430_reg_CONTROL_PADCONF_SDRC_D26 4 @OMAP3430_SCM_BASE+0x64
f OMAP3430_reg_CONTROL_PADCONF_SDRC_D28 4 @OMAP3430_SCM_BASE+0x68
f OMAP3430_reg_CONTROL_PADCONF_SDRC_D30 4 @OMAP3430_SCM_BASE+0x6C
f OMAP3430_reg_CONTROL_PADCONF_SDRC_CLK 4 @OMAP3430_SCM_BASE+0x70
f OMAP3430_reg_CONTROL_PADCONF_SDRC_DQS1 4 @OMAP3430_SCM_BASE+0x74
f OMAP3430_reg_CONTROL_PADCONF_SDRC_DQS3 4 @OMAP3430_SCM_BASE+0x78
f OMAP3430_reg_CONTROL_PADCONF_GPMC_A2 4 @OMAP3430_SCM_BASE+0x7C
f OMAP3430_reg_CONTROL_PADCONF_GPMC_A4 4 @OMAP3430_SCM_BASE+0x80
f OMAP3430_reg_CONTROL_PADCONF_GPMC_A6 4 @OMAP3430_SCM_BASE+0x84
f OMAP3430_reg_CONTROL_PADCONF_GPMC_A8 4 @OMAP3430_SCM_BASE+0x88
f OMAP3430_reg_CONTROL_PADCONF_GPMC_A10 4 @OMAP3430_SCM_BASE+0x8C
f OMAP3430_reg_CONTROL_PADCONF_GPMC_D1 4 @OMAP3430_SCM_BASE+0x90
f OMAP3430_reg_CONTROL_PADCONF_GPMC_D3 4 @OMAP3430_SCM_BASE+0x94
f OMAP3430_reg_CONTROL_PADCONF_GPMC_D5 4 @OMAP3430_SCM_BASE+0x98
f OMAP3430_reg_CONTROL_PADCONF_GPMC_D7 4 @OMAP3430_SCM_BASE+0x9C
f OMAP3430_reg_CONTROL_PADCONF_GPMC_D9 4 @OMAP3430_SCM_BASE+0xA0
f OMAP3430_reg_CONTROL_PADCONF_GPMC_D11 4 @OMAP3430_SCM_BASE+0xA4
f OMAP3430_reg_CONTROL_PADCONF_GPMC_D13 4 @OMAP3430_SCM_BASE+0xA8
f OMAP3430_reg_CONTROL_PADCONF_GPMC_D15 4 @OMAP3430_SCM_BASE+0xAC
f OMAP3430_reg_CONTROL_PADCONF_GPMC_NCS1 4 @OMAP3430_SCM_BASE+0xB0
f OMAP3430_reg_CONTROL_PADCONF_GPMC_NCS3 4 @OMAP3430_SCM_BASE+0xB4
f OMAP3430_reg_CONTROL_PADCONF_GPMC_NCS5 4 @OMAP3430_SCM_BASE+0xB8
f OMAP3430_reg_CONTROL_PADCONF_GPMC_NCS7 4 @OMAP3430_SCM_BASE+0xBC
f OMAP3430_reg_CONTROL_PADCONF_GPMC_NADV_ALE 4 @OMAP3430_SCM_BASE+0xC0
f OMAP3430_reg_CONTROL_PADCONF_GPMC_NWE 4 @OMAP3430_SCM_BASE+0xC4
f OMAP3430_reg_CONTROL_PADCONF_GPMC_NBE1 4 @OMAP3430_SCM_BASE+0xC8
f OMAP3430_reg_CONTROL_PADCONF_GPMC_WAIT0 4 @OMAP3430_SCM_BASE+0xCC
f OMAP3430_reg_CONTROL_PADCONF_GPMC_WAIT2 4 @OMAP3430_SCM_BASE+0xD0
f OMAP3430_reg_CONTROL_PADCONF_DSS_PCLK 4 @OMAP3430_SCM_BASE+0xD4
f OMAP3430_reg_CONTROL_PADCONF_DSS_VSYNC 4 @OMAP3430_SCM_BASE+0xD8
f OMAP3430_reg_CONTROL_PADCONF_DSS_DATA0 4 @OMAP3430_SCM_BASE+0xDC
f OMAP3430_reg_CONTROL_PADCONF_DSS_DATA2 4 @OMAP3430_SCM_BASE+0xE0
f OMAP3430_reg_CONTROL_PADCONF_DSS_DATA4 4 @OMAP3430_SCM_BASE+0xE4
f OMAP3430_reg_CONTROL_PADCONF_DSS_DATA6 4 @OMAP3430_SCM_BASE+0xE8
f OMAP3430_reg_CONTROL_PADCONF_DSS_DATA8 4 @OMAP3430_SCM_BASE+0xEC
f OMAP3430_reg_CONTROL_PADCONF_DSS_DATA10 4 @OMAP3430_SCM_BASE+0xF0
f OMAP3430_reg_CONTROL_PADCONF_DSS_DATA12 4 @OMAP3430_SCM_BASE+0xF4
f OMAP3430_reg_CONTROL_PADCONF_DSS_DATA14 4 @OMAP3430_SCM_BASE+0xF8
f OMAP3430_reg_CONTROL_PADCONF_DSS_DATA16 4 @OMAP3430_SCM_BASE+0xFC
f OMAP3430_reg_CONTROL_PADCONF_DSS_DATA18 4 @OMAP3430_SCM_BASE+0x100
f OMAP3430_reg_CONTROL_PADCONF_DSS_DATA20 4 @OMAP3430_SCM_BASE+0x104
f OMAP3430_reg_CONTROL_PADCONF_DSS_DATA22 4 @OMAP3430_SCM_BASE+0x108
f OMAP3430_reg_CONTROL_PADCONF_CAM_HS 4 @OMAP3430_SCM_BASE+0x10C
f OMAP3430_reg_CONTROL_PADCONF_CAM_XCLKA 4 @OMAP3430_SCM_BASE+0x110
f OMAP3430_reg_CONTROL_PADCONF_CAM_FLD 4 @OMAP3430_SCM_BASE+0x114
f OMAP3430_reg_CONTROL_PADCONF_CAM_D1 4 @OMAP3430_SCM_BASE+0x118
f OMAP3430_reg_CONTROL_PADCONF_CAM_D3 4 @OMAP3430_SCM_BASE+0x11C
f OMAP3430_reg_CONTROL_PADCONF_CAM_D5 4 @OMAP3430_SCM_BASE+0x120
f OMAP3430_reg_CONTROL_PADCONF_CAM_D7 4 @OMAP3430_SCM_BASE+0x124
f OMAP3430_reg_CONTROL_PADCONF_CAM_D9 4 @OMAP3430_SCM_BASE+0x128
f OMAP3430_reg_CONTROL_PADCONF_CAM_D11 4 @OMAP3430_SCM_BASE+0x12C
f OMAP3430_reg_CONTROL_PADCONF_CAM_WEN 4 @OMAP3430_SCM_BASE+0x130
f OMAP3430_reg_CONTROL_PADCONF_CSI2_DX0 4 @OMAP3430_SCM_BASE+0x134
f OMAP3430_reg_CONTROL_PADCONF_CSI2_DX1 4 @OMAP3430_SCM_BASE+0x138
f OMAP3430_reg_CONTROL_PADCONF_MCBSP2_FSX 4 @OMAP3430_SCM_BASE+0x13C
f OMAP3430_reg_CONTROL_PADCONF_MCBSP2_DR 4 @OMAP3430_SCM_BASE+0x140
f OMAP3430_reg_CONTROL_PADCONF_MMC1_CLK 4 @OMAP3430_SCM_BASE+0x144
f OMAP3430_reg_CONTROL_PADCONF_MMC1_DAT0 4 @OMAP3430_SCM_BASE+0x148
f OMAP3430_reg_CONTROL_PADCONF_MMC1_DAT2 4 @OMAP3430_SCM_BASE+0x14C
f OMAP3430_reg_CONTROL_PADCONF_MMC1_DAT4 4 @OMAP3430_SCM_BASE+0x150
f OMAP3430_reg_CONTROL_PADCONF_MMC1_DAT6 4 @OMAP3430_SCM_BASE+0x154
f OMAP3430_reg_CONTROL_PADCONF_MMC2_CLK 4 @OMAP3430_SCM_BASE+0x158
f OMAP3430_reg_CONTROL_PADCONF_MMC2_DAT0 4 @OMAP3430_SCM_BASE+0x15C
f OMAP3430_reg_CONTROL_PADCONF_MMC2_DAT2 4 @OMAP3430_SCM_BASE+0x160
f OMAP3430_reg_CONTROL_PADCONF_MMC2_DAT4 4 @OMAP3430_SCM_BASE+0x164
f OMAP3430_reg_CONTROL_PADCONF_MMC2_DAT6 4 @OMAP3430_SCM_BASE+0x168
f OMAP3430_reg_CONTROL_PADCONF_MCBSP3_DX 4 @OMAP3430_SCM_BASE+0x16C
f OMAP3430_reg_CONTROL_PADCONF_MCBSP3_CLKX 4 @OMAP3430_SCM_BASE+0x170
f OMAP3430_reg_CONTROL_PADCONF_UART2_CTS 4 @OMAP3430_SCM_BASE+0x174
f OMAP3430_reg_CONTROL_PADCONF_UART2_TX 4 @OMAP3430_SCM_BASE+0x178
f OMAP3430_reg_CONTROL_PADCONF_UART1_TX 4 @OMAP3430_SCM_BASE+0x17C
f OMAP3430_reg_CONTROL_PADCONF_UART1_CTS 4 @OMAP3430_SCM_BASE+0x180
f OMAP3430_reg_CONTROL_PADCONF_MCBSP4_CLKX 4 @OMAP3430_SCM_BASE+0x184
f OMAP3430_reg_CONTROL_PADCONF_MCBSP4_DX 4 @OMAP3430_SCM_BASE+0x188
f OMAP3430_reg_CONTROL_PADCONF_MCBSP1_CLKR 4 @OMAP3430_SCM_BASE+0x18C
f OMAP3430_reg_CONTROL_PADCONF_MCBSP1_DX 4 @OMAP3430_SCM_BASE+0x190
f OMAP3430_reg_CONTROL_PADCONF_MCBSP_CLKS 4 @OMAP3430_SCM_BASE+0x194
f OMAP3430_reg_CONTROL_PADCONF_MCBSP1_CLKX 4 @OMAP3430_SCM_BASE+0x198
f OMAP3430_reg_CONTROL_PADCONF_UART3_RTS_SD 4 @OMAP3430_SCM_BASE+0x19C
f OMAP3430_reg_CONTROL_PADCONF_UART3_TX_IRTX 4 @OMAP3430_SCM_BASE+0x1A0
f OMAP3430_reg_CONTROL_PADCONF_HSUSB0_STP 4 @OMAP3430_SCM_BASE+0x1A4
f OMAP3430_reg_CONTROL_PADCONF_HSUSB0_NXT 4 @OMAP3430_SCM_BASE+0x1A8
f OMAP3430_reg_CONTROL_PADCONF_HSUSB0_DATA1 4 @OMAP3430_SCM_BASE+0x1AC
f OMAP3430_reg_CONTROL_PADCONF_HSUSB0_DATA3 4 @OMAP3430_SCM_BASE+0x1B0
f OMAP3430_reg_CONTROL_PADCONF_HSUSB0_DATA5 4 @OMAP3430_SCM_BASE+0x1B4
f OMAP3430_reg_CONTROL_PADCONF_HSUSB0_DATA7 4 @OMAP3430_SCM_BASE+0x1B8
f OMAP3430_reg_CONTROL_PADCONF_I2C1_SDA 4 @OMAP3430_SCM_BASE+0x1BC
f OMAP3430_reg_CONTROL_PADCONF_I2C2_SDA 4 @OMAP3430_SCM_BASE+0x1C0
f OMAP3430_reg_CONTROL_PADCONF_I2C3_SDA 4 @OMAP3430_SCM_BASE+0x1C4
f OMAP3430_reg_CONTROL_PADCONF_MCSPI1_CLK 4 @OMAP3430_SCM_BASE+0x1C8
f OMAP3430_reg_CONTROL_PADCONF_MCSPI1_SOMI 4 @OMAP3430_SCM_BASE+0x1CC
f OMAP3430_reg_CONTROL_PADCONF_MCSPI1_CS1 4 @OMAP3430_SCM_BASE+0x1D0
f OMAP3430_reg_CONTROL_PADCONF_MCSPI1_CS3 4 @OMAP3430_SCM_BASE+0x1D4
f OMAP3430_reg_CONTROL_PADCONF_MCSPI2_SIMO 4 @OMAP3430_SCM_BASE+0x1D8
f OMAP3430_reg_CONTROL_PADCONF_MCSPI2_CS0 4 @OMAP3430_SCM_BASE+0x1DC
f OMAP3430_reg_CONTROL_PADCONF_SYS_NIRQ 4 @OMAP3430_SCM_BASE+0x1E0
f OMAP3430_reg_CONTROL_PADCONF_SAD2D_MCAD0 4 @OMAP3430_SCM_BASE+0x1E4
f OMAP3430_reg_CONTROL_PADCONF_SAD2D_MCAD2 4 @OMAP3430_SCM_BASE+0x1E8
f OMAP3430_reg_CONTROL_PADCONF_SAD2D_MCAD4 4 @OMAP3430_SCM_BASE+0x1EC
f OMAP3430_reg_CONTROL_PADCONF_SAD2D_MCAD6 4 @OMAP3430_SCM_BASE+0x1F0
f OMAP3430_reg_CONTROL_PADCONF_SAD2D_MCAD8 4 @OMAP3430_SCM_BASE+0x1F4
f OMAP3430_reg_CONTROL_PADCONF_SAD2D_MCAD10 4 @OMAP3430_SCM_BASE+0x1F8
f OMAP3430_reg_CONTROL_PADCONF_SAD2D_MCAD12 4 @OMAP3430_SCM_BASE+0x1FC
f OMAP3430_reg_CONTROL_PADCONF_SAD2D_MCAD14 4 @OMAP3430_SCM_BASE+0x200
f OMAP3430_reg_CONTROL_PADCONF_SAD2D_MCAD16 4 @OMAP3430_SCM_BASE+0x204
f OMAP3430_reg_CONTROL_PADCONF_SAD2D_MCAD18 4 @OMAP3430_SCM_BASE+0x208
f OMAP3430_reg_CONTROL_PADCONF_SAD2D_MCAD20 4 @OMAP3430_SCM_BASE+0x20C
f OMAP3430_reg_CONTROL_PADCONF_SAD2D_MCAD22 4 @OMAP3430_SCM_BASE+0x210
f OMAP3430_reg_CONTROL_PADCONF_SAD2D_MCAD24 4 @OMAP3430_SCM_BASE+0x214
f OMAP3430_reg_CONTROL_PADCONF_SAD2D_MCAD26 4 @OMAP3430_SCM_BASE+0x218
f OMAP3430_reg_CONTROL_PADCONF_SAD2D_MCAD28 4 @OMAP3430_SCM_BASE+0x21C
f OMAP3430_reg_CONTROL_PADCONF_SAD2D_MCAD30 4 @OMAP3430_SCM_BASE+0x220
f OMAP3430_reg_CONTROL_PADCONF_SAD2D_MCAD32 4 @OMAP3430_SCM_BASE+0x224
f OMAP3430_reg_CONTROL_PADCONF_SAD2D_MCAD34 4 @OMAP3430_SCM_BASE+0x228
f OMAP3430_reg_CONTROL_PADCONF_SAD2D_MCAD36 4 @OMAP3430_SCM_BASE+0x22C
f OMAP3430_reg_CONTROL_PADCONF_SAD2D_NRESPWRON 4 @OMAP3430_SCM_BASE+0x230
f OMAP3430_reg_CONTROL_PADCONF_SAD2D_ARMNIRQ 4 @OMAP3430_SCM_BASE+0x234
f OMAP3430_reg_CONTROL_PADCONF_SAD2D_SPINT 4 @OMAP3430_SCM_BASE+0x238
f OMAP3430_reg_CONTROL_PADCONF_SAD2D_DMAREQ0 4 @OMAP3430_SCM_BASE+0x23C
f OMAP3430_reg_CONTROL_PADCONF_SAD2D_DMAREQ2 4 @OMAP3430_SCM_BASE+0x240
f OMAP3430_reg_CONTROL_PADCONF_SAD2D_NTRST 4 @OMAP3430_SCM_BASE+0x244
f OMAP3430_reg_CONTROL_PADCONF_SAD2D_TDO 4 @OMAP3430_SCM_BASE+0x248
f OMAP3430_reg_CONTROL_PADCONF_SAD2D_TCK 4 @OMAP3430_SCM_BASE+0x24C
f OMAP3430_reg_CONTROL_PADCONF_SAD2D_MSTDBY 4 @OMAP3430_SCM_BASE+0x250
f OMAP3430_reg_CONTROL_PADCONF_SAD2D_IDLEACK 4 @OMAP3430_SCM_BASE+0x254
f OMAP3430_reg_CONTROL_PADCONF_SAD2D_SWRITE 4 @OMAP3430_SCM_BASE+0x258
f OMAP3430_reg_CONTROL_PADCONF_SAD2D_SREAD 4 @OMAP3430_SCM_BASE+0x25C
f OMAP3430_reg_CONTROL_PADCONF_SAD2D_SBUSFLAG 4 @OMAP3430_SCM_BASE+0x260
f OMAP3430_reg_CONTROL_PADCONF_SDRC_CKE1 4 @OMAP3430_SCM_BASE+0x264
f OMAP3430_reg_CONTROL_PADCONF_ETK_CLK 4 @OMAP3430_SCM_BASE+0x5D8
f OMAP3430_reg_CONTROL_PADCONF_ETK_D0 4 @OMAP3430_SCM_BASE+0x5DC
f OMAP3430_reg_CONTROL_PADCONF_ETK_D2 4 @OMAP3430_SCM_BASE+0x5E0
f OMAP3430_reg_CONTROL_PADCONF_ETK_D4 4 @OMAP3430_SCM_BASE+0x5E4
f OMAP3430_reg_CONTROL_PADCONF_ETK_D6 4 @OMAP3430_SCM_BASE+0x5E8
f OMAP3430_reg_CONTROL_PADCONF_ETK_D8 4 @OMAP3430_SCM_BASE+0x5EC
f OMAP3430_reg_CONTROL_PADCONF_ETK_D10 4 @OMAP3430_SCM_BASE+0x5F0
f OMAP3430_reg_CONTROL_PADCONF_ETK_D12 4 @OMAP3430_SCM_BASE+0x5F4
f OMAP3430_reg_CONTROL_PADCONF_ETK_D14 4 @OMAP3430_SCM_BASE+0x5F8
f OMAP3430_reg_CONTROL_PADCONF_OFF 4 @OMAP3430_SCM_BASE+0x270 Off mode pad configuration register
f OMAP3430_reg_CONTROL_DEVCONF0 4 @OMAP3430_SCM_BASE+0x274 Static device configuration register-0. Module dedicated functions
f OMAP3430_reg_CONTROL_RESERVED_0 4 @OMAP3430_SCM_BASE+0x278
f OMAP3430_reg_CONTROL_RESERVED_1 4 @OMAP3430_SCM_BASE+0x27C
f OMAP3430_reg_CONTROL_MSUSPENDMUX_0 4 @OMAP3430_SCM_BASE+0x290 MSuspend Control register: control the use of MSuspend signals at module level
f OMAP3430_reg_CONTROL_MSUSPENDMUX_1 4 @OMAP3430_SCM_BASE+0x294 MSuspend Control register: control the use of MSuspend signals at module level
f OMAP3430_reg_CONTROL_MSUSPENDMUX_2 4 @OMAP3430_SCM_BASE+0x298
f OMAP3430_reg_CONTROL_MSUSPENDMUX_3 4 @OMAP3430_SCM_BASE+0x29C
f OMAP3430_reg_CONTROL_MSUSPENDMUX_4 4 @OMAP3430_SCM_BASE+0x2A0
f OMAP3430_reg_CONTROL_MSUSPENDMUX_5 4 @OMAP3430_SCM_BASE+0x2A4
f OMAP3430_reg_CONTROL_PROT_CTRL 4 @OMAP3430_SCM_BASE+0x2B0
f OMAP3430_reg_CONTROL_DEVCONF1 4 @OMAP3430_SCM_BASE+0x2D8 Static device configuration register-1, Module dedicated functions
f OMAP3430_reg_CONTROL_CSIRXFE 4 @OMAP3430_SCM_BASE+0x2DC This register makes possible to control some settings of CSIRXFE cells used in the design
f OMAP3430_reg_CONTROL_PROT_ERR_STATUS 4 @OMAP3430_SCM_BASE+0x2E4 Protection Error Status Register
f OMAP3430_reg_CONTROL_PROT_ERR_STATUS_DEBUG 4 @OMAP3430_SCM_BASE+0x2E8 Protection Error Status Debug Register
f OMAP3430_reg_CONTROL_STATUS 4 @OMAP3430_SCM_BASE+0x2F0 Control Module Status register: latches system information at reset time
f OMAP3430_reg_CONTROL_GENERAL_PURPOSE_STATUS 4 @OMAP3430_SCM_BASE+0x2F4
f OMAP3430_reg_CONTROL_RPUB_KEY_H_0 4 @OMAP3430_SCM_BASE+0x300 Root public key hash: B-field
f OMAP3430_reg_CONTROL_RPUB_KEY_H_1 4 @OMAP3430_SCM_BASE+0x304 Root public key hash: B-field
f OMAP3430_reg_CONTROL_RPUB_KEY_H_2 4 @OMAP3430_SCM_BASE+0x308 Root public key hash: B-field
f OMAP3430_reg_CONTROL_RPUB_KEY_H_3 4 @OMAP3430_SCM_BASE+0x30C Root public key hash: B-field
f OMAP3430_reg_CONTROL_RPUB_KEY_H_4 4 @OMAP3430_SCM_BASE+0x310 Root public key hash: B-field
f OMAP3430_reg_CONTROL_USB_CONF_0 4 @OMAP3430_SCM_BASE+0x370 USB Fuse conf [31:0], USB Product ID [31:16], Vendor ID [15:0]
f OMAP3430_reg_CONTROL_USB_CONF_1 4 @OMAP3430_SCM_BASE+0x374 USB Fuse conf 1, SEQ_DISADAPTCLK[1], USB PHY detection mode [0]
f OMAP3430_reg_CONTROL_FUSE_OPP1_VDD1 4 @OMAP3430_SCM_BASE+0x380 Standard Fuse OPP1 VDD1
f OMAP3430_reg_CONTROL_FUSE_OPP2_VDD1 4 @OMAP3430_SCM_BASE+0x384 Standard Fuse OPP2 VDD1
f OMAP3430_reg_CONTROL_FUSE_OPP3_VDD1 4 @OMAP3430_SCM_BASE+0x388 Standard Fuse OPP3 VDD1
f OMAP3430_reg_CONTROL_FUSE_OPP4_VDD1 4 @OMAP3430_SCM_BASE+0x38C Standard Fuse OPP4 VDD1
f OMAP3430_reg_CONTROL_FUSE_OPP5_VDD1 4 @OMAP3430_SCM_BASE+0x390 Standard Fuse OPP5 VDD1
f OMAP3430_reg_CONTROL_FUSE_OPP1_VDD2 4 @OMAP3430_SCM_BASE+0x394 Standard Fuse OPP1 VDD2
f OMAP3430_reg_CONTROL_FUSE_OPP2_VDD2 4 @OMAP3430_SCM_BASE+0x398 Standard Fuse OPP2 VDD2
f OMAP3430_reg_CONTROL_FUSE_OPP3_VDD2 4 @OMAP3430_SCM_BASE+0x39C Standard Fuse OPP3 VDD2
f OMAP3430_reg_CONTROL_RESERVED_3 4 @OMAP3430_SCM_BASE+0x3A0
f OMAP3430_reg_CONTROL_IVA2_BOOTADDR 4 @OMAP3430_SCM_BASE+0x400 This register defines the physical address of the IVA2 boot loader
f OMAP3430_reg_CONTROL_IVA2_BOOTMOD 4 @OMAP3430_SCM_BASE+0x404 This register defines the IVA2 bootmode
f OMAP3430_reg_CONTROL_DEBOBS_0 4 @OMAP3430_SCM_BASE+0x420 Select the set of signals to be observed for hw_dbg0, hw_dbg1
f OMAP3430_reg_CONTROL_DEBOBS_1 4 @OMAP3430_SCM_BASE+0x424 Select the set of signals to be observed for hw_dbg2, hw_dbg3
f OMAP3430_reg_CONTROL_DEBOBS_2 4 @OMAP3430_SCM_BASE+0x428 Select the set of signals to be observed for hw_dbg4, hw_dbg5
f OMAP3430_reg_CONTROL_DEBOBS_3 4 @OMAP3430_SCM_BASE+0x42C Select the set of signals to be observed for hw_dbg6, hw_dbg7
f OMAP3430_reg_CONTROL_DEBOBS_4 4 @OMAP3430_SCM_BASE+0x430 Select the set of signals to be observed for hw_dbg8, hw_dbg9
f OMAP3430_reg_CONTROL_DEBOBS_5 4 @OMAP3430_SCM_BASE+0x434 Select the set of signals to be observed for hw_dbg10, hw_dbg11
f OMAP3430_reg_CONTROL_DEBOBS_6 4 @OMAP3430_SCM_BASE+0x438 Select the set of signals to be observed for hw_dbg12, hw_dbg13
f OMAP3430_reg_CONTROL_DEBOBS_7 4 @OMAP3430_SCM_BASE+0x43C Select the set of signals to be observed for hw_dbg14, hw_dbg15
f OMAP3430_reg_CONTROL_DEBOBS_8 4 @OMAP3430_SCM_BASE+0x440 Select the set of signals to be observed for hw_dbg16, hw_dbg17
f OMAP3430_reg_CONTROL_PROG_IO0 4 @OMAP3430_SCM_BASE+0x444 Configure drive strength of I/O cells
f OMAP3430_reg_CONTROL_PROG_IO1 4 @OMAP3430_SCM_BASE+0x448 Configure drive strength of I/O cells
f OMAP3430_reg_CONTROL_DSS_DPLL_SPREADING 4 @OMAP3430_SCM_BASE+0x450 This register controls the EMI Reduction feature for Display_SS/DSI DPLL
f OMAP3430_reg_CONTROL_CORE_DPLL_SPREADING 4 @OMAP3430_SCM_BASE+0x454 This register controls the EMI Reduction feature for CORE domain DPLL
f OMAP3430_reg_CONTROL_PER_DPLL_SPREADING 4 @OMAP3430_SCM_BASE+0x458 This register controls the EMI Reduction feature for PER domain DPLL
f OMAP3430_reg_CONTROL_USBHOST_DPLL_SPREADING 4 @OMAP3430_SCM_BASE+0x45C This register controls the EMI Reduction feature for USBHOST domain DPLL
f OMAP3430_reg_CONTROL_SDRC_SHARING 4 @OMAP3430_SCM_BASE+0x460 SDRC Sharing configuration register
f OMAP3430_reg_CONTROL_SDRC_MCFG0 4 @OMAP3430_SCM_BASE+0x464 SDRC MCFG Configuration register-0
f OMAP3430_reg_CONTROL_SDRC_MCFG1 4 @OMAP3430_SCM_BASE+0x468 SDRC MCFG Configuration register-1
f OMAP3430_reg_CONTROL_MODEM_FW_CONFIGURATION_LOCK 4 @OMAP3430_SCM_BASE+0x46C Allows locking of the modem isolation registers in the SCM until the next battery removal
f OMAP3430_reg_CONTROL_MODEM_MEMORY_RESOURCES_CONF 4 @OMAP3430_SCM_BASE+0x470 Modem Memory Resources configuration
f OMAP3430_reg_CONTROL_MODEM_GPMC_DT_FW_REQ_INFO 4 @OMAP3430_SCM_BASE+0x474 Modem GPMC Default firewall request info register
f OMAP3430_reg_CONTROL_MODEM_GPMC_DT_FW_RD 4 @OMAP3430_SCM_BASE+0x478 Modem GPMC Default firewall read permission register
f OMAP3430_reg_CONTROL_MODEM_GPMC_DT_FW_WR 4 @OMAP3430_SCM_BASE+0x47C Modem GPMC Default firewall write permission register
f OMAP3430_reg_CONTROL_MODEM_GPMC_BOOT_CODE 4 @OMAP3430_SCM_BASE+0x480 GPMC Flash Boot Code protection register
f OMAP3430_reg_CONTROL_MODEM_SMS_RG_ATT1 4 @OMAP3430_SCM_BASE+0x484 Modem SMS Default firewall register
f OMAP3430_reg_CONTROL_MODEM_SMS_RG_RDPERM1 4 @OMAP3430_SCM_BASE+0x488 Modem SMS Default firewall read permission register
f OMAP3430_reg_CONTROL_MODEM_SMS_RG_WRPERM1 4 @OMAP3430_SCM_BASE+0x48C Modem SMS Default firewall write permission register
f OMAP3430_reg_CONTROL_MODEM_D2D_FW_DEBUG_MODE 4 @OMAP3430_SCM_BASE+0x490 D2D firewall debug mode register
f OMAP3430_reg_CONTROL_DPF_OCM_RAM_FW_ADDR_MATCH 4 @OMAP3430_SCM_BASE+0x498 OCM RAM Dynamic Power Framework Handling
f OMAP3430_reg_CONTROL_DPF_OCM_RAM_FW_REQINFO 4 @OMAP3430_SCM_BASE+0x49C OCM RAM Dynamic Power Framework Handling
f OMAP3430_reg_CONTROL_DPF_OCM_RAM_FW_WR 4 @OMAP3430_SCM_BASE+0x4A0 OCM RAM Dynamic Power Framework Handling
f OMAP3430_reg_CONTROL_DPF_REGION4_GPMC_FW_ADDR_MATCH 4 @OMAP3430_SCM_BASE+0x4A4 GPMC Dynamic Power Framework Handling
f OMAP3430_reg_CONTROL_DPF_REGION4_GPMC_FW_REQINFO 4 @OMAP3430_SCM_BASE+0x4A8 GPMC Dynamic Power Framework Handling
f OMAP3430_reg_CONTROL_DPF_REGION4_GPMC_FW_WR 4 @OMAP3430_SCM_BASE+0x4AC GPMC Dynamic Power Framework Handling
f OMAP3430_reg_CONTROL_DPF_REGION1_IVA2_FW_ADDR_MATCH 4 @OMAP3430_SCM_BASE+0x4B0 IVA2 Dynamic Power Framework Handling
f OMAP3430_reg_CONTROL_DPF_REGION1_IVA2_FW_REQINFO 4 @OMAP3430_SCM_BASE+0x4B4 IVA2 Dynamic Power Framework Handling
f OMAP3430_reg_CONTROL_DPF_REGION1_IVA2_FW_WR 4 @OMAP3430_SCM_BASE+0x4B8 IVA2 Dynamic Power Framework Handling
f OMAP3430_reg_CONTROL_DPF_MAD2D_FW_ADDR_MATCH 4 @OMAP3430_SCM_BASE+0x538 MAD2D Dynamic Power Framework Handling
f OMAP3430_reg_CONTROL_DPF_MAD2D_FW_REQINFO 4 @OMAP3430_SCM_BASE+0x53C MAD2D Dynamic Power Framework Handling
f OMAP3430_reg_CONTROL_DPF_MAD2D_FW_WR 4 @OMAP3430_SCM_BASE+0x540 MAD2D Dynamic Power Framework Handling
f OMAP3430_reg_CONTROL_PBIAS_LITE 4 @OMAP3430_SCM_BASE+0x520 This register controls the settings for PBIAS LITE MMC/SD/SDIO1 pins
f OMAP3430_reg_CONTROL_TEMP_SENSOR 4 @OMAP3430_SCM_BASE+0x524 Temperature Sensor register
f OMAP3430_reg_CONTROL_CSI 4 @OMAP3430_SCM_BASE+0x530 Controls CSIb receiver trimming setting
f OMAP3430_reg_CONTROL_SAVE_RESTORE_MEM 4 @OMAP3430_SCM_BASE+0x9FC
f OMAP3430_reg_CONTROL_PADCONF_I2C4_SCL 4 @OMAP3430_SCM_BASE+0xA00
f OMAP3430_reg_CONTROL_PADCONF_SYS_32K 4 @OMAP3430_SCM_BASE+0xA04
f OMAP3430_reg_CONTROL_PADCONF_SYS_NRESWARM 4 @OMAP3430_SCM_BASE+0xA08
f OMAP3430_reg_CONTROL_PADCONF_SYS_BOOT1 4 @OMAP3430_SCM_BASE+0xA0C
f OMAP3430_reg_CONTROL_PADCONF_SYS_BOOT3 4 @OMAP3430_SCM_BASE+0xA10
f OMAP3430_reg_CONTROL_PADCONF_SYS_BOOT5 4 @OMAP3430_SCM_BASE+0xA14
f OMAP3430_reg_CONTROL_PADCONF_SYS_OFF_MODE 4 @OMAP3430_SCM_BASE+0xA18
f OMAP3430_reg_CONTROL_PADCONF_JTAG_NTRST 4 @OMAP3430_SCM_BASE+0xA1C
f OMAP3430_reg_CONTROL_PADCONF_JTAG_TMS_TMSC 4 @OMAP3430_SCM_BASE+0xA20
f OMAP3430_reg_CONTROL_PADCONF_JTAG_EMU0 4 @OMAP3430_SCM_BASE+0xA24
f OMAP3430_reg_CONTROL_PADCONF_SAD2D_SWAKEUP 4 @OMAP3430_SCM_BASE+0xA4C
f OMAP3430_reg_CONTROL_PADCONF_JTAG_TDO 4 @OMAP3430_SCM_BASE+0xA50
f OMAP3430_reg_CONTROL_WKUP_CTRL 4 @OMAP3430_SCM_BASE+0xA5C USB TXEN polarity control and log modem warm reset source mux sel
f OMAP3430_reg_CONTROL_WKUP_DEBOBS_0 4 @OMAP3430_SCM_BASE+0xA68 Select the WKUP domain set of signals to be observed for hw_dbg3, hw_dbg2, hw_dbg1, hw_dbg0
f OMAP3430_reg_CONTROL_WKUP_DEBOBS_1 4 @OMAP3430_SCM_BASE+0xA6C Select the WKUP domain set of signals to be observed for hw_dbg7, hw_dbg6, hw_dbg5, hw_dbg4
f OMAP3430_reg_CONTROL_WKUP_DEBOBS_2 4 @OMAP3430_SCM_BASE+0xA70 Select the WKUP domain set of signals to be observed for hw_dbg11, hw_dbg10, hw_dbg9, hw_dbg8
f OMAP3430_reg_CONTROL_WKUP_DEBOBS_3 4 @OMAP3430_SCM_BASE+0xA74 Select the WKUP domain set of signals to be observed for hw_dbg15, hw_dbg14, hw_dbg13, hw_dbg12
f OMAP3430_reg_CONTROL_WKUP_DEBOBS_4 4 @OMAP3430_SCM_BASE+0xA78 Select the WKUP domain set of signals to be observed for hw_dbg17, hw_dbg16
f OMAP3430_reg_CM_FCLKEN_IVA2 4 @OMAP3430_CM_REG_A_BASE+0x0 This register controls the IVA2 domain functional clock activity
f OMAP3430_reg_CM_CLKEN_PLL_IVA2 4 @OMAP3430_CM_REG_A_BASE+0x4 This register controls the IVA2 DPLL modes
f OMAP3430_reg_CM_IDLEST_IVA2 4 @OMAP3430_CM_REG_A_BASE+0x20 IVA2 standby status and access availability monitoring. This register is read only and automatically updated
f OMAP3430_reg_CM_IDLEST_PLL_IVA2 4 @OMAP3430_CM_REG_A_BASE+0x24 This register allows monitoring the master clock activiry. This register is read only and automatically updated
f OMAP3430_reg_CM_AUTOIDLE_PLL_IVA2 4 @OMAP3430_CM_REG_A_BASE+0x34 This register provides automatic control over the IVA2 DPLL activity
f OMAP3430_reg_CM_CLKSEL1_PLL_IVA2 4 @OMAP3430_CM_REG_A_BASE+0x40 This register provides controls over the IVA2 DPLL
f OMAP3430_reg_CM_CLKSEL2_PLL_IVA2 4 @OMAP3430_CM_REG_A_BASE+0x44 This register provides controls over the IVA2 DPLL
f OMAP3430_reg_CM_CLKSTCTRL_IVA2 4 @OMAP3430_CM_REG_A_BASE+0x48 This register enables the domain power state transition. It controls the HW supervised domain power state transition between ACTIVE and INACTIVE states
f OMAP3430_reg_CM_CLKSTST_IVA2 4 @OMAP3430_CM_REG_A_BASE+0x4C This register provides a status on the clock activity in the domain (IVA2 DPLL output clock)
f OMAP3430_reg_CM_REVISION 4 @OMAP3430_CM_REG_A_BASE+0x800 This register contains the IP revision code for the CM part of the PRCM
f OMAP3430_reg_CM_SYSCONFIG 4 @OMAP3430_CM_REG_A_BASE+0x810 This register controls the various parameters of the interface clock
f OMAP3430_reg_CM_CLKEN_PLL_MPU 4 @OMAP3430_CM_REG_A_BASE+0x904 This register controls the DPLL1 modes
f OMAP3430_reg_CM_IDLEST_MPU 4 @OMAP3430_CM_REG_A_BASE+0x920 Modules access availability monitoring. This register is read only and automatically updated
f OMAP3430_reg_CM_IDLEST_PLL_MPU 4 @OMAP3430_CM_REG_A_BASE+0x924 This register allows monitoring the master clock activity. This register is read only and automatically updated
f OMAP3430_reg_CM_AUTOIDLE_PLL_MPU 4 @OMAP3430_CM_REG_A_BASE+0x934 This register provides automatic control over the DPLL1 activity
f OMAP3430_reg_CM_CLKSEL1_PLL_MPU 4 @OMAP3430_CM_REG_A_BASE+0x940 This register provides controls over the MPU DPLL
f OMAP3430_reg_CM_CLKSEL2_PLL_MPU 4 @OMAP3430_CM_REG_A_BASE+0x944 This register provides controls over the MPU DPLL
f OMAP3430_reg_CM_CLKSTCTRL_MPU 4 @OMAP3430_CM_REG_A_BASE+0x948 This register enables the domain power state transition. It controls the HW supervised domain power state transition betweeen ACTIVE and INACTIVE states
f OMAP3430_reg_CM_CLKSTST_MPU 4 @OMAP3430_CM_REG_A_BASE+0x94C This register provides a status on the clock activity in the domain (MPU DPLL output clock)
f OMAP3430_reg_CM_FCLKEN1_CORE 4 @OMAP3430_CM_REG_A_BASE+0xA00 Controls the module functional clock activity
f OMAP3430_reg_CM_FCLKEN3_CORE 4 @OMAP3430_CM_REG_A_BASE+0xA08 Controls the module functional clock activity
f OMAP3430_reg_CM_ICLKEN1_CORE 4 @OMAP3430_CM_REG_A_BASE+0xA10 Controls the modules interface clock activity
f OMAP3430_reg_CM_ICLKEN3_CORE 4 @OMAP3430_CM_REG_A_BASE+0xA18 Controls the modules interface clock activity
f OMAP3430_reg_CM_IDLEST1_CORE 4 @OMAP3430_CM_REG_A_BASE+0xA20 CORE modules access availability monitoring. This register read only and automatically updated
f OMAP3430_reg_CM_IDLEST3_CORE 4 @OMAP3430_CM_REG_A_BASE+0xA28 CORE modules access availability monitoring. This register read only and automatically updated
f OMAP3430_reg_CM_AUTOIDLE1_CORE 4 @OMAP3430_CM_REG_A_BASE+0xA30 This register controls the automatic control of the CORE modules interface clock activity
f OMAP3430_reg_CM_AUTOIDLE3_CORE 4 @OMAP3430_CM_REG_A_BASE+0xA38 This register controls the automatic control of the CORE modules interface clock activity
f OMAP3430_reg_CM_CLKSEL_CORE 4 @OMAP3430_CM_REG_A_BASE+0xA40 CORE modules clock selection
f OMAP3430_reg_CM_CLKSTCTRL_CORE 4 @OMAP3430_CM_REG_A_BASE+0xA48 This register enables the domain power state transition. It controls the HW supervised domain power state transition between ACTIVE and INACTIVE states
f OMAP3430_reg_CM_CLKSTST_CORE 4 @OMAP3430_CM_REG_A_BASE+0xA4C This register provides a status on the interface clock activity in the domain
f OMAP3430_reg_CM_FCLKEN_SGX 4 @OMAP3430_CM_REG_A_BASE+0xB00 Controls the Graphic engine functional clock activity
f OMAP3430_reg_CM_ICLKEN_SGX 4 @OMAP3430_CM_REG_A_BASE+0xB10 Controls the Graphic engine interface clock activity
f OMAP3430_reg_CM_IDLEST_SGX 4 @OMAP3430_CM_REG_A_BASE+0xB20 SGX standby status. This register is read only and automatically updated
f OMAP3430_reg_CM_CLKSEL_SGX 4 @OMAP3430_CM_REG_A_BASE+0xB40 SGX clock selection
f OMAP3430_reg_CM_SLEEPDEP_SGX 4 @OMAP3430_CM_REG_A_BASE+0xB44 This register allows enabling or disabling the sleep transition dependency of SGX domain with respect to other domain
f OMAP3430_reg_CM_CLKSTCTRL_SGX 4 @OMAP3430_CM_REG_A_BASE+0xB48 This register enables the domain power state transition. It controls the HW supervised domain power state transition between ACTIVE and INACTIVE states
f OMAP3430_reg_CM_CLKSTST_SGX 4 @OMAP3430_CM_REG_A_BASE+0xB4C This register provides a status on the interface clock activity in the domain
f OMAP3430_reg_CM_FCLKEN_WKUP 4 @OMAP3430_CM_REG_A_BASE+0xC00 Controls the modules functional clock activity
f OMAP3430_reg_CM_ICLKEN_WKUP 4 @OMAP3430_CM_REG_A_BASE+0xC10 Controls the modules interface clock activity
f OMAP3430_reg_CM_IDLEST_WKUP 4 @OMAP3430_CM_REG_A_BASE+0xC20 WAKEUP domain modules access monitoring. This register is read only and automatically updated
f OMAP3430_reg_CM_AUTOIDLE_WKUP 4 @OMAP3430_CM_REG_A_BASE+0xC30 This register controls the automatic control of the WAKEUP modules interface clock activity. This activity is related to CORE domain activity
f OMAP3430_reg_CM_CLKSEL_WKUP 4 @OMAP3430_CM_REG_A_BASE+0xC40 WAKEUP domain modules source clock selection
f OMAP3430_reg_CM_CLKEN_PLL 4 @OMAP3430_CM_REG_A_BASE+0xD00 This register allows controlling the DPLL3 and DPLL4 modes
f OMAP3430_reg_CM_CLKEN2_PLL 4 @OMAP3430_CM_REG_A_BASE+0xD04 This register controls the DPLL5 modes
f OMAP3430_reg_CM_IDLEST_CKGEN 4 @OMAP3430_CM_REG_A_BASE+0xD20 This register allows monitoring the master clock activity. This register is read only and automatically updated
f OMAP3430_reg_CM_IDLEST2_CKGEN 4 @OMAP3430_CM_REG_A_BASE+0xD24 This register allows monitoring the master clock activity. This register is read only and automatically updated
f OMAP3430_reg_CM_AUTOIDLE_PLL 4 @OMAP3430_CM_REG_A_BASE+0xD30 This register provides automatic control over the DPLL3 and DPLL4 activity
f OMAP3430_reg_CM_AUTOIDEL2_PLL 4 @OMAP3430_CM_REG_A_BASE+0xD34 This register provides automatic control over the DPLL5 activity
f OMAP3430_reg_CM_CLKSEL1_PLL 4 @OMAP3430_CM_REG_A_BASE+0xD40 This register controls the selection of the master clock frequencies
f OMAP3430_reg_CM_CLKSEL2_PLL 4 @OMAP3430_CM_REG_A_BASE+0xD44 This register controls the selection of the master clock frequencies
f OMAP3430_reg_CM_CLKSEL3_PLL 4 @OMAP3430_CM_REG_A_BASE+0xD48 This register controls the selection of the master clock frequencies
f OMAP3430_reg_CM_CLKSEL4_PLL 4 @OMAP3430_CM_REG_A_BASE+0xD4C This register controls the selection of the master clock frequencies
f OMAP3430_reg_CM_CLKSEL5_PLL 4 @OMAP3430_CM_REG_A_BASE+0xD50 This register controls the selection of the master clock frequencies
f OMAP3430_reg_CM_CLKOUT_CTRL 4 @OMAP3430_CM_REG_A_BASE+0xD70 This register provides control over the SYS_CLKOUT2 output clock
f OMAP3430_reg_CM_FCLKEN_DSS 4 @OMAP3430_CM_REG_A_BASE+0xE00 Controls the modules functional clock activity
f OMAP3430_reg_CM_ICLKEN_DSS 4 @OMAP3430_CM_REG_A_BASE+0xE10 Controls the modules interface clock activity
f OMAP3430_reg_CM_IDLEST_DSS 4 @OMAP3430_CM_REG_A_BASE+0xE20 Module access availability monitoring. This register is read only and automatically updated
f OMAP3430_reg_CM_AUTOIDLE_DSS 4 @OMAP3430_CM_REG_A_BASE+0xE30 This register controls the automatic control of the modules interface clock activity
f OMAP3430_reg_CM_CLKSEL_DSS 4 @OMAP3430_CM_REG_A_BASE+0xE40 Modules clock selection
f OMAP3430_reg_CM_SLEEPDEP_DSS 4 @OMAP3430_CM_REG_A_BASE+0xE44 This register allows enebling or disabling the sleep transition dependency of DSS domain with respect to other domain
f OMAP3430_reg_CM_CLKSTCTRL_DSS 4 @OMAP3430_CM_REG_A_BASE+0xE48 This register enables the domain power state transition. It controls the HW supervised domain power state transition between ACTIVE and INACTIVE states
f OMAP3430_reg_CM_CLKSTST_DSS 4 @OMAP3430_CM_REG_A_BASE+0xE4C This register provides a status on the OCP interface clock activity in the domain
f OMAP3430_reg_CM_FCLKEN_CAM 4 @OMAP3430_CM_REG_A_BASE+0xF00 Controls the modules functional clock activity
f OMAP3430_reg_CM_ICLKEN_CAM 4 @OMAP3430_CM_REG_A_BASE+0xF10 Controls the modules interface clock activity
f OMAP3403_reg_CM_IDLEST_CAM 4 @OMAP3430_CM_REG_A_BASE+0xF20 Modules access availability monitoring. This register is read only and automatically updated
f OMAP3430_reg_CM_AUTOIDLE_CAM 4 @OMAP3430_CM_REG_A_BASE+0xF30 This register controls the automatic control of the modules interface clock activity
f OMAP3430_reg_CM_CLKSEL_CAM 4 @OMAP3430_CM_REG_A_BASE+0xF40 CAM module clock selection
f OMAP3430_reg_CM_SLEEPDEP_CAM 4 @OMAP3430_CM_REG_A_BASE+0xF44 This register allows enabling or disabling the sleep transition dependency of CAM domain with respect to other domain
f OMAP3430_reg_CM_CLKSTCTRL_CAM 4 @OMAP3430_CM_REG_A_BASE+0xF48 This register allows to enable or disable SW and HW supervised transition between ACTIVE and INACTIVE states
f OMAP3430_reg_CM_CLKSTST_CAM 4 @OMAP3430_CM_REG_A_BASE+0xF4C This register provides a status on the OCP interface clock activity in the domain
f OMAP3430_reg_CM_FCLKEN_PER 4 @OMAP3430_CM_REG_A_BASE+0x1000 Controls the modules functional clock activity
f OMAP3430_reg_CM_ICLKEN_PER 4 @OMAP3430_CM_REG_A_BASE+0x1010 Controls the modules interface clock activity
f OMAP3430_reg_CM_IDLEST_PER 4 @OMAP3430_CM_REG_A_BASE+0x1020 Modules access availability monitoring. This register is read only and automatically updated
f OMAP3430_reg_CM_AUTOIDLE_PER 4 @OMAP3430_CM_REG_A_BASE+0x1030 This register controls the automatic control of the modules interface clock activity
f OMAP3430_reg_CM_CLKSEL_PER 4 @OMAP3430_CM_REG_A_BASE+0x1040 PER domain modules source clock selection
f OMAP3430_reg_CM_SLEEPDEP_PER 4 @OMAP3430_CM_REG_A_BASE+0x1044 This register allows enebling or disabling the sleep transition dependency of PER domain with respect to other domain
f OMAP3430_reg_CM_CLKSTCTRL_PER 4 @OMAP3430_CM_REG_A_BASE+0x1048 This register enables the domain power state transition. It controls the HW supervised domain power state transition between ACTIVE and INACTIVE states
f OMAP3430_reg_CM_CLKSTST_PER 4 @OMAP3430_CM_REG_A_BASE+0x104C This register provides a status on the OCP interface clock activity in the domain
f OMAP3430_reg_CM_CLKSEL1_EMU 4 @OMAP3430_CM_REG_A_BASE+0x1140 Modules clock selection
f OMAP3430_reg_CM_CLKSTCTRL_EMU 4 @OMAP3430_CM_REG_A_BASE+0x1148 This register allows to enable or disable SW and HW supervised trasition between ACTIVE and INACTIVE states
f OMAP3430_reg_CM_CLKSTST_EMU 4 @OMAP3430_CM_REG_A_BASE+0x114C This register provides a status on the clock activity in the domain (dpends on the selected source clock)
f OMAP3430_reg_CM_CLKSEL2_EMU 4 @OMAP3430_CM_REG_A_BASE+0x1150 This register provides override controls over the DPLL3
f OMAP3430_reg_CM_CLKSEL3_EMU 4 @OMAP3430_CM_REG_A_BASE+0x1154 This register provides override controls over the PERIPHERAL DPLL
f OMAP3430_reg_CM_POLCTRL 4 @OMAP3430_CM_REG_A_BASE+0x129C This register allows setting the polarity of device outputs control signals
f OMAP3430_reg_CM_IDLEST_NEON 4 @OMAP3430_CM_REG_A_BASE+0x1320 Modules access availability monitoring. This register is read only and automatically updated
f OMAP3430_reg_CM_CLKSTCTRL_NEON 4 @OMAP3430_CM_REG_A_BASE+0x1348 This register enables the domain power state transition. It controls the HW supervised domain power state transition between ACTIVE and INACTIVE states
f OMAP3430_reg_CM_FCLKEN_USBHOST 4 @OMAP3430_CM_REG_A_BASE+0x1400 Controls the modules functional clock activity
f OMAP3430_reg_CM_ICLKEN_USBHOST 4 @OMAP3430_CM_REG_A_BASE+0x1410 Controls the modules interface clock activity
f OMAP3430_reg_CM_IDLEST_USBHOST 4 @OMAP3430_CM_REG_A_BASE+0x1420 Modules access availability monitoring. This register is read only and automatically updated
f OMAP3430_reg_CM_AUTOIDLE_USBHOST 4 @OMAP3430_CM_REG_A_BASE+0x1430 This register controls the automatic control of the modules interface clock activity
f OMAP3430_reg_CM_SLEEPDEP_USBHOST 4 @OMAP3430_CM_REG_A_BASE+0x1444 This register allows enabling or disabling the sleep transition dependency of USB HOST domain with respect to other domain
f OMAP3430_reg_CM_CLKSTCTRL_USBHOST 4 @OMAP3430_CM_REG_A_BASE+0x1448 This register enables the domain power state transition. It controls the HW supervised domain power state transition between ACTIVE and INACTIVE states
f OMAP3430_reg_CM_CLKSTST_USBHOST 4 @OMAP3430_CM_REG_A_BASE+0x144C This register provides a status on the interface clock activity in the domain
f OMAP3430_reg_RM_RSTCTRL_IVA2 4 @OMAP3430_PRM_BASE+0x50 This register controls the release of the IVA2 sub-system resets
f OMAP3430_reg_RM_RSTST_IVA2 4 @OMAP3430_PRM_BASE+0x58 This register logs the different reset sources of the IVA2 domain. Each bit is set upon release of the domain reset signal. Must be cleared by software
f OMAP3430_reg_PM_WKDEP_IVA2 4 @OMAP3430_PRM_BASE+0xC8 This register allows enabling or disabling the wake-up of the IVA2 domain upon another domain wakeup events
f OMAP3430_reg_PM_PWSTCTRL_IVA2 4 @OMAP3430_PRM_BASE+0xE0 This register controls the IVA2 domain power state transition
f OMAP3430_reg_PM_PWSTST_IVA2 4 @OMAP3430_PRM_BASE+0xE4 This register provides a status on the power state transition of the IVA2 domain
f OMAP3430_reg_PM_PREPWSTST_IVA2 4 @OMAP3430_PRM_BASE+0xE8 This register provides a status on the IVA2 domain previous power state. It indicates the state entered during the last sleep transition
f OMAP3430_reg_PRM_IRQSTATUS_IVA2 4 @OMAP3430_PRM_BASE+0xF8 This interrupt status register regroups all the status of the module internal events that can generate an interrupt. Write1 to a given bit resets this bit. This register applies on the interrupt line 1 mapped to the IVA2 interrupt controller
f OMAP3430_reg_PRM_IRQENABLE_IVA2 4 @OMAP3430_PRM_BASE+0xFC This interrupt enable register allows masking/unmasking the module internal sources of interrupt, on a event-by-event basis. This register applies on the interrupt line 0 mapped to the IVA2 Wake-Up Generator
f OMAP3430_reg_PRM_REVISION 4 @OMAP3430_PRM_BASE+0x804 This register contains the IP revision code for the PRM part of the PRCM
f OMAP3430_reg_PRM_SYSCONFIG 4 @OMAP3430_PRM_BASE+0x814 This register controls the various parameters of the interface
f OMAP3430_reg_PRM_IRQSTATUS_MPU 4 @OMAP3430_PRM_BASE+0x818 This interrupt status register regroups all the status of the module internal events that can generate an interrupt. Write 1 to a given bit resets this bit. This registers applies on the interrupt line 0 mapped to the MPU interrupt controller
f OMAP3430_reg_PRM_IRQENABLE_MPU 4 @OMAP3430_PRM_BASE+0x81C The interrupt enable register allows masking/unmasking the module internal sources of interrupt, on a event-by-event basis. This register applies on the interrupt line 0 mapped to the MPU interrupt controller
f OMAP3430_reg_RM_RSTST_MPU 4 @OMAP3430_PRM_BASE+0x958 This register logs the different reset sources of the MPU domain. Each bit is set upon release of the domain reset signal. Must be cleared by software
f OMAP3430_reg_PM_WKDEP_MPU 4 @OMAP3430_PRM_BASE+0x9C8 This register allows enabling or disabling the wake-up of the MPU domain upon another domain wakeup events
f OMAP3430_reg_PM_EVGENCTRL_MPU 4 @OMAP3430_PRM_BASE+0x9D4 This register allows controlling the feature of the event generator
f OMAP3430_reg_PM_EVGENONTIM_MPU 4 @OMAP3430_PRM_BASE+0x9D8 This register sets the ON count duration of the event generator (number of system clock cycles)
f OMAP3430_reg_PM_EVGENOFFTIM_MPU 4 @OMAP3430_PRM_BASE+0x9DC This register sets the OFF count duration of the event generator (number of system clock cycles)
f OMAP3430_reg_PM_PWSTCTRL_MPU 4 @OMAP3430_PRM_BASE+0x9E0 This register controls the MPU domain power state transition
f OMAP3430_reg_PM_PWSTST_MPU 4 @OMAP3430_PRM_BASE+0x9E4 This register provides a status on the MPU domain power state
f OMAP3430_reg_PM_PREPWSTST_MPU 4 @OMAP3430_PRM_BASE+0x9E8 This register provides a status on the MPU domain previous power state. It indicates the state entered during the last sleep transition
f OMAP3430_reg_RM_RSTST_CORE 4 @OMAP3430_PRM_BASE+0xA58 This register logs the different reset sources of the CORE domain. Each bit is set upon release of thee domain reset signal. Must be cleared by software
f OMAP3430_reg_PM_WKEN1_CORE 4 @OMAP3430_PRM_BASE+0xAA0 This register allows enabling/disabling modules wake-up events
f OMAP3430_reg_PM_MPUGRPSEL1_CORE 4 @OMAP3430_PRM_BASE+0xAA4 This register allows selecting the group of modules that wake-up the MPU
f OMAP3430_reg_PM_IVA2GRPSEL1_CORE 4 @OMAP3430_PRM_BASE+0xAA8 This register allows selecting the group of modules that wake-up the IVA2
f OMAP3430_reg_PM_WKST1_CORE 4 @OMAP3430_PRM_BASE+0xAB0 This register logs module wake-up events. Must be cleared by software. If it is not cleared, it prevents further domain transition
f OMAP3430_reg_PM_WKST3_CORE 4 @OMAP3430_PRM_BASE+0xAB8 This register logs module wake-up events. Must be cleared by software. If it is not cleared, it prevents further domain transition
f OMAP3430_reg_PM_PWSTCTRL_CORE 4 @OMAP3430_PRM_BASE+0xAE0 This register controls the CORE domain power state transition
f OMAP3430_reg_PM_PWSTST_CORE 4 @OMAP3430_PRM_BASE+0xAE4 This register provides a status on the power state transition of the CORE domain
f OMAP3430_reg_PM_PREPWSTST_CORE 4 @OMAP3430_PRM_BASE+0xAE8 This register provides a status on the CORE domain previous power state. It indicates the state entered during the last sleep transition
f OMAP3430_reg_PM_WKEN3_CORE 4 @OMAP3430_PRM_BASE+0xAF0 This register allows enabling/disabling modules wake-up events
f OMAP3430_reg_PM_IVA2GRPSEL3_CORE 4 @OMAP3430_PRM_BASE+0xAF4 This register allows selecting the group of modules that wake-up the IVA2
f OMAP3430_reg_PM_MPUGRPSEL3_CORE 4 @OMAP3430_PRM_BASE+0xAF8 This register allows selecting the group of modules that wake-up the MPU
f OMAP3430_reg_RM_RSTST_SGX 4 @OMAP3430_PRM_BASE+0xB58 This register logs the different reset sources of the SGX domain. Each bit is set upon release of the domain reset signal. Must be cleared by software
f OMAP3430_reg_PM_WKDEP_SGX 4 @OMAP3430_PRM_BASE+0xBC8 This register allows enabling or disabling the wake-up of the SGX domain upon another domain wakeup
f OMAP3430_reg_PM_PWSTCTRL_SGX 4 @OMAP3430_PRM_BASE+0xBE0 This register controls the SGX domain power state transition
f OMAP3430_reg_PM_PWSTST_SGX 4 @OMAP3430_PRM_BASE+0xBE4 This register provides a status on the power state transition of the SGX domain
f OMAP3430_reg_PM_PREPWSTST_SGX 4 @OMAP3430_PRM_BASE+0xBE8 This register provides a status on the SGX domain previous power state. It indicates the state entered during the last sleep transition
f OMAP3430_reg_PM_WKEN_WKUP 4 @OMAP3430_PRM_BASE+0xCA0 This register allows enabling/disabling modules wake-up events
f OMAP3430_reg_PM_MPUGRPSEL_WKUP 4 @OMAP3430_PRM_BASE+0xCA4 IO pad is always selected in the MPU wake-up events group
f OMAP3430_reg_PM_IVA2GRPSEL_WKUP 4 @OMAP3430_PRM_BASE+0xCA8 This register allows selecting the group of modules that wake-up the IVA2
f OMAP3430_reg_PM_WKST_WKUP 4 @OMAP3430_PRM_BASE+0xCB0 This register logs module wake-up events. Must be cleared by software. If it is not cleared, it prevents further domain transition
f OMAP3430_reg_PRM_CLKSEL 4 @OMAP3430_PRM_BASE+0xD40 This register controls the selection of the system clock frequency. This register is reset on power-up only
f OMAP3430_reg_PRM_CLKOUT_CTRL 4 @OMAP3430_PRM_BASE+0xD70 This register provides control over the SYS_CLKOUT1 output clock
f OMAP3430_reg_RM_RSTST_DSS 4 @OMAP3430_PRM_BASE+0xE58 This register logs the different reset sources of the DSS domain. Each bit is set upon release of the domain reset signal. Must be cleared by software
f OMAP3430_reg_PM_WKEN_DSS 4 @OMAP3430_PRM_BASE+0xEA0 This register allows enabling/disabling modules wake-up events
f OMAP3430_reg_PM_WKDEP_DSS 4 @OMAP3430_PRM_BASE+0xEC8 This register allows enabling or disabling the wake-up of the DISPLAY domain upon another domain wakeup
f OMAP3430_reg_PM_PWSTCTRL_DSS 4 @OMAP3430_PRM_BASE+0xEE0 This register controls the DISPLAY domain power state transition
f OMAP3430_reg_PM_PWSTST_DSS 4 @OMAP3430_PRM_BASE+0xEE4 This register provides a status on the power state transition of the DSS domain
f OMAP3430_reg_PM_PREPWSTST_DSS 4 @OMAP3430_PRM_BASE+0xEE8 This register provides a status on the DSS domain previous power state. It indicates the state entered during the last sleep transition
f OMAP3430_reg_RM_RSTST_CAM 4 @OMAP3430_PRM_BASE+0xF58 This register logs the different reset sources of the CAMERA domain. Each bit is set upon release of the domain reset signal. Must be cleared by software
f OMAP3430_reg_PM_WKDEP_CAM 4 @OMAP3430_PRM_BASE+0xFC8 This register allows enabling or disabling the wake-up of the CAM domain upon another domain
f OMAP3430_reg_PM_PWSTCTRL_CAM 4 @OMAP3430_PRM_BASE+0xFE0 This register controls the CAM domain power state transition
f OMAP3430_reg_PM_PWSTST_CAM 4 @OMAP3430_PRM_BASE+0xFE4 This register provides a status on the power state transition of the CAMERA domain
f OMAP3430_reg_PM_PREPWSTST_CAM 4 @OMAP3430_PRM_BASE+0xFE8 This register provides a status on the CAM domain previous power state. It indicates the state entered during the last sleep transition
f OMAP3430_reg_RM_RSTST_PER 4 @OMAP3430_PRM_BASE+0x1058 This register logs the different reset sources of the PERIPHERAL domain. Each bit is set upon release of the domain reset signal. Must be cleared by software
f OMAP3430_reg_PM_WKEN_PER 4 @OMAP3430_PRM_BASE+0x10A0 This register allows enabling/disabling modules wake-up events
f OMAP3430_reg_PM_MPUGRPSEL_PER 4 @OMAP3430_PRM_BASE+0x10A4 This register allows selecting the group of modules that wake-up the MPU
f OMAP3430_reg_PM_IVA2GRPSEL_PER 4 @OMAP3430_PRM_BASE+0x10A8 This register allows selecting the group of modules that wake-up the IVA2
f OMAP3430_reg_PM_WKST_PER 4 @OMAP3430_PRM_BASE+0x10B0 This register logs module wake-up events. Must be cleared by software. If it is not cleared, it prevents further domain transition
f OMAP3430_reg_PM_WKDEP_PER 4 @OMAP3430_PRM_BASE+0x10C8 This register allows enabling or disabling the wake-up of the PER domain upon another domain wakeup events
f OMAP3430_reg_PM_PWSTCTRL_PER 4 @OMAP3430_PRM_BASE+0x10E0 This register controls the PER domain power state transition
f OMAP3430_reg_PM_PWSTST_PER 4 @OMAP3430_PRM_BASE+0x10E4 This register provides a status on the power state transition of the PERIPHERAL domain
f OMAP3430_reg_PM_PREPWSTST_PER 4 @OMAP3430_PRM_BASE+0x10E8 This register provides a status on the PER domain previous power state. It indicates the state entered during the last sleep transition
f OMAP3430_reg_RM_RSTST_EMU 4 @OMAP3430_PRM_BASE+0x1158 This register logs the different reset sources of the EMU domain. Each bit is set upon release of the domain reset signal. Must be cleared by software
f OMAP3430_reg_PM_PWSTST_EMU 4 @OMAP3430_PRM_BASE+0x11E4 This register provides a status on the power state transition of the EMULATION domain
f OMAP3430_reg_PRM_VC_SMPS_SA 4 @OMAP3430_PRM_BASE+0x1220 This register allows the setting of the I2C slave address of the Power IC device
f OMAP3430_reg_PRM_VC_SMPS_VOL_RA 4 @OMAP3430_PRM_BASE+0x1224 This register allows the setting of the voltage configuration register address for the VDD channels
f OMAP3430_reg_PRM_VC_SMPS_CMD_RA 4 @OMAP3430_PRM_BASE+0x1228 This register allows the setting of the ON/Retention/OFF command configuration register address for the VDD channels. It is used if the Power IC device has different register addresses for voltage value and ON/Retention/OFF command
f OMAP3430_reg_PRM_VC_CMD_VAL_0 4 @OMAP3430_PRM_BASE+0x122C This register allows the setting of the ON/Retention/OFF voltage level values for the first VDD channel
f OMAP3430_reg_PRM_VC_CMD_VAL_1 4 @OMAP3430_PRM_BASE+0x1230 This register allows the setting of the ON/Retention/OFF voltage level values for the second VDD channel. It is used of the second channel has different values than the first channel
f OMAP3430_reg_PRM_VC_CH_CONF 4 @OMAP3430_PRM_BASE+0x1234 This register allows the configuration pointers for both VDD channels
f OMAP3430_reg_PRM_VC_I2C_CFG 4 @OMAP3430_PRM_BASE+0x1238 This register allows the configuration pointers for both VDD channels
f OMAP3430_reg_PRM_VC_BYPASS_VAL 4 @OMAP3430_PRM_BASE+0x123C This register allows the programming of the Power IC device using the bypass interface
f OMAP3430_reg_PRM_RSTCTRL 4 @OMAP3430_PRM_BASE+0x1250 Global software and DPLL3 reset control. This register is auto-cleared/ Only write 1 is possible. A read returns 0 only
f OMAP3430_reg_PRM_RSTTIME 4 @OMAP3430_PRM_BASE+0x1254 Reset duration control
f OMAP3430_reg_PRM_RSTST 4 @OMAP3430_PRM_BASE+0x1258 This register logs the global reset sources. Each bit is set upon release of the domain reset signal. Must be cleared by software
f OMAP3430_reg_PRM_VOLTCTRL 4 @OMAP3430_PRM_BASE+0x1260 This register allows a direct control on the external power IC
f OMAP3430_reg_PRM_SRAM_PCHARGE 4 @OMAP3430_PRM_BASE+0x1264 This register allows setting the pre-charge time of the SRAM
f OMAP3430_reg_PRM_CLKSRC_CTRL 4 @OMAP3430_PRM_BASE+0x1270 This register provides control over the device source clock
f OMAP3430_reg_PRM_OBS 4 @OMAP3430_PRM_BASE+0x1280 This register logs the observable signals (18 bits). This register is inteded to be read through the debugger interface when the device is in OFF mode
f OMAP3430_reg_PRM_VOLTSETUP1 4 @OMAP3430_PRM_BASE+0x1290 This register allows setting the setup time of the VDD1 and VDD2 regulators. This register is used when exiting off/retention/sleep mode (or entering off/retention/sleep mode) and when OMAP manages the sequencing of the voltages regulation steps
f OMAP3430_reg_PRM_VOLTOFFSET 4 @OMAP3430_PRM_BASE+0x1294 This register allows controlling the sys_offmode signal upon wake-up from OFF mode when the OFF sequence is supervised by the Power IC. This register allows setting the offset-time to de-assert sys_offmode when exiting the OFF mode
f OMAP3430_reg_PRM_CLKSETUP 4 @OMAP3430_PRM_BASE+0x1298 This register allows setting the setup time of the oscillator system clock (sys_clk), based on nnumber of 32 kHz clock cycles
f OMAP3430_reg_PRM_POLCTRL 4 @OMAP3430_PRM_BASE+0x129C This register allows setting the polarity of device outputs control signals
f OMAP3430_reg_PRM_VOLTSETUP2 4 @OMAP3430_PRM_BASE+0x12A0 This register allows setting the overall setup time of VDD1 and VDD2 regulators. This register is used when exiting OFF mode and when the Power IC manages the sequencing of the voltages regulation steps

# Here is an Secret Register Array. All information about them not available in public domain

f OMAP3430_reg_RM_RSTST_NEON 4 @OMAP3430_PRM_BASE+0x1358 This register logs the different reset sources of the NEON domain. Each bit is set upon release of the domain reset signal. Must be cleared by software
f OMAP3430_reg_PM_WKDEP_NEON 4 @OMAP3430_PRM_BASE+0x13C8 This register allows enabling or disabling the wake-up of the NEON domain upon another domain
f OMAP3430_reg_PM_PWSTCTRL_NEON 4 @OMAP3430_PRM_BASE+0x13E0 This register controls the NEON domain power state transition
f OMAP3430_reg_PM_PWSTST_NEON 4 @OMAP3430_PRM_BASE+0x13E4 This register provides a status on the power state transition of the NEON domain
f OMAP3430_reg_PM_PREPWSTST_NEON 4 @OMAP3430_PRM_BASE+0x13E8 This register provides a status on the NEON domain previous power state. It indicates the state entered during the last sleep transition
f OMAP3430_reg_RM_RSTST_USBHOST 4 @OMAP3430_PRM_BASE+0x1458 This register logs the different reset sources of the USBHOST domain. Each bit is set upon release of the domain reset signal. Must be cleared by software
f OMAP3430_reg_PM_WKEN_USBHOST 4 @OMAP3430_PRM_BASE+0x14A0 This register allows enabling/disabling modules wake-up events
f OMAP3430_reg_PM_MPUGRPSEL_USBHOST 4 @OMAP3430_PRM_BASE+0x14A4 This register allows selecting the group of modules that wake-up the MPU
f OMAP3430_reg_PM_IVA2GRPSEL_USBHOST 4 @OMAP3430_PRM_BASE+0x14A8 This register allows selecting the group of modules that wake-up the IVA2
f OMAP3430_reg_PM_WKST_USBHOST 4 @OMAP3430_PRM_BASE+0x14B0 This register logs module wake-up events. Must be cleared by software. If it is not cleared, it prevents further domain transition
f OMAP3430_reg_PM_WKDEP_USBHOST 4 @OMAP3430_PRM_BASE+0x14C8 This register allows enabling or disabling the wake-up of the USB HOST domain upon another domain wakeup
f OMAP3430_reg_PM_PWSTCTRL_USBHOST 4 @OMAP3430_PRM_BASE+0x14E0 This register controls the USB HOST domain power state transition
f OMAP3430_reg_PM_PWSTST_USBHOST 4 @OMAP3430_PRM_BASE+0x14E4 This register provides a status on the power state transition of the USB HOST domain
f OMAP3430_reg_PM_PREPWSTST_USBHOST 4 @OMAP3430_PRM_BASE+0x14E8 This register provides a status on the USB HOST domain previous power state. It indicates the state entered during the last sleep transition
f OMAP3430_reg_MAILBOX_REVISION 4 @OMAP3430_MLB_BASE+0x0 This register contains the IP revision code.
f OMAP3430_reg_MAILBOX_SYSCONFIG 4 @OMAP3430_MLB_BASE+0x10 This register controls the various parameters of the L4-Core interface
f OMAP3430_reg_MAILBOX_SYSSTATUS 4 @OMAP3430_MLB_BASE+0x14 This register provides status information about the module, excluding the interrupt status information
f OMAP3430_reg_MAILBOX_MESSAGE_0 4 @OMAP3430_MLB_BASE+0x40 The message register stores the next to be read message of the mailbox 0
f OMAP3430_reg_MAILBOX_MESSAGE_1 4 @OMAP3430_MLB_BASE+0x44 The message register stores the next to be read message of the mailbox 1
f OMAP3430_reg_MAILBOX_FIFOSTATUS_0 4 @OMAP3430_MLB_BASE+0x80 The FIFO status register has the status related to the mailbox internal FIFO
f OMAP3430_reg_MAILBOX_FIFOSTATUS_1 4 @OMAP3430_MLB_BASE+0x84 The FIFO status register has the status related to the mailbox internal FIFO
f OMAP3430_reg_MAILBOX_MSGSTATUS_0 4 @OMAP3430_MLB_BASE+0xC0 The message status register has the status of the messages in the mailbox
f OMAP3430_reg_MAILBOX_MSGSTATUS_1 4 @OMAP3430_MLB_BASE+0xC4 The message status register has the status of the messages in the mailbox
f OMAP3430_reg_MAILBOX_IRQSTATUS_0 4 @OMAP3430_MLB_BASE+0x100 The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit
f OMAP3430_reg_MAILBOX_IRQENABLE_0 4 @OMAP3430_MLB_BASE+0x104 The interrupt enable register enables to mask/unmask the module internal source of interrupt to the corresponding user
f OMAP3430_reg_MAILBOX_IRQSTATUS_1 4 @OMAP3430_MLB_BASE+0x108 The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit
f OMAP3430_reg_MAILBOX_IRQENABLE_1 4 @OMAP3430_MLB_BASE+0x10C The interrupt enable register enables to mask/unmask the module internal source of interrupt to the corresponding user
f OMAP3430_reg_CAM_MMU_REVISION 4 @OMAP3430_MMU_CAM_BASE+0x0 This register contains the IP revision code
f OMAP3430_reg_CAM_MMU_SYSCONFIG 4 @OMAP3430_MMU_CAM_BASE+0x10 This register contains the various parameters of the interconnect interface
f OMAP3430_reg_CAM_MMU_SYSSTATUS 4 @OMAP3430_MMU_CAM_BASE+0x14 This register provides status information about the module, excluding the interrupt status information
f OMAP3430_reg_CAM_MMU_IRQSTATUS 4 @OMAP3430_MMU_CAM_BASE+0x18 This interrupt status register regroups all the status of the module internal events that can generate an interrupt
f OMAP3430_reg_CAM_MMU_IRQENABLE 4 @OMAP3430_MMU_CAM_BASE+0x1C The interrupt enable register allows the module's internal sources of interrupt to be masked and unmasked on an event-by-event basis
f OMAP3430_reg_CAM_MMU_WALKING_ST 4 @OMAP3430_MMU_CAM_BASE+0x40 This register provides status information about the table walking logic
f OMAP3430_reg_CAM_MMU_CNTL 4 @OMAP3430_MMU_CAM_BASE+0x44 This register programs the MMU features
f OMAP3430_reg_CAM_MMU_FAULT_AD 4 @OMAP3430_MMU_CAM_BASE+0x48 This register contains the virtual address that generated the interrupt
f OMAP3430_reg_CAM_MMU_TTB 4 @OMAP3430_MMU_CAM_BASE+0x4C This register contains the resolution table base address
f OMAP3430_reg_CAM_MMU_LOCK 4 @OMAP3430_MMU_CAM_BASE+0x50 This register locks some of the TLB entries or specifies the TLB entry to be read
f OMAP3430_reg_CAM_MMU_LD_TLB 4 @OMAP3430_MMU_CAM_BASE+0x54 This register loads a TLB entry (CAM+RAM)
f OMAP3430_reg_CAM_MMU_CAM 4 @OMAP3430_MMU_CAM_BASE+0x58 This register holds a CAM entry
f OMAP3430_reg_CAM_MMU_RAM 4 @OMAP3430_MMU_CAM_BASE+0x5C This register holds a RAM entry
f OMAP3430_reg_CAM_MMU_GFLUSH 4 @OMAP3430_MMU_CAM_BASE+0x60 This register flushes all the non-protected TLB entries
f OMAP3430_reg_CAM_MMU_FLUSH_ENTRY 4 @OMAP3430_MMU_CAM_BASE+0x64 This register flushes the entry pointed to by the CAM virtual address
f OMAP3430_reg_CAM_MMU_READ_CAM 4 @OMAP3430_MMU_CAM_BASE+0x68 This register reads CAM data from a CAM entry
f OMAP3430_reg_CAM_MMU_READ_RAM 4 @OMAP3430_MMU_CAM_BASE+0x6C This register reads RAM data from a RAM entry
f OMAP3430_reg_CAM_MMU_EMU_FAULT_AD 4 @OMAP3430_MMU_CAM_BASE+0x70 This register contains the last virtual address of a fault caused by the debugger
f OMAP3430_reg_IVA2_MMU_REVISION 4 @OMAP3430_MMU_IVA2_BASE+0x0 This register contains the IP revision code
f OMAP3430_reg_IVA2_MMU_SYSCONFIG 4 @OMAP3430_MMU_IVA2_BASE+0x10 This register contains the various parameters of the interconnect interface
f OMAP3430_reg_IVA2_MMU_SYSSTATUS 4 @OMAP3430_MMU_IVA2_BASE+0x14 This register provides status information about the modules, excluding the interrupt status information
f OMAP3430_reg_IVA2_MMU_IRQSTATUS 4 @OMAP3430_MMU_IVA2_BASE+0x18 This interrupt status register regroups all the status of the module internal events that can generate an interrupt
f OMAP3430_reg_IVA2_MMU_IRQENABLE 4 @OMAP3430_MMU_IVA2_BASE+0x1C The interrupt enable register allows the module's internal sources of interrupt to be masked and unmasked on an event-by-event basis
f OMAP3430_reg_IVA2_MMU_WALKING_ST 4 @OMAP3430_MMU_IVA2_BASE+0x40 This register provides status information about the table walking logic
f OMAP3430_reg_IVA2_MMU_CNTL 4 @OMAP3430_MMU_IVA2_BASE+0x44 This register programs the MMU features
f OMAP3430_reg_IVA2_MMU_FAULT_AD 4 @OMAP3430_MMU_IVA2_BASE+0x48 This register contains the virtual address that generated the interrupt
f OMAP3430_reg_IVA2_MMU_TTB 4 @OMAP3430_MMU_IVA2_BASE+0x4C This register contains the resolution table base address
f OMAP3430_reg_IVA2_MMU_LOCK 4 @OMAP3430_MMU_IVA2_BASE+0x50 This register locks some of the TLB entries or specifies the TLB entry to be read
f OMAP3430_Reg_IVA2_MMU_LD_TLB 4 @OMAP3430_MMU_IVA2_BASE+0x54 This register loads a TLB entry (CAM+RAM)
f OMAP3430_reg_IVA2_MMU_CAM 4 @OMAP3430_MMU_IVA2_BASE+0x58 This register holds a CAM entry
f OMAP3430_reg_IVA2_MMU_RAM 4 @OMAP3430_MMU_IVA2_BASE+0x5C This register holds a RAM entry
f OMAP3430_reg_IVA2_MMU_GFLUSH 4 @OMAP3430_MMU_IVA2_BASE+0x60 This register flushes all the non-protected TLB entries
f OMAP3430_reg_IVA2_MMU_FLUSH_ENTRY 4 @OMAP3430_MMU_IVA2_BASE+0x64 This register flushes the entry pointed to by the CAM virtual address
f OMAP3430_reg_IVA2_MMU_READ_CAM 4 @OMAP3430_MMU_IVA2_BASE+0x68 This register read CAM data from a CAM entry
f OMAP3430_reg_IVA2_MMU_READ_RAM 4 @OMAP3430_MMU_IVA2_BASE+0x6C This register read RAM data from a RAM entry
f OMAP3430_reg_IVA2_MMU_EMU_FAULT_AD 4 @OMAP3430_MMU_IVA2_BASE+0x70 This register contains the last virtual address of a fault caused by the debugger
f OMAP3430_reg_DMA4_REVISION 4 @OMAP3430_SDMA_BASE+0x0 This register contains the DMA revision code
f OMAP3430_reg_DMA4_IRQSTATUS_L0 4 @OMAP3430_SDMA_BASE+0x8 The interrupt status register regroups all the status of the DMA4 channels that can generate an interrupt over line L0
f OMAP3430_reg_DMA4_IRQSTATUS_L1 4 @OMAP3430_SDMA_BASE+0xC The interrupt status register regroups all the status of the DMA4 channels that can generate an interrupt over line L1
f OMAP3430_reg_DMA4_IRQSTATUS_L2 4 @OMAP3430_SDMA_BASE+0x10 The interrupt status register regroups all the status of the DMA4 channels that can generate an interrupt over line L2
f OMAP3430_reg_DMA4_IRQSTATUS_L3 4 @OMAP3430_SDMA_BASE+0x14 The interrupt status register regroups all the status of the DMA4 channels that can generate an interrupt over line L3
f OMAP3430_reg_DMA4_IRQENABLE_L0 4 @OMAP3430_SDMA_BASE+0x18 The interrupt enable register allows to mask/unmask the module internal sources of interrupt, on line L0
f OMAP3430_reg_DMA4_IRQENABLE_L1 4 @OMAP3430_SDMA_BASE+0x1C The interrupt enable register allows to mask/unmask the module internal sources of interrupt, on line L1
f OMAP3430_reg_DMA4_IRQENABLE_L2 4 @OMAP3430_SDMA_BASE+0x20 The interrupt enable register allows to mask/unmask the module internal sources of interrupt, on line L2
f OMAP3430_reg_DMA4_IRQENABLE_L3 4 @OMAP3430_SDMA_BASE+0x24 The interrupt enable register allows to mask/unmask the module internal sources of interrupt, on line L3
f OMAP3430_reg_DMA4_SYSSTATUS 4 @OMAP3430_SDMA_BASE+0x28 The register provides status information about the module excluding the interrupt status information
f OMAP3430_reg_DMA4_OCP_SYSCONFIG 4 @OMAP3430_SDMA_BASE+0x2C This register controls the various parameters of the OCP interface
f OMAP3430_reg_DMA4_CAPS_0 4 @OMAP3430_SDMA_BASE+0x64 DMA Capabilities Register 0 LSW
f OMAP3430_reg_DMA4_CAPS_2 4 @OMAP3430_SDMA_BASE+0x6C DMA Capabilities Register 2
f OMAP3430_reg_DMA4_CAPS_3 4 @OMAP3430_SDMA_BASE+0x70 DMA Capabilities Register 3
f OMAP3430_reg_DMA4_CAPS_4 4 @OMAP3430_SDMA_BASE+0x74 DMA Capabilities Register 4
f OMAP3430_reg_DMA4_GCR 4 @OMAP3430_SDMA_BASE+0x78 FIFO sharing between high and low priority channel. The Maximum per channel FIFO depth is bounded by the low and high channel FIFO bufget. The high respectively low priority channels maximum burst size must be less than the min (high respectively low priority channel FIFO budget, per channel maximum FIFO depth)
f OMAP3430_reg_DMA4_CCR0 4 @OMAP3430_SDMA_BASE+0x80 Channel Control Register
f OMAP3430_reg_DMA4_CLNK_CTRL0 4 @OMAP3430_SDMA_BASE+0x84 Channel Link Control Register
f OMAP3430_reg_DMA4_CICR0 4 @OMAP3430_SDMA_BASE+0x88 Channel Interrupt Control Register
f OMAP3430_reg_DMA4_CSR0 4 @OMAP3430_SDMA_BASE+0x8C Channel Status Register
f OMAP3430_reg_DMA4_CSDP0 4 @OMAP3430_SDMA_BASE+0x90 Channel Source Destination Parameters
f OMAP3430_reg_DMA4_CEN0 4 @OMAP3430_SDMA_BASE+0x94 Channel Element Number
f OMAP3430_reg_DMA4_CFN0 4 @OMAP3430_SDMA_BASE+0x98 Channel Frame Number
f OMAP3430_reg_DMA4_CSSA0 4 @OMAP3430_SDMA_BASE+0x9C Channel Source Start Address
f OMAP3430_reg_DMA4_CDSA0 4 @OMAP3430_SDMA_BASE+0xA0 Channel Destination Start Address
f OMAP3430_reg_DMA4_CSEI0 4 @OMAP3430_SDMA_BASE+0xA4 Channel Source Element Index (Signed)
f OMAP3430_reg_DMA4_CSFI0 4 @OMAP3430_SDMA_BASE+0xA8 Channel Source Frame Index (Signed) or 16-bit Packet size
f OMAP3430_reg_DMA4_CDEI0 4 @OMAP3430_SDMA_BASE+0xAC Channel Destination Element Index (Signed)
f OMAP3430_reg_DMA4_CDFI0 4 @OMAP3430_SDMA_BASE+0xB0 Channel Destination Frame Index (Signed) or 16-bit Packet size
f OMAP3430_reg_DMA4_CSAC0 4 @OMAP3430_SDMA_BASE+0xB4 Channel Source Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16-bit data may be corrupted
f OMAP3430_reg_DMA4_CDAC0 4 @OMAP3430_SDMA_BASE+0xB8 Channel Destination Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16-bit data may be corrupted
f OMAP3430_reg_DMA4_CCEN0 4 @OMAP3430_SDMA_BASE+0xBC Channel Current Transferred Element Number in the current frame. User has to access this register only in 32-bit access. If accessed in 8-bit or 16-bit data may be corrupted
f OMAP3430_reg_DMA4_CCFN0 4 @OMAP3430_SDMA_BASE+0xC0 Channel Current Transferred Frame Number in the current transfer. User has to access this register only in 32-bit access. If accessed in 8-bit or 16-bit data may be corrupted
f OMAP3430_reg_DMA4_COLOR0 4 @OMAP3430_SDMA_BASE+0xC4 Channel DMA COLOR KEY / SOLID COLOR
f OMAP3430_reg_DMA4_CCR1 4 @OMAP3430_SDMA_BASE+0xE0 Channel Control Register
f OMAP3430_reg_DMA4_CLNK_CTRL1 4 @OMAP3430_SDMA_BASE+0xE4 Channel Link Control Register
f OMAP3430_reg_DMA4_CICR1 4 @OMAP3430_SDMA_BASE+0xE8 Channel Interrupt Control Register
f OMAP3430_reg_DMA4_CSR1 4 @OMAP3430_SDMA_BASE+0xEC Channel Status Register
f OMAP3430_reg_DMA4_CSDP1 4 @OMAP3430_SDMA_BASE+0xF0 Channel Source Destination Parameters
f OMAP3430_reg_DMA4_CEN1 4 @OMAP3430_SDMA_BASE+0xF4 Channel Element Number
f OMAP3430_reg_DMA4_CFN1 4 @OMAP3430_SDMA_BASE+0xF8 Channel Frame Number
f OMAP3430_reg_DMA4_CSSA1 4 @OMAP3430_SDMA_BASE+0xFC Channel Source Start Address
f OMAP3430_reg_DMA4_CDSA1 4 @OMAP3430_SDMA_BASE+0x100 Channel Destination Start Address
f OMAP3430_reg_DMA4_CSEI1 4 @OMAP3430_SDMA_BASE+0x104 Channel Source Element Index (Signed)
f OMAP3430_reg_DMA4_CSFI1 4 @OMAP3430_SDMA_BASE+0x108 Channel Source Frame Index (Signed) or 16-bit Packet size
f OMAP3430_reg_DMA4_CDEI1 4 @OMAP3430_SDMA_BASE+0x10C Channel Destination Element Index (Signed)
f OMAP3430_reg_DMA4_CDFI1 4 @OMAP3430_SDMA_BASE+0x110 Channel Destination Frame Index (Signed) or 16-bit Packet size
f OMAP3430_reg_DMA4_CSAC1 4 @OMAP3430_SDMA_BASE+0x114 Channel Source Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16-bit data may be corrupted
f OMAP3430_reg_DMA4_CDAC1 4 @OMAP3430_SDMA_BASE+0x118 Channel Destination Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16-bit data may be corrupted
f OMAP3430_reg_DMA4_CCEN1 4 @OMAP3430_SDMA_BASE+0x11C Channel Current Transferred Element Number in the current frame. User has to access this register only in 32-bit access. If accessed in 8-bit or 16-bit data may be corrupted
f OMAP3430_reg_DMA4_CCFN1 4 @OMAP3430_SDMA_BASE+0x120 Channel Current Transferred Frame Number in the current transfer. User has to access this register only in 32-bit access. If accessed in 8-bit or 16-bit data may be corrupted
f OMAP3430_reg_DMA4_COLOR1 4 @OMAP3430_SDMA_BASE+0x124 Channel DMA COLOR KEY / SOLID COLOR
f OMAP3430_reg_DMA4_CCR2 4 @OMAP3430_SDMA_BASE+0x140 Channel Control Register
f OMAP3430_reg_DMA4_CLNK_CTRL2 4 @OMAP3430_SDMA_BASE+0x144 Channel Link Control Register
f OMAP3430_reg_DMA4_CICR2 4 @OMAP3430_SDMA_BASE+0x148 Channel Interrupt Control Register
f OMAP3430_reg_DMA4_CSR2 4 @OMAP3430_SDMA_BASE+0x14C Channel Status Register
f OMAP3430_reg_DMA4_CSDP2 4 @OMAP3430_SDMA_BASE+0x150 Channel Source Destination Parameters
f OMAP3430_reg_DMA4_CEN2 4 @OMAP3430_SDMA_BASE+0x154 Channel Element Number
f OMAP3430_reg_DMA4_CFN2 4 @OMAP3430_SDMA_BASE+0x158 Channel Frame Number
f OMAP3430_reg_DMA4_CSSA2 4 @OMAP3430_SDMA_BASE+0x15C Channel Source Start Address
f OMAP3430_reg_DMA4_CDSA2 4 @OMAP3430_SDMA_BASE+0x160 Channel Destination Start Address
f OMAP3430_reg_DMA4_CSEI2 4 @OMAP3430_SDMA_BASE+0x164 Channel Source Element Index (Signed)
f OMAP3430_reg_DMA4_CSFI2 4 @OMAP3430_SDMA_BASE+0x168 Channel Source Frame Index (Signed) or 16-bit Packet size
f OMAP3430_reg_DMA4_CDEI2 4 @OMAP3430_SDMA_BASE+0x16C Channel Destination Element Index (Signed)
f OMAP3430_reg_DMA4_CDFI2 4 @OMAP3430_SDMA_BASE+0x170 Channel Destination Frame Index (Signed) or 16-bit Packet size
f OMAP3430_reg_DMA4_CSAC2 4 @OMAP3430_SDMA_BASE+0x174 Channel Source Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16-bit data may be corrupted
f OMAP3430_reg_DMA4_CDAC2 4 @OMAP3430_SDMA_BASE+0x178 Channel Destination Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16-bit data may be corrupted
f OMAP3430_reg_DMA4_CCEN2 4 @OMAP3430_SDMA_BASE+0x17C Channel Current Transferred Element Number in the current frame. User has to access this register only in 32-bit access. If accessed in 8-bit or 16-bit data may be corrupted
f OMAP3430_reg_DMA4_CCFN2 4 @OMAP3430_SDMA_BASE+0x180 Channel Current Transferred Frame Number in the current transfer. User has to access this register only in 32-bit access. If accessed in 8-bit or 16-bit data may be corrupted
f OMAP3430_reg_DMA4_COLOR2 4 @OMAP3430_SDMA_BASE+0x184 Channel DMA COLOR KEY / SOLID COLOR
f OMAP3430_reg_DMA4_CCR3 4 @OMAP3430_SDMA_BASE+0x1A0 Channel Control Register
f OMAP3430_reg_DMA4_CLNK_CTRL3 4 @OMAP3430_SDMA_BASE+0x1A4 Channel Link Control Register
f OMAP3430_reg_DMA4_CICR3 4 @OMAP3430_SDMA_BASE+0x1A8 Channel Interrupt Control Register
f OMAP3430_reg_DMA4_CSR3 4 @OMAP3430_SDMA_BASE+0x1AC Channel Status Register
f OMAP3430_reg_DMA4_CSDP3 4 @OMAP3430_SDMA_BASE+0x1B0 Channel Source Destination Parameters
f OMAP3430_reg_DMA4_CEN3 4 @OMAP3430_SDMA_BASE+0x1B4 Channel Element Number
f OMAP3430_reg_DMA4_CFN3 4 @OMAP3430_SDMA_BASE+0x1B8 Channel Frame Number
f OMAP3430_reg_DMA4_CSSA3 4 @OMAP3430_SDMA_BASE+0x1BC Channel Source Start Address
f OMAP3430_reg_DMA4_CDSA3 4 @OMAP3430_SDMA_BASE+0x1C0 Channel Destination Start Address
f OMAP3430_reg_DMA4_CSEI3 4 @OMAP3430_SDMA_BASE+0x1C4 Channel Source Element Index (Signed)
f OMAP3430_reg_DMA4_CSFI3 4 @OMAP3430_SDMA_BASE+0x1C8 Channel Source Frame Index (Signed) or 16-bit Packet size
f OMAP3430_reg_DMA4_CDEI3 4 @OMAP3430_SDMA_BASE+0x1CC Channel Destination Element Index (Signed)
f OMAP3430_reg_DMA4_CDFI3 4 @OMAP3430_SDMA_BASE+0x1D0 Channel Destination Frame Index (Signed) or 16-bit Packet size
f OMAP3430_reg_DMA4_CSAC3 4 @OMAP3430_SDMA_BASE+0x1D4 Channel Source Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16-bit data may be corrupted
f OMAP3430_reg_DMA4_CDAC3 4 @OMAP3430_SDMA_BASE+0x1D8 Channel Destination Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16-bit data may be corrupted
f OMAP3430_reg_DMA4_CCEN3 4 @OMAP3430_SDMA_BASE+0x1DC Channel Current Transferred Element Number in the current frame. User has to access this register only in 32-bit access. If accessed in 8-bit or 16-bit data may be corrupted
f OMAP3430_reg_DMA4_CCFN3 4 @OMAP3430_SDMA_BASE+0x1E0 Channel Current Transferred Frame Number in the current transfer. User has to access this register only in 32-bit access. If accessed in 8-bit or 16-bit data may be corrupted
f OMAP3430_reg_DMA4_COLOR3 4 @OMAP3430_SDMA_BASE+0x1E4 Channel DMA COLOR KEY / SOLID COLOR
f OMAP3430_reg_DMA4_CCR4 4 @OMAP3430_SDMA_BASE+0x200 Channel Control Register
f OMAP3430_reg_DMA4_CLNK_CTRL4 4 @OMAP3430_SDMA_BASE+0x204 Channel Link Control Register
f OMAP3430_reg_DMA4_CICR4 4 @OMAP3430_SDMA_BASE+0x208 Channel Interrupt Control Register
f OMAP3430_reg_DMA4_CSR4 4 @OMAP3430_SDMA_BASE+0x20C Channel Status Register
f OMAP3430_reg_DMA4_CSDP4 4 @OMAP3430_SDMA_BASE+0x210 Channel Source Destination Parameters
f OMAP3430_reg_DMA4_CEN4 4 @OMAP3430_SDMA_BASE+0x214 Channel Element Number
f OMAP3430_reg_DMA4_CFN4 4 @OMAP3430_SDMA_BASE+0x218 Channel Frame Number
f OMAP3430_reg_DMA4_CSSA4 4 @OMAP3430_SDMA_BASE+0x21C Channel Source Start Address
f OMAP3430_reg_DMA4_CDSA4 4 @OMAP3430_SDMA_BASE+0x220 Channel Destination Start Address
f OMAP3430_reg_DMA4_CSEI4 4 @OMAP3430_SDMA_BASE+0x224 Channel Source Element Index (Signed)
f OMAP3430_reg_DMA4_CSFI4 4 @OMAP3430_SDMA_BASE+0x228 Channel Source Frame Index (Signed) or 16-bit Packet size
f OMAP3430_reg_DMA4_CDEI4 4 @OMAP3430_SDMA_BASE+0x22C Channel Destination Element Index (Signed)
f OMAP3430_reg_DMA4_CDFI4 4 @OMAP3430_SDMA_BASE+0x230 Channel Destination Frame Index (Signed) or 16-bit Packet size
f OMAP3430_reg_DMA4_CSAC4 4 @OMAP3430_SDMA_BASE+0x234 Channel Source Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16-bit data may be corrupted
f OMAP3430_reg_DMA4_CDAC4 4 @OMAP3430_SDMA_BASE+0x238 Channel Destination Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16-bit data may be corrupted
f OMAP3430_reg_DMA4_CCEN4 4 @OMAP3430_SDMA_BASE+0x23C Channel Current Transferred Element Number in the current frame. User has to access this register only in 32-bit access. If accessed in 8-bit or 16-bit data may be corrupted
f OMAP3430_reg_DMA4_CCFN4 4 @OMAP3430_SDMA_BASE+0x240 Channel Current Transferred Frame Number in the current transfer. User has to access this register only in 32-bit access. If accessed in 8-bit or 16-bit data may be corrupted
f OMAP3430_reg_DMA4_COLOR4 4 @OMAP3430_SDMA_BASE+0x244 Channel DMA COLOR KEY / SOLID COLOR
f OMAP3430_reg_DMA4_CCR5 4 @OMAP3430_SDMA_BASE+0x260 Channel Control Register
f OMAP3430_reg_DMA4_CLNK_CTRL5 4 @OMAP3430_SDMA_BASE+0x264 Channel Link Control Register
f OMAP3430_reg_DMA4_CICR5 4 @OMAP3430_SDMA_BASE+0x268 Channel Interrupt Control Register
f OMAP3430_reg_DMA4_CSR5 4 @OMAP3430_SDMA_BASE+0x26C Channel Status Register
f OMAP3430_reg_DMA4_CSDP5 4 @OMAP3430_SDMA_BASE+0x270 Channel Source Destination Parameters
f OMAP3430_reg_DMA4_CEN5 4 @OMAP3430_SDMA_BASE+0x274 Channel Element Number
f OMAP3430_reg_DMA4_CFN5 4 @OMAP3430_SDMA_BASE+0x278 Channel Frame Number
f OMAP3430_reg_DMA4_CSSA5 4 @OMAP3430_SDMA_BASE+0x27C Channel Source Start Address
f OMAP3430_reg_DMA4_CDSA5 4 @OMAP3430_SDMA_BASE+0x280 Channel Destination Start Address
f OMAP3430_reg_DMA4_CSEI5 4 @OMAP3430_SDMA_BASE+0x284 Channel Source Element Index (Signed)
f OMAP3430_reg_DMA4_CSFI5 4 @OMAP3430_SDMA_BASE+0x288 Channel Source Frame Index (Signed) or 16-bit Packet size
f OMAP3430_reg_DMA4_CDEI5 4 @OMAP3430_SDMA_BASE+0x28C Channel Destination Element Index (Signed)
f OMAP3430_reg_DMA4_CDFI5 4 @OMAP3430_SDMA_BASE+0x290 Channel Destination Frame Index (Signed) or 16-bit Packet size
f OMAP3430_reg_DMA4_CSAC5 4 @OMAP3430_SDMA_BASE+0x294 Channel Source Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16-bit data may be corrupted
f OMAP3430_reg_DMA4_CDAC5 4 @OMAP3430_SDMA_BASE+0x298 Channel Destination Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16-bit data may be corrupted
f OMAP3430_reg_DMA4_CCEN5 4 @OMAP3430_SDMA_BASE+0x29C Channel Current Transferred Element Number in the current frame. User has to access this register only in 32-bit access. If accessed in 8-bit or 16-bit data may be corrupted
f OMAP3430_reg_DMA4_CCFN5 4 @OMAP3430_SDMA_BASE+0x2A0 Channel Current Transferred Frame Number in the current transfer. User has to access this register only in 32-bit access. If accessed in 8-bit or 16-bit data may be corrupted
f OMAP3430_reg_DMA4_COLOR5 4 @OMAP3430_SDMA_BASE+0x2A4 Channel DMA COLOR KEY / SOLID COLOR
f OMAP3430_reg_DMA4_CCR6 4 @OMAP3430_SDMA_BASE+0x2C0 Channel Control Register
f OMAP3430_reg_DMA4_CLNK_CTRL6 4 @OMAP3430_SDMA_BASE+0x2C4 Channel Link Control Register
f OMAP3430_reg_DMA4_CICR6 4 @OMAP3430_SDMA_BASE+0x2C8 Channel Interrupt Control Register
f OMAP3430_reg_DMA4_CSR6 4 @OMAP3430_SDMA_BASE+0x2CC Channel Status Register
f OMAP3430_reg_DMA4_CSDP6 4 @OMAP3430_SDMA_BASE+0x2D0 Channel Source Destination Parameters
f OMAP3430_reg_DMA4_CEN6 4 @OMAP3430_SDMA_BASE+0x2D4 Channel Element Number
f OMAP3430_reg_DMA4_CFN6 4 @OMAP3430_SDMA_BASE+0x2D8 Channel Frame Number
f OMAP3430_reg_DMA4_CSSA6 4 @OMAP3430_SDMA_BASE+0x2DC Channel Source Start Address
f OMAP3430_reg_DMA4_CDSA6 4 @OMAP3430_SDMA_BASE+0x2E0 Channel Destination Start Address
f OMAP3430_reg_DMA4_CSEI6 4 @OMAP3430_SDMA_BASE+0x2E4 Channel Source Element Index (Signed)
f OMAP3430_reg_DMA4_CSFI6 4 @OMAP3430_SDMA_BASE+0x2E8 Channel Source Frame Index (Signed) or 16-bit Packet size
f OMAP3430_reg_DMA4_CDEI6 4 @OMAP3430_SDMA_BASE+0x2EC Channel Destination Element Index (Signed)
f OMAP3430_reg_DMA4_CDFI6 4 @OMAP3430_SDMA_BASE+0x2F0 Channel Destination Frame Index (Signed) or 16-bit Packet size
f OMAP3430_reg_DMA4_CSAC6 4 @OMAP3430_SDMA_BASE+0x2F4 Channel Source Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16-bit data may be corrupted
f OMAP3430_reg_DMA4_CDAC6 4 @OMAP3430_SDMA_BASE+0x2F8 Channel Destination Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16-bit data may be corrupted
f OMAP3430_reg_DMA4_CCEN6 4 @OMAP3430_SDMA_BASE+0x2FC Channel Current Transferred Element Number in the current frame. User has to access this register only in 32-bit access. If accessed in 8-bit or 16-bit data may be corrupted
f OMAP3430_reg_DMA4_CCFN6 4 @OMAP3430_SDMA_BASE+0x300 Channel Current Transferred Frame Number in the current transfer. User has to access this register only in 32-bit access. If accessed in 8-bit or 16-bit data may be corrupted
f OMAP3430_reg_DMA4_COLOR6 4 @OMAP3430_SDMA_BASE+0x304 Channel DMA COLOR KEY / SOLID COLOR
f OMAP3430_reg_DMA4_CCR7 4 @OMAP3430_SDMA_BASE+0x320 Channel Control Register
f OMAP3430_reg_DMA4_CLNK_CTRL7 4 @OMAP3430_SDMA_BASE+0x324 Channel Link Control Register
f OMAP3430_reg_DMA4_CICR7 4 @OMAP3430_SDMA_BASE+0x328 Channel Interrupt Control Register
f OMAP3430_reg_DMA4_CSR7 4 @OMAP3430_SDMA_BASE+0x32C Channel Status Register
f OMAP3430_reg_DMA4_CSDP7 4 @OMAP3430_SDMA_BASE+0x330 Channel Source Destination Parameters
f OMAP3430_reg_DMA4_CEN7 4 @OMAP3430_SDMA_BASE+0x334 Channel Element Number
f OMAP3430_reg_DMA4_CFN7 4 @OMAP3430_SDMA_BASE+0x338 Channel Frame Number
f OMAP3430_reg_DMA4_CSSA7 4 @OMAP3430_SDMA_BASE+0x33C Channel Source Start Address
f OMAP3430_reg_DMA4_CDSA7 4 @OMAP3430_SDMA_BASE+0x340 Channel Destination Start Address
f OMAP3430_reg_DMA4_CSEI7 4 @OMAP3430_SDMA_BASE+0x344 Channel Source Element Index (Signed)
f OMAP3430_reg_DMA4_CSFI7 4 @OMAP3430_SDMA_BASE+0x348 Channel Source Frame Index (Signed) or 16-bit Packet size
f OMAP3430_reg_DMA4_CDEI7 4 @OMAP3430_SDMA_BASE+0x34C Channel Destination Element Index (Signed)
f OMAP3430_reg_DMA4_CDFI7 4 @OMAP3430_SDMA_BASE+0x350 Channel Destination Frame Index (Signed) or 16-bit Packet size
f OMAP3430_reg_DMA4_CSAC7 4 @OMAP3430_SDMA_BASE+0x354 Channel Source Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16-bit data may be corrupted
f OMAP3430_reg_DMA4_CDAC7 4 @OMAP3430_SDMA_BASE+0x358 Channel Destination Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16-bit data may be corrupted
f OMAP3430_reg_DMA4_CCEN7 4 @OMAP3430_SDMA_BASE+0x35C Channel Current Transferred Element Number in the current frame. User has to access this register only in 32-bit access. If accessed in 8-bit or 16-bit data may be corrupted
f OMAP3430_reg_DMA4_CCFN7 4 @OMAP3430_SDMA_BASE+0x360 Channel Current Transferred Frame Number in the current transfer. User has to access this register only in 32-bit access. If accessed in 8-bit or 16-bit data may be corrupted
f OMAP3430_reg_DMA4_COLOR7 4 @OMAP3430_SDMA_BASE+0x364 Channel DMA COLOR KEY / SOLID COLOR
f OMAP3430_reg_DMA4_CCR8 4 @OMAP3430_SDMA_BASE+0x380 Channel Control Register
f OMAP3430_reg_DMA4_CLNK_CTRL8 4 @OMAP3430_SDMA_BASE+0x384 Channel Link Control Register
f OMAP3430_reg_DMA4_CICR8 4 @OMAP3430_SDMA_BASE+0x388 Channel Interrupt Control Register
f OMAP3430_reg_DMA4_CSR8 4 @OMAP3430_SDMA_BASE+0x38C Channel Status Register
f OMAP3430_reg_DMA4_CSDP8 4 @OMAP3430_SDMA_BASE+0x390 Channel Source Destination Parameters
f OMAP3430_reg_DMA4_CEN8 4 @OMAP3430_SDMA_BASE+0x394 Channel Element Number
f OMAP3430_reg_DMA4_CFN8 4 @OMAP3430_SDMA_BASE+0x398 Channel Frame Number
f OMAP3430_reg_DMA4_CSSA8 4 @OMAP3430_SDMA_BASE+0x39C Channel Source Start Address
f OMAP3430_reg_DMA4_CDSA8 4 @OMAP3430_SDMA_BASE+0x3A0 Channel Destination Start Address
f OMAP3430_reg_DMA4_CSEI8 4 @OMAP3430_SDMA_BASE+0x3A4 Channel Source Element Index (Signed)
f OMAP3430_reg_DMA4_CSFI8 4 @OMAP3430_SDMA_BASE+0x3A8 Channel Source Frame Index (Signed) or 16-bit Packet size
f OMAP3430_reg_DMA4_CDEI8 4 @OMAP3430_SDMA_BASE+0x3AC Channel Destination Element Index (Signed)
f OMAP3430_reg_DMA4_CDFI8 4 @OMAP3430_SDMA_BASE+0x3B0 Channel Destination Frame Index (Signed) or 16-bit Packet size
f OMAP3430_reg_DMA4_CSAC8 4 @OMAP3430_SDMA_BASE+0x3B4 Channel Source Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16-bit data may be corrupted
f OMAP3430_reg_DMA4_CDAC8 4 @OMAP3430_SDMA_BASE+0x3B8 Channel Destination Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16-bit data may be corrupted
f OMAP3430_reg_DMA4_CCEN8 4 @OMAP3430_SDMA_BASE+0x3BC Channel Current Transferred Element Number in the current frame. User has to access this register only in 32-bit access. If accessed in 8-bit or 16-bit data may be corrupted
f OMAP3430_reg_DMA4_CCFN8 4 @OMAP3430_SDMA_BASE+0x3C0 Channel Current Transferred Frame Number in the current transfer. User has to access this register only in 32-bit access. If accessed in 8-bit or 16-bit data may be corrupted
f OMAP3430_reg_DMA4_COLOR8 4 @OMAP3430_SDMA_BASE+0x3C4 Channel DMA COLOR KEY / SOLID COLOR
f OMAP3430_reg_DMA4_CCR9 4 @OMAP3430_SDMA_BASE+0x3E0 Channel Control Register
f OMAP3430_reg_DMA4_CLNK_CTRL9 4 @OMAP3430_SDMA_BASE+0x3E4 Channel Link Control Register
f OMAP3430_reg_DMA4_CICR9 4 @OMAP3430_SDMA_BASE+0x3E8 Channel Interrupt Control Register
f OMAP3430_reg_DMA4_CSR9 4 @OMAP3430_SDMA_BASE+0x3EC Channel Status Register
f OMAP3430_reg_DMA4_CSDP9 4 @OMAP3430_SDMA_BASE+0x3F0 Channel Source Destination Parameters
f OMAP3430_reg_DMA4_CEN9 4 @OMAP3430_SDMA_BASE+0x3F4 Channel Element Number
f OMAP3430_reg_DMA4_CFN9 4 @OMAP3430_SDMA_BASE+0x3F8 Channel Frame Number
f OMAP3430_reg_DMA4_CSSA9 4 @OMAP3430_SDMA_BASE+0x3FC Channel Source Start Address
f OMAP3430_reg_DMA4_CDSA9 4 @OMAP3430_SDMA_BASE+0x400 Channel Destination Start Address
f OMAP3430_reg_DMA4_CSEI9 4 @OMAP3430_SDMA_BASE+0x404 Channel Source Element Index (Signed)
f OMAP3430_reg_DMA4_CSFI9 4 @OMAP3430_SDMA_BASE+0x408 Channel Source Frame Index (Signed) or 16-bit Packet size
f OMAP3430_reg_DMA4_CDEI9 4 @OMAP3430_SDMA_BASE+0x40C Channel Destination Element Index (Signed)
f OMAP3430_reg_DMA4_CDFI9 4 @OMAP3430_SDMA_BASE+0x410 Channel Destination Frame Index (Signed) or 16-bit Packet size
f OMAP3430_reg_DMA4_CSAC9 4 @OMAP3430_SDMA_BASE+0x414 Channel Source Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16-bit data may be corrupted
f OMAP3430_reg_DMA4_CDAC9 4 @OMAP3430_SDMA_BASE+0x418 Channel Destination Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16-bit data may be corrupted
f OMAP3430_reg_DMA4_CCEN9 4 @OMAP3430_SDMA_BASE+0x41C Channel Current Transferred Element Number in the current frame. User has to access this register only in 32-bit access. If accessed in 8-bit or 16-bit data may be corrupted
f OMAP3430_reg_DMA4_CCFN9 4 @OMAP3430_SDMA_BASE+0x420 Channel Current Transferred Frame Number in the current transfer. User has to access this register only in 32-bit access. If accessed in 8-bit or 16-bit data may be corrupted
f OMAP3430_reg_DMA4_COLOR9 4 @OMAP3430_SDMA_BASE+0x424 Channel DMA COLOR KEY / SOLID COLOR
f OMAP3430_reg_DMA4_CCR10 4 @OMAP3430_SDMA_BASE+0x440 Channel Control Register
f OMAP3430_reg_DMA4_CLNK_CTRL10 4 @OMAP3430_SDMA_BASE+0x444 Channel Link Control Register
f OMAP3430_reg_DMA4_CICR10 4 @OMAP3430_SDMA_BASE+0x448 Channel Interrupt Control Register
f OMAP3430_reg_DMA4_CSR10 4 @OMAP3430_SDMA_BASE+0x44C Channel Status Register
f OMAP3430_reg_DMA4_CSDP10 4 @OMAP3430_SDMA_BASE+0x450 Channel Source Destination Parameters
f OMAP3430_reg_DMA4_CEN10 4 @OMAP3430_SDMA_BASE+0x454 Channel Element Number
f OMAP3430_reg_DMA4_CFN10 4 @OMAP3430_SDMA_BASE+0x458 Channel Frame Number
f OMAP3430_reg_DMA4_CSSA10 4 @OMAP3430_SDMA_BASE+0x45C Channel Source Start Address
f OMAP3430_reg_DMA4_CDSA10 4 @OMAP3430_SDMA_BASE+0x460 Channel Destination Start Address
f OMAP3430_reg_DMA4_CSEI10 4 @OMAP3430_SDMA_BASE+0x464 Channel Source Element Index (Signed)
f OMAP3430_reg_DMA4_CSFI10 4 @OMAP3430_SDMA_BASE+0x468 Channel Source Frame Index (Signed) or 16-bit Packet size
f OMAP3430_reg_DMA4_CDEI10 4 @OMAP3430_SDMA_BASE+0x46C Channel Destination Element Index (Signed)
f OMAP3430_reg_DMA4_CDFI10 4 @OMAP3430_SDMA_BASE+0x470 Channel Destination Frame Index (Signed) or 16-bit Packet size
f OMAP3430_reg_DMA4_CSAC10 4 @OMAP3430_SDMA_BASE+0x474 Channel Source Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16-bit data may be corrupted
f OMAP3430_reg_DMA4_CDAC10 4 @OMAP3430_SDMA_BASE+0x478 Channel Destination Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16-bit data may be corrupted
f OMAP3430_reg_DMA4_CCEN10 4 @OMAP3430_SDMA_BASE+0x47C Channel Current Transferred Element Number in the current frame. User has to access this register only in 32-bit access. If accessed in 8-bit or 16-bit data may be corrupted
f OMAP3430_reg_DMA4_CCFN10 4 @OMAP3430_SDMA_BASE+0x480 Channel Current Transferred Frame Number in the current transfer. User has to access this register only in 32-bit access. If accessed in 8-bit or 16-bit data may be corrupted
f OMAP3430_reg_DMA4_COLOR10 4 @OMAP3430_SDMA_BASE+0x484 Channel DMA COLOR KEY / SOLID COLOR
f OMAP3430_reg_DMA4_CCR11 4 @OMAP3430_SDMA_BASE+0x4A0 Channel Control Register
f OMAP3430_reg_DMA4_CLNK_CTRL11 4 @OMAP3430_SDMA_BASE+0x4A4 Channel Link Control Register
f OMAP3430_reg_DMA4_CICR11 4 @OMAP3430_SDMA_BASE+0x4A8 Channel Interrupt Control Register
f OMAP3430_reg_DMA4_CSR11 4 @OMAP3430_SDMA_BASE+0x4AC Channel Status Register
f OMAP3430_reg_DMA4_CSDP11 4 @OMAP3430_SDMA_BASE+0x4B0 Channel Source Destination Parameters
f OMAP3430_reg_DMA4_CEN11 4 @OMAP3430_SDMA_BASE+0x4B4 Channel Element Number
f OMAP3430_reg_DMA4_CFN11 4 @OMAP3430_SDMA_BASE+0x4B8 Channel Frame Number
f OMAP3430_reg_DMA4_CSSA11 4 @OMAP3430_SDMA_BASE+0x4BC Channel Source Start Address
f OMAP3430_reg_DMA4_CDSA11 4 @OMAP3430_SDMA_BASE+0x4C0 Channel Destination Start Address
f OMAP3430_reg_DMA4_CSEI11 4 @OMAP3430_SDMA_BASE+0x4C4 Channel Source Element Index (Signed)
f OMAP3430_reg_DMA4_CSFI11 4 @OMAP3430_SDMA_BASE+0x4C8 Channel Source Frame Index (Signed) or 16-bit Packet size
f OMAP3430_reg_DMA4_CDEI11 4 @OMAP3430_SDMA_BASE+0x4CC Channel Destination Element Index (Signed)
f OMAP3430_reg_DMA4_CDFI11 4 @OMAP3430_SDMA_BASE+0x4D0 Channel Destination Frame Index (Signed) or 16-bit Packet size
f OMAP3430_reg_DMA4_CSAC11 4 @OMAP3430_SDMA_BASE+0x4D4 Channel Source Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16-bit data may be corrupted
f OMAP3430_reg_DMA4_CDAC11 4 @OMAP3430_SDMA_BASE+0x4D8 Channel Destination Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16-bit data may be corrupted
f OMAP3430_reg_DMA4_CCEN11 4 @OMAP3430_SDMA_BASE+0x4DC Channel Current Transferred Element Number in the current frame. User has to access this register only in 32-bit access. If accessed in 8-bit or 16-bit data may be corrupted
f OMAP3430_reg_DMA4_CCFN11 4 @OMAP3430_SDMA_BASE+0x4E0 Channel Current Transferred Frame Number in the current transfer. User has to access this register only in 32-bit access. If accessed in 8-bit or 16-bit data may be corrupted
f OMAP3430_reg_DMA4_COLOR11 4 @OMAP3430_SDMA_BASE+0x4E4 Channel DMA COLOR KEY / SOLID COLOR
f OMAP3430_reg_DMA4_CCR12 4 @OMAP3430_SDMA_BASE+0x500 Channel Control Register
f OMAP3430_reg_DMA4_CLNK_CTRL12 4 @OMAP3430_SDMA_BASE+0x504 Channel Link Control Register
f OMAP3430_reg_DMA4_CICR12 4 @OMAP3430_SDMA_BASE+0x508 Channel Interrupt Control Register
f OMAP3430_reg_DMA4_CSR12 4 @OMAP3430_SDMA_BASE+0x50C Channel Status Register
f OMAP3430_reg_DMA4_CSDP12 4 @OMAP3430_SDMA_BASE+0x510 Channel Source Destination Parameters
f OMAP3430_reg_DMA4_CEN12 4 @OMAP3430_SDMA_BASE+0x514 Channel Element Number
f OMAP3430_reg_DMA4_CFN12 4 @OMAP3430_SDMA_BASE+0x518 Channel Frame Number
f OMAP3430_reg_DMA4_CSSA12 4 @OMAP3430_SDMA_BASE+0x51C Channel Source Start Address
f OMAP3430_reg_DMA4_CDSA12 4 @OMAP3430_SDMA_BASE+0x520 Channel Destination Start Address
f OMAP3430_reg_DMA4_CSEI12 4 @OMAP3430_SDMA_BASE+0x524 Channel Source Element Index (Signed)
f OMAP3430_reg_DMA4_CSFI12 4 @OMAP3430_SDMA_BASE+0x528 Channel Source Frame Index (Signed) or 16-bit Packet size
f OMAP3430_reg_DMA4_CDEI12 4 @OMAP3430_SDMA_BASE+0x52C Channel Destination Element Index (Signed)
f OMAP3430_reg_DMA4_CDFI12 4 @OMAP3430_SDMA_BASE+0x530 Channel Destination Frame Index (Signed) or 16-bit Packet size
f OMAP3430_reg_DMA4_CSAC12 4 @OMAP3430_SDMA_BASE+0x534 Channel Source Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16-bit data may be corrupted
f OMAP3430_reg_DMA4_CDAC12 4 @OMAP3430_SDMA_BASE+0x538 Channel Destination Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16-bit data may be corrupted
f OMAP3430_reg_DMA4_CCEN12 4 @OMAP3430_SDMA_BASE+0x53C Channel Current Transferred Element Number in the current frame. User has to access this register only in 32-bit access. If accessed in 8-bit or 16-bit data may be corrupted
f OMAP3430_reg_DMA4_CCFN12 4 @OMAP3430_SDMA_BASE+0x540 Channel Current Transferred Frame Number in the current transfer. User has to access this register only in 32-bit access. If accessed in 8-bit or 16-bit data may be corrupted
f OMAP3430_reg_DMA4_COLOR12 4 @OMAP3430_SDMA_BASE+0x544 Channel DMA COLOR KEY / SOLID COLOR
f OMAP3430_reg_DMA4_CCR13 4 @OMAP3430_SDMA_BASE+0x560 Channel Control Register
f OMAP3430_reg_DMA4_CLNK_CTRL13 4 @OMAP3430_SDMA_BASE+0x564 Channel Link Control Register
f OMAP3430_reg_DMA4_CICR13 4 @OMAP3430_SDMA_BASE+0x568 Channel Interrupt Control Register
f OMAP3430_reg_DMA4_CSR13 4 @OMAP3430_SDMA_BASE+0x56C Channel Status Register
f OMAP3430_reg_DMA4_CSDP13 4 @OMAP3430_SDMA_BASE+0x570 Channel Source Destination Parameters
f OMAP3430_reg_DMA4_CEN13 4 @OMAP3430_SDMA_BASE+0x574 Channel Element Number
f OMAP3430_reg_DMA4_CFN13 4 @OMAP3430_SDMA_BASE+0x578 Channel Frame Number
f OMAP3430_reg_DMA4_CSSA13 4 @OMAP3430_SDMA_BASE+0x57C Channel Source Start Address
f OMAP3430_reg_DMA4_CDSA13 4 @OMAP3430_SDMA_BASE+0x580 Channel Destination Start Address
f OMAP3430_reg_DMA4_CSEI13 4 @OMAP3430_SDMA_BASE+0x584 Channel Source Element Index (Signed)
f OMAP3430_reg_DMA4_CSFI13 4 @OMAP3430_SDMA_BASE+0x588 Channel Source Frame Index (Signed) or 16-bit Packet size
f OMAP3430_reg_DMA4_CDEI13 4 @OMAP3430_SDMA_BASE+0x58C Channel Destination Element Index (Signed)
f OMAP3430_reg_DMA4_CDFI13 4 @OMAP3430_SDMA_BASE+0x590 Channel Destination Frame Index (Signed) or 16-bit Packet size
f OMAP3430_reg_DMA4_CSAC13 4 @OMAP3430_SDMA_BASE+0x594 Channel Source Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16-bit data may be corrupted
f OMAP3430_reg_DMA4_CDAC13 4 @OMAP3430_SDMA_BASE+0x598 Channel Destination Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16-bit data may be corrupted
f OMAP3430_reg_DMA4_CCEN13 4 @OMAP3430_SDMA_BASE+0x59C Channel Current Transferred Element Number in the current frame. User has to access this register only in 32-bit access. If accessed in 8-bit or 16-bit data may be corrupted
f OMAP3430_reg_DMA4_CCFN13 4 @OMAP3430_SDMA_BASE+0x5A0 Channel Current Transferred Frame Number in the current transfer. User has to access this register only in 32-bit access. If accessed in 8-bit or 16-bit data may be corrupted
f OMAP3430_reg_DMA4_COLOR13 4 @OMAP3430_SDMA_BASE+0x5A4 Channel DMA COLOR KEY / SOLID COLOR
f OMAP3430_reg_DMA4_CCR14 4 @OMAP3430_SDMA_BASE+0x5C0 Channel Control Register
f OMAP3430_reg_DMA4_CLNK_CTRL14 4 @OMAP3430_SDMA_BASE+0x5C4 Channel Link Control Register
f OMAP3430_reg_DMA4_CICR14 4 @OMAP3430_SDMA_BASE+0x5C8 Channel Interrupt Control Register
f OMAP3430_reg_DMA4_CSR14 4 @OMAP3430_SDMA_BASE+0x5CC Channel Status Register
f OMAP3430_reg_DMA4_CSDP14 4 @OMAP3430_SDMA_BASE+0x5D0 Channel Source Destination Parameters
f OMAP3430_reg_DMA4_CEN14 4 @OMAP3430_SDMA_BASE+0x5D4 Channel Element Number
f OMAP3430_reg_DMA4_CFN14 4 @OMAP3430_SDMA_BASE+0x5D8 Channel Frame Number
f OMAP3430_reg_DMA4_CSSA14 4 @OMAP3430_SDMA_BASE+0x5DC Channel Source Start Address
f OMAP3430_reg_DMA4_CDSA14 4 @OMAP3430_SDMA_BASE+0x5E0 Channel Destination Start Address
f OMAP3430_reg_DMA4_CSEI14 4 @OMAP3430_SDMA_BASE+0x5E4 Channel Source Element Index (Signed)
f OMAP3430_reg_DMA4_CSFI14 4 @OMAP3430_SDMA_BASE+0x5E8 Channel Source Frame Index (Signed) or 16-bit Packet size
f OMAP3430_reg_DMA4_CDEI14 4 @OMAP3430_SDMA_BASE+0x5EC Channel Destination Element Index (Signed)
f OMAP3430_reg_DMA4_CDFI14 4 @OMAP3430_SDMA_BASE+0x5F0 Channel Destination Frame Index (Signed) or 16-bit Packet size
f OMAP3430_reg_DMA4_CSAC14 4 @OMAP3430_SDMA_BASE+0x5F4 Channel Source Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16-bit data may be corrupted
f OMAP3430_reg_DMA4_CDAC14 4 @OMAP3430_SDMA_BASE+0x5F8 Channel Destination Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16-bit data may be corrupted
f OMAP3430_reg_DMA4_CCEN14 4 @OMAP3430_SDMA_BASE+0x5FC Channel Current Transferred Element Number in the current frame. User has to access this register only in 32-bit access. If accessed in 8-bit or 16-bit data may be corrupted
f OMAP3430_reg_DMA4_CCFN14 4 @OMAP3430_SDMA_BASE+0x600 Channel Current Transferred Frame Number in the current transfer. User has to access this register only in 32-bit access. If accessed in 8-bit or 16-bit data may be corrupted
f OMAP3430_reg_DMA4_COLOR14 4 @OMAP3430_SDMA_BASE+0x604 Channel DMA COLOR KEY / SOLID COLOR
f OMAP3430_reg_DMA4_CCR15 4 @OMAP3430_SDMA_BASE+0x620 Channel Control Register
f OMAP3430_reg_DMA4_CLNK_CTRL15 4 @OMAP3430_SDMA_BASE+0x624 Channel Link Control Register
f OMAP3430_reg_DMA4_CICR15 4 @OMAP3430_SDMA_BASE+0x628 Channel Interrupt Control Register
f OMAP3430_reg_DMA4_CSR15 4 @OMAP3430_SDMA_BASE+0x62C Channel Status Register
f OMAP3430_reg_DMA4_CSDP15 4 @OMAP3430_SDMA_BASE+0x630 Channel Source Destination Parameters
f OMAP3430_reg_DMA4_CEN15 4 @OMAP3430_SDMA_BASE+0x634 Channel Element Number
f OMAP3430_reg_DMA4_CFN15 4 @OMAP3430_SDMA_BASE+0x638 Channel Frame Number
f OMAP3430_reg_DMA4_CSSA15 4 @OMAP3430_SDMA_BASE+0x63C Channel Source Start Address
f OMAP3430_reg_DMA4_CDSA15 4 @OMAP3430_SDMA_BASE+0x640 Channel Destination Start Address
f OMAP3430_reg_DMA4_CSEI15 4 @OMAP3430_SDMA_BASE+0x644 Channel Source Element Index (Signed)
f OMAP3430_reg_DMA4_CSFI15 4 @OMAP3430_SDMA_BASE+0x648 Channel Source Frame Index (Signed) or 16-bit Packet size
f OMAP3430_reg_DMA4_CDEI15 4 @OMAP3430_SDMA_BASE+0x64C Channel Destination Element Index (Signed)
f OMAP3430_reg_DMA4_CDFI15 4 @OMAP3430_SDMA_BASE+0x650 Channel Destination Frame Index (Signed) or 16-bit Packet size
f OMAP3430_reg_DMA4_CSAC15 4 @OMAP3430_SDMA_BASE+0x654 Channel Source Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16-bit data may be corrupted
f OMAP3430_reg_DMA4_CDAC15 4 @OMAP3430_SDMA_BASE+0x658 Channel Destination Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16-bit data may be corrupted
f OMAP3430_reg_DMA4_CCEN15 4 @OMAP3430_SDMA_BASE+0x65C Channel Current Transferred Element Number in the current frame. User has to access this register only in 32-bit access. If accessed in 8-bit or 16-bit data may be corrupted
f OMAP3430_reg_DMA4_CCFN15 4 @OMAP3430_SDMA_BASE+0x660 Channel Current Transferred Frame Number in the current transfer. User has to access this register only in 32-bit access. If accessed in 8-bit or 16-bit data may be corrupted
f OMAP3430_reg_DMA4_COLOR15 4 @OMAP3430_SDMA_BASE+0x664 Channel DMA COLOR KEY / SOLID COLOR
f OMAP3430_reg_DMA4_CCR16 4 @OMAP3430_SDMA_BASE+0x680 Channel Control Register
f OMAP3430_reg_DMA4_CLNK_CTRL16 4 @OMAP3430_SDMA_BASE+0x684 Channel Link Control Register
f OMAP3430_reg_DMA4_CICR16 4 @OMAP3430_SDMA_BASE+0x688 Channel Interrupt Control Register
f OMAP3430_reg_DMA4_CSR16 4 @OMAP3430_SDMA_BASE+0x68C Channel Status Register
f OMAP3430_reg_DMA4_CSDP16 4 @OMAP3430_SDMA_BASE+0x690 Channel Source Destination Parameters
f OMAP3430_reg_DMA4_CEN16 4 @OMAP3430_SDMA_BASE+0x694 Channel Element Number
f OMAP3430_reg_DMA4_CFN16 4 @OMAP3430_SDMA_BASE+0x698 Channel Frame Number
f OMAP3430_reg_DMA4_CSSA16 4 @OMAP3430_SDMA_BASE+0x69C Channel Source Start Address
f OMAP3430_reg_DMA4_CDSA16 4 @OMAP3430_SDMA_BASE+0x6A0 Channel Destination Start Address
f OMAP3430_reg_DMA4_CSEI16 4 @OMAP3430_SDMA_BASE+0x6A4 Channel Source Element Index (Signed)
f OMAP3430_reg_DMA4_CSFI16 4 @OMAP3430_SDMA_BASE+0x6A8 Channel Source Frame Index (Signed) or 16-bit Packet size
f OMAP3430_reg_DMA4_CDEI16 4 @OMAP3430_SDMA_BASE+0x6AC Channel Destination Element Index (Signed)
f OMAP3430_reg_DMA4_CDFI16 4 @OMAP3430_SDMA_BASE+0x6B0 Channel Destination Frame Index (Signed) or 16-bit Packet size
f OMAP3430_reg_DMA4_CSAC16 4 @OMAP3430_SDMA_BASE+0x6B4 Channel Source Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16-bit data may be corrupted
f OMAP3430_reg_DMA4_CDAC16 4 @OMAP3430_SDMA_BASE+0x6B8 Channel Destination Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16-bit data may be corrupted
f OMAP3430_reg_DMA4_CCEN16 4 @OMAP3430_SDMA_BASE+0x6BC Channel Current Transferred Element Number in the current frame. User has to access this register only in 32-bit access. If accessed in 8-bit or 16-bit data may be corrupted
f OMAP3430_reg_DMA4_CCFN16 4 @OMAP3430_SDMA_BASE+0x6C0 Channel Current Transferred Frame Number in the current transfer. User has to access this register only in 32-bit access. If accessed in 8-bit or 16-bit data may be corrupted
f OMAP3430_reg_DMA4_COLOR16 4 @OMAP3430_SDMA_BASE+0x6C4 Channel DMA COLOR KEY / SOLID COLOR
f OMAP3430_reg_DMA4_CCR17 4 @OMAP3430_SDMA_BASE+0x6E0 Channel Control Register
f OMAP3430_reg_DMA4_CLNK_CTRL17 4 @OMAP3430_SDMA_BASE+0x6E4 Channel Link Control Register
f OMAP3430_reg_DMA4_CICR17 4 @OMAP3430_SDMA_BASE+0x6E8 Channel Interrupt Control Register
f OMAP3430_reg_DMA4_CSR17 4 @OMAP3430_SDMA_BASE+0x6EC Channel Status Register
f OMAP3430_reg_DMA4_CSDP17 4 @OMAP3430_SDMA_BASE+0x6F0 Channel Source Destination Parameters
f OMAP3430_reg_DMA4_CEN17 4 @OMAP3430_SDMA_BASE+0x6F4 Channel Element Number
f OMAP3430_reg_DMA4_CFN17 4 @OMAP3430_SDMA_BASE+0x6F8 Channel Frame Number
f OMAP3430_reg_DMA4_CSSA17 4 @OMAP3430_SDMA_BASE+0x6FC Channel Source Start Address
f OMAP3430_reg_DMA4_CDSA17 4 @OMAP3430_SDMA_BASE+0x700 Channel Destination Start Address
f OMAP3430_reg_DMA4_CSEI17 4 @OMAP3430_SDMA_BASE+0x704 Channel Source Element Index (Signed)
f OMAP3430_reg_DMA4_CSFI17 4 @OMAP3430_SDMA_BASE+0x708 Channel Source Frame Index (Signed) or 16-bit Packet size
f OMAP3430_reg_DMA4_CDEI17 4 @OMAP3430_SDMA_BASE+0x70C Channel Destination Element Index (Signed)
f OMAP3430_reg_DMA4_CDFI17 4 @OMAP3430_SDMA_BASE+0x710 Channel Destination Frame Index (Signed) or 16-bit Packet size
f OMAP3430_reg_DMA4_CSAC17 4 @OMAP3430_SDMA_BASE+0x714 Channel Source Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16-bit data may be corrupted
f OMAP3430_reg_DMA4_CDAC17 4 @OMAP3430_SDMA_BASE+0x718 Channel Destination Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16-bit data may be corrupted
f OMAP3430_reg_DMA4_CCEN17 4 @OMAP3430_SDMA_BASE+0x71C Channel Current Transferred Element Number in the current frame. User has to access this register only in 32-bit access. If accessed in 8-bit or 16-bit data may be corrupted
f OMAP3430_reg_DMA4_CCFN17 4 @OMAP3430_SDMA_BASE+0x720 Channel Current Transferred Frame Number in the current transfer. User has to access this register only in 32-bit access. If accessed in 8-bit or 16-bit data may be corrupted
f OMAP3430_reg_DMA4_COLOR17 4 @OMAP3430_SDMA_BASE+0x724 Channel DMA COLOR KEY / SOLID COLOR
f OMAP3430_reg_DMA4_CCR18 4 @OMAP3430_SDMA_BASE+0x740 Channel Control Register
f OMAP3430_reg_DMA4_CLNK_CTRL18 4 @OMAP3430_SDMA_BASE+0x744 Channel Link Control Register
f OMAP3430_reg_DMA4_CICR18 4 @OMAP3430_SDMA_BASE+0x748 Channel Interrupt Control Register
f OMAP3430_reg_DMA4_CSR18 4 @OMAP3430_SDMA_BASE+0x74C Channel Status Register
f OMAP3430_reg_DMA4_CSDP18 4 @OMAP3430_SDMA_BASE+0x750 Channel Source Destination Parameters
f OMAP3430_reg_DMA4_CEN18 4 @OMAP3430_SDMA_BASE+0x754 Channel Element Number
f OMAP3430_reg_DMA4_CFN18 4 @OMAP3430_SDMA_BASE+0x758 Channel Frame Number
f OMAP3430_reg_DMA4_CSSA18 4 @OMAP3430_SDMA_BASE+0x75C Channel Source Start Address
f OMAP3430_reg_DMA4_CDSA18 4 @OMAP3430_SDMA_BASE+0x760 Channel Destination Start Address
f OMAP3430_reg_DMA4_CSEI18 4 @OMAP3430_SDMA_BASE+0x764 Channel Source Element Index (Signed)
f OMAP3430_reg_DMA4_CSFI18 4 @OMAP3430_SDMA_BASE+0x768 Channel Source Frame Index (Signed) or 16-bit Packet size
f OMAP3430_reg_DMA4_CDEI18 4 @OMAP3430_SDMA_BASE+0x76C Channel Destination Element Index (Signed)
f OMAP3430_reg_DMA4_CDFI18 4 @OMAP3430_SDMA_BASE+0x770 Channel Destination Frame Index (Signed) or 16-bit Packet size
f OMAP3430_reg_DMA4_CSAC18 4 @OMAP3430_SDMA_BASE+0x774 Channel Source Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16-bit data may be corrupted
f OMAP3430_reg_DMA4_CDAC18 4 @OMAP3430_SDMA_BASE+0x778 Channel Destination Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16-bit data may be corrupted
f OMAP3430_reg_DMA4_CCEN18 4 @OMAP3430_SDMA_BASE+0x77C Channel Current Transferred Element Number in the current frame. User has to access this register only in 32-bit access. If accessed in 8-bit or 16-bit data may be corrupted
f OMAP3430_reg_DMA4_CCFN18 4 @OMAP3430_SDMA_BASE+0x780 Channel Current Transferred Frame Number in the current transfer. User has to access this register only in 32-bit access. If accessed in 8-bit or 16-bit data may be corrupted
f OMAP3430_reg_DMA4_COLOR18 4 @OMAP3430_SDMA_BASE+0x784 Channel DMA COLOR KEY / SOLID COLOR
f OMAP3430_reg_DMA4_CCR19 4 @OMAP3430_SDMA_BASE+0x7A0 Channel Control Register
f OMAP3430_reg_DMA4_CLNK_CTRL19 4 @OMAP3430_SDMA_BASE+0x7A4 Channel Link Control Register
f OMAP3430_reg_DMA4_CICR19 4 @OMAP3430_SDMA_BASE+0x7A8 Channel Interrupt Control Register
f OMAP3430_reg_DMA4_CSR19 4 @OMAP3430_SDMA_BASE+0x7AC Channel Status Register
f OMAP3430_reg_DMA4_CSDP19 4 @OMAP3430_SDMA_BASE+0x7B0 Channel Source Destination Parameters
f OMAP3430_reg_DMA4_CEN19 4 @OMAP3430_SDMA_BASE+0x7B4 Channel Element Number
f OMAP3430_reg_DMA4_CFN19 4 @OMAP3430_SDMA_BASE+0x7B8 Channel Frame Number
f OMAP3430_reg_DMA4_CSSA19 4 @OMAP3430_SDMA_BASE+0x7BC Channel Source Start Address
f OMAP3430_reg_DMA4_CDSA19 4 @OMAP3430_SDMA_BASE+0x7C0 Channel Destination Start Address
f OMAP3430_reg_DMA4_CSEI19 4 @OMAP3430_SDMA_BASE+0x7C4 Channel Source Element Index (Signed)
f OMAP3430_reg_DMA4_CSFI19 4 @OMAP3430_SDMA_BASE+0x7C8 Channel Source Frame Index (Signed) or 16-bit Packet size
f OMAP3430_reg_DMA4_CDEI19 4 @OMAP3430_SDMA_BASE+0x7CC Channel Destination Element Index (Signed)
f OMAP3430_reg_DMA4_CDFI19 4 @OMAP3430_SDMA_BASE+0x7D0 Channel Destination Frame Index (Signed) or 16-bit Packet size
f OMAP3430_reg_DMA4_CSAC19 4 @OMAP3430_SDMA_BASE+0x7D4 Channel Source Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16-bit data may be corrupted
f OMAP3430_reg_DMA4_CDAC19 4 @OMAP3430_SDMA_BASE+0x7D8 Channel Destination Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16-bit data may be corrupted
f OMAP3430_reg_DMA4_CCEN19 4 @OMAP3430_SDMA_BASE+0x7DC Channel Current Transferred Element Number in the current frame. User has to access this register only in 32-bit access. If accessed in 8-bit or 16-bit data may be corrupted
f OMAP3430_reg_DMA4_CCFN19 4 @OMAP3430_SDMA_BASE+0x7E0 Channel Current Transferred Frame Number in the current transfer. User has to access this register only in 32-bit access. If accessed in 8-bit or 16-bit data may be corrupted
f OMAP3430_reg_DMA4_COLOR19 4 @OMAP3430_SDMA_BASE+0x7E4 Channel DMA COLOR KEY / SOLID COLOR
f OMAP3430_reg_DMA4_CCR20 4 @OMAP3430_SDMA_BASE+0x800 Channel Control Register
f OMAP3430_reg_DMA4_CLNK_CTRL20 4 @OMAP3430_SDMA_BASE+0x804 Channel Link Control Register
f OMAP3430_reg_DMA4_CICR20 4 @OMAP3430_SDMA_BASE+0x808 Channel Interrupt Control Register
f OMAP3430_reg_DMA4_CSR20 4 @OMAP3430_SDMA_BASE+0x80C Channel Status Register
f OMAP3430_reg_DMA4_CSDP20 4 @OMAP3430_SDMA_BASE+0x810 Channel Source Destination Parameters
f OMAP3430_reg_DMA4_CEN20 4 @OMAP3430_SDMA_BASE+0x814 Channel Element Number
f OMAP3430_reg_DMA4_CFN20 4 @OMAP3430_SDMA_BASE+0x818 Channel Frame Number
f OMAP3430_reg_DMA4_CSSA20 4 @OMAP3430_SDMA_BASE+0x81C Channel Source Start Address
f OMAP3430_reg_DMA4_CDSA20 4 @OMAP3430_SDMA_BASE+0x820 Channel Destination Start Address
f OMAP3430_reg_DMA4_CSEI20 4 @OMAP3430_SDMA_BASE+0x824 Channel Source Element Index (Signed)
f OMAP3430_reg_DMA4_CSFI20 4 @OMAP3430_SDMA_BASE+0x828 Channel Source Frame Index (Signed) or 16-bit Packet size
f OMAP3430_reg_DMA4_CDEI20 4 @OMAP3430_SDMA_BASE+0x82C Channel Destination Element Index (Signed)
f OMAP3430_reg_DMA4_CDFI20 4 @OMAP3430_SDMA_BASE+0x830 Channel Destination Frame Index (Signed) or 16-bit Packet size
f OMAP3430_reg_DMA4_CSAC20 4 @OMAP3430_SDMA_BASE+0x834 Channel Source Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16-bit data may be corrupted
f OMAP3430_reg_DMA4_CDAC20 4 @OMAP3430_SDMA_BASE+0x838 Channel Destination Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16-bit data may be corrupted
f OMAP3430_reg_DMA4_CCEN20 4 @OMAP3430_SDMA_BASE+0x83C Channel Current Transferred Element Number in the current frame. User has to access this register only in 32-bit access. If accessed in 8-bit or 16-bit data may be corrupted
f OMAP3430_reg_DMA4_CCFN20 4 @OMAP3430_SDMA_BASE+0x840 Channel Current Transferred Frame Number in the current transfer. User has to access this register only in 32-bit access. If accessed in 8-bit or 16-bit data may be corrupted
f OMAP3430_reg_DMA4_COLOR20 4 @OMAP3430_SDMA_BASE+0x844 Channel DMA COLOR KEY / SOLID COLOR
f OMAP3430_reg_DMA4_CCR21 4 @OMAP3430_SDMA_BASE+0x860 Channel Control Register
f OMAP3430_reg_DMA4_CLNK_CTRL21 4 @OMAP3430_SDMA_BASE+0x864 Channel Link Control Register
f OMAP3430_reg_DMA4_CICR21 4 @OMAP3430_SDMA_BASE+0x868 Channel Interrupt Control Register
f OMAP3430_reg_DMA4_CSR21 4 @OMAP3430_SDMA_BASE+0x86C Channel Status Register
f OMAP3430_reg_DMA4_CSDP21 4 @OMAP3430_SDMA_BASE+0x870 Channel Source Destination Parameters
f OMAP3430_reg_DMA4_CEN21 4 @OMAP3430_SDMA_BASE+0x874 Channel Element Number
f OMAP3430_reg_DMA4_CFN21 4 @OMAP3430_SDMA_BASE+0x878 Channel Frame Number
f OMAP3430_reg_DMA4_CSSA21 4 @OMAP3430_SDMA_BASE+0x87C Channel Source Start Address
f OMAP3430_reg_DMA4_CDSA21 4 @OMAP3430_SDMA_BASE+0x880 Channel Destination Start Address
f OMAP3430_reg_DMA4_CSEI21 4 @OMAP3430_SDMA_BASE+0x884 Channel Source Element Index (Signed)
f OMAP3430_reg_DMA4_CSFI21 4 @OMAP3430_SDMA_BASE+0x888 Channel Source Frame Index (Signed) or 16-bit Packet size
f OMAP3430_reg_DMA4_CDEI21 4 @OMAP3430_SDMA_BASE+0x88C Channel Destination Element Index (Signed)
f OMAP3430_reg_DMA4_CDFI21 4 @OMAP3430_SDMA_BASE+0x890 Channel Destination Frame Index (Signed) or 16-bit Packet size
f OMAP3430_reg_DMA4_CSAC21 4 @OMAP3430_SDMA_BASE+0x894 Channel Source Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16-bit data may be corrupted
f OMAP3430_reg_DMA4_CDAC21 4 @OMAP3430_SDMA_BASE+0x898 Channel Destination Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16-bit data may be corrupted
f OMAP3430_reg_DMA4_CCEN21 4 @OMAP3430_SDMA_BASE+0x89C Channel Current Transferred Element Number in the current frame. User has to access this register only in 32-bit access. If accessed in 8-bit or 16-bit data may be corrupted
f OMAP3430_reg_DMA4_CCFN21 4 @OMAP3430_SDMA_BASE+0x8A0 Channel Current Transferred Frame Number in the current transfer. User has to access this register only in 32-bit access. If accessed in 8-bit or 16-bit data may be corrupted
f OMAP3430_reg_DMA4_COLOR21 4 @OMAP3430_SDMA_BASE+0x8A4 Channel DMA COLOR KEY / SOLID COLOR
f OMAP3430_reg_DMA4_CCR22 4 @OMAP3430_SDMA_BASE+0x8C0 Channel Control Register
f OMAP3430_reg_DMA4_CLNK_CTRL22 4 @OMAP3430_SDMA_BASE+0x8C4 Channel Link Control Register
f OMAP3430_reg_DMA4_CICR22 4 @OMAP3430_SDMA_BASE+0x8C8 Channel Interrupt Control Register
f OMAP3430_reg_DMA4_CSR22 4 @OMAP3430_SDMA_BASE+0x8CC Channel Status Register
f OMAP3430_reg_DMA4_CSDP22 4 @OMAP3430_SDMA_BASE+0x8D0 Channel Source Destination Parameters
f OMAP3430_reg_DMA4_CEN22 4 @OMAP3430_SDMA_BASE+0x8D4 Channel Element Number
f OMAP3430_reg_DMA4_CFN22 4 @OMAP3430_SDMA_BASE+0x8D8 Channel Frame Number
f OMAP3430_reg_DMA4_CSSA22 4 @OMAP3430_SDMA_BASE+0x8DC Channel Source Start Address
f OMAP3430_reg_DMA4_CDSA22 4 @OMAP3430_SDMA_BASE+0x8E0 Channel Destination Start Address
f OMAP3430_reg_DMA4_CSEI22 4 @OMAP3430_SDMA_BASE+0x8E4 Channel Source Element Index (Signed)
f OMAP3430_reg_DMA4_CSFI22 4 @OMAP3430_SDMA_BASE+0x8E8 Channel Source Frame Index (Signed) or 16-bit Packet size
f OMAP3430_reg_DMA4_CDEI22 4 @OMAP3430_SDMA_BASE+0x8EC Channel Destination Element Index (Signed)
f OMAP3430_reg_DMA4_CDFI22 4 @OMAP3430_SDMA_BASE+0x8F0 Channel Destination Frame Index (Signed) or 16-bit Packet size
f OMAP3430_reg_DMA4_CSAC22 4 @OMAP3430_SDMA_BASE+0x8F4 Channel Source Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16-bit data may be corrupted
f OMAP3430_reg_DMA4_CDAC22 4 @OMAP3430_SDMA_BASE+0x8F8 Channel Destination Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16-bit data may be corrupted
f OMAP3430_reg_DMA4_CCEN22 4 @OMAP3430_SDMA_BASE+0x8FC Channel Current Transferred Element Number in the current frame. User has to access this register only in 32-bit access. If accessed in 8-bit or 16-bit data may be corrupted
f OMAP3430_reg_DMA4_CCFN22 4 @OMAP3430_SDMA_BASE+0x900 Channel Current Transferred Frame Number in the current transfer. User has to access this register only in 32-bit access. If accessed in 8-bit or 16-bit data may be corrupted
f OMAP3430_reg_DMA4_COLOR22 4 @OMAP3430_SDMA_BASE+0x904 Channel DMA COLOR KEY / SOLID COLOR
f OMAP3430_reg_DMA4_CCR23 4 @OMAP3430_SDMA_BASE+0x920 Channel Control Register
f OMAP3430_reg_DMA4_CLNK_CTRL23 4 @OMAP3430_SDMA_BASE+0x924 Channel Link Control Register
f OMAP3430_reg_DMA4_CICR23 4 @OMAP3430_SDMA_BASE+0x928 Channel Interrupt Control Register
f OMAP3430_reg_DMA4_CSR23 4 @OMAP3430_SDMA_BASE+0x92C Channel Status Register
f OMAP3430_reg_DMA4_CSDP23 4 @OMAP3430_SDMA_BASE+0x930 Channel Source Destination Parameters
f OMAP3430_reg_DMA4_CEN23 4 @OMAP3430_SDMA_BASE+0x934 Channel Element Number
f OMAP3430_reg_DMA4_CFN23 4 @OMAP3430_SDMA_BASE+0x938 Channel Frame Number
f OMAP3430_reg_DMA4_CSSA23 4 @OMAP3430_SDMA_BASE+0x93C Channel Source Start Address
f OMAP3430_reg_DMA4_CDSA23 4 @OMAP3430_SDMA_BASE+0x940 Channel Destination Start Address
f OMAP3430_reg_DMA4_CSEI23 4 @OMAP3430_SDMA_BASE+0x944 Channel Source Element Index (Signed)
f OMAP3430_reg_DMA4_CSFI23 4 @OMAP3430_SDMA_BASE+0x948 Channel Source Frame Index (Signed) or 16-bit Packet size
f OMAP3430_reg_DMA4_CDEI23 4 @OMAP3430_SDMA_BASE+0x94C Channel Destination Element Index (Signed)
f OMAP3430_reg_DMA4_CDFI23 4 @OMAP3430_SDMA_BASE+0x950 Channel Destination Frame Index (Signed) or 16-bit Packet size
f OMAP3430_reg_DMA4_CSAC23 4 @OMAP3430_SDMA_BASE+0x954 Channel Source Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16-bit data may be corrupted
f OMAP3430_reg_DMA4_CDAC23 4 @OMAP3430_SDMA_BASE+0x958 Channel Destination Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16-bit data may be corrupted
f OMAP3430_reg_DMA4_CCEN23 4 @OMAP3430_SDMA_BASE+0x95C Channel Current Transferred Element Number in the current frame. User has to access this register only in 32-bit access. If accessed in 8-bit or 16-bit data may be corrupted
f OMAP3430_reg_DMA4_CCFN23 4 @OMAP3430_SDMA_BASE+0x960 Channel Current Transferred Frame Number in the current transfer. User has to access this register only in 32-bit access. If accessed in 8-bit or 16-bit data may be corrupted
f OMAP3430_reg_DMA4_COLOR23 4 @OMAP3430_SDMA_BASE+0x964 Channel DMA COLOR KEY / SOLID COLOR
f OMAP3430_reg_DMA4_CCR24 4 @OMAP3430_SDMA_BASE+0x980 Channel Control Register
f OMAP3430_reg_DMA4_CLNK_CTRL24 4 @OMAP3430_SDMA_BASE+0x984 Channel Link Control Register
f OMAP3430_reg_DMA4_CICR24 4 @OMAP3430_SDMA_BASE+0x988 Channel Interrupt Control Register
f OMAP3430_reg_DMA4_CSR24 4 @OMAP3430_SDMA_BASE+0x98C Channel Status Register
f OMAP3430_reg_DMA4_CSDP24 4 @OMAP3430_SDMA_BASE+0x990 Channel Source Destination Parameters
f OMAP3430_reg_DMA4_CEN24 4 @OMAP3430_SDMA_BASE+0x994 Channel Element Number
f OMAP3430_reg_DMA4_CFN24 4 @OMAP3430_SDMA_BASE+0x998 Channel Frame Number
f OMAP3430_reg_DMA4_CSSA24 4 @OMAP3430_SDMA_BASE+0x99C Channel Source Start Address
f OMAP3430_reg_DMA4_CDSA24 4 @OMAP3430_SDMA_BASE+0x9A0 Channel Destination Start Address
f OMAP3430_reg_DMA4_CSEI24 4 @OMAP3430_SDMA_BASE+0x9A4 Channel Source Element Index (Signed)
f OMAP3430_reg_DMA4_CSFI24 4 @OMAP3430_SDMA_BASE+0x9A8 Channel Source Frame Index (Signed) or 16-bit Packet size
f OMAP3430_reg_DMA4_CDEI24 4 @OMAP3430_SDMA_BASE+0x9AC Channel Destination Element Index (Signed)
f OMAP3430_reg_DMA4_CDFI24 4 @OMAP3430_SDMA_BASE+0x9B0 Channel Destination Frame Index (Signed) or 16-bit Packet size
f OMAP3430_reg_DMA4_CSAC24 4 @OMAP3430_SDMA_BASE+0x9B4 Channel Source Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16-bit data may be corrupted
f OMAP3430_reg_DMA4_CDAC24 4 @OMAP3430_SDMA_BASE+0x9B8 Channel Destination Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16-bit data may be corrupted
f OMAP3430_reg_DMA4_CCEN24 4 @OMAP3430_SDMA_BASE+0x9BC Channel Current Transferred Element Number in the current frame. User has to access this register only in 32-bit access. If accessed in 8-bit or 16-bit data may be corrupted
f OMAP3430_reg_DMA4_CCFN24 4 @OMAP3430_SDMA_BASE+0x9C0 Channel Current Transferred Frame Number in the current transfer. User has to access this register only in 32-bit access. If accessed in 8-bit or 16-bit data may be corrupted
f OMAP3430_reg_DMA4_COLOR24 4 @OMAP3430_SDMA_BASE+0x9C4 Channel DMA COLOR KEY / SOLID COLOR
f OMAP3430_reg_DMA4_CCR25 4 @OMAP3430_SDMA_BASE+0x9E0 Channel Control Register
f OMAP3430_reg_DMA4_CLNK_CTRL25 4 @OMAP3430_SDMA_BASE+0x9E4 Channel Link Control Register
f OMAP3430_reg_DMA4_CICR25 4 @OMAP3430_SDMA_BASE+0x9E8 Channel Interrupt Control Register
f OMAP3430_reg_DMA4_CSR25 4 @OMAP3430_SDMA_BASE+0x9EC Channel Status Register
f OMAP3430_reg_DMA4_CSDP25 4 @OMAP3430_SDMA_BASE+0x9F0 Channel Source Destination Parameters
f OMAP3430_reg_DMA4_CEN25 4 @OMAP3430_SDMA_BASE+0x9F4 Channel Element Number
f OMAP3430_reg_DMA4_CFN25 4 @OMAP3430_SDMA_BASE+0x9F8 Channel Frame Number
f OMAP3430_reg_DMA4_CSSA25 4 @OMAP3430_SDMA_BASE+0x9FC Channel Source Start Address
f OMAP3430_reg_DMA4_CDSA25 4 @OMAP3430_SDMA_BASE+0xA00 Channel Destination Start Address
f OMAP3430_reg_DMA4_CSEI25 4 @OMAP3430_SDMA_BASE+0xA04 Channel Source Element Index (Signed)
f OMAP3430_reg_DMA4_CSFI25 4 @OMAP3430_SDMA_BASE+0xA08 Channel Source Frame Index (Signed) or 16-bit Packet size
f OMAP3430_reg_DMA4_CDEI25 4 @OMAP3430_SDMA_BASE+0xA0C Channel Destination Element Index (Signed)
f OMAP3430_reg_DMA4_CDFI25 4 @OMAP3430_SDMA_BASE+0xA10 Channel Destination Frame Index (Signed) or 16-bit Packet size
f OMAP3430_reg_DMA4_CSAC25 4 @OMAP3430_SDMA_BASE+0xA14 Channel Source Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16-bit data may be corrupted
f OMAP3430_reg_DMA4_CDAC25 4 @OMAP3430_SDMA_BASE+0xA18 Channel Destination Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16-bit data may be corrupted
f OMAP3430_reg_DMA4_CCEN25 4 @OMAP3430_SDMA_BASE+0xA1C Channel Current Transferred Element Number in the current frame. User has to access this register only in 32-bit access. If accessed in 8-bit or 16-bit data may be corrupted
f OMAP3430_reg_DMA4_CCFN25 4 @OMAP3430_SDMA_BASE+0xA20 Channel Current Transferred Frame Number in the current transfer. User has to access this register only in 32-bit access. If accessed in 8-bit or 16-bit data may be corrupted
f OMAP3430_reg_DMA4_COLOR25 4 @OMAP3430_SDMA_BASE+0xA24 Channel DMA COLOR KEY / SOLID COLOR
f OMAP3430_reg_DMA4_CCR26 4 @OMAP3430_SDMA_BASE+0xA40 Channel Control Register
f OMAP3430_reg_DMA4_CLNK_CTRL26 4 @OMAP3430_SDMA_BASE+0xA44 Channel Link Control Register
f OMAP3430_reg_DMA4_CICR26 4 @OMAP3430_SDMA_BASE+0xA48 Channel Interrupt Control Register
f OMAP3430_reg_DMA4_CSR26 4 @OMAP3430_SDMA_BASE+0xA4C Channel Status Register
f OMAP3430_reg_DMA4_CSDP26 4 @OMAP3430_SDMA_BASE+0xA50 Channel Source Destination Parameters
f OMAP3430_reg_DMA4_CEN26 4 @OMAP3430_SDMA_BASE+0xA54 Channel Element Number
f OMAP3430_reg_DMA4_CFN26 4 @OMAP3430_SDMA_BASE+0xA58 Channel Frame Number
f OMAP3430_reg_DMA4_CSSA26 4 @OMAP3430_SDMA_BASE+0xA5C Channel Source Start Address
f OMAP3430_reg_DMA4_CDSA26 4 @OMAP3430_SDMA_BASE+0xA60 Channel Destination Start Address
f OMAP3430_reg_DMA4_CSEI26 4 @OMAP3430_SDMA_BASE+0xA64 Channel Source Element Index (Signed)
f OMAP3430_reg_DMA4_CSFI26 4 @OMAP3430_SDMA_BASE+0xA68 Channel Source Frame Index (Signed) or 16-bit Packet size
f OMAP3430_reg_DMA4_CDEI26 4 @OMAP3430_SDMA_BASE+0xA6C Channel Destination Element Index (Signed)
f OMAP3430_reg_DMA4_CDFI26 4 @OMAP3430_SDMA_BASE+0xA70 Channel Destination Frame Index (Signed) or 16-bit Packet size
f OMAP3430_reg_DMA4_CSAC26 4 @OMAP3430_SDMA_BASE+0xA74 Channel Source Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16-bit data may be corrupted
f OMAP3430_reg_DMA4_CDAC26 4 @OMAP3430_SDMA_BASE+0xA78 Channel Destination Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16-bit data may be corrupted
f OMAP3430_reg_DMA4_CCEN26 4 @OMAP3430_SDMA_BASE+0xA7C Channel Current Transferred Element Number in the current frame. User has to access this register only in 32-bit access. If accessed in 8-bit or 16-bit data may be corrupted
f OMAP3430_reg_DMA4_CCFN26 4 @OMAP3430_SDMA_BASE+0xA80 Channel Current Transferred Frame Number in the current transfer. User has to access this register only in 32-bit access. If accessed in 8-bit or 16-bit data may be corrupted
f OMAP3430_reg_DMA4_COLOR26 4 @OMAP3430_SDMA_BASE+0xA84 Channel DMA COLOR KEY / SOLID COLOR
f OMAP3430_reg_DMA4_CCR27 4 @OMAP3430_SDMA_BASE+0xAA0 Channel Control Register
f OMAP3430_reg_DMA4_CLNK_CTRL27 4 @OMAP3430_SDMA_BASE+0xAA4 Channel Link Control Register
f OMAP3430_reg_DMA4_CICR27 4 @OMAP3430_SDMA_BASE+0xAA8 Channel Interrupt Control Register
f OMAP3430_reg_DMA4_CSR27 4 @OMAP3430_SDMA_BASE+0xAAC Channel Status Register
f OMAP3430_reg_DMA4_CSDP27 4 @OMAP3430_SDMA_BASE+0xAB0 Channel Source Destination Parameters
f OMAP3430_reg_DMA4_CEN27 4 @OMAP3430_SDMA_BASE+0xAB4 Channel Element Number
f OMAP3430_reg_DMA4_CFN27 4 @OMAP3430_SDMA_BASE+0xAB8 Channel Frame Number
f OMAP3430_reg_DMA4_CSSA27 4 @OMAP3430_SDMA_BASE+0xABC Channel Source Start Address
f OMAP3430_reg_DMA4_CDSA27 4 @OMAP3430_SDMA_BASE+0xAC0 Channel Destination Start Address
f OMAP3430_reg_DMA4_CSEI27 4 @OMAP3430_SDMA_BASE+0xAC4 Channel Source Element Index (Signed)
f OMAP3430_reg_DMA4_CSFI27 4 @OMAP3430_SDMA_BASE+0xAC8 Channel Source Frame Index (Signed) or 16-bit Packet size
f OMAP3430_reg_DMA4_CDEI27 4 @OMAP3430_SDMA_BASE+0xACC Channel Destination Element Index (Signed)
f OMAP3430_reg_DMA4_CDFI27 4 @OMAP3430_SDMA_BASE+0xAD0 Channel Destination Frame Index (Signed) or 16-bit Packet size
f OMAP3430_reg_DMA4_CSAC27 4 @OMAP3430_SDMA_BASE+0xAD4 Channel Source Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16-bit data may be corrupted
f OMAP3430_reg_DMA4_CDAC27 4 @OMAP3430_SDMA_BASE+0xAD8 Channel Destination Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16-bit data may be corrupted
f OMAP3430_reg_DMA4_CCEN27 4 @OMAP3430_SDMA_BASE+0xADC Channel Current Transferred Element Number in the current frame. User has to access this register only in 32-bit access. If accessed in 8-bit or 16-bit data may be corrupted
f OMAP3430_reg_DMA4_CCFN27 4 @OMAP3430_SDMA_BASE+0xAE0 Channel Current Transferred Frame Number in the current transfer. User has to access this register only in 32-bit access. If accessed in 8-bit or 16-bit data may be corrupted
f OMAP3430_reg_DMA4_COLOR27 4 @OMAP3430_SDMA_BASE+0xAE4 Channel DMA COLOR KEY / SOLID COLOR
f OMAP3430_reg_DMA4_CCR28 4 @OMAP3430_SDMA_BASE+0xB00 Channel Control Register
f OMAP3430_reg_DMA4_CLNK_CTRL28 4 @OMAP3430_SDMA_BASE+0xB04 Channel Link Control Register
f OMAP3430_reg_DMA4_CICR28 4 @OMAP3430_SDMA_BASE+0xB08 Channel Interrupt Control Register
f OMAP3430_reg_DMA4_CSR28 4 @OMAP3430_SDMA_BASE+0xB0C Channel Status Register
f OMAP3430_reg_DMA4_CSDP28 4 @OMAP3430_SDMA_BASE+0xB10 Channel Source Destination Parameters
f OMAP3430_reg_DMA4_CEN28 4 @OMAP3430_SDMA_BASE+0xB14 Channel Element Number
f OMAP3430_reg_DMA4_CFN28 4 @OMAP3430_SDMA_BASE+0xB18 Channel Frame Number
f OMAP3430_reg_DMA4_CSSA28 4 @OMAP3430_SDMA_BASE+0xB1C Channel Source Start Address
f OMAP3430_reg_DMA4_CDSA28 4 @OMAP3430_SDMA_BASE+0xB20 Channel Destination Start Address
f OMAP3430_reg_DMA4_CSEI28 4 @OMAP3430_SDMA_BASE+0xB24 Channel Source Element Index (Signed)
f OMAP3430_reg_DMA4_CSFI28 4 @OMAP3430_SDMA_BASE+0xB28 Channel Source Frame Index (Signed) or 16-bit Packet size
f OMAP3430_reg_DMA4_CDEI28 4 @OMAP3430_SDMA_BASE+0xB2C Channel Destination Element Index (Signed)
f OMAP3430_reg_DMA4_CDFI28 4 @OMAP3430_SDMA_BASE+0xB30 Channel Destination Frame Index (Signed) or 16-bit Packet size
f OMAP3430_reg_DMA4_CSAC28 4 @OMAP3430_SDMA_BASE+0xB34 Channel Source Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16-bit data may be corrupted
f OMAP3430_reg_DMA4_CDAC28 4 @OMAP3430_SDMA_BASE+0xB38 Channel Destination Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16-bit data may be corrupted
f OMAP3430_reg_DMA4_CCEN28 4 @OMAP3430_SDMA_BASE+0xB3C Channel Current Transferred Element Number in the current frame. User has to access this register only in 32-bit access. If accessed in 8-bit or 16-bit data may be corrupted
f OMAP3430_reg_DMA4_CCFN28 4 @OMAP3430_SDMA_BASE+0xB40 Channel Current Transferred Frame Number in the current transfer. User has to access this register only in 32-bit access. If accessed in 8-bit or 16-bit data may be corrupted
f OMAP3430_reg_DMA4_COLOR28 4 @OMAP3430_SDMA_BASE+0xB44 Channel DMA COLOR KEY / SOLID COLOR
f OMAP3430_reg_DMA4_CCR29 4 @OMAP3430_SDMA_BASE+0xB60 Channel Control Register
f OMAP3430_reg_DMA4_CLNK_CTRL29 4 @OMAP3430_SDMA_BASE+0xB64 Channel Link Control Register
f OMAP3430_reg_DMA4_CICR29 4 @OMAP3430_SDMA_BASE+0xB68 Channel Interrupt Control Register
f OMAP3430_reg_DMA4_CSR29 4 @OMAP3430_SDMA_BASE+0xB6C Channel Status Register
f OMAP3430_reg_DMA4_CSDP29 4 @OMAP3430_SDMA_BASE+0xB70 Channel Source Destination Parameters
f OMAP3430_reg_DMA4_CEN29 4 @OMAP3430_SDMA_BASE+0xB74 Channel Element Number
f OMAP3430_reg_DMA4_CFN29 4 @OMAP3430_SDMA_BASE+0xB78 Channel Frame Number
f OMAP3430_reg_DMA4_CSSA29 4 @OMAP3430_SDMA_BASE+0xB7C Channel Source Start Address
f OMAP3430_reg_DMA4_CDSA29 4 @OMAP3430_SDMA_BASE+0xB80 Channel Destination Start Address
f OMAP3430_reg_DMA4_CSEI29 4 @OMAP3430_SDMA_BASE+0xB84 Channel Source Element Index (Signed)
f OMAP3430_reg_DMA4_CSFI29 4 @OMAP3430_SDMA_BASE+0xB88 Channel Source Frame Index (Signed) or 16-bit Packet size
f OMAP3430_reg_DMA4_CDEI29 4 @OMAP3430_SDMA_BASE+0xB8C Channel Destination Element Index (Signed)
f OMAP3430_reg_DMA4_CDFI29 4 @OMAP3430_SDMA_BASE+0xB90 Channel Destination Frame Index (Signed) or 16-bit Packet size
f OMAP3430_reg_DMA4_CSAC29 4 @OMAP3430_SDMA_BASE+0xB94 Channel Source Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16-bit data may be corrupted
f OMAP3430_reg_DMA4_CDAC29 4 @OMAP3430_SDMA_BASE+0xB98 Channel Destination Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16-bit data may be corrupted
f OMAP3430_reg_DMA4_CCEN29 4 @OMAP3430_SDMA_BASE+0xB9C Channel Current Transferred Element Number in the current frame. User has to access this register only in 32-bit access. If accessed in 8-bit or 16-bit data may be corrupted
f OMAP3430_reg_DMA4_CCFN29 4 @OMAP3430_SDMA_BASE+0xBA0 Channel Current Transferred Frame Number in the current transfer. User has to access this register only in 32-bit access. If accessed in 8-bit or 16-bit data may be corrupted
f OMAP3430_reg_DMA4_COLOR29 4 @OMAP3430_SDMA_BASE+0xBA4 Channel DMA COLOR KEY / SOLID COLOR
f OMAP3430_reg_DMA4_CCR30 4 @OMAP3430_SDMA_BASE+0xBC0 Channel Control Register
f OMAP3430_reg_DMA4_CLNK_CTRL30 4 @OMAP3430_SDMA_BASE+0xBC4 Channel Link Control Register
f OMAP3430_reg_DMA4_CICR30 4 @OMAP3430_SDMA_BASE+0xBC8 Channel Interrupt Control Register
f OMAP3430_reg_DMA4_CSR30 4 @OMAP3430_SDMA_BASE+0xBCC Channel Status Register
f OMAP3430_reg_DMA4_CSDP30 4 @OMAP3430_SDMA_BASE+0xBD0 Channel Source Destination Parameters
f OMAP3430_reg_DMA4_CEN30 4 @OMAP3430_SDMA_BASE+0xBD4 Channel Element Number
f OMAP3430_reg_DMA4_CFN30 4 @OMAP3430_SDMA_BASE+0xBD8 Channel Frame Number
f OMAP3430_reg_DMA4_CSSA30 4 @OMAP3430_SDMA_BASE+0xBDC Channel Source Start Address
f OMAP3430_reg_DMA4_CDSA30 4 @OMAP3430_SDMA_BASE+0xBE0 Channel Destination Start Address
f OMAP3430_reg_DMA4_CSEI30 4 @OMAP3430_SDMA_BASE+0xBE4 Channel Source Element Index (Signed)
f OMAP3430_reg_DMA4_CSFI30 4 @OMAP3430_SDMA_BASE+0xBE8 Channel Source Frame Index (Signed) or 16-bit Packet size
f OMAP3430_reg_DMA4_CDEI30 4 @OMAP3430_SDMA_BASE+0xBEC Channel Destination Element Index (Signed)
f OMAP3430_reg_DMA4_CDFI30 4 @OMAP3430_SDMA_BASE+0xBF0 Channel Destination Frame Index (Signed) or 16-bit Packet size
f OMAP3430_reg_DMA4_CSAC30 4 @OMAP3430_SDMA_BASE+0xBF4 Channel Source Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16-bit data may be corrupted
f OMAP3430_reg_DMA4_CDAC30 4 @OMAP3430_SDMA_BASE+0xBF8 Channel Destination Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16-bit data may be corrupted
f OMAP3430_reg_DMA4_CCEN30 4 @OMAP3430_SDMA_BASE+0xBFC Channel Current Transferred Element Number in the current frame. User has to access this register only in 32-bit access. If accessed in 8-bit or 16-bit data may be corrupted
f OMAP3430_reg_DMA4_CCFN30 4 @OMAP3430_SDMA_BASE+0xC00 Channel Current Transferred Frame Number in the current transfer. User has to access this register only in 32-bit access. If accessed in 8-bit or 16-bit data may be corrupted
f OMAP3430_reg_DMA4_COLOR30 4 @OMAP3430_SDMA_BASE+0xC04 Channel DMA COLOR KEY / SOLID COLOR
f OMAP3430_reg_DMA4_CCR31 4 @OMAP3430_SDMA_BASE+0xC20 Channel Control Register
f OMAP3430_reg_DMA4_CLNK_CTRL31 4 @OMAP3430_SDMA_BASE+0xC24 Channel Link Control Register
f OMAP3430_reg_DMA4_CICR31 4 @OMAP3430_SDMA_BASE+0xC28 Channel Interrupt Control Register
f OMAP3430_reg_DMA4_CSR31 4 @OMAP3430_SDMA_BASE+0xC2C Channel Status Register
f OMAP3430_reg_DMA4_CSDP31 4 @OMAP3430_SDMA_BASE+0xC30 Channel Source Destination Parameters
f OMAP3430_reg_DMA4_CEN31 4 @OMAP3430_SDMA_BASE+0xC34 Channel Element Number
f OMAP3430_reg_DMA4_CFN31 4 @OMAP3430_SDMA_BASE+0xC38 Channel Frame Number
f OMAP3430_reg_DMA4_CSSA31 4 @OMAP3430_SDMA_BASE+0xC3C Channel Source Start Address
f OMAP3430_reg_DMA4_CDSA31 4 @OMAP3430_SDMA_BASE+0xC40 Channel Destination Start Address
f OMAP3430_reg_DMA4_CSEI31 4 @OMAP3430_SDMA_BASE+0xC44 Channel Source Element Index (Signed)
f OMAP3430_reg_DMA4_CSFI31 4 @OMAP3430_SDMA_BASE+0xC48 Channel Source Frame Index (Signed) or 16-bit Packet size
f OMAP3430_reg_DMA4_CDEI31 4 @OMAP3430_SDMA_BASE+0xC4C Channel Destination Element Index (Signed)
f OMAP3430_reg_DMA4_CDFI31 4 @OMAP3430_SDMA_BASE+0xC50 Channel Destination Frame Index (Signed) or 16-bit Packet size
f OMAP3430_reg_DMA4_CSAC31 4 @OMAP3430_SDMA_BASE+0xC54 Channel Source Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16-bit data may be corrupted
f OMAP3430_reg_DMA4_CDAC31 4 @OMAP3430_SDMA_BASE+0xC58 Channel Destination Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16-bit data may be corrupted
f OMAP3430_reg_DMA4_CCEN31 4 @OMAP3430_SDMA_BASE+0xC5C Channel Current Transferred Element Number in the current frame. User has to access this register only in 32-bit access. If accessed in 8-bit or 16-bit data may be corrupted
f OMAP3430_reg_DMA4_CCFN31 4 @OMAP3430_SDMA_BASE+0xC60 Channel Current Transferred Frame Number in the current transfer. User has to access this register only in 32-bit access. If accessed in 8-bit or 16-bit data may be corrupted
f OMAP3430_reg_DMA4_COLOR31 4 @OMAP3430_SDMA_BASE+0xC64 Channel DMA COLOR KEY / SOLID COLOR
f OMAP3430_reg_INTCPS_REVISION 4 @OMAP3430_MPU_INTC_BASE+0x0 This register contains the IP revision code
f OMAP3430_reg_INTCPS_SYSCONFIG 4 @OMAP3430_MPU_INTC_BASE+0x10 This register controls various parameters of the module interface
f OMAP3430_reg_INTCPS_SYSSTATUS 4 @OMAP3430_MPU_INTC_BASE+0x14 This register provides status information about the module
f OMAP3430_reg_INTCPS_SIR_IRQ 4 @OMAP3430_MPU_INTC_BASE+0x40 This register supplies the currently active IRQ interrupt number
f OMAP3430_reg_INTCPS_SIR_FIQ 4 @OMAP3430_MPU_INTC_BASE+0x44 This register supplies the currently active FIQ interrupt number
f OMAP3430_reg_INTCPS_CONTROL 4 @OMAP3430_MPU_INTC_BASE+0x48 This register contains the new interrupt agreement bits
f OMAP3430_reg_INTCPS_PROTECTION 4 @OMAP3430_MPU_INTC_BASE+0x4C This register controls protection of the other registers. It can be accessed only in supervisor mode, regardless of the current value of the protection bit
f OMAP3430_reg_INTCPS_IDLE 4 @OMAP3430_MPU_INTC_BASE+0x50 This register controls the functional clock auto-idle and the synchronizer clock auto-gating
f OMAP3430_reg_INTCPS_IRQ_PRIORITY 4 @OMAP3430_MPU_INTC_BASE+0x60 This register supplies the currently active IRQ priority level
f OMAP3430_reg_INTCPS_FIQ_PRIORITY 4 @OMAP3430_MPU_INTC_BASE+0x64 This register supplies the currently active FIQ priority level
f OMAP3430_reg_INTCPS_THRESHOLD 4 @OMAP3430_MPU_INTC_BASE+0x68 This register sets the priority threshold
f OMAP3430_reg_INTCPS_ITR0 4 @OMAP3430_MPU_INTC_BASE+0x80 This register shows the raw interrupt input status before masking
f OMAP3430_reg_INTCPS_MIR0 4 @OMAP3430_MPU_INTC_BASE+0x84 This register contains the interrupt mask
f OMAP3430_reg_INTCPS_MIR_CLEAR0 4 @OMAP3430_MPU_INTC_BASE+0x88 This register is used to clear the interrupt mask bits
f OMAP3430_reg_INTCPS_MIR_SET0 4 @OMAP3430_MPU_INTC_BASE+0x8C This register is used to set the interrupt mask bits
f OMAP3430_reg_INTCPS_ISR_SET0 4 @OMAP3430_MPU_INTC_BASE+0x90 This register is used to set the software interrupt bits. It is also used to read the currently active software interrupts
f OMAP3430_reg_INTCPS_ISR_CLEAR0 4 @OMAP3430_MPU_INTC_BASE+0x94 This register is used to clear the software interrupt bits
f OMAP3430_reg_INTCPS_PENDING_IRQ0 4 @OMAP3430_MPU_INTC_BASE+0x98 This register contains the IRQ status after masking
f OMAP3430_reg_INTCPS_PENDING_FIQ0 4 @OMAP3430_MPU_INTC_BASE+0x9C This register contains the FIQ status after masking
f OMAP3430_reg_INTCPS_ITR1 4 @OMAP3430_MPU_INTC_BASE+0xA0 This register shows the raw interrupt status before masking
f OMAP3430_reg_INTCPS_MIR1 4 @OMAP3430_MPU_INTC_BASE+0xA4 This register contains the interrupt mask
f OMAP3430_reg_INTCPS_MIR_CLEAR1 4 @OMAP3430_MPU_INTC_BASE+0xA8 This register is used to clear the interrupt mask bits
f OMAP3430_reg_INTCPS_MIR_SET1 4 @OMAP3430_MPU_INTC_BASE+0xAC This register is used to set the interrupt mask bits
f OMAP3430_reg_INTCPS_ISR_SET1 4 @OMAP3430_MPU_INTC_BASE+0xB0 This register is used to set the software interrupt bits. It is also used to read the currently active software interrupts
f OMAP3430_reg_INTCPS_ISR_CLEAR1 4 @OMAP3430_MPU_INTC_BASE+0xB4 This register is ised to clear the software interrupt bits
f OMAP3430_reg_INTCPS_PENDING_IRQ1 4 @OMAP3430_MPU_INTC_BASE+0xB8 This register contains the IRQ status after masking
f OMAP3430_reg_INTCPS_PENDING_FIQ1 4 @OMAP3430_MPU_INTC_BASE+0xBC This register contains the FIQ status after masking
f OMAP3430_reg_INTCPS_ITR2 4 @OMAP3430_MPU_INTC_BASE+0xC0 This register shows the raw interrupt status before masking
f OMAP3430_reg_INTCPS_MIR2 4 @OMAP3430_MPU_INTC_BASE+0xC4 This register contains the interrupt mask
f OMAP3430_reg_INTCPS_MIR_CLEAR2 4 @OMAP3430_MPU_INTC_BASE+0xC8 This register is used to clear the interrupt mask bits
f OMAP3430_reg_INTCPS_MIR_SET2 4 @OMAP3430_MPU_INTC_BASE+0xCC This register is used to set the interrupt mask bits
f OMAP3430_reg_INTCPS_ISR_SET2 4 @OMAP3430_MPU_INTC_BASE+0xD0 This register is used to set the software interrupt bits. It is also used to read the currently active software interrupts
f OMAP3430_reg_INTCPS_ISR_CLEAR2 4 @OMAP3430_MPU_INTC_BASE+0xD4 This register is used to clear the software interrupt bits
f OMAP3430_reg_INTCPS_PENDING_IRQ2 4 @OMAP3430_MPU_INTC_BASE+0xD8 This register contains the IRQ status after masking
f OMAP3430_reg_INTCPS_PENDING_FIQ2 4 @OMAP3430_MPU_INTC_BASE+0xDC This register contains the FIQ status after masking
f OMAP3430_reg_INTCPS_ILR0 4 @OMAP3430_MPU_INTC_BASE+0x100 This register contain the priority for the interrupts and the FIQ/IRQ steering
f OMAP3430_reg_INTCPS_ILR1 4 @OMAP3430_MPU_INTC_BASE+0x104 This register contain the priority for the interrupts and the FIQ/IRQ steering
f OMAP3430_reg_INTCPS_ILR2 4 @OMAP3430_MPU_INTC_BASE+0x108 This register contain the priority for the interrupts and the FIQ/IRQ steering
f OMAP3430_reg_INTCPS_ILR3 4 @OMAP3430_MPU_INTC_BASE+0x10C This register contain the priority for the interrupts and the FIQ/IRQ steering
f OMAP3430_reg_INTCPS_ILR4 4 @OMAP3430_MPU_INTC_BASE+0x110 This register contain the priority for the interrupts and the FIQ/IRQ steering
f OMAP3430_reg_INTCPS_ILR5 4 @OMAP3430_MPU_INTC_BASE+0x114 This register contain the priority for the interrupts and the FIQ/IRQ steering
f OMAP3430_reg_INTCPS_ILR6 4 @OMAP3430_MPU_INTC_BASE+0x118 This register contain the priority for the interrupts and the FIQ/IRQ steering
f OMAP3430_reg_INTCPS_ILR7 4 @OMAP3430_MPU_INTC_BASE+0x11C This register contain the priority for the interrupts and the FIQ/IRQ steering
f OMAP3430_reg_INTCPS_ILR8 4 @OMAP3430_MPU_INTC_BASE+0x120 This register contain the priority for the interrupts and the FIQ/IRQ steering
f OMAP3430_reg_INTCPS_ILR9 4 @OMAP3430_MPU_INTC_BASE+0x124 This register contain the priority for the interrupts and the FIQ/IRQ steering
f OMAP3430_reg_INTCPS_ILR10 4 @OMAP3430_MPU_INTC_BASE+0x128 This register contain the priority for the interrupts and the FIQ/IRQ steering
f OMAP3430_reg_INTCPS_ILR11 4 @OMAP3430_MPU_INTC_BASE+0x12C This register contain the priority for the interrupts and the FIQ/IRQ steering
f OMAP3430_reg_INTCPS_ILR12 4 @OMAP3430_MPU_INTC_BASE+0x130 This register contain the priority for the interrupts and the FIQ/IRQ steering
f OMAP3430_reg_INTCPS_ILR13 4 @OMAP3430_MPU_INTC_BASE+0x134 This register contain the priority for the interrupts and the FIQ/IRQ steering
f OMAP3430_reg_INTCPS_ILR14 4 @OMAP3430_MPU_INTC_BASE+0x138 This register contain the priority for the interrupts and the FIQ/IRQ steering
f OMAP3430_reg_INTCPS_ILR15 4 @OMAP3430_MPU_INTC_BASE+0x13C This register contain the priority for the interrupts and the FIQ/IRQ steering
f OMAP3430_reg_INTCPS_ILR16 4 @OMAP3430_MPU_INTC_BASE+0x140 This register contain the priority for the interrupts and the FIQ/IRQ steering
f OMAP3430_reg_INTCPS_ILR17 4 @OMAP3430_MPU_INTC_BASE+0x144 This register contain the priority for the interrupts and the FIQ/IRQ steering
f OMAP3430_reg_INTCPS_ILR18 4 @OMAP3430_MPU_INTC_BASE+0x148 This register contain the priority for the interrupts and the FIQ/IRQ steering
f OMAP3430_reg_INTCPS_ILR19 4 @OMAP3430_MPU_INTC_BASE+0x14C This register contain the priority for the interrupts and the FIQ/IRQ steering
f OMAP3430_reg_INTCPS_ILR20 4 @OMAP3430_MPU_INTC_BASE+0x150 This register contain the priority for the interrupts and the FIQ/IRQ steering
f OMAP3430_reg_INTCPS_ILR21 4 @OMAP3430_MPU_INTC_BASE+0x154 This register contain the priority for the interrupts and the FIQ/IRQ steering
f OMAP3430_reg_INTCPS_ILR22 4 @OMAP3430_MPU_INTC_BASE+0x158 This register contain the priority for the interrupts and the FIQ/IRQ steering
f OMAP3430_reg_INTCPS_ILR23 4 @OMAP3430_MPU_INTC_BASE+0x15C This register contain the priority for the interrupts and the FIQ/IRQ steering
f OMAP3430_reg_INTCPS_ILR24 4 @OMAP3430_MPU_INTC_BASE+0x160 This register contain the priority for the interrupts and the FIQ/IRQ steering
f OMAP3430_reg_INTCPS_ILR25 4 @OMAP3430_MPU_INTC_BASE+0x164 This register contain the priority for the interrupts and the FIQ/IRQ steering
f OMAP3430_reg_INTCPS_ILR26 4 @OMAP3430_MPU_INTC_BASE+0x168 This register contain the priority for the interrupts and the FIQ/IRQ steering
f OMAP3430_reg_INTCPS_ILR27 4 @OMAP3430_MPU_INTC_BASE+0x16C This register contain the priority for the interrupts and the FIQ/IRQ steering
f OMAP3430_reg_INTCPS_ILR28 4 @OMAP3430_MPU_INTC_BASE+0x170 This register contain the priority for the interrupts and the FIQ/IRQ steering
f OMAP3430_reg_INTCPS_ILR29 4 @OMAP3430_MPU_INTC_BASE+0x174 This register contain the priority for the interrupts and the FIQ/IRQ steering
f OMAP3430_reg_INTCPS_ILR30 4 @OMAP3430_MPU_INTC_BASE+0x178 This register contain the priority for the interrupts and the FIQ/IRQ steering
f OMAP3430_reg_INTCPS_ILR31 4 @OMAP3430_MPU_INTC_BASE+0x17C This register contain the priority for the interrupts and the FIQ/IRQ steering
f OMAP3430_reg_INTCPS_ILR32 4 @OMAP3430_MPU_INTC_BASE+0x180 This register contain the priority for the interrupts and the FIQ/IRQ steering
f OMAP3430_reg_INTCPS_ILR33 4 @OMAP3430_MPU_INTC_BASE+0x184 This register contain the priority for the interrupts and the FIQ/IRQ steering
f OMAP3430_reg_INTCPS_ILR34 4 @OMAP3430_MPU_INTC_BASE+0x188 This register contain the priority for the interrupts and the FIQ/IRQ steering
f OMAP3430_reg_INTCPS_ILR35 4 @OMAP3430_MPU_INTC_BASE+0x18C This register contain the priority for the interrupts and the FIQ/IRQ steering
f OMAP3430_reg_INTCPS_ILR36 4 @OMAP3430_MPU_INTC_BASE+0x190 This register contain the priority for the interrupts and the FIQ/IRQ steering
f OMAP3430_reg_INTCPS_ILR37 4 @OMAP3430_MPU_INTC_BASE+0x194 This register contain the priority for the interrupts and the FIQ/IRQ steering
f OMAP3430_reg_INTCPS_ILR38 4 @OMAP3430_MPU_INTC_BASE+0x198 This register contain the priority for the interrupts and the FIQ/IRQ steering
f OMAP3430_reg_INTCPS_ILR39 4 @OMAP3430_MPU_INTC_BASE+0x19C This register contain the priority for the interrupts and the FIQ/IRQ steering
f OMAP3430_reg_INTCPS_ILR40 4 @OMAP3430_MPU_INTC_BASE+0x1A0 This register contain the priority for the interrupts and the FIQ/IRQ steering
f OMAP3430_reg_INTCPS_ILR41 4 @OMAP3430_MPU_INTC_BASE+0x1A4 This register contain the priority for the interrupts and the FIQ/IRQ steering
f OMAP3430_reg_INTCPS_ILR42 4 @OMAP3430_MPU_INTC_BASE+0x1A8 This register contain the priority for the interrupts and the FIQ/IRQ steering
f OMAP3430_reg_INTCPS_ILR43 4 @OMAP3430_MPU_INTC_BASE+0x1AC This register contain the priority for the interrupts and the FIQ/IRQ steering
f OMAP3430_reg_INTCPS_ILR44 4 @OMAP3430_MPU_INTC_BASE+0x1B0 This register contain the priority for the interrupts and the FIQ/IRQ steering
f OMAP3430_reg_INTCPS_ILR45 4 @OMAP3430_MPU_INTC_BASE+0x1B4 This register contain the priority for the interrupts and the FIQ/IRQ steering
f OMAP3430_reg_INTCPS_ILR46 4 @OMAP3430_MPU_INTC_BASE+0x1B8 This register contain the priority for the interrupts and the FIQ/IRQ steering
f OMAP3430_reg_INTCPS_ILR47 4 @OMAP3430_MPU_INTC_BASE+0x1BC This register contain the priority for the interrupts and the FIQ/IRQ steering
f OMAP3430_reg_INTCPS_ILR48 4 @OMAP3430_MPU_INTC_BASE+0x1C0 This register contain the priority for the interrupts and the FIQ/IRQ steering
f OMAP3430_reg_INTCPS_ILR49 4 @OMAP3430_MPU_INTC_BASE+0x1C4 This register contain the priority for the interrupts and the FIQ/IRQ steering
f OMAP3430_reg_INTCPS_ILR50 4 @OMAP3430_MPU_INTC_BASE+0x1C8 This register contain the priority for the interrupts and the FIQ/IRQ steering
f OMAP3430_reg_INTCPS_ILR51 4 @OMAP3430_MPU_INTC_BASE+0x1CC This register contain the priority for the interrupts and the FIQ/IRQ steering
f OMAP3430_reg_INTCPS_ILR52 4 @OMAP3430_MPU_INTC_BASE+0x1D0 This register contain the priority for the interrupts and the FIQ/IRQ steering
f OMAP3430_reg_INTCPS_ILR53 4 @OMAP3430_MPU_INTC_BASE+0x1D4 This register contain the priority for the interrupts and the FIQ/IRQ steering
f OMAP3430_reg_INTCPS_ILR54 4 @OMAP3430_MPU_INTC_BASE+0x1D8 This register contain the priority for the interrupts and the FIQ/IRQ steering
f OMAP3430_reg_INTCPS_ILR55 4 @OMAP3430_MPU_INTC_BASE+0x1DC This register contain the priority for the interrupts and the FIQ/IRQ steering
f OMAP3430_reg_INTCPS_ILR56 4 @OMAP3430_MPU_INTC_BASE+0x1E0 This register contain the priority for the interrupts and the FIQ/IRQ steering
f OMAP3430_reg_INTCPS_ILR57 4 @OMAP3430_MPU_INTC_BASE+0x1E4 This register contain the priority for the interrupts and the FIQ/IRQ steering
f OMAP3430_reg_INTCPS_ILR58 4 @OMAP3430_MPU_INTC_BASE+0x1E8 This register contain the priority for the interrupts and the FIQ/IRQ steering
f OMAP3430_reg_INTCPS_ILR59 4 @OMAP3430_MPU_INTC_BASE+0x1EC This register contain the priority for the interrupts and the FIQ/IRQ steering
f OMAP3430_reg_INTCPS_ILR60 4 @OMAP3430_MPU_INTC_BASE+0x1F0 This register contain the priority for the interrupts and the FIQ/IRQ steering
f OMAP3430_reg_INTCPS_ILR61 4 @OMAP3430_MPU_INTC_BASE+0x1F4 This register contain the priority for the interrupts and the FIQ/IRQ steering
f OMAP3430_reg_INTCPS_ILR62 4 @OMAP3430_MPU_INTC_BASE+0x1F8 This register contain the priority for the interrupts and the FIQ/IRQ steering
f OMAP3430_reg_INTCPS_ILR63 4 @OMAP3430_MPU_INTC_BASE+0x1FC This register contain the priority for the interrupts and the FIQ/IRQ steering
f OMAP3430_reg_INTCPS_ILR64 4 @OMAP3430_MPU_INTC_BASE+0x200 This register contain the priority for the interrupts and the FIQ/IRQ steering
f OMAP3430_reg_INTCPS_ILR65 4 @OMAP3430_MPU_INTC_BASE+0x204 This register contain the priority for the interrupts and the FIQ/IRQ steering
f OMAP3430_reg_INTCPS_ILR66 4 @OMAP3430_MPU_INTC_BASE+0x208 This register contain the priority for the interrupts and the FIQ/IRQ steering
f OMAP3430_reg_INTCPS_ILR67 4 @OMAP3430_MPU_INTC_BASE+0x20C This register contain the priority for the interrupts and the FIQ/IRQ steering
f OMAP3430_reg_INTCPS_ILR68 4 @OMAP3430_MPU_INTC_BASE+0x210 This register contain the priority for the interrupts and the FIQ/IRQ steering
f OMAP3430_reg_INTCPS_ILR69 4 @OMAP3430_MPU_INTC_BASE+0x214 This register contain the priority for the interrupts and the FIQ/IRQ steering
f OMAP3430_reg_INTCPS_ILR70 4 @OMAP3430_MPU_INTC_BASE+0x218 This register contain the priority for the interrupts and the FIQ/IRQ steering
f OMAP3430_reg_INTCPS_ILR71 4 @OMAP3430_MPU_INTC_BASE+0x21C This register contain the priority for the interrupts and the FIQ/IRQ steering
f OMAP3430_reg_INTCPS_ILR72 4 @OMAP3430_MPU_INTC_BASE+0x220 This register contain the priority for the interrupts and the FIQ/IRQ steering
f OMAP3430_reg_INTCPS_ILR73 4 @OMAP3430_MPU_INTC_BASE+0x224 This register contain the priority for the interrupts and the FIQ/IRQ steering
f OMAP3430_reg_INTCPS_ILR74 4 @OMAP3430_MPU_INTC_BASE+0x228 This register contain the priority for the interrupts and the FIQ/IRQ steering
f OMAP3430_reg_INTCPS_ILR75 4 @OMAP3430_MPU_INTC_BASE+0x22C This register contain the priority for the interrupts and the FIQ/IRQ steering
f OMAP3430_reg_INTCPS_ILR76 4 @OMAP3430_MPU_INTC_BASE+0x230 This register contain the priority for the interrupts and the FIQ/IRQ steering
f OMAP3430_reg_INTCPS_ILR77 4 @OMAP3430_MPU_INTC_BASE+0x234 This register contain the priority for the interrupts and the FIQ/IRQ steering
f OMAP3430_reg_INTCPS_ILR78 4 @OMAP3430_MPU_INTC_BASE+0x238 This register contain the priority for the interrupts and the FIQ/IRQ steering
f OMAP3430_reg_INTCPS_ILR79 4 @OMAP3430_MPU_INTC_BASE+0x23C This register contain the priority for the interrupts and the FIQ/IRQ steering
f OMAP3430_reg_INTCPS_ILR80 4 @OMAP3430_MPU_INTC_BASE+0x240 This register contain the priority for the interrupts and the FIQ/IRQ steering
f OMAP3430_reg_INTCPS_ILR81 4 @OMAP3430_MPU_INTC_BASE+0x244 This register contain the priority for the interrupts and the FIQ/IRQ steering
f OMAP3430_reg_INTCPS_ILR82 4 @OMAP3430_MPU_INTC_BASE+0x248 This register contain the priority for the interrupts and the FIQ/IRQ steering
f OMAP3430_reg_INTCPS_ILR83 4 @OMAP3430_MPU_INTC_BASE+0x24C This register contain the priority for the interrupts and the FIQ/IRQ steering
f OMAP3430_reg_INTCPS_ILR84 4 @OMAP3430_MPU_INTC_BASE+0x250 This register contain the priority for the interrupts and the FIQ/IRQ steering
f OMAP3430_reg_INTCPS_ILR85 4 @OMAP3430_MPU_INTC_BASE+0x254 This register contain the priority for the interrupts and the FIQ/IRQ steering
f OMAP3430_reg_INTCPS_ILR86 4 @OMAP3430_MPU_INTC_BASE+0x258 This register contain the priority for the interrupts and the FIQ/IRQ steering
f OMAP3430_reg_INTCPS_ILR87 4 @OMAP3430_MPU_INTC_BASE+0x25C This register contain the priority for the interrupts and the FIQ/IRQ steering
f OMAP3430_reg_INTCPS_ILR88 4 @OMAP3430_MPU_INTC_BASE+0x260 This register contain the priority for the interrupts and the FIQ/IRQ steering
f OMAP3430_reg_INTCPS_ILR89 4 @OMAP3430_MPU_INTC_BASE+0x264 This register contain the priority for the interrupts and the FIQ/IRQ steering
f OMAP3430_reg_INTCPS_ILR90 4 @OMAP3430_MPU_INTC_BASE+0x268 This register contain the priority for the interrupts and the FIQ/IRQ steering
f OMAP3430_reg_INTCPS_ILR91 4 @OMAP3430_MPU_INTC_BASE+0x26C This register contain the priority for the interrupts and the FIQ/IRQ steering
f OMAP3430_reg_INTCPS_ILR92 4 @OMAP3430_MPU_INTC_BASE+0x270 This register contain the priority for the interrupts and the FIQ/IRQ steering
f OMAP3430_reg_INTCPS_ILR93 4 @OMAP3430_MPU_INTC_BASE+0x274 This register contain the priority for the interrupts and the FIQ/IRQ steering
f OMAP3430_reg_INTCPS_ILR94 4 @OMAP3430_MPU_INTC_BASE+0x278 This register contain the priority for the interrupts and the FIQ/IRQ steering
f OMAP3430_reg_INTCPS_ILR95 4 @OMAP3430_MPU_INTC_BASE+0x27C This register contain the priority for the interrupts and the FIQ/IRQ steering
f OMAP3430_reg_INTC_SYSCONFIG 4 @OMAP3430_MODEM_INTC_BASE+0x10 This register controls various parameters of the module interface
f OMAP3430_reg_INTC_IDLE 4 @OMAP3430_MODEM_INTC_BASE+0x50 This register controls the functional clock auto-idle and the synchronizer clock auto-gating
f OMAP3430_reg_GPMC_REVISION 4 @OMAP3430_GPMC_BASE+0x0 This register contains the IP revision code
f OMAP3430_reg_GPMC_SYSCONFIG 4 @OMAP3430_GPMC_BASE+0x10 This register controls the various parameters of the Interconnect
f OMAP3430_reg_GPMC_SYSSTATUS 4 @OMAP3430_GPMC_BASE+0x14 This register provides status information about the module, excluding the interrupt status information
f OMAP3430_reg_GPMC_IRQSTATUS 4 @OMAP3430_GPMC_BASE+0x18 This interrupt status register regroups all the status of the module internal events that can generate an interrupt
f OMAP3430_reg_GPMC_IRQENABLE 4 @OMAP3430_GPMC_BASE+0x1C This interrupt enable register allows to mask/unmask the module internal sources of interrupt, on a event-by-event basis
f OMAP3430_reg_GPMC_TIMEOUT_CONTROL 4 @OMAP3430_GPMC_BASE+0x40 This register allows the user to set the start value of the timeout counter
f OMAP3430_reg_GPMC_ERR_ADDRESS 4 @OMAP3430_GPMC_BASE+0x44 This register stores the address of the illegal access when an error occurs
f OMAP3430_reg_GPMC_ERR_TYPE 4 @OMAP3430_GPMC_BASE+0x48 This register stores the type of error when an error occurs
f OMAP3430_reg_GPMC_CONFIG 4 @OMAP3430_GPMC_BASE+0x50 The configuration register allows global configuration of the GPMC
f OMAP3430_reg_GPMC_STATUS 4 @OMAP3430_GPMC_BASE+0x54 The status register provides global status bits of the GPMC
f OMAP3430_reg_GPMC_CONFIG1_0 4 @OMAP3430_GPMC_BASE+0x60 The configuration register 1 sets signal control parameters per chip-select
f OMAP3430_reg_GPMC_CONFIG2_0 4 @OMAP3430_GPMC_BASE+0x64 CS signal timing parameter configuration
f OMAP3430_reg_GPMC_CONFIG3_0 4 @OMAP3430_GPMC_BASE+0x68 nADV signal timing parameter configuration
f OMAP3430_reg_GPMC_CONFIG4_0 4 @OMAP3430_GPMC_BASE+0x6C nWE and nOE signals timing parameter configuration
f OMAP3430_reg_GPMC_CONFIG5_0 4 @OMAP3430_GPMC_BASE+0x70 RdAccessTime and CycleTime timing parameters configuration
f OMAP3430_reg_GPMC_CONFIG6_0 4 @OMAP3430_GPMC_BASE+0x74 WrAccessTime, WrDataOnADmuxBus, Cycle2Cycle and BusTurnAround parameters configuration
f OMAP3430_reg_GPMC_CONFIG7_0 4 @OMAP3430_GPMC_BASE+0x78 CS address mapping configuration
f OMAP3430_reg_GPMC_NAND_COMMAND_0 4 @OMAP3430_GPMC_BASE+0x7C This register is not a true register, just an address location
f OMAP3430_reg_GPMC_NAND_ADDRESS_0 4 @OMAP3430_GPMC_BASE+0x80 This register is not a true register, just an address location
f OMAP3430_reg_GPMC_NAND_DATA_0 4 @OMAP3430_GPMC_BASE+0x84 This register is not a true register, just an address location
f OMAP3430_reg_GPMC_CONFIG1_1 4 @OMAP3430_GPMC_BASE+0x60 The configuration register 1 sets signal control parameters per chip-select
f OMAP3430_reg_GPMC_CONFIG2_1 4 @OMAP3430_GPMC_BASE+0x64 CS signal timing parameter configuration
f OMAP3430_reg_GPMC_CONFIG3_1 4 @OMAP3430_GPMC_BASE+0x68 nADV signal timing parameter configuration
f OMAP3430_reg_GPMC_CONFIG4_1 4 @OMAP3430_GPMC_BASE+0x6C nWE and nOE signals timing parameter configuration
f OMAP3430_reg_GPMC_CONFIG5_1 4 @OMAP3430_GPMC_BASE+0x70 RdAccessTime and CycleTime timing parameters configuration
f OMAP3430_reg_GPMC_CONFIG6_1 4 @OMAP3430_GPMC_BASE+0x74 WrAccessTime, WrDataOnADmuxBus, Cycle2Cycle and BusTurnAround parameters configuration
f OMAP3430_reg_GPMC_CONFIG7_1 4 @OMAP3430_GPMC_BASE+0x78 CS address mapping configuration
f OMAP3430_reg_GPMC_NAND_COMMAND_1 4 @OMAP3430_GPMC_BASE+0x7C This register is not a true register, just an address location
f OMAP3430_reg_GPMC_NAND_ADDRESS_1 4 @OMAP3430_GPMC_BASE+0x80 This register is not a true register, just an address location
f OMAP3430_reg_GPMC_NAND_DATA_1 4 @OMAP3430_GPMC_BASE+0x84 This register is not a true register, just an address location
f OMAP3430_reg_GPMC_CONFIG1_2 4 @OMAP3430_GPMC_BASE+0x60 The configuration register 1 sets signal control parameters per chip-select
f OMAP3430_reg_GPMC_CONFIG2_2 4 @OMAP3430_GPMC_BASE+0x64 CS signal timing parameter configuration
f OMAP3430_reg_GPMC_CONFIG3_2 4 @OMAP3430_GPMC_BASE+0x68 nADV signal timing parameter configuration
f OMAP3430_reg_GPMC_CONFIG4_2 4 @OMAP3430_GPMC_BASE+0x6C nWE and nOE signals timing parameter configuration
f OMAP3430_reg_GPMC_CONFIG5_2 4 @OMAP3430_GPMC_BASE+0x70 RdAccessTime and CycleTime timing parameters configuration
f OMAP3430_reg_GPMC_CONFIG6_2 4 @OMAP3430_GPMC_BASE+0x74 WrAccessTime, WrDataOnADmuxBus, Cycle2Cycle and BusTurnAround parameters configuration
f OMAP3430_reg_GPMC_CONFIG7_2 4 @OMAP3430_GPMC_BASE+0x78 CS address mapping configuration
f OMAP3430_reg_GPMC_NAND_COMMAND_2 4 @OMAP3430_GPMC_BASE+0x7C This register is not a true register, just an address location
f OMAP3430_reg_GPMC_NAND_ADDRESS_2 4 @OMAP3430_GPMC_BASE+0x80 This register is not a true register, just an address location
f OMAP3430_reg_GPMC_NAND_DATA_2 4 @OMAP3430_GPMC_BASE+0x84 This register is not a true register, just an address location
f OMAP3430_reg_GPMC_CONFIG1_3 4 @OMAP3430_GPMC_BASE+0x60 The configuration register 1 sets signal control parameters per chip-select
f OMAP3430_reg_GPMC_CONFIG2_3 4 @OMAP3430_GPMC_BASE+0x64 CS signal timing parameter configuration
f OMAP3430_reg_GPMC_CONFIG3_3 4 @OMAP3430_GPMC_BASE+0x68 nADV signal timing parameter configuration
f OMAP3430_reg_GPMC_CONFIG4_3 4 @OMAP3430_GPMC_BASE+0x6C nWE and nOE signals timing parameter configuration
f OMAP3430_reg_GPMC_CONFIG5_3 4 @OMAP3430_GPMC_BASE+0x70 RdAccessTime and CycleTime timing parameters configuration
f OMAP3430_reg_GPMC_CONFIG6_3 4 @OMAP3430_GPMC_BASE+0x74 WrAccessTime, WrDataOnADmuxBus, Cycle2Cycle and BusTurnAround parameters configuration
f OMAP3430_reg_GPMC_CONFIG7_3 4 @OMAP3430_GPMC_BASE+0x78 CS address mapping configuration
f OMAP3430_reg_GPMC_NAND_COMMAND_3 4 @OMAP3430_GPMC_BASE+0x7C This register is not a true register, just an address location
f OMAP3430_reg_GPMC_NAND_ADDRESS_3 4 @OMAP3430_GPMC_BASE+0x80 This register is not a true register, just an address location
f OMAP3430_reg_GPMC_NAND_DATA_3 4 @OMAP3430_GPMC_BASE+0x84 This register is not a true register, just an address location
f OMAP3430_reg_GPMC_CONFIG1_4 4 @OMAP3430_GPMC_BASE+0x60 The configuration register 1 sets signal control parameters per chip-select
f OMAP3430_reg_GPMC_CONFIG2_4 4 @OMAP3430_GPMC_BASE+0x64 CS signal timing parameter configuration
f OMAP3430_reg_GPMC_CONFIG3_4 4 @OMAP3430_GPMC_BASE+0x68 nADV signal timing parameter configuration
f OMAP3430_reg_GPMC_CONFIG4_4 4 @OMAP3430_GPMC_BASE+0x6C nWE and nOE signals timing parameter configuration
f OMAP3430_reg_GPMC_CONFIG5_4 4 @OMAP3430_GPMC_BASE+0x70 RdAccessTime and CycleTime timing parameters configuration
f OMAP3430_reg_GPMC_CONFIG6_4 4 @OMAP3430_GPMC_BASE+0x74 WrAccessTime, WrDataOnADmuxBus, Cycle2Cycle and BusTurnAround parameters configuration
f OMAP3430_reg_GPMC_CONFIG7_4 4 @OMAP3430_GPMC_BASE+0x78 CS address mapping configuration
f OMAP3430_reg_GPMC_NAND_COMMAND_4 4 @OMAP3430_GPMC_BASE+0x7C This register is not a true register, just an address location
f OMAP3430_reg_GPMC_NAND_ADDRESS_4 4 @OMAP3430_GPMC_BASE+0x80 This register is not a true register, just an address location
f OMAP3430_reg_GPMC_NAND_DATA_4 4 @OMAP3430_GPMC_BASE+0x84 This register is not a true register, just an address location
f OMAP3430_reg_GPMC_CONFIG1_5 4 @OMAP3430_GPMC_BASE+0x60 The configuration register 1 sets signal control parameters per chip-select
f OMAP3430_reg_GPMC_CONFIG2_5 4 @OMAP3430_GPMC_BASE+0x64 CS signal timing parameter configuration
f OMAP3430_reg_GPMC_CONFIG3_5 4 @OMAP3430_GPMC_BASE+0x68 nADV signal timing parameter configuration
f OMAP3430_reg_GPMC_CONFIG4_5 4 @OMAP3430_GPMC_BASE+0x6C nWE and nOE signals timing parameter configuration
f OMAP3430_reg_GPMC_CONFIG5_5 4 @OMAP3430_GPMC_BASE+0x70 RdAccessTime and CycleTime timing parameters configuration
f OMAP3430_reg_GPMC_CONFIG6_5 4 @OMAP3430_GPMC_BASE+0x74 WrAccessTime, WrDataOnADmuxBus, Cycle2Cycle and BusTurnAround parameters configuration
f OMAP3430_reg_GPMC_CONFIG7_5 4 @OMAP3430_GPMC_BASE+0x78 CS address mapping configuration
f OMAP3430_reg_GPMC_NAND_COMMAND_5 4 @OMAP3430_GPMC_BASE+0x7C This register is not a true register, just an address location
f OMAP3430_reg_GPMC_NAND_ADDRESS_5 4 @OMAP3430_GPMC_BASE+0x80 This register is not a true register, just an address location
f OMAP3430_reg_GPMC_NAND_DATA_5 4 @OMAP3430_GPMC_BASE+0x84 This register is not a true register, just an address location
f OMAP3430_reg_GPMC_CONFIG1_6 4 @OMAP3430_GPMC_BASE+0x60 The configuration register 1 sets signal control parameters per chip-select
f OMAP3430_reg_GPMC_CONFIG2_6 4 @OMAP3430_GPMC_BASE+0x64 CS signal timing parameter configuration
f OMAP3430_reg_GPMC_CONFIG3_6 4 @OMAP3430_GPMC_BASE+0x68 nADV signal timing parameter configuration
f OMAP3430_reg_GPMC_CONFIG4_6 4 @OMAP3430_GPMC_BASE+0x6C nWE and nOE signals timing parameter configuration
f OMAP3430_reg_GPMC_CONFIG5_6 4 @OMAP3430_GPMC_BASE+0x70 RdAccessTime and CycleTime timing parameters configuration
f OMAP3430_reg_GPMC_CONFIG6_6 4 @OMAP3430_GPMC_BASE+0x74 WrAccessTime, WrDataOnADmuxBus, Cycle2Cycle and BusTurnAround parameters configuration
f OMAP3430_reg_GPMC_CONFIG7_6 4 @OMAP3430_GPMC_BASE+0x78 CS address mapping configuration
f OMAP3430_reg_GPMC_NAND_COMMAND_6 4 @OMAP3430_GPMC_BASE+0x7C This register is not a true register, just an address location
f OMAP3430_reg_GPMC_NAND_ADDRESS_6 4 @OMAP3430_GPMC_BASE+0x80 This register is not a true register, just an address location
f OMAP3430_reg_GPMC_NAND_DATA_6 4 @OMAP3430_GPMC_BASE+0x84 This register is not a true register, just an address location
f OMAP3430_reg_GPMC_CONFIG1_7 4 @OMAP3430_GPMC_BASE+0x60 The configuration register 1 sets signal control parameters per chip-select
f OMAP3430_reg_GPMC_CONFIG2_7 4 @OMAP3430_GPMC_BASE+0x64 CS signal timing parameter configuration
f OMAP3430_reg_GPMC_CONFIG3_7 4 @OMAP3430_GPMC_BASE+0x68 nADV signal timing parameter configuration
f OMAP3430_reg_GPMC_CONFIG4_7 4 @OMAP3430_GPMC_BASE+0x6C nWE and nOE signals timing parameter configuration
f OMAP3430_reg_GPMC_CONFIG5_7 4 @OMAP3430_GPMC_BASE+0x70 RdAccessTime and CycleTime timing parameters configuration
f OMAP3430_reg_GPMC_CONFIG6_7 4 @OMAP3430_GPMC_BASE+0x74 WrAccessTime, WrDataOnADmuxBus, Cycle2Cycle and BusTurnAround parameters configuration
f OMAP3430_reg_GPMC_CONFIG7_7 4 @OMAP3430_GPMC_BASE+0x78 CS address mapping configuration
f OMAP3430_reg_GPMC_NAND_COMMAND_7 4 @OMAP3430_GPMC_BASE+0x7C This register is not a true register, just an address location
f OMAP3430_reg_GPMC_NAND_ADDRESS_7 4 @OMAP3430_GPMC_BASE+0x80 This register is not a true register, just an address location
f OMAP3430_reg_GPMC_NAND_DATA_7 4 @OMAP3430_GPMC_BASE+0x84 This register is not a true register, just an address location

f OMAP3430_reg_GPMC_PREFETCH_CONFIG1 4 @OMAP3430_GPMC_BASE+0x1E0 Prefetch engine configuration 1
f OMAP3430_reg_GPMC_PREFETCH_CONFIG2 4 @OMAP3430_GPMC_BASE+0x1E4 Prefetch engine configuration 2
f OMAP3430_reg_GPMC_PREFETCH_CONTROL 4 @OMAP3430_GPMC_BASE+0x1EC Prefetch engine control
f OMAP3430_reg_GPMC_PREFETCH_STATUS 4 @OMAP3430_GPMC_BASE+0x1F0 Prefetch engine status
f OMAP3430_reg_GPMC_ECC_CONFIG 4 @OMAP3430_GPMC_BASE+0x1F4 ECC configuration
f OMAP3430_reg_GPMC_ECC_CONTROL 4 @OMAP3430_GPMC_BASE+0x1F8 ECC control
f OMAP3430_reg_GPMC_ECC_SIZE_CONFIG 4 @OMAP3430_GPMC_BASE+0x1FC ECC size
f OMAP3430_reg_GPMC_ECC1_RESULT 4 @OMAP3430_GPMC_BASE+0x200 ECC result register

f OMAP3430_reg_GPMC_BCH_RESULT0_0 4 @OMAP3430_GPMC_BASE+0x240 BCH ECC result (bits 0 to 31)
f OMAP3430_reg_GPMC_BCH_RESULT1_0 4 @OMAP3430_GPMC_BASE+0x244 BCH ECC result (bits 32 to 63)
f OMAP3430_reg_GPMC_BCH_RESULT2_0 4 @OMAP3430_GPMC_BASE+0x248 BCH ECC result (bits 64 to 95)
f OMAP3430_reg_GPMC_BCH_RESULT3_0 4 @OMAP3430_GPMC_BASE+0x24C BCH ECC result (bits 96 to 103)

f OMAP3430_reg_GPMC_BCH_SWDATA 4 @OMAP3430_GPMC_BASE+0x2D0 This register is used to directly pass data to the BCH ECC calculator without accessing the actual NAND flash interface
f OMAP3430_reg_GPIO1_REVISION 4 @OMAP3430_GPIO1_BASE+0x0 This register contains the IP revision code.