1 //===-- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA --------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9
10 /* Capstone Disassembly Engine */
11 /* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
12
13 #ifdef CAPSTONE_HAS_ARM
14
15 #include <stdio.h>
16 #include <string.h>
17 #include <stdlib.h>
18 #include <capstone/platform.h>
19
20 #include "ARMAddressingModes.h"
21 #include "ARMBaseInfo.h"
22 #include "../../MCFixedLenDisassembler.h"
23 #include "../../MCInst.h"
24 #include "../../MCInstrDesc.h"
25 #include "../../MCRegisterInfo.h"
26 #include "../../LEB128.h"
27 #include "../../MCDisassembler.h"
28 #include "../../cs_priv.h"
29 #include "../../utils.h"
30
31 #include "ARMDisassembler.h"
32
33 //#define GET_REGINFO_ENUM
34 //#include "X86GenRegisterInfo.inc"
35
36 #define GET_SUBTARGETINFO_ENUM
37 #include "ARMGenSubtargetInfo.inc"
38
39 #define GET_INSTRINFO_MC_DESC
40 #include "ARMGenInstrInfo.inc"
41
42 #define GET_INSTRINFO_ENUM
43 #include "ARMGenInstrInfo.inc"
44
ITStatus_push_back(ARM_ITStatus * it,char v)45 static bool ITStatus_push_back(ARM_ITStatus *it, char v)
46 {
47 if (it->size >= sizeof(it->ITStates)) {
48 // TODO: consider warning user.
49 it->size = 0;
50 }
51 it->ITStates[it->size] = v;
52 it->size++;
53
54 return true;
55 }
56
57 // Returns true if the current instruction is in an IT block
ITStatus_instrInITBlock(ARM_ITStatus * it)58 static bool ITStatus_instrInITBlock(ARM_ITStatus *it)
59 {
60 //return !ITStates.empty();
61 return (it->size > 0);
62 }
63
64 // Returns true if current instruction is the last instruction in an IT block
ITStatus_instrLastInITBlock(ARM_ITStatus * it)65 static bool ITStatus_instrLastInITBlock(ARM_ITStatus *it)
66 {
67 return (it->size == 1);
68 }
69
70 // Handles the condition code status of instructions in IT blocks
71
72 // Returns the condition code for instruction in IT block
ITStatus_getITCC(ARM_ITStatus * it)73 static unsigned ITStatus_getITCC(ARM_ITStatus *it)
74 {
75 unsigned CC = ARMCC_AL;
76 if (ITStatus_instrInITBlock(it))
77 //CC = ITStates.back();
78 CC = it->ITStates[it->size-1];
79 return CC;
80 }
81
82 // Advances the IT block state to the next T or E
ITStatus_advanceITState(ARM_ITStatus * it)83 static void ITStatus_advanceITState(ARM_ITStatus *it)
84 {
85 //ITStates.pop_back();
86 it->size--;
87 }
88
89 // Called when decoding an IT instruction. Sets the IT state for the following
90 // instructions that for the IT block. Firstcond and Mask correspond to the
91 // fields in the IT instruction encoding.
ITStatus_setITState(ARM_ITStatus * it,char Firstcond,char Mask)92 static void ITStatus_setITState(ARM_ITStatus *it, char Firstcond, char Mask)
93 {
94 // (3 - the number of trailing zeros) is the number of then / else.
95 unsigned CondBit0 = Firstcond & 1;
96 unsigned NumTZ = CountTrailingZeros_32(Mask);
97 unsigned char CCBits = (unsigned char)Firstcond & 0xf;
98 unsigned Pos;
99 //assert(NumTZ <= 3 && "Invalid IT mask!");
100 // push condition codes onto the stack the correct order for the pops
101 for (Pos = NumTZ+1; Pos <= 3; ++Pos) {
102 bool T = ((Mask >> Pos) & 1) == (int)CondBit0;
103 if (T)
104 ITStatus_push_back(it, CCBits);
105 else
106 ITStatus_push_back(it, CCBits ^ 1);
107 }
108 ITStatus_push_back(it, CCBits);
109 }
110
111 /// ThumbDisassembler - Thumb disassembler for all Thumb platforms.
112
Check(DecodeStatus * Out,DecodeStatus In)113 static bool Check(DecodeStatus *Out, DecodeStatus In)
114 {
115 switch (In) {
116 case MCDisassembler_Success:
117 // Out stays the same.
118 return true;
119 case MCDisassembler_SoftFail:
120 *Out = In;
121 return true;
122 case MCDisassembler_Fail:
123 *Out = In;
124 return false;
125 default: // never reached
126 return false;
127 }
128 }
129
130 // Forward declare these because the autogenerated code will reference them.
131 // Definitions are further down.
132 static DecodeStatus DecodeGPRRegisterClass(MCInst *Inst, unsigned RegNo,
133 uint64_t Address, const void *Decoder);
134 static DecodeStatus DecodeGPRnopcRegisterClass(MCInst *Inst,
135 unsigned RegNo, uint64_t Address, const void *Decoder);
136 static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst *Inst,
137 unsigned RegNo, uint64_t Address, const void *Decoder);
138 static DecodeStatus DecodetGPRRegisterClass(MCInst *Inst, unsigned RegNo,
139 uint64_t Address, const void *Decoder);
140 static DecodeStatus DecodetcGPRRegisterClass(MCInst *Inst, unsigned RegNo,
141 uint64_t Address, const void *Decoder);
142 static DecodeStatus DecoderGPRRegisterClass(MCInst *Inst, unsigned RegNo,
143 uint64_t Address, const void *Decoder);
144 static DecodeStatus DecodeGPRPairRegisterClass(MCInst *Inst, unsigned RegNo,
145 uint64_t Address, const void *Decoder);
146 static DecodeStatus DecodeSPRRegisterClass(MCInst *Inst, unsigned RegNo,
147 uint64_t Address, const void *Decoder);
148 static DecodeStatus DecodeDPRRegisterClass(MCInst *Inst, unsigned RegNo,
149 uint64_t Address, const void *Decoder);
150 static DecodeStatus DecodeDPR_8RegisterClass(MCInst *Inst, unsigned RegNo,
151 uint64_t Address, const void *Decoder);
152 static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst *Inst,
153 unsigned RegNo, uint64_t Address, const void *Decoder);
154 static DecodeStatus DecodeQPRRegisterClass(MCInst *Inst, unsigned RegNo,
155 uint64_t Address, const void *Decoder);
156 static DecodeStatus DecodeDPairRegisterClass(MCInst *Inst, unsigned RegNo,
157 uint64_t Address, const void *Decoder);
158 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst *Inst,
159 unsigned RegNo, uint64_t Address, const void *Decoder);
160 static DecodeStatus DecodePredicateOperand(MCInst *Inst, unsigned Val,
161 uint64_t Address, const void *Decoder);
162 static DecodeStatus DecodeCCOutOperand(MCInst *Inst, unsigned Val,
163 uint64_t Address, const void *Decoder);
164 static DecodeStatus DecodeRegListOperand(MCInst *Inst, unsigned Val,
165 uint64_t Address, const void *Decoder);
166 static DecodeStatus DecodeSPRRegListOperand(MCInst *Inst, unsigned Val,
167 uint64_t Address, const void *Decoder);
168 static DecodeStatus DecodeDPRRegListOperand(MCInst *Inst, unsigned Val,
169 uint64_t Address, const void *Decoder);
170 static DecodeStatus DecodeBitfieldMaskOperand(MCInst *Inst, unsigned Insn,
171 uint64_t Address, const void *Decoder);
172 static DecodeStatus DecodeCopMemInstruction(MCInst *Inst, unsigned Insn,
173 uint64_t Address, const void *Decoder);
174 static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst *Inst,
175 unsigned Insn, uint64_t Address, const void *Decoder);
176 static DecodeStatus DecodeSORegMemOperand(MCInst *Inst, unsigned Insn,
177 uint64_t Address, const void *Decoder);
178 static DecodeStatus DecodeAddrMode3Instruction(MCInst *Inst,unsigned Insn,
179 uint64_t Address, const void *Decoder);
180 static DecodeStatus DecodeSORegImmOperand(MCInst *Inst, unsigned Insn,
181 uint64_t Address, const void *Decoder);
182 static DecodeStatus DecodeSORegRegOperand(MCInst *Inst, unsigned Insn,
183 uint64_t Address, const void *Decoder);
184 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst * Inst,
185 unsigned Insn, uint64_t Adddress, const void *Decoder);
186 static DecodeStatus DecodeT2MOVTWInstruction(MCInst *Inst, unsigned Insn,
187 uint64_t Address, const void *Decoder);
188 static DecodeStatus DecodeArmMOVTWInstruction(MCInst *Inst, unsigned Insn,
189 uint64_t Address, const void *Decoder);
190 static DecodeStatus DecodeSMLAInstruction(MCInst *Inst, unsigned Insn,
191 uint64_t Address, const void *Decoder);
192 static DecodeStatus DecodeCPSInstruction(MCInst *Inst, unsigned Insn,
193 uint64_t Address, const void *Decoder);
194 static DecodeStatus DecodeT2CPSInstruction(MCInst *Inst, unsigned Insn,
195 uint64_t Address, const void *Decoder);
196 static DecodeStatus DecodeAddrModeImm12Operand(MCInst *Inst, unsigned Val,
197 uint64_t Address, const void *Decoder);
198 static DecodeStatus DecodeAddrMode5Operand(MCInst *Inst, unsigned Val,
199 uint64_t Address, const void *Decoder);
200 static DecodeStatus DecodeAddrMode7Operand(MCInst *Inst, unsigned Val,
201 uint64_t Address, const void *Decoder);
202 static DecodeStatus DecodeT2BInstruction(MCInst *Inst, unsigned Insn,
203 uint64_t Address, const void *Decoder);
204 static DecodeStatus DecodeBranchImmInstruction(MCInst *Inst,unsigned Insn,
205 uint64_t Address, const void *Decoder);
206 static DecodeStatus DecodeAddrMode6Operand(MCInst *Inst, unsigned Val,
207 uint64_t Address, const void *Decoder);
208 static DecodeStatus DecodeVLDST1Instruction(MCInst *Inst, unsigned Val,
209 uint64_t Address, const void *Decoder);
210 static DecodeStatus DecodeVLDST2Instruction(MCInst *Inst, unsigned Val,
211 uint64_t Address, const void *Decoder);
212 static DecodeStatus DecodeVLDST3Instruction(MCInst *Inst, unsigned Val,
213 uint64_t Address, const void *Decoder);
214 static DecodeStatus DecodeVLDST4Instruction(MCInst *Inst, unsigned Val,
215 uint64_t Address, const void *Decoder);
216 static DecodeStatus DecodeVLDInstruction(MCInst *Inst, unsigned Val,
217 uint64_t Address, const void *Decoder);
218 static DecodeStatus DecodeVSTInstruction(MCInst *Inst, unsigned Val,
219 uint64_t Address, const void *Decoder);
220 static DecodeStatus DecodeVLD1DupInstruction(MCInst *Inst, unsigned Val,
221 uint64_t Address, const void *Decoder);
222 static DecodeStatus DecodeVLD2DupInstruction(MCInst *Inst, unsigned Val,
223 uint64_t Address, const void *Decoder);
224 static DecodeStatus DecodeVLD3DupInstruction(MCInst *Inst, unsigned Val,
225 uint64_t Address, const void *Decoder);
226 static DecodeStatus DecodeVLD4DupInstruction(MCInst *Inst, unsigned Val,
227 uint64_t Address, const void *Decoder);
228 static DecodeStatus DecodeNEONModImmInstruction(MCInst *Inst,unsigned Val,
229 uint64_t Address, const void *Decoder);
230 static DecodeStatus DecodeVSHLMaxInstruction(MCInst *Inst, unsigned Val,
231 uint64_t Address, const void *Decoder);
232 static DecodeStatus DecodeShiftRight8Imm(MCInst *Inst, unsigned Val,
233 uint64_t Address, const void *Decoder);
234 static DecodeStatus DecodeShiftRight16Imm(MCInst *Inst, unsigned Val,
235 uint64_t Address, const void *Decoder);
236 static DecodeStatus DecodeShiftRight32Imm(MCInst *Inst, unsigned Val,
237 uint64_t Address, const void *Decoder);
238 static DecodeStatus DecodeShiftRight64Imm(MCInst *Inst, unsigned Val,
239 uint64_t Address, const void *Decoder);
240 static DecodeStatus DecodeTBLInstruction(MCInst *Inst, unsigned Insn,
241 uint64_t Address, const void *Decoder);
242 static DecodeStatus DecodePostIdxReg(MCInst *Inst, unsigned Insn,
243 uint64_t Address, const void *Decoder);
244 static DecodeStatus DecodeCoprocessor(MCInst *Inst, unsigned Insn,
245 uint64_t Address, const void *Decoder);
246 static DecodeStatus DecodeMemBarrierOption(MCInst *Inst, unsigned Insn,
247 uint64_t Address, const void *Decoder);
248 static DecodeStatus DecodeInstSyncBarrierOption(MCInst *Inst, unsigned Insn,
249 uint64_t Address, const void *Decoder);
250 static DecodeStatus DecodeMSRMask(MCInst *Inst, unsigned Insn,
251 uint64_t Address, const void *Decoder);
252 static DecodeStatus DecodeBankedReg(MCInst *Inst, unsigned Insn,
253 uint64_t Address, const void *Decoder);
254 static DecodeStatus DecodeDoubleRegLoad(MCInst *Inst, unsigned Insn,
255 uint64_t Address, const void *Decoder);
256 static DecodeStatus DecodeDoubleRegStore(MCInst *Inst, unsigned Insn,
257 uint64_t Address, const void *Decoder);
258 static DecodeStatus DecodeLDRPreImm(MCInst *Inst, unsigned Insn,
259 uint64_t Address, const void *Decoder);
260 static DecodeStatus DecodeLDRPreReg(MCInst *Inst, unsigned Insn,
261 uint64_t Address, const void *Decoder);
262 static DecodeStatus DecodeSTRPreImm(MCInst *Inst, unsigned Insn,
263 uint64_t Address, const void *Decoder);
264 static DecodeStatus DecodeSTRPreReg(MCInst *Inst, unsigned Insn,
265 uint64_t Address, const void *Decoder);
266 static DecodeStatus DecodeVLD1LN(MCInst *Inst, unsigned Insn,
267 uint64_t Address, const void *Decoder);
268 static DecodeStatus DecodeVLD2LN(MCInst *Inst, unsigned Insn,
269 uint64_t Address, const void *Decoder);
270 static DecodeStatus DecodeVLD3LN(MCInst *Inst, unsigned Insn,
271 uint64_t Address, const void *Decoder);
272 static DecodeStatus DecodeVLD4LN(MCInst *Inst, unsigned Insn,
273 uint64_t Address, const void *Decoder);
274 static DecodeStatus DecodeVST1LN(MCInst *Inst, unsigned Insn,
275 uint64_t Address, const void *Decoder);
276 static DecodeStatus DecodeVST2LN(MCInst *Inst, unsigned Insn,
277 uint64_t Address, const void *Decoder);
278 static DecodeStatus DecodeVST3LN(MCInst *Inst, unsigned Insn,
279 uint64_t Address, const void *Decoder);
280 static DecodeStatus DecodeVST4LN(MCInst *Inst, unsigned Insn,
281 uint64_t Address, const void *Decoder);
282 static DecodeStatus DecodeVMOVSRR(MCInst *Inst, unsigned Insn,
283 uint64_t Address, const void *Decoder);
284 static DecodeStatus DecodeVMOVRRS(MCInst *Inst, unsigned Insn,
285 uint64_t Address, const void *Decoder);
286 static DecodeStatus DecodeSwap(MCInst *Inst, unsigned Insn,
287 uint64_t Address, const void *Decoder);
288 static DecodeStatus DecodeVCVTD(MCInst *Inst, unsigned Insn,
289 uint64_t Address, const void *Decoder);
290 static DecodeStatus DecodeVCVTQ(MCInst *Inst, unsigned Insn,
291 uint64_t Address, const void *Decoder);
292 static DecodeStatus DecodeThumbAddSpecialReg(MCInst *Inst, uint16_t Insn,
293 uint64_t Address, const void *Decoder);
294 static DecodeStatus DecodeThumbBROperand(MCInst *Inst, unsigned Val,
295 uint64_t Address, const void *Decoder);
296 static DecodeStatus DecodeT2BROperand(MCInst *Inst, unsigned Val,
297 uint64_t Address, const void *Decoder);
298 static DecodeStatus DecodeThumbCmpBROperand(MCInst *Inst, unsigned Val,
299 uint64_t Address, const void *Decoder);
300 static DecodeStatus DecodeThumbAddrModeRR(MCInst *Inst, unsigned Val,
301 uint64_t Address, const void *Decoder);
302 static DecodeStatus DecodeThumbAddrModeIS(MCInst *Inst, unsigned Val,
303 uint64_t Address, const void *Decoder);
304 static DecodeStatus DecodeThumbAddrModePC(MCInst *Inst, unsigned Val,
305 uint64_t Address, const void *Decoder);
306 static DecodeStatus DecodeThumbAddrModeSP(MCInst *Inst, unsigned Val,
307 uint64_t Address, const void *Decoder);
308 static DecodeStatus DecodeT2AddrModeSOReg(MCInst *Inst, unsigned Val,
309 uint64_t Address, const void *Decoder);
310 static DecodeStatus DecodeT2LoadShift(MCInst *Inst, unsigned Val,
311 uint64_t Address, const void *Decoder);
312 static DecodeStatus DecodeT2LoadImm8(MCInst *Inst, unsigned Insn,
313 uint64_t Address, const void* Decoder);
314 static DecodeStatus DecodeT2LoadImm12(MCInst *Inst, unsigned Insn,
315 uint64_t Address, const void* Decoder);
316 static DecodeStatus DecodeT2LoadT(MCInst *Inst, unsigned Insn,
317 uint64_t Address, const void* Decoder);
318 static DecodeStatus DecodeT2LoadLabel(MCInst *Inst, unsigned Insn,
319 uint64_t Address, const void* Decoder);
320 static DecodeStatus DecodeT2Imm8S4(MCInst *Inst, unsigned Val,
321 uint64_t Address, const void *Decoder);
322 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst *Inst, unsigned Val,
323 uint64_t Address, const void *Decoder);
324 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst *Inst,unsigned Val,
325 uint64_t Address, const void *Decoder);
326 static DecodeStatus DecodeT2Imm8(MCInst *Inst, unsigned Val,
327 uint64_t Address, const void *Decoder);
328 static DecodeStatus DecodeT2AddrModeImm8(MCInst *Inst, unsigned Val,
329 uint64_t Address, const void *Decoder);
330 static DecodeStatus DecodeThumbAddSPImm(MCInst *Inst, uint16_t Val,
331 uint64_t Address, const void *Decoder);
332 static DecodeStatus DecodeThumbAddSPReg(MCInst *Inst, uint16_t Insn,
333 uint64_t Address, const void *Decoder);
334 static DecodeStatus DecodeThumbCPS(MCInst *Inst, uint16_t Insn,
335 uint64_t Address, const void *Decoder);
336 static DecodeStatus DecodeQADDInstruction(MCInst *Inst, unsigned Insn,
337 uint64_t Address, const void *Decoder);
338 static DecodeStatus DecodeThumbBLXOffset(MCInst *Inst, unsigned Insn,
339 uint64_t Address, const void *Decoder);
340 static DecodeStatus DecodeT2AddrModeImm12(MCInst *Inst, unsigned Val,
341 uint64_t Address, const void *Decoder);
342 static DecodeStatus DecodeThumbTableBranch(MCInst *Inst, unsigned Val,
343 uint64_t Address, const void *Decoder);
344 static DecodeStatus DecodeThumb2BCCInstruction(MCInst *Inst, unsigned Val,
345 uint64_t Address, const void *Decoder);
346 static DecodeStatus DecodeT2SOImm(MCInst *Inst, unsigned Val,
347 uint64_t Address, const void *Decoder);
348 static DecodeStatus DecodeThumbBCCTargetOperand(MCInst *Inst,unsigned Val,
349 uint64_t Address, const void *Decoder);
350 static DecodeStatus DecodeThumbBLTargetOperand(MCInst *Inst, unsigned Val,
351 uint64_t Address, const void *Decoder);
352 static DecodeStatus DecodeIT(MCInst *Inst, unsigned Val,
353 uint64_t Address, const void *Decoder);
354 static DecodeStatus DecodeT2LDRDPreInstruction(MCInst *Inst,unsigned Insn,
355 uint64_t Address, const void *Decoder);
356 static DecodeStatus DecodeT2STRDPreInstruction(MCInst *Inst,unsigned Insn,
357 uint64_t Address, const void *Decoder);
358 static DecodeStatus DecodeT2Adr(MCInst *Inst, uint32_t Val,
359 uint64_t Address, const void *Decoder);
360 static DecodeStatus DecodeT2LdStPre(MCInst *Inst, unsigned Val,
361 uint64_t Address, const void *Decoder);
362 static DecodeStatus DecodeT2ShifterImmOperand(MCInst *Inst, uint32_t Val,
363 uint64_t Address, const void *Decoder);
364
365 static DecodeStatus DecodeLDR(MCInst *Inst, unsigned Val,
366 uint64_t Address, const void *Decoder);
367 static DecodeStatus DecodeMRRC2(MCInst *Inst, unsigned Val,
368 uint64_t Address, const void *Decoder);
369
370 // Hacky: enable all features for disassembler
ARM_getFeatureBits(unsigned int mode)371 uint64_t ARM_getFeatureBits(unsigned int mode)
372 {
373 uint64_t Bits = (uint64_t)-1; // everything by default
374
375 // FIXME: ARM_FeatureVFPOnlySP is conflicting with everything else??
376 Bits &= (~ARM_FeatureVFPOnlySP);
377
378 // FIXME: no Armv8 support?
379 //Bits -= ARM_HasV7Ops;
380 //Bits &= ~ARM_FeatureMP;
381 if ((mode & CS_MODE_V8) == 0)
382 Bits &= ~ARM_HasV8Ops;
383 //Bits &= ~ARM_HasV6Ops;
384
385 if ((mode & CS_MODE_MCLASS) == 0)
386 Bits &= (~ARM_FeatureMClass);
387
388 // some features are mutually exclusive
389 if (mode & CS_MODE_THUMB) {
390 //Bits &= ~ARM_HasV6Ops;
391 //Bits &= ~ARM_FeatureCRC;
392 //Bits &= ~ARM_HasV5TEOps;
393 //Bits &= ~ARM_HasV4TOps;
394 //Bits &= ~ARM_HasV6T2Ops;
395 //Bits &= ~ARM_FeatureDB;
396 //Bits &= ~ARM_FeatureHWDivARM;
397 //Bits &= ~ARM_FeatureNaClTrap;
398 //Bits &= ~ARM_FeatureMClass;
399 // ArmV8
400 } else { // ARM mode
401 Bits &= ~ARM_ModeThumb;
402 Bits &= ~ARM_FeatureThumb2;
403 }
404
405 return Bits;
406 }
407
408 #include "ARMGenDisassemblerTables.inc"
409
DecodePredicateOperand(MCInst * Inst,unsigned Val,uint64_t Address,const void * Decoder)410 static DecodeStatus DecodePredicateOperand(MCInst *Inst, unsigned Val,
411 uint64_t Address, const void *Decoder)
412 {
413 if (Val == 0xF) return MCDisassembler_Fail;
414 // AL predicate is not allowed on Thumb1 branches.
415 if (MCInst_getOpcode(Inst) == ARM_tBcc && Val == 0xE)
416 return MCDisassembler_Fail;
417 MCOperand_CreateImm0(Inst, Val);
418 if (Val == ARMCC_AL) {
419 MCOperand_CreateReg0(Inst, 0);
420 } else
421 MCOperand_CreateReg0(Inst, ARM_CPSR);
422 return MCDisassembler_Success;
423 }
424
425 #define GET_REGINFO_MC_DESC
426 #include "ARMGenRegisterInfo.inc"
ARM_init(MCRegisterInfo * MRI)427 void ARM_init(MCRegisterInfo *MRI)
428 {
429 /*
430 InitMCRegisterInfo(ARMRegDesc, 289,
431 RA, PC,
432 ARMMCRegisterClasses, 100,
433 ARMRegUnitRoots, 77, ARMRegDiffLists, ARMRegStrings,
434 ARMSubRegIdxLists, 57,
435 ARMSubRegIdxRanges, ARMRegEncodingTable);
436 */
437
438 MCRegisterInfo_InitMCRegisterInfo(MRI, ARMRegDesc, 289,
439 0, 0,
440 ARMMCRegisterClasses, 100,
441 0, 0, ARMRegDiffLists, 0,
442 ARMSubRegIdxLists, 57,
443 0);
444 }
445
446 // Post-decoding checks
checkDecodedInstruction(MCInst * MI,uint32_t Insn,DecodeStatus Result)447 static DecodeStatus checkDecodedInstruction(MCInst *MI,
448 uint32_t Insn,
449 DecodeStatus Result)
450 {
451 switch (MCInst_getOpcode(MI)) {
452 case ARM_HVC: {
453 // HVC is undefined if condition = 0xf otherwise upredictable
454 // if condition != 0xe
455 uint32_t Cond = (Insn >> 28) & 0xF;
456 if (Cond == 0xF)
457 return MCDisassembler_Fail;
458 if (Cond != 0xE)
459 return MCDisassembler_SoftFail;
460 return Result;
461 }
462 default:
463 return Result;
464 }
465 }
466
_ARM_getInstruction(cs_struct * ud,MCInst * MI,const uint8_t * code,size_t code_len,uint16_t * Size,uint64_t Address)467 static DecodeStatus _ARM_getInstruction(cs_struct *ud, MCInst *MI, const uint8_t *code, size_t code_len,
468 uint16_t *Size, uint64_t Address)
469 {
470 uint32_t insn, i;
471 DecodeStatus result;
472
473 if (code_len < 4)
474 // not enough data
475 return MCDisassembler_Fail;
476
477 if (MI->flat_insn->detail) {
478 memset(MI->flat_insn->detail, 0, offsetof(cs_detail, arm)+sizeof(cs_arm));
479 for (i = 0; i < ARR_SIZE(MI->flat_insn->detail->arm.operands); i++) {
480 MI->flat_insn->detail->arm.operands[i].vector_index = -1;
481 MI->flat_insn->detail->arm.operands[i].neon_lane = -1;
482 }
483 }
484
485 if (MODE_IS_BIG_ENDIAN(ud->mode))
486 insn = (code[3] << 0) |
487 (code[2] << 8) |
488 (code[1] << 16) |
489 ((uint32_t) code[0] << 24);
490 else
491 insn = ((uint32_t) code[3] << 24) |
492 (code[2] << 16) |
493 (code[1] << 8) |
494 (code[0] << 0);
495
496 // Calling the auto-generated decoder function.
497 result = decodeInstruction_4(DecoderTableARM32, MI, insn, Address, NULL, ud->mode);
498 if (result != MCDisassembler_Fail) {
499 result = checkDecodedInstruction(MI, insn, result);
500 if (result != MCDisassembler_Fail)
501 *Size = 4;
502 return result;
503 }
504
505 // VFP and NEON instructions, similarly, are shared between ARM
506 // and Thumb modes.
507 MCInst_clear(MI);
508 result = decodeInstruction_4(DecoderTableVFP32, MI, insn, Address, NULL, ud->mode);
509 if (result != MCDisassembler_Fail) {
510 *Size = 4;
511 return result;
512 }
513
514 MCInst_clear(MI);
515 result = decodeInstruction_4(DecoderTableVFPV832, MI, insn, Address, NULL, ud->mode);
516 if (result != MCDisassembler_Fail) {
517 *Size = 4;
518 return result;
519 }
520
521 MCInst_clear(MI);
522 result = decodeInstruction_4(DecoderTableNEONData32, MI, insn, Address, NULL, ud->mode);
523 if (result != MCDisassembler_Fail) {
524 *Size = 4;
525 // Add a fake predicate operand, because we share these instruction
526 // definitions with Thumb2 where these instructions are predicable.
527 if (!DecodePredicateOperand(MI, 0xE, Address, NULL))
528 return MCDisassembler_Fail;
529 return result;
530 }
531
532 MCInst_clear(MI);
533 result = decodeInstruction_4(DecoderTableNEONLoadStore32, MI, insn, Address, NULL, ud->mode);
534 if (result != MCDisassembler_Fail) {
535 *Size = 4;
536 // Add a fake predicate operand, because we share these instruction
537 // definitions with Thumb2 where these instructions are predicable.
538 if (!DecodePredicateOperand(MI, 0xE, Address, NULL))
539 return MCDisassembler_Fail;
540 return result;
541 }
542
543 MCInst_clear(MI);
544 result = decodeInstruction_4(DecoderTableNEONDup32, MI, insn, Address, NULL, ud->mode);
545 if (result != MCDisassembler_Fail) {
546 *Size = 4;
547 // Add a fake predicate operand, because we share these instruction
548 // definitions with Thumb2 where these instructions are predicable.
549 if (!DecodePredicateOperand(MI, 0xE, Address, NULL))
550 return MCDisassembler_Fail;
551 return result;
552 }
553
554 MCInst_clear(MI);
555 result = decodeInstruction_4(DecoderTablev8NEON32, MI, insn, Address, NULL, ud->mode);
556 if (result != MCDisassembler_Fail) {
557 *Size = 4;
558 return result;
559 }
560
561 MCInst_clear(MI);
562 result = decodeInstruction_4(DecoderTablev8Crypto32, MI, insn, Address, NULL, ud->mode);
563 if (result != MCDisassembler_Fail) {
564 *Size = 4;
565 return result;
566 }
567
568 MCInst_clear(MI);
569 *Size = 0;
570 return MCDisassembler_Fail;
571 }
572
573 // Thumb1 instructions don't have explicit S bits. Rather, they
574 // implicitly set CPSR. Since it's not represented in the encoding, the
575 // auto-generated decoder won't inject the CPSR operand. We need to fix
576 // that as a post-pass.
AddThumb1SBit(MCInst * MI,bool InITBlock)577 static void AddThumb1SBit(MCInst *MI, bool InITBlock)
578 {
579 const MCOperandInfo *OpInfo = ARMInsts[MCInst_getOpcode(MI)].OpInfo;
580 unsigned short NumOps = ARMInsts[MCInst_getOpcode(MI)].NumOperands;
581 unsigned i;
582
583 for (i = 0; i < NumOps; ++i) {
584 if (i == MCInst_getNumOperands(MI)) break;
585 if (MCOperandInfo_isOptionalDef(&OpInfo[i]) && OpInfo[i].RegClass == ARM_CCRRegClassID) {
586 if (i > 0 && MCOperandInfo_isPredicate(&OpInfo[i-1])) continue;
587 MCInst_insert0(MI, i, MCOperand_CreateReg1(MI, InITBlock ? 0 : ARM_CPSR));
588 return;
589 }
590 }
591
592 //MI.insert(I, MCOperand_CreateReg0(Inst, InITBlock ? 0 : ARM_CPSR));
593 MCInst_insert0(MI, i, MCOperand_CreateReg1(MI, InITBlock ? 0 : ARM_CPSR));
594 }
595
596 // Most Thumb instructions don't have explicit predicates in the
597 // encoding, but rather get their predicates from IT context. We need
598 // to fix up the predicate operands using this context information as a
599 // post-pass.
AddThumbPredicate(cs_struct * ud,MCInst * MI)600 static DecodeStatus AddThumbPredicate(cs_struct *ud, MCInst *MI)
601 {
602 DecodeStatus S = MCDisassembler_Success;
603 const MCOperandInfo *OpInfo;
604 unsigned short NumOps;
605 unsigned int i;
606 unsigned CC;
607
608 // A few instructions actually have predicates encoded in them. Don't
609 // try to overwrite it if we're seeing one of those.
610 switch (MCInst_getOpcode(MI)) {
611 case ARM_tBcc:
612 case ARM_t2Bcc:
613 case ARM_tCBZ:
614 case ARM_tCBNZ:
615 case ARM_tCPS:
616 case ARM_t2CPS3p:
617 case ARM_t2CPS2p:
618 case ARM_t2CPS1p:
619 case ARM_tMOVSr:
620 case ARM_tSETEND:
621 // Some instructions (mostly conditional branches) are not
622 // allowed in IT blocks.
623 if (ITStatus_instrInITBlock(&(ud->ITBlock)))
624 S = MCDisassembler_SoftFail;
625 else
626 return MCDisassembler_Success;
627 break;
628 case ARM_tB:
629 case ARM_t2B:
630 case ARM_t2TBB:
631 case ARM_t2TBH:
632 // Some instructions (mostly unconditional branches) can
633 // only appears at the end of, or outside of, an IT.
634 //if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock())
635 if (ITStatus_instrInITBlock(&(ud->ITBlock)) && !ITStatus_instrLastInITBlock(&(ud->ITBlock)))
636 S = MCDisassembler_SoftFail;
637 break;
638 default:
639 break;
640 }
641
642 // If we're in an IT block, base the predicate on that. Otherwise,
643 // assume a predicate of AL.
644 CC = ITStatus_getITCC(&(ud->ITBlock));
645 if (CC == 0xF)
646 CC = ARMCC_AL;
647 if (ITStatus_instrInITBlock(&(ud->ITBlock)))
648 ITStatus_advanceITState(&(ud->ITBlock));
649
650 OpInfo = ARMInsts[MCInst_getOpcode(MI)].OpInfo;
651 NumOps = ARMInsts[MCInst_getOpcode(MI)].NumOperands;
652
653 for (i = 0; i < NumOps; ++i) {
654 if (i == MCInst_getNumOperands(MI)) break;
655 if (MCOperandInfo_isPredicate(&OpInfo[i])) {
656 MCInst_insert0(MI, i, MCOperand_CreateImm1(MI, CC));
657 if (CC == ARMCC_AL)
658 MCInst_insert0(MI, i+1, MCOperand_CreateReg1(MI, 0));
659 else
660 MCInst_insert0(MI, i+1, MCOperand_CreateReg1(MI, ARM_CPSR));
661 return S;
662 }
663 }
664
665 MCInst_insert0(MI, i, MCOperand_CreateImm1(MI, CC));
666 if (CC == ARMCC_AL)
667 MCInst_insert0(MI, i+1, MCOperand_CreateReg1(MI, 0));
668 else
669 MCInst_insert0(MI, i+1, MCOperand_CreateReg1(MI, ARM_CPSR));
670
671 return S;
672 }
673
674 // Thumb VFP instructions are a special case. Because we share their
675 // encodings between ARM and Thumb modes, and they are predicable in ARM
676 // mode, the auto-generated decoder will give them an (incorrect)
677 // predicate operand. We need to rewrite these operands based on the IT
678 // context as a post-pass.
UpdateThumbVFPPredicate(cs_struct * ud,MCInst * MI)679 static void UpdateThumbVFPPredicate(cs_struct *ud, MCInst *MI)
680 {
681 unsigned CC;
682 unsigned short NumOps;
683 const MCOperandInfo *OpInfo;
684 unsigned i;
685
686 CC = ITStatus_getITCC(&(ud->ITBlock));
687 if (ITStatus_instrInITBlock(&(ud->ITBlock)))
688 ITStatus_advanceITState(&(ud->ITBlock));
689
690 OpInfo = ARMInsts[MCInst_getOpcode(MI)].OpInfo;
691 NumOps = ARMInsts[MCInst_getOpcode(MI)].NumOperands;
692
693 for (i = 0; i < NumOps; ++i) {
694 if (MCOperandInfo_isPredicate(&OpInfo[i])) {
695 MCOperand_setImm(MCInst_getOperand(MI, i), CC);
696 if (CC == ARMCC_AL)
697 MCOperand_setReg(MCInst_getOperand(MI, i+1), 0);
698 else
699 MCOperand_setReg(MCInst_getOperand(MI, i+1), ARM_CPSR);
700 return;
701 }
702 }
703 }
704
_Thumb_getInstruction(cs_struct * ud,MCInst * MI,const uint8_t * code,size_t code_len,uint16_t * Size,uint64_t Address)705 static DecodeStatus _Thumb_getInstruction(cs_struct *ud, MCInst *MI, const uint8_t *code, size_t code_len,
706 uint16_t *Size, uint64_t Address)
707 {
708 uint16_t insn16;
709 DecodeStatus result;
710 bool InITBlock;
711 unsigned Firstcond, Mask;
712 uint32_t NEONLdStInsn, insn32, NEONDataInsn, NEONCryptoInsn, NEONv8Insn;
713 size_t i;
714
715 // We want to read exactly 2 bytes of data.
716 if (code_len < 2)
717 // not enough data
718 return MCDisassembler_Fail;
719
720 if (MI->flat_insn->detail) {
721 memset(MI->flat_insn->detail, 0, offsetof(cs_detail, arm)+sizeof(cs_arm));
722 for (i = 0; i < ARR_SIZE(MI->flat_insn->detail->arm.operands); i++) {
723 MI->flat_insn->detail->arm.operands[i].vector_index = -1;
724 MI->flat_insn->detail->arm.operands[i].neon_lane = -1;
725 }
726 }
727
728 if (MODE_IS_BIG_ENDIAN(ud->mode))
729 insn16 = (code[0] << 8) | code[1];
730 else
731 insn16 = (code[1] << 8) | code[0];
732
733 result = decodeInstruction_2(DecoderTableThumb16, MI, insn16, Address, NULL, ud->mode);
734 if (result != MCDisassembler_Fail) {
735 *Size = 2;
736 Check(&result, AddThumbPredicate(ud, MI));
737 return result;
738 }
739
740 MCInst_clear(MI);
741 result = decodeInstruction_2(DecoderTableThumbSBit16, MI, insn16, Address, NULL, ud->mode);
742 if (result) {
743 *Size = 2;
744 InITBlock = ITStatus_instrInITBlock(&(ud->ITBlock));
745 Check(&result, AddThumbPredicate(ud, MI));
746 AddThumb1SBit(MI, InITBlock);
747 return result;
748 }
749
750 MCInst_clear(MI);
751 result = decodeInstruction_2(DecoderTableThumb216, MI, insn16, Address, NULL, ud->mode);
752 if (result != MCDisassembler_Fail) {
753 *Size = 2;
754
755 // Nested IT blocks are UNPREDICTABLE. Must be checked before we add
756 // the Thumb predicate.
757 if (MCInst_getOpcode(MI) == ARM_t2IT && ITStatus_instrInITBlock(&(ud->ITBlock)))
758 return MCDisassembler_SoftFail;
759 Check(&result, AddThumbPredicate(ud, MI));
760
761 // If we find an IT instruction, we need to parse its condition
762 // code and mask operands so that we can apply them correctly
763 // to the subsequent instructions.
764 if (MCInst_getOpcode(MI) == ARM_t2IT) {
765
766 Firstcond = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, 0));
767 Mask = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, 1));
768 ITStatus_setITState(&(ud->ITBlock), (char)Firstcond, (char)Mask);
769 }
770
771 return result;
772 }
773
774 // We want to read exactly 4 bytes of data.
775 if (code_len < 4)
776 // not enough data
777 return MCDisassembler_Fail;
778
779 if (MODE_IS_BIG_ENDIAN(ud->mode))
780 insn32 = (code[3] << 0) |
781 (code[2] << 8) |
782 (code[1] << 16) |
783 ((uint32_t) code[0] << 24);
784 else
785 insn32 = (code[3] << 8) |
786 (code[2] << 0) |
787 ((uint32_t) code[1] << 24) |
788 (code[0] << 16);
789
790 MCInst_clear(MI);
791 result = decodeInstruction_4(DecoderTableThumb32, MI, insn32, Address, NULL, ud->mode);
792 if (result != MCDisassembler_Fail) {
793 *Size = 4;
794 InITBlock = ITStatus_instrInITBlock(&(ud->ITBlock));
795 Check(&result, AddThumbPredicate(ud, MI));
796 AddThumb1SBit(MI, InITBlock);
797 return result;
798 }
799
800 MCInst_clear(MI);
801 result = decodeInstruction_4(DecoderTableThumb232, MI, insn32, Address, NULL, ud->mode);
802 if (result != MCDisassembler_Fail) {
803 *Size = 4;
804 Check(&result, AddThumbPredicate(ud, MI));
805 return result;
806 }
807
808 MCInst_clear(MI);
809 result = decodeInstruction_4(DecoderTableVFP32, MI, insn32, Address, NULL, ud->mode);
810 if (result != MCDisassembler_Fail) {
811 *Size = 4;
812 UpdateThumbVFPPredicate(ud, MI);
813 return result;
814 }
815
816 if (fieldFromInstruction_4(insn32, 28, 4) == 0xE) {
817 MCInst_clear(MI);
818 result = decodeInstruction_4(DecoderTableVFP32, MI, insn32, Address, NULL, ud->mode);
819 if (result != MCDisassembler_Fail) {
820 *Size = 4;
821 UpdateThumbVFPPredicate(ud, MI);
822 return result;
823 }
824 }
825
826 MCInst_clear(MI);
827 result = decodeInstruction_4(DecoderTableVFPV832, MI, insn32, Address, NULL, ud->mode);
828 if (result != MCDisassembler_Fail) {
829 *Size = 4;
830 return result;
831 }
832
833 if (fieldFromInstruction_4(insn32, 28, 4) == 0xE) {
834 MCInst_clear(MI);
835 result = decodeInstruction_4(DecoderTableNEONDup32, MI, insn32, Address, NULL, ud->mode);
836 if (result != MCDisassembler_Fail) {
837 *Size = 4;
838 Check(&result, AddThumbPredicate(ud, MI));
839 return result;
840 }
841 }
842
843 if (fieldFromInstruction_4(insn32, 24, 8) == 0xF9) {
844 MCInst_clear(MI);
845 NEONLdStInsn = insn32;
846 NEONLdStInsn &= 0xF0FFFFFF;
847 NEONLdStInsn |= 0x04000000;
848 result = decodeInstruction_4(DecoderTableNEONLoadStore32, MI, NEONLdStInsn, Address, NULL, ud->mode);
849 if (result != MCDisassembler_Fail) {
850 *Size = 4;
851 Check(&result, AddThumbPredicate(ud, MI));
852 return result;
853 }
854 }
855
856 if (fieldFromInstruction_4(insn32, 24, 4) == 0xF) {
857 MCInst_clear(MI);
858 NEONDataInsn = insn32;
859 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24
860 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
861 NEONDataInsn |= 0x12000000; // Set bits 28 and 25
862 result = decodeInstruction_4(DecoderTableNEONData32, MI, NEONDataInsn, Address, NULL, ud->mode);
863 if (result != MCDisassembler_Fail) {
864 *Size = 4;
865 Check(&result, AddThumbPredicate(ud, MI));
866 return result;
867 }
868 }
869
870 MCInst_clear(MI);
871 NEONCryptoInsn = insn32;
872 NEONCryptoInsn &= 0xF0FFFFFF; // Clear bits 27-24
873 NEONCryptoInsn |= (NEONCryptoInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
874 NEONCryptoInsn |= 0x12000000; // Set bits 28 and 25
875 result = decodeInstruction_4(DecoderTablev8Crypto32, MI, NEONCryptoInsn,
876 Address, NULL, ud->mode);
877 if (result != MCDisassembler_Fail) {
878 *Size = 4;
879 return result;
880 }
881
882 MCInst_clear(MI);
883 NEONv8Insn = insn32;
884 NEONv8Insn &= 0xF3FFFFFF; // Clear bits 27-26
885 result = decodeInstruction_4(DecoderTablev8NEON32, MI, NEONv8Insn, Address, NULL, ud->mode);
886 if (result != MCDisassembler_Fail) {
887 *Size = 4;
888 return result;
889 }
890
891 MCInst_clear(MI);
892 *Size = 0;
893 return MCDisassembler_Fail;
894 }
895
Thumb_getInstruction(csh ud,const uint8_t * code,size_t code_len,MCInst * instr,uint16_t * size,uint64_t address,void * info)896 bool Thumb_getInstruction(csh ud, const uint8_t *code, size_t code_len, MCInst *instr,
897 uint16_t *size, uint64_t address, void *info)
898 {
899 DecodeStatus status = _Thumb_getInstruction((cs_struct *)ud, instr, code, code_len, size, address);
900
901 //return status == MCDisassembler_Success;
902 return status != MCDisassembler_Fail;
903 }
904
ARM_getInstruction(csh ud,const uint8_t * code,size_t code_len,MCInst * instr,uint16_t * size,uint64_t address,void * info)905 bool ARM_getInstruction(csh ud, const uint8_t *code, size_t code_len, MCInst *instr,
906 uint16_t *size, uint64_t address, void *info)
907 {
908 DecodeStatus status = _ARM_getInstruction((cs_struct *)ud, instr, code, code_len, size, address);
909
910 //return status == MCDisassembler_Success;
911 return status != MCDisassembler_Fail;
912 }
913
914 static const uint16_t GPRDecoderTable[] = {
915 ARM_R0, ARM_R1, ARM_R2, ARM_R3,
916 ARM_R4, ARM_R5, ARM_R6, ARM_R7,
917 ARM_R8, ARM_R9, ARM_R10, ARM_R11,
918 ARM_R12, ARM_SP, ARM_LR, ARM_PC
919 };
920
DecodeGPRRegisterClass(MCInst * Inst,unsigned RegNo,uint64_t Address,const void * Decoder)921 static DecodeStatus DecodeGPRRegisterClass(MCInst *Inst, unsigned RegNo,
922 uint64_t Address, const void *Decoder)
923 {
924 unsigned Register;
925 if (RegNo > 15)
926 return MCDisassembler_Fail;
927
928 Register = GPRDecoderTable[RegNo];
929 MCOperand_CreateReg0(Inst, Register);
930 return MCDisassembler_Success;
931 }
932
DecodeGPRnopcRegisterClass(MCInst * Inst,unsigned RegNo,uint64_t Address,const void * Decoder)933 static DecodeStatus DecodeGPRnopcRegisterClass(MCInst *Inst, unsigned RegNo,
934 uint64_t Address, const void *Decoder)
935 {
936 DecodeStatus S = MCDisassembler_Success;
937
938 if (RegNo == 15)
939 S = MCDisassembler_SoftFail;
940
941 Check(&S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
942
943 return S;
944 }
945
DecodeGPRwithAPSRRegisterClass(MCInst * Inst,unsigned RegNo,uint64_t Address,const void * Decoder)946 static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst *Inst, unsigned RegNo,
947 uint64_t Address, const void *Decoder)
948 {
949 DecodeStatus S = MCDisassembler_Success;
950
951 if (RegNo == 15) {
952 MCOperand_CreateReg0(Inst, ARM_APSR_NZCV);
953 return MCDisassembler_Success;
954 }
955
956 Check(&S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
957 return S;
958 }
959
DecodetGPRRegisterClass(MCInst * Inst,unsigned RegNo,uint64_t Address,const void * Decoder)960 static DecodeStatus DecodetGPRRegisterClass(MCInst *Inst, unsigned RegNo,
961 uint64_t Address, const void *Decoder)
962 {
963 if (RegNo > 7)
964 return MCDisassembler_Fail;
965 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
966 }
967
968 static const uint16_t GPRPairDecoderTable[] = {
969 ARM_R0_R1, ARM_R2_R3, ARM_R4_R5, ARM_R6_R7,
970 ARM_R8_R9, ARM_R10_R11, ARM_R12_SP
971 };
972
DecodeGPRPairRegisterClass(MCInst * Inst,unsigned RegNo,uint64_t Address,const void * Decoder)973 static DecodeStatus DecodeGPRPairRegisterClass(MCInst *Inst, unsigned RegNo,
974 uint64_t Address, const void *Decoder)
975 {
976 unsigned RegisterPair;
977 DecodeStatus S = MCDisassembler_Success;
978
979 if (RegNo > 13)
980 return MCDisassembler_Fail;
981
982 if ((RegNo & 1) || RegNo == 0xe)
983 S = MCDisassembler_SoftFail;
984
985 RegisterPair = GPRPairDecoderTable[RegNo/2];
986 MCOperand_CreateReg0(Inst, RegisterPair);
987 return S;
988 }
989
DecodetcGPRRegisterClass(MCInst * Inst,unsigned RegNo,uint64_t Address,const void * Decoder)990 static DecodeStatus DecodetcGPRRegisterClass(MCInst *Inst, unsigned RegNo,
991 uint64_t Address, const void *Decoder)
992 {
993 unsigned Register = 0;
994 switch (RegNo) {
995 case 0:
996 Register = ARM_R0;
997 break;
998 case 1:
999 Register = ARM_R1;
1000 break;
1001 case 2:
1002 Register = ARM_R2;
1003 break;
1004 case 3:
1005 Register = ARM_R3;
1006 break;
1007 case 9:
1008 Register = ARM_R9;
1009 break;
1010 case 12:
1011 Register = ARM_R12;
1012 break;
1013 default:
1014 return MCDisassembler_Fail;
1015 }
1016
1017 MCOperand_CreateReg0(Inst, Register);
1018 return MCDisassembler_Success;
1019 }
1020
DecoderGPRRegisterClass(MCInst * Inst,unsigned RegNo,uint64_t Address,const void * Decoder)1021 static DecodeStatus DecoderGPRRegisterClass(MCInst *Inst, unsigned RegNo,
1022 uint64_t Address, const void *Decoder)
1023 {
1024 DecodeStatus S = MCDisassembler_Success;
1025 if (RegNo == 13 || RegNo == 15)
1026 S = MCDisassembler_SoftFail;
1027 Check(&S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
1028 return S;
1029 }
1030
1031 static const uint16_t SPRDecoderTable[] = {
1032 ARM_S0, ARM_S1, ARM_S2, ARM_S3,
1033 ARM_S4, ARM_S5, ARM_S6, ARM_S7,
1034 ARM_S8, ARM_S9, ARM_S10, ARM_S11,
1035 ARM_S12, ARM_S13, ARM_S14, ARM_S15,
1036 ARM_S16, ARM_S17, ARM_S18, ARM_S19,
1037 ARM_S20, ARM_S21, ARM_S22, ARM_S23,
1038 ARM_S24, ARM_S25, ARM_S26, ARM_S27,
1039 ARM_S28, ARM_S29, ARM_S30, ARM_S31
1040 };
1041
DecodeSPRRegisterClass(MCInst * Inst,unsigned RegNo,uint64_t Address,const void * Decoder)1042 static DecodeStatus DecodeSPRRegisterClass(MCInst *Inst, unsigned RegNo,
1043 uint64_t Address, const void *Decoder)
1044 {
1045 unsigned Register;
1046 if (RegNo > 31)
1047 return MCDisassembler_Fail;
1048
1049 Register = SPRDecoderTable[RegNo];
1050 MCOperand_CreateReg0(Inst, Register);
1051 return MCDisassembler_Success;
1052 }
1053
1054 static const uint16_t DPRDecoderTable[] = {
1055 ARM_D0, ARM_D1, ARM_D2, ARM_D3,
1056 ARM_D4, ARM_D5, ARM_D6, ARM_D7,
1057 ARM_D8, ARM_D9, ARM_D10, ARM_D11,
1058 ARM_D12, ARM_D13, ARM_D14, ARM_D15,
1059 ARM_D16, ARM_D17, ARM_D18, ARM_D19,
1060 ARM_D20, ARM_D21, ARM_D22, ARM_D23,
1061 ARM_D24, ARM_D25, ARM_D26, ARM_D27,
1062 ARM_D28, ARM_D29, ARM_D30, ARM_D31
1063 };
1064
DecodeDPRRegisterClass(MCInst * Inst,unsigned RegNo,uint64_t Address,const void * Decoder)1065 static DecodeStatus DecodeDPRRegisterClass(MCInst *Inst, unsigned RegNo,
1066 uint64_t Address, const void *Decoder)
1067 {
1068 unsigned Register;
1069
1070 //uint64_t featureBits = ARM_getFeatureBits(Inst->csh->mode);
1071 //bool hasD16 = featureBits & ARM_FeatureD16;
1072
1073 //if (RegNo > 31 || (hasD16 && RegNo > 15)) // FIXME
1074 if (RegNo > 31)
1075 return MCDisassembler_Fail;
1076
1077 Register = DPRDecoderTable[RegNo];
1078 MCOperand_CreateReg0(Inst, Register);
1079
1080 return MCDisassembler_Success;
1081 }
1082
DecodeDPR_8RegisterClass(MCInst * Inst,unsigned RegNo,uint64_t Address,const void * Decoder)1083 static DecodeStatus DecodeDPR_8RegisterClass(MCInst *Inst, unsigned RegNo,
1084 uint64_t Address, const void *Decoder)
1085 {
1086 if (RegNo > 7)
1087 return MCDisassembler_Fail;
1088 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
1089 }
1090
1091 static DecodeStatus
DecodeDPR_VFP2RegisterClass(MCInst * Inst,unsigned RegNo,uint64_t Address,const void * Decoder)1092 DecodeDPR_VFP2RegisterClass(MCInst *Inst, unsigned RegNo,
1093 uint64_t Address, const void *Decoder)
1094 {
1095 if (RegNo > 15)
1096 return MCDisassembler_Fail;
1097 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
1098 }
1099
1100 static const uint16_t QPRDecoderTable[] = {
1101 ARM_Q0, ARM_Q1, ARM_Q2, ARM_Q3,
1102 ARM_Q4, ARM_Q5, ARM_Q6, ARM_Q7,
1103 ARM_Q8, ARM_Q9, ARM_Q10, ARM_Q11,
1104 ARM_Q12, ARM_Q13, ARM_Q14, ARM_Q15
1105 };
1106
DecodeQPRRegisterClass(MCInst * Inst,unsigned RegNo,uint64_t Address,const void * Decoder)1107 static DecodeStatus DecodeQPRRegisterClass(MCInst *Inst, unsigned RegNo,
1108 uint64_t Address, const void *Decoder)
1109 {
1110 unsigned Register;
1111 if (RegNo > 31 || (RegNo & 1) != 0)
1112 return MCDisassembler_Fail;
1113 RegNo >>= 1;
1114
1115 Register = QPRDecoderTable[RegNo];
1116 MCOperand_CreateReg0(Inst, Register);
1117 return MCDisassembler_Success;
1118 }
1119
1120 static const uint16_t DPairDecoderTable[] = {
1121 ARM_Q0, ARM_D1_D2, ARM_Q1, ARM_D3_D4, ARM_Q2, ARM_D5_D6,
1122 ARM_Q3, ARM_D7_D8, ARM_Q4, ARM_D9_D10, ARM_Q5, ARM_D11_D12,
1123 ARM_Q6, ARM_D13_D14, ARM_Q7, ARM_D15_D16, ARM_Q8, ARM_D17_D18,
1124 ARM_Q9, ARM_D19_D20, ARM_Q10, ARM_D21_D22, ARM_Q11, ARM_D23_D24,
1125 ARM_Q12, ARM_D25_D26, ARM_Q13, ARM_D27_D28, ARM_Q14, ARM_D29_D30,
1126 ARM_Q15
1127 };
1128
DecodeDPairRegisterClass(MCInst * Inst,unsigned RegNo,uint64_t Address,const void * Decoder)1129 static DecodeStatus DecodeDPairRegisterClass(MCInst *Inst, unsigned RegNo,
1130 uint64_t Address, const void *Decoder)
1131 {
1132 unsigned Register;
1133 if (RegNo > 30)
1134 return MCDisassembler_Fail;
1135
1136 Register = DPairDecoderTable[RegNo];
1137 MCOperand_CreateReg0(Inst, Register);
1138 return MCDisassembler_Success;
1139 }
1140
1141 static const uint16_t DPairSpacedDecoderTable[] = {
1142 ARM_D0_D2, ARM_D1_D3, ARM_D2_D4, ARM_D3_D5,
1143 ARM_D4_D6, ARM_D5_D7, ARM_D6_D8, ARM_D7_D9,
1144 ARM_D8_D10, ARM_D9_D11, ARM_D10_D12, ARM_D11_D13,
1145 ARM_D12_D14, ARM_D13_D15, ARM_D14_D16, ARM_D15_D17,
1146 ARM_D16_D18, ARM_D17_D19, ARM_D18_D20, ARM_D19_D21,
1147 ARM_D20_D22, ARM_D21_D23, ARM_D22_D24, ARM_D23_D25,
1148 ARM_D24_D26, ARM_D25_D27, ARM_D26_D28, ARM_D27_D29,
1149 ARM_D28_D30, ARM_D29_D31
1150 };
1151
DecodeDPairSpacedRegisterClass(MCInst * Inst,unsigned RegNo,uint64_t Address,const void * Decoder)1152 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst *Inst,
1153 unsigned RegNo, uint64_t Address, const void *Decoder)
1154 {
1155 unsigned Register;
1156 if (RegNo > 29)
1157 return MCDisassembler_Fail;
1158
1159 Register = DPairSpacedDecoderTable[RegNo];
1160 MCOperand_CreateReg0(Inst, Register);
1161 return MCDisassembler_Success;
1162 }
1163
DecodeCCOutOperand(MCInst * Inst,unsigned Val,uint64_t Address,const void * Decoder)1164 static DecodeStatus DecodeCCOutOperand(MCInst *Inst, unsigned Val,
1165 uint64_t Address, const void *Decoder)
1166 {
1167 if (Val)
1168 MCOperand_CreateReg0(Inst, ARM_CPSR);
1169 else
1170 MCOperand_CreateReg0(Inst, 0);
1171 return MCDisassembler_Success;
1172 }
1173
DecodeSORegImmOperand(MCInst * Inst,unsigned Val,uint64_t Address,const void * Decoder)1174 static DecodeStatus DecodeSORegImmOperand(MCInst *Inst, unsigned Val,
1175 uint64_t Address, const void *Decoder)
1176 {
1177 DecodeStatus S = MCDisassembler_Success;
1178 ARM_AM_ShiftOpc Shift;
1179 unsigned Op;
1180 unsigned Rm = fieldFromInstruction_4(Val, 0, 4);
1181 unsigned type = fieldFromInstruction_4(Val, 5, 2);
1182 unsigned imm = fieldFromInstruction_4(Val, 7, 5);
1183
1184 // Register-immediate
1185 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1186 return MCDisassembler_Fail;
1187
1188 Shift = ARM_AM_lsl;
1189 switch (type) {
1190 case 0:
1191 Shift = ARM_AM_lsl;
1192 break;
1193 case 1:
1194 Shift = ARM_AM_lsr;
1195 break;
1196 case 2:
1197 Shift = ARM_AM_asr;
1198 break;
1199 case 3:
1200 Shift = ARM_AM_ror;
1201 break;
1202 }
1203
1204 if (Shift == ARM_AM_ror && imm == 0)
1205 Shift = ARM_AM_rrx;
1206
1207 Op = Shift | (imm << 3);
1208 MCOperand_CreateImm0(Inst, Op);
1209
1210 return S;
1211 }
1212
DecodeSORegRegOperand(MCInst * Inst,unsigned Val,uint64_t Address,const void * Decoder)1213 static DecodeStatus DecodeSORegRegOperand(MCInst *Inst, unsigned Val,
1214 uint64_t Address, const void *Decoder)
1215 {
1216 DecodeStatus S = MCDisassembler_Success;
1217 ARM_AM_ShiftOpc Shift;
1218
1219 unsigned Rm = fieldFromInstruction_4(Val, 0, 4);
1220 unsigned type = fieldFromInstruction_4(Val, 5, 2);
1221 unsigned Rs = fieldFromInstruction_4(Val, 8, 4);
1222
1223 // Register-register
1224 if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1225 return MCDisassembler_Fail;
1226 if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)))
1227 return MCDisassembler_Fail;
1228
1229 Shift = ARM_AM_lsl;
1230 switch (type) {
1231 case 0:
1232 Shift = ARM_AM_lsl;
1233 break;
1234 case 1:
1235 Shift = ARM_AM_lsr;
1236 break;
1237 case 2:
1238 Shift = ARM_AM_asr;
1239 break;
1240 case 3:
1241 Shift = ARM_AM_ror;
1242 break;
1243 }
1244
1245 MCOperand_CreateImm0(Inst, Shift);
1246
1247 return S;
1248 }
1249
DecodeRegListOperand(MCInst * Inst,unsigned Val,uint64_t Address,const void * Decoder)1250 static DecodeStatus DecodeRegListOperand(MCInst *Inst, unsigned Val,
1251 uint64_t Address, const void *Decoder)
1252 {
1253 unsigned i;
1254 DecodeStatus S = MCDisassembler_Success;
1255 unsigned opcode;
1256
1257 bool NeedDisjointWriteback = false;
1258 unsigned WritebackReg = 0;
1259
1260 opcode = MCInst_getOpcode(Inst);
1261 switch (opcode) {
1262 default:
1263 break;
1264 case ARM_LDMIA_UPD:
1265 case ARM_LDMDB_UPD:
1266 case ARM_LDMIB_UPD:
1267 case ARM_LDMDA_UPD:
1268 case ARM_t2LDMIA_UPD:
1269 case ARM_t2LDMDB_UPD:
1270 case ARM_t2STMIA_UPD:
1271 case ARM_t2STMDB_UPD:
1272 NeedDisjointWriteback = true;
1273 WritebackReg = MCOperand_getReg(MCInst_getOperand(Inst, 0));
1274 break;
1275 }
1276
1277 // Empty register lists are not allowed.
1278 if (Val == 0) return MCDisassembler_Fail;
1279 for (i = 0; i < 16; ++i) {
1280 if (Val & (1 << i)) {
1281 if (!Check(&S, DecodeGPRRegisterClass(Inst, i, Address, Decoder)))
1282 return MCDisassembler_Fail;
1283 // Writeback not allowed if Rn is in the target list.
1284 if (NeedDisjointWriteback && WritebackReg == MCOperand_getReg(&(Inst->Operands[Inst->size-1])))
1285 Check(&S, MCDisassembler_SoftFail);
1286 }
1287 }
1288
1289 if (opcode == ARM_t2LDMIA_UPD && WritebackReg == ARM_SP) {
1290 if (Val & (1 << 13) || ((Val & (1 << 15)) && (Val & (1 << 14)))) {
1291 // invalid thumb2 pop
1292 // needs no sp in reglist and not both pc and lr set at the same time
1293 return MCDisassembler_Fail;
1294 }
1295 }
1296
1297 return S;
1298 }
1299
DecodeSPRRegListOperand(MCInst * Inst,unsigned Val,uint64_t Address,const void * Decoder)1300 static DecodeStatus DecodeSPRRegListOperand(MCInst *Inst, unsigned Val,
1301 uint64_t Address, const void *Decoder)
1302 {
1303 DecodeStatus S = MCDisassembler_Success;
1304 unsigned i;
1305 unsigned Vd = fieldFromInstruction_4(Val, 8, 5);
1306 unsigned regs = fieldFromInstruction_4(Val, 0, 8);
1307
1308 // In case of unpredictable encoding, tweak the operands.
1309 if (regs == 0 || (Vd + regs) > 32) {
1310 regs = Vd + regs > 32 ? 32 - Vd : regs;
1311 regs = (1u > regs? 1u : regs);
1312 S = MCDisassembler_SoftFail;
1313 }
1314
1315 if (!Check(&S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder)))
1316 return MCDisassembler_Fail;
1317 for (i = 0; i < (regs - 1); ++i) {
1318 if (!Check(&S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder)))
1319 return MCDisassembler_Fail;
1320 }
1321
1322 return S;
1323 }
1324
DecodeDPRRegListOperand(MCInst * Inst,unsigned Val,uint64_t Address,const void * Decoder)1325 static DecodeStatus DecodeDPRRegListOperand(MCInst *Inst, unsigned Val,
1326 uint64_t Address, const void *Decoder)
1327 {
1328 DecodeStatus S = MCDisassembler_Success;
1329 unsigned i;
1330 unsigned Vd = fieldFromInstruction_4(Val, 8, 5);
1331 unsigned regs = fieldFromInstruction_4(Val, 1, 7);
1332
1333 // In case of unpredictable encoding, tweak the operands.
1334 if (regs == 0 || regs > 16 || (Vd + regs) > 32) {
1335 regs = Vd + regs > 32 ? 32 - Vd : regs;
1336 regs = (1u > regs? 1u : regs);
1337 regs = (16u > regs? regs : 16u);
1338 S = MCDisassembler_SoftFail;
1339 }
1340
1341 if (!Check(&S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
1342 return MCDisassembler_Fail;
1343
1344 for (i = 0; i < (regs - 1); ++i) {
1345 if (!Check(&S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder)))
1346 return MCDisassembler_Fail;
1347 }
1348
1349 return S;
1350 }
1351
DecodeBitfieldMaskOperand(MCInst * Inst,unsigned Val,uint64_t Address,const void * Decoder)1352 static DecodeStatus DecodeBitfieldMaskOperand(MCInst *Inst, unsigned Val,
1353 uint64_t Address, const void *Decoder)
1354 {
1355 // This operand encodes a mask of contiguous zeros between a specified MSB
1356 // and LSB. To decode it, we create the mask of all bits MSB-and-lower,
1357 // the mask of all bits LSB-and-lower, and then xor them to create
1358 // the mask of that's all ones on [msb, lsb]. Finally we not it to
1359 // create the final mask.
1360 unsigned msb = fieldFromInstruction_4(Val, 5, 5);
1361 unsigned lsb = fieldFromInstruction_4(Val, 0, 5);
1362 uint32_t lsb_mask, msb_mask;
1363
1364 DecodeStatus S = MCDisassembler_Success;
1365 if (lsb > msb) {
1366 Check(&S, MCDisassembler_SoftFail);
1367 // The check above will cause the warning for the "potentially undefined
1368 // instruction encoding" but we can't build a bad MCOperand value here
1369 // with a lsb > msb or else printing the MCInst will cause a crash.
1370 lsb = msb;
1371 }
1372
1373 msb_mask = 0xFFFFFFFF;
1374 if (msb != 31) msb_mask = (1U << (msb+1)) - 1;
1375 lsb_mask = (1U << lsb) - 1;
1376
1377 MCOperand_CreateImm0(Inst, ~(msb_mask ^ lsb_mask));
1378 return S;
1379 }
1380
DecodeCopMemInstruction(MCInst * Inst,unsigned Insn,uint64_t Address,const void * Decoder)1381 static DecodeStatus DecodeCopMemInstruction(MCInst *Inst, unsigned Insn,
1382 uint64_t Address, const void *Decoder)
1383 {
1384 DecodeStatus S = MCDisassembler_Success;
1385
1386 unsigned pred = fieldFromInstruction_4(Insn, 28, 4);
1387 unsigned CRd = fieldFromInstruction_4(Insn, 12, 4);
1388 unsigned coproc = fieldFromInstruction_4(Insn, 8, 4);
1389 unsigned imm = fieldFromInstruction_4(Insn, 0, 8);
1390 unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
1391 unsigned U = fieldFromInstruction_4(Insn, 23, 1);
1392
1393 switch (MCInst_getOpcode(Inst)) {
1394 case ARM_LDC_OFFSET:
1395 case ARM_LDC_PRE:
1396 case ARM_LDC_POST:
1397 case ARM_LDC_OPTION:
1398 case ARM_LDCL_OFFSET:
1399 case ARM_LDCL_PRE:
1400 case ARM_LDCL_POST:
1401 case ARM_LDCL_OPTION:
1402 case ARM_STC_OFFSET:
1403 case ARM_STC_PRE:
1404 case ARM_STC_POST:
1405 case ARM_STC_OPTION:
1406 case ARM_STCL_OFFSET:
1407 case ARM_STCL_PRE:
1408 case ARM_STCL_POST:
1409 case ARM_STCL_OPTION:
1410 case ARM_t2LDC_OFFSET:
1411 case ARM_t2LDC_PRE:
1412 case ARM_t2LDC_POST:
1413 case ARM_t2LDC_OPTION:
1414 case ARM_t2LDCL_OFFSET:
1415 case ARM_t2LDCL_PRE:
1416 case ARM_t2LDCL_POST:
1417 case ARM_t2LDCL_OPTION:
1418 case ARM_t2STC_OFFSET:
1419 case ARM_t2STC_PRE:
1420 case ARM_t2STC_POST:
1421 case ARM_t2STC_OPTION:
1422 case ARM_t2STCL_OFFSET:
1423 case ARM_t2STCL_PRE:
1424 case ARM_t2STCL_POST:
1425 case ARM_t2STCL_OPTION:
1426 if (coproc == 0xA || coproc == 0xB)
1427 return MCDisassembler_Fail;
1428 break;
1429 default:
1430 break;
1431 }
1432
1433 MCOperand_CreateImm0(Inst, coproc);
1434 MCOperand_CreateImm0(Inst, CRd);
1435 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1436 return MCDisassembler_Fail;
1437
1438 switch (MCInst_getOpcode(Inst)) {
1439 case ARM_t2LDC2_OFFSET:
1440 case ARM_t2LDC2L_OFFSET:
1441 case ARM_t2LDC2_PRE:
1442 case ARM_t2LDC2L_PRE:
1443 case ARM_t2STC2_OFFSET:
1444 case ARM_t2STC2L_OFFSET:
1445 case ARM_t2STC2_PRE:
1446 case ARM_t2STC2L_PRE:
1447 case ARM_LDC2_OFFSET:
1448 case ARM_LDC2L_OFFSET:
1449 case ARM_LDC2_PRE:
1450 case ARM_LDC2L_PRE:
1451 case ARM_STC2_OFFSET:
1452 case ARM_STC2L_OFFSET:
1453 case ARM_STC2_PRE:
1454 case ARM_STC2L_PRE:
1455 case ARM_t2LDC_OFFSET:
1456 case ARM_t2LDCL_OFFSET:
1457 case ARM_t2LDC_PRE:
1458 case ARM_t2LDCL_PRE:
1459 case ARM_t2STC_OFFSET:
1460 case ARM_t2STCL_OFFSET:
1461 case ARM_t2STC_PRE:
1462 case ARM_t2STCL_PRE:
1463 case ARM_LDC_OFFSET:
1464 case ARM_LDCL_OFFSET:
1465 case ARM_LDC_PRE:
1466 case ARM_LDCL_PRE:
1467 case ARM_STC_OFFSET:
1468 case ARM_STCL_OFFSET:
1469 case ARM_STC_PRE:
1470 case ARM_STCL_PRE:
1471 imm = ARM_AM_getAM5Opc(U ? ARM_AM_add : ARM_AM_sub, (unsigned char)imm);
1472 MCOperand_CreateImm0(Inst, imm);
1473 break;
1474 case ARM_t2LDC2_POST:
1475 case ARM_t2LDC2L_POST:
1476 case ARM_t2STC2_POST:
1477 case ARM_t2STC2L_POST:
1478 case ARM_LDC2_POST:
1479 case ARM_LDC2L_POST:
1480 case ARM_STC2_POST:
1481 case ARM_STC2L_POST:
1482 case ARM_t2LDC_POST:
1483 case ARM_t2LDCL_POST:
1484 case ARM_t2STC_POST:
1485 case ARM_t2STCL_POST:
1486 case ARM_LDC_POST:
1487 case ARM_LDCL_POST:
1488 case ARM_STC_POST:
1489 case ARM_STCL_POST:
1490 imm |= U << 8;
1491 // fall through.
1492 default:
1493 // The 'option' variant doesn't encode 'U' in the immediate since
1494 // the immediate is unsigned [0,255].
1495 MCOperand_CreateImm0(Inst, imm);
1496 break;
1497 }
1498
1499 switch (MCInst_getOpcode(Inst)) {
1500 case ARM_LDC_OFFSET:
1501 case ARM_LDC_PRE:
1502 case ARM_LDC_POST:
1503 case ARM_LDC_OPTION:
1504 case ARM_LDCL_OFFSET:
1505 case ARM_LDCL_PRE:
1506 case ARM_LDCL_POST:
1507 case ARM_LDCL_OPTION:
1508 case ARM_STC_OFFSET:
1509 case ARM_STC_PRE:
1510 case ARM_STC_POST:
1511 case ARM_STC_OPTION:
1512 case ARM_STCL_OFFSET:
1513 case ARM_STCL_PRE:
1514 case ARM_STCL_POST:
1515 case ARM_STCL_OPTION:
1516 if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1517 return MCDisassembler_Fail;
1518 break;
1519 default:
1520 break;
1521 }
1522
1523 return S;
1524 }
1525
DecodeAddrMode2IdxInstruction(MCInst * Inst,unsigned Insn,uint64_t Address,const void * Decoder)1526 static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst *Inst, unsigned Insn,
1527 uint64_t Address, const void *Decoder)
1528 {
1529 DecodeStatus S = MCDisassembler_Success;
1530 ARM_AM_AddrOpc Op;
1531 ARM_AM_ShiftOpc Opc;
1532 bool writeback;
1533 unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
1534 unsigned Rt = fieldFromInstruction_4(Insn, 12, 4);
1535 unsigned Rm = fieldFromInstruction_4(Insn, 0, 4);
1536 unsigned imm = fieldFromInstruction_4(Insn, 0, 12);
1537 unsigned pred = fieldFromInstruction_4(Insn, 28, 4);
1538 unsigned reg = fieldFromInstruction_4(Insn, 25, 1);
1539 unsigned P = fieldFromInstruction_4(Insn, 24, 1);
1540 unsigned W = fieldFromInstruction_4(Insn, 21, 1);
1541 unsigned idx_mode = 0, amt, tmp;
1542
1543 // On stores, the writeback operand precedes Rt.
1544 switch (MCInst_getOpcode(Inst)) {
1545 case ARM_STR_POST_IMM:
1546 case ARM_STR_POST_REG:
1547 case ARM_STRB_POST_IMM:
1548 case ARM_STRB_POST_REG:
1549 case ARM_STRT_POST_REG:
1550 case ARM_STRT_POST_IMM:
1551 case ARM_STRBT_POST_REG:
1552 case ARM_STRBT_POST_IMM:
1553 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1554 return MCDisassembler_Fail;
1555 break;
1556 default:
1557 break;
1558 }
1559
1560 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
1561 return MCDisassembler_Fail;
1562
1563 // On loads, the writeback operand comes after Rt.
1564 switch (MCInst_getOpcode(Inst)) {
1565 case ARM_LDR_POST_IMM:
1566 case ARM_LDR_POST_REG:
1567 case ARM_LDRB_POST_IMM:
1568 case ARM_LDRB_POST_REG:
1569 case ARM_LDRBT_POST_REG:
1570 case ARM_LDRBT_POST_IMM:
1571 case ARM_LDRT_POST_REG:
1572 case ARM_LDRT_POST_IMM:
1573 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1574 return MCDisassembler_Fail;
1575 break;
1576 default:
1577 break;
1578 }
1579
1580 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1581 return MCDisassembler_Fail;
1582
1583 Op = ARM_AM_add;
1584 if (!fieldFromInstruction_4(Insn, 23, 1))
1585 Op = ARM_AM_sub;
1586
1587 writeback = (P == 0) || (W == 1);
1588 if (P && writeback)
1589 idx_mode = ARMII_IndexModePre;
1590 else if (!P && writeback)
1591 idx_mode = ARMII_IndexModePost;
1592
1593 if (writeback && (Rn == 15 || Rn == Rt))
1594 S = MCDisassembler_SoftFail; // UNPREDICTABLE
1595
1596 if (reg) {
1597 if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1598 return MCDisassembler_Fail;
1599 Opc = ARM_AM_lsl;
1600 switch( fieldFromInstruction_4(Insn, 5, 2)) {
1601 case 0:
1602 Opc = ARM_AM_lsl;
1603 break;
1604 case 1:
1605 Opc = ARM_AM_lsr;
1606 break;
1607 case 2:
1608 Opc = ARM_AM_asr;
1609 break;
1610 case 3:
1611 Opc = ARM_AM_ror;
1612 break;
1613 default:
1614 return MCDisassembler_Fail;
1615 }
1616 amt = fieldFromInstruction_4(Insn, 7, 5);
1617 if (Opc == ARM_AM_ror && amt == 0)
1618 Opc = ARM_AM_rrx;
1619 imm = ARM_AM_getAM2Opc(Op, amt, Opc, idx_mode);
1620
1621 MCOperand_CreateImm0(Inst, imm);
1622 } else {
1623 MCOperand_CreateReg0(Inst, 0);
1624 tmp = ARM_AM_getAM2Opc(Op, imm, ARM_AM_lsl, idx_mode);
1625 MCOperand_CreateImm0(Inst, tmp);
1626 }
1627
1628 if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1629 return MCDisassembler_Fail;
1630
1631 return S;
1632 }
1633
DecodeSORegMemOperand(MCInst * Inst,unsigned Val,uint64_t Address,const void * Decoder)1634 static DecodeStatus DecodeSORegMemOperand(MCInst *Inst, unsigned Val,
1635 uint64_t Address, const void *Decoder)
1636 {
1637 DecodeStatus S = MCDisassembler_Success;
1638 ARM_AM_ShiftOpc ShOp;
1639 unsigned shift;
1640 unsigned Rn = fieldFromInstruction_4(Val, 13, 4);
1641 unsigned Rm = fieldFromInstruction_4(Val, 0, 4);
1642 unsigned type = fieldFromInstruction_4(Val, 5, 2);
1643 unsigned imm = fieldFromInstruction_4(Val, 7, 5);
1644 unsigned U = fieldFromInstruction_4(Val, 12, 1);
1645
1646 ShOp = ARM_AM_lsl;
1647 switch (type) {
1648 case 0:
1649 ShOp = ARM_AM_lsl;
1650 break;
1651 case 1:
1652 ShOp = ARM_AM_lsr;
1653 break;
1654 case 2:
1655 ShOp = ARM_AM_asr;
1656 break;
1657 case 3:
1658 ShOp = ARM_AM_ror;
1659 break;
1660 }
1661
1662 if (ShOp == ARM_AM_ror && imm == 0)
1663 ShOp = ARM_AM_rrx;
1664
1665 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1666 return MCDisassembler_Fail;
1667 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1668 return MCDisassembler_Fail;
1669 if (U)
1670 shift = ARM_AM_getAM2Opc(ARM_AM_add, imm, ShOp, 0);
1671 else
1672 shift = ARM_AM_getAM2Opc(ARM_AM_sub, imm, ShOp, 0);
1673 MCOperand_CreateImm0(Inst, shift);
1674
1675 return S;
1676 }
1677
DecodeAddrMode3Instruction(MCInst * Inst,unsigned Insn,uint64_t Address,const void * Decoder)1678 static DecodeStatus DecodeAddrMode3Instruction(MCInst *Inst, unsigned Insn,
1679 uint64_t Address, const void *Decoder)
1680 {
1681 DecodeStatus S = MCDisassembler_Success;
1682
1683 unsigned Rt = fieldFromInstruction_4(Insn, 12, 4);
1684 unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
1685 unsigned Rm = fieldFromInstruction_4(Insn, 0, 4);
1686 unsigned type = fieldFromInstruction_4(Insn, 22, 1);
1687 unsigned imm = fieldFromInstruction_4(Insn, 8, 4);
1688 unsigned U = ((~fieldFromInstruction_4(Insn, 23, 1)) & 1) << 8;
1689 unsigned pred = fieldFromInstruction_4(Insn, 28, 4);
1690 unsigned W = fieldFromInstruction_4(Insn, 21, 1);
1691 unsigned P = fieldFromInstruction_4(Insn, 24, 1);
1692 unsigned Rt2 = Rt + 1;
1693
1694 bool writeback = (W == 1) | (P == 0);
1695
1696 // For {LD,ST}RD, Rt must be even, else undefined.
1697 switch (MCInst_getOpcode(Inst)) {
1698 case ARM_STRD:
1699 case ARM_STRD_PRE:
1700 case ARM_STRD_POST:
1701 case ARM_LDRD:
1702 case ARM_LDRD_PRE:
1703 case ARM_LDRD_POST:
1704 if (Rt & 0x1) S = MCDisassembler_SoftFail;
1705 break;
1706 default:
1707 break;
1708 }
1709 switch (MCInst_getOpcode(Inst)) {
1710 case ARM_STRD:
1711 case ARM_STRD_PRE:
1712 case ARM_STRD_POST:
1713 if (P == 0 && W == 1)
1714 S = MCDisassembler_SoftFail;
1715
1716 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2))
1717 S = MCDisassembler_SoftFail;
1718 if (type && Rm == 15)
1719 S = MCDisassembler_SoftFail;
1720 if (Rt2 == 15)
1721 S = MCDisassembler_SoftFail;
1722 if (!type && fieldFromInstruction_4(Insn, 8, 4))
1723 S = MCDisassembler_SoftFail;
1724 break;
1725 case ARM_STRH:
1726 case ARM_STRH_PRE:
1727 case ARM_STRH_POST:
1728 if (Rt == 15)
1729 S = MCDisassembler_SoftFail;
1730 if (writeback && (Rn == 15 || Rn == Rt))
1731 S = MCDisassembler_SoftFail;
1732 if (!type && Rm == 15)
1733 S = MCDisassembler_SoftFail;
1734 break;
1735 case ARM_LDRD:
1736 case ARM_LDRD_PRE:
1737 case ARM_LDRD_POST:
1738 if (type && Rn == 15){
1739 if (Rt2 == 15)
1740 S = MCDisassembler_SoftFail;
1741 break;
1742 }
1743 if (P == 0 && W == 1)
1744 S = MCDisassembler_SoftFail;
1745 if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2))
1746 S = MCDisassembler_SoftFail;
1747 if (!type && writeback && Rn == 15)
1748 S = MCDisassembler_SoftFail;
1749 if (writeback && (Rn == Rt || Rn == Rt2))
1750 S = MCDisassembler_SoftFail;
1751 break;
1752 case ARM_LDRH:
1753 case ARM_LDRH_PRE:
1754 case ARM_LDRH_POST:
1755 if (type && Rn == 15){
1756 if (Rt == 15)
1757 S = MCDisassembler_SoftFail;
1758 break;
1759 }
1760 if (Rt == 15)
1761 S = MCDisassembler_SoftFail;
1762 if (!type && Rm == 15)
1763 S = MCDisassembler_SoftFail;
1764 if (!type && writeback && (Rn == 15 || Rn == Rt))
1765 S = MCDisassembler_SoftFail;
1766 break;
1767 case ARM_LDRSH:
1768 case ARM_LDRSH_PRE:
1769 case ARM_LDRSH_POST:
1770 case ARM_LDRSB:
1771 case ARM_LDRSB_PRE:
1772 case ARM_LDRSB_POST:
1773 if (type && Rn == 15){
1774 if (Rt == 15)
1775 S = MCDisassembler_SoftFail;
1776 break;
1777 }
1778 if (type && (Rt == 15 || (writeback && Rn == Rt)))
1779 S = MCDisassembler_SoftFail;
1780 if (!type && (Rt == 15 || Rm == 15))
1781 S = MCDisassembler_SoftFail;
1782 if (!type && writeback && (Rn == 15 || Rn == Rt))
1783 S = MCDisassembler_SoftFail;
1784 break;
1785 default:
1786 break;
1787 }
1788
1789 if (writeback) { // Writeback
1790 Inst->writeback = true;
1791 if (P)
1792 U |= ARMII_IndexModePre << 9;
1793 else
1794 U |= ARMII_IndexModePost << 9;
1795
1796 // On stores, the writeback operand precedes Rt.
1797 switch (MCInst_getOpcode(Inst)) {
1798 case ARM_STRD:
1799 case ARM_STRD_PRE:
1800 case ARM_STRD_POST:
1801 case ARM_STRH:
1802 case ARM_STRH_PRE:
1803 case ARM_STRH_POST:
1804 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1805 return MCDisassembler_Fail;
1806 break;
1807 default:
1808 break;
1809 }
1810 }
1811
1812 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
1813 return MCDisassembler_Fail;
1814 switch (MCInst_getOpcode(Inst)) {
1815 case ARM_STRD:
1816 case ARM_STRD_PRE:
1817 case ARM_STRD_POST:
1818 case ARM_LDRD:
1819 case ARM_LDRD_PRE:
1820 case ARM_LDRD_POST:
1821 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
1822 return MCDisassembler_Fail;
1823 break;
1824 default:
1825 break;
1826 }
1827
1828 if (writeback) {
1829 // On loads, the writeback operand comes after Rt.
1830 switch (MCInst_getOpcode(Inst)) {
1831 case ARM_LDRD:
1832 case ARM_LDRD_PRE:
1833 case ARM_LDRD_POST:
1834 case ARM_LDRH:
1835 case ARM_LDRH_PRE:
1836 case ARM_LDRH_POST:
1837 case ARM_LDRSH:
1838 case ARM_LDRSH_PRE:
1839 case ARM_LDRSH_POST:
1840 case ARM_LDRSB:
1841 case ARM_LDRSB_PRE:
1842 case ARM_LDRSB_POST:
1843 case ARM_LDRHTr:
1844 case ARM_LDRSBTr:
1845 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1846 return MCDisassembler_Fail;
1847 break;
1848 default:
1849 break;
1850 }
1851 }
1852
1853 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1854 return MCDisassembler_Fail;
1855
1856 if (type) {
1857 MCOperand_CreateReg0(Inst, 0);
1858 MCOperand_CreateImm0(Inst, U | (imm << 4) | Rm);
1859 } else {
1860 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1861 return MCDisassembler_Fail;
1862 MCOperand_CreateImm0(Inst, U);
1863 }
1864
1865 if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1866 return MCDisassembler_Fail;
1867
1868 return S;
1869 }
1870
DecodeRFEInstruction(MCInst * Inst,unsigned Insn,uint64_t Address,const void * Decoder)1871 static DecodeStatus DecodeRFEInstruction(MCInst *Inst, unsigned Insn,
1872 uint64_t Address, const void *Decoder)
1873 {
1874 DecodeStatus S = MCDisassembler_Success;
1875
1876 unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
1877 unsigned mode = fieldFromInstruction_4(Insn, 23, 2);
1878
1879 switch (mode) {
1880 case 0:
1881 mode = ARM_AM_da;
1882 break;
1883 case 1:
1884 mode = ARM_AM_ia;
1885 break;
1886 case 2:
1887 mode = ARM_AM_db;
1888 break;
1889 case 3:
1890 mode = ARM_AM_ib;
1891 break;
1892 }
1893
1894 MCOperand_CreateImm0(Inst, mode);
1895 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1896 return MCDisassembler_Fail;
1897
1898 return S;
1899 }
1900
DecodeQADDInstruction(MCInst * Inst,unsigned Insn,uint64_t Address,const void * Decoder)1901 static DecodeStatus DecodeQADDInstruction(MCInst *Inst, unsigned Insn,
1902 uint64_t Address, const void *Decoder)
1903 {
1904 DecodeStatus S = MCDisassembler_Success;
1905
1906 unsigned Rd = fieldFromInstruction_4(Insn, 12, 4);
1907 unsigned Rm = fieldFromInstruction_4(Insn, 0, 4);
1908 unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
1909 unsigned pred = fieldFromInstruction_4(Insn, 28, 4);
1910
1911 if (pred == 0xF)
1912 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
1913
1914 if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
1915 return MCDisassembler_Fail;
1916 if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1917 return MCDisassembler_Fail;
1918 if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
1919 return MCDisassembler_Fail;
1920 if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1921 return MCDisassembler_Fail;
1922 return S;
1923 }
1924
DecodeMemMultipleWritebackInstruction(MCInst * Inst,unsigned Insn,uint64_t Address,const void * Decoder)1925 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst *Inst,
1926 unsigned Insn, uint64_t Address, const void *Decoder)
1927 {
1928 DecodeStatus S = MCDisassembler_Success;
1929
1930 unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
1931 unsigned pred = fieldFromInstruction_4(Insn, 28, 4);
1932 unsigned reglist = fieldFromInstruction_4(Insn, 0, 16);
1933
1934 if (pred == 0xF) {
1935 // Ambiguous with RFE and SRS
1936 switch (MCInst_getOpcode(Inst)) {
1937 case ARM_LDMDA:
1938 MCInst_setOpcode(Inst, ARM_RFEDA);
1939 break;
1940 case ARM_LDMDA_UPD:
1941 MCInst_setOpcode(Inst, ARM_RFEDA_UPD);
1942 break;
1943 case ARM_LDMDB:
1944 MCInst_setOpcode(Inst, ARM_RFEDB);
1945 break;
1946 case ARM_LDMDB_UPD:
1947 MCInst_setOpcode(Inst, ARM_RFEDB_UPD);
1948 break;
1949 case ARM_LDMIA:
1950 MCInst_setOpcode(Inst, ARM_RFEIA);
1951 break;
1952 case ARM_LDMIA_UPD:
1953 MCInst_setOpcode(Inst, ARM_RFEIA_UPD);
1954 break;
1955 case ARM_LDMIB:
1956 MCInst_setOpcode(Inst, ARM_RFEIB);
1957 break;
1958 case ARM_LDMIB_UPD:
1959 MCInst_setOpcode(Inst, ARM_RFEIB_UPD);
1960 break;
1961 case ARM_STMDA:
1962 MCInst_setOpcode(Inst, ARM_SRSDA);
1963 break;
1964 case ARM_STMDA_UPD:
1965 MCInst_setOpcode(Inst, ARM_SRSDA_UPD);
1966 break;
1967 case ARM_STMDB:
1968 MCInst_setOpcode(Inst, ARM_SRSDB);
1969 break;
1970 case ARM_STMDB_UPD:
1971 MCInst_setOpcode(Inst, ARM_SRSDB_UPD);
1972 break;
1973 case ARM_STMIA:
1974 MCInst_setOpcode(Inst, ARM_SRSIA);
1975 break;
1976 case ARM_STMIA_UPD:
1977 MCInst_setOpcode(Inst, ARM_SRSIA_UPD);
1978 break;
1979 case ARM_STMIB:
1980 MCInst_setOpcode(Inst, ARM_SRSIB);
1981 break;
1982 case ARM_STMIB_UPD:
1983 MCInst_setOpcode(Inst, ARM_SRSIB_UPD);
1984 break;
1985 default:
1986 return MCDisassembler_Fail;
1987 }
1988
1989 // For stores (which become SRS's, the only operand is the mode.
1990 if (fieldFromInstruction_4(Insn, 20, 1) == 0) {
1991 // Check SRS encoding constraints
1992 if (!(fieldFromInstruction_4(Insn, 22, 1) == 1 &&
1993 fieldFromInstruction_4(Insn, 20, 1) == 0))
1994 return MCDisassembler_Fail;
1995
1996 MCOperand_CreateImm0(Inst, fieldFromInstruction_4(Insn, 0, 4));
1997 return S;
1998 }
1999
2000 return DecodeRFEInstruction(Inst, Insn, Address, Decoder);
2001 }
2002
2003 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2004 return MCDisassembler_Fail;
2005 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2006 return MCDisassembler_Fail; // Tied
2007 if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2008 return MCDisassembler_Fail;
2009 if (!Check(&S, DecodeRegListOperand(Inst, reglist, Address, Decoder)))
2010 return MCDisassembler_Fail;
2011
2012 return S;
2013 }
2014
DecodeCPSInstruction(MCInst * Inst,unsigned Insn,uint64_t Address,const void * Decoder)2015 static DecodeStatus DecodeCPSInstruction(MCInst *Inst, unsigned Insn,
2016 uint64_t Address, const void *Decoder)
2017 {
2018 unsigned imod = fieldFromInstruction_4(Insn, 18, 2);
2019 unsigned M = fieldFromInstruction_4(Insn, 17, 1);
2020 unsigned iflags = fieldFromInstruction_4(Insn, 6, 3);
2021 unsigned mode = fieldFromInstruction_4(Insn, 0, 5);
2022
2023 DecodeStatus S = MCDisassembler_Success;
2024
2025 // This decoder is called from multiple location that do not check
2026 // the full encoding is valid before they do.
2027 if (fieldFromInstruction_4(Insn, 5, 1) != 0 ||
2028 fieldFromInstruction_4(Insn, 16, 1) != 0 ||
2029 fieldFromInstruction_4(Insn, 20, 8) != 0x10)
2030 return MCDisassembler_Fail;
2031
2032 // imod == '01' --> UNPREDICTABLE
2033 // NOTE: Even though this is technically UNPREDICTABLE, we choose to
2034 // return failure here. The '01' imod value is unprintable, so there's
2035 // nothing useful we could do even if we returned UNPREDICTABLE.
2036
2037 if (imod == 1) return MCDisassembler_Fail;
2038
2039 if (imod && M) {
2040 MCInst_setOpcode(Inst, ARM_CPS3p);
2041 MCOperand_CreateImm0(Inst, imod);
2042 MCOperand_CreateImm0(Inst, iflags);
2043 MCOperand_CreateImm0(Inst, mode);
2044 } else if (imod && !M) {
2045 MCInst_setOpcode(Inst, ARM_CPS2p);
2046 MCOperand_CreateImm0(Inst, imod);
2047 MCOperand_CreateImm0(Inst, iflags);
2048 if (mode) S = MCDisassembler_SoftFail;
2049 } else if (!imod && M) {
2050 MCInst_setOpcode(Inst, ARM_CPS1p);
2051 MCOperand_CreateImm0(Inst, mode);
2052 if (iflags) S = MCDisassembler_SoftFail;
2053 } else {
2054 // imod == '00' && M == '0' --> UNPREDICTABLE
2055 MCInst_setOpcode(Inst, ARM_CPS1p);
2056 MCOperand_CreateImm0(Inst, mode);
2057 S = MCDisassembler_SoftFail;
2058 }
2059
2060 return S;
2061 }
2062
DecodeT2CPSInstruction(MCInst * Inst,unsigned Insn,uint64_t Address,const void * Decoder)2063 static DecodeStatus DecodeT2CPSInstruction(MCInst *Inst, unsigned Insn,
2064 uint64_t Address, const void *Decoder)
2065 {
2066 unsigned imod = fieldFromInstruction_4(Insn, 9, 2);
2067 unsigned M = fieldFromInstruction_4(Insn, 8, 1);
2068 unsigned iflags = fieldFromInstruction_4(Insn, 5, 3);
2069 unsigned mode = fieldFromInstruction_4(Insn, 0, 5);
2070
2071 DecodeStatus S = MCDisassembler_Success;
2072
2073 // imod == '01' --> UNPREDICTABLE
2074 // NOTE: Even though this is technically UNPREDICTABLE, we choose to
2075 // return failure here. The '01' imod value is unprintable, so there's
2076 // nothing useful we could do even if we returned UNPREDICTABLE.
2077
2078 if (imod == 1) return MCDisassembler_Fail;
2079
2080 if (imod && M) {
2081 MCInst_setOpcode(Inst, ARM_t2CPS3p);
2082 MCOperand_CreateImm0(Inst, imod);
2083 MCOperand_CreateImm0(Inst, iflags);
2084 MCOperand_CreateImm0(Inst, mode);
2085 } else if (imod && !M) {
2086 MCInst_setOpcode(Inst, ARM_t2CPS2p);
2087 MCOperand_CreateImm0(Inst, imod);
2088 MCOperand_CreateImm0(Inst, iflags);
2089 if (mode) S = MCDisassembler_SoftFail;
2090 } else if (!imod && M) {
2091 MCInst_setOpcode(Inst, ARM_t2CPS1p);
2092 MCOperand_CreateImm0(Inst, mode);
2093 if (iflags) S = MCDisassembler_SoftFail;
2094 } else {
2095 // imod == '00' && M == '0' --> this is a HINT instruction
2096 int imm = fieldFromInstruction_4(Insn, 0, 8);
2097 // HINT are defined only for immediate in [0..4]
2098 if(imm > 4) return MCDisassembler_Fail;
2099 MCInst_setOpcode(Inst, ARM_t2HINT);
2100 MCOperand_CreateImm0(Inst, imm);
2101 }
2102
2103 return S;
2104 }
2105
DecodeT2MOVTWInstruction(MCInst * Inst,unsigned Insn,uint64_t Address,const void * Decoder)2106 static DecodeStatus DecodeT2MOVTWInstruction(MCInst *Inst, unsigned Insn,
2107 uint64_t Address, const void *Decoder)
2108 {
2109 DecodeStatus S = MCDisassembler_Success;
2110
2111 unsigned Rd = fieldFromInstruction_4(Insn, 8, 4);
2112 unsigned imm = 0;
2113
2114 imm |= (fieldFromInstruction_4(Insn, 0, 8) << 0);
2115 imm |= (fieldFromInstruction_4(Insn, 12, 3) << 8);
2116 imm |= (fieldFromInstruction_4(Insn, 16, 4) << 12);
2117 imm |= (fieldFromInstruction_4(Insn, 26, 1) << 11);
2118
2119 if (MCInst_getOpcode(Inst) == ARM_t2MOVTi16)
2120 if (!Check(&S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
2121 return MCDisassembler_Fail;
2122 if (!Check(&S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
2123 return MCDisassembler_Fail;
2124
2125 MCOperand_CreateImm0(Inst, imm);
2126
2127 return S;
2128 }
2129
DecodeArmMOVTWInstruction(MCInst * Inst,unsigned Insn,uint64_t Address,const void * Decoder)2130 static DecodeStatus DecodeArmMOVTWInstruction(MCInst *Inst, unsigned Insn,
2131 uint64_t Address, const void *Decoder)
2132 {
2133 DecodeStatus S = MCDisassembler_Success;
2134
2135 unsigned Rd = fieldFromInstruction_4(Insn, 12, 4);
2136 unsigned pred = fieldFromInstruction_4(Insn, 28, 4);
2137 unsigned imm = 0;
2138
2139 imm |= (fieldFromInstruction_4(Insn, 0, 12) << 0);
2140 imm |= (fieldFromInstruction_4(Insn, 16, 4) << 12);
2141
2142 if (MCInst_getOpcode(Inst) == ARM_MOVTi16)
2143 if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
2144 return MCDisassembler_Fail;
2145
2146 if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
2147 return MCDisassembler_Fail;
2148
2149 MCOperand_CreateImm0(Inst, imm);
2150
2151 if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2152 return MCDisassembler_Fail;
2153
2154 return S;
2155 }
2156
DecodeSMLAInstruction(MCInst * Inst,unsigned Insn,uint64_t Address,const void * Decoder)2157 static DecodeStatus DecodeSMLAInstruction(MCInst *Inst, unsigned Insn,
2158 uint64_t Address, const void *Decoder)
2159 {
2160 DecodeStatus S = MCDisassembler_Success;
2161
2162 unsigned Rd = fieldFromInstruction_4(Insn, 16, 4);
2163 unsigned Rn = fieldFromInstruction_4(Insn, 0, 4);
2164 unsigned Rm = fieldFromInstruction_4(Insn, 8, 4);
2165 unsigned Ra = fieldFromInstruction_4(Insn, 12, 4);
2166 unsigned pred = fieldFromInstruction_4(Insn, 28, 4);
2167
2168 if (pred == 0xF)
2169 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
2170
2171 if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
2172 return MCDisassembler_Fail;
2173 if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
2174 return MCDisassembler_Fail;
2175 if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
2176 return MCDisassembler_Fail;
2177 if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder)))
2178 return MCDisassembler_Fail;
2179
2180 if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2181 return MCDisassembler_Fail;
2182
2183 return S;
2184 }
2185
DecodeAddrModeImm12Operand(MCInst * Inst,unsigned Val,uint64_t Address,const void * Decoder)2186 static DecodeStatus DecodeAddrModeImm12Operand(MCInst *Inst, unsigned Val,
2187 uint64_t Address, const void *Decoder)
2188 {
2189 DecodeStatus S = MCDisassembler_Success;
2190
2191 unsigned add = fieldFromInstruction_4(Val, 12, 1);
2192 unsigned imm = fieldFromInstruction_4(Val, 0, 12);
2193 unsigned Rn = fieldFromInstruction_4(Val, 13, 4);
2194
2195 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2196 return MCDisassembler_Fail;
2197
2198 if (!add) imm *= (unsigned int)-1;
2199 if (imm == 0 && !add) imm = (unsigned int)INT32_MIN;
2200 MCOperand_CreateImm0(Inst, imm);
2201 //if (Rn == 15)
2202 // tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder);
2203
2204 return S;
2205 }
2206
DecodeAddrMode5Operand(MCInst * Inst,unsigned Val,uint64_t Address,const void * Decoder)2207 static DecodeStatus DecodeAddrMode5Operand(MCInst *Inst, unsigned Val,
2208 uint64_t Address, const void *Decoder)
2209 {
2210 DecodeStatus S = MCDisassembler_Success;
2211
2212 unsigned Rn = fieldFromInstruction_4(Val, 9, 4);
2213 unsigned U = fieldFromInstruction_4(Val, 8, 1);
2214 unsigned imm = fieldFromInstruction_4(Val, 0, 8);
2215
2216 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2217 return MCDisassembler_Fail;
2218
2219 if (U)
2220 MCOperand_CreateImm0(Inst, ARM_AM_getAM5Opc(ARM_AM_add, (unsigned char)imm));
2221 else
2222 MCOperand_CreateImm0(Inst, ARM_AM_getAM5Opc(ARM_AM_sub, (unsigned char)imm));
2223
2224 return S;
2225 }
2226
DecodeAddrMode7Operand(MCInst * Inst,unsigned Val,uint64_t Address,const void * Decoder)2227 static DecodeStatus DecodeAddrMode7Operand(MCInst *Inst, unsigned Val,
2228 uint64_t Address, const void *Decoder)
2229 {
2230 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder);
2231 }
2232
DecodeT2BInstruction(MCInst * Inst,unsigned Insn,uint64_t Address,const void * Decoder)2233 static DecodeStatus DecodeT2BInstruction(MCInst *Inst, unsigned Insn,
2234 uint64_t Address, const void *Decoder)
2235 {
2236 DecodeStatus Status = MCDisassembler_Success;
2237
2238 // Note the J1 and J2 values are from the encoded instruction. So here
2239 // change them to I1 and I2 values via as documented:
2240 // I1 = NOT(J1 EOR S);
2241 // I2 = NOT(J2 EOR S);
2242 // and build the imm32 with one trailing zero as documented:
2243 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32);
2244 unsigned S = fieldFromInstruction_4(Insn, 26, 1);
2245 unsigned J1 = fieldFromInstruction_4(Insn, 13, 1);
2246 unsigned J2 = fieldFromInstruction_4(Insn, 11, 1);
2247 unsigned I1 = !(J1 ^ S);
2248 unsigned I2 = !(J2 ^ S);
2249 unsigned imm10 = fieldFromInstruction_4(Insn, 16, 10);
2250 unsigned imm11 = fieldFromInstruction_4(Insn, 0, 11);
2251 unsigned tmp = (S << 23) | (I1 << 22) | (I2 << 21) | (imm10 << 11) | imm11;
2252 int imm32 = SignExtend32(tmp << 1, 25);
2253 MCOperand_CreateImm0(Inst, imm32);
2254
2255 return Status;
2256 }
2257
DecodeBranchImmInstruction(MCInst * Inst,unsigned Insn,uint64_t Address,const void * Decoder)2258 static DecodeStatus DecodeBranchImmInstruction(MCInst *Inst, unsigned Insn,
2259 uint64_t Address, const void *Decoder)
2260 {
2261 DecodeStatus S = MCDisassembler_Success;
2262
2263 unsigned pred = fieldFromInstruction_4(Insn, 28, 4);
2264 unsigned imm = fieldFromInstruction_4(Insn, 0, 24) << 2;
2265
2266 if (pred == 0xF) {
2267 MCInst_setOpcode(Inst, ARM_BLXi);
2268 imm |= fieldFromInstruction_4(Insn, 24, 1) << 1;
2269 MCOperand_CreateImm0(Inst, SignExtend32(imm, 26));
2270 return S;
2271 }
2272
2273 MCOperand_CreateImm0(Inst, SignExtend32(imm, 26));
2274 if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2275 return MCDisassembler_Fail;
2276
2277 return S;
2278 }
2279
2280
DecodeAddrMode6Operand(MCInst * Inst,unsigned Val,uint64_t Address,const void * Decoder)2281 static DecodeStatus DecodeAddrMode6Operand(MCInst *Inst, unsigned Val,
2282 uint64_t Address, const void *Decoder)
2283 {
2284 DecodeStatus S = MCDisassembler_Success;
2285
2286 unsigned Rm = fieldFromInstruction_4(Val, 0, 4);
2287 unsigned align = fieldFromInstruction_4(Val, 4, 2);
2288
2289 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2290 return MCDisassembler_Fail;
2291 if (!align)
2292 MCOperand_CreateImm0(Inst, 0);
2293 else
2294 MCOperand_CreateImm0(Inst, 4 << align);
2295
2296 return S;
2297 }
2298
DecodeVLDInstruction(MCInst * Inst,unsigned Insn,uint64_t Address,const void * Decoder)2299 static DecodeStatus DecodeVLDInstruction(MCInst *Inst, unsigned Insn,
2300 uint64_t Address, const void *Decoder)
2301 {
2302 DecodeStatus S = MCDisassembler_Success;
2303 unsigned wb, Rn, Rm;
2304 unsigned Rd = fieldFromInstruction_4(Insn, 12, 4);
2305 Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4;
2306 wb = fieldFromInstruction_4(Insn, 16, 4);
2307 Rn = fieldFromInstruction_4(Insn, 16, 4);
2308 Rn |= fieldFromInstruction_4(Insn, 4, 2) << 4;
2309 Rm = fieldFromInstruction_4(Insn, 0, 4);
2310
2311 // First output register
2312 switch (MCInst_getOpcode(Inst)) {
2313 case ARM_VLD1q16: case ARM_VLD1q32: case ARM_VLD1q64: case ARM_VLD1q8:
2314 case ARM_VLD1q16wb_fixed: case ARM_VLD1q16wb_register:
2315 case ARM_VLD1q32wb_fixed: case ARM_VLD1q32wb_register:
2316 case ARM_VLD1q64wb_fixed: case ARM_VLD1q64wb_register:
2317 case ARM_VLD1q8wb_fixed: case ARM_VLD1q8wb_register:
2318 case ARM_VLD2d16: case ARM_VLD2d32: case ARM_VLD2d8:
2319 case ARM_VLD2d16wb_fixed: case ARM_VLD2d16wb_register:
2320 case ARM_VLD2d32wb_fixed: case ARM_VLD2d32wb_register:
2321 case ARM_VLD2d8wb_fixed: case ARM_VLD2d8wb_register:
2322 if (!Check(&S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2323 return MCDisassembler_Fail;
2324 break;
2325 case ARM_VLD2b16:
2326 case ARM_VLD2b32:
2327 case ARM_VLD2b8:
2328 case ARM_VLD2b16wb_fixed:
2329 case ARM_VLD2b16wb_register:
2330 case ARM_VLD2b32wb_fixed:
2331 case ARM_VLD2b32wb_register:
2332 case ARM_VLD2b8wb_fixed:
2333 case ARM_VLD2b8wb_register:
2334 if (!Check(&S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
2335 return MCDisassembler_Fail;
2336 break;
2337 default:
2338 if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2339 return MCDisassembler_Fail;
2340 }
2341
2342 // Second output register
2343 switch (MCInst_getOpcode(Inst)) {
2344 case ARM_VLD3d8:
2345 case ARM_VLD3d16:
2346 case ARM_VLD3d32:
2347 case ARM_VLD3d8_UPD:
2348 case ARM_VLD3d16_UPD:
2349 case ARM_VLD3d32_UPD:
2350 case ARM_VLD4d8:
2351 case ARM_VLD4d16:
2352 case ARM_VLD4d32:
2353 case ARM_VLD4d8_UPD:
2354 case ARM_VLD4d16_UPD:
2355 case ARM_VLD4d32_UPD:
2356 if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
2357 return MCDisassembler_Fail;
2358 break;
2359 case ARM_VLD3q8:
2360 case ARM_VLD3q16:
2361 case ARM_VLD3q32:
2362 case ARM_VLD3q8_UPD:
2363 case ARM_VLD3q16_UPD:
2364 case ARM_VLD3q32_UPD:
2365 case ARM_VLD4q8:
2366 case ARM_VLD4q16:
2367 case ARM_VLD4q32:
2368 case ARM_VLD4q8_UPD:
2369 case ARM_VLD4q16_UPD:
2370 case ARM_VLD4q32_UPD:
2371 if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2372 return MCDisassembler_Fail;
2373 default:
2374 break;
2375 }
2376
2377 // Third output register
2378 switch(MCInst_getOpcode(Inst)) {
2379 case ARM_VLD3d8:
2380 case ARM_VLD3d16:
2381 case ARM_VLD3d32:
2382 case ARM_VLD3d8_UPD:
2383 case ARM_VLD3d16_UPD:
2384 case ARM_VLD3d32_UPD:
2385 case ARM_VLD4d8:
2386 case ARM_VLD4d16:
2387 case ARM_VLD4d32:
2388 case ARM_VLD4d8_UPD:
2389 case ARM_VLD4d16_UPD:
2390 case ARM_VLD4d32_UPD:
2391 if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2392 return MCDisassembler_Fail;
2393 break;
2394 case ARM_VLD3q8:
2395 case ARM_VLD3q16:
2396 case ARM_VLD3q32:
2397 case ARM_VLD3q8_UPD:
2398 case ARM_VLD3q16_UPD:
2399 case ARM_VLD3q32_UPD:
2400 case ARM_VLD4q8:
2401 case ARM_VLD4q16:
2402 case ARM_VLD4q32:
2403 case ARM_VLD4q8_UPD:
2404 case ARM_VLD4q16_UPD:
2405 case ARM_VLD4q32_UPD:
2406 if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
2407 return MCDisassembler_Fail;
2408 break;
2409 default:
2410 break;
2411 }
2412
2413 // Fourth output register
2414 switch (MCInst_getOpcode(Inst)) {
2415 case ARM_VLD4d8:
2416 case ARM_VLD4d16:
2417 case ARM_VLD4d32:
2418 case ARM_VLD4d8_UPD:
2419 case ARM_VLD4d16_UPD:
2420 case ARM_VLD4d32_UPD:
2421 if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
2422 return MCDisassembler_Fail;
2423 break;
2424 case ARM_VLD4q8:
2425 case ARM_VLD4q16:
2426 case ARM_VLD4q32:
2427 case ARM_VLD4q8_UPD:
2428 case ARM_VLD4q16_UPD:
2429 case ARM_VLD4q32_UPD:
2430 if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
2431 return MCDisassembler_Fail;
2432 break;
2433 default:
2434 break;
2435 }
2436
2437 // Writeback operand
2438 switch (MCInst_getOpcode(Inst)) {
2439 case ARM_VLD1d8wb_fixed:
2440 case ARM_VLD1d16wb_fixed:
2441 case ARM_VLD1d32wb_fixed:
2442 case ARM_VLD1d64wb_fixed:
2443 case ARM_VLD1d8wb_register:
2444 case ARM_VLD1d16wb_register:
2445 case ARM_VLD1d32wb_register:
2446 case ARM_VLD1d64wb_register:
2447 case ARM_VLD1q8wb_fixed:
2448 case ARM_VLD1q16wb_fixed:
2449 case ARM_VLD1q32wb_fixed:
2450 case ARM_VLD1q64wb_fixed:
2451 case ARM_VLD1q8wb_register:
2452 case ARM_VLD1q16wb_register:
2453 case ARM_VLD1q32wb_register:
2454 case ARM_VLD1q64wb_register:
2455 case ARM_VLD1d8Twb_fixed:
2456 case ARM_VLD1d8Twb_register:
2457 case ARM_VLD1d16Twb_fixed:
2458 case ARM_VLD1d16Twb_register:
2459 case ARM_VLD1d32Twb_fixed:
2460 case ARM_VLD1d32Twb_register:
2461 case ARM_VLD1d64Twb_fixed:
2462 case ARM_VLD1d64Twb_register:
2463 case ARM_VLD1d8Qwb_fixed:
2464 case ARM_VLD1d8Qwb_register:
2465 case ARM_VLD1d16Qwb_fixed:
2466 case ARM_VLD1d16Qwb_register:
2467 case ARM_VLD1d32Qwb_fixed:
2468 case ARM_VLD1d32Qwb_register:
2469 case ARM_VLD1d64Qwb_fixed:
2470 case ARM_VLD1d64Qwb_register:
2471 case ARM_VLD2d8wb_fixed:
2472 case ARM_VLD2d16wb_fixed:
2473 case ARM_VLD2d32wb_fixed:
2474 case ARM_VLD2q8wb_fixed:
2475 case ARM_VLD2q16wb_fixed:
2476 case ARM_VLD2q32wb_fixed:
2477 case ARM_VLD2d8wb_register:
2478 case ARM_VLD2d16wb_register:
2479 case ARM_VLD2d32wb_register:
2480 case ARM_VLD2q8wb_register:
2481 case ARM_VLD2q16wb_register:
2482 case ARM_VLD2q32wb_register:
2483 case ARM_VLD2b8wb_fixed:
2484 case ARM_VLD2b16wb_fixed:
2485 case ARM_VLD2b32wb_fixed:
2486 case ARM_VLD2b8wb_register:
2487 case ARM_VLD2b16wb_register:
2488 case ARM_VLD2b32wb_register:
2489 MCOperand_CreateImm0(Inst, 0);
2490 break;
2491 case ARM_VLD3d8_UPD:
2492 case ARM_VLD3d16_UPD:
2493 case ARM_VLD3d32_UPD:
2494 case ARM_VLD3q8_UPD:
2495 case ARM_VLD3q16_UPD:
2496 case ARM_VLD3q32_UPD:
2497 case ARM_VLD4d8_UPD:
2498 case ARM_VLD4d16_UPD:
2499 case ARM_VLD4d32_UPD:
2500 case ARM_VLD4q8_UPD:
2501 case ARM_VLD4q16_UPD:
2502 case ARM_VLD4q32_UPD:
2503 if (!Check(&S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
2504 return MCDisassembler_Fail;
2505 break;
2506 default:
2507 break;
2508 }
2509
2510 // AddrMode6 Base (register+alignment)
2511 if (!Check(&S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
2512 return MCDisassembler_Fail;
2513
2514 // AddrMode6 Offset (register)
2515 switch (MCInst_getOpcode(Inst)) {
2516 default:
2517 // The below have been updated to have explicit am6offset split
2518 // between fixed and register offset. For those instructions not
2519 // yet updated, we need to add an additional reg0 operand for the
2520 // fixed variant.
2521 //
2522 // The fixed offset encodes as Rm == 0xd, so we check for that.
2523 if (Rm == 0xd) {
2524 MCOperand_CreateReg0(Inst, 0);
2525 break;
2526 }
2527 // Fall through to handle the register offset variant.
2528 case ARM_VLD1d8wb_fixed:
2529 case ARM_VLD1d16wb_fixed:
2530 case ARM_VLD1d32wb_fixed:
2531 case ARM_VLD1d64wb_fixed:
2532 case ARM_VLD1d8Twb_fixed:
2533 case ARM_VLD1d16Twb_fixed:
2534 case ARM_VLD1d32Twb_fixed:
2535 case ARM_VLD1d64Twb_fixed:
2536 case ARM_VLD1d8Qwb_fixed:
2537 case ARM_VLD1d16Qwb_fixed:
2538 case ARM_VLD1d32Qwb_fixed:
2539 case ARM_VLD1d64Qwb_fixed:
2540 case ARM_VLD1d8wb_register:
2541 case ARM_VLD1d16wb_register:
2542 case ARM_VLD1d32wb_register:
2543 case ARM_VLD1d64wb_register:
2544 case ARM_VLD1q8wb_fixed:
2545 case ARM_VLD1q16wb_fixed:
2546 case ARM_VLD1q32wb_fixed:
2547 case ARM_VLD1q64wb_fixed:
2548 case ARM_VLD1q8wb_register:
2549 case ARM_VLD1q16wb_register:
2550 case ARM_VLD1q32wb_register:
2551 case ARM_VLD1q64wb_register:
2552 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback
2553 // variant encodes Rm == 0xf. Anything else is a register offset post-
2554 // increment and we need to add the register operand to the instruction.
2555 if (Rm != 0xD && Rm != 0xF &&
2556 !Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2557 return MCDisassembler_Fail;
2558 break;
2559 case ARM_VLD2d8wb_fixed:
2560 case ARM_VLD2d16wb_fixed:
2561 case ARM_VLD2d32wb_fixed:
2562 case ARM_VLD2b8wb_fixed:
2563 case ARM_VLD2b16wb_fixed:
2564 case ARM_VLD2b32wb_fixed:
2565 case ARM_VLD2q8wb_fixed:
2566 case ARM_VLD2q16wb_fixed:
2567 case ARM_VLD2q32wb_fixed:
2568 break;
2569 }
2570
2571 return S;
2572 }
2573
DecodeVLDST1Instruction(MCInst * Inst,unsigned Insn,uint64_t Address,const void * Decoder)2574 static DecodeStatus DecodeVLDST1Instruction(MCInst *Inst, unsigned Insn,
2575 uint64_t Address, const void *Decoder)
2576 {
2577 unsigned load;
2578 unsigned type = fieldFromInstruction_4(Insn, 8, 4);
2579 unsigned align = fieldFromInstruction_4(Insn, 4, 2);
2580 if (type == 6 && (align & 2)) return MCDisassembler_Fail;
2581 if (type == 7 && (align & 2)) return MCDisassembler_Fail;
2582 if (type == 10 && align == 3) return MCDisassembler_Fail;
2583
2584 load = fieldFromInstruction_4(Insn, 21, 1);
2585 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
2586 : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
2587 }
2588
DecodeVLDST2Instruction(MCInst * Inst,unsigned Insn,uint64_t Address,const void * Decoder)2589 static DecodeStatus DecodeVLDST2Instruction(MCInst *Inst, unsigned Insn,
2590 uint64_t Address, const void *Decoder)
2591 {
2592 unsigned type, align, load;
2593 unsigned size = fieldFromInstruction_4(Insn, 6, 2);
2594 if (size == 3) return MCDisassembler_Fail;
2595
2596 type = fieldFromInstruction_4(Insn, 8, 4);
2597 align = fieldFromInstruction_4(Insn, 4, 2);
2598 if (type == 8 && align == 3) return MCDisassembler_Fail;
2599 if (type == 9 && align == 3) return MCDisassembler_Fail;
2600
2601 load = fieldFromInstruction_4(Insn, 21, 1);
2602 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
2603 : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
2604 }
2605
DecodeVLDST3Instruction(MCInst * Inst,unsigned Insn,uint64_t Address,const void * Decoder)2606 static DecodeStatus DecodeVLDST3Instruction(MCInst *Inst, unsigned Insn,
2607 uint64_t Address, const void *Decoder)
2608 {
2609 unsigned align, load;
2610 unsigned size = fieldFromInstruction_4(Insn, 6, 2);
2611 if (size == 3) return MCDisassembler_Fail;
2612
2613 align = fieldFromInstruction_4(Insn, 4, 2);
2614 if (align & 2) return MCDisassembler_Fail;
2615
2616 load = fieldFromInstruction_4(Insn, 21, 1);
2617 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
2618 : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
2619 }
2620
DecodeVLDST4Instruction(MCInst * Inst,unsigned Insn,uint64_t Address,const void * Decoder)2621 static DecodeStatus DecodeVLDST4Instruction(MCInst *Inst, unsigned Insn,
2622 uint64_t Address, const void *Decoder)
2623 {
2624 unsigned load;
2625 unsigned size = fieldFromInstruction_4(Insn, 6, 2);
2626 if (size == 3) return MCDisassembler_Fail;
2627
2628 load = fieldFromInstruction_4(Insn, 21, 1);
2629 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
2630 : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
2631 }
2632
DecodeVSTInstruction(MCInst * Inst,unsigned Insn,uint64_t Address,const void * Decoder)2633 static DecodeStatus DecodeVSTInstruction(MCInst *Inst, unsigned Insn,
2634 uint64_t Address, const void *Decoder)
2635 {
2636 DecodeStatus S = MCDisassembler_Success;
2637 unsigned wb, Rn, Rm;
2638 unsigned Rd = fieldFromInstruction_4(Insn, 12, 4);
2639 Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4;
2640 wb = fieldFromInstruction_4(Insn, 16, 4);
2641 Rn = fieldFromInstruction_4(Insn, 16, 4);
2642 Rn |= fieldFromInstruction_4(Insn, 4, 2) << 4;
2643 Rm = fieldFromInstruction_4(Insn, 0, 4);
2644
2645 // Writeback Operand
2646 switch (MCInst_getOpcode(Inst)) {
2647 case ARM_VST1d8wb_fixed:
2648 case ARM_VST1d16wb_fixed:
2649 case ARM_VST1d32wb_fixed:
2650 case ARM_VST1d64wb_fixed:
2651 case ARM_VST1d8wb_register:
2652 case ARM_VST1d16wb_register:
2653 case ARM_VST1d32wb_register:
2654 case ARM_VST1d64wb_register:
2655 case ARM_VST1q8wb_fixed:
2656 case ARM_VST1q16wb_fixed:
2657 case ARM_VST1q32wb_fixed:
2658 case ARM_VST1q64wb_fixed:
2659 case ARM_VST1q8wb_register:
2660 case ARM_VST1q16wb_register:
2661 case ARM_VST1q32wb_register:
2662 case ARM_VST1q64wb_register:
2663 case ARM_VST1d8Twb_fixed:
2664 case ARM_VST1d16Twb_fixed:
2665 case ARM_VST1d32Twb_fixed:
2666 case ARM_VST1d64Twb_fixed:
2667 case ARM_VST1d8Twb_register:
2668 case ARM_VST1d16Twb_register:
2669 case ARM_VST1d32Twb_register:
2670 case ARM_VST1d64Twb_register:
2671 case ARM_VST1d8Qwb_fixed:
2672 case ARM_VST1d16Qwb_fixed:
2673 case ARM_VST1d32Qwb_fixed:
2674 case ARM_VST1d64Qwb_fixed:
2675 case ARM_VST1d8Qwb_register:
2676 case ARM_VST1d16Qwb_register:
2677 case ARM_VST1d32Qwb_register:
2678 case ARM_VST1d64Qwb_register:
2679 case ARM_VST2d8wb_fixed:
2680 case ARM_VST2d16wb_fixed:
2681 case ARM_VST2d32wb_fixed:
2682 case ARM_VST2d8wb_register:
2683 case ARM_VST2d16wb_register:
2684 case ARM_VST2d32wb_register:
2685 case ARM_VST2q8wb_fixed:
2686 case ARM_VST2q16wb_fixed:
2687 case ARM_VST2q32wb_fixed:
2688 case ARM_VST2q8wb_register:
2689 case ARM_VST2q16wb_register:
2690 case ARM_VST2q32wb_register:
2691 case ARM_VST2b8wb_fixed:
2692 case ARM_VST2b16wb_fixed:
2693 case ARM_VST2b32wb_fixed:
2694 case ARM_VST2b8wb_register:
2695 case ARM_VST2b16wb_register:
2696 case ARM_VST2b32wb_register:
2697 if (Rm == 0xF)
2698 return MCDisassembler_Fail;
2699 MCOperand_CreateImm0(Inst, 0);
2700 break;
2701 case ARM_VST3d8_UPD:
2702 case ARM_VST3d16_UPD:
2703 case ARM_VST3d32_UPD:
2704 case ARM_VST3q8_UPD:
2705 case ARM_VST3q16_UPD:
2706 case ARM_VST3q32_UPD:
2707 case ARM_VST4d8_UPD:
2708 case ARM_VST4d16_UPD:
2709 case ARM_VST4d32_UPD:
2710 case ARM_VST4q8_UPD:
2711 case ARM_VST4q16_UPD:
2712 case ARM_VST4q32_UPD:
2713 if (!Check(&S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
2714 return MCDisassembler_Fail;
2715 break;
2716 default:
2717 break;
2718 }
2719
2720 // AddrMode6 Base (register+alignment)
2721 if (!Check(&S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
2722 return MCDisassembler_Fail;
2723
2724 // AddrMode6 Offset (register)
2725 switch (MCInst_getOpcode(Inst)) {
2726 default:
2727 if (Rm == 0xD)
2728 MCOperand_CreateReg0(Inst, 0);
2729 else if (Rm != 0xF) {
2730 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2731 return MCDisassembler_Fail;
2732 }
2733 break;
2734 case ARM_VST1d8wb_fixed:
2735 case ARM_VST1d16wb_fixed:
2736 case ARM_VST1d32wb_fixed:
2737 case ARM_VST1d64wb_fixed:
2738 case ARM_VST1q8wb_fixed:
2739 case ARM_VST1q16wb_fixed:
2740 case ARM_VST1q32wb_fixed:
2741 case ARM_VST1q64wb_fixed:
2742 case ARM_VST1d8Twb_fixed:
2743 case ARM_VST1d16Twb_fixed:
2744 case ARM_VST1d32Twb_fixed:
2745 case ARM_VST1d64Twb_fixed:
2746 case ARM_VST1d8Qwb_fixed:
2747 case ARM_VST1d16Qwb_fixed:
2748 case ARM_VST1d32Qwb_fixed:
2749 case ARM_VST1d64Qwb_fixed:
2750 case ARM_VST2d8wb_fixed:
2751 case ARM_VST2d16wb_fixed:
2752 case ARM_VST2d32wb_fixed:
2753 case ARM_VST2q8wb_fixed:
2754 case ARM_VST2q16wb_fixed:
2755 case ARM_VST2q32wb_fixed:
2756 case ARM_VST2b8wb_fixed:
2757 case ARM_VST2b16wb_fixed:
2758 case ARM_VST2b32wb_fixed:
2759 break;
2760 }
2761
2762
2763 // First input register
2764 switch (MCInst_getOpcode(Inst)) {
2765 case ARM_VST1q16:
2766 case ARM_VST1q32:
2767 case ARM_VST1q64:
2768 case ARM_VST1q8:
2769 case ARM_VST1q16wb_fixed:
2770 case ARM_VST1q16wb_register:
2771 case ARM_VST1q32wb_fixed:
2772 case ARM_VST1q32wb_register:
2773 case ARM_VST1q64wb_fixed:
2774 case ARM_VST1q64wb_register:
2775 case ARM_VST1q8wb_fixed:
2776 case ARM_VST1q8wb_register:
2777 case ARM_VST2d16:
2778 case ARM_VST2d32:
2779 case ARM_VST2d8:
2780 case ARM_VST2d16wb_fixed:
2781 case ARM_VST2d16wb_register:
2782 case ARM_VST2d32wb_fixed:
2783 case ARM_VST2d32wb_register:
2784 case ARM_VST2d8wb_fixed:
2785 case ARM_VST2d8wb_register:
2786 if (!Check(&S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2787 return MCDisassembler_Fail;
2788 break;
2789 case ARM_VST2b16:
2790 case ARM_VST2b32:
2791 case ARM_VST2b8:
2792 case ARM_VST2b16wb_fixed:
2793 case ARM_VST2b16wb_register:
2794 case ARM_VST2b32wb_fixed:
2795 case ARM_VST2b32wb_register:
2796 case ARM_VST2b8wb_fixed:
2797 case ARM_VST2b8wb_register:
2798 if (!Check(&S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
2799 return MCDisassembler_Fail;
2800 break;
2801 default:
2802 if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2803 return MCDisassembler_Fail;
2804 }
2805
2806 // Second input register
2807 switch (MCInst_getOpcode(Inst)) {
2808 case ARM_VST3d8:
2809 case ARM_VST3d16:
2810 case ARM_VST3d32:
2811 case ARM_VST3d8_UPD:
2812 case ARM_VST3d16_UPD:
2813 case ARM_VST3d32_UPD:
2814 case ARM_VST4d8:
2815 case ARM_VST4d16:
2816 case ARM_VST4d32:
2817 case ARM_VST4d8_UPD:
2818 case ARM_VST4d16_UPD:
2819 case ARM_VST4d32_UPD:
2820 if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
2821 return MCDisassembler_Fail;
2822 break;
2823 case ARM_VST3q8:
2824 case ARM_VST3q16:
2825 case ARM_VST3q32:
2826 case ARM_VST3q8_UPD:
2827 case ARM_VST3q16_UPD:
2828 case ARM_VST3q32_UPD:
2829 case ARM_VST4q8:
2830 case ARM_VST4q16:
2831 case ARM_VST4q32:
2832 case ARM_VST4q8_UPD:
2833 case ARM_VST4q16_UPD:
2834 case ARM_VST4q32_UPD:
2835 if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2836 return MCDisassembler_Fail;
2837 break;
2838 default:
2839 break;
2840 }
2841
2842 // Third input register
2843 switch (MCInst_getOpcode(Inst)) {
2844 case ARM_VST3d8:
2845 case ARM_VST3d16:
2846 case ARM_VST3d32:
2847 case ARM_VST3d8_UPD:
2848 case ARM_VST3d16_UPD:
2849 case ARM_VST3d32_UPD:
2850 case ARM_VST4d8:
2851 case ARM_VST4d16:
2852 case ARM_VST4d32:
2853 case ARM_VST4d8_UPD:
2854 case ARM_VST4d16_UPD:
2855 case ARM_VST4d32_UPD:
2856 if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2857 return MCDisassembler_Fail;
2858 break;
2859 case ARM_VST3q8:
2860 case ARM_VST3q16:
2861 case ARM_VST3q32:
2862 case ARM_VST3q8_UPD:
2863 case ARM_VST3q16_UPD:
2864 case ARM_VST3q32_UPD:
2865 case ARM_VST4q8:
2866 case ARM_VST4q16:
2867 case ARM_VST4q32:
2868 case ARM_VST4q8_UPD:
2869 case ARM_VST4q16_UPD:
2870 case ARM_VST4q32_UPD:
2871 if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
2872 return MCDisassembler_Fail;
2873 break;
2874 default:
2875 break;
2876 }
2877
2878 // Fourth input register
2879 switch (MCInst_getOpcode(Inst)) {
2880 case ARM_VST4d8:
2881 case ARM_VST4d16:
2882 case ARM_VST4d32:
2883 case ARM_VST4d8_UPD:
2884 case ARM_VST4d16_UPD:
2885 case ARM_VST4d32_UPD:
2886 if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
2887 return MCDisassembler_Fail;
2888 break;
2889 case ARM_VST4q8:
2890 case ARM_VST4q16:
2891 case ARM_VST4q32:
2892 case ARM_VST4q8_UPD:
2893 case ARM_VST4q16_UPD:
2894 case ARM_VST4q32_UPD:
2895 if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
2896 return MCDisassembler_Fail;
2897 break;
2898 default:
2899 break;
2900 }
2901
2902 return S;
2903 }
2904
DecodeVLD1DupInstruction(MCInst * Inst,unsigned Insn,uint64_t Address,const void * Decoder)2905 static DecodeStatus DecodeVLD1DupInstruction(MCInst *Inst, unsigned Insn,
2906 uint64_t Address, const void *Decoder)
2907 {
2908 DecodeStatus S = MCDisassembler_Success;
2909 unsigned Rn, Rm, align, size;
2910 unsigned Rd = fieldFromInstruction_4(Insn, 12, 4);
2911 Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4;
2912 Rn = fieldFromInstruction_4(Insn, 16, 4);
2913 Rm = fieldFromInstruction_4(Insn, 0, 4);
2914 align = fieldFromInstruction_4(Insn, 4, 1);
2915 size = fieldFromInstruction_4(Insn, 6, 2);
2916
2917 if (size == 0 && align == 1)
2918 return MCDisassembler_Fail;
2919 align *= (1 << size);
2920
2921 switch (MCInst_getOpcode(Inst)) {
2922 case ARM_VLD1DUPq16: case ARM_VLD1DUPq32: case ARM_VLD1DUPq8:
2923 case ARM_VLD1DUPq16wb_fixed: case ARM_VLD1DUPq16wb_register:
2924 case ARM_VLD1DUPq32wb_fixed: case ARM_VLD1DUPq32wb_register:
2925 case ARM_VLD1DUPq8wb_fixed: case ARM_VLD1DUPq8wb_register:
2926 if (!Check(&S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2927 return MCDisassembler_Fail;
2928 break;
2929 default:
2930 if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2931 return MCDisassembler_Fail;
2932 break;
2933 }
2934 if (Rm != 0xF) {
2935 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2936 return MCDisassembler_Fail;
2937 }
2938
2939 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2940 return MCDisassembler_Fail;
2941 MCOperand_CreateImm0(Inst, align);
2942
2943 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback
2944 // variant encodes Rm == 0xf. Anything else is a register offset post-
2945 // increment and we need to add the register operand to the instruction.
2946 if (Rm != 0xD && Rm != 0xF &&
2947 !Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2948 return MCDisassembler_Fail;
2949
2950 return S;
2951 }
2952
DecodeVLD2DupInstruction(MCInst * Inst,unsigned Insn,uint64_t Address,const void * Decoder)2953 static DecodeStatus DecodeVLD2DupInstruction(MCInst *Inst, unsigned Insn,
2954 uint64_t Address, const void *Decoder)
2955 {
2956 DecodeStatus S = MCDisassembler_Success;
2957 unsigned Rn, Rm, align, size;
2958 unsigned Rd = fieldFromInstruction_4(Insn, 12, 4);
2959 Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4;
2960 Rn = fieldFromInstruction_4(Insn, 16, 4);
2961 Rm = fieldFromInstruction_4(Insn, 0, 4);
2962 align = fieldFromInstruction_4(Insn, 4, 1);
2963 size = 1 << fieldFromInstruction_4(Insn, 6, 2);
2964 align *= 2*size;
2965
2966 switch (MCInst_getOpcode(Inst)) {
2967 case ARM_VLD2DUPd16: case ARM_VLD2DUPd32: case ARM_VLD2DUPd8:
2968 case ARM_VLD2DUPd16wb_fixed: case ARM_VLD2DUPd16wb_register:
2969 case ARM_VLD2DUPd32wb_fixed: case ARM_VLD2DUPd32wb_register:
2970 case ARM_VLD2DUPd8wb_fixed: case ARM_VLD2DUPd8wb_register:
2971 if (!Check(&S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2972 return MCDisassembler_Fail;
2973 break;
2974 case ARM_VLD2DUPd16x2: case ARM_VLD2DUPd32x2: case ARM_VLD2DUPd8x2:
2975 case ARM_VLD2DUPd16x2wb_fixed: case ARM_VLD2DUPd16x2wb_register:
2976 case ARM_VLD2DUPd32x2wb_fixed: case ARM_VLD2DUPd32x2wb_register:
2977 case ARM_VLD2DUPd8x2wb_fixed: case ARM_VLD2DUPd8x2wb_register:
2978 if (!Check(&S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
2979 return MCDisassembler_Fail;
2980 break;
2981 default:
2982 if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2983 return MCDisassembler_Fail;
2984 break;
2985 }
2986
2987 if (Rm != 0xF)
2988 MCOperand_CreateImm0(Inst, 0);
2989
2990 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2991 return MCDisassembler_Fail;
2992 MCOperand_CreateImm0(Inst, align);
2993
2994 if (Rm != 0xD && Rm != 0xF) {
2995 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2996 return MCDisassembler_Fail;
2997 }
2998
2999 return S;
3000 }
3001
DecodeVLD3DupInstruction(MCInst * Inst,unsigned Insn,uint64_t Address,const void * Decoder)3002 static DecodeStatus DecodeVLD3DupInstruction(MCInst *Inst, unsigned Insn,
3003 uint64_t Address, const void *Decoder)
3004 {
3005 DecodeStatus S = MCDisassembler_Success;
3006 unsigned Rn, Rm, inc;
3007 unsigned Rd = fieldFromInstruction_4(Insn, 12, 4);
3008 Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4;
3009 Rn = fieldFromInstruction_4(Insn, 16, 4);
3010 Rm = fieldFromInstruction_4(Insn, 0, 4);
3011 inc = fieldFromInstruction_4(Insn, 5, 1) + 1;
3012
3013 if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3014 return MCDisassembler_Fail;
3015 if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
3016 return MCDisassembler_Fail;
3017 if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
3018 return MCDisassembler_Fail;
3019 if (Rm != 0xF) {
3020 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3021 return MCDisassembler_Fail;
3022 }
3023
3024 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3025 return MCDisassembler_Fail;
3026 MCOperand_CreateImm0(Inst, 0);
3027
3028 if (Rm == 0xD)
3029 MCOperand_CreateReg0(Inst, 0);
3030 else if (Rm != 0xF) {
3031 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3032 return MCDisassembler_Fail;
3033 }
3034
3035 return S;
3036 }
3037
DecodeVLD4DupInstruction(MCInst * Inst,unsigned Insn,uint64_t Address,const void * Decoder)3038 static DecodeStatus DecodeVLD4DupInstruction(MCInst *Inst, unsigned Insn,
3039 uint64_t Address, const void *Decoder)
3040 {
3041 DecodeStatus S = MCDisassembler_Success;
3042 unsigned Rn, Rm, size, inc, align;
3043 unsigned Rd = fieldFromInstruction_4(Insn, 12, 4);
3044 Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4;
3045 Rn = fieldFromInstruction_4(Insn, 16, 4);
3046 Rm = fieldFromInstruction_4(Insn, 0, 4);
3047 size = fieldFromInstruction_4(Insn, 6, 2);
3048 inc = fieldFromInstruction_4(Insn, 5, 1) + 1;
3049 align = fieldFromInstruction_4(Insn, 4, 1);
3050
3051 if (size == 0x3) {
3052 if (align == 0)
3053 return MCDisassembler_Fail;
3054 align = 16;
3055 } else {
3056 if (size == 2) {
3057 align *= 8;
3058 } else {
3059 size = 1 << size;
3060 align *= 4 * size;
3061 }
3062 }
3063
3064 if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3065 return MCDisassembler_Fail;
3066 if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
3067 return MCDisassembler_Fail;
3068 if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
3069 return MCDisassembler_Fail;
3070 if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder)))
3071 return MCDisassembler_Fail;
3072 if (Rm != 0xF) {
3073 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3074 return MCDisassembler_Fail;
3075 }
3076
3077 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3078 return MCDisassembler_Fail;
3079 MCOperand_CreateImm0(Inst, align);
3080
3081 if (Rm == 0xD)
3082 MCOperand_CreateReg0(Inst, 0);
3083 else if (Rm != 0xF) {
3084 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3085 return MCDisassembler_Fail;
3086 }
3087
3088 return S;
3089 }
3090
DecodeNEONModImmInstruction(MCInst * Inst,unsigned Insn,uint64_t Address,const void * Decoder)3091 static DecodeStatus DecodeNEONModImmInstruction(MCInst *Inst, unsigned Insn,
3092 uint64_t Address, const void *Decoder)
3093 {
3094 DecodeStatus S = MCDisassembler_Success;
3095 unsigned imm, Q;
3096 unsigned Rd = fieldFromInstruction_4(Insn, 12, 4);
3097 Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4;
3098 imm = fieldFromInstruction_4(Insn, 0, 4);
3099 imm |= fieldFromInstruction_4(Insn, 16, 3) << 4;
3100 imm |= fieldFromInstruction_4(Insn, 24, 1) << 7;
3101 imm |= fieldFromInstruction_4(Insn, 8, 4) << 8;
3102 imm |= fieldFromInstruction_4(Insn, 5, 1) << 12;
3103 Q = fieldFromInstruction_4(Insn, 6, 1);
3104
3105 if (Q) {
3106 if (!Check(&S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
3107 return MCDisassembler_Fail;
3108 } else {
3109 if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3110 return MCDisassembler_Fail;
3111 }
3112
3113 MCOperand_CreateImm0(Inst, imm);
3114
3115 switch (MCInst_getOpcode(Inst)) {
3116 case ARM_VORRiv4i16:
3117 case ARM_VORRiv2i32:
3118 case ARM_VBICiv4i16:
3119 case ARM_VBICiv2i32:
3120 if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3121 return MCDisassembler_Fail;
3122 break;
3123 case ARM_VORRiv8i16:
3124 case ARM_VORRiv4i32:
3125 case ARM_VBICiv8i16:
3126 case ARM_VBICiv4i32:
3127 if (!Check(&S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
3128 return MCDisassembler_Fail;
3129 break;
3130 default:
3131 break;
3132 }
3133
3134 return S;
3135 }
3136
DecodeVSHLMaxInstruction(MCInst * Inst,unsigned Insn,uint64_t Address,const void * Decoder)3137 static DecodeStatus DecodeVSHLMaxInstruction(MCInst *Inst, unsigned Insn,
3138 uint64_t Address, const void *Decoder)
3139 {
3140 DecodeStatus S = MCDisassembler_Success;
3141 unsigned Rm, size;
3142 unsigned Rd = fieldFromInstruction_4(Insn, 12, 4);
3143 Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4;
3144 Rm = fieldFromInstruction_4(Insn, 0, 4);
3145 Rm |= fieldFromInstruction_4(Insn, 5, 1) << 4;
3146 size = fieldFromInstruction_4(Insn, 18, 2);
3147
3148 if (!Check(&S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
3149 return MCDisassembler_Fail;
3150 if (!Check(&S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
3151 return MCDisassembler_Fail;
3152 MCOperand_CreateImm0(Inst, 8 << size);
3153
3154 return S;
3155 }
3156
DecodeShiftRight8Imm(MCInst * Inst,unsigned Val,uint64_t Address,const void * Decoder)3157 static DecodeStatus DecodeShiftRight8Imm(MCInst *Inst, unsigned Val,
3158 uint64_t Address, const void *Decoder)
3159 {
3160 MCOperand_CreateImm0(Inst, 8 - Val);
3161 return MCDisassembler_Success;
3162 }
3163
DecodeShiftRight16Imm(MCInst * Inst,unsigned Val,uint64_t Address,const void * Decoder)3164 static DecodeStatus DecodeShiftRight16Imm(MCInst *Inst, unsigned Val,
3165 uint64_t Address, const void *Decoder)
3166 {
3167 MCOperand_CreateImm0(Inst, 16 - Val);
3168 return MCDisassembler_Success;
3169 }
3170
DecodeShiftRight32Imm(MCInst * Inst,unsigned Val,uint64_t Address,const void * Decoder)3171 static DecodeStatus DecodeShiftRight32Imm(MCInst *Inst, unsigned Val,
3172 uint64_t Address, const void *Decoder)
3173 {
3174 MCOperand_CreateImm0(Inst, 32 - Val);
3175 return MCDisassembler_Success;
3176 }
3177
DecodeShiftRight64Imm(MCInst * Inst,unsigned Val,uint64_t Address,const void * Decoder)3178 static DecodeStatus DecodeShiftRight64Imm(MCInst *Inst, unsigned Val,
3179 uint64_t Address, const void *Decoder)
3180 {
3181 MCOperand_CreateImm0(Inst, 64 - Val);
3182 return MCDisassembler_Success;
3183 }
3184
DecodeTBLInstruction(MCInst * Inst,unsigned Insn,uint64_t Address,const void * Decoder)3185 static DecodeStatus DecodeTBLInstruction(MCInst *Inst, unsigned Insn,
3186 uint64_t Address, const void *Decoder)
3187 {
3188 DecodeStatus S = MCDisassembler_Success;
3189 unsigned Rn, Rm, op;
3190 unsigned Rd = fieldFromInstruction_4(Insn, 12, 4);
3191 Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4;
3192 Rn = fieldFromInstruction_4(Insn, 16, 4);
3193 Rn |= fieldFromInstruction_4(Insn, 7, 1) << 4;
3194 Rm = fieldFromInstruction_4(Insn, 0, 4);
3195 Rm |= fieldFromInstruction_4(Insn, 5, 1) << 4;
3196 op = fieldFromInstruction_4(Insn, 6, 1);
3197
3198 if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3199 return MCDisassembler_Fail;
3200 if (op) {
3201 if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3202 return MCDisassembler_Fail; // Writeback
3203 }
3204
3205 switch (MCInst_getOpcode(Inst)) {
3206 case ARM_VTBL2:
3207 case ARM_VTBX2:
3208 if (!Check(&S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder)))
3209 return MCDisassembler_Fail;
3210 break;
3211 default:
3212 if (!Check(&S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder)))
3213 return MCDisassembler_Fail;
3214 }
3215
3216 if (!Check(&S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
3217 return MCDisassembler_Fail;
3218
3219 return S;
3220 }
3221
DecodeThumbAddSpecialReg(MCInst * Inst,uint16_t Insn,uint64_t Address,const void * Decoder)3222 static DecodeStatus DecodeThumbAddSpecialReg(MCInst *Inst, uint16_t Insn,
3223 uint64_t Address, const void *Decoder)
3224 {
3225 DecodeStatus S = MCDisassembler_Success;
3226
3227 unsigned dst = fieldFromInstruction_2(Insn, 8, 3);
3228 unsigned imm = fieldFromInstruction_2(Insn, 0, 8);
3229
3230 if (!Check(&S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder)))
3231 return MCDisassembler_Fail;
3232
3233 switch(MCInst_getOpcode(Inst)) {
3234 default:
3235 return MCDisassembler_Fail;
3236 case ARM_tADR:
3237 break; // tADR does not explicitly represent the PC as an operand.
3238 case ARM_tADDrSPi:
3239 MCOperand_CreateReg0(Inst, ARM_SP);
3240 break;
3241 }
3242
3243 MCOperand_CreateImm0(Inst, imm);
3244 return S;
3245 }
3246
DecodeThumbBROperand(MCInst * Inst,unsigned Val,uint64_t Address,const void * Decoder)3247 static DecodeStatus DecodeThumbBROperand(MCInst *Inst, unsigned Val,
3248 uint64_t Address, const void *Decoder)
3249 {
3250 MCOperand_CreateImm0(Inst, SignExtend32(Val << 1, 12));
3251 return MCDisassembler_Success;
3252 }
3253
DecodeT2BROperand(MCInst * Inst,unsigned Val,uint64_t Address,const void * Decoder)3254 static DecodeStatus DecodeT2BROperand(MCInst *Inst, unsigned Val,
3255 uint64_t Address, const void *Decoder)
3256 {
3257 MCOperand_CreateImm0(Inst, SignExtend32(Val, 21));
3258 return MCDisassembler_Success;
3259 }
3260
DecodeThumbCmpBROperand(MCInst * Inst,unsigned Val,uint64_t Address,const void * Decoder)3261 static DecodeStatus DecodeThumbCmpBROperand(MCInst *Inst, unsigned Val,
3262 uint64_t Address, const void *Decoder)
3263 {
3264 MCOperand_CreateImm0(Inst, Val << 1);
3265 return MCDisassembler_Success;
3266 }
3267
DecodeThumbAddrModeRR(MCInst * Inst,unsigned Val,uint64_t Address,const void * Decoder)3268 static DecodeStatus DecodeThumbAddrModeRR(MCInst *Inst, unsigned Val,
3269 uint64_t Address, const void *Decoder)
3270 {
3271 DecodeStatus S = MCDisassembler_Success;
3272
3273 unsigned Rn = fieldFromInstruction_4(Val, 0, 3);
3274 unsigned Rm = fieldFromInstruction_4(Val, 3, 3);
3275
3276 if (!Check(&S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
3277 return MCDisassembler_Fail;
3278 if (!Check(&S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder)))
3279 return MCDisassembler_Fail;
3280
3281 return S;
3282 }
3283
DecodeThumbAddrModeIS(MCInst * Inst,unsigned Val,uint64_t Address,const void * Decoder)3284 static DecodeStatus DecodeThumbAddrModeIS(MCInst *Inst, unsigned Val,
3285 uint64_t Address, const void *Decoder)
3286 {
3287 DecodeStatus S = MCDisassembler_Success;
3288
3289 unsigned Rn = fieldFromInstruction_4(Val, 0, 3);
3290 unsigned imm = fieldFromInstruction_4(Val, 3, 5);
3291
3292 if (!Check(&S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
3293 return MCDisassembler_Fail;
3294 MCOperand_CreateImm0(Inst, imm);
3295
3296 return S;
3297 }
3298
DecodeThumbAddrModePC(MCInst * Inst,unsigned Val,uint64_t Address,const void * Decoder)3299 static DecodeStatus DecodeThumbAddrModePC(MCInst *Inst, unsigned Val,
3300 uint64_t Address, const void *Decoder)
3301 {
3302 unsigned imm = Val << 2;
3303
3304 MCOperand_CreateImm0(Inst, imm);
3305 //tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder);
3306
3307 return MCDisassembler_Success;
3308 }
3309
DecodeThumbAddrModeSP(MCInst * Inst,unsigned Val,uint64_t Address,const void * Decoder)3310 static DecodeStatus DecodeThumbAddrModeSP(MCInst *Inst, unsigned Val,
3311 uint64_t Address, const void *Decoder)
3312 {
3313 MCOperand_CreateReg0(Inst, ARM_SP);
3314 MCOperand_CreateImm0(Inst, Val);
3315
3316 return MCDisassembler_Success;
3317 }
3318
DecodeT2AddrModeSOReg(MCInst * Inst,unsigned Val,uint64_t Address,const void * Decoder)3319 static DecodeStatus DecodeT2AddrModeSOReg(MCInst *Inst, unsigned Val,
3320 uint64_t Address, const void *Decoder)
3321 {
3322 DecodeStatus S = MCDisassembler_Success;
3323
3324 unsigned Rn = fieldFromInstruction_4(Val, 6, 4);
3325 unsigned Rm = fieldFromInstruction_4(Val, 2, 4);
3326 unsigned imm = fieldFromInstruction_4(Val, 0, 2);
3327
3328 // Thumb stores cannot use PC as dest register.
3329 switch (MCInst_getOpcode(Inst)) {
3330 case ARM_t2STRHs:
3331 case ARM_t2STRBs:
3332 case ARM_t2STRs:
3333 if (Rn == 15)
3334 return MCDisassembler_Fail;
3335 default:
3336 break;
3337 }
3338
3339 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3340 return MCDisassembler_Fail;
3341 if (!Check(&S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
3342 return MCDisassembler_Fail;
3343 MCOperand_CreateImm0(Inst, imm);
3344
3345 return S;
3346 }
3347
DecodeT2LoadShift(MCInst * Inst,unsigned Insn,uint64_t Address,const void * Decoder)3348 static DecodeStatus DecodeT2LoadShift(MCInst *Inst, unsigned Insn,
3349 uint64_t Address, const void *Decoder)
3350 {
3351 DecodeStatus S = MCDisassembler_Success;
3352 unsigned addrmode;
3353 unsigned Rt = fieldFromInstruction_4(Insn, 12, 4);
3354 unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
3355 uint64_t featureBits = ARM_getFeatureBits(Inst->csh->mode);
3356 bool hasMP = ((featureBits & ARM_FeatureMP) != 0);
3357 bool hasV7Ops = ((featureBits & ARM_HasV7Ops) != 0);
3358
3359 if (Rn == 15) {
3360 switch (MCInst_getOpcode(Inst)) {
3361 case ARM_t2LDRBs:
3362 MCInst_setOpcode(Inst, ARM_t2LDRBpci);
3363 break;
3364 case ARM_t2LDRHs:
3365 MCInst_setOpcode(Inst, ARM_t2LDRHpci);
3366 break;
3367 case ARM_t2LDRSHs:
3368 MCInst_setOpcode(Inst, ARM_t2LDRSHpci);
3369 break;
3370 case ARM_t2LDRSBs:
3371 MCInst_setOpcode(Inst, ARM_t2LDRSBpci);
3372 break;
3373 case ARM_t2LDRs:
3374 MCInst_setOpcode(Inst, ARM_t2LDRpci);
3375 break;
3376 case ARM_t2PLDs:
3377 MCInst_setOpcode(Inst, ARM_t2PLDpci);
3378 break;
3379 case ARM_t2PLIs:
3380 MCInst_setOpcode(Inst, ARM_t2PLIpci);
3381 break;
3382 default:
3383 return MCDisassembler_Fail;
3384 }
3385
3386 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3387 }
3388
3389 if (Rt == 15) {
3390 switch (MCInst_getOpcode(Inst)) {
3391 case ARM_t2LDRSHs:
3392 return MCDisassembler_Fail;
3393 case ARM_t2LDRHs:
3394 MCInst_setOpcode(Inst, ARM_t2PLDWs);
3395 break;
3396 case ARM_t2LDRSBs:
3397 MCInst_setOpcode(Inst, ARM_t2PLIs);
3398 default:
3399 break;
3400 }
3401 }
3402
3403 switch (MCInst_getOpcode(Inst)) {
3404 case ARM_t2PLDs:
3405 break;
3406 case ARM_t2PLIs:
3407 if (!hasV7Ops)
3408 return MCDisassembler_Fail;
3409 break;
3410 case ARM_t2PLDWs:
3411 if (!hasV7Ops || !hasMP)
3412 return MCDisassembler_Fail;
3413 break;
3414 default:
3415 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3416 return MCDisassembler_Fail;
3417 }
3418
3419 addrmode = fieldFromInstruction_4(Insn, 4, 2);
3420 addrmode |= fieldFromInstruction_4(Insn, 0, 4) << 2;
3421 addrmode |= fieldFromInstruction_4(Insn, 16, 4) << 6;
3422 if (!Check(&S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder)))
3423 return MCDisassembler_Fail;
3424
3425 return S;
3426 }
3427
DecodeT2LoadImm8(MCInst * Inst,unsigned Insn,uint64_t Address,const void * Decoder)3428 static DecodeStatus DecodeT2LoadImm8(MCInst *Inst, unsigned Insn,
3429 uint64_t Address, const void* Decoder)
3430 {
3431 DecodeStatus S = MCDisassembler_Success;
3432
3433 unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
3434 unsigned Rt = fieldFromInstruction_4(Insn, 12, 4);
3435 unsigned U = fieldFromInstruction_4(Insn, 9, 1);
3436 unsigned imm = fieldFromInstruction_4(Insn, 0, 8);
3437 unsigned add = fieldFromInstruction_4(Insn, 9, 1);
3438
3439 uint64_t featureBits = ARM_getFeatureBits(Inst->csh->mode);
3440 bool hasMP = ((featureBits & ARM_FeatureMP) != 0);
3441 bool hasV7Ops = ((featureBits & ARM_HasV7Ops) != 0);
3442
3443 imm |= (U << 8);
3444 imm |= (Rn << 9);
3445 if (Rn == 15) {
3446 switch (MCInst_getOpcode(Inst)) {
3447 case ARM_t2LDRi8:
3448 MCInst_setOpcode(Inst, ARM_t2LDRpci);
3449 break;
3450 case ARM_t2LDRBi8:
3451 MCInst_setOpcode(Inst, ARM_t2LDRBpci);
3452 break;
3453 case ARM_t2LDRSBi8:
3454 MCInst_setOpcode(Inst, ARM_t2LDRSBpci);
3455 break;
3456 case ARM_t2LDRHi8:
3457 MCInst_setOpcode(Inst, ARM_t2LDRHpci);
3458 break;
3459 case ARM_t2LDRSHi8:
3460 MCInst_setOpcode(Inst, ARM_t2LDRSHpci);
3461 break;
3462 case ARM_t2PLDi8:
3463 MCInst_setOpcode(Inst, ARM_t2PLDpci);
3464 break;
3465 case ARM_t2PLIi8:
3466 MCInst_setOpcode(Inst, ARM_t2PLIpci);
3467 break;
3468 default:
3469 return MCDisassembler_Fail;
3470 }
3471 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3472 }
3473
3474 if (Rt == 15) {
3475 switch (MCInst_getOpcode(Inst)) {
3476 case ARM_t2LDRSHi8:
3477 return MCDisassembler_Fail;
3478 case ARM_t2LDRHi8:
3479 if (!add)
3480 MCInst_setOpcode(Inst, ARM_t2PLDWi8);
3481 break;
3482 case ARM_t2LDRSBi8:
3483 MCInst_setOpcode(Inst, ARM_t2PLIi8);
3484 break;
3485 default:
3486 break;
3487 }
3488 }
3489
3490 switch (MCInst_getOpcode(Inst)) {
3491 case ARM_t2PLDi8:
3492 break;
3493 case ARM_t2PLIi8:
3494 if (!hasV7Ops)
3495 return MCDisassembler_Fail;
3496 break;
3497 case ARM_t2PLDWi8:
3498 if (!hasV7Ops || !hasMP)
3499 return MCDisassembler_Fail;
3500 break;
3501 default:
3502 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3503 return MCDisassembler_Fail;
3504 }
3505
3506 if (!Check(&S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder)))
3507 return MCDisassembler_Fail;
3508 return S;
3509 }
3510
DecodeT2LoadImm12(MCInst * Inst,unsigned Insn,uint64_t Address,const void * Decoder)3511 static DecodeStatus DecodeT2LoadImm12(MCInst *Inst, unsigned Insn,
3512 uint64_t Address, const void* Decoder)
3513 {
3514 DecodeStatus S = MCDisassembler_Success;
3515
3516 unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
3517 unsigned Rt = fieldFromInstruction_4(Insn, 12, 4);
3518 unsigned imm = fieldFromInstruction_4(Insn, 0, 12);
3519 uint64_t featureBits = ARM_getFeatureBits(Inst->csh->mode);
3520 bool hasMP = ((featureBits & ARM_FeatureMP) != 0);
3521 bool hasV7Ops = ((featureBits & ARM_HasV7Ops) != 0);
3522
3523 imm |= (Rn << 13);
3524
3525 if (Rn == 15) {
3526 switch (MCInst_getOpcode(Inst)) {
3527 case ARM_t2LDRi12:
3528 MCInst_setOpcode(Inst, ARM_t2LDRpci);
3529 break;
3530 case ARM_t2LDRHi12:
3531 MCInst_setOpcode(Inst, ARM_t2LDRHpci);
3532 break;
3533 case ARM_t2LDRSHi12:
3534 MCInst_setOpcode(Inst, ARM_t2LDRSHpci);
3535 break;
3536 case ARM_t2LDRBi12:
3537 MCInst_setOpcode(Inst, ARM_t2LDRBpci);
3538 break;
3539 case ARM_t2LDRSBi12:
3540 MCInst_setOpcode(Inst, ARM_t2LDRSBpci);
3541 break;
3542 case ARM_t2PLDi12:
3543 MCInst_setOpcode(Inst, ARM_t2PLDpci);
3544 break;
3545 case ARM_t2PLIi12:
3546 MCInst_setOpcode(Inst, ARM_t2PLIpci);
3547 break;
3548 default:
3549 return MCDisassembler_Fail;
3550 }
3551 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3552 }
3553
3554 if (Rt == 15) {
3555 switch (MCInst_getOpcode(Inst)) {
3556 case ARM_t2LDRSHi12:
3557 return MCDisassembler_Fail;
3558 case ARM_t2LDRHi12:
3559 MCInst_setOpcode(Inst, ARM_t2PLDWi12);
3560 break;
3561 case ARM_t2LDRSBi12:
3562 MCInst_setOpcode(Inst, ARM_t2PLIi12);
3563 break;
3564 default:
3565 break;
3566 }
3567 }
3568
3569 switch (MCInst_getOpcode(Inst)) {
3570 case ARM_t2PLDi12:
3571 break;
3572 case ARM_t2PLIi12:
3573 if (!hasV7Ops)
3574 return MCDisassembler_Fail;
3575 break;
3576 case ARM_t2PLDWi12:
3577 if (!hasV7Ops || !hasMP)
3578 return MCDisassembler_Fail;
3579 break;
3580 default:
3581 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3582 return MCDisassembler_Fail;
3583 }
3584
3585 if (!Check(&S, DecodeT2AddrModeImm12(Inst, imm, Address, Decoder)))
3586 return MCDisassembler_Fail;
3587 return S;
3588 }
3589
DecodeT2LoadT(MCInst * Inst,unsigned Insn,uint64_t Address,const void * Decoder)3590 static DecodeStatus DecodeT2LoadT(MCInst *Inst, unsigned Insn,
3591 uint64_t Address, const void* Decoder)
3592 {
3593 DecodeStatus S = MCDisassembler_Success;
3594
3595 unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
3596 unsigned Rt = fieldFromInstruction_4(Insn, 12, 4);
3597 unsigned imm = fieldFromInstruction_4(Insn, 0, 8);
3598 imm |= (Rn << 9);
3599
3600 if (Rn == 15) {
3601 switch (MCInst_getOpcode(Inst)) {
3602 case ARM_t2LDRT:
3603 MCInst_setOpcode(Inst, ARM_t2LDRpci);
3604 break;
3605 case ARM_t2LDRBT:
3606 MCInst_setOpcode(Inst, ARM_t2LDRBpci);
3607 break;
3608 case ARM_t2LDRHT:
3609 MCInst_setOpcode(Inst, ARM_t2LDRHpci);
3610 break;
3611 case ARM_t2LDRSBT:
3612 MCInst_setOpcode(Inst, ARM_t2LDRSBpci);
3613 break;
3614 case ARM_t2LDRSHT:
3615 MCInst_setOpcode(Inst, ARM_t2LDRSHpci);
3616 break;
3617 default:
3618 return MCDisassembler_Fail;
3619 }
3620 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3621 }
3622
3623 if (!Check(&S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
3624 return MCDisassembler_Fail;
3625 if (!Check(&S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder)))
3626 return MCDisassembler_Fail;
3627 return S;
3628 }
3629
DecodeT2LoadLabel(MCInst * Inst,unsigned Insn,uint64_t Address,const void * Decoder)3630 static DecodeStatus DecodeT2LoadLabel(MCInst *Inst, unsigned Insn,
3631 uint64_t Address, const void* Decoder)
3632 {
3633 DecodeStatus S = MCDisassembler_Success;
3634
3635 unsigned Rt = fieldFromInstruction_4(Insn, 12, 4);
3636 unsigned U = fieldFromInstruction_4(Insn, 23, 1);
3637 int imm = fieldFromInstruction_4(Insn, 0, 12);
3638 uint64_t featureBits = ARM_getFeatureBits(Inst->csh->mode);
3639 bool hasV7Ops = ((featureBits & ARM_HasV7Ops) != 0);
3640
3641 if (Rt == 15) {
3642 switch (MCInst_getOpcode(Inst)) {
3643 case ARM_t2LDRBpci:
3644 case ARM_t2LDRHpci:
3645 MCInst_setOpcode(Inst, ARM_t2PLDpci);
3646 break;
3647 case ARM_t2LDRSBpci:
3648 MCInst_setOpcode(Inst, ARM_t2PLIpci);
3649 break;
3650 case ARM_t2LDRSHpci:
3651 return MCDisassembler_Fail;
3652 default:
3653 break;
3654 }
3655 }
3656
3657 switch(MCInst_getOpcode(Inst)) {
3658 case ARM_t2PLDpci:
3659 break;
3660 case ARM_t2PLIpci:
3661 if (!hasV7Ops)
3662 return MCDisassembler_Fail;
3663 break;
3664 default:
3665 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3666 return MCDisassembler_Fail;
3667 }
3668
3669 if (!U) {
3670 // Special case for #-0.
3671 if (imm == 0)
3672 imm = INT32_MIN;
3673 else
3674 imm = -imm;
3675 }
3676 MCOperand_CreateImm0(Inst, imm);
3677
3678 return S;
3679 }
3680
DecodeT2Imm8S4(MCInst * Inst,unsigned Val,uint64_t Address,const void * Decoder)3681 static DecodeStatus DecodeT2Imm8S4(MCInst *Inst, unsigned Val,
3682 uint64_t Address, const void *Decoder)
3683 {
3684 if (Val == 0)
3685 MCOperand_CreateImm0(Inst, INT32_MIN);
3686 else {
3687 int imm = Val & 0xFF;
3688
3689 if (!(Val & 0x100)) imm *= -1;
3690 MCOperand_CreateImm0(Inst, imm * 4);
3691 }
3692
3693 return MCDisassembler_Success;
3694 }
3695
DecodeT2AddrModeImm8s4(MCInst * Inst,unsigned Val,uint64_t Address,const void * Decoder)3696 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst *Inst, unsigned Val,
3697 uint64_t Address, const void *Decoder)
3698 {
3699 DecodeStatus S = MCDisassembler_Success;
3700
3701 unsigned Rn = fieldFromInstruction_4(Val, 9, 4);
3702 unsigned imm = fieldFromInstruction_4(Val, 0, 9);
3703
3704 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3705 return MCDisassembler_Fail;
3706 if (!Check(&S, DecodeT2Imm8S4(Inst, imm, Address, Decoder)))
3707 return MCDisassembler_Fail;
3708
3709 return S;
3710 }
3711
DecodeT2AddrModeImm0_1020s4(MCInst * Inst,unsigned Val,uint64_t Address,const void * Decoder)3712 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst *Inst,unsigned Val,
3713 uint64_t Address, const void *Decoder)
3714 {
3715 DecodeStatus S = MCDisassembler_Success;
3716
3717 unsigned Rn = fieldFromInstruction_4(Val, 8, 4);
3718 unsigned imm = fieldFromInstruction_4(Val, 0, 8);
3719
3720 if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
3721 return MCDisassembler_Fail;
3722
3723 MCOperand_CreateImm0(Inst, imm);
3724
3725 return S;
3726 }
3727
DecodeT2Imm8(MCInst * Inst,unsigned Val,uint64_t Address,const void * Decoder)3728 static DecodeStatus DecodeT2Imm8(MCInst *Inst, unsigned Val,
3729 uint64_t Address, const void *Decoder)
3730 {
3731 int imm = Val & 0xFF;
3732 if (Val == 0)
3733 imm = INT32_MIN;
3734 else if (!(Val & 0x100))
3735 imm *= -1;
3736 MCOperand_CreateImm0(Inst, imm);
3737
3738 return MCDisassembler_Success;
3739 }
3740
DecodeT2AddrModeImm8(MCInst * Inst,unsigned Val,uint64_t Address,const void * Decoder)3741 static DecodeStatus DecodeT2AddrModeImm8(MCInst *Inst, unsigned Val,
3742 uint64_t Address, const void *Decoder)
3743 {
3744 DecodeStatus S = MCDisassembler_Success;
3745
3746 unsigned Rn = fieldFromInstruction_4(Val, 9, 4);
3747 unsigned imm = fieldFromInstruction_4(Val, 0, 9);
3748
3749 // Thumb stores cannot use PC as dest register.
3750 switch (MCInst_getOpcode(Inst)) {
3751 case ARM_t2STRT:
3752 case ARM_t2STRBT:
3753 case ARM_t2STRHT:
3754 case ARM_t2STRi8:
3755 case ARM_t2STRHi8:
3756 case ARM_t2STRBi8:
3757 if (Rn == 15)
3758 return MCDisassembler_Fail;
3759 break;
3760 default:
3761 break;
3762 }
3763
3764 // Some instructions always use an additive offset.
3765 switch (MCInst_getOpcode(Inst)) {
3766 case ARM_t2LDRT:
3767 case ARM_t2LDRBT:
3768 case ARM_t2LDRHT:
3769 case ARM_t2LDRSBT:
3770 case ARM_t2LDRSHT:
3771 case ARM_t2STRT:
3772 case ARM_t2STRBT:
3773 case ARM_t2STRHT:
3774 imm |= 0x100;
3775 break;
3776 default:
3777 break;
3778 }
3779
3780 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3781 return MCDisassembler_Fail;
3782 if (!Check(&S, DecodeT2Imm8(Inst, imm, Address, Decoder)))
3783 return MCDisassembler_Fail;
3784
3785 return S;
3786 }
3787
DecodeT2LdStPre(MCInst * Inst,unsigned Insn,uint64_t Address,const void * Decoder)3788 static DecodeStatus DecodeT2LdStPre(MCInst *Inst, unsigned Insn,
3789 uint64_t Address, const void *Decoder)
3790 {
3791 DecodeStatus S = MCDisassembler_Success;
3792 unsigned load;
3793 unsigned Rt = fieldFromInstruction_4(Insn, 12, 4);
3794 unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
3795 unsigned addr = fieldFromInstruction_4(Insn, 0, 8);
3796 addr |= fieldFromInstruction_4(Insn, 9, 1) << 8;
3797 addr |= Rn << 9;
3798 load = fieldFromInstruction_4(Insn, 20, 1);
3799
3800 if (Rn == 15) {
3801 switch (MCInst_getOpcode(Inst)) {
3802 case ARM_t2LDR_PRE:
3803 case ARM_t2LDR_POST:
3804 MCInst_setOpcode(Inst, ARM_t2LDRpci);
3805 break;
3806 case ARM_t2LDRB_PRE:
3807 case ARM_t2LDRB_POST:
3808 MCInst_setOpcode(Inst, ARM_t2LDRBpci);
3809 break;
3810 case ARM_t2LDRH_PRE:
3811 case ARM_t2LDRH_POST:
3812 MCInst_setOpcode(Inst, ARM_t2LDRHpci);
3813 break;
3814 case ARM_t2LDRSB_PRE:
3815 case ARM_t2LDRSB_POST:
3816 if (Rt == 15)
3817 MCInst_setOpcode(Inst, ARM_t2PLIpci);
3818 else
3819 MCInst_setOpcode(Inst, ARM_t2LDRSBpci);
3820 break;
3821 case ARM_t2LDRSH_PRE:
3822 case ARM_t2LDRSH_POST:
3823 MCInst_setOpcode(Inst, ARM_t2LDRSHpci);
3824 break;
3825 default:
3826 return MCDisassembler_Fail;
3827 }
3828 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3829 }
3830
3831 if (!load) {
3832 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3833 return MCDisassembler_Fail;
3834 }
3835
3836 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3837 return MCDisassembler_Fail;
3838
3839 if (load) {
3840 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3841 return MCDisassembler_Fail;
3842 }
3843
3844 if (!Check(&S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder)))
3845 return MCDisassembler_Fail;
3846
3847 return S;
3848 }
3849
DecodeT2AddrModeImm12(MCInst * Inst,unsigned Val,uint64_t Address,const void * Decoder)3850 static DecodeStatus DecodeT2AddrModeImm12(MCInst *Inst, unsigned Val,
3851 uint64_t Address, const void *Decoder)
3852 {
3853 DecodeStatus S = MCDisassembler_Success;
3854
3855 unsigned Rn = fieldFromInstruction_4(Val, 13, 4);
3856 unsigned imm = fieldFromInstruction_4(Val, 0, 12);
3857
3858 // Thumb stores cannot use PC as dest register.
3859 switch (MCInst_getOpcode(Inst)) {
3860 case ARM_t2STRi12:
3861 case ARM_t2STRBi12:
3862 case ARM_t2STRHi12:
3863 if (Rn == 15)
3864 return MCDisassembler_Fail;
3865 default:
3866 break;
3867 }
3868
3869 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3870 return MCDisassembler_Fail;
3871 MCOperand_CreateImm0(Inst, imm);
3872
3873 return S;
3874 }
3875
DecodeThumbAddSPImm(MCInst * Inst,uint16_t Insn,uint64_t Address,const void * Decoder)3876 static DecodeStatus DecodeThumbAddSPImm(MCInst *Inst, uint16_t Insn,
3877 uint64_t Address, const void *Decoder)
3878 {
3879 unsigned imm = fieldFromInstruction_2(Insn, 0, 7);
3880
3881 MCOperand_CreateReg0(Inst, ARM_SP);
3882 MCOperand_CreateReg0(Inst, ARM_SP);
3883 MCOperand_CreateImm0(Inst, imm);
3884
3885 return MCDisassembler_Success;
3886 }
3887
DecodeThumbAddSPReg(MCInst * Inst,uint16_t Insn,uint64_t Address,const void * Decoder)3888 static DecodeStatus DecodeThumbAddSPReg(MCInst *Inst, uint16_t Insn,
3889 uint64_t Address, const void *Decoder)
3890 {
3891 DecodeStatus S = MCDisassembler_Success;
3892
3893 if (MCInst_getOpcode(Inst) == ARM_tADDrSP) {
3894 unsigned Rdm = fieldFromInstruction_2(Insn, 0, 3);
3895 Rdm |= fieldFromInstruction_2(Insn, 7, 1) << 3;
3896
3897 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
3898 return MCDisassembler_Fail;
3899 MCOperand_CreateReg0(Inst, ARM_SP);
3900 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
3901 return MCDisassembler_Fail;
3902 } else if (MCInst_getOpcode(Inst) == ARM_tADDspr) {
3903 unsigned Rm = fieldFromInstruction_2(Insn, 3, 4);
3904
3905 MCOperand_CreateReg0(Inst, ARM_SP);
3906 MCOperand_CreateReg0(Inst, ARM_SP);
3907 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3908 return MCDisassembler_Fail;
3909 }
3910
3911 return S;
3912 }
3913
DecodeThumbCPS(MCInst * Inst,uint16_t Insn,uint64_t Address,const void * Decoder)3914 static DecodeStatus DecodeThumbCPS(MCInst *Inst, uint16_t Insn,
3915 uint64_t Address, const void *Decoder)
3916 {
3917 unsigned imod = fieldFromInstruction_2(Insn, 4, 1) | 0x2;
3918 unsigned flags = fieldFromInstruction_2(Insn, 0, 3);
3919
3920 MCOperand_CreateImm0(Inst, imod);
3921 MCOperand_CreateImm0(Inst, flags);
3922
3923 return MCDisassembler_Success;
3924 }
3925
DecodePostIdxReg(MCInst * Inst,unsigned Insn,uint64_t Address,const void * Decoder)3926 static DecodeStatus DecodePostIdxReg(MCInst *Inst, unsigned Insn,
3927 uint64_t Address, const void *Decoder)
3928 {
3929 DecodeStatus S = MCDisassembler_Success;
3930 unsigned Rm = fieldFromInstruction_4(Insn, 0, 4);
3931 unsigned add = fieldFromInstruction_4(Insn, 4, 1);
3932
3933 if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
3934 return MCDisassembler_Fail;
3935 MCOperand_CreateImm0(Inst, add);
3936
3937 return S;
3938 }
3939
DecodeThumbBLXOffset(MCInst * Inst,unsigned Val,uint64_t Address,const void * Decoder)3940 static DecodeStatus DecodeThumbBLXOffset(MCInst *Inst, unsigned Val,
3941 uint64_t Address, const void *Decoder)
3942 {
3943 // Val is passed in as S:J1:J2:imm10H:imm10L:'0'
3944 // Note only one trailing zero not two. Also the J1 and J2 values are from
3945 // the encoded instruction. So here change to I1 and I2 values via:
3946 // I1 = NOT(J1 EOR S);
3947 // I2 = NOT(J2 EOR S);
3948 // and build the imm32 with two trailing zeros as documented:
3949 // imm32 = SignExtend(S:I1:I2:imm10H:imm10L:'00', 32);
3950 unsigned S = (Val >> 23) & 1;
3951 unsigned J1 = (Val >> 22) & 1;
3952 unsigned J2 = (Val >> 21) & 1;
3953 unsigned I1 = !(J1 ^ S);
3954 unsigned I2 = !(J2 ^ S);
3955 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21);
3956 int imm32 = SignExtend32(tmp << 1, 25);
3957
3958 MCOperand_CreateImm0(Inst, imm32);
3959 return MCDisassembler_Success;
3960 }
3961
DecodeCoprocessor(MCInst * Inst,unsigned Val,uint64_t Address,const void * Decoder)3962 static DecodeStatus DecodeCoprocessor(MCInst *Inst, unsigned Val,
3963 uint64_t Address, const void *Decoder)
3964 {
3965 if (Val == 0xA || Val == 0xB)
3966 return MCDisassembler_Fail;
3967
3968 MCOperand_CreateImm0(Inst, Val);
3969 return MCDisassembler_Success;
3970 }
3971
DecodeThumbTableBranch(MCInst * Inst,unsigned Insn,uint64_t Address,const void * Decoder)3972 static DecodeStatus DecodeThumbTableBranch(MCInst *Inst, unsigned Insn,
3973 uint64_t Address, const void *Decoder)
3974 {
3975 DecodeStatus S = MCDisassembler_Success;
3976
3977 unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
3978 unsigned Rm = fieldFromInstruction_4(Insn, 0, 4);
3979
3980 if (Rn == ARM_SP) S = MCDisassembler_SoftFail;
3981 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3982 return MCDisassembler_Fail;
3983 if (!Check(&S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
3984 return MCDisassembler_Fail;
3985 return S;
3986 }
3987
DecodeThumb2BCCInstruction(MCInst * Inst,unsigned Insn,uint64_t Address,const void * Decoder)3988 static DecodeStatus DecodeThumb2BCCInstruction(MCInst *Inst, unsigned Insn,
3989 uint64_t Address, const void *Decoder)
3990 {
3991 DecodeStatus S = MCDisassembler_Success;
3992 unsigned brtarget;
3993 unsigned pred = fieldFromInstruction_4(Insn, 22, 4);
3994 if (pred == 0xE || pred == 0xF) {
3995 unsigned imm;
3996 unsigned opc = fieldFromInstruction_4(Insn, 4, 28);
3997 switch (opc) {
3998 default:
3999 return MCDisassembler_Fail;
4000 case 0xf3bf8f4:
4001 MCInst_setOpcode(Inst, ARM_t2DSB);
4002 break;
4003 case 0xf3bf8f5:
4004 MCInst_setOpcode(Inst, ARM_t2DMB);
4005 break;
4006 case 0xf3bf8f6:
4007 MCInst_setOpcode(Inst, ARM_t2ISB);
4008 break;
4009 }
4010
4011 imm = fieldFromInstruction_4(Insn, 0, 4);
4012 return DecodeMemBarrierOption(Inst, imm, Address, Decoder);
4013 }
4014
4015 brtarget = fieldFromInstruction_4(Insn, 0, 11) << 1;
4016 brtarget |= fieldFromInstruction_4(Insn, 11, 1) << 19;
4017 brtarget |= fieldFromInstruction_4(Insn, 13, 1) << 18;
4018 brtarget |= fieldFromInstruction_4(Insn, 16, 6) << 12;
4019 brtarget |= fieldFromInstruction_4(Insn, 26, 1) << 20;
4020
4021 if (!Check(&S, DecodeT2BROperand(Inst, brtarget, Address, Decoder)))
4022 return MCDisassembler_Fail;
4023 if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4024 return MCDisassembler_Fail;
4025
4026 return S;
4027 }
4028
4029 // Decode a shifted immediate operand. These basically consist
4030 // of an 8-bit value, and a 4-bit directive that specifies either
4031 // a splat operation or a rotation.
DecodeT2SOImm(MCInst * Inst,unsigned Val,uint64_t Address,const void * Decoder)4032 static DecodeStatus DecodeT2SOImm(MCInst *Inst, unsigned Val,
4033 uint64_t Address, const void *Decoder)
4034 {
4035 unsigned ctrl = fieldFromInstruction_4(Val, 10, 2);
4036 if (ctrl == 0) {
4037 unsigned byte = fieldFromInstruction_4(Val, 8, 2);
4038 unsigned imm = fieldFromInstruction_4(Val, 0, 8);
4039 switch (byte) {
4040 case 0:
4041 MCOperand_CreateImm0(Inst, imm);
4042 break;
4043 case 1:
4044 MCOperand_CreateImm0(Inst, (imm << 16) | imm);
4045 break;
4046 case 2:
4047 MCOperand_CreateImm0(Inst, (imm << 24) | (imm << 8));
4048 break;
4049 case 3:
4050 MCOperand_CreateImm0(Inst, (imm << 24) | (imm << 16) | (imm << 8) | imm);
4051 break;
4052 }
4053 } else {
4054 unsigned unrot = fieldFromInstruction_4(Val, 0, 7) | 0x80;
4055 unsigned rot = fieldFromInstruction_4(Val, 7, 5);
4056 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31));
4057 MCOperand_CreateImm0(Inst, imm);
4058 }
4059
4060 return MCDisassembler_Success;
4061 }
4062
DecodeThumbBCCTargetOperand(MCInst * Inst,unsigned Val,uint64_t Address,const void * Decoder)4063 static DecodeStatus DecodeThumbBCCTargetOperand(MCInst *Inst, unsigned Val,
4064 uint64_t Address, const void *Decoder)
4065 {
4066 MCOperand_CreateImm0(Inst, SignExtend32(Val << 1, 9));
4067 return MCDisassembler_Success;
4068 }
4069
DecodeThumbBLTargetOperand(MCInst * Inst,unsigned Val,uint64_t Address,const void * Decoder)4070 static DecodeStatus DecodeThumbBLTargetOperand(MCInst *Inst, unsigned Val,
4071 uint64_t Address, const void *Decoder)
4072 {
4073 // Val is passed in as S:J1:J2:imm10:imm11
4074 // Note no trailing zero after imm11. Also the J1 and J2 values are from
4075 // the encoded instruction. So here change to I1 and I2 values via:
4076 // I1 = NOT(J1 EOR S);
4077 // I2 = NOT(J2 EOR S);
4078 // and build the imm32 with one trailing zero as documented:
4079 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32);
4080 unsigned S = (Val >> 23) & 1;
4081 unsigned J1 = (Val >> 22) & 1;
4082 unsigned J2 = (Val >> 21) & 1;
4083 unsigned I1 = !(J1 ^ S);
4084 unsigned I2 = !(J2 ^ S);
4085 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21);
4086 int imm32 = SignExtend32(tmp << 1, 25);
4087
4088 MCOperand_CreateImm0(Inst, imm32);
4089 return MCDisassembler_Success;
4090 }
4091
DecodeMemBarrierOption(MCInst * Inst,unsigned Val,uint64_t Address,const void * Decoder)4092 static DecodeStatus DecodeMemBarrierOption(MCInst *Inst, unsigned Val,
4093 uint64_t Address, const void *Decoder)
4094 {
4095 if (Val & ~0xf)
4096 return MCDisassembler_Fail;
4097
4098 MCOperand_CreateImm0(Inst, Val);
4099 return MCDisassembler_Success;
4100 }
4101
DecodeInstSyncBarrierOption(MCInst * Inst,unsigned Val,uint64_t Address,const void * Decoder)4102 static DecodeStatus DecodeInstSyncBarrierOption(MCInst *Inst, unsigned Val,
4103 uint64_t Address, const void *Decoder)
4104 {
4105 if (Val & ~0xf)
4106 return MCDisassembler_Fail;
4107
4108 MCOperand_CreateImm0(Inst, Val);
4109 return MCDisassembler_Success;
4110 }
4111
DecodeMSRMask(MCInst * Inst,unsigned Val,uint64_t Address,const void * Decoder)4112 static DecodeStatus DecodeMSRMask(MCInst *Inst, unsigned Val,
4113 uint64_t Address, const void *Decoder)
4114 {
4115 DecodeStatus S = MCDisassembler_Success;
4116 uint64_t FeatureBits = ARM_getFeatureBits(Inst->csh->mode);
4117 if (FeatureBits & ARM_FeatureMClass) {
4118 unsigned ValLow = Val & 0xff;
4119
4120 // Validate the SYSm value first.
4121 switch (ValLow) {
4122 case 0: // apsr
4123 case 1: // iapsr
4124 case 2: // eapsr
4125 case 3: // xpsr
4126 case 5: // ipsr
4127 case 6: // epsr
4128 case 7: // iepsr
4129 case 8: // msp
4130 case 9: // psp
4131 case 16: // primask
4132 case 20: // control
4133 break;
4134 case 17: // basepri
4135 case 18: // basepri_max
4136 case 19: // faultmask
4137 if (!(FeatureBits & ARM_HasV7Ops))
4138 // Values basepri, basepri_max and faultmask are only valid for v7m.
4139 return MCDisassembler_Fail;
4140 break;
4141 default:
4142 return MCDisassembler_Fail;
4143 }
4144
4145 if (MCInst_getOpcode(Inst) == ARM_t2MSR_M) {
4146 unsigned Mask = fieldFromInstruction_4(Val, 10, 2);
4147 if (!(FeatureBits & ARM_HasV7Ops)) {
4148 // The ARMv6-M MSR bits {11-10} can be only 0b10, other values are
4149 // unpredictable.
4150 if (Mask != 2)
4151 S = MCDisassembler_SoftFail;
4152 }
4153 else {
4154 // The ARMv7-M architecture stores an additional 2-bit mask value in
4155 // MSR bits {11-10}. The mask is used only with apsr, iapsr, eapsr and
4156 // xpsr, it has to be 0b10 in other cases. Bit mask{1} indicates if
4157 // the NZCVQ bits should be moved by the instruction. Bit mask{0}
4158 // indicates the move for the GE{3:0} bits, the mask{0} bit can be set
4159 // only if the processor includes the DSP extension.
4160 if (Mask == 0 || (Mask != 2 && ValLow > 3) ||
4161 (!(FeatureBits & ARM_FeatureDSPThumb2) && (Mask & 1)))
4162 S = MCDisassembler_SoftFail;
4163 }
4164 }
4165 } else {
4166 // A/R class
4167 if (Val == 0)
4168 return MCDisassembler_Fail;
4169 }
4170
4171 MCOperand_CreateImm0(Inst, Val);
4172 return S;
4173 }
4174
DecodeBankedReg(MCInst * Inst,unsigned Val,uint64_t Address,const void * Decoder)4175 static DecodeStatus DecodeBankedReg(MCInst *Inst, unsigned Val,
4176 uint64_t Address, const void *Decoder)
4177 {
4178
4179 unsigned R = fieldFromInstruction_4(Val, 5, 1);
4180 unsigned SysM = fieldFromInstruction_4(Val, 0, 5);
4181
4182 // The table of encodings for these banked registers comes from B9.2.3 of the
4183 // ARM ARM. There are patterns, but nothing regular enough to make this logic
4184 // neater. So by fiat, these values are UNPREDICTABLE:
4185 if (!R) {
4186 if (SysM == 0x7 || SysM == 0xf || SysM == 0x18 || SysM == 0x19 ||
4187 SysM == 0x1a || SysM == 0x1b)
4188 return MCDisassembler_SoftFail;
4189 } else {
4190 if (SysM != 0xe && SysM != 0x10 && SysM != 0x12 && SysM != 0x14 &&
4191 SysM != 0x16 && SysM != 0x1c && SysM != 0x1e)
4192 return MCDisassembler_SoftFail;
4193 }
4194
4195 MCOperand_CreateImm0(Inst, Val);
4196 return MCDisassembler_Success;
4197 }
4198
DecodeDoubleRegLoad(MCInst * Inst,unsigned Insn,uint64_t Address,const void * Decoder)4199 static DecodeStatus DecodeDoubleRegLoad(MCInst *Inst, unsigned Insn,
4200 uint64_t Address, const void *Decoder)
4201 {
4202 DecodeStatus S = MCDisassembler_Success;
4203
4204 unsigned Rt = fieldFromInstruction_4(Insn, 12, 4);
4205 unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
4206 unsigned pred = fieldFromInstruction_4(Insn, 28, 4);
4207
4208 if (Rn == 0xF)
4209 S = MCDisassembler_SoftFail;
4210
4211 if (!Check(&S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder)))
4212 return MCDisassembler_Fail;
4213 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4214 return MCDisassembler_Fail;
4215 if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4216 return MCDisassembler_Fail;
4217
4218 return S;
4219 }
4220
DecodeDoubleRegStore(MCInst * Inst,unsigned Insn,uint64_t Address,const void * Decoder)4221 static DecodeStatus DecodeDoubleRegStore(MCInst *Inst, unsigned Insn,
4222 uint64_t Address, const void *Decoder)
4223 {
4224 DecodeStatus S = MCDisassembler_Success;
4225
4226 unsigned Rd = fieldFromInstruction_4(Insn, 12, 4);
4227 unsigned Rt = fieldFromInstruction_4(Insn, 0, 4);
4228 unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
4229 unsigned pred = fieldFromInstruction_4(Insn, 28, 4);
4230
4231 if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
4232 return MCDisassembler_Fail;
4233
4234 if (Rn == 0xF || Rd == Rn || Rd == Rt || Rd == Rt+1)
4235 S = MCDisassembler_SoftFail;
4236
4237 if (!Check(&S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder)))
4238 return MCDisassembler_Fail;
4239 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4240 return MCDisassembler_Fail;
4241 if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4242 return MCDisassembler_Fail;
4243
4244 return S;
4245 }
4246
DecodeLDRPreImm(MCInst * Inst,unsigned Insn,uint64_t Address,const void * Decoder)4247 static DecodeStatus DecodeLDRPreImm(MCInst *Inst, unsigned Insn,
4248 uint64_t Address, const void *Decoder)
4249 {
4250 DecodeStatus S = MCDisassembler_Success;
4251 unsigned pred;
4252 unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
4253 unsigned Rt = fieldFromInstruction_4(Insn, 12, 4);
4254 unsigned imm = fieldFromInstruction_4(Insn, 0, 12);
4255 imm |= fieldFromInstruction_4(Insn, 16, 4) << 13;
4256 imm |= fieldFromInstruction_4(Insn, 23, 1) << 12;
4257 pred = fieldFromInstruction_4(Insn, 28, 4);
4258
4259 if (Rn == 0xF || Rn == Rt) S = MCDisassembler_SoftFail;
4260
4261 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4262 return MCDisassembler_Fail;
4263 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4264 return MCDisassembler_Fail;
4265 if (!Check(&S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
4266 return MCDisassembler_Fail;
4267 if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4268 return MCDisassembler_Fail;
4269
4270 return S;
4271 }
4272
DecodeLDRPreReg(MCInst * Inst,unsigned Insn,uint64_t Address,const void * Decoder)4273 static DecodeStatus DecodeLDRPreReg(MCInst *Inst, unsigned Insn,
4274 uint64_t Address, const void *Decoder)
4275 {
4276 DecodeStatus S = MCDisassembler_Success;
4277 unsigned pred, Rm;
4278 unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
4279 unsigned Rt = fieldFromInstruction_4(Insn, 12, 4);
4280 unsigned imm = fieldFromInstruction_4(Insn, 0, 12);
4281 imm |= fieldFromInstruction_4(Insn, 16, 4) << 13;
4282 imm |= fieldFromInstruction_4(Insn, 23, 1) << 12;
4283 pred = fieldFromInstruction_4(Insn, 28, 4);
4284 Rm = fieldFromInstruction_4(Insn, 0, 4);
4285
4286 if (Rn == 0xF || Rn == Rt) S = MCDisassembler_SoftFail;
4287 if (Rm == 0xF) S = MCDisassembler_SoftFail;
4288
4289 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4290 return MCDisassembler_Fail;
4291 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4292 return MCDisassembler_Fail;
4293 if (!Check(&S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
4294 return MCDisassembler_Fail;
4295 if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4296 return MCDisassembler_Fail;
4297
4298 return S;
4299 }
4300
DecodeSTRPreImm(MCInst * Inst,unsigned Insn,uint64_t Address,const void * Decoder)4301 static DecodeStatus DecodeSTRPreImm(MCInst *Inst, unsigned Insn,
4302 uint64_t Address, const void *Decoder)
4303 {
4304 DecodeStatus S = MCDisassembler_Success;
4305 unsigned pred;
4306 unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
4307 unsigned Rt = fieldFromInstruction_4(Insn, 12, 4);
4308 unsigned imm = fieldFromInstruction_4(Insn, 0, 12);
4309 imm |= fieldFromInstruction_4(Insn, 16, 4) << 13;
4310 imm |= fieldFromInstruction_4(Insn, 23, 1) << 12;
4311 pred = fieldFromInstruction_4(Insn, 28, 4);
4312
4313 if (Rn == 0xF || Rn == Rt) S = MCDisassembler_SoftFail;
4314
4315 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4316 return MCDisassembler_Fail;
4317 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4318 return MCDisassembler_Fail;
4319 if (!Check(&S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
4320 return MCDisassembler_Fail;
4321 if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4322 return MCDisassembler_Fail;
4323
4324 return S;
4325 }
4326
DecodeSTRPreReg(MCInst * Inst,unsigned Insn,uint64_t Address,const void * Decoder)4327 static DecodeStatus DecodeSTRPreReg(MCInst *Inst, unsigned Insn,
4328 uint64_t Address, const void *Decoder)
4329 {
4330 DecodeStatus S = MCDisassembler_Success;
4331 unsigned pred;
4332 unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
4333 unsigned Rt = fieldFromInstruction_4(Insn, 12, 4);
4334 unsigned imm = fieldFromInstruction_4(Insn, 0, 12);
4335 imm |= fieldFromInstruction_4(Insn, 16, 4) << 13;
4336 imm |= fieldFromInstruction_4(Insn, 23, 1) << 12;
4337 pred = fieldFromInstruction_4(Insn, 28, 4);
4338
4339 if (Rn == 0xF || Rn == Rt) S = MCDisassembler_SoftFail;
4340
4341 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4342 return MCDisassembler_Fail;
4343 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4344 return MCDisassembler_Fail;
4345 if (!Check(&S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
4346 return MCDisassembler_Fail;
4347 if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4348 return MCDisassembler_Fail;
4349
4350 return S;
4351 }
4352
DecodeVLD1LN(MCInst * Inst,unsigned Insn,uint64_t Address,const void * Decoder)4353 static DecodeStatus DecodeVLD1LN(MCInst *Inst, unsigned Insn,
4354 uint64_t Address, const void *Decoder)
4355 {
4356 DecodeStatus S = MCDisassembler_Success;
4357 unsigned size, align = 0, index = 0;
4358 unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
4359 unsigned Rm = fieldFromInstruction_4(Insn, 0, 4);
4360 unsigned Rd = fieldFromInstruction_4(Insn, 12, 4);
4361 Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4;
4362 size = fieldFromInstruction_4(Insn, 10, 2);
4363
4364 switch (size) {
4365 default:
4366 return MCDisassembler_Fail;
4367 case 0:
4368 if (fieldFromInstruction_4(Insn, 4, 1))
4369 return MCDisassembler_Fail; // UNDEFINED
4370 index = fieldFromInstruction_4(Insn, 5, 3);
4371 break;
4372 case 1:
4373 if (fieldFromInstruction_4(Insn, 5, 1))
4374 return MCDisassembler_Fail; // UNDEFINED
4375 index = fieldFromInstruction_4(Insn, 6, 2);
4376 if (fieldFromInstruction_4(Insn, 4, 1))
4377 align = 2;
4378 break;
4379 case 2:
4380 if (fieldFromInstruction_4(Insn, 6, 1))
4381 return MCDisassembler_Fail; // UNDEFINED
4382 index = fieldFromInstruction_4(Insn, 7, 1);
4383
4384 switch (fieldFromInstruction_4(Insn, 4, 2)) {
4385 case 0 :
4386 align = 0; break;
4387 case 3:
4388 align = 4; break;
4389 default:
4390 return MCDisassembler_Fail;
4391 }
4392 break;
4393 }
4394
4395 if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4396 return MCDisassembler_Fail;
4397 if (Rm != 0xF) { // Writeback
4398 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4399 return MCDisassembler_Fail;
4400 }
4401 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4402 return MCDisassembler_Fail;
4403 MCOperand_CreateImm0(Inst, align);
4404 if (Rm != 0xF) {
4405 if (Rm != 0xD) {
4406 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4407 return MCDisassembler_Fail;
4408 } else
4409 MCOperand_CreateReg0(Inst, 0);
4410 }
4411
4412 if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4413 return MCDisassembler_Fail;
4414 MCOperand_CreateImm0(Inst, index);
4415
4416 return S;
4417 }
4418
DecodeVST1LN(MCInst * Inst,unsigned Insn,uint64_t Address,const void * Decoder)4419 static DecodeStatus DecodeVST1LN(MCInst *Inst, unsigned Insn,
4420 uint64_t Address, const void *Decoder)
4421 {
4422 DecodeStatus S = MCDisassembler_Success;
4423 unsigned size, align = 0, index = 0;
4424 unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
4425 unsigned Rm = fieldFromInstruction_4(Insn, 0, 4);
4426 unsigned Rd = fieldFromInstruction_4(Insn, 12, 4);
4427 Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4;
4428 size = fieldFromInstruction_4(Insn, 10, 2);
4429
4430 switch (size) {
4431 default:
4432 return MCDisassembler_Fail;
4433 case 0:
4434 if (fieldFromInstruction_4(Insn, 4, 1))
4435 return MCDisassembler_Fail; // UNDEFINED
4436 index = fieldFromInstruction_4(Insn, 5, 3);
4437 break;
4438 case 1:
4439 if (fieldFromInstruction_4(Insn, 5, 1))
4440 return MCDisassembler_Fail; // UNDEFINED
4441 index = fieldFromInstruction_4(Insn, 6, 2);
4442 if (fieldFromInstruction_4(Insn, 4, 1))
4443 align = 2;
4444 break;
4445 case 2:
4446 if (fieldFromInstruction_4(Insn, 6, 1))
4447 return MCDisassembler_Fail; // UNDEFINED
4448 index = fieldFromInstruction_4(Insn, 7, 1);
4449
4450 switch (fieldFromInstruction_4(Insn, 4, 2)) {
4451 case 0:
4452 align = 0; break;
4453 case 3:
4454 align = 4; break;
4455 default:
4456 return MCDisassembler_Fail;
4457 }
4458 break;
4459 }
4460
4461 if (Rm != 0xF) { // Writeback
4462 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4463 return MCDisassembler_Fail;
4464 }
4465 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4466 return MCDisassembler_Fail;
4467 MCOperand_CreateImm0(Inst, align);
4468 if (Rm != 0xF) {
4469 if (Rm != 0xD) {
4470 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4471 return MCDisassembler_Fail;
4472 } else
4473 MCOperand_CreateReg0(Inst, 0);
4474 }
4475
4476 if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4477 return MCDisassembler_Fail;
4478 MCOperand_CreateImm0(Inst, index);
4479
4480 return S;
4481 }
4482
DecodeVLD2LN(MCInst * Inst,unsigned Insn,uint64_t Address,const void * Decoder)4483 static DecodeStatus DecodeVLD2LN(MCInst *Inst, unsigned Insn,
4484 uint64_t Address, const void *Decoder)
4485 {
4486 DecodeStatus S = MCDisassembler_Success;
4487 unsigned size, align = 0, index = 0, inc = 1;
4488 unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
4489 unsigned Rm = fieldFromInstruction_4(Insn, 0, 4);
4490 unsigned Rd = fieldFromInstruction_4(Insn, 12, 4);
4491 Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4;
4492 size = fieldFromInstruction_4(Insn, 10, 2);
4493
4494 switch (size) {
4495 default:
4496 return MCDisassembler_Fail;
4497 case 0:
4498 index = fieldFromInstruction_4(Insn, 5, 3);
4499 if (fieldFromInstruction_4(Insn, 4, 1))
4500 align = 2;
4501 break;
4502 case 1:
4503 index = fieldFromInstruction_4(Insn, 6, 2);
4504 if (fieldFromInstruction_4(Insn, 4, 1))
4505 align = 4;
4506 if (fieldFromInstruction_4(Insn, 5, 1))
4507 inc = 2;
4508 break;
4509 case 2:
4510 if (fieldFromInstruction_4(Insn, 5, 1))
4511 return MCDisassembler_Fail; // UNDEFINED
4512 index = fieldFromInstruction_4(Insn, 7, 1);
4513 if (fieldFromInstruction_4(Insn, 4, 1) != 0)
4514 align = 8;
4515 if (fieldFromInstruction_4(Insn, 6, 1))
4516 inc = 2;
4517 break;
4518 }
4519
4520 if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4521 return MCDisassembler_Fail;
4522 if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4523 return MCDisassembler_Fail;
4524 if (Rm != 0xF) { // Writeback
4525 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4526 return MCDisassembler_Fail;
4527 }
4528 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4529 return MCDisassembler_Fail;
4530 MCOperand_CreateImm0(Inst, align);
4531 if (Rm != 0xF) {
4532 if (Rm != 0xD) {
4533 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4534 return MCDisassembler_Fail;
4535 } else
4536 MCOperand_CreateReg0(Inst, 0);
4537 }
4538
4539 if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4540 return MCDisassembler_Fail;
4541 if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4542 return MCDisassembler_Fail;
4543 MCOperand_CreateImm0(Inst, index);
4544
4545 return S;
4546 }
4547
DecodeVST2LN(MCInst * Inst,unsigned Insn,uint64_t Address,const void * Decoder)4548 static DecodeStatus DecodeVST2LN(MCInst *Inst, unsigned Insn,
4549 uint64_t Address, const void *Decoder)
4550 {
4551 DecodeStatus S = MCDisassembler_Success;
4552 unsigned size, align = 0, index = 0, inc = 1;
4553 unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
4554 unsigned Rm = fieldFromInstruction_4(Insn, 0, 4);
4555 unsigned Rd = fieldFromInstruction_4(Insn, 12, 4);
4556 Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4;
4557 size = fieldFromInstruction_4(Insn, 10, 2);
4558
4559 switch (size) {
4560 default:
4561 return MCDisassembler_Fail;
4562 case 0:
4563 index = fieldFromInstruction_4(Insn, 5, 3);
4564 if (fieldFromInstruction_4(Insn, 4, 1))
4565 align = 2;
4566 break;
4567 case 1:
4568 index = fieldFromInstruction_4(Insn, 6, 2);
4569 if (fieldFromInstruction_4(Insn, 4, 1))
4570 align = 4;
4571 if (fieldFromInstruction_4(Insn, 5, 1))
4572 inc = 2;
4573 break;
4574 case 2:
4575 if (fieldFromInstruction_4(Insn, 5, 1))
4576 return MCDisassembler_Fail; // UNDEFINED
4577 index = fieldFromInstruction_4(Insn, 7, 1);
4578 if (fieldFromInstruction_4(Insn, 4, 1) != 0)
4579 align = 8;
4580 if (fieldFromInstruction_4(Insn, 6, 1))
4581 inc = 2;
4582 break;
4583 }
4584
4585 if (Rm != 0xF) { // Writeback
4586 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4587 return MCDisassembler_Fail;
4588 }
4589 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4590 return MCDisassembler_Fail;
4591 MCOperand_CreateImm0(Inst, align);
4592 if (Rm != 0xF) {
4593 if (Rm != 0xD) {
4594 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4595 return MCDisassembler_Fail;
4596 } else
4597 MCOperand_CreateReg0(Inst, 0);
4598 }
4599
4600 if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4601 return MCDisassembler_Fail;
4602 if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4603 return MCDisassembler_Fail;
4604 MCOperand_CreateImm0(Inst, index);
4605
4606 return S;
4607 }
4608
DecodeVLD3LN(MCInst * Inst,unsigned Insn,uint64_t Address,const void * Decoder)4609 static DecodeStatus DecodeVLD3LN(MCInst *Inst, unsigned Insn,
4610 uint64_t Address, const void *Decoder)
4611 {
4612 DecodeStatus S = MCDisassembler_Success;
4613 unsigned size, align = 0, index = 0, inc = 1;
4614 unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
4615 unsigned Rm = fieldFromInstruction_4(Insn, 0, 4);
4616 unsigned Rd = fieldFromInstruction_4(Insn, 12, 4);
4617 Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4;
4618 size = fieldFromInstruction_4(Insn, 10, 2);
4619
4620 switch (size) {
4621 default:
4622 return MCDisassembler_Fail;
4623 case 0:
4624 if (fieldFromInstruction_4(Insn, 4, 1))
4625 return MCDisassembler_Fail; // UNDEFINED
4626 index = fieldFromInstruction_4(Insn, 5, 3);
4627 break;
4628 case 1:
4629 if (fieldFromInstruction_4(Insn, 4, 1))
4630 return MCDisassembler_Fail; // UNDEFINED
4631 index = fieldFromInstruction_4(Insn, 6, 2);
4632 if (fieldFromInstruction_4(Insn, 5, 1))
4633 inc = 2;
4634 break;
4635 case 2:
4636 if (fieldFromInstruction_4(Insn, 4, 2))
4637 return MCDisassembler_Fail; // UNDEFINED
4638 index = fieldFromInstruction_4(Insn, 7, 1);
4639 if (fieldFromInstruction_4(Insn, 6, 1))
4640 inc = 2;
4641 break;
4642 }
4643
4644 if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4645 return MCDisassembler_Fail;
4646 if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4647 return MCDisassembler_Fail;
4648 if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4649 return MCDisassembler_Fail;
4650
4651 if (Rm != 0xF) { // Writeback
4652 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4653 return MCDisassembler_Fail;
4654 }
4655 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4656 return MCDisassembler_Fail;
4657 MCOperand_CreateImm0(Inst, align);
4658 if (Rm != 0xF) {
4659 if (Rm != 0xD) {
4660 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4661 return MCDisassembler_Fail;
4662 } else
4663 MCOperand_CreateReg0(Inst, 0);
4664 }
4665
4666 if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4667 return MCDisassembler_Fail;
4668 if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4669 return MCDisassembler_Fail;
4670 if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4671 return MCDisassembler_Fail;
4672 MCOperand_CreateImm0(Inst, index);
4673
4674 return S;
4675 }
4676
DecodeVST3LN(MCInst * Inst,unsigned Insn,uint64_t Address,const void * Decoder)4677 static DecodeStatus DecodeVST3LN(MCInst *Inst, unsigned Insn,
4678 uint64_t Address, const void *Decoder)
4679 {
4680 DecodeStatus S = MCDisassembler_Success;
4681 unsigned size, align = 0, index = 0, inc = 1;
4682 unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
4683 unsigned Rm = fieldFromInstruction_4(Insn, 0, 4);
4684 unsigned Rd = fieldFromInstruction_4(Insn, 12, 4);
4685 Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4;
4686 size = fieldFromInstruction_4(Insn, 10, 2);
4687
4688 switch (size) {
4689 default:
4690 return MCDisassembler_Fail;
4691 case 0:
4692 if (fieldFromInstruction_4(Insn, 4, 1))
4693 return MCDisassembler_Fail; // UNDEFINED
4694 index = fieldFromInstruction_4(Insn, 5, 3);
4695 break;
4696 case 1:
4697 if (fieldFromInstruction_4(Insn, 4, 1))
4698 return MCDisassembler_Fail; // UNDEFINED
4699 index = fieldFromInstruction_4(Insn, 6, 2);
4700 if (fieldFromInstruction_4(Insn, 5, 1))
4701 inc = 2;
4702 break;
4703 case 2:
4704 if (fieldFromInstruction_4(Insn, 4, 2))
4705 return MCDisassembler_Fail; // UNDEFINED
4706 index = fieldFromInstruction_4(Insn, 7, 1);
4707 if (fieldFromInstruction_4(Insn, 6, 1))
4708 inc = 2;
4709 break;
4710 }
4711
4712 if (Rm != 0xF) { // Writeback
4713 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4714 return MCDisassembler_Fail;
4715 }
4716 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4717 return MCDisassembler_Fail;
4718 MCOperand_CreateImm0(Inst, align);
4719 if (Rm != 0xF) {
4720 if (Rm != 0xD) {
4721 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4722 return MCDisassembler_Fail;
4723 } else
4724 MCOperand_CreateReg0(Inst, 0);
4725 }
4726
4727 if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4728 return MCDisassembler_Fail;
4729 if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4730 return MCDisassembler_Fail;
4731 if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4732 return MCDisassembler_Fail;
4733 MCOperand_CreateImm0(Inst, index);
4734
4735 return S;
4736 }
4737
DecodeVLD4LN(MCInst * Inst,unsigned Insn,uint64_t Address,const void * Decoder)4738 static DecodeStatus DecodeVLD4LN(MCInst *Inst, unsigned Insn,
4739 uint64_t Address, const void *Decoder)
4740 {
4741 DecodeStatus S = MCDisassembler_Success;
4742 unsigned size, align = 0, index = 0, inc = 1;
4743 unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
4744 unsigned Rm = fieldFromInstruction_4(Insn, 0, 4);
4745 unsigned Rd = fieldFromInstruction_4(Insn, 12, 4);
4746 Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4;
4747 size = fieldFromInstruction_4(Insn, 10, 2);
4748
4749 switch (size) {
4750 default:
4751 return MCDisassembler_Fail;
4752 case 0:
4753 if (fieldFromInstruction_4(Insn, 4, 1))
4754 align = 4;
4755 index = fieldFromInstruction_4(Insn, 5, 3);
4756 break;
4757 case 1:
4758 if (fieldFromInstruction_4(Insn, 4, 1))
4759 align = 8;
4760 index = fieldFromInstruction_4(Insn, 6, 2);
4761 if (fieldFromInstruction_4(Insn, 5, 1))
4762 inc = 2;
4763 break;
4764 case 2:
4765 switch (fieldFromInstruction_4(Insn, 4, 2)) {
4766 case 0:
4767 align = 0; break;
4768 case 3:
4769 return MCDisassembler_Fail;
4770 default:
4771 align = 4 << fieldFromInstruction_4(Insn, 4, 2); break;
4772 }
4773
4774 index = fieldFromInstruction_4(Insn, 7, 1);
4775 if (fieldFromInstruction_4(Insn, 6, 1))
4776 inc = 2;
4777 break;
4778 }
4779
4780 if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4781 return MCDisassembler_Fail;
4782 if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4783 return MCDisassembler_Fail;
4784 if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4785 return MCDisassembler_Fail;
4786 if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
4787 return MCDisassembler_Fail;
4788
4789 if (Rm != 0xF) { // Writeback
4790 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4791 return MCDisassembler_Fail;
4792 }
4793 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4794 return MCDisassembler_Fail;
4795 MCOperand_CreateImm0(Inst, align);
4796 if (Rm != 0xF) {
4797 if (Rm != 0xD) {
4798 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4799 return MCDisassembler_Fail;
4800 } else
4801 MCOperand_CreateReg0(Inst, 0);
4802 }
4803
4804 if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4805 return MCDisassembler_Fail;
4806 if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4807 return MCDisassembler_Fail;
4808 if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4809 return MCDisassembler_Fail;
4810 if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
4811 return MCDisassembler_Fail;
4812 MCOperand_CreateImm0(Inst, index);
4813
4814 return S;
4815 }
4816
DecodeVST4LN(MCInst * Inst,unsigned Insn,uint64_t Address,const void * Decoder)4817 static DecodeStatus DecodeVST4LN(MCInst *Inst, unsigned Insn,
4818 uint64_t Address, const void *Decoder)
4819 {
4820 DecodeStatus S = MCDisassembler_Success;
4821 unsigned size, align = 0, index = 0, inc = 1;
4822 unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
4823 unsigned Rm = fieldFromInstruction_4(Insn, 0, 4);
4824 unsigned Rd = fieldFromInstruction_4(Insn, 12, 4);
4825 Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4;
4826 size = fieldFromInstruction_4(Insn, 10, 2);
4827
4828 switch (size) {
4829 default:
4830 return MCDisassembler_Fail;
4831 case 0:
4832 if (fieldFromInstruction_4(Insn, 4, 1))
4833 align = 4;
4834 index = fieldFromInstruction_4(Insn, 5, 3);
4835 break;
4836 case 1:
4837 if (fieldFromInstruction_4(Insn, 4, 1))
4838 align = 8;
4839 index = fieldFromInstruction_4(Insn, 6, 2);
4840 if (fieldFromInstruction_4(Insn, 5, 1))
4841 inc = 2;
4842 break;
4843 case 2:
4844 switch (fieldFromInstruction_4(Insn, 4, 2)) {
4845 case 0:
4846 align = 0; break;
4847 case 3:
4848 return MCDisassembler_Fail;
4849 default:
4850 align = 4 << fieldFromInstruction_4(Insn, 4, 2); break;
4851 }
4852
4853 index = fieldFromInstruction_4(Insn, 7, 1);
4854 if (fieldFromInstruction_4(Insn, 6, 1))
4855 inc = 2;
4856 break;
4857 }
4858
4859 if (Rm != 0xF) { // Writeback
4860 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4861 return MCDisassembler_Fail;
4862 }
4863 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4864 return MCDisassembler_Fail;
4865 MCOperand_CreateImm0(Inst, align);
4866 if (Rm != 0xF) {
4867 if (Rm != 0xD) {
4868 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4869 return MCDisassembler_Fail;
4870 } else
4871 MCOperand_CreateReg0(Inst, 0);
4872 }
4873
4874 if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4875 return MCDisassembler_Fail;
4876 if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4877 return MCDisassembler_Fail;
4878 if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4879 return MCDisassembler_Fail;
4880 if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
4881 return MCDisassembler_Fail;
4882 MCOperand_CreateImm0(Inst, index);
4883
4884 return S;
4885 }
4886
DecodeVMOVSRR(MCInst * Inst,unsigned Insn,uint64_t Address,const void * Decoder)4887 static DecodeStatus DecodeVMOVSRR(MCInst *Inst, unsigned Insn,
4888 uint64_t Address, const void *Decoder)
4889 {
4890 DecodeStatus S = MCDisassembler_Success;
4891 unsigned Rt = fieldFromInstruction_4(Insn, 12, 4);
4892 unsigned Rt2 = fieldFromInstruction_4(Insn, 16, 4);
4893 unsigned Rm = fieldFromInstruction_4(Insn, 5, 1);
4894 unsigned pred = fieldFromInstruction_4(Insn, 28, 4);
4895 Rm |= fieldFromInstruction_4(Insn, 0, 4) << 1;
4896
4897 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
4898 S = MCDisassembler_SoftFail;
4899
4900 if (!Check(&S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
4901 return MCDisassembler_Fail;
4902 if (!Check(&S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
4903 return MCDisassembler_Fail;
4904 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
4905 return MCDisassembler_Fail;
4906 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
4907 return MCDisassembler_Fail;
4908 if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4909 return MCDisassembler_Fail;
4910
4911 return S;
4912 }
4913
DecodeVMOVRRS(MCInst * Inst,unsigned Insn,uint64_t Address,const void * Decoder)4914 static DecodeStatus DecodeVMOVRRS(MCInst *Inst, unsigned Insn,
4915 uint64_t Address, const void *Decoder)
4916 {
4917 DecodeStatus S = MCDisassembler_Success;
4918 unsigned Rt = fieldFromInstruction_4(Insn, 12, 4);
4919 unsigned Rt2 = fieldFromInstruction_4(Insn, 16, 4);
4920 unsigned Rm = fieldFromInstruction_4(Insn, 5, 1);
4921 unsigned pred = fieldFromInstruction_4(Insn, 28, 4);
4922 Rm |= fieldFromInstruction_4(Insn, 0, 4) << 1;
4923
4924 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
4925 S = MCDisassembler_SoftFail;
4926
4927 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
4928 return MCDisassembler_Fail;
4929 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
4930 return MCDisassembler_Fail;
4931 if (!Check(&S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
4932 return MCDisassembler_Fail;
4933 if (!Check(&S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
4934 return MCDisassembler_Fail;
4935 if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4936 return MCDisassembler_Fail;
4937
4938 return S;
4939 }
4940
DecodeIT(MCInst * Inst,unsigned Insn,uint64_t Address,const void * Decoder)4941 static DecodeStatus DecodeIT(MCInst *Inst, unsigned Insn,
4942 uint64_t Address, const void *Decoder)
4943 {
4944 DecodeStatus S = MCDisassembler_Success;
4945 unsigned pred = fieldFromInstruction_4(Insn, 4, 4);
4946 unsigned mask = fieldFromInstruction_4(Insn, 0, 4);
4947
4948 if (pred == 0xF) {
4949 pred = 0xE;
4950 S = MCDisassembler_SoftFail;
4951 }
4952
4953 if (mask == 0x0)
4954 return MCDisassembler_Fail;
4955
4956 MCOperand_CreateImm0(Inst, pred);
4957 MCOperand_CreateImm0(Inst, mask);
4958 return S;
4959 }
4960
DecodeT2LDRDPreInstruction(MCInst * Inst,unsigned Insn,uint64_t Address,const void * Decoder)4961 static DecodeStatus DecodeT2LDRDPreInstruction(MCInst *Inst, unsigned Insn,
4962 uint64_t Address, const void *Decoder)
4963 {
4964 DecodeStatus S = MCDisassembler_Success;
4965
4966 unsigned Rt = fieldFromInstruction_4(Insn, 12, 4);
4967 unsigned Rt2 = fieldFromInstruction_4(Insn, 8, 4);
4968 unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
4969 unsigned addr = fieldFromInstruction_4(Insn, 0, 8);
4970 unsigned W = fieldFromInstruction_4(Insn, 21, 1);
4971 unsigned U = fieldFromInstruction_4(Insn, 23, 1);
4972 unsigned P = fieldFromInstruction_4(Insn, 24, 1);
4973 bool writeback = (W == 1) | (P == 0);
4974
4975 addr |= (U << 8) | (Rn << 9);
4976
4977 if (writeback && (Rn == Rt || Rn == Rt2))
4978 Check(&S, MCDisassembler_SoftFail);
4979 if (Rt == Rt2)
4980 Check(&S, MCDisassembler_SoftFail);
4981
4982 // Rt
4983 if (!Check(&S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
4984 return MCDisassembler_Fail;
4985 // Rt2
4986 if (!Check(&S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
4987 return MCDisassembler_Fail;
4988 // Writeback operand
4989 if (!Check(&S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
4990 return MCDisassembler_Fail;
4991 // addr
4992 if (!Check(&S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
4993 return MCDisassembler_Fail;
4994
4995 return S;
4996 }
4997
DecodeT2STRDPreInstruction(MCInst * Inst,unsigned Insn,uint64_t Address,const void * Decoder)4998 static DecodeStatus DecodeT2STRDPreInstruction(MCInst *Inst, unsigned Insn,
4999 uint64_t Address, const void *Decoder)
5000 {
5001 DecodeStatus S = MCDisassembler_Success;
5002
5003 unsigned Rt = fieldFromInstruction_4(Insn, 12, 4);
5004 unsigned Rt2 = fieldFromInstruction_4(Insn, 8, 4);
5005 unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
5006 unsigned addr = fieldFromInstruction_4(Insn, 0, 8);
5007 unsigned W = fieldFromInstruction_4(Insn, 21, 1);
5008 unsigned U = fieldFromInstruction_4(Insn, 23, 1);
5009 unsigned P = fieldFromInstruction_4(Insn, 24, 1);
5010 bool writeback = (W == 1) | (P == 0);
5011
5012 addr |= (U << 8) | (Rn << 9);
5013
5014 if (writeback && (Rn == Rt || Rn == Rt2))
5015 Check(&S, MCDisassembler_SoftFail);
5016
5017 // Writeback operand
5018 if (!Check(&S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
5019 return MCDisassembler_Fail;
5020 // Rt
5021 if (!Check(&S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
5022 return MCDisassembler_Fail;
5023 // Rt2
5024 if (!Check(&S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
5025 return MCDisassembler_Fail;
5026 // addr
5027 if (!Check(&S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
5028 return MCDisassembler_Fail;
5029
5030 return S;
5031 }
5032
DecodeT2Adr(MCInst * Inst,uint32_t Insn,uint64_t Address,const void * Decoder)5033 static DecodeStatus DecodeT2Adr(MCInst *Inst, uint32_t Insn,
5034 uint64_t Address, const void *Decoder)
5035 {
5036 unsigned Val;
5037 unsigned sign1 = fieldFromInstruction_4(Insn, 21, 1);
5038 unsigned sign2 = fieldFromInstruction_4(Insn, 23, 1);
5039 if (sign1 != sign2) return MCDisassembler_Fail;
5040
5041 Val = fieldFromInstruction_4(Insn, 0, 8);
5042 Val |= fieldFromInstruction_4(Insn, 12, 3) << 8;
5043 Val |= fieldFromInstruction_4(Insn, 26, 1) << 11;
5044 Val |= sign1 << 12;
5045 MCOperand_CreateImm0(Inst, SignExtend32(Val, 13));
5046
5047 return MCDisassembler_Success;
5048 }
5049
DecodeT2ShifterImmOperand(MCInst * Inst,uint32_t Val,uint64_t Address,const void * Decoder)5050 static DecodeStatus DecodeT2ShifterImmOperand(MCInst *Inst, uint32_t Val,
5051 uint64_t Address, const void *Decoder)
5052 {
5053 DecodeStatus S = MCDisassembler_Success;
5054
5055 // Shift of "asr #32" is not allowed in Thumb2 mode.
5056 if (Val == 0x20)
5057 S = MCDisassembler_Fail;
5058 MCOperand_CreateImm0(Inst, Val);
5059
5060 return S;
5061 }
5062
DecodeSwap(MCInst * Inst,unsigned Insn,uint64_t Address,const void * Decoder)5063 static DecodeStatus DecodeSwap(MCInst *Inst, unsigned Insn,
5064 uint64_t Address, const void *Decoder)
5065 {
5066 DecodeStatus S;
5067
5068 unsigned Rt = fieldFromInstruction_4(Insn, 12, 4);
5069 unsigned Rt2 = fieldFromInstruction_4(Insn, 0, 4);
5070 unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
5071 unsigned pred = fieldFromInstruction_4(Insn, 28, 4);
5072
5073 if (pred == 0xF)
5074 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
5075
5076 S = MCDisassembler_Success;
5077
5078 if (Rt == Rn || Rn == Rt2)
5079 S = MCDisassembler_SoftFail;
5080
5081 if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
5082 return MCDisassembler_Fail;
5083 if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
5084 return MCDisassembler_Fail;
5085 if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
5086 return MCDisassembler_Fail;
5087 if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
5088 return MCDisassembler_Fail;
5089
5090 return S;
5091 }
5092
DecodeVCVTD(MCInst * Inst,unsigned Insn,uint64_t Address,const void * Decoder)5093 static DecodeStatus DecodeVCVTD(MCInst *Inst, unsigned Insn,
5094 uint64_t Address, const void *Decoder)
5095 {
5096 DecodeStatus S = MCDisassembler_Success;
5097 unsigned Vm, imm, cmode, op;
5098 unsigned Vd = (fieldFromInstruction_4(Insn, 12, 4) << 0);
5099 Vd |= (fieldFromInstruction_4(Insn, 22, 1) << 4);
5100 Vm = (fieldFromInstruction_4(Insn, 0, 4) << 0);
5101 Vm |= (fieldFromInstruction_4(Insn, 5, 1) << 4);
5102 imm = fieldFromInstruction_4(Insn, 16, 6);
5103 cmode = fieldFromInstruction_4(Insn, 8, 4);
5104 op = fieldFromInstruction_4(Insn, 5, 1);
5105
5106 // VMOVv2f32 is ambiguous with these decodings.
5107 if (!(imm & 0x38) && cmode == 0xF) {
5108 if (op == 1) return MCDisassembler_Fail;
5109 MCInst_setOpcode(Inst, ARM_VMOVv2f32);
5110 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder);
5111 }
5112
5113 if (!(imm & 0x20)) return MCDisassembler_Fail;
5114
5115 if (!Check(&S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
5116 return MCDisassembler_Fail;
5117 if (!Check(&S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder)))
5118 return MCDisassembler_Fail;
5119 MCOperand_CreateImm0(Inst, 64 - imm);
5120
5121 return S;
5122 }
5123
DecodeVCVTQ(MCInst * Inst,unsigned Insn,uint64_t Address,const void * Decoder)5124 static DecodeStatus DecodeVCVTQ(MCInst *Inst, unsigned Insn,
5125 uint64_t Address, const void *Decoder)
5126 {
5127 DecodeStatus S = MCDisassembler_Success;
5128 unsigned Vm, imm, cmode, op;
5129 unsigned Vd = (fieldFromInstruction_4(Insn, 12, 4) << 0);
5130 Vd |= (fieldFromInstruction_4(Insn, 22, 1) << 4);
5131 Vm = (fieldFromInstruction_4(Insn, 0, 4) << 0);
5132 Vm |= (fieldFromInstruction_4(Insn, 5, 1) << 4);
5133 imm = fieldFromInstruction_4(Insn, 16, 6);
5134 cmode = fieldFromInstruction_4(Insn, 8, 4);
5135 op = fieldFromInstruction_4(Insn, 5, 1);
5136
5137 // VMOVv4f32 is ambiguous with these decodings.
5138 if (!(imm & 0x38) && cmode == 0xF) {
5139 if (op == 1) return MCDisassembler_Fail;
5140 MCInst_setOpcode(Inst, ARM_VMOVv4f32);
5141 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder);
5142 }
5143
5144 if (!(imm & 0x20)) return MCDisassembler_Fail;
5145
5146 if (!Check(&S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder)))
5147 return MCDisassembler_Fail;
5148 if (!Check(&S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder)))
5149 return MCDisassembler_Fail;
5150 MCOperand_CreateImm0(Inst, 64 - imm);
5151
5152 return S;
5153 }
5154
DecodeLDR(MCInst * Inst,unsigned Val,uint64_t Address,const void * Decoder)5155 static DecodeStatus DecodeLDR(MCInst *Inst, unsigned Val,
5156 uint64_t Address, const void *Decoder)
5157 {
5158 DecodeStatus S = MCDisassembler_Success;
5159 unsigned Cond;
5160 unsigned Rn = fieldFromInstruction_4(Val, 16, 4);
5161 unsigned Rt = fieldFromInstruction_4(Val, 12, 4);
5162 unsigned Rm = fieldFromInstruction_4(Val, 0, 4);
5163 Rm |= (fieldFromInstruction_4(Val, 23, 1) << 4);
5164 Cond = fieldFromInstruction_4(Val, 28, 4);
5165
5166 if (fieldFromInstruction_4(Val, 8, 4) != 0 || Rn == Rt)
5167 S = MCDisassembler_SoftFail;
5168
5169 if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
5170 return MCDisassembler_Fail;
5171 if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
5172 return MCDisassembler_Fail;
5173 if (!Check(&S, DecodeAddrMode7Operand(Inst, Rn, Address, Decoder)))
5174 return MCDisassembler_Fail;
5175 if (!Check(&S, DecodePostIdxReg(Inst, Rm, Address, Decoder)))
5176 return MCDisassembler_Fail;
5177 if (!Check(&S, DecodePredicateOperand(Inst, Cond, Address, Decoder)))
5178 return MCDisassembler_Fail;
5179
5180 return S;
5181 }
5182
DecodeMRRC2(MCInst * Inst,unsigned Val,uint64_t Address,const void * Decoder)5183 static DecodeStatus DecodeMRRC2(MCInst *Inst, unsigned Val,
5184 uint64_t Address, const void *Decoder)
5185 {
5186
5187 DecodeStatus S = MCDisassembler_Success;
5188
5189 unsigned CRm = fieldFromInstruction_4(Val, 0, 4);
5190 unsigned opc1 = fieldFromInstruction_4(Val, 4, 4);
5191 unsigned cop = fieldFromInstruction_4(Val, 8, 4);
5192 unsigned Rt = fieldFromInstruction_4(Val, 12, 4);
5193 unsigned Rt2 = fieldFromInstruction_4(Val, 16, 4);
5194
5195 if ((cop & ~0x1) == 0xa)
5196 return MCDisassembler_Fail;
5197
5198 if (Rt == Rt2)
5199 S = MCDisassembler_SoftFail;
5200
5201 MCOperand_CreateImm0(Inst, cop);
5202 MCOperand_CreateImm0(Inst, opc1);
5203 if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
5204 return MCDisassembler_Fail;
5205 if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
5206 return MCDisassembler_Fail;
5207 MCOperand_CreateImm0(Inst, CRm);
5208
5209 return S;
5210 }
5211
5212 #endif
5213