1 /* Capstone Disassembler Engine */
2 /* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013 */
3
4 // This sample code demonstrates the APIs cs_malloc() & cs_disasm_iter().
5 #include <stdio.h>
6 #include <stdlib.h>
7
8 #include <capstone/platform.h>
9 #include <capstone/capstone.h>
10
11 struct platform {
12 cs_arch arch;
13 cs_mode mode;
14 unsigned char *code;
15 size_t size;
16 const char *comment;
17 cs_opt_type opt_type;
18 cs_opt_value opt_value;
19 };
20
print_string_hex(unsigned char * str,size_t len)21 static void print_string_hex(unsigned char *str, size_t len)
22 {
23 unsigned char *c;
24
25 printf("Code: ");
26 for (c = str; c < str + len; c++) {
27 printf("0x%02x ", *c & 0xff);
28 }
29 printf("\n");
30 }
31
test()32 static void test()
33 {
34 #ifdef CAPSTONE_HAS_X86
35 #define X86_CODE16 "\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00"
36 #define X86_CODE32 "\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00"
37 //#define X86_CODE32 "\x0f\xa7\xc0" // xstorerng
38 #define X86_CODE64 "\x55\x48\x8b\x05\xb8\x13\x00\x00"
39 #endif
40 #ifdef CAPSTONE_HAS_ARM
41 //#define ARM_CODE "\x04\xe0\x2d\xe5"
42 #define ARM_CODE "\xED\xFF\xFF\xEB\x04\xe0\x2d\xe5\x00\x00\x00\x00\xe0\x83\x22\xe5\xf1\x02\x03\x0e\x00\x00\xa0\xe3\x02\x30\xc1\xe7\x00\x00\x53\xe3"
43 #define ARM_CODE2 "\x10\xf1\x10\xe7\x11\xf2\x31\xe7\xdc\xa1\x2e\xf3\xe8\x4e\x62\xf3"
44 #define THUMB_CODE "\x70\x47\xeb\x46\x83\xb0\xc9\x68"
45 #define THUMB_CODE2 "\x4f\xf0\x00\x01\xbd\xe8\x00\x88\xd1\xe8\x00\xf0"
46 #endif
47 #ifdef CAPSTONE_HAS_MIPS
48 #define MIPS_CODE "\x0C\x10\x00\x97\x00\x00\x00\x00\x24\x02\x00\x0c\x8f\xa2\x00\x00\x34\x21\x34\x56\x00\x80\x04\x08"
49 //#define MIPS_CODE "\x21\x38\x00\x01"
50 //#define MIPS_CODE "\x21\x30\xe6\x70"
51 //#define MIPS_CODE "\x1c\x00\x40\x14"
52 #define MIPS_CODE2 "\x56\x34\x21\x34\xc2\x17\x01\x00"
53 #endif
54 #ifdef CAPSTONE_HAS_ARM64
55 //#define ARM64_CODE "\xe1\x0b\x40\xb9" // ldr w1, [sp, #0x8]
56 //#define ARM64_CODE "\x00\x40\x21\x4b" // sub w0, w0, w1, uxtw
57 //#define ARM64_CODE "\x21\x7c\x02\x9b" // mul x1, x1, x2
58 //#define ARM64_CODE "\x20\x74\x0b\xd5" // dc zva, x0
59 //#define ARM64_CODE "\x20\xfc\x02\x9b" // mneg x0, x1, x2
60 //#define ARM64_CODE "\x21\x7c\x02\x9b\x21\x7c\x00\x53\x00\x40\x21\x4b\xe1\x0b\x40\xb9\x10\x20\x21\x1e"
61 //#define ARM64_CODE "\x21\x7c\x00\x53"
62 #define ARM64_CODE "\x09\x00\x38\xd5\xbf\x40\x00\xd5\x0c\x05\x13\xd5\x20\x50\x02\x0e\x20\xe4\x3d\x0f\x00\x18\xa0\x5f\xa2\x00\xae\x9e\x9f\x37\x03\xd5\xbf\x33\x03\xd5\xdf\x3f\x03\xd5\x21\x7c\x02\x9b\x21\x7c\x00\x53\x00\x40\x21\x4b\xe1\x0b\x40\xb9\x20\x04\x81\xda\x20\x08\x02\x8b\x10\x5b\xe8\x3c"
63 #endif
64 //#define THUMB_CODE "\x0a\xbf" // itet eq
65 //#define X86_CODE32 "\x77\x04" // ja +6
66 #ifdef CAPSTONE_HAS_PPC
67 #define PPC_CODE "\x80\x20\x00\x00\x80\x3f\x00\x00\x10\x43\x23\x0e\xd0\x44\x00\x80\x4c\x43\x22\x02\x2d\x03\x00\x80\x7c\x43\x20\x14\x7c\x43\x20\x93\x4f\x20\x00\x21\x4c\xc8\x00\x21\x40\x82\x00\x14"
68 #endif
69 #ifdef CAPSTONE_HAS_SPARC
70 #define SPARC_CODE "\x80\xa0\x40\x02\x85\xc2\x60\x08\x85\xe8\x20\x01\x81\xe8\x00\x00\x90\x10\x20\x01\xd5\xf6\x10\x16\x21\x00\x00\x0a\x86\x00\x40\x02\x01\x00\x00\x00\x12\xbf\xff\xff\x10\xbf\xff\xff\xa0\x02\x00\x09\x0d\xbf\xff\xff\xd4\x20\x60\x00\xd4\x4e\x00\x16\x2a\xc2\x80\x03"
71 #define SPARCV9_CODE "\x81\xa8\x0a\x24\x89\xa0\x10\x20\x89\xa0\x1a\x60\x89\xa0\x00\xe0"
72 #endif
73 #ifdef CAPSTONE_HAS_SYSZ
74 #define SYSZ_CODE "\xed\x00\x00\x00\x00\x1a\x5a\x0f\x1f\xff\xc2\x09\x80\x00\x00\x00\x07\xf7\xeb\x2a\xff\xff\x7f\x57\xe3\x01\xff\xff\x7f\x57\xeb\x00\xf0\x00\x00\x24\xb2\x4f\x00\x78"
75 #endif
76 #ifdef CAPSTONE_HAS_XCORE
77 #define XCORE_CODE "\xfe\x0f\xfe\x17\x13\x17\xc6\xfe\xec\x17\x97\xf8\xec\x4f\x1f\xfd\xec\x37\x07\xf2\x45\x5b\xf9\xfa\x02\x06\x1b\x10"
78 #endif
79 #ifdef CAPSTONE_HAS_M680X
80 #define M680X_CODE "\x06\x10\x19\x1a\x55\x1e\x01\x23\xe9\x31\x06\x34\x55\xa6\x81\xa7\x89\x7f\xff\xa6\x9d\x10\x00\xa7\x91\xa6\x9f\x10\x00\x11\xac\x99\x10\x00\x39"
81 #endif
82
83 struct platform platforms[] = {
84 #ifdef CAPSTONE_HAS_X86
85 {
86 CS_ARCH_X86,
87 CS_MODE_16,
88 (unsigned char *)X86_CODE16,
89 sizeof(X86_CODE32) - 1,
90 "X86 16bit (Intel syntax)"
91 },
92 {
93 CS_ARCH_X86,
94 CS_MODE_32,
95 (unsigned char *)X86_CODE32,
96 sizeof(X86_CODE32) - 1,
97 "X86 32bit (ATT syntax)",
98 CS_OPT_SYNTAX,
99 CS_OPT_SYNTAX_ATT,
100 },
101 {
102 CS_ARCH_X86,
103 CS_MODE_32,
104 (unsigned char *)X86_CODE32,
105 sizeof(X86_CODE32) - 1,
106 "X86 32 (Intel syntax)"
107 },
108 {
109 CS_ARCH_X86,
110 CS_MODE_64,
111 (unsigned char *)X86_CODE64,
112 sizeof(X86_CODE64) - 1,
113 "X86 64 (Intel syntax)"
114 },
115 #endif
116 #ifdef CAPSTONE_HAS_ARM
117 {
118 CS_ARCH_ARM,
119 CS_MODE_ARM,
120 (unsigned char *)ARM_CODE,
121 sizeof(ARM_CODE) - 1,
122 "ARM"
123 },
124 {
125 CS_ARCH_ARM,
126 CS_MODE_THUMB,
127 (unsigned char *)THUMB_CODE2,
128 sizeof(THUMB_CODE2) - 1,
129 "THUMB-2"
130 },
131 {
132 CS_ARCH_ARM,
133 CS_MODE_ARM,
134 (unsigned char *)ARM_CODE2,
135 sizeof(ARM_CODE2) - 1,
136 "ARM: Cortex-A15 + NEON"
137 },
138 {
139 CS_ARCH_ARM,
140 CS_MODE_THUMB,
141 (unsigned char *)THUMB_CODE,
142 sizeof(THUMB_CODE) - 1,
143 "THUMB"
144 },
145 #endif
146 #ifdef CAPSTONE_HAS_MIPS
147 {
148 CS_ARCH_MIPS,
149 (cs_mode)(CS_MODE_MIPS32 + CS_MODE_BIG_ENDIAN),
150 (unsigned char *)MIPS_CODE,
151 sizeof(MIPS_CODE) - 1,
152 "MIPS-32 (Big-endian)"
153 },
154 {
155 CS_ARCH_MIPS,
156 (cs_mode)(CS_MODE_MIPS64 + CS_MODE_LITTLE_ENDIAN),
157 (unsigned char *)MIPS_CODE2,
158 sizeof(MIPS_CODE2) - 1,
159 "MIPS-64-EL (Little-endian)"
160 },
161 #endif
162 #ifdef CAPSTONE_HAS_ARM64
163 {
164 CS_ARCH_ARM64,
165 CS_MODE_ARM,
166 (unsigned char *)ARM64_CODE,
167 sizeof(ARM64_CODE) - 1,
168 "ARM-64"
169 },
170 #endif
171 #ifdef CAPSTONE_HAS_PPC
172 {
173 CS_ARCH_PPC,
174 CS_MODE_BIG_ENDIAN,
175 (unsigned char*)PPC_CODE,
176 sizeof(PPC_CODE) - 1,
177 "PPC-64"
178 },
179 #endif
180 #ifdef CAPSTONE_HAS_SPARC
181 {
182 CS_ARCH_SPARC,
183 CS_MODE_BIG_ENDIAN,
184 (unsigned char*)SPARC_CODE,
185 sizeof(SPARC_CODE) - 1,
186 "Sparc"
187 },
188 {
189 CS_ARCH_SPARC,
190 (cs_mode)(CS_MODE_BIG_ENDIAN + CS_MODE_V9),
191 (unsigned char*)SPARCV9_CODE,
192 sizeof(SPARCV9_CODE) - 1,
193 "SparcV9"
194 },
195 #endif
196 #ifdef CAPSTONE_HAS_SYSZ
197 {
198 CS_ARCH_SYSZ,
199 (cs_mode)0,
200 (unsigned char*)SYSZ_CODE,
201 sizeof(SYSZ_CODE) - 1,
202 "SystemZ"
203 },
204 #endif
205 #ifdef CAPSTONE_HAS_XCORE
206 {
207 CS_ARCH_XCORE,
208 (cs_mode)0,
209 (unsigned char*)XCORE_CODE,
210 sizeof(XCORE_CODE) - 1,
211 "XCore"
212 },
213 #endif
214 #ifdef CAPSTONE_HAS_M680X
215 {
216 CS_ARCH_M680X,
217 (cs_mode)CS_MODE_M680X_6809,
218 (unsigned char*)M680X_CODE,
219 sizeof(M680X_CODE) - 1,
220 "M680X_6809"
221 },
222 #endif
223 };
224
225 csh handle;
226 uint64_t address;
227 cs_insn *insn;
228 cs_detail *detail;
229 int i;
230 cs_err err;
231 const uint8_t *code;
232 size_t size;
233
234 for (i = 0; i < sizeof(platforms)/sizeof(platforms[0]); i++) {
235 printf("****************\n");
236 printf("Platform: %s\n", platforms[i].comment);
237 err = cs_open(platforms[i].arch, platforms[i].mode, &handle);
238 if (err) {
239 printf("Failed on cs_open() with error returned: %u\n", err);
240 abort();
241 }
242
243 if (platforms[i].opt_type)
244 cs_option(handle, platforms[i].opt_type, platforms[i].opt_value);
245
246 cs_option(handle, CS_OPT_DETAIL, CS_OPT_ON);
247
248 // allocate memory for the cache to be used by cs_disasm_iter()
249 insn = cs_malloc(handle);
250
251 print_string_hex(platforms[i].code, platforms[i].size);
252 printf("Disasm:\n");
253
254 address = 0x1000;
255 code = platforms[i].code;
256 size = platforms[i].size;
257 while(cs_disasm_iter(handle, &code, &size, &address, insn)) {
258 int n;
259
260 printf("0x%" PRIx64 ":\t%s\t\t%s // insn-ID: %u, insn-mnem: %s\n",
261 insn->address, insn->mnemonic, insn->op_str,
262 insn->id, cs_insn_name(handle, insn->id));
263
264 // print implicit registers used by this instruction
265 detail = insn->detail;
266
267 if (detail->regs_read_count > 0) {
268 printf("\tImplicit registers read: ");
269 for (n = 0; n < detail->regs_read_count; n++) {
270 printf("%s ", cs_reg_name(handle, detail->regs_read[n]));
271 }
272 printf("\n");
273 }
274
275 // print implicit registers modified by this instruction
276 if (detail->regs_write_count > 0) {
277 printf("\tImplicit registers modified: ");
278 for (n = 0; n < detail->regs_write_count; n++) {
279 printf("%s ", cs_reg_name(handle, detail->regs_write[n]));
280 }
281 printf("\n");
282 }
283
284 // print the groups this instruction belong to
285 if (detail->groups_count > 0) {
286 printf("\tThis instruction belongs to groups: ");
287 for (n = 0; n < detail->groups_count; n++) {
288 printf("%s ", cs_group_name(handle, detail->groups[n]));
289 }
290 printf("\n");
291 }
292 }
293
294 printf("\n");
295
296 // free memory allocated by cs_malloc()
297 cs_free(insn, 1);
298
299 cs_close(&handle);
300 }
301 }
302
main()303 int main()
304 {
305 test();
306
307 return 0;
308 }
309