1;; Scheduling description for Motorola PowerPC 750 and PowerPC 7400 processors. 2;; Copyright (C) 2003-2018 Free Software Foundation, Inc. 3;; 4;; This file is part of GCC. 5 6;; GCC is free software; you can redistribute it and/or modify it 7;; under the terms of the GNU General Public License as published 8;; by the Free Software Foundation; either version 3, or (at your 9;; option) any later version. 10 11;; GCC is distributed in the hope that it will be useful, but WITHOUT 12;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 13;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 14;; License for more details. 15 16;; You should have received a copy of the GNU General Public License 17;; along with GCC; see the file COPYING3. If not see 18;; <http://www.gnu.org/licenses/>. 19 20(define_automaton "ppc7xx,ppc7xxfp") 21(define_cpu_unit "iu1_7xx,iu2_7xx" "ppc7xx") 22(define_cpu_unit "fpu_7xx" "ppc7xxfp") 23(define_cpu_unit "lsu_7xx,bpu_7xx,sru_7xx" "ppc7xx") 24(define_cpu_unit "du1_7xx,du2_7xx" "ppc7xx") 25(define_cpu_unit "veccmplx_7xx,vecperm_7xx,vdu_7xx" "ppc7xx") 26 27;; PPC740/PPC750/PPC7400 32-bit 2xIU, LSU, SRU, FPU, BPU 28;; IU1 can perform all integer operations 29;; IU2 can perform all integer operations except imul and idiv 30;; LSU 2 stage pipelined 31;; FPU 3 stage pipelined 32;; Max issue 3 insns/clock cycle (includes 1 branch) 33;; In-order execution 34 35 36;; The PPC750 user's manual recommends that to reduce branch mispredictions, 37;; the insn that sets CR bits should be separated from the branch insn 38;; that evaluates them. There is no advantage have more than 10 cycles 39;; of separation. 40;; This could be artificially achieved by exaggerating the latency of 41;; compare insns but at the expense of a poorer schedule. 42 43;; Branches go straight to the BPU. All other insns are handled 44;; by a dispatch unit which can issue a max of 2 insns per cycle. 45(define_reservation "ppc750_du" "du1_7xx|du2_7xx") 46(define_reservation "ppc7400_vec_du" "vdu_7xx") 47 48(define_insn_reservation "ppc750-load" 2 49 (and (eq_attr "type" "load,fpload,vecload,load_l") 50 (eq_attr "cpu" "ppc750,ppc7400")) 51 "ppc750_du,lsu_7xx") 52 53(define_insn_reservation "ppc750-store" 2 54 (and (eq_attr "type" "store,fpstore,vecstore") 55 (eq_attr "cpu" "ppc750,ppc7400")) 56 "ppc750_du,lsu_7xx") 57 58(define_insn_reservation "ppc750-storec" 8 59 (and (eq_attr "type" "store_c") 60 (eq_attr "cpu" "ppc750,ppc7400")) 61 "ppc750_du,lsu_7xx") 62 63(define_insn_reservation "ppc750-integer" 1 64 (and (ior (eq_attr "type" "integer,insert,trap,cntlz,isel") 65 (and (eq_attr "type" "add,logical,shift,exts") 66 (eq_attr "dot" "no"))) 67 (eq_attr "cpu" "ppc750,ppc7400")) 68 "ppc750_du,iu1_7xx|iu2_7xx") 69 70(define_insn_reservation "ppc750-two" 1 71 (and (eq_attr "type" "two") 72 (eq_attr "cpu" "ppc750,ppc7400")) 73 "ppc750_du,iu1_7xx|iu2_7xx,iu1_7xx|iu2_7xx") 74 75(define_insn_reservation "ppc750-three" 1 76 (and (eq_attr "type" "three") 77 (eq_attr "cpu" "ppc750,ppc7400")) 78 "ppc750_du,iu1_7xx|iu2_7xx,iu1_7xx|iu2_7xx,iu1_7xx|iu2_7xx") 79 80(define_insn_reservation "ppc750-imul" 4 81 (and (eq_attr "type" "mul") 82 (eq_attr "size" "32") 83 (eq_attr "cpu" "ppc750,ppc7400")) 84 "ppc750_du,iu1_7xx*4") 85 86(define_insn_reservation "ppc750-imul2" 3 87 (and (eq_attr "type" "mul") 88 (eq_attr "size" "16") 89 (eq_attr "cpu" "ppc750,ppc7400")) 90 "ppc750_du,iu1_7xx*2") 91 92(define_insn_reservation "ppc750-imul3" 2 93 (and (eq_attr "type" "mul") 94 (eq_attr "size" "8") 95 (eq_attr "cpu" "ppc750,ppc7400")) 96 "ppc750_du,iu1_7xx") 97 98(define_insn_reservation "ppc750-idiv" 19 99 (and (eq_attr "type" "div") 100 (eq_attr "cpu" "ppc750,ppc7400")) 101 "ppc750_du,iu1_7xx*19") 102 103(define_insn_reservation "ppc750-compare" 2 104 (and (ior (eq_attr "type" "cmp") 105 (and (eq_attr "type" "add,logical,shift,exts") 106 (eq_attr "dot" "yes"))) 107 (eq_attr "cpu" "ppc750,ppc7400")) 108 "ppc750_du,(iu1_7xx|iu2_7xx)") 109 110(define_insn_reservation "ppc750-fpcompare" 2 111 (and (eq_attr "type" "fpcompare") 112 (eq_attr "cpu" "ppc750,ppc7400")) 113 "ppc750_du,fpu_7xx") 114 115(define_insn_reservation "ppc750-fp" 3 116 (and (eq_attr "type" "fp,fpsimple") 117 (eq_attr "cpu" "ppc750,ppc7400")) 118 "ppc750_du,fpu_7xx") 119 120(define_insn_reservation "ppc750-dmul" 4 121 (and (eq_attr "type" "dmul") 122 (eq_attr "cpu" "ppc750")) 123 "ppc750_du,fpu_7xx*2") 124 125(define_insn_reservation "ppc7400-dmul" 3 126 (and (eq_attr "type" "dmul") 127 (eq_attr "cpu" "ppc7400")) 128 "ppc750_du,fpu_7xx") 129 130; Divides are not pipelined 131(define_insn_reservation "ppc750-sdiv" 17 132 (and (eq_attr "type" "sdiv") 133 (eq_attr "cpu" "ppc750,ppc7400")) 134 "ppc750_du,fpu_7xx*17") 135 136(define_insn_reservation "ppc750-ddiv" 31 137 (and (eq_attr "type" "ddiv") 138 (eq_attr "cpu" "ppc750,ppc7400")) 139 "ppc750_du,fpu_7xx*31") 140 141(define_insn_reservation "ppc750-mfcr" 2 142 (and (eq_attr "type" "mfcr,mtcr") 143 (eq_attr "cpu" "ppc750,ppc7400")) 144 "ppc750_du,iu1_7xx") 145 146(define_insn_reservation "ppc750-crlogical" 3 147 (and (eq_attr "type" "cr_logical,delayed_cr") 148 (eq_attr "cpu" "ppc750,ppc7400")) 149 "nothing,sru_7xx*2") 150 151(define_insn_reservation "ppc750-mtjmpr" 2 152 (and (eq_attr "type" "mtjmpr,isync,sync") 153 (eq_attr "cpu" "ppc750,ppc7400")) 154 "nothing,sru_7xx*2") 155 156(define_insn_reservation "ppc750-mfjmpr" 3 157 (and (eq_attr "type" "mfjmpr") 158 (eq_attr "cpu" "ppc750,ppc7400")) 159 "nothing,sru_7xx*2") 160 161(define_insn_reservation "ppc750-jmpreg" 1 162 (and (eq_attr "type" "jmpreg,branch,isync") 163 (eq_attr "cpu" "ppc750,ppc7400")) 164 "nothing,bpu_7xx") 165 166;; Altivec 167(define_insn_reservation "ppc7400-vecsimple" 1 168 (and (eq_attr "type" "vecsimple,veclogical,vecmove,veccmp,veccmpfx") 169 (eq_attr "cpu" "ppc7400")) 170 "ppc750_du,ppc7400_vec_du,veccmplx_7xx") 171 172(define_insn_reservation "ppc7400-veccomplex" 4 173 (and (eq_attr "type" "veccomplex") 174 (eq_attr "cpu" "ppc7400")) 175 "ppc750_du,ppc7400_vec_du,veccmplx_7xx") 176 177(define_insn_reservation "ppc7400-vecfloat" 4 178 (and (eq_attr "type" "vecfloat") 179 (eq_attr "cpu" "ppc7400")) 180 "ppc750_du,ppc7400_vec_du,veccmplx_7xx") 181 182(define_insn_reservation "ppc7400-vecperm" 2 183 (and (eq_attr "type" "vecperm") 184 (eq_attr "cpu" "ppc7400")) 185 "ppc750_du,ppc7400_vec_du,vecperm_7xx") 186 187