1;; GCC machine description for SPARC synchronization instructions. 2;; Copyright (C) 2005-2018 Free Software Foundation, Inc. 3;; 4;; This file is part of GCC. 5;; 6;; GCC is free software; you can redistribute it and/or modify 7;; it under the terms of the GNU General Public License as published by 8;; the Free Software Foundation; either version 3, or (at your option) 9;; any later version. 10;; 11;; GCC is distributed in the hope that it will be useful, 12;; but WITHOUT ANY WARRANTY; without even the implied warranty of 13;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14;; GNU General Public License for more details. 15;; 16;; You should have received a copy of the GNU General Public License 17;; along with GCC; see the file COPYING3. If not see 18;; <http://www.gnu.org/licenses/>. 19 20(define_mode_iterator I12MODE [QI HI]) 21(define_mode_iterator I124MODE [QI HI SI]) 22(define_mode_iterator I24MODE [HI SI]) 23(define_mode_iterator I48MODE [SI (DI "TARGET_ARCH64 || TARGET_V8PLUS")]) 24(define_mode_attr modesuffix [(SI "") (DI "x")]) 25 26(define_expand "mem_thread_fence" 27 [(match_operand:SI 0 "const_int_operand")] 28 "TARGET_V8 || TARGET_V9" 29{ 30 enum memmodel model = (enum memmodel) INTVAL (operands[0]); 31 sparc_emit_membar_for_model (model, 3, 3); 32 DONE; 33}) 34 35(define_expand "membar" 36 [(set (match_dup 1) 37 (unspec:BLK [(match_dup 1) (match_operand:SI 0 "const_int_operand")] 38 UNSPEC_MEMBAR))] 39 "TARGET_V8 || TARGET_V9" 40{ 41 operands[1] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode)); 42 MEM_VOLATILE_P (operands[1]) = 1; 43}) 44 45;; A compiler-only memory barrier. Generic code, when checking for the 46;; existence of various named patterns, uses asm("":::"memory") when we 47;; don't need an actual instruction. Here, it's easiest to pretend that 48;; membar 0 is such a barrier. Further, this gives us a nice hook to 49;; ignore all such barriers on Sparc V7. 50(define_insn "*membar_empty" 51 [(set (match_operand:BLK 0 "" "") 52 (unspec:BLK [(match_dup 0) (match_operand:SI 1 "zero_or_v7_operand")] 53 UNSPEC_MEMBAR))] 54 "" 55 "" 56 [(set_attr "type" "multi") 57 (set_attr "length" "0")]) 58 59;; For V8, STBAR is exactly membar #StoreStore, by definition. 60(define_insn "*membar_storestore" 61 [(set (match_operand:BLK 0 "" "") 62 (unspec:BLK [(match_dup 0) (const_int 8)] UNSPEC_MEMBAR))] 63 "TARGET_V8" 64 "stbar" 65 [(set_attr "type" "multi")]) 66 67;; For LEON3, STB has the effect of membar #StoreLoad. 68(define_insn "*membar_storeload_leon3" 69 [(set (match_operand:BLK 0 "" "") 70 (unspec:BLK [(match_dup 0) (const_int 2)] UNSPEC_MEMBAR))] 71 "TARGET_LEON3" 72 "stb\t%%g0, [%%sp-1]" 73 [(set_attr "type" "store")]) 74 75;; For V8, LDSTUB has the effect of membar #StoreLoad. 76(define_insn "*membar_storeload" 77 [(set (match_operand:BLK 0 "" "") 78 (unspec:BLK [(match_dup 0) (const_int 2)] UNSPEC_MEMBAR))] 79 "TARGET_V8 && !TARGET_LEON3" 80 "ldstub\t[%%sp-1], %%g0" 81 [(set_attr "type" "multi")]) 82 83;; Put the two together, in combination with the fact that V8 implements PSO 84;; as its weakest memory model, means a full barrier. Match all remaining 85;; instances of the membar pattern for Sparc V8. 86(define_insn "*membar_v8" 87 [(set (match_operand:BLK 0 "" "") 88 (unspec:BLK [(match_dup 0) (match_operand:SI 1 "const_int_operand")] 89 UNSPEC_MEMBAR))] 90 "TARGET_V8" 91 "stbar\n\tldstub\t[%%sp-1], %%g0" 92 [(set_attr "type" "multi") 93 (set_attr "length" "2")]) 94 95;; For V9, we have the full membar instruction. 96(define_insn "*membar" 97 [(set (match_operand:BLK 0 "" "") 98 (unspec:BLK [(match_dup 0) (match_operand:SI 1 "const_int_operand")] 99 UNSPEC_MEMBAR))] 100 "TARGET_V9" 101 "membar\t%1" 102 [(set_attr "type" "multi")]) 103 104(define_peephole2 105 [(set (match_operand:BLK 0 "" "") 106 (unspec:BLK [(match_dup 0) (match_operand:SI 1 "const_int_operand")] 107 UNSPEC_MEMBAR)) 108 (set (match_operand:BLK 2 "" "") 109 (unspec:BLK [(match_dup 2) (match_operand:SI 3 "const_int_operand")] 110 UNSPEC_MEMBAR))] 111 "" 112 [(set (match_operand:BLK 0 "" "") 113 (unspec:BLK [(match_dup 0) (match_dup 1)] UNSPEC_MEMBAR))] 114{ operands[1] = GEN_INT (UINTVAL (operands[1]) | UINTVAL (operands[3])); }) 115 116(define_expand "atomic_load<mode>" 117 [(match_operand:I 0 "register_operand" "") 118 (match_operand:I 1 "memory_operand" "") 119 (match_operand:SI 2 "const_int_operand" "")] 120 "" 121{ 122 enum memmodel model = (enum memmodel) INTVAL (operands[2]); 123 124 sparc_emit_membar_for_model (model, 1, 1); 125 126 if (TARGET_ARCH64 || <MODE>mode != DImode) 127 emit_move_insn (operands[0], operands[1]); 128 else 129 emit_insn (gen_atomic_loaddi_1 (operands[0], operands[1])); 130 131 sparc_emit_membar_for_model (model, 1, 2); 132 DONE; 133}) 134 135(define_insn "atomic_loaddi_1" 136 [(set (match_operand:DI 0 "register_operand" "=r,?*f") 137 (unspec:DI [(match_operand:DI 1 "memory_operand" "T,T")] 138 UNSPEC_ATOMIC))] 139 "TARGET_ARCH32" 140 "ldd\t%1, %0" 141 [(set_attr "type" "load,fpload")]) 142 143(define_expand "atomic_store<mode>" 144 [(match_operand:I 0 "memory_operand" "") 145 (match_operand:I 1 "register_operand" "") 146 (match_operand:SI 2 "const_int_operand" "")] 147 "" 148{ 149 enum memmodel model = (enum memmodel) INTVAL (operands[2]); 150 151 sparc_emit_membar_for_model (model, 2, 1); 152 153 if (TARGET_ARCH64 || <MODE>mode != DImode) 154 emit_move_insn (operands[0], operands[1]); 155 else 156 emit_insn (gen_atomic_storedi_1 (operands[0], operands[1])); 157 158 sparc_emit_membar_for_model (model, 2, 2); 159 DONE; 160}) 161 162(define_insn "atomic_storedi_1" 163 [(set (match_operand:DI 0 "memory_operand" "=T,T,T") 164 (unspec:DI 165 [(match_operand:DI 1 "register_or_v9_zero_operand" "J,r,?*f")] 166 UNSPEC_ATOMIC))] 167 "TARGET_ARCH32" 168 "@ 169 stx\t%r1, %0 170 std\t%1, %0 171 std\t%1, %0" 172 [(set_attr "type" "store,store,fpstore") 173 (set_attr "cpu_feature" "v9,*,*")]) 174 175(define_expand "atomic_compare_and_swap<mode>" 176 [(match_operand:SI 0 "register_operand" "") ;; bool output 177 (match_operand:I 1 "register_operand" "") ;; val output 178 (match_operand:I 2 "mem_noofs_operand" "") ;; memory 179 (match_operand:I 3 "register_operand" "") ;; expected 180 (match_operand:I 4 "register_operand" "") ;; desired 181 (match_operand:SI 5 "const_int_operand" "") ;; is_weak 182 (match_operand:SI 6 "const_int_operand" "") ;; mod_s 183 (match_operand:SI 7 "const_int_operand" "")] ;; mod_f 184 "(TARGET_V9 || TARGET_LEON3) 185 && (<MODE>mode != DImode || TARGET_ARCH64 || TARGET_V8PLUS)" 186{ 187 sparc_expand_compare_and_swap (operands); 188 DONE; 189}) 190 191(define_expand "atomic_compare_and_swap<mode>_1" 192 [(parallel 193 [(set (match_operand:I48MODE 0 "register_operand" "") 194 (match_operand:I48MODE 1 "mem_noofs_operand" "")) 195 (set (match_dup 1) 196 (unspec_volatile:I48MODE 197 [(match_operand:I48MODE 2 "register_operand" "") 198 (match_operand:I48MODE 3 "register_operand" "")] 199 UNSPECV_CAS))])] 200 "TARGET_V9 || TARGET_LEON3" 201 "") 202 203(define_insn "*atomic_compare_and_swap<mode>_1" 204 [(set (match_operand:I48MODE 0 "register_operand" "=r") 205 (match_operand:I48MODE 1 "mem_noofs_operand" "+w")) 206 (set (match_dup 1) 207 (unspec_volatile:I48MODE 208 [(match_operand:I48MODE 2 "register_operand" "r") 209 (match_operand:I48MODE 3 "register_operand" "0")] 210 UNSPECV_CAS))] 211 "TARGET_V9 && (<MODE>mode != DImode || TARGET_ARCH64)" 212 "cas<modesuffix>\t%1, %2, %0" 213 [(set_attr "type" "multi")]) 214 215(define_insn "atomic_compare_and_swap_leon3_1" 216 [(set (match_operand:SI 0 "register_operand" "=r") 217 (match_operand:SI 1 "mem_noofs_operand" "+w")) 218 (set (match_dup 1) 219 (unspec_volatile:SI 220 [(match_operand:SI 2 "register_operand" "r") 221 (match_operand:SI 3 "register_operand" "0")] 222 UNSPECV_CAS))] 223 "TARGET_LEON3" 224{ 225 if (sparc_fix_gr712rc) 226 output_asm_insn (".align\t16", operands); 227 if (TARGET_SV_MODE) 228 return "casa\t%1 0xb, %2, %0"; /* ASI for supervisor data space. */ 229 else 230 return "casa\t%1 0xa, %2, %0"; /* ASI for user data space. */ 231} 232 [(set_attr "type" "multi") 233 (set (attr "length") (if_then_else (eq_attr "fix_gr712rc" "true") 234 (const_int 4) (const_int 1)))]) 235 236(define_insn "*atomic_compare_and_swapdi_v8plus" 237 [(set (match_operand:DI 0 "register_operand" "=h") 238 (match_operand:DI 1 "mem_noofs_operand" "+w")) 239 (set (match_dup 1) 240 (unspec_volatile:DI 241 [(match_operand:DI 2 "register_operand" "h") 242 (match_operand:DI 3 "register_operand" "0")] 243 UNSPECV_CAS))] 244 "TARGET_V8PLUS" 245{ 246 if (sparc_check_64 (operands[3], insn) <= 0) 247 output_asm_insn ("srl\t%L3, 0, %L3", operands); 248 output_asm_insn ("sllx\t%H3, 32, %H3", operands); 249 output_asm_insn ("or\t%L3, %H3, %L3", operands); 250 if (sparc_check_64 (operands[2], insn) <= 0) 251 output_asm_insn ("srl\t%L2, 0, %L2", operands); 252 output_asm_insn ("sllx\t%H2, 32, %H3", operands); 253 output_asm_insn ("or\t%L2, %H3, %H3", operands); 254 output_asm_insn ("casx\t%1, %H3, %L3", operands); 255 return "srlx\t%L3, 32, %H3"; 256} 257 [(set_attr "type" "multi") 258 (set_attr "length" "8")]) 259 260(define_expand "atomic_exchangesi" 261 [(match_operand:SI 0 "register_operand" "") 262 (match_operand:SI 1 "memory_operand" "") 263 (match_operand:SI 2 "register_operand" "") 264 (match_operand:SI 3 "const_int_operand" "")] 265 "(TARGET_V8 || TARGET_V9) && !sparc_fix_ut699" 266{ 267 enum memmodel model = (enum memmodel) INTVAL (operands[3]); 268 269 sparc_emit_membar_for_model (model, 3, 1); 270 emit_insn (gen_swapsi (operands[0], operands[1], operands[2])); 271 sparc_emit_membar_for_model (model, 3, 2); 272 DONE; 273}) 274 275(define_insn "swapsi" 276 [(set (match_operand:SI 0 "register_operand" "=r") 277 (unspec_volatile:SI [(match_operand:SI 1 "memory_operand" "+m")] 278 UNSPECV_SWAP)) 279 (set (match_dup 1) 280 (match_operand:SI 2 "register_operand" "0"))] 281 "(TARGET_V8 || TARGET_V9) && !sparc_fix_ut699" 282{ 283 if (sparc_fix_gr712rc) 284 return ".align\t16\n\tswap\t%1, %0"; 285 else 286 return "swap\t%1, %0"; 287} 288 [(set_attr "type" "multi") 289 (set (attr "length") (if_then_else (eq_attr "fix_gr712rc" "true") 290 (const_int 4) (const_int 1)))]) 291 292(define_expand "atomic_test_and_set" 293 [(match_operand:QI 0 "register_operand" "") 294 (match_operand:QI 1 "memory_operand" "") 295 (match_operand:SI 2 "const_int_operand" "")] 296 "!sparc_fix_ut699" 297{ 298 enum memmodel model = (enum memmodel) INTVAL (operands[2]); 299 rtx ret; 300 301 sparc_emit_membar_for_model (model, 3, 1); 302 emit_insn (gen_ldstub (operands[0], operands[1])); 303 sparc_emit_membar_for_model (model, 3, 2); 304 305 /* Convert the 0/0xff result we would otherwise have to a boolean. 306 I.e. ignore all but bit 0. */ 307 ret = expand_simple_binop (QImode, AND, operands[0], const1_rtx, 308 operands[0], true, OPTAB_LIB_WIDEN); 309 if (ret != operands[0]) 310 emit_move_insn (operands[0], ret); 311 312 DONE; 313}) 314 315(define_insn "ldstub" 316 [(set (match_operand:QI 0 "register_operand" "=r") 317 (unspec_volatile:QI [(match_operand:QI 1 "memory_operand" "+m")] 318 UNSPECV_LDSTUB)) 319 (set (match_dup 1) (const_int -1))] 320 "!sparc_fix_ut699" 321{ 322 if (sparc_fix_gr712rc) 323 return ".align\t16\n\tldstub\t%1, %0"; 324 else 325 return "ldstub\t%1, %0"; 326} 327 [(set_attr "type" "multi") 328 (set (attr "length") (if_then_else (eq_attr "fix_gr712rc" "true") 329 (const_int 4) (const_int 1)))]) 330