1 /* This file tests an intrinsic which currently has only an f16 variant and that 2 is only available when FP16 arithmetic instructions are supported. */ 3 /* { dg-require-effective-target arm_v8_2a_fp16_neon_hw } */ 4 5 #include <arm_neon.h> 6 #include "arm-neon-ref.h" 7 #include "compute-ref-data.h" 8 9 #define INSN_NAME vminnm 10 #define TEST_MSG "VMINNM/VMINMQ" 11 12 #if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) 13 #define HAS_FLOAT16_VARIANT 14 #endif 15 16 /* Expected results. */ 17 #if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) 18 VECT_VAR_DECL(expected, hfloat, 16, 4) [] = { 0xcc00, 0xcbc0, 0xcbc0, 0xcbc0 }; 19 VECT_VAR_DECL(expected, hfloat, 16, 8) [] = { 0xcc00, 0xcb80, 0xcb40, 0xcb40, 20 0xcb40, 0xcb40, 0xcb40, 0xcb40 }; 21 #endif 22 23 /* Expected results with special FP values. */ 24 #if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) 25 VECT_VAR_DECL(expected_nan, hfloat, 16, 8) [] = { 0x3c00, 0x3c00, 26 0x3c00, 0x3c00, 27 0x3c00, 0x3c00, 28 0x3c00, 0x3c00 }; 29 VECT_VAR_DECL(expected_mnan, hfloat, 16, 8) [] = { 0x3c00, 0x3c00, 30 0x3c00, 0x3c00, 31 0x3c00, 0x3c00, 32 0x3c00, 0x3c00 }; 33 VECT_VAR_DECL(expected_inf, hfloat, 16, 8) [] = { 0x3c00, 0x3c00, 34 0x3c00, 0x3c00, 35 0x3c00, 0x3c00, 36 0x3c00, 0x3c00 }; 37 VECT_VAR_DECL(expected_minf, hfloat, 16, 8) [] = { 0xfc00, 0xfc00, 38 0xfc00, 0xfc00, 39 0xfc00, 0xfc00, 40 0xfc00, 0xfc00 }; 41 VECT_VAR_DECL(expected_zero1, hfloat, 16, 8) [] = { 0x8000, 0x8000, 42 0x8000, 0x8000, 43 0x8000, 0x8000, 44 0x8000, 0x8000 }; 45 VECT_VAR_DECL(expected_zero2, hfloat, 16, 8) [] = { 0x8000, 0x8000, 46 0x8000, 0x8000, 47 0x8000, 0x8000, 48 0x8000, 0x8000 }; 49 #endif 50 51 #include "binary_op_float.inc" 52