1 /* Definitions of target machine for GNU compiler, Argonaut EPIPHANY cpu. 2 Copyright (C) 1994-2018 Free Software Foundation, Inc. 3 Contributed by Embecosm on behalf of Adapteva, Inc. 4 5 This file is part of GCC. 6 7 GCC is free software; you can redistribute it and/or modify 8 it under the terms of the GNU General Public License as published by 9 the Free Software Foundation; either version 3, or (at your option) 10 any later version. 11 12 GCC is distributed in the hope that it will be useful, 13 but WITHOUT ANY WARRANTY; without even the implied warranty of 14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 GNU General Public License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with GCC; see the file COPYING3. If not see 19 <http://www.gnu.org/licenses/>. */ 20 21 #ifndef GCC_EPIPHANY_H 22 #define GCC_EPIPHANY_H 23 24 #undef LINK_SPEC 25 #undef STARTFILE_SPEC 26 #undef ENDFILE_SPEC 27 #undef SIZE_TYPE 28 #undef PTRDIFF_TYPE 29 #undef WCHAR_TYPE 30 #undef WCHAR_TYPE_SIZE 31 32 /* Names to predefine in the preprocessor for this target machine. */ 33 #define TARGET_CPU_CPP_BUILTINS() \ 34 do \ 35 { \ 36 builtin_define ("__epiphany__"); \ 37 builtin_define ("__little_endian__"); \ 38 builtin_define_with_int_value ("__EPIPHANY_STACK_OFFSET__", \ 39 epiphany_stack_offset); \ 40 builtin_assert ("cpu=epiphany"); \ 41 builtin_assert ("machine=epiphany"); \ 42 } while (0) 43 44 /* Pick up the libgloss library. One day we may do this by linker script, but 45 for now its static. 46 libgloss might use errno/__errno, which might not have been needed when we 47 saw libc the first time, so link with libc a second time. */ 48 #undef LIB_SPEC 49 #define LIB_SPEC "%{!shared:%{g*:-lg} %{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p}} -lepiphany %{!shared:%{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p}}" 50 51 #define LINK_SPEC "%{v}" 52 53 #define STARTFILE_SPEC "%{!shared:crt0.o%s} crti.o%s " \ 54 "%{mfp-mode=int:crtint.o%s} %{mfp-mode=truncate:crtrunc.o%s} " \ 55 "%{m1reg-r43:crtm1reg-r43.o%s} %{m1reg-r63:crtm1reg-r63.o%s} " \ 56 "crtbegin.o%s" 57 58 #define ENDFILE_SPEC "crtend.o%s crtn.o%s" 59 60 #define EPIPHANY_LIBRARY_EXTRA_SPEC \ 61 "-ffixed-r40 -ffixed-r41 -ffixed-r42 -ffixed-r43" 62 63 /* In the "spec:" rule,, t-epiphany changes this to epiphany_library_stub_spec 64 and epiphany_library_extra_spec, respectively. */ 65 #define EXTRA_SPECS \ 66 { "epiphany_library_extra_spec", "" }, \ 67 { "epiphany_library_build_spec", EPIPHANY_LIBRARY_EXTRA_SPEC }, \ 68 69 #define DRIVER_SELF_SPECS " %(epiphany_library_extra_spec) " 70 71 #undef USER_LABEL_PREFIX 72 #define USER_LABEL_PREFIX "_" 73 74 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \ 75 asm (SECTION_OP "\n\ 76 mov r0,%low(" USER_LABEL_PREFIX #FUNC")\n\ 77 movt r0,%high(" USER_LABEL_PREFIX #FUNC")\n\ 78 jalr r0\n\ 79 .text"); 80 81 #if 0 /* We would like to use Posix for profiling, but the simulator 82 interface still lacks mkdir. */ 83 #define TARGET_POSIX_IO 84 #endif 85 86 /* Target machine storage layout. */ 87 88 /* Define this if most significant bit is lowest numbered 89 in instructions that operate on numbered bit-fields. */ 90 #define BITS_BIG_ENDIAN 0 91 92 /* Define this if most significant byte of a word is the lowest numbered. */ 93 #define BYTES_BIG_ENDIAN 0 94 95 /* Define this if most significant word of a multiword number is the lowest 96 numbered. */ 97 #define WORDS_BIG_ENDIAN 0 98 99 /* Width of a word, in units (bytes). */ 100 #define UNITS_PER_WORD 4 101 102 /* Define this macro if it is advisable to hold scalars in registers 103 in a wider mode than that declared by the program. In such cases, 104 the value is constrained to be within the bounds of the declared 105 type, but kept valid in the wider mode. The signedness of the 106 extension may differ from that of the type. */ 107 /* It is far faster to zero extend chars than to sign extend them */ 108 109 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ 110 if (GET_MODE_CLASS (MODE) == MODE_INT \ 111 && GET_MODE_SIZE (MODE) < 4) \ 112 { \ 113 if (MODE == QImode) \ 114 UNSIGNEDP = 1; \ 115 else if (MODE == HImode) \ 116 UNSIGNEDP = 1; \ 117 (MODE) = SImode; \ 118 } 119 120 /* Allocation boundary (in *bits*) for storing arguments in argument list. */ 121 #define PARM_BOUNDARY 32 122 123 /* Boundary (in *bits*) on which stack pointer should be aligned. */ 124 #define STACK_BOUNDARY 64 125 126 /* ALIGN FRAMES on word boundaries */ 127 #define EPIPHANY_STACK_ALIGN(LOC) (((LOC)+7) & ~7) 128 129 /* Allocation boundary (in *bits*) for the code of a function. */ 130 #define FUNCTION_BOUNDARY 32 131 132 /* Every structure's size must be a multiple of this. */ 133 #define STRUCTURE_SIZE_BOUNDARY 8 134 135 /* A bit-field declared as `int' forces `int' alignment for the struct. */ 136 #define PCC_BITFIELD_TYPE_MATTERS 1 137 138 /* No data type wants to be aligned rounder than this. */ 139 /* This is bigger than currently necessary for the EPIPHANY. If 8 byte floats are 140 ever added it's not clear whether they'll need such alignment or not. For 141 now we assume they will. We can always relax it if necessary but the 142 reverse isn't true. */ 143 #define BIGGEST_ALIGNMENT 64 144 145 /* The best alignment to use in cases where we have a choice. */ 146 #define FASTEST_ALIGNMENT 64 147 148 #define MALLOC_ABI_ALIGNMENT BIGGEST_ALIGNMENT 149 150 /* Make arrays of chars dword-aligned for the same reasons. 151 Also, align arrays of SImode items. */ 152 #define DATA_ALIGNMENT(TYPE, ALIGN) \ 153 (TREE_CODE (TYPE) == ARRAY_TYPE \ 154 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \ 155 && (ALIGN) < FASTEST_ALIGNMENT \ 156 ? FASTEST_ALIGNMENT \ 157 : (TREE_CODE (TYPE) == ARRAY_TYPE \ 158 && TYPE_MODE (TREE_TYPE (TYPE)) == SImode \ 159 && (ALIGN) < FASTEST_ALIGNMENT) \ 160 ? FASTEST_ALIGNMENT \ 161 : (ALIGN)) 162 163 /* Set this nonzero if move instructions will actually fail to work 164 when given unaligned data. */ 165 /* On the EPIPHANY the lower address bits are masked to 0 as necessary. The chip 166 won't croak when given an unaligned address, but the insn will still fail 167 to produce the correct result. */ 168 #define STRICT_ALIGNMENT 1 169 170 /* layout_type overrides our ADJUST_ALIGNMENT settings from epiphany-modes.def 171 for vector modes, so we have to override it back. */ 172 #define ROUND_TYPE_ALIGN(TYPE, MANGLED_ALIGN, SPECIFIED_ALIGN) \ 173 (TREE_CODE (TYPE) == VECTOR_TYPE && !TYPE_USER_ALIGN (TYPE) \ 174 && SPECIFIED_ALIGN <= GET_MODE_ALIGNMENT (TYPE_MODE (TYPE)) \ 175 ? GET_MODE_ALIGNMENT (TYPE_MODE (TYPE)) \ 176 : ((TREE_CODE (TYPE) == RECORD_TYPE \ 177 || TREE_CODE (TYPE) == UNION_TYPE \ 178 || TREE_CODE (TYPE) == QUAL_UNION_TYPE) \ 179 && !TYPE_PACKED (TYPE)) \ 180 ? epiphany_special_round_type_align ((TYPE), (MANGLED_ALIGN), \ 181 (SPECIFIED_ALIGN)) \ 182 : MAX ((MANGLED_ALIGN), (SPECIFIED_ALIGN))) 183 184 #define ADJUST_FIELD_ALIGN(FIELD, TYPE, COMPUTED) \ 185 epiphany_adjust_field_align((TYPE), (COMPUTED)) 186 187 /* Layout of source language data types. */ 188 189 #define SHORT_TYPE_SIZE 16 190 #define INT_TYPE_SIZE 32 191 #define LONG_TYPE_SIZE 32 192 #define LONG_LONG_TYPE_SIZE 64 193 #define FLOAT_TYPE_SIZE 32 194 #define DOUBLE_TYPE_SIZE 64 195 #define LONG_DOUBLE_TYPE_SIZE 64 196 197 /* Define this as 1 if `char' should by default be signed; else as 0. */ 198 #define DEFAULT_SIGNED_CHAR 0 199 200 #define SIZE_TYPE "long unsigned int" 201 #define PTRDIFF_TYPE "long int" 202 #define WCHAR_TYPE "unsigned int" 203 #define WCHAR_TYPE_SIZE BITS_PER_WORD 204 205 /* Standard register usage. */ 206 207 /* Number of actual hardware registers. 208 The hardware registers are assigned numbers for the compiler 209 from 0 to just below FIRST_PSEUDO_REGISTER. 210 All registers that the compiler knows about must be given numbers, 211 even those that are not normally considered general registers. */ 212 213 #define FIRST_PSEUDO_REGISTER 78 214 215 216 /* General purpose registers. */ 217 #define GPR_FIRST 0 /* First gpr */ 218 219 #define PIC_REGNO (GPR_FIRST + 28) /* PIC register. */ 220 #define GPR_LAST (GPR_FIRST + 63) /* Last gpr */ 221 #define CORE_CONTROL_FIRST CONFIG_REGNUM 222 #define CORE_CONTROL_LAST IRET_REGNUM 223 224 #define GPR_P(R) IN_RANGE (R, GPR_FIRST, GPR_LAST) 225 #define GPR_OR_AP_P(R) (GPR_P (R) || (R) == ARG_POINTER_REGNUM) 226 227 #define GPR_OR_PSEUDO_P(R) (GPR_P (R) || (R) >= FIRST_PSEUDO_REGISTER) 228 #define GPR_AP_OR_PSEUDO_P(R) (GPR_OR_AP_P (R) || (R) >= FIRST_PSEUDO_REGISTER) 229 230 #define FIXED_REGISTERS \ 231 { /* Integer Registers */ \ 232 0, 0, 0, 0, 0, 0, 0, 0, /* 000-007, gr0 - gr7 */ \ 233 0, 0, 0, 0, 0, 1, 0, 0, /* 008-015, gr8 - gr15 */ \ 234 0, 0, 0, 0, 0, 0, 0, 0, /* 016-023, gr16 - gr23 */ \ 235 0, 0, 0, 0, 1, 1, 1, 1, /* 024-031, gr24 - gr31 */ \ 236 0, 0, 0, 0, 0, 0, 0, 0, /* 032-039, gr32 - gr39 */ \ 237 0, 0, 0, 0, 0, 0, 0, 0, /* 040-047, gr40 - gr47 */ \ 238 0, 0, 0, 0, 0, 0, 0, 0, /* 048-055, gr48 - gr55 */ \ 239 0, 0, 0, 0, 0, 0, 0, 0, /* 056-063, gr56 - gr63 */ \ 240 /* Other registers */ \ 241 1, /* 64 AP - fake arg ptr */ \ 242 1, /* soft frame pointer */ \ 243 1, /* CC_REGNUM - integer conditions */\ 244 1, /* CCFP_REGNUM - fp conditions */\ 245 1, 1, 1, 1, 1, 1, /* Core Control Registers. */ \ 246 1, 1, 1, /* FP_{NEAREST,...}_REGNUM */\ 247 1, /* UNKNOWN_REGNUM - placeholder. */\ 248 } 249 250 /* Like `FIXED_REGISTERS' but has 1 for each register that is clobbered (in 251 general) by function calls as well as for fixed registers. This macro 252 therefore identifies the registers that are not available for general 253 allocation of values that must live across function calls. 254 255 If a register has 0 in `CALL_USED_REGISTERS', the compiler automatically 256 saves it on function entry and restores it on function exit, if the register 257 is used within the function. */ 258 259 #define CALL_USED_REGISTERS \ 260 { /* Integer Registers */ \ 261 1, 1, 1, 1, 0, 0, 0, 0, /* 000-007, gr0 - gr7 */ \ 262 0, 0, 0, 0, 1, 1, 1, 0, /* 008-015, gr8 - gr15 */ \ 263 1, 1, 1, 1, 1, 1, 1, 1, /* 016-023, gr16 - gr23 */ \ 264 1, 1, 1, 1, 1, 1, 1, 1, /* 024-031, gr24 - gr31 */ \ 265 0, 0, 0, 0, 0, 0, 0, 0, /* 032-039, gr32 - gr38 */ \ 266 0, 0, 0, 0, 1, 1, 1, 1, /* 040-047, gr40 - gr47 */ \ 267 1, 1, 1, 1, 1, 1, 1, 1, /* 048-055, gr48 - gr55 */ \ 268 1, 1, 1, 1, 1, 1, 1, 1, /* 056-063, gr56 - gr63 */ \ 269 1, /* 64 AP - fake arg ptr */ \ 270 1, /* soft frame pointer */ \ 271 1, /* 66 CC_REGNUM */ \ 272 1, /* 67 CCFP_REGNUM */ \ 273 1, 1, 1, 1, 1, 1, /* Core Control Registers. */ \ 274 1, 1, 1, /* FP_{NEAREST,...}_REGNUM */\ 275 1, /* UNKNOWN_REGNUM - placeholder. */\ 276 } 277 278 #define REG_ALLOC_ORDER \ 279 { \ 280 0, 1, 2, 3, /* Caller-saved 'small' registers. */ \ 281 12, /* Caller-saved unpaired register. */ \ 282 /* Caller-saved registers. */ \ 283 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, \ 284 44, 45, 46, 47, \ 285 48, 49, 50, 51, 52, 53, 54, 55, \ 286 56, 57, 58, 59, 60, 61, 62, 63, \ 287 4, 5, 6, 7, /* Calle-saved 'small' registers. */ \ 288 15, /* Calle-saved unpaired register. */ \ 289 8, 9, 10, 11, /* Calle-saved registers. */ \ 290 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, \ 291 14, 13, /* Link register, stack pointer. */ \ 292 /* Can't allocate, but must name these... */ \ 293 28, 29, 30, 31, \ 294 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77 \ 295 } 296 297 #define HARD_REGNO_RENAME_OK(SRC, DST) epiphany_regno_rename_ok (SRC, DST) 298 299 /* Register classes and constants. */ 300 301 /* Define the classes of registers for register constraints in the 302 machine description. Also define ranges of constants. 303 304 One of the classes must always be named ALL_REGS and include all hard regs. 305 If there is more than one class, another class must be named NO_REGS 306 and contain no registers. 307 308 The name GENERAL_REGS must be the name of a class (or an alias for 309 another name such as ALL_REGS). This is the class of registers 310 that is allowed by "g" or "r" in a register constraint. 311 Also, registers outside this class are allocated only when 312 instructions express preferences for them. 313 314 The classes must be numbered in nondecreasing order; that is, 315 a larger-numbered class must never be contained completely 316 in a smaller-numbered class. 317 318 For any two classes, it is very desirable that there be another 319 class that represents their union. 320 321 It is important that any condition codes have class NO_REGS. 322 See `register_operand'. */ 323 324 enum reg_class { 325 NO_REGS, 326 LR_REGS, 327 SHORT_INSN_REGS, 328 SIBCALL_REGS, 329 GENERAL_REGS, 330 CORE_CONTROL_REGS, 331 ALL_REGS, 332 LIM_REG_CLASSES 333 }; 334 335 #define N_REG_CLASSES ((int) LIM_REG_CLASSES) 336 337 /* Give names of register classes as strings for dump file. */ 338 #define REG_CLASS_NAMES \ 339 { \ 340 "NO_REGS", \ 341 "LR_REGS", \ 342 "SHORT_INSN_REGS", \ 343 "SIBCALL_REGS", \ 344 "GENERAL_REGS", \ 345 "CORE_CONTROL_REGS", \ 346 "ALL_REGS" \ 347 } 348 349 /* Define which registers fit in which classes. 350 This is an initializer for a vector of HARD_REG_SET 351 of length N_REG_CLASSES. */ 352 353 #define REG_CLASS_CONTENTS \ 354 { /* r0-r31 r32-r63 ap/sfp/cc1/cc2/iret/status */ \ 355 { 0x00000000,0x00000000,0x0}, /* NO_REGS */ \ 356 { 0x00004000,0x00000000,0x0}, /* LR_REGS */ \ 357 { 0x000000ff,0x00000000,0x0}, /* SHORT_INSN_REGS */ \ 358 { 0xffff100f,0xffffff00,0x0}, /* SIBCALL_REGS */ \ 359 { 0xffffffff,0xffffffff,0x0003}, /* GENERAL_REGS */ \ 360 { 0x00000000,0x00000000,0x03f0}, /* CORE_CONTROL_REGS */ \ 361 { 0xffffffff,0xffffffff,0x3fff}, /* ALL_REGS */ \ 362 } 363 364 365 /* The same information, inverted: 366 Return the class number of the smallest class containing 367 reg number REGNO. This could be a conditional expression 368 or could index an array. */ 369 extern enum reg_class epiphany_regno_reg_class[FIRST_PSEUDO_REGISTER]; 370 #define REGNO_REG_CLASS(REGNO) \ 371 (epiphany_regno_reg_class[REGNO]) 372 373 /* The class value for index registers, and the one for base regs. */ 374 #define BASE_REG_CLASS GENERAL_REGS 375 #define INDEX_REG_CLASS GENERAL_REGS 376 377 /* These assume that REGNO is a hard or pseudo reg number. 378 They give nonzero only if REGNO is a hard reg of the suitable class 379 or a pseudo reg currently allocated to a suitable hard reg. 380 Since they use reg_renumber, they are safe only once reg_renumber 381 has been allocated, which happens in reginfo.c during register 382 allocation. */ 383 #define REGNO_OK_FOR_BASE_P(REGNO) \ 384 ((REGNO) < FIRST_PSEUDO_REGISTER || (unsigned) reg_renumber[REGNO] < FIRST_PSEUDO_REGISTER) 385 #define REGNO_OK_FOR_INDEX_P(REGNO) \ 386 ((REGNO) < FIRST_PSEUDO_REGISTER || (unsigned) reg_renumber[REGNO] < FIRST_PSEUDO_REGISTER) 387 388 389 390 /* Given an rtx X being reloaded into a reg required to be 391 in class CLASS, return the class of reg to actually use. 392 In general this is just CLASS; but on some machines 393 in some cases it is preferable to use a more restrictive class. */ 394 #define PREFERRED_RELOAD_CLASS(X,CLASS) \ 395 (CLASS) 396 397 /* Return the maximum number of consecutive registers 398 needed to represent mode MODE in a register of class CLASS. */ 399 #define CLASS_MAX_NREGS(CLASS, MODE) \ 400 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) 401 402 /* The letters I, J, K, L, M, N, O, P in a register constraint string 403 can be used to stand for particular ranges of immediate operands. 404 This macro defines what the ranges are. 405 C is the letter, and VALUE is a constant value. 406 Return 1 if VALUE is in the range specified by C. */ 407 408 /* 'I' is used for 16 bit unsigned. 409 'Cal' is used for long immediates (32 bits) 410 'K' is used for any constant up to 5 bits. 411 'L' is used for any 11 bit signed. 412 */ 413 414 #define IMM16(X) (IN_RANGE ((X), 0, 0xFFFF)) 415 #define SIMM16(X) (IN_RANGE ((X), -65536, 65535)) 416 #define SIMM11(X) (IN_RANGE ((X), -1024, 1023)) 417 #define IMM5(X) (IN_RANGE ((X), 0, 0x1F)) 418 419 typedef struct GTY (()) machine_function 420 { 421 unsigned args_parsed : 1; 422 unsigned pretend_args_odd : 1; 423 unsigned lr_clobbered : 1; 424 unsigned control_use_inserted : 1; 425 unsigned lr_slot_known : 1; 426 unsigned sw_entities_processed : 6; 427 long lr_slot_offset; 428 rtx and_mask; 429 rtx or_mask; 430 unsigned unknown_mode_uses; 431 unsigned unknown_mode_sets; 432 } machine_function_t; 433 434 #define MACHINE_FUNCTION(fun) (fun)->machine 435 436 #define INIT_EXPANDERS epiphany_init_expanders () 437 438 /* Stack layout and stack pointer usage. */ 439 440 /* Define this macro if pushing a word onto the stack moves the stack 441 pointer to a smaller address. */ 442 #define STACK_GROWS_DOWNWARD 1 443 444 /* Define this to nonzero if the nominal address of the stack frame 445 is at the high-address end of the local variables; 446 that is, each additional local variable allocated 447 goes at a more negative offset in the frame. */ 448 #define FRAME_GROWS_DOWNWARD 1 449 450 /* Offset from the stack pointer register to the first location at which 451 outgoing arguments are placed. */ 452 #define STACK_POINTER_OFFSET epiphany_stack_offset 453 454 /* Offset of first parameter from the argument pointer register value. */ 455 /* 4 bytes for each of previous fp, return address, and previous gp. 456 4 byte reserved area for future considerations. */ 457 #define FIRST_PARM_OFFSET(FNDECL) \ 458 (epiphany_stack_offset \ 459 + (MACHINE_FUNCTION (DECL_STRUCT_FUNCTION (FNDECL))->pretend_args_odd \ 460 ? 4 : 0)) 461 462 #define INCOMING_FRAME_SP_OFFSET epiphany_stack_offset 463 464 /* Register to use for pushing function arguments. */ 465 #define STACK_POINTER_REGNUM GPR_SP 466 467 /* Base register for access to local variables of the function. */ 468 #define HARD_FRAME_POINTER_REGNUM GPR_FP 469 470 /* Register in which static-chain is passed to a function. This must 471 not be a register used by the prologue. */ 472 #define STATIC_CHAIN_REGNUM GPR_IP 473 474 /* Define the offset between two registers, one to be eliminated, and the other 475 its replacement, at the start of a routine. */ 476 477 #define ELIMINABLE_REGS \ 478 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 479 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ 480 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 481 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ 482 } 483 484 /* Define the offset between two registers, one to be eliminated, and the other 485 its replacement, at the start of a routine. */ 486 487 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 488 ((OFFSET) = epiphany_initial_elimination_offset ((FROM), (TO))) 489 490 /* Function argument passing. */ 491 492 /* If defined, the maximum amount of space required for outgoing 493 arguments will be computed and placed into the variable 494 `current_function_outgoing_args_size'. No space will be pushed 495 onto the stack for each call; instead, the function prologue should 496 increase the stack frame size by this amount. */ 497 #define ACCUMULATE_OUTGOING_ARGS 1 498 499 /* Define a data type for recording info about an argument list 500 during the scan of that argument list. This data type should 501 hold all necessary information about the function itself 502 and about the args processed so far, enough to enable macros 503 such as FUNCTION_ARG to determine where the next arg should go. */ 504 #define CUMULATIVE_ARGS int 505 506 /* Initialize a variable CUM of type CUMULATIVE_ARGS 507 for a call to a function whose data type is FNTYPE. 508 For a library call, FNTYPE is 0. */ 509 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \ 510 ((CUM) = 0) 511 512 /* The number of registers used for parameter passing. Local to this file. */ 513 #define MAX_EPIPHANY_PARM_REGS 4 514 515 /* 1 if N is a possible register number for function argument passing. */ 516 #define FUNCTION_ARG_REGNO_P(N) \ 517 ((unsigned) (N) < MAX_EPIPHANY_PARM_REGS) 518 519 /* Return boolean indicating arg of type TYPE and mode MODE will be passed in 520 a reg. This includes arguments that have to be passed by reference as the 521 pointer to them is passed in a reg if one is available (and that is what 522 we're given). 523 This macro is only used in this file. */ 524 /* We must use partial argument passing because of the chosen mode 525 of varargs handling. */ 526 #define PASS_IN_REG_P(CUM, MODE, TYPE) \ 527 (ROUND_ADVANCE_CUM ((CUM), (MODE), (TYPE)) < MAX_EPIPHANY_PARM_REGS) 528 529 /* Tell GCC to use TARGET_RETURN_IN_MEMORY. */ 530 #define DEFAULT_PCC_STRUCT_RETURN 0 531 532 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, 533 the stack pointer does not matter. The value is tested only in 534 functions that have frame pointers. 535 No definition is equivalent to always zero. */ 536 #define EXIT_IGNORE_STACK 1 537 538 #define EPILOGUE_USES(REGNO) epiphany_epilogue_uses (REGNO) 539 540 /* Output assembler code to FILE to increment profiler label # LABELNO 541 for profiling a function entry. */ 542 #define FUNCTION_PROFILER(FILE, LABELNO) 543 544 /* Given an rtx for the frame pointer, 545 return an rtx for the address of the frame. */ 546 #define FRAME_ADDR_RTX(frame) \ 547 ((frame) == hard_frame_pointer_rtx ? arg_pointer_rtx : NULL) 548 549 #define EPIPHANY_RETURN_REGNO \ 550 ((current_function_decl != NULL \ 551 && epiphany_is_interrupt_p (current_function_decl)) \ 552 ? IRET_REGNUM : GPR_LR) 553 /* This is not only for dwarf unwind info, but also for the benefit of 554 df-scan.c to tell it that LR is live at the function start. */ 555 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, EPIPHANY_RETURN_REGNO) 556 557 /* However, we haven't implemented the rest needed for dwarf2 unwind info. */ 558 #define DWARF2_UNWIND_INFO 0 559 560 #define RETURN_ADDR_RTX(count, frame) \ 561 (count ? NULL_RTX \ 562 : gen_rtx_UNSPEC (SImode, gen_rtvec (1, const0_rtx), UNSPEC_RETURN_ADDR)) 563 564 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (EPIPHANY_RETURN_REGNO) 565 566 /* Trampolines. 567 An epiphany trampoline looks like this: 568 mov r16,%low(fnaddr) 569 movt r16,%high(fnaddr) 570 mov ip,%low(cxt) 571 movt ip,%high(cxt) 572 jr r16 */ 573 574 /* Length in units of the trampoline for entering a nested function. */ 575 #define TRAMPOLINE_SIZE 20 576 577 /* Addressing modes, and classification of registers for them. */ 578 579 /* Maximum number of registers that can appear in a valid memory address. */ 580 #define MAX_REGS_PER_ADDRESS 2 581 582 /* We have post_modify (load/store with update). */ 583 #define HAVE_POST_INCREMENT TARGET_POST_INC 584 #define HAVE_POST_DECREMENT TARGET_POST_INC 585 #define HAVE_POST_MODIFY_DISP TARGET_POST_MODIFY 586 #define HAVE_POST_MODIFY_REG TARGET_POST_MODIFY 587 588 /* Currently, the only users of the USE_*CREMENT macros are 589 move_by_pieces / store_by_pieces_1 . We don't want them to use 590 POST_MODIFY modes, because we got ample addressing range for the 591 reg+offset addressing mode; besides, there are short index+offset loads, 592 but the only short post-modify load uses POST_MODIFY_REG. 593 Moreover, using auto-increment in move_by_pieces from structure copying 594 in the prologue causes confused debug output. 595 If another pass starts using these macros where the use of these 596 addressing modes would make more sense, we can try checking the 597 current pass. */ 598 #define USE_LOAD_POST_INCREMENT(MODE) 0 599 #define USE_LOAD_POST_DECREMENT(MODE) 0 600 #define USE_STORE_POST_INCREMENT(MODE) 0 601 #define USE_STORE_POST_DECREMENT(MODE) 0 602 603 /* Recognize any constant value that is a valid address. */ 604 #define CONSTANT_ADDRESS_P(X) \ 605 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \ 606 || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST) 607 608 #define RTX_OK_FOR_OFFSET_P(MODE, X) \ 609 RTX_OK_FOR_OFFSET_1 (GET_MODE_CLASS (MODE) == MODE_VECTOR_INT \ 610 && epiphany_vect_align == 4 \ 611 ? (machine_mode) SImode : (machine_mode) (MODE), X) 612 #define RTX_OK_FOR_OFFSET_1(MODE, X) \ 613 (GET_CODE (X) == CONST_INT \ 614 && !(INTVAL (X) & (GET_MODE_SIZE (MODE) - 1)) \ 615 && INTVAL (X) >= -2047 * (int) GET_MODE_SIZE (MODE) \ 616 && INTVAL (X) <= 2047 * (int) GET_MODE_SIZE (MODE)) 617 618 /* Frame offsets cannot be evaluated till the frame pointer is eliminated. */ 619 #define RTX_FRAME_OFFSET_P(X) \ 620 ((X) == frame_pointer_rtx \ 621 || (GET_CODE (X) == PLUS && XEXP ((X), 0) == frame_pointer_rtx \ 622 && CONST_INT_P (XEXP ((X), 1)))) 623 624 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, 625 return the mode to be used for the comparison. */ 626 #define SELECT_CC_MODE(OP, X, Y) \ 627 epiphany_select_cc_mode (OP, X, Y) 628 629 /* Return nonzero if SELECT_CC_MODE will never return MODE for a 630 floating point inequality comparison. */ 631 632 #define REVERSE_CONDITION(CODE, MODE) \ 633 ((MODE) == CC_FPmode || (MODE) == CC_FP_EQmode || (MODE) == CC_FP_GTEmode \ 634 || (MODE) == CC_FP_ORDmode || (MODE) == CC_FP_UNEQmode \ 635 ? reverse_condition_maybe_unordered (CODE) \ 636 : (MODE) == CCmode ? reverse_condition (CODE) \ 637 : UNKNOWN) 638 639 /* We can reverse all CCmodes with REVERSE_CONDITION. */ 640 #define REVERSIBLE_CC_MODE(MODE) \ 641 ((MODE) == CCmode || (MODE) == CC_FPmode || (MODE) == CC_FP_EQmode \ 642 || (MODE) == CC_FP_GTEmode || (MODE) == CC_FP_ORDmode \ 643 || (MODE) == CC_FP_UNEQmode) 644 645 /* Costs. */ 646 647 /* The cost of a branch insn. */ 648 /* ??? What's the right value here? Branches are certainly more 649 expensive than reg->reg moves. */ 650 #define BRANCH_COST(speed_p, predictable_p) \ 651 (speed_p ? epiphany_branch_cost : 1) 652 653 /* Nonzero if access to memory by bytes is slow and undesirable. 654 For RISC chips, it means that access to memory by bytes is no 655 better than access by words when possible, so grab a whole word 656 and maybe make use of that. */ 657 #define SLOW_BYTE_ACCESS 1 658 659 /* Define this macro if it is as good or better to call a constant 660 function address than to call an address kept in a register. */ 661 /* On the EPIPHANY, calling through registers is slow. */ 662 #define NO_FUNCTION_CSE 1 663 664 /* Section selection. */ 665 /* WARNING: These section names also appear in dwarf2out.c. */ 666 667 #define TEXT_SECTION_ASM_OP "\t.section .text" 668 #define DATA_SECTION_ASM_OP "\t.section .data" 669 670 #undef READONLY_DATA_SECTION_ASM_OP 671 #define READONLY_DATA_SECTION_ASM_OP "\t.section .rodata" 672 673 #define BSS_SECTION_ASM_OP "\t.section .bss" 674 675 /* Define this macro if jump tables (for tablejump insns) should be 676 output in the text section, along with the assembler instructions. 677 Otherwise, the readonly data section is used. 678 This macro is irrelevant if there is no separate readonly data section. */ 679 #define JUMP_TABLES_IN_TEXT_SECTION (flag_pic) 680 681 /* PIC */ 682 683 /* The register number of the register used to address a table of static 684 data addresses in memory. In some cases this register is defined by a 685 processor's ``application binary interface'' (ABI). When this macro 686 is defined, RTL is generated for this register once, as with the stack 687 pointer and frame pointer registers. If this macro is not defined, it 688 is up to the machine-dependent files to allocate such a register (if 689 necessary). */ 690 #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? PIC_REGNO : INVALID_REGNUM) 691 692 /* Control the assembler format that we output. */ 693 694 /* A C string constant describing how to begin a comment in the target 695 assembler language. The compiler assumes that the comment will 696 end at the end of the line. */ 697 #define ASM_COMMENT_START ";" 698 699 /* Output to assembler file text saying following lines 700 may contain character constants, extra white space, comments, etc. */ 701 #define ASM_APP_ON "" 702 703 /* Output to assembler file text saying following lines 704 no longer contain unusual constructs. */ 705 #define ASM_APP_OFF "" 706 707 /* Globalizing directive for a label. */ 708 #define GLOBAL_ASM_OP "\t.global\t" 709 710 /* How to refer to registers in assembler output. 711 This sequence is indexed by compiler's hard-register-number (see above). */ 712 713 #define REGISTER_NAMES \ 714 { \ 715 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \ 716 "r8", "r9", "r10", "fp", "ip", "sp", "lr", "r15", \ 717 "r16", "r17","r18", "r19", "r20", "r21", "r22", "r23", \ 718 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", \ 719 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39", \ 720 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47", \ 721 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55", \ 722 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63", \ 723 "ap", "sfp", "cc1", "cc2", \ 724 "config", "status", "lc", "ls", "le", "iret", \ 725 "fp_near", "fp_trunc", "fp_anyfp", "unknown" \ 726 } 727 728 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \ 729 epiphany_final_prescan_insn (INSN, OPVEC, NOPERANDS) 730 731 #define LOCAL_LABEL_PREFIX "." 732 733 /* A C expression which evaluates to true if CODE is a valid 734 punctuation character for use in the `PRINT_OPERAND' macro. */ 735 extern char epiphany_punct_chars[256]; 736 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \ 737 epiphany_punct_chars[(unsigned char) (CHAR)] 738 739 /* This is how to output an element of a case-vector that is absolute. */ 740 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ 741 do { \ 742 if (CASE_VECTOR_MODE == Pmode) \ 743 asm_fprintf ((FILE), "\t.word %LL%d\n", (VALUE)); \ 744 else \ 745 asm_fprintf ((FILE), "\t.short %LL%d\n", (VALUE)); \ 746 } while (0) 747 748 /* This is how to output an element of a case-vector that is relative. */ 749 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ 750 do { \ 751 if (CASE_VECTOR_MODE == Pmode) \ 752 asm_fprintf ((FILE), "\t.word"); \ 753 else \ 754 asm_fprintf ((FILE), "\t.short"); \ 755 asm_fprintf ((FILE), " %LL%d-%LL%d\n", (VALUE), (REL)); \ 756 } while (0) 757 758 /* This is how to output an assembler line 759 that says to advance the location counter 760 to a multiple of 2**LOG bytes. */ 761 #define ASM_OUTPUT_ALIGN(FILE, LOG) \ 762 do { if ((LOG) != 0) fprintf (FILE, "\t.balign %d\n", 1 << (LOG)); } while (0) 763 764 /* Inside the text section, align with nops rather than zeros. */ 765 #define ASM_OUTPUT_ALIGN_WITH_NOP(FILE, LOG) \ 766 do \ 767 { \ 768 if ((LOG) != 0) fprintf (FILE, "\t.balignw %d,0x01a2\n", 1 << (LOG)); \ 769 } while (0) 770 771 /* This is how to declare the size of a function. */ 772 #undef ASM_DECLARE_FUNCTION_SIZE 773 #define ASM_DECLARE_FUNCTION_SIZE(FILE, FNAME, DECL) \ 774 do \ 775 { \ 776 const char *__name = (FNAME); \ 777 tree attrs = DECL_ATTRIBUTES ((DECL)); \ 778 \ 779 if (!flag_inhibit_size_directive) \ 780 { \ 781 if (lookup_attribute ("forwarder_section", attrs)) \ 782 { \ 783 const char *prefix = "__forwarder_dst_"; \ 784 char *dst_name \ 785 = (char *) alloca (strlen (prefix) + strlen (__name) + 1); \ 786 \ 787 strcpy (dst_name, prefix); \ 788 strcat (dst_name, __name); \ 789 __name = dst_name; \ 790 } \ 791 ASM_OUTPUT_MEASURED_SIZE ((FILE), __name); \ 792 } \ 793 } \ 794 while (0) 795 796 /* Debugging information. */ 797 798 /* Generate DBX and DWARF debugging information. */ 799 #define DBX_DEBUGGING_INFO 1 800 801 #undef PREFERRED_DEBUGGING_TYPE 802 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG 803 804 /* Turn off splitting of long stabs. */ 805 #define DBX_CONTIN_LENGTH 0 806 807 /* Miscellaneous. */ 808 809 /* Specify the machine mode that this machine uses 810 for the index in the tablejump instruction. */ 811 #define CASE_VECTOR_MODE (TARGET_SMALL16 && optimize_size ? HImode : Pmode) 812 813 /* Define if operations between registers always perform the operation 814 on the full register even if a narrower mode is specified. */ 815 #define WORD_REGISTER_OPERATIONS 1 816 817 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD 818 will either zero-extend or sign-extend. The value of this macro should 819 be the code that says which one of the two operations is implicitly 820 done, UNKNOWN if none. */ 821 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND 822 823 /* Max number of bytes we can move from memory to memory 824 in one reasonably fast instruction. */ 825 #define MOVE_MAX 8 826 827 /* Define this to be nonzero if shift instructions ignore all but the low-order 828 few bits. */ 829 #define SHIFT_COUNT_TRUNCATED 1 830 831 /* Specify the machine mode that pointers have. 832 After generation of rtl, the compiler makes no further distinction 833 between pointers and any other objects of this machine mode. */ 834 835 #define Pmode SImode 836 837 /* A function address in a call instruction. */ 838 #define FUNCTION_MODE SImode 839 840 /* EPIPHANY function types. */ 841 enum epiphany_function_type 842 { 843 EPIPHANY_FUNCTION_UNKNOWN, EPIPHANY_FUNCTION_NORMAL, 844 EPIPHANY_FUNCTION_INTERRUPT 845 }; 846 847 #define EPIPHANY_INTERRUPT_P(TYPE) ((TYPE) == EPIPHANY_FUNCTION_INTERRUPT) 848 849 /* Compute the type of a function from its DECL. */ 850 851 #define IMMEDIATE_PREFIX "#" 852 853 #define OPTIMIZE_MODE_SWITCHING(ENTITY) \ 854 (epiphany_optimize_mode_switching (ENTITY)) 855 856 /* We have two fake entities for lazy code motion of the mask constants, 857 one entity each for round-to-nearest / truncating 858 with a different idea what FP_MODE_ROUND_UNKNOWN will be, and 859 finally an entity that runs in a second mode switching pass to 860 resolve FP_MODE_ROUND_UNKNOWN. */ 861 #define NUM_MODES_FOR_MODE_SWITCHING \ 862 { 2, 2, 2, \ 863 FP_MODE_NONE, FP_MODE_NONE, FP_MODE_NONE, FP_MODE_NONE, FP_MODE_NONE } 864 865 #define TARGET_INSERT_MODE_SWITCH_USE epiphany_insert_mode_switch_use 866 867 /* Mode switching entities. */ 868 enum 869 { 870 EPIPHANY_MSW_ENTITY_AND, 871 EPIPHANY_MSW_ENTITY_OR, 872 EPIPHANY_MSW_ENTITY_CONFIG, /* 1 means config is known or saved. */ 873 EPIPHANY_MSW_ENTITY_NEAREST, 874 EPIPHANY_MSW_ENTITY_TRUNC, 875 EPIPHANY_MSW_ENTITY_ROUND_UNKNOWN, 876 EPIPHANY_MSW_ENTITY_ROUND_KNOWN, 877 EPIPHANY_MSW_ENTITY_FPU_OMNIBUS, 878 EPIPHANY_MSW_ENTITY_NUM 879 }; 880 881 extern int epiphany_normal_fp_rounding; 882 #ifndef USED_FOR_TARGET 883 extern rtl_opt_pass *make_pass_mode_switch_use (gcc::context *ctxt); 884 extern rtl_opt_pass *make_pass_resolve_sw_modes (gcc::context *ctxt); 885 #endif 886 887 /* This will need to be adjusted when FP_CONTRACT_ON is properly 888 implemented. */ 889 #define TARGET_FUSED_MADD (flag_fp_contract_mode == FP_CONTRACT_FAST) 890 891 #undef ASM_DECLARE_FUNCTION_NAME 892 #define ASM_DECLARE_FUNCTION_NAME(FILE, NAME, DECL) \ 893 epiphany_start_function ((FILE), (NAME), (DECL)) 894 895 /* This is how we tell the assembler that two symbols have the same value. */ 896 #define ASM_OUTPUT_DEF(FILE, NAME1, NAME2) \ 897 do \ 898 { \ 899 assemble_name (FILE, NAME1); \ 900 fputs (" = ", FILE); \ 901 assemble_name (FILE, NAME2); \ 902 fputc ('\n', FILE); \ 903 } \ 904 while (0) 905 906 #endif /* !GCC_EPIPHANY_H */ 907