1;; Scheduling description for z900 (cpu 2064).
2;;   Copyright (C) 2003, 2004, 2005 Free Software Foundation, Inc.
3;;   Contributed by Hartmut Penner (hpenner@de.ibm.com) and
4;;                  Ulrich Weigand (uweigand@de.ibm.com).
5
6;; This file is part of GCC.
7
8;; GCC is free software; you can redistribute it and/or modify it under
9;; the terms of the GNU General Public License as published by the Free
10;; Software Foundation; either version 2, or (at your option) any later
11;; version.
12
13;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14;; WARRANTY; without even the implied warranty of MERCHANTABILITY or
15;; FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
16;; for more details.
17
18;; You should have received a copy of the GNU General Public License
19;; along with GCC; see the file COPYING.  If not, write to the Free
20;; Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
21;; 02110-1301, USA.
22
23;;
24;; References:
25;;   The microarchitecture of the IBM eServer z900 processor.
26;;   E.M. Schwarz et al.
27;;   IBM Journal of Research and Development Vol. 46 No 4/5, 2002.
28;;
29;;            z900 (cpu 2064) pipeline
30;;
31;;                 dec
32;;              --> | <---
33;;  LA bypass  |  agen    |
34;;             |    |     |
35;;              --- c1    |  Load bypass
36;;                  |     |
37;;                  c2----
38;;                  |
39;;                  e1
40;;                  |
41;;                  wr
42
43;; This scheduler description is also used for the g5 and g6.
44
45(define_automaton "z_ipu")
46(define_cpu_unit "z_e1"   "z_ipu")
47(define_cpu_unit "z_wr"   "z_ipu")
48
49
50(define_insn_reservation "z_la" 1
51  (and (eq_attr "cpu" "z900,g5,g6")
52       (eq_attr "type" "la"))
53  "z_e1,z_wr")
54
55(define_insn_reservation "z_larl" 1
56  (and (eq_attr "cpu" "z900,g5,g6")
57       (eq_attr "type" "larl"))
58  "z_e1,z_wr")
59
60(define_insn_reservation "z_load" 1
61  (and (eq_attr "cpu" "z900,g5,g6")
62       (eq_attr "type" "load"))
63  "z_e1,z_wr")
64
65(define_insn_reservation "z_store" 1
66  (and (eq_attr "cpu" "z900,g5,g6")
67       (eq_attr "type" "store"))
68  "z_e1,z_wr")
69
70(define_insn_reservation "z_sem" 2
71  (and (eq_attr "cpu" "z900,g5,g6")
72       (eq_attr "type" "sem"))
73  "z_e1*2,z_wr")
74
75(define_insn_reservation "z_call" 5
76  (and (eq_attr "cpu" "z900,g5,g6")
77       (eq_attr "type" "jsr"))
78  "z_e1*5,z_wr")
79
80(define_insn_reservation "z_mul" 5
81  (and (eq_attr "cpu" "g5,g6,z900")
82       (eq_attr "type" "imulsi,imulhi"))
83  "z_e1*5,z_wr")
84
85(define_insn_reservation "z_inf" 10
86  (and (eq_attr "cpu" "g5,g6,z900")
87       (eq_attr "type" "idiv,imuldi"))
88  "z_e1*10,z_wr")
89
90;; For everything else we check the atype flag.
91
92(define_insn_reservation "z_int" 1
93  (and (eq_attr "cpu" "z900,g5,g6")
94       (and (not (eq_attr "type" "la,larl,load,store,jsr"))
95            (eq_attr "atype" "reg")))
96  "z_e1,z_wr")
97
98(define_insn_reservation "z_agen" 1
99  (and (eq_attr "cpu" "z900,g5,g6")
100       (and (not (eq_attr "type" "la,larl,load,store,jsr"))
101            (eq_attr "atype" "agen")))
102  "z_e1,z_wr")
103
104;;
105;; s390_agen_dep_p returns 1, if a register is set in the
106;; first insn and used in the dependent insn to form a address.
107;;
108
109;;
110;; If an instruction uses a register to address memory, it needs
111;; to be set 5 cycles in advance.
112;;
113
114(define_bypass 5 "z_int,z_agen"
115	       "z_agen,z_la,z_call,z_load,z_store" "s390_agen_dep_p")
116
117;;
118;; A load type instruction uses a bypass to feed the result back
119;; to the address generation pipeline stage.
120;;
121
122(define_bypass 3 "z_load"
123	         "z_agen,z_la,z_call,z_load,z_store" "s390_agen_dep_p")
124
125;;
126;; A load address type instruction uses a bypass to feed the
127;; result back to the address generation pipeline stage.
128;;
129
130(define_bypass 2 "z_larl,z_la"
131	         "z_agen,z_la,z_call,z_load,z_store" "s390_agen_dep_p")
132
133
134
135
136
137