1 /* --------------------------------------------------------------  */
2 /* (C)Copyright 2001,2008,                                         */
3 /* International Business Machines Corporation,                    */
4 /* Sony Computer Entertainment, Incorporated,                      */
5 /* Toshiba Corporation,                                            */
6 /*                                                                 */
7 /* All Rights Reserved.                                            */
8 /*                                                                 */
9 /* Redistribution and use in source and binary forms, with or      */
10 /* without modification, are permitted provided that the           */
11 /* following conditions are met:                                   */
12 /*                                                                 */
13 /* - Redistributions of source code must retain the above copyright*/
14 /*   notice, this list of conditions and the following disclaimer. */
15 /*                                                                 */
16 /* - Redistributions in binary form must reproduce the above       */
17 /*   copyright notice, this list of conditions and the following   */
18 /*   disclaimer in the documentation and/or other materials        */
19 /*   provided with the distribution.                               */
20 /*                                                                 */
21 /* - Neither the name of IBM Corporation nor the names of its      */
22 /*   contributors may be used to endorse or promote products       */
23 /*   derived from this software without specific prior written     */
24 /*   permission.                                                   */
25 /*                                                                 */
26 /* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND          */
27 /* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,     */
28 /* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF        */
29 /* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE        */
30 /* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR            */
31 /* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,    */
32 /* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT    */
33 /* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;    */
34 /* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)        */
35 /* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN       */
36 /* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR    */
37 /* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,  */
38 /* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.              */
39 /* --------------------------------------------------------------  */
40 /* PROLOG END TAG zYx                                              */
41 #ifdef __SPU__
42 #ifndef _RECIPF4_H_
43 #define _RECIPF4_H_		1
44 
45 #include <spu_intrinsics.h>
46 
47 /*
48  * FUNCTION
49  *	vector float _recipf4(vector float value)
50  *
51  * DESCRIPTION
52  * 	The _recipf4 function inverts the vector "value" and returns the
53  *      result.
54  *
55  */
_recipf4(vector float a)56 static __inline vector float _recipf4(vector float a)
57 {
58   /* This function has been designed to provide a
59    * full function operation that presisely computes
60    * the reciprocal for the entire range of extended
61    * single precision input <a>. This includes:
62    *
63    * 1) Computing the reciprocal to full single precision
64    *    floating point accuracy.
65    * 2) Round the result consistently with the rounding
66    *    mode of the processor - truncated toward zero.
67    * 3) Underflow and overflow results are clamped to
68    *    Smin and Smax and flagged with the appropriate
69    *    UNF or OVF exception in the FPSCR.
70    * 4) Divide By Zero (DBZ) exception is produced when
71    *    the input <a> has a zero exponent. A reciprocal
72    *    of correctly signed Smax is produced.
73    * 5) Resulting denorm reciprocal will be coerced to +0.
74    * 6) If a non-compliant IEEE result is produced, the
75    *    a DIFF exception is generated.
76    */
77   vector float err, x0, x1;
78   vector float mult;
79   vector float mant_a;
80   vector float one = spu_splats(1.0f);
81   vector unsigned int exp, exp_a;
82   vector unsigned int exp_mask = (vec_uint4)spu_splats(0x7F800000);
83 
84   /* If a has a zero exponent, then set the divide by zero
85    * (DBZ) exception flag. The estimate result is discarded.
86    */
87   (void)si_frest((qword)(a));
88 
89   /* For computing the reciprocal, force the value
90    * into the range (1.0 <= 0 < 2.0).
91    */
92   mant_a = spu_sel(a, one, exp_mask);
93 
94   /* Compute the reciprocal using the reciprocal estimate
95    * followed by one iteration of the Newton-Raphson.
96    * Due to truncation error, the quotient result may be low
97    * by 1 ulp (unit of least position). Conditionally add one
98    * if the estimate is too small.
99    */
100   x0 = spu_re(mant_a);
101   x0  = spu_madd(spu_nmsub(mant_a, x0, one), x0, x0);
102 
103   x1 = (vector float)(spu_add((vector unsigned int)(x0), 1));
104   err = spu_nmsub(mant_a, x1, one);
105 
106   x1 = spu_sel(x0, x1, spu_cmpgt((vector signed int)(err), -1));
107 
108   /* Compute the reciprocal's expected exponent. If the exponent
109    * is out of range, then force the resulting exponent to 0.
110    * (127 with the bias). We correct for the out of range
111    * values by computing a multiplier (mult) that will force the
112    * result to the correct out of range value and set the
113    * correct exception flag (UNF, OVF, or neither). The multiplier
114    * is also conditioned to generate correctly signed Smax if the
115    * inoput <a> is a denorm or zero.
116    */
117   exp_a = spu_and((vector unsigned int)a, exp_mask);
118   exp   = spu_add(spu_sub(spu_splats((unsigned int)0x7F000000), exp_a), spu_cmpabsgt(mant_a, one));
119 
120   /* The default multiplier is 1.0. If an underflow is detected (ie,
121    * either the dividend <a> is a denorm/zero, or the computed exponent is
122    * less than or equal to a biased 0), force the multiplier to 0.0.
123    */
124   mult = spu_and(one, (vector float)spu_cmpgt((vector signed int)(exp), 0));
125 
126   /* Force the multiplier to positive Smax (0x7FFFFFFF) and the biased exponent
127    * to 127, if the divisor is denorm/zero or the computed biased exponent is
128    * greater than 255.
129    */
130   mult = spu_or(mult, (vector float)spu_rlmask(spu_cmpeq(exp_a, 0), -1));
131 
132   /* Insert the exponent into the result and perform the
133    * final multiplication.
134    */
135   x1    = spu_sel(x1, (vector float)exp, exp_mask);
136   x1    = spu_mul(x1, mult);
137 
138   return (x1);
139 }
140 
141 #endif /* _RECIPF4_H_ */
142 #endif /* __SPU__ */
143