1net_decl input.sv /^module net_decl;$/;" m 2a input.sv /^ trireg a;$/;" n module:net_decl 3cap1 input.sv /^ trireg (large) #(0,0,50) cap1;$/;" n module:net_decl 4cap2 input.sv /^ trireg (small) signed [3:0] cap2;$/;" n module:net_decl 5w input.sv /^ wire w = vara & varb; \/\/ net with a continuous assignment$/;" n module:net_decl 6v input.sv /^ logic v = consta & constb; \/\/ variable with initialization$/;" r module:net_decl 7vw input.sv /^ logic vw; \/\/ no initial assignment$/;" r module:net_decl 8circ input.sv /^ real circ;$/;" r module:net_decl 9top input.sv /^module top();$/;" m 10iBus input.sv /^ interconnect [0:1] iBus;$/;" n module:top 11l1 input.sv /^ lDriver l1(iBus[0]);$/;" i module:top 12r1 input.sv /^ rDriver r1(iBus[1]);$/;" i module:top 13m1 input.sv /^ rlMod m1(iBus);$/;" i module:top 14rlMod input.sv /^module rlMod(input interconnect [0:1] iBus);$/;" m 15iBus input.sv /^module rlMod(input interconnect [0:1] iBus);$/;" p module:rlMod 16l1 input.sv /^ lMod l1(iBus[0]);$/;" i module:rlMod 17r1 input.sv /^ rMod r1(iBus[1]);$/;" i module:rlMod 18Net_declarations input.sv /^module Net_declarations;$/;" m 19cap1 input.sv /^ trireg (large) logic #(0,0,0) cap1;$/;" n module:Net_declarations 20addressT input.sv /^ typedef logic [31:0] addressT;$/;" T module:Net_declarations 21w1 input.sv /^ wire addressT w1;$/;" n module:Net_declarations 22memsig input.sv /^ wire struct packed { logic ecc; logic [7:0] data; } memsig;$/;" n module:Net_declarations 23w input.sv /^ wire w; \/\/ equivalent to "wire logic w;"$/;" n module:Net_declarations 24w input.sv /^ wire logic w;$/;" n module:Net_declarations 25ww input.sv /^ wire [15:0] ww; \/\/ equivalent to "wire logic [15:0] ww;"$/;" n module:Net_declarations 26ww input.sv /^ wire logic [15:0] ww;$/;" n module:Net_declarations 27w1 input.sv /^ interconnect w1; \/\/ legal$/;" n module:Net_declarations 28w2 input.sv /^ interconnect [3:0] w2; \/\/ legal$/;" n module:Net_declarations 29w3 input.sv /^ interconnect [3:0] w3 [1:0]; \/\/ legal$/;" n module:Net_declarations 30wT input.sv /^ nettype T wT;$/;" N module:Net_declarations 31wTsum input.sv /^ nettype T wTsum with Tsum;$/;" N module:Net_declarations 32w1 input.sv /^ wT w1;$/;" r module:Net_declarations 33w2 input.sv /^ wT w2[8];$/;" r module:Net_declarations 34w3 input.sv /^ wTsum w3;$/;" r module:Net_declarations 35w4 input.sv /^ wTsum w4[8];$/;" r module:Net_declarations 36TR input.sv /^ typedef real TR[5];$/;" T module:Net_declarations 37wTR input.sv /^ nettype TR wTR;$/;" N module:Net_declarations 38w5 input.sv /^ wTR w5;$/;" r module:Net_declarations 39w6 input.sv /^ wTR w6[8];$/;" r module:Net_declarations 40Variable_declarations input.sv /^module Variable_declarations;$/;" m 41s1 input.sv /^ shortint s1, s2[0:9];$/;" r module:Variable_declarations 42s2 input.sv /^ shortint s1, s2[0:9];$/;" r module:Variable_declarations 43v input.sv /^ var v; \/\/ equivalent to "var logic v;"$/;" r module:Variable_declarations 44vw input.sv /^ var [15:0] vw; \/\/ equivalent to "var logic [15:0] vw;"$/;" r module:Variable_declarations 45status input.sv /^ var enum bit { clear, error } status;$/;" r module:Variable_declarations 46data_in input.sv /^ input var logic data_in;$/;" p module:Variable_declarations 47r input.sv /^ var reg r;$/;" r module:Variable_declarations 48i input.sv /^ int i = 0;$/;" r module:Variable_declarations 49Vector_declarations input.sv /^module Vector_declarations;$/;" m 50w input.sv /^ wand w; \/\/ a scalar "wand" net$/;" n module:Vector_declarations 51busa input.sv /^ tri [15:0] busa; \/\/ a 16-bit bus$/;" n module:Vector_declarations 52storeit input.sv /^ trireg (small) storeit; \/\/ a charge storage node of strength small$/;" n module:Vector_declarations 53a input.sv /^ logic a; \/\/ a scalar variable$/;" r module:Vector_declarations 54v input.sv /^ logic[3:0] v; \/\/ a 4-bit vector made up of (from most to$/;" r module:Vector_declarations 55signed_reg input.sv /^ logic signed [3:0] signed_reg; \/\/ a 4-bit vector in range -8 to 7$/;" r module:Vector_declarations 56b input.sv /^ logic [-1:4] b; \/\/ a 6-bit vector$/;" r module:Vector_declarations 57w1 input.sv /^ wire w1, w2; \/\/ declares two nets$/;" n module:Vector_declarations 58w2 input.sv /^ wire w1, w2; \/\/ declares two nets$/;" n module:Vector_declarations 59x input.sv /^ logic [4:0] x, y, z; \/\/ declares three 5-bit variables$/;" r module:Vector_declarations 60y input.sv /^ logic [4:0] x, y, z; \/\/ declares three 5-bit variables$/;" r module:Vector_declarations 61z input.sv /^ logic [4:0] x, y, z; \/\/ declares three 5-bit variables$/;" r module:Vector_declarations 62bus64 input.sv /^ tri1 scalared [63:0] bus64; \/\/a bus that will be expanded$/;" n module:Vector_declarations 63data input.sv /^ tri vectored [31:0] data; \/\/a bus that may or may not be expanded$/;" n module:Vector_declarations 64String_data_type input.sv /^module String_data_type;$/;" m 65default_name input.sv /^ parameter string default_name = "John Smith";$/;" c module:String_data_type 66myName input.sv /^ string myName = default_name;$/;" r module:String_data_type 67c input.sv /^ byte c = "A"; \/\/ assigns to c "A"$/;" r module:String_data_type 68b input.sv /^ bit [10:0] b = "\\x41"; \/\/ assigns to b 'b000_0100_0001$/;" r module:String_data_type 69h input.sv /^ bit [1:4][7:0] h = "hello" ; \/\/ assigns to h "ello"$/;" r module:String_data_type 70s0 input.sv /^ string s0 = "String literal assign";\/\/ sets s0 to "String literal assign"$/;" r module:String_data_type 71s1 input.sv /^ string s1 = "hello\\0world"; \/\/ sets s1 to "helloworld"$/;" r module:String_data_type 72b input.sv /^ bit [11:0] b = 12'ha41;$/;" r module:String_data_type 73s2 input.sv /^ string s2 = string'(b); \/\/ sets s2 to 16'h0a41$/;" r module:String_data_type 74r_t input.sv /^ typedef logic [15:0] r_t;$/;" T module:String_data_type 75r input.sv /^ r_t r;$/;" r module:String_data_type 76i input.sv /^ integer i = 1;$/;" r module:String_data_type 77b input.sv /^ string b = "";$/;" r module:String_data_type 78a input.sv /^ string a = {"Hi", b};$/;" r module:String_data_type 79event_data_type input.sv /^module event_data_type;$/;" m 80done input.sv /^ event done; \/\/ declare a new event called done$/;" e module:event_data_type 81done_too input.sv /^ event done_too = done; \/\/ declare done_too as alias to done$/;" e module:event_data_type 82empty input.sv /^ event empty = null; \/\/ event variable with no synchronization object$/;" e module:event_data_type 83user_define_types_0 input.sv /^module user_define_types_0;$/;" m 84intP input.sv /^ typedef int intP;$/;" T module:user_define_types_0 85a input.sv /^ intP a, b;$/;" r module:user_define_types_0 86b input.sv /^ intP a, b;$/;" r module:user_define_types_0 87intf_i input.sv /^interface intf_i;$/;" I 88data_t input.sv /^ typedef int data_t;$/;" T interface:intf_i 89sub input.sv /^module sub(intf_i p);$/;" m 90p input.sv /^module sub(intf_i p);$/;" p module:sub 91my_data_t input.sv /^ typedef p.data_t my_data_t;$/;" T module:sub 92data input.sv /^ my_data_t data;$/;" r module:sub 93cbs input.sv /^module cbs;$/;" m 94cbs_t input.sv /^ typedef p[10].data_t cbs_t;$/;" T module:cbs 95user_define_types_1 input.sv /^module user_define_types_1;$/;" m 96enum_test input.sv /^module enum_test;$/;" m 97light1 input.sv /^ enum {red, yellow, green} light1, light2; \/\/ anonymous int type$/;" E module:enum_test 98red input.sv /^ enum {red, yellow, green} light1, light2; \/\/ anonymous int type$/;" c enum:enum_test.light1 99yellow input.sv /^ enum {red, yellow, green} light1, light2; \/\/ anonymous int type$/;" c enum:enum_test.light1 100green input.sv /^ enum {red, yellow, green} light1, light2; \/\/ anonymous int type$/;" c enum:enum_test.light1 101light2 input.sv /^ enum {red, yellow, green} light1, light2; \/\/ anonymous int type$/;" E module:enum_test 102red input.sv /^ enum {red, yellow, green} light1, light2; \/\/ anonymous int type$/;" c enum:enum_test.light2 103yellow input.sv /^ enum {red, yellow, green} light1, light2; \/\/ anonymous int type$/;" c enum:enum_test.light2 104green input.sv /^ enum {red, yellow, green} light1, light2; \/\/ anonymous int type$/;" c enum:enum_test.light2 105state input.sv /^ enum integer {IDLE, XX='x, S1='b01, S2='b10} state, next;$/;" E module:enum_test 106IDLE input.sv /^ enum integer {IDLE, XX='x, S1='b01, S2='b10} state, next;$/;" c enum:enum_test.state 107XX input.sv /^ enum integer {IDLE, XX='x, S1='b01, S2='b10} state, next;$/;" c enum:enum_test.state 108S1 input.sv /^ enum integer {IDLE, XX='x, S1='b01, S2='b10} state, next;$/;" c enum:enum_test.state 109S2 input.sv /^ enum integer {IDLE, XX='x, S1='b01, S2='b10} state, next;$/;" c enum:enum_test.state 110next input.sv /^ enum integer {IDLE, XX='x, S1='b01, S2='b10} state, next;$/;" E module:enum_test 111IDLE input.sv /^ enum integer {IDLE, XX='x, S1='b01, S2='b10} state, next;$/;" c enum:enum_test.next 112XX input.sv /^ enum integer {IDLE, XX='x, S1='b01, S2='b10} state, next;$/;" c enum:enum_test.next 113S1 input.sv /^ enum integer {IDLE, XX='x, S1='b01, S2='b10} state, next;$/;" c enum:enum_test.next 114S2 input.sv /^ enum integer {IDLE, XX='x, S1='b01, S2='b10} state, next;$/;" c enum:enum_test.next 115medal input.sv /^ enum {bronze=3, silver, gold} medal; \/\/ silver=4, gold=5$/;" E module:enum_test 116bronze input.sv /^ enum {bronze=3, silver, gold} medal; \/\/ silver=4, gold=5$/;" c enum:enum_test.medal 117silver input.sv /^ enum {bronze=3, silver, gold} medal; \/\/ silver=4, gold=5$/;" c enum:enum_test.medal 118gold input.sv /^ enum {bronze=3, silver, gold} medal; \/\/ silver=4, gold=5$/;" c enum:enum_test.medal 119medal2 input.sv /^ enum bit [3:0] {bronze='h3, silver, gold='h5} medal2;$/;" E module:enum_test 120bronze input.sv /^ enum bit [3:0] {bronze='h3, silver, gold='h5} medal2;$/;" c enum:enum_test.medal2 121silver input.sv /^ enum bit [3:0] {bronze='h3, silver, gold='h5} medal2;$/;" c enum:enum_test.medal2 122gold input.sv /^ enum bit [3:0] {bronze='h3, silver, gold='h5} medal2;$/;" c enum:enum_test.medal2 123medal3 input.sv /^ enum bit [3:0] {bronze=4'h3, silver, gold=4'h5} medal3;$/;" E module:enum_test 124bronze input.sv /^ enum bit [3:0] {bronze=4'h3, silver, gold=4'h5} medal3;$/;" c enum:enum_test.medal3 125silver input.sv /^ enum bit [3:0] {bronze=4'h3, silver, gold=4'h5} medal3;$/;" c enum:enum_test.medal3 126gold input.sv /^ enum bit [3:0] {bronze=4'h3, silver, gold=4'h5} medal3;$/;" c enum:enum_test.medal3 127boolean input.sv /^ typedef enum {NO, YES} boolean;$/;" T module:enum_test 128NO input.sv /^ typedef enum {NO, YES} boolean;$/;" c typedef:enum_test.boolean 129YES input.sv /^ typedef enum {NO, YES} boolean;$/;" c typedef:enum_test.boolean 130myvar input.sv /^ boolean myvar; \/\/ named type$/;" r module:enum_test 131E1 input.sv /^ typedef enum { add=10, sub[5], jmp[6:8] } E1; \/\/ FIXME$/;" T module:enum_test 132add input.sv /^ typedef enum { add=10, sub[5], jmp[6:8] } E1; \/\/ FIXME$/;" c typedef:enum_test.E1 133sub input.sv /^ typedef enum { add=10, sub[5], jmp[6:8] } E1; \/\/ FIXME$/;" c typedef:enum_test.E1 134jmp input.sv /^ typedef enum { add=10, sub[5], jmp[6:8] } E1; \/\/ FIXME$/;" c typedef:enum_test.E1 135vr input.sv /^ enum { register[2] = 1, register[2:4] = 10 } vr; \/\/ FIXME$/;" E module:enum_test 136register input.sv /^ enum { register[2] = 1, register[2:4] = 10 } vr; \/\/ FIXME$/;" c enum:enum_test.vr 137register input.sv /^ enum { register[2] = 1, register[2:4] = 10 } vr; \/\/ FIXME$/;" c enum:enum_test.vr 138cmplx_enum1 input.sv /^ enum logic signed [3:0] { foo, bar } [1:0] cmplx_enum1; $/;" E module:enum_test 139foo input.sv /^ enum logic signed [3:0] { foo, bar } [1:0] cmplx_enum1; $/;" c enum:enum_test.cmplx_enum1 140bar input.sv /^ enum logic signed [3:0] { foo, bar } [1:0] cmplx_enum1; $/;" c enum:enum_test.cmplx_enum1 141cmplx_enum2 input.sv /^ enum logic unsigned [3:0] { foo, bar } [] cmplx_enum2; $/;" E module:enum_test 142foo input.sv /^ enum logic unsigned [3:0] { foo, bar } [] cmplx_enum2; $/;" c enum:enum_test.cmplx_enum2 143bar input.sv /^ enum logic unsigned [3:0] { foo, bar } [] cmplx_enum2; $/;" c enum:enum_test.cmplx_enum2 144delay_control input.sv /^module delay_control #(d, e);$/;" m 145d input.sv /^module delay_control #(d, e);$/;" c module:delay_control 146e input.sv /^module delay_control #(d, e);$/;" c module:delay_control 147rega input.sv /^ int rega, regb, regr;$/;" r module:delay_control 148regb input.sv /^ int rega, regb, regr;$/;" r module:delay_control 149regr input.sv /^ int rega, regb, regr;$/;" r module:delay_control 150delay_control_wire input.sv /^module delay_control_wire #(d, e);$/;" m 151d input.sv /^module delay_control_wire #(d, e);$/;" c module:delay_control_wire 152e input.sv /^module delay_control_wire #(d, e);$/;" c module:delay_control_wire 153wirea input.sv /^ wire wirea #10 = wireb;$/;" n module:delay_control_wire 154wireb input.sv /^ wire wireb #d = wireb;$/;" n module:delay_control_wire 155wirec input.sv /^ wire wirec #((d+e)\/2) = wireb;$/;" n module:delay_control_wire 156wired input.sv /^ wire wired #wirer = wirer + 1;$/;" n module:delay_control_wire 157w$ire input.sv /^ wire w$ire, wire$; \/\/ '$' included$/;" n module:delay_control_wire 158wire$ input.sv /^ wire w$ire, wire$; \/\/ '$' included$/;" n module:delay_control_wire 159rst input.sv /^module rst;$/;" m 160trst_n input.sv /^ logic trst_n;$/;" r module:rst 161