1//===- MipsEVAInstrInfo.td - EVA ASE instructions -*- tablegen ------------*-=// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file describes Mips EVA ASE instructions. 10// 11//===----------------------------------------------------------------------===// 12 13//===----------------------------------------------------------------------===// 14// 15// Instruction encodings 16// 17//===----------------------------------------------------------------------===// 18 19// Memory Load/Store EVA encodings 20class LBE_ENC : SPECIAL3_EVA_LOAD_STORE_FM<OPCODE6_LBE>; 21class LBuE_ENC : SPECIAL3_EVA_LOAD_STORE_FM<OPCODE6_LBuE>; 22class LHE_ENC : SPECIAL3_EVA_LOAD_STORE_FM<OPCODE6_LHE>; 23class LHuE_ENC : SPECIAL3_EVA_LOAD_STORE_FM<OPCODE6_LHuE>; 24class LWE_ENC : SPECIAL3_EVA_LOAD_STORE_FM<OPCODE6_LWE>; 25 26class SBE_ENC : SPECIAL3_EVA_LOAD_STORE_FM<OPCODE6_SBE>; 27class SHE_ENC : SPECIAL3_EVA_LOAD_STORE_FM<OPCODE6_SHE>; 28class SWE_ENC : SPECIAL3_EVA_LOAD_STORE_FM<OPCODE6_SWE>; 29 30// load/store left/right EVA encodings 31class LWLE_ENC : SPECIAL3_EVA_LOAD_STORE_FM<OPCODE6_LWLE>; 32class LWRE_ENC : SPECIAL3_EVA_LOAD_STORE_FM<OPCODE6_LWRE>; 33class SWLE_ENC : SPECIAL3_EVA_LOAD_STORE_FM<OPCODE6_SWLE>; 34class SWRE_ENC : SPECIAL3_EVA_LOAD_STORE_FM<OPCODE6_SWRE>; 35 36// Load-linked EVA, Store-conditional EVA encodings 37class LLE_ENC : SPECIAL3_EVA_LOAD_STORE_FM<OPCODE6_LLE>; 38class SCE_ENC : SPECIAL3_EVA_LOAD_STORE_FM<OPCODE6_SCE>; 39 40class TLBINV_ENC : TLB_FM<OPCODE6_TLBINV>; 41class TLBINVF_ENC : TLB_FM<OPCODE6_TLBINVF>; 42 43class CACHEE_ENC : SPECIAL3_EVA_LOAD_STORE_FM<OPCODE6_CACHEE>; 44class PREFE_ENC : SPECIAL3_EVA_LOAD_STORE_FM<OPCODE6_PREFE>; 45 46//===----------------------------------------------------------------------===// 47// 48// Instruction descriptions 49// 50//===----------------------------------------------------------------------===// 51 52// Memory Load/Store EVA descriptions 53class LOAD_EVA_DESC_BASE<string instr_asm, RegisterOperand GPROpnd, 54 InstrItinClass itin = NoItinerary> { 55 dag OutOperandList = (outs GPROpnd:$rt); 56 dag InOperandList = (ins mem_simm9:$addr); 57 string AsmString = !strconcat(instr_asm, "\t$rt, $addr"); 58 list<dag> Pattern = []; 59 string DecoderMethod = "DecodeMemEVA"; 60 bit canFoldAsLoad = 1; 61 string BaseOpcode = instr_asm; 62 bit mayLoad = 1; 63 InstrItinClass Itinerary = itin; 64} 65 66class LBE_DESC : LOAD_EVA_DESC_BASE<"lbe", GPR32Opnd, II_LBE>; 67class LBuE_DESC : LOAD_EVA_DESC_BASE<"lbue", GPR32Opnd, II_LBUE>; 68class LHE_DESC : LOAD_EVA_DESC_BASE<"lhe", GPR32Opnd, II_LHE>; 69class LHuE_DESC : LOAD_EVA_DESC_BASE<"lhue", GPR32Opnd, II_LHUE>; 70class LWE_DESC : LOAD_EVA_DESC_BASE<"lwe", GPR32Opnd, II_LWE>; 71 72class STORE_EVA_DESC_BASE<string instr_asm, RegisterOperand GPROpnd, 73 SDPatternOperator OpNode = null_frag, 74 InstrItinClass itin = NoItinerary> { 75 dag OutOperandList = (outs); 76 dag InOperandList = (ins GPROpnd:$rt, mem_simm9:$addr); 77 string AsmString = !strconcat(instr_asm, "\t$rt, $addr"); 78 list<dag> Pattern = []; 79 string DecoderMethod = "DecodeMemEVA"; 80 string BaseOpcode = instr_asm; 81 bit mayStore = 1; 82 InstrItinClass Itinerary = itin; 83} 84 85class SBE_DESC : STORE_EVA_DESC_BASE<"sbe", GPR32Opnd, null_frag, II_SBE>; 86class SHE_DESC : STORE_EVA_DESC_BASE<"she", GPR32Opnd, null_frag, II_SHE>; 87class SWE_DESC : STORE_EVA_DESC_BASE<"swe", GPR32Opnd, null_frag, II_SWE>; 88 89// Load/Store Left/Right EVA descriptions 90class LOAD_LEFT_RIGHT_EVA_DESC_BASE<string instr_asm, RegisterOperand GPROpnd, 91 InstrItinClass itin = NoItinerary> { 92 dag OutOperandList = (outs GPROpnd:$rt); 93 dag InOperandList = (ins mem_simm9:$addr, GPROpnd:$src); 94 string AsmString = !strconcat(instr_asm, "\t$rt, $addr"); 95 list<dag> Pattern = []; 96 string DecoderMethod = "DecodeMemEVA"; 97 string BaseOpcode = instr_asm; 98 string Constraints = "$src = $rt"; 99 bit canFoldAsLoad = 1; 100 InstrItinClass Itinerary = itin; 101 bit mayLoad = 1; 102 bit mayStore = 0; 103} 104 105class LWLE_DESC : LOAD_LEFT_RIGHT_EVA_DESC_BASE<"lwle", GPR32Opnd, II_LWLE>; 106class LWRE_DESC : LOAD_LEFT_RIGHT_EVA_DESC_BASE<"lwre", GPR32Opnd, II_LWRE>; 107 108class STORE_LEFT_RIGHT_EVA_DESC_BASE<string instr_asm, RegisterOperand GPROpnd, 109 InstrItinClass itin = NoItinerary> { 110 dag OutOperandList = (outs); 111 dag InOperandList = (ins GPROpnd:$rt, mem_simm9:$addr); 112 string AsmString = !strconcat(instr_asm, "\t$rt, $addr"); 113 list<dag> Pattern = []; 114 string DecoderMethod = "DecodeMemEVA"; 115 string BaseOpcode = instr_asm; 116 InstrItinClass Itinerary = itin; 117 bit mayLoad = 0; 118 bit mayStore = 1; 119} 120 121class SWLE_DESC : STORE_LEFT_RIGHT_EVA_DESC_BASE<"swle", GPR32Opnd, II_SWLE>; 122class SWRE_DESC : STORE_LEFT_RIGHT_EVA_DESC_BASE<"swre", GPR32Opnd, II_SWRE>; 123 124// Load-linked EVA, Store-conditional EVA descriptions 125class LLE_DESC_BASE<string instr_asm, RegisterOperand GPROpnd, 126 InstrItinClass itin = NoItinerary> { 127 dag OutOperandList = (outs GPROpnd:$rt); 128 dag InOperandList = (ins mem_simm9:$addr); 129 string AsmString = !strconcat(instr_asm, "\t$rt, $addr"); 130 list<dag> Pattern = []; 131 string BaseOpcode = instr_asm; 132 bit mayLoad = 1; 133 string DecoderMethod = "DecodeMemEVA"; 134 InstrItinClass Itinerary = itin; 135} 136 137class LLE_DESC : LLE_DESC_BASE<"lle", GPR32Opnd, II_LLE>; 138 139class SCE_DESC_BASE<string instr_asm, RegisterOperand GPROpnd, 140 InstrItinClass itin = NoItinerary> { 141 dag OutOperandList = (outs GPROpnd:$dst); 142 dag InOperandList = (ins GPROpnd:$rt, mem_simm9:$addr); 143 string AsmString = !strconcat(instr_asm, "\t$rt, $addr"); 144 list<dag> Pattern = []; 145 string BaseOpcode = instr_asm; 146 bit mayStore = 1; 147 string Constraints = "$rt = $dst"; 148 string DecoderMethod = "DecodeMemEVA"; 149 InstrItinClass Itinerary = itin; 150} 151 152class SCE_DESC : SCE_DESC_BASE<"sce", GPR32Opnd, II_SCE>; 153 154class TLB_DESC_BASE<string instr_asm, InstrItinClass itin = NoItinerary> { 155 dag OutOperandList = (outs); 156 dag InOperandList = (ins); 157 string AsmString = instr_asm; 158 list<dag> Pattern = []; 159 InstrItinClass Itinerary = itin; 160} 161 162class TLBINV_DESC : TLB_DESC_BASE<"tlbinv", II_TLBINV>; 163class TLBINVF_DESC : TLB_DESC_BASE<"tlbinvf", II_TLBINVF>; 164 165class CACHEE_DESC_BASE<string instr_asm, Operand MemOpnd, 166 InstrItinClass itin = NoItinerary> { 167 dag OutOperandList = (outs); 168 dag InOperandList = (ins MemOpnd:$addr, uimm5:$hint); 169 string AsmString = !strconcat(instr_asm, "\t$hint, $addr"); 170 list<dag> Pattern = []; 171 string BaseOpcode = instr_asm; 172 string DecoderMethod = "DecodeCacheeOp_CacheOpR6"; 173 InstrItinClass Itinerary = itin; 174} 175 176class CACHEE_DESC : CACHEE_DESC_BASE<"cachee", mem_simm9, II_CACHEE>; 177class PREFE_DESC : CACHEE_DESC_BASE<"prefe", mem_simm9, II_PREFE>; 178 179//===----------------------------------------------------------------------===// 180// 181// Instruction definitions 182// 183//===----------------------------------------------------------------------===// 184 185let AdditionalPredicates = [NotInMicroMips] in { 186 /// Load and Store EVA Instructions 187 def LBE : MMRel, LBE_ENC, LBE_DESC, ISA_MIPS32R2, ASE_EVA; 188 def LBuE : MMRel, LBuE_ENC, LBuE_DESC, ISA_MIPS32R2, ASE_EVA; 189 def LHE : MMRel, LHE_ENC, LHE_DESC, ISA_MIPS32R2, ASE_EVA; 190 def LHuE : MMRel, LHuE_ENC, LHuE_DESC, ISA_MIPS32R2, ASE_EVA; 191 def LWE : MMRel, LWE_ENC, LWE_DESC, ISA_MIPS32R2, ASE_EVA; 192 def SBE : MMRel, SBE_ENC, SBE_DESC, ISA_MIPS32R2, ASE_EVA; 193 def SHE : MMRel, SHE_ENC, SHE_DESC, ISA_MIPS32R2, ASE_EVA; 194 def SWE : MMRel, SWE_ENC, SWE_DESC, ISA_MIPS32R2, ASE_EVA; 195 196 /// load/store left/right EVA 197 def LWLE : MMRel, LWLE_ENC, LWLE_DESC, ISA_MIPS32R2_NOT_32R6_64R6, ASE_EVA; 198 def LWRE : MMRel, LWRE_ENC, LWRE_DESC, ISA_MIPS32R2_NOT_32R6_64R6, ASE_EVA; 199 def SWLE : MMRel, SWLE_ENC, SWLE_DESC, ISA_MIPS32R2_NOT_32R6_64R6, ASE_EVA; 200 def SWRE : MMRel, SWRE_ENC, SWRE_DESC, ISA_MIPS32R2_NOT_32R6_64R6, ASE_EVA; 201 202 /// Load-linked EVA, Store-conditional EVA 203 def LLE : MMRel, LLE_ENC, LLE_DESC, ISA_MIPS32R2, ASE_EVA; 204 def SCE : MMRel, SCE_ENC, SCE_DESC, ISA_MIPS32R2, ASE_EVA; 205 206 /// TLB invalidate instructions 207 def TLBINV : TLBINV_ENC, TLBINV_DESC, ISA_MIPS32R2, ASE_EVA; 208 def TLBINVF : TLBINVF_ENC, TLBINVF_DESC, ISA_MIPS32R2, ASE_EVA; 209 210 /// EVA versions of cache and pref 211 def CACHEE : MMRel, CACHEE_ENC, CACHEE_DESC, ISA_MIPS32R2, ASE_EVA; 212 def PREFE : MMRel, PREFE_ENC, PREFE_DESC, ISA_MIPS32R2, ASE_EVA; 213} 214