1// Mask immediates for MMA instructions (2, 4 and 8 bits). 2def Msk2Imm : ImmLeaf<i32, [{ return isUInt<2>(Imm); }]>; 3def Msk4Imm : ImmLeaf<i32, [{ return isUInt<4>(Imm); }]>; 4def Msk8Imm : ImmLeaf<i32, [{ return isUInt<8>(Imm); }]>; 5 6//===----------------------------------------------------------------------===// 7// PowerPC ISA 3.1 specific type constraints. 8// 9 10def SDT_PPCSplat32 : SDTypeProfile<1, 3, [ SDTCisVT<0, v2i64>, 11 SDTCisVec<1>, SDTCisInt<2>, SDTCisInt<3> 12]>; 13def SDT_PPCAccBuild : SDTypeProfile<1, 4, [ 14 SDTCisVT<0, v512i1>, SDTCisVT<1, v4i32>, SDTCisVT<2, v4i32>, 15 SDTCisVT<3, v4i32>, SDTCisVT<4, v4i32> 16]>; 17def SDT_PPCPairBuild : SDTypeProfile<1, 2, [ 18 SDTCisVT<0, v256i1>, SDTCisVT<1, v4i32>, SDTCisVT<2, v4i32> 19]>; 20def SDT_PPCAccExtractVsx : SDTypeProfile<1, 2, [ 21 SDTCisVT<0, v4i32>, SDTCisVT<1, v512i1>, SDTCisInt<2> 22]>; 23def SDT_PPCPairExtractVsx : SDTypeProfile<1, 2, [ 24 SDTCisVT<0, v4i32>, SDTCisVT<1, v256i1>, SDTCisInt<2> 25]>; 26def SDT_PPCxxmfacc : SDTypeProfile<1, 1, [ 27 SDTCisVT<0, v512i1>, SDTCisVT<1, v512i1> 28]>; 29 30//===----------------------------------------------------------------------===// 31// ISA 3.1 specific PPCISD nodes. 32// 33 34def PPCxxsplti32dx : SDNode<"PPCISD::XXSPLTI32DX", SDT_PPCSplat32, []>; 35def PPCAccBuild : SDNode<"PPCISD::ACC_BUILD", SDT_PPCAccBuild, []>; 36def PPCPairBuild : SDNode<"PPCISD::PAIR_BUILD", SDT_PPCPairBuild, []>; 37def PPCAccExtractVsx : SDNode<"PPCISD::EXTRACT_VSX_REG", SDT_PPCAccExtractVsx, 38 []>; 39def PPCPairExtractVsx : SDNode<"PPCISD::EXTRACT_VSX_REG", SDT_PPCPairExtractVsx, 40 []>; 41def PPCxxmfacc : SDNode<"PPCISD::XXMFACC", SDT_PPCxxmfacc, []>; 42 43//===----------------------------------------------------------------------===// 44 45// PC Relative flag (for instructions that use the address of the prefix for 46// address computations). 47class isPCRel { bit PCRel = 1; } 48 49// PowerPC specific type constraints. 50def SDT_PPCLXVRZX : SDTypeProfile<1, 2, [ 51 SDTCisVT<0, v1i128>, SDTCisPtrTy<1>, SDTCisPtrTy<2> 52]>; 53 54// PPC Specific DAG Nodes. 55def PPClxvrzx : SDNode<"PPCISD::LXVRZX", SDT_PPCLXVRZX, 56 [SDNPHasChain, SDNPMayLoad]>; 57 58// Top-level class for prefixed instructions. 59class PI<bits<6> pref, bits<6> opcode, dag OOL, dag IOL, string asmstr, 60 InstrItinClass itin> : Instruction { 61 field bits<64> Inst; 62 field bits<64> SoftFail = 0; 63 bit PCRel = 0; // Default value, set by isPCRel. 64 let Size = 8; 65 66 let Namespace = "PPC"; 67 let OutOperandList = OOL; 68 let InOperandList = IOL; 69 let AsmString = asmstr; 70 let Itinerary = itin; 71 let Inst{0-5} = pref; 72 let Inst{32-37} = opcode; 73 74 bits<1> PPC970_First = 0; 75 bits<1> PPC970_Single = 0; 76 bits<1> PPC970_Cracked = 0; 77 bits<3> PPC970_Unit = 0; 78 79 /// These fields correspond to the fields in PPCInstrInfo.h. Any changes to 80 /// these must be reflected there! See comments there for what these are. 81 let TSFlags{0} = PPC970_First; 82 let TSFlags{1} = PPC970_Single; 83 let TSFlags{2} = PPC970_Cracked; 84 let TSFlags{5-3} = PPC970_Unit; 85 86 bits<1> Prefixed = 1; // This is a prefixed instruction. 87 let TSFlags{7} = Prefixed; 88 89 // For cases where multiple instruction definitions really represent the 90 // same underlying instruction but with one definition for 64-bit arguments 91 // and one for 32-bit arguments, this bit breaks the degeneracy between 92 // the two forms and allows TableGen to generate mapping tables. 93 bit Interpretation64Bit = 0; 94 95 // Fields used for relation models. 96 string BaseName = ""; 97} 98 99// VX-Form: [ PO VT R VB RC XO ] 100class VXForm_VTB5_RC<bits<10> xo, bits<5> R, dag OOL, dag IOL, string asmstr, 101 InstrItinClass itin, list<dag> pattern> 102 : I<4, OOL, IOL, asmstr, itin> { 103 bits<5> VT; 104 bits<5> VB; 105 bit RC = 0; 106 107 let Pattern = pattern; 108 109 let Inst{6-10} = VT; 110 let Inst{11-15} = R; 111 let Inst{16-20} = VB; 112 let Inst{21} = RC; 113 let Inst{22-31} = xo; 114} 115 116// Multiclass definition to account for record and non-record form 117// instructions of VXRForm. 118multiclass VXForm_VTB5_RCr<bits<10> xo, bits<5> R, dag OOL, dag IOL, 119 string asmbase, string asmstr, 120 InstrItinClass itin, list<dag> pattern> { 121 let BaseName = asmbase in { 122 def NAME : VXForm_VTB5_RC<xo, R, OOL, IOL, 123 !strconcat(asmbase, !strconcat(" ", asmstr)), 124 itin, pattern>, RecFormRel; 125 let Defs = [CR6] in 126 def _rec : VXForm_VTB5_RC<xo, R, OOL, IOL, 127 !strconcat(asmbase, !strconcat(". ", asmstr)), 128 itin, []>, isRecordForm, RecFormRel; 129 } 130} 131 132class MLS_DForm_R_SI34_RTA5_MEM<bits<6> opcode, dag OOL, dag IOL, string asmstr, 133 InstrItinClass itin, list<dag> pattern> 134 : PI<1, opcode, OOL, IOL, asmstr, itin> { 135 bits<5> FRS; 136 bits<39> D_RA; 137 138 let Pattern = pattern; 139 140 // The prefix. 141 let Inst{6-7} = 2; 142 let Inst{8-10} = 0; 143 let Inst{11} = PCRel; 144 let Inst{12-13} = 0; 145 let Inst{14-31} = D_RA{33-16}; // d0 146 147 // The instruction. 148 let Inst{38-42} = FRS{4-0}; 149 let Inst{43-47} = D_RA{38-34}; // RA 150 let Inst{48-63} = D_RA{15-0}; // d1 151} 152 153class MLS_DForm_R_SI34_RTA5<bits<6> opcode, dag OOL, dag IOL, string asmstr, 154 InstrItinClass itin, list<dag> pattern> 155 : PI<1, opcode, OOL, IOL, asmstr, itin> { 156 bits<5> RT; 157 bits<5> RA; 158 bits<34> SI; 159 160 let Pattern = pattern; 161 162 // The prefix. 163 let Inst{6-7} = 2; 164 let Inst{8-10} = 0; 165 let Inst{11} = PCRel; 166 let Inst{12-13} = 0; 167 let Inst{14-31} = SI{33-16}; 168 169 // The instruction. 170 let Inst{38-42} = RT; 171 let Inst{43-47} = RA; 172 let Inst{48-63} = SI{15-0}; 173} 174 175class MLS_DForm_SI34_RT5<bits<6> opcode, dag OOL, dag IOL, string asmstr, 176 InstrItinClass itin, list<dag> pattern> 177 : PI<1, opcode, OOL, IOL, asmstr, itin> { 178 bits<5> RT; 179 bits<34> SI; 180 181 let Pattern = pattern; 182 183 // The prefix. 184 let Inst{6-7} = 2; 185 let Inst{8-10} = 0; 186 let Inst{11} = 0; 187 let Inst{12-13} = 0; 188 let Inst{14-31} = SI{33-16}; 189 190 // The instruction. 191 let Inst{38-42} = RT; 192 let Inst{43-47} = 0; 193 let Inst{48-63} = SI{15-0}; 194} 195 196multiclass MLS_DForm_R_SI34_RTA5_p<bits<6> opcode, dag OOL, dag IOL, 197 dag PCRel_IOL, string asmstr, 198 InstrItinClass itin> { 199 def NAME : MLS_DForm_R_SI34_RTA5<opcode, OOL, IOL, 200 !strconcat(asmstr, ", 0"), itin, []>; 201 def pc : MLS_DForm_R_SI34_RTA5<opcode, OOL, PCRel_IOL, 202 !strconcat(asmstr, ", 1"), itin, []>, isPCRel; 203} 204 205class 8LS_DForm_R_SI34_RTA5<bits<6> opcode, dag OOL, dag IOL, string asmstr, 206 InstrItinClass itin, list<dag> pattern> 207 : PI<1, opcode, OOL, IOL, asmstr, itin> { 208 bits<5> RT; 209 bits<39> D_RA; 210 211 let Pattern = pattern; 212 213 // The prefix. 214 let Inst{6-10} = 0; 215 let Inst{11} = PCRel; 216 let Inst{12-13} = 0; 217 let Inst{14-31} = D_RA{33-16}; // d0 218 219 // The instruction. 220 let Inst{38-42} = RT{4-0}; 221 let Inst{43-47} = D_RA{38-34}; // RA 222 let Inst{48-63} = D_RA{15-0}; // d1 223} 224 225// 8LS:D-Form: [ 1 0 0 // R // d0 226// PO TX T RA d1 ] 227class 8LS_DForm_R_SI34_XT6_RA5<bits<5> opcode, dag OOL, dag IOL, string asmstr, 228 InstrItinClass itin, list<dag> pattern> 229 : PI<1, { opcode, ? }, OOL, IOL, asmstr, itin> { 230 bits<6> XT; 231 bits<39> D_RA; 232 233 let Pattern = pattern; 234 235 // The prefix. 236 let Inst{6-7} = 0; 237 let Inst{8} = 0; 238 let Inst{9-10} = 0; // reserved 239 let Inst{11} = PCRel; 240 let Inst{12-13} = 0; // reserved 241 let Inst{14-31} = D_RA{33-16}; // d0 242 243 // The instruction. 244 let Inst{37} = XT{5}; 245 let Inst{38-42} = XT{4-0}; 246 let Inst{43-47} = D_RA{38-34}; // RA 247 let Inst{48-63} = D_RA{15-0}; // d1 248} 249 250// X-Form: [PO T IMM VRB XO TX] 251class XForm_XT6_IMM5_VB5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 252 string asmstr, InstrItinClass itin, list<dag> pattern> 253 : I<opcode, OOL, IOL, asmstr, itin> { 254 bits<6> XT; 255 bits<5> VRB; 256 bits<5> IMM; 257 258 let Pattern = pattern; 259 let Inst{6-10} = XT{4-0}; 260 let Inst{11-15} = IMM; 261 let Inst{16-20} = VRB; 262 let Inst{21-30} = xo; 263 let Inst{31} = XT{5}; 264} 265 266class 8RR_XX4Form_IMM8_XTAB6<bits<6> opcode, bits<2> xo, 267 dag OOL, dag IOL, string asmstr, 268 InstrItinClass itin, list<dag> pattern> 269 : PI<1, opcode, OOL, IOL, asmstr, itin> { 270 bits<6> XT; 271 bits<6> XA; 272 bits<6> XB; 273 bits<6> XC; 274 bits<8> IMM; 275 276 let Pattern = pattern; 277 278 // The prefix. 279 let Inst{6-7} = 1; 280 let Inst{8} = 0; 281 let Inst{9-11} = 0; 282 let Inst{12-13} = 0; 283 let Inst{14-23} = 0; 284 let Inst{24-31} = IMM; 285 286 // The instruction. 287 let Inst{38-42} = XT{4-0}; 288 let Inst{43-47} = XA{4-0}; 289 let Inst{48-52} = XB{4-0}; 290 let Inst{53-57} = XC{4-0}; 291 let Inst{58-59} = xo; 292 let Inst{60} = XC{5}; 293 let Inst{61} = XA{5}; 294 let Inst{62} = XB{5}; 295 let Inst{63} = XT{5}; 296} 297 298class VXForm_RD5_N3_VB5<bits<11> xo, dag OOL, dag IOL, string asmstr, 299 InstrItinClass itin, list<dag> pattern> 300 : I<4, OOL, IOL, asmstr, itin> { 301 bits<5> RD; 302 bits<5> VB; 303 bits<3> N; 304 305 let Pattern = pattern; 306 307 let Inst{6-10} = RD; 308 let Inst{11-12} = 0; 309 let Inst{13-15} = N; 310 let Inst{16-20} = VB; 311 let Inst{21-31} = xo; 312} 313 314 315// VX-Form: [PO VRT RA VRB XO]. 316// Destructive (insert) forms are suffixed with _ins. 317class VXForm_VTB5_RA5_ins<bits<11> xo, string opc, list<dag> pattern> 318 : VXForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vDi, gprc:$rA, vrrc:$vB), 319 !strconcat(opc, " $vD, $rA, $vB"), IIC_VecGeneral, pattern>, 320 RegConstraint<"$vDi = $vD">, NoEncode<"$vDi">; 321 322// VX-Form: [PO VRT RA RB XO]. 323// Destructive (insert) forms are suffixed with _ins. 324class VXForm_VRT5_RAB5_ins<bits<11> xo, string opc, list<dag> pattern> 325 : VXForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vDi, gprc:$rA, gprc:$rB), 326 !strconcat(opc, " $vD, $rA, $rB"), IIC_VecGeneral, pattern>, 327 RegConstraint<"$vDi = $vD">, NoEncode<"$vDi">; 328 329// VX-Form: [ PO BF // VRA VRB XO ] 330class VXForm_BF3_VAB5<bits<11> xo, dag OOL, dag IOL, string asmstr, 331 InstrItinClass itin, list<dag> pattern> 332 : I<4, OOL, IOL, asmstr, itin> { 333 bits<3> BF; 334 bits<5> VA; 335 bits<5> VB; 336 337 let Pattern = pattern; 338 339 let Inst{6-8} = BF; 340 let Inst{9-10} = 0; 341 let Inst{11-15} = VA; 342 let Inst{16-20} = VB; 343 let Inst{21-31} = xo; 344} 345 346// VN-Form: [PO VRT VRA VRB PS SD XO] 347// SD is "Shift Direction" 348class VNForm_VTAB5_SD3<bits<6> xo, bits<2> ps, dag OOL, dag IOL, string asmstr, 349 InstrItinClass itin, list<dag> pattern> 350 : I<4, OOL, IOL, asmstr, itin> { 351 bits<5> VRT; 352 bits<5> VRA; 353 bits<5> VRB; 354 bits<3> SD; 355 356 let Pattern = pattern; 357 358 let Inst{6-10} = VRT; 359 let Inst{11-15} = VRA; 360 let Inst{16-20} = VRB; 361 let Inst{21-22} = ps; 362 let Inst{23-25} = SD; 363 let Inst{26-31} = xo; 364} 365 366class VXForm_RD5_MP_VB5<bits<11> xo, bits<4> eo, dag OOL, dag IOL, 367 string asmstr, InstrItinClass itin, list<dag> pattern> 368 : I<4, OOL, IOL, asmstr, itin> { 369 bits<5> RD; 370 bits<5> VB; 371 bit MP; 372 373 let Pattern = pattern; 374 375 let Inst{6-10} = RD; 376 let Inst{11-14} = eo; 377 let Inst{15} = MP; 378 let Inst{16-20} = VB; 379 let Inst{21-31} = xo; 380} 381 382// 8RR:D-Form: [ 1 1 0 // // imm0 383// PO T XO TX imm1 ]. 384class 8RR_DForm_IMM32_XT6<bits<6> opcode, bits<4> xo, dag OOL, dag IOL, 385 string asmstr, InstrItinClass itin, 386 list<dag> pattern> 387 : PI<1, opcode, OOL, IOL, asmstr, itin> { 388 bits<6> XT; 389 bits<32> IMM32; 390 391 let Pattern = pattern; 392 393 // The prefix. 394 let Inst{6-7} = 1; 395 let Inst{8-11} = 0; 396 let Inst{12-13} = 0; // reserved 397 let Inst{14-15} = 0; // reserved 398 let Inst{16-31} = IMM32{31-16}; 399 400 // The instruction. 401 let Inst{38-42} = XT{4-0}; 402 let Inst{43-46} = xo; 403 let Inst{47} = XT{5}; 404 let Inst{48-63} = IMM32{15-0}; 405} 406 407// 8RR:D-Form: [ 1 1 0 // // imm0 408// PO T XO IX TX imm1 ]. 409class 8RR_DForm_IMM32_XT6_IX<bits<6> opcode, bits<3> xo, dag OOL, dag IOL, 410 string asmstr, InstrItinClass itin, 411 list<dag> pattern> 412 : PI<1, opcode, OOL, IOL, asmstr, itin> { 413 bits<6> XT; 414 bit IX; 415 bits<32> IMM32; 416 417 let Pattern = pattern; 418 419 // The prefix. 420 let Inst{6-7} = 1; 421 let Inst{8-11} = 0; 422 let Inst{12-13} = 0; // reserved 423 let Inst{14-15} = 0; // reserved 424 let Inst{16-31} = IMM32{31-16}; 425 426 // The instruction. 427 let Inst{38-42} = XT{4-0}; 428 let Inst{43-45} = xo; 429 let Inst{46} = IX; 430 let Inst{47} = XT{5}; 431 let Inst{48-63} = IMM32{15-0}; 432} 433 434class 8RR_XX4Form_XTABC6<bits<6> opcode, bits<2> xo, dag OOL, dag IOL, 435 string asmstr, InstrItinClass itin, list<dag> pattern> 436 : PI<1, opcode, OOL, IOL, asmstr, itin> { 437 bits<6> XT; 438 bits<6> XA; 439 bits<6> XB; 440 bits<6> XC; 441 442 let Pattern = pattern; 443 444 // The prefix. 445 let Inst{6-7} = 1; 446 let Inst{8-11} = 0; 447 let Inst{12-13} = 0; 448 let Inst{14-31} = 0; 449 450 // The instruction. 451 let Inst{38-42} = XT{4-0}; 452 let Inst{43-47} = XA{4-0}; 453 let Inst{48-52} = XB{4-0}; 454 let Inst{53-57} = XC{4-0}; 455 let Inst{58-59} = xo; 456 let Inst{60} = XC{5}; 457 let Inst{61} = XA{5}; 458 let Inst{62} = XB{5}; 459 let Inst{63} = XT{5}; 460} 461 462class 8RR_XX4Form_IMM3_XTABC6<bits<6> opcode, bits<2> xo, dag OOL, dag IOL, 463 string asmstr, InstrItinClass itin, 464 list<dag> pattern> 465 : PI<1, opcode, OOL, IOL, asmstr, itin> { 466 bits<6> XT; 467 bits<6> XA; 468 bits<6> XB; 469 bits<6> XC; 470 bits<3> IMM; 471 472 let Pattern = pattern; 473 474 // The prefix. 475 let Inst{6-7} = 1; 476 let Inst{8-11} = 0; 477 let Inst{12-13} = 0; 478 let Inst{14-28} = 0; 479 let Inst{29-31} = IMM; 480 481 // The instruction. 482 let Inst{38-42} = XT{4-0}; 483 let Inst{43-47} = XA{4-0}; 484 let Inst{48-52} = XB{4-0}; 485 let Inst{53-57} = XC{4-0}; 486 let Inst{58-59} = xo; 487 let Inst{60} = XC{5}; 488 let Inst{61} = XA{5}; 489 let Inst{62} = XB{5}; 490 let Inst{63} = XT{5}; 491} 492 493// [PO BF / XO2 B XO BX /] 494class XX2_BF3_XO5_XB6_XO9<bits<6> opcode, bits<5> xo2, bits<9> xo, dag OOL, 495 dag IOL, string asmstr, InstrItinClass itin, 496 list<dag> pattern> 497 : I<opcode, OOL, IOL, asmstr, itin> { 498 bits<3> BF; 499 bits<6> XB; 500 501 let Pattern = pattern; 502 503 let Inst{6-8} = BF; 504 let Inst{9-10} = 0; 505 let Inst{11-15} = xo2; 506 let Inst{16-20} = XB{4-0}; 507 let Inst{21-29} = xo; 508 let Inst{30} = XB{5}; 509 let Inst{31} = 0; 510} 511 512// X-Form: [ PO RT BI /// XO / ] 513class XForm_XT5_BI5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 514 string asmstr, InstrItinClass itin, list<dag> pattern> 515 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 516 let B = 0; 517} 518 519multiclass MLS_DForm_R_SI34_RTA5_MEM_p<bits<6> opcode, dag OOL, dag IOL, 520 dag PCRel_IOL, string asmstr, 521 InstrItinClass itin> { 522 def NAME : MLS_DForm_R_SI34_RTA5_MEM<opcode, OOL, IOL, 523 !strconcat(asmstr, ", 0"), itin, []>; 524 def pc : MLS_DForm_R_SI34_RTA5_MEM<opcode, OOL, PCRel_IOL, 525 !strconcat(asmstr, ", 1"), itin, []>, 526 isPCRel; 527} 528 529multiclass 8LS_DForm_R_SI34_RTA5_p<bits<6> opcode, dag OOL, dag IOL, 530 dag PCRel_IOL, string asmstr, 531 InstrItinClass itin> { 532 def NAME : 8LS_DForm_R_SI34_RTA5<opcode, OOL, IOL, 533 !strconcat(asmstr, ", 0"), itin, []>; 534 def pc : 8LS_DForm_R_SI34_RTA5<opcode, OOL, PCRel_IOL, 535 !strconcat(asmstr, ", 1"), itin, []>, isPCRel; 536} 537 538multiclass 8LS_DForm_R_SI34_XT6_RA5_p<bits<5> opcode, dag OOL, dag IOL, 539 dag PCRel_IOL, string asmstr, 540 InstrItinClass itin> { 541 def NAME : 8LS_DForm_R_SI34_XT6_RA5<opcode, OOL, IOL, 542 !strconcat(asmstr, ", 0"), itin, []>; 543 def pc : 8LS_DForm_R_SI34_XT6_RA5<opcode, OOL, PCRel_IOL, 544 !strconcat(asmstr, ", 1"), itin, []>, 545 isPCRel; 546} 547 548def PPCRegVSRpRCAsmOperand : AsmOperandClass { 549 let Name = "RegVSRpRC"; let PredicateMethod = "isVSRpEvenRegNumber"; 550} 551 552def vsrprc : RegisterOperand<VSRpRC> { 553 let ParserMatchClass = PPCRegVSRpRCAsmOperand; 554} 555 556def PPCRegVSRpEvenRCAsmOperand : AsmOperandClass { 557 let Name = "RegVSRpEvenRC"; let PredicateMethod = "isVSRpEvenRegNumber"; 558} 559 560def vsrpevenrc : RegisterOperand<VSRpRC> { 561 let ParserMatchClass = PPCRegVSRpEvenRCAsmOperand; 562 let EncoderMethod = "getVSRpEvenEncoding"; 563 let DecoderMethod = "decodeVSRpEvenOperands"; 564} 565 566class DQForm_XTp5_RA17_MEM<bits<6> opcode, bits<4> xo, dag OOL, dag IOL, 567 string asmstr, InstrItinClass itin, list<dag> pattern> 568 : I<opcode, OOL, IOL, asmstr, itin> { 569 bits<5> XTp; 570 bits<17> DQ_RA; 571 let Pattern = pattern; 572 573 let Inst{6-9} = XTp{3-0}; 574 let Inst{10} = XTp{4}; 575 let Inst{11-15} = DQ_RA{16-12}; // Register # 576 let Inst{16-27} = DQ_RA{11-0}; // Displacement. 577 let Inst{28-31} = xo; 578} 579 580class XForm_XTp5_XAB5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 581 string asmstr, InstrItinClass itin, list<dag> pattern> 582 : I<opcode, OOL, IOL, asmstr, itin>, XFormMemOp { 583 bits<5> XTp; 584 bits<5> A; 585 bits<5> B; 586 587 let Pattern = pattern; 588 let Inst{6-9} = XTp{3-0}; 589 let Inst{10} = XTp{4}; 590 let Inst{11-15} = A; 591 let Inst{16-20} = B; 592 let Inst{21-30} = xo; 593 let Inst{31} = 0; 594} 595 596class 8LS_DForm_R_XTp5_SI34_MEM<bits<6> opcode, dag OOL, dag IOL, string asmstr, 597 InstrItinClass itin, list<dag> pattern> 598 : PI<1, opcode, OOL, IOL, asmstr, itin> { 599 bits<5> XTp; 600 bits<39> D_RA; 601 602 let Pattern = pattern; 603 604 // The prefix. 605 let Inst{6-10} = 0; 606 let Inst{11} = PCRel; 607 let Inst{12-13} = 0; 608 let Inst{14-31} = D_RA{33-16}; // Imm18 609 610 // The instruction. 611 let Inst{38-41} = XTp{3-0}; 612 let Inst{42} = XTp{4}; 613 let Inst{43-47} = D_RA{38-34}; // Register # 614 let Inst{48-63} = D_RA{15-0}; // D 615} 616 617multiclass 8LS_DForm_R_XTp5_SI34_MEM_p<bits<6> pref, bits<6> opcode, dag OOL, 618 dag IOL, dag PCRel_IOL, 619 string asmstr, InstrItinClass itin> { 620 def NAME : 8LS_DForm_R_XTp5_SI34_MEM<opcode, OOL, IOL, 621 !strconcat(asmstr, ", 0"), itin, []>; 622 def pc : 8LS_DForm_R_XTp5_SI34_MEM<opcode, OOL, PCRel_IOL, 623 !strconcat(asmstr, ", 1"), itin, []>, 624 isPCRel; 625} 626 627def PPCRegACCRCAsmOperand : AsmOperandClass { 628 let Name = "RegACCRC"; let PredicateMethod = "isACCRegNumber"; 629} 630 631def acc : RegisterOperand<ACCRC> { 632 let ParserMatchClass = PPCRegACCRCAsmOperand; 633} 634 635def uacc : RegisterOperand<UACCRC> { 636 let ParserMatchClass = PPCRegACCRCAsmOperand; 637} 638 639// [PO AS XO2 XO] 640class XForm_AT3<bits<6> opcode, bits<5> xo2, bits<10> xo, dag OOL, dag IOL, 641 string asmstr, InstrItinClass itin, list<dag> pattern> 642 : I<opcode, OOL, IOL, asmstr, itin> { 643 bits<3> AT; 644 645 let Pattern = pattern; 646 647 let Inst{6-8} = AT; 648 let Inst{9-10} = 0; 649 let Inst{11-15} = xo2; 650 let Inst{16-20} = 0; 651 let Inst{21-30} = xo; 652 let Inst{31} = 0; 653} 654 655class XX3Form_AT3_XAB6<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, 656 string asmstr, InstrItinClass itin, 657 list<dag> pattern> 658 : I<opcode, OOL, IOL, asmstr, itin> { 659 bits<3> AT; 660 bits<6> XA; 661 bits<6> XB; 662 663 let Pattern = pattern; 664 665 let Inst{6-8} = AT; 666 let Inst{9-10} = 0; 667 let Inst{11-15} = XA{4-0}; 668 let Inst{16-20} = XB{4-0}; 669 let Inst{21-28} = xo; 670 let Inst{29} = XA{5}; 671 let Inst{30} = XB{5}; 672 let Inst{31} = 0; 673} 674 675class MMIRR_XX3Form_XY4P2_XAB6<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, 676 string asmstr, InstrItinClass itin, 677 list<dag> pattern> 678 : PI<1, opcode, OOL, IOL, asmstr, itin> { 679 bits<3> AT; 680 bits<6> XA; 681 bits<6> XB; 682 bits<4> XMSK; 683 bits<4> YMSK; 684 bits<2> PMSK; 685 686 let Pattern = pattern; 687 688 // The prefix. 689 let Inst{6-7} = 3; 690 let Inst{8-11} = 9; 691 let Inst{12-15} = 0; 692 let Inst{16-17} = PMSK; 693 let Inst{18-23} = 0; 694 let Inst{24-27} = XMSK; 695 let Inst{28-31} = YMSK; 696 697 // The instruction. 698 let Inst{38-40} = AT; 699 let Inst{41-42} = 0; 700 let Inst{43-47} = XA{4-0}; 701 let Inst{48-52} = XB{4-0}; 702 let Inst{53-60} = xo; 703 let Inst{61} = XA{5}; 704 let Inst{62} = XB{5}; 705 let Inst{63} = 0; 706} 707 708class MMIRR_XX3Form_XY4_XAB6<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, 709 string asmstr, InstrItinClass itin, 710 list<dag> pattern> 711 : PI<1, opcode, OOL, IOL, asmstr, itin> { 712 bits<3> AT; 713 bits<6> XA; 714 bits<6> XB; 715 bits<4> XMSK; 716 bits<4> YMSK; 717 718 let Pattern = pattern; 719 720 // The prefix. 721 let Inst{6-7} = 3; 722 let Inst{8-11} = 9; 723 let Inst{12-23} = 0; 724 let Inst{24-27} = XMSK; 725 let Inst{28-31} = YMSK; 726 727 // The instruction. 728 let Inst{38-40} = AT; 729 let Inst{41-42} = 0; 730 let Inst{43-47} = XA{4-0}; 731 let Inst{48-52} = XB{4-0}; 732 let Inst{53-60} = xo; 733 let Inst{61} = XA{5}; 734 let Inst{62} = XB{5}; 735 let Inst{63} = 0; 736} 737 738class MMIRR_XX3Form_X4Y2_XAB6<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, 739 string asmstr, InstrItinClass itin, 740 list<dag> pattern> 741 : PI<1, opcode, OOL, IOL, asmstr, itin> { 742 bits<3> AT; 743 bits<6> XA; 744 bits<6> XB; 745 bits<4> XMSK; 746 bits<2> YMSK; 747 748 let Pattern = pattern; 749 750 // The prefix. 751 let Inst{6-7} = 3; 752 let Inst{8-11} = 9; 753 let Inst{12-23} = 0; 754 let Inst{24-27} = XMSK; 755 let Inst{28-29} = YMSK; 756 let Inst{30-31} = 0; 757 758 // The instruction. 759 let Inst{38-40} = AT; 760 let Inst{41-42} = 0; 761 let Inst{43-47} = XA{4-0}; 762 let Inst{48-52} = XB{4-0}; 763 let Inst{53-60} = xo; 764 let Inst{61} = XA{5}; 765 let Inst{62} = XB{5}; 766 let Inst{63} = 0; 767} 768 769class MMIRR_XX3Form_XY4P8_XAB6<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, 770 string asmstr, InstrItinClass itin, 771 list<dag> pattern> 772 : PI<1, opcode, OOL, IOL, asmstr, itin> { 773 bits<3> AT; 774 bits<6> XA; 775 bits<6> XB; 776 bits<4> XMSK; 777 bits<4> YMSK; 778 bits<8> PMSK; 779 780 let Pattern = pattern; 781 782 // The prefix. 783 let Inst{6-7} = 3; 784 let Inst{8-11} = 9; 785 let Inst{12-15} = 0; 786 let Inst{16-23} = PMSK; 787 let Inst{24-27} = XMSK; 788 let Inst{28-31} = YMSK; 789 790 // The instruction. 791 let Inst{38-40} = AT; 792 let Inst{41-42} = 0; 793 let Inst{43-47} = XA{4-0}; 794 let Inst{48-52} = XB{4-0}; 795 let Inst{53-60} = xo; 796 let Inst{61} = XA{5}; 797 let Inst{62} = XB{5}; 798 let Inst{63} = 0; 799} 800 801class MMIRR_XX3Form_XYP4_XAB6<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, 802 string asmstr, InstrItinClass itin, 803 list<dag> pattern> 804 : PI<1, opcode, OOL, IOL, asmstr, itin> { 805 bits<3> AT; 806 bits<6> XA; 807 bits<6> XB; 808 bits<4> XMSK; 809 bits<4> YMSK; 810 bits<4> PMSK; 811 812 let Pattern = pattern; 813 814 // The prefix. 815 let Inst{6-7} = 3; 816 let Inst{8-11} = 9; 817 let Inst{12-15} = 0; 818 let Inst{16-19} = PMSK; 819 let Inst{20-23} = 0; 820 let Inst{24-27} = XMSK; 821 let Inst{28-31} = YMSK; 822 823 // The instruction. 824 let Inst{38-40} = AT; 825 let Inst{41-42} = 0; 826 let Inst{43-47} = XA{4-0}; 827 let Inst{48-52} = XB{4-0}; 828 let Inst{53-60} = xo; 829 let Inst{61} = XA{5}; 830 let Inst{62} = XB{5}; 831 let Inst{63} = 0; 832} 833 834def PrefixInstrs : Predicate<"Subtarget->hasPrefixInstrs()">; 835def IsISA3_1 : Predicate<"Subtarget->isISA3_1()">; 836def PairedVectorMemops : Predicate<"Subtarget->pairedVectorMemops()">; 837def MMA : Predicate<"Subtarget->hasMMA()">; 838 839def RCCp { 840 dag AToVSRC = (COPY_TO_REGCLASS $XA, VSRC); 841 dag BToVSRC = (COPY_TO_REGCLASS $XB, VSRC); 842} 843 844let Predicates = [PrefixInstrs] in { 845 let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 846 defm PADDI8 : 847 MLS_DForm_R_SI34_RTA5_p<14, (outs g8rc:$RT), (ins g8rc:$RA, s34imm:$SI), 848 (ins immZero:$RA, s34imm_pcrel:$SI), 849 "paddi $RT, $RA, $SI", IIC_LdStLFD>; 850 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in { 851 def PLI8 : MLS_DForm_SI34_RT5<14, (outs g8rc:$RT), 852 (ins s34imm:$SI), 853 "pli $RT, $SI", IIC_IntSimple, []>; 854 } 855 } 856 defm PADDI : 857 MLS_DForm_R_SI34_RTA5_p<14, (outs gprc:$RT), (ins gprc:$RA, s34imm:$SI), 858 (ins immZero:$RA, s34imm_pcrel:$SI), 859 "paddi $RT, $RA, $SI", IIC_LdStLFD>; 860 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in { 861 def PLI : MLS_DForm_SI34_RT5<14, (outs gprc:$RT), 862 (ins s34imm:$SI), 863 "pli $RT, $SI", IIC_IntSimple, []>; 864 } 865 866 let mayLoad = 1, mayStore = 0 in { 867 defm PLXV : 868 8LS_DForm_R_SI34_XT6_RA5_p<25, (outs vsrc:$XT), (ins memri34:$D_RA), 869 (ins memri34_pcrel:$D_RA), "plxv $XT, $D_RA", 870 IIC_LdStLFD>; 871 defm PLFS : 872 MLS_DForm_R_SI34_RTA5_MEM_p<48, (outs f4rc:$FRT), (ins memri34:$D_RA), 873 (ins memri34_pcrel:$D_RA), "plfs $FRT, $D_RA", 874 IIC_LdStLFD>; 875 defm PLFD : 876 MLS_DForm_R_SI34_RTA5_MEM_p<50, (outs f8rc:$FRT), (ins memri34:$D_RA), 877 (ins memri34_pcrel:$D_RA), "plfd $FRT, $D_RA", 878 IIC_LdStLFD>; 879 defm PLXSSP : 880 8LS_DForm_R_SI34_RTA5_p<43, (outs vfrc:$VRT), (ins memri34:$D_RA), 881 (ins memri34_pcrel:$D_RA), "plxssp $VRT, $D_RA", 882 IIC_LdStLFD>; 883 defm PLXSD : 884 8LS_DForm_R_SI34_RTA5_p<42, (outs vfrc:$VRT), (ins memri34:$D_RA), 885 (ins memri34_pcrel:$D_RA), "plxsd $VRT, $D_RA", 886 IIC_LdStLFD>; 887 let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 888 defm PLBZ8 : 889 MLS_DForm_R_SI34_RTA5_MEM_p<34, (outs g8rc:$RT), (ins memri34:$D_RA), 890 (ins memri34_pcrel:$D_RA), "plbz $RT, $D_RA", 891 IIC_LdStLFD>; 892 defm PLHZ8 : 893 MLS_DForm_R_SI34_RTA5_MEM_p<40, (outs g8rc:$RT), (ins memri34:$D_RA), 894 (ins memri34_pcrel:$D_RA), "plhz $RT, $D_RA", 895 IIC_LdStLFD>; 896 defm PLHA8 : 897 MLS_DForm_R_SI34_RTA5_MEM_p<42, (outs g8rc:$RT), (ins memri34:$D_RA), 898 (ins memri34_pcrel:$D_RA), "plha $RT, $D_RA", 899 IIC_LdStLFD>; 900 defm PLWA8 : 901 8LS_DForm_R_SI34_RTA5_p<41, (outs g8rc:$RT), (ins memri34:$D_RA), 902 (ins memri34_pcrel:$D_RA), "plwa $RT, $D_RA", 903 IIC_LdStLFD>; 904 defm PLWZ8 : 905 MLS_DForm_R_SI34_RTA5_MEM_p<32, (outs g8rc:$RT), (ins memri34:$D_RA), 906 (ins memri34_pcrel:$D_RA), "plwz $RT, $D_RA", 907 IIC_LdStLFD>; 908 } 909 defm PLBZ : 910 MLS_DForm_R_SI34_RTA5_MEM_p<34, (outs gprc:$RT), (ins memri34:$D_RA), 911 (ins memri34_pcrel:$D_RA), "plbz $RT, $D_RA", 912 IIC_LdStLFD>; 913 defm PLHZ : 914 MLS_DForm_R_SI34_RTA5_MEM_p<40, (outs gprc:$RT), (ins memri34:$D_RA), 915 (ins memri34_pcrel:$D_RA), "plhz $RT, $D_RA", 916 IIC_LdStLFD>; 917 defm PLHA : 918 MLS_DForm_R_SI34_RTA5_MEM_p<42, (outs gprc:$RT), (ins memri34:$D_RA), 919 (ins memri34_pcrel:$D_RA), "plha $RT, $D_RA", 920 IIC_LdStLFD>; 921 defm PLWZ : 922 MLS_DForm_R_SI34_RTA5_MEM_p<32, (outs gprc:$RT), (ins memri34:$D_RA), 923 (ins memri34_pcrel:$D_RA), "plwz $RT, $D_RA", 924 IIC_LdStLFD>; 925 defm PLWA : 926 8LS_DForm_R_SI34_RTA5_p<41, (outs gprc:$RT), (ins memri34:$D_RA), 927 (ins memri34_pcrel:$D_RA), "plwa $RT, $D_RA", 928 IIC_LdStLFD>; 929 defm PLD : 930 8LS_DForm_R_SI34_RTA5_p<57, (outs g8rc:$RT), (ins memri34:$D_RA), 931 (ins memri34_pcrel:$D_RA), "pld $RT, $D_RA", 932 IIC_LdStLFD>; 933 } 934 935 let mayStore = 1, mayLoad = 0 in { 936 defm PSTXV : 937 8LS_DForm_R_SI34_XT6_RA5_p<27, (outs), (ins vsrc:$XS, memri34:$D_RA), 938 (ins vsrc:$XS, memri34_pcrel:$D_RA), 939 "pstxv $XS, $D_RA", IIC_LdStLFD>; 940 defm PSTFS : 941 MLS_DForm_R_SI34_RTA5_MEM_p<52, (outs), (ins f4rc:$FRS, memri34:$D_RA), 942 (ins f4rc:$FRS, memri34_pcrel:$D_RA), 943 "pstfs $FRS, $D_RA", IIC_LdStLFD>; 944 defm PSTFD : 945 MLS_DForm_R_SI34_RTA5_MEM_p<54, (outs), (ins f8rc:$FRS, memri34:$D_RA), 946 (ins f8rc:$FRS, memri34_pcrel:$D_RA), 947 "pstfd $FRS, $D_RA", IIC_LdStLFD>; 948 defm PSTXSSP : 949 8LS_DForm_R_SI34_RTA5_p<47, (outs), (ins vfrc:$VRS, memri34:$D_RA), 950 (ins vfrc:$VRS, memri34_pcrel:$D_RA), 951 "pstxssp $VRS, $D_RA", IIC_LdStLFD>; 952 defm PSTXSD : 953 8LS_DForm_R_SI34_RTA5_p<46, (outs), (ins vfrc:$VRS, memri34:$D_RA), 954 (ins vfrc:$VRS, memri34_pcrel:$D_RA), 955 "pstxsd $VRS, $D_RA", IIC_LdStLFD>; 956 let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 957 defm PSTB8 : 958 MLS_DForm_R_SI34_RTA5_MEM_p<38, (outs), (ins g8rc:$RS, memri34:$D_RA), 959 (ins g8rc:$RS, memri34_pcrel:$D_RA), 960 "pstb $RS, $D_RA", IIC_LdStLFD>; 961 defm PSTH8 : 962 MLS_DForm_R_SI34_RTA5_MEM_p<44, (outs), (ins g8rc:$RS, memri34:$D_RA), 963 (ins g8rc:$RS, memri34_pcrel:$D_RA), 964 "psth $RS, $D_RA", IIC_LdStLFD>; 965 defm PSTW8 : 966 MLS_DForm_R_SI34_RTA5_MEM_p<36, (outs), (ins g8rc:$RS, memri34:$D_RA), 967 (ins g8rc:$RS, memri34_pcrel:$D_RA), 968 "pstw $RS, $D_RA", IIC_LdStLFD>; 969 } 970 defm PSTB : 971 MLS_DForm_R_SI34_RTA5_MEM_p<38, (outs), (ins gprc:$RS, memri34:$D_RA), 972 (ins gprc:$RS, memri34_pcrel:$D_RA), 973 "pstb $RS, $D_RA", IIC_LdStLFD>; 974 defm PSTH : 975 MLS_DForm_R_SI34_RTA5_MEM_p<44, (outs), (ins gprc:$RS, memri34:$D_RA), 976 (ins gprc:$RS, memri34_pcrel:$D_RA), 977 "psth $RS, $D_RA", IIC_LdStLFD>; 978 defm PSTW : 979 MLS_DForm_R_SI34_RTA5_MEM_p<36, (outs), (ins gprc:$RS, memri34:$D_RA), 980 (ins gprc:$RS, memri34_pcrel:$D_RA), 981 "pstw $RS, $D_RA", IIC_LdStLFD>; 982 defm PSTD : 983 8LS_DForm_R_SI34_RTA5_p<61, (outs), (ins g8rc:$RS, memri34:$D_RA), 984 (ins g8rc:$RS, memri34_pcrel:$D_RA), 985 "pstd $RS, $D_RA", IIC_LdStLFD>; 986 } 987} 988 989// Multiclass definitions for MMA accumulator instructions. 990// ---------------------------------------------------------------------------- 991 992// Defines 2 unmasked instructions where the xo field for acc/non-acc version 993// is even/odd. 994multiclass ACC_UM_XOEO<bits<6> opcode, bits<8> xo, dag IOL, string asmbase, 995 string asmstr> { 996 let Predicates = [MMA] in { 997 def NAME : 998 XX3Form_AT3_XAB6<opcode, !or(xo, 0x01), (outs acc:$AT), IOL, 999 !strconcat(asmbase#" ", asmstr), IIC_VecFP, []>, 1000 RegConstraint<"@earlyclobber $AT">; 1001 def PP : 1002 XX3Form_AT3_XAB6<opcode, xo, (outs acc:$AT), !con((ins acc:$ATi), IOL), 1003 !strconcat(asmbase#"pp ", asmstr), IIC_VecFP, []>, 1004 RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">; 1005 } 1006} 1007 1008// Defines 4 instructions, masked/unmasked with masks 8, 4, 4 bits. 1009// The XO field for acc/non-acc version is even/odd. 1010multiclass ACC_UM_M844_XOEO<bits<6> opcode, bits<8> xo, dag IOL, string asmbase, 1011 string asmstr> { 1012 defm NAME : ACC_UM_XOEO<opcode, xo, IOL, asmbase, asmstr>; 1013 let Predicates = [MMA, PrefixInstrs] in { 1014 def PM#NAME : 1015 MMIRR_XX3Form_XY4P8_XAB6< 1016 opcode, !or(xo, 0x01), (outs acc:$AT), 1017 !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK, u8imm:$PMSK)), 1018 !strconcat("pm"#asmbase#" ", asmstr#", $XMSK, $YMSK, $PMSK"), 1019 IIC_VecFP, []>, 1020 RegConstraint<"@earlyclobber $AT">; 1021 def PM#NAME#PP : 1022 MMIRR_XX3Form_XY4P8_XAB6< 1023 opcode, xo, (outs acc:$AT), 1024 !con((ins acc:$ATi), 1025 !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK, u8imm:$PMSK))), 1026 !strconcat("pm"#asmbase#"pp ", asmstr#", $XMSK, $YMSK, $PMSK"), 1027 IIC_VecFP, []>, 1028 RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">; 1029 } 1030} 1031 1032// Defines 4 instructions, masked/unmasked with masks 4, 4, 4 bits. 1033// The XO field for acc/non-acc version is even/odd. 1034multiclass ACC_UM_M444_XOEO<bits<6> opcode, bits<8> xo, dag IOL, string asmbase, 1035 string asmstr> { 1036 defm NAME : ACC_UM_XOEO<opcode, xo, IOL, asmbase, asmstr>; 1037 let Predicates = [MMA, PrefixInstrs] in { 1038 def PM#NAME : 1039 MMIRR_XX3Form_XYP4_XAB6< 1040 opcode, !or(xo, 0x01), (outs acc:$AT), 1041 !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK, u4imm:$PMSK)), 1042 !strconcat("pm"#asmbase#" ", asmstr#", $XMSK, $YMSK, $PMSK"), 1043 IIC_VecFP, []>, 1044 RegConstraint<"@earlyclobber $AT">; 1045 def PM#NAME#PP : 1046 MMIRR_XX3Form_XYP4_XAB6< 1047 opcode, xo, (outs acc:$AT), 1048 !con((ins acc:$ATi), 1049 !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK, u4imm:$PMSK))), 1050 !strconcat("pm"#asmbase#"pp ", asmstr#", $XMSK, $YMSK, $PMSK"), 1051 IIC_VecFP, []>, 1052 RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">; 1053 } 1054} 1055 1056// Defines 4 instructions, masked/unmasked with masks 2, 4, 4 bits. 1057// The XO field for acc/non-acc version is even/odd. 1058multiclass ACC_UM_M244_XOEO<bits<6> opcode, bits<8> xo, dag IOL, string asmbase, 1059 string asmstr> { 1060 defm NAME : ACC_UM_XOEO<opcode, xo, IOL, asmbase, asmstr>; 1061 let Predicates = [MMA, PrefixInstrs] in { 1062 def PM#NAME : 1063 MMIRR_XX3Form_XY4P2_XAB6< 1064 opcode, !or(xo, 0x01), (outs acc:$AT), 1065 !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK, u2imm:$PMSK)), 1066 !strconcat("pm"#asmbase#" ", asmstr#", $XMSK, $YMSK, $PMSK"), 1067 IIC_VecFP, []>, 1068 RegConstraint<"@earlyclobber $AT">; 1069 def PM#NAME#PP : 1070 MMIRR_XX3Form_XY4P2_XAB6< 1071 opcode, xo, (outs acc:$AT), 1072 !con((ins acc:$ATi), !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK, u2imm:$PMSK))), 1073 !strconcat("pm"#asmbase#"pp ", asmstr#", $XMSK, $YMSK, $PMSK"), 1074 IIC_VecFP, []>, 1075 RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">; 1076 } 1077} 1078 1079// Defines 4 instructions, masked/unmasked with masks 2, 4, 4 bits. 1080// Upper nibble of XO field for acc/non-acc version is 0x4/0x6. 1081multiclass ACC_UM_M244_XO46<bits<6> opcode, bits<8> xo, dag IOL, string asmbase, 1082 string asmstr> { 1083 let Predicates = [MMA] in { 1084 def NAME : 1085 XX3Form_AT3_XAB6<opcode, xo, (outs acc:$AT), IOL, 1086 !strconcat(asmbase#" ", asmstr), IIC_VecFP, []>, 1087 RegConstraint<"@earlyclobber $AT">; 1088 def PP : 1089 XX3Form_AT3_XAB6< 1090 opcode, !or(xo, 0x20), (outs acc:$AT), !con((ins acc:$ATi), IOL), 1091 !strconcat(asmbase#"pp ", asmstr), IIC_VecFP, []>, 1092 RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">; 1093 } 1094 let Predicates = [MMA, PrefixInstrs] in { 1095 def PM#NAME : 1096 MMIRR_XX3Form_XY4P2_XAB6< 1097 opcode, xo, (outs acc:$AT), 1098 !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK, u2imm:$PMSK)), 1099 !strconcat("pm"#asmbase#" ", asmstr#", $XMSK, $YMSK, $PMSK"), 1100 IIC_VecFP, []>, 1101 RegConstraint<"@earlyclobber $AT">; 1102 def PM#NAME#PP : 1103 MMIRR_XX3Form_XY4P2_XAB6< 1104 opcode, !or(xo, 0x20), (outs acc:$AT), 1105 !con((ins acc:$ATi), 1106 !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK, u2imm:$PMSK))), 1107 !strconcat("pm"#asmbase#"pp ", asmstr#", $XMSK, $YMSK, $PMSK"), 1108 IIC_VecFP, []>, 1109 RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">; 1110 } 1111} 1112 1113// Defines 10 instructions, operand negating, unmasked, masked with 2, 4, 4 1114// bits. Upper nibble are masked with 0x8, 0x4, 0xC for negating operands. 1115multiclass ACC_NEG_UM_M244_XOM84C<bits<6> opcode, bits<8> xo, dag IOL, 1116 string asmbase, string asmstr> { 1117 defm NAME : ACC_UM_M244_XOEO<opcode, xo, IOL, asmbase, asmstr>; 1118 let Predicates = [MMA] in { 1119 def PN : XX3Form_AT3_XAB6< 1120 opcode, !or(xo, 0x80), (outs acc:$AT), !con((ins acc:$ATi), IOL), 1121 !strconcat(asmbase#"pn ", asmstr), IIC_VecFP, []>, 1122 RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">; 1123 def NP : XX3Form_AT3_XAB6< 1124 opcode, !or(xo, 0x40), (outs acc:$AT), !con((ins acc:$ATi), IOL), 1125 !strconcat(asmbase#"np ", asmstr), IIC_VecFP, []>, 1126 RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">; 1127 def NN : XX3Form_AT3_XAB6< 1128 opcode, !or(xo, 0xC0), (outs acc:$AT), !con((ins acc:$ATi), IOL), 1129 !strconcat(asmbase#"nn ", asmstr), IIC_VecFP, []>, 1130 RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">; 1131 } 1132 let Predicates = [MMA, PrefixInstrs] in { 1133 def PM#NAME#PN : 1134 MMIRR_XX3Form_XY4P2_XAB6< 1135 opcode, !or(xo, 0x80), (outs acc:$AT), 1136 !con((ins acc:$ATi), !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK, u2imm:$PMSK))), 1137 !strconcat("pm"#asmbase#"pn ", asmstr#", $XMSK, $YMSK, $PMSK"), 1138 IIC_VecFP, []>, 1139 RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">; 1140 def PM#NAME#NP : 1141 MMIRR_XX3Form_XY4P2_XAB6< 1142 opcode, !or(xo, 0x40), (outs acc:$AT), 1143 !con((ins acc:$ATi), !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK, u2imm:$PMSK))), 1144 !strconcat("pm"#asmbase#"np ", asmstr#", $XMSK, $YMSK, $PMSK"), 1145 IIC_VecFP, []>, 1146 RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">; 1147 def PM#NAME#NN : 1148 MMIRR_XX3Form_XY4P2_XAB6< 1149 opcode, !or(xo, 0xC0), (outs acc:$AT), 1150 !con((ins acc:$ATi), !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK, u2imm:$PMSK))), 1151 !strconcat("pm"#asmbase#"nn ", asmstr#", $XMSK, $YMSK, $PMSK"), 1152 IIC_VecFP, []>, 1153 RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">; 1154 } 1155} 1156 1157// Defines 5 instructions, unmasked, operand negating. 1158// Upper nibble are masked with 0x8, 0x4, 0xC for negating operands. 1159multiclass ACC_NEG_UM_XOM84C<bits<6> opcode, bits<8> xo, dag IOL, 1160 string asmbase, string asmstr> { 1161 defm NAME : ACC_UM_XOEO<opcode, xo, IOL, asmbase, asmstr>; 1162 let Predicates = [MMA] in { 1163 def PN : XX3Form_AT3_XAB6<opcode, !or(xo, 0x80), (outs acc:$AT), 1164 !con((ins acc:$ATi), IOL), 1165 !strconcat(asmbase#"pn ", asmstr), IIC_VecFP, []>, 1166 RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">; 1167 def NP : XX3Form_AT3_XAB6<opcode, !or(xo, 0x40), (outs acc:$AT), 1168 !con((ins acc:$ATi), IOL), 1169 !strconcat(asmbase#"np ", asmstr), IIC_VecFP, []>, 1170 RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">; 1171 def NN : XX3Form_AT3_XAB6<opcode, !or(xo, 0xC0), (outs acc:$AT), 1172 !con((ins acc:$ATi), IOL), 1173 !strconcat(asmbase#"nn ", asmstr), IIC_VecFP, []>, 1174 RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">; 1175 } 1176} 1177 1178// Defines 10 instructions, operand negating, unmasked, masked with 4, 4 bits. 1179// Upper nibble are masked with 0x8, 0x4, 0xC for negating operands. 1180multiclass ACC_NEG_UM_M44_XOM84C<bits<6> opcode, bits<8> xo, dag IOL, 1181 string asmbase, string asmstr> { 1182 defm NAME : ACC_NEG_UM_XOM84C<opcode, xo, IOL, asmbase, asmstr>; 1183 let Predicates = [MMA, PrefixInstrs] in { 1184 def PM#NAME : 1185 MMIRR_XX3Form_XY4_XAB6< 1186 opcode, !or(xo, 0x01), (outs acc:$AT), 1187 !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK)), 1188 !strconcat("pm"#asmbase#" ", asmstr#", $XMSK, $YMSK"), 1189 IIC_VecFP, []>, 1190 RegConstraint<"@earlyclobber $AT">; 1191 def PM#NAME#PP : 1192 MMIRR_XX3Form_XY4_XAB6< 1193 opcode, xo, (outs acc:$AT), 1194 !con((ins acc:$ATi), !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK))), 1195 !strconcat("pm"#asmbase#"pp ", asmstr#", $XMSK, $YMSK"), 1196 IIC_VecFP, []>, 1197 RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">; 1198 def PM#NAME#PN : 1199 MMIRR_XX3Form_XY4_XAB6< 1200 opcode, !or(xo, 0x80), (outs acc:$AT), 1201 !con((ins acc:$ATi), !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK))), 1202 !strconcat("pm"#asmbase#"pn ", asmstr#", $XMSK, $YMSK"), 1203 IIC_VecFP, []>, 1204 RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">; 1205 def PM#NAME#NP : 1206 MMIRR_XX3Form_XY4_XAB6< 1207 opcode, !or(xo, 0x40), (outs acc:$AT), 1208 !con((ins acc:$ATi), !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK))), 1209 !strconcat("pm"#asmbase#"np ", asmstr#", $XMSK, $YMSK"), 1210 IIC_VecFP, []>, 1211 RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">; 1212 def PM#NAME#NN : 1213 MMIRR_XX3Form_XY4_XAB6< 1214 opcode, !or(xo, 0xC0), (outs acc:$AT), 1215 !con((ins acc:$ATi), !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK))), 1216 !strconcat("pm"#asmbase#"nn ", asmstr#", $XMSK, $YMSK"), 1217 IIC_VecFP, []>, 1218 RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">; 1219 } 1220} 1221 1222// Defines 10 instructions, operand negating, unmasked, masked with 4, 2 bits. 1223// Upper nibble are masked with 0x8, 0x4, 0xC for negating operands. 1224multiclass ACC_NEG_UM_M42_XOM84C<bits<6> opcode, bits<8> xo, dag IOL, 1225 string asmbase, string asmstr> { 1226 defm NAME : ACC_NEG_UM_XOM84C<opcode, xo, IOL, asmbase, asmstr>; 1227 let Predicates = [MMA, PrefixInstrs] in { 1228 def PM#NAME : 1229 MMIRR_XX3Form_X4Y2_XAB6< 1230 opcode, !or(xo, 0x01), (outs acc:$AT), 1231 !con(IOL, (ins u4imm:$XMSK, u2imm:$YMSK)), 1232 !strconcat("pm"#asmbase#" ", asmstr#", $XMSK, $YMSK"), 1233 IIC_VecFP, []>, 1234 RegConstraint<"@earlyclobber $AT">; 1235 def PM#NAME#PP : 1236 MMIRR_XX3Form_X4Y2_XAB6< 1237 opcode, xo, (outs acc:$AT), 1238 !con((ins acc:$ATi), !con(IOL, (ins u4imm:$XMSK, u2imm:$YMSK))), 1239 !strconcat("pm"#asmbase#"pp ", asmstr#", $XMSK, $YMSK"), 1240 IIC_VecFP, []>, 1241 RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">; 1242 def PM#NAME#PN : 1243 MMIRR_XX3Form_X4Y2_XAB6< 1244 opcode, !or(xo, 0x80), (outs acc:$AT), 1245 !con((ins acc:$ATi), !con(IOL, (ins u4imm:$XMSK, u2imm:$YMSK))), 1246 !strconcat("pm"#asmbase#"pn ", asmstr#", $XMSK, $YMSK"), 1247 IIC_VecFP, []>, 1248 RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">; 1249 def PM#NAME#NP : 1250 MMIRR_XX3Form_X4Y2_XAB6< 1251 opcode, !or(xo, 0x40), (outs acc:$AT), 1252 !con((ins acc:$ATi), !con(IOL, (ins u4imm:$XMSK, u2imm:$YMSK))), 1253 !strconcat("pm"#asmbase#"np ", asmstr#", $XMSK, $YMSK"), 1254 IIC_VecFP, []>, 1255 RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">; 1256 def PM#NAME#NN : 1257 MMIRR_XX3Form_X4Y2_XAB6< 1258 opcode, !or(xo, 0xC0), (outs acc:$AT), 1259 !con((ins acc:$ATi), !con(IOL, (ins u4imm:$XMSK, u2imm:$YMSK))), 1260 !strconcat("pm"#asmbase#"nn ", asmstr#", $XMSK, $YMSK"), 1261 IIC_VecFP, []>, 1262 RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">; 1263 } 1264} 1265 1266// End of class definitions. 1267//----------------------------------------------------------------------------- 1268 1269let Predicates = [MMA] in { 1270 def XXMFACC : 1271 XForm_AT3<31, 0, 177, (outs acc:$ASo), (ins acc:$AS), "xxmfacc $AS", 1272 IIC_VecGeneral, 1273 [(set v512i1:$ASo, (int_ppc_mma_xxmfacc v512i1:$AS))]>, 1274 RegConstraint<"$ASo = $AS">, NoEncode<"$ASo">; 1275 def XXMTACC : 1276 XForm_AT3<31, 1, 177, (outs acc:$AT), (ins acc:$ATi), "xxmtacc $AT", 1277 IIC_VecGeneral, 1278 [(set v512i1:$AT, (int_ppc_mma_xxmtacc v512i1:$ATi))]>, 1279 RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">; 1280 def KILL_PAIR : PPCPostRAExpPseudo<(outs vsrprc:$XTp), (ins vsrprc:$XSp), 1281 "#KILL_PAIR", []>, 1282 RegConstraint<"$XTp = $XSp">; 1283 def BUILD_UACC : PPCPostRAExpPseudo<(outs acc:$AT), (ins uacc:$AS), 1284 "#BUILD_UACC $AT, $AS", []>; 1285 // We define XXSETACCZ as rematerializable to undo CSE of that intrinsic in 1286 // the backend. We avoid CSE here because it generates a copy of the acc 1287 // register and this copy is more expensive than calling the intrinsic again. 1288 let isAsCheapAsAMove = 1, isReMaterializable = 1 in { 1289 def XXSETACCZ : 1290 XForm_AT3<31, 3, 177, (outs acc:$AT), (ins), "xxsetaccz $AT", IIC_VecGeneral, 1291 [(set v512i1:$AT, (int_ppc_mma_xxsetaccz))]>; 1292 } 1293 def XVI8GER4SPP : 1294 XX3Form_AT3_XAB6<59, 99, (outs acc:$AT), (ins acc:$ATi, vsrc:$XA, vsrc:$XB), 1295 "xvi8ger4spp $AT, $XA, $XB", IIC_VecGeneral, []>, 1296 RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">; 1297 let mayStore = 1 in { 1298 def SPILL_ACC: PPCEmitTimePseudo<(outs), (ins acc:$AT, memrix16:$dst), 1299 "#SPILL_ACC", []>; 1300 def SPILL_UACC: PPCEmitTimePseudo<(outs), (ins uacc:$AT, memrix16:$dst), 1301 "#SPILL_UACC", []>; 1302 } 1303 let mayLoad = 1, hasSideEffects = 0 in { 1304 def RESTORE_ACC: PPCEmitTimePseudo<(outs acc:$AT), (ins memrix16:$src), 1305 "#RESTORE_ACC", []>; 1306 def RESTORE_UACC: PPCEmitTimePseudo<(outs uacc:$AT), (ins memrix16:$src), 1307 "#RESTORE_UACC", []>; 1308 } 1309} 1310 1311let Predicates = [MMA, PrefixInstrs] in { 1312 def PMXVI8GER4SPP : 1313 MMIRR_XX3Form_XYP4_XAB6<59, 99, (outs acc:$AT), 1314 (ins acc:$ATi, vsrc:$XA,vsrc:$XB, u4imm:$XMSK, 1315 u4imm:$YMSK, u4imm:$PMSK), 1316 "pmxvi8ger4spp $AT, $XA, $XB, $XMSK, $YMSK, $PMSK", 1317 IIC_VecGeneral, []>, 1318 RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">; 1319} 1320 1321// MMA accumulating/non-accumulating instructions. 1322//------------------------------------------------------------------------------ 1323 1324// XVBF16GER2, XVBF16GER2PP, XVBF16GER2PN, XVBF16GER2NP, XVBF16GER2NN 1325// PMXVBF16GER2, PMXVBF16GER2PP, PMXVBF16GER2PN, PMXVBF16GER2NP, PMXVBF16GER2NN 1326defm XVBF16GER2 : ACC_NEG_UM_M244_XOM84C<59, 50, (ins vsrc:$XA, vsrc:$XB), 1327 "xvbf16ger2", "$AT, $XA, $XB">; 1328 1329// XVI4GER8, XVI4GER8PP, PMXVI4GER8, PMXVI4GER8PP 1330defm XVI4GER8 : ACC_UM_M844_XOEO<59, 34, (ins vsrc:$XA, vsrc:$XB), 1331 "xvi4ger8", "$AT, $XA, $XB">; 1332 1333// XVI8GER4, XVI8GER4PP, PMXVI8GER4, PMXVI8GER4PP 1334defm XVI8GER4 : ACC_UM_M444_XOEO<59, 2, (ins vsrc:$XA, vsrc:$XB), 1335 "xvi8ger4", "$AT, $XA, $XB">; 1336 1337// XVI16GER2, XVI16GER2PP, PMXVI16GER2, PMXVI16GER2PP 1338defm XVI16GER2 : ACC_UM_M244_XO46<59, 75, (ins vsrc:$XA, vsrc:$XB), 1339 "xvi16ger2", "$AT, $XA, $XB">; 1340 1341// XVI16GER2S, XVI16GER2SPP, PMXVI16GER2S, PMXVI16GER2SPP 1342defm XVI16GER2S : ACC_UM_M244_XOEO<59, 42, (ins vsrc:$XA, vsrc:$XB), 1343 "xvi16ger2s", "$AT, $XA, $XB">; 1344 1345// XVF16GER2, XVF16GER2PP, XVF16GER2PN, XVF16GER2NP, XVF16GER2NN 1346// PMXVF16GER2, PMXVF16GER2PP, PMXVF16GER2PN, PMXVF16GER2NP, PMXVF16GER2NN 1347defm XVF16GER2 : ACC_NEG_UM_M244_XOM84C<59, 18, (ins vsrc:$XA, vsrc:$XB), 1348 "xvf16ger2", "$AT, $XA, $XB">; 1349 1350// XVF32GER, XVF32GERPP, XVF32GERPN, XVF32GERNP, XVF32GERPP 1351// PMXVF32GER, PMXVF32GERPP, PMXVF32GERPN, PMXVF32GERNP, PMXVF32GERPP 1352defm XVF32GER : ACC_NEG_UM_M44_XOM84C<59, 26, (ins vsrc:$XA, vsrc:$XB), 1353 "xvf32ger", "$AT, $XA, $XB">; 1354 1355// XVF64GER, XVF64GERPP, XVF64GERPN, XVF64GERNP, XVF64GERNN 1356// PMXVF64GER, PMXVF64GERPP, PMXVF64GERPN, PMXVF64GERNP, PMXVF64GERNN 1357defm XVF64GER : ACC_NEG_UM_M42_XOM84C<59, 58, (ins vsrpevenrc:$XA, vsrc:$XB), 1358 "xvf64ger", "$AT, $XA, $XB">; 1359//------------------------------------------------------------------------------ 1360 1361// MMA Intrinsics 1362let Predicates = [MMA] in { 1363 def : Pat<(v512i1 (int_ppc_mma_xvi4ger8 v16i8:$XA, v16i8:$XB)), 1364 (XVI4GER8 RCCp.AToVSRC, RCCp.BToVSRC)>; 1365 def : Pat<(v512i1 (int_ppc_mma_xvi4ger8pp v512i1:$ATi, v16i8:$XA, v16i8:$XB)), 1366 (XVI4GER8PP $ATi, RCCp.AToVSRC, RCCp.BToVSRC)>; 1367 1368 def : Pat<(v512i1 (int_ppc_mma_xvi8ger4 v16i8:$XA, v16i8:$XB)), 1369 (XVI8GER4 RCCp.AToVSRC, RCCp.BToVSRC)>; 1370 def : Pat<(v512i1 (int_ppc_mma_xvi8ger4pp v512i1:$ATi, v16i8:$XA, v16i8:$XB)), 1371 (XVI8GER4PP $ATi, RCCp.AToVSRC, RCCp.BToVSRC)>; 1372 1373 def : Pat<(v512i1 (int_ppc_mma_xvi16ger2s v16i8:$XA, v16i8:$XB)), 1374 (XVI16GER2S RCCp.AToVSRC, RCCp.BToVSRC)>; 1375 def : Pat<(v512i1 (int_ppc_mma_xvi16ger2spp v512i1:$ATi, v16i8:$XA, v16i8:$XB)), 1376 (XVI16GER2SPP $ATi, RCCp.AToVSRC, RCCp.BToVSRC)>; 1377 1378 def : Pat<(v512i1 (int_ppc_mma_xvf16ger2 v16i8:$XA, v16i8:$XB)), 1379 (XVF16GER2 RCCp.AToVSRC, RCCp.BToVSRC)>; 1380 def : Pat<(v512i1 (int_ppc_mma_xvf16ger2pp v512i1:$ATi, v16i8:$XA, v16i8:$XB)), 1381 (XVF16GER2PP $ATi, RCCp.AToVSRC, RCCp.BToVSRC)>; 1382 def : Pat<(v512i1 (int_ppc_mma_xvf16ger2pn v512i1:$ATi, v16i8:$XA, v16i8:$XB)), 1383 (XVF16GER2PN $ATi, RCCp.AToVSRC, RCCp.BToVSRC)>; 1384 def : Pat<(v512i1 (int_ppc_mma_xvf16ger2np v512i1:$ATi, v16i8:$XA, v16i8:$XB)), 1385 (XVF16GER2NP $ATi, RCCp.AToVSRC, RCCp.BToVSRC)>; 1386 def : Pat<(v512i1 (int_ppc_mma_xvf16ger2nn v512i1:$ATi, v16i8:$XA, v16i8:$XB)), 1387 (XVF16GER2NN $ATi, RCCp.AToVSRC, RCCp.BToVSRC)>; 1388 1389 def : Pat<(v512i1 (int_ppc_mma_xvf32ger v16i8:$XA, v16i8:$XB)), 1390 (XVF32GER RCCp.AToVSRC, RCCp.BToVSRC)>; 1391 def : Pat<(v512i1 (int_ppc_mma_xvf32gerpp v512i1:$ATi, v16i8:$XA, v16i8:$XB)), 1392 (XVF32GERPP $ATi, RCCp.AToVSRC, RCCp.BToVSRC)>; 1393 def : Pat<(v512i1 (int_ppc_mma_xvf32gerpn v512i1:$ATi, v16i8:$XA, v16i8:$XB)), 1394 (XVF32GERPN $ATi, RCCp.AToVSRC, RCCp.BToVSRC)>; 1395 def : Pat<(v512i1 (int_ppc_mma_xvf32gernp v512i1:$ATi, v16i8:$XA, v16i8:$XB)), 1396 (XVF32GERNP $ATi, RCCp.AToVSRC, RCCp.BToVSRC)>; 1397 def : Pat<(v512i1 (int_ppc_mma_xvf32gernn v512i1:$ATi, v16i8:$XA, v16i8:$XB)), 1398 (XVF32GERNN $ATi, RCCp.AToVSRC, RCCp.BToVSRC)>; 1399 def : Pat<(v512i1 (int_ppc_mma_xvf64ger v256i1:$XA, v16i8:$XB)), 1400 (XVF64GER $XA, RCCp.BToVSRC)>; 1401 def : Pat<(v512i1 (int_ppc_mma_xvf64gerpp v512i1:$ATi, v256i1:$XA, v16i8:$XB)), 1402 (XVF64GERPP $ATi, $XA, RCCp.BToVSRC)>; 1403 def : Pat<(v512i1 (int_ppc_mma_xvf64gerpn v512i1:$ATi, v256i1:$XA, v16i8:$XB)), 1404 (XVF64GERPN $ATi, $XA, RCCp.BToVSRC)>; 1405 def : Pat<(v512i1 (int_ppc_mma_xvf64gernp v512i1:$ATi, v256i1:$XA, v16i8:$XB)), 1406 (XVF64GERNP $ATi, $XA, RCCp.BToVSRC)>; 1407 def : Pat<(v512i1 (int_ppc_mma_xvf64gernn v512i1:$ATi, v256i1:$XA, v16i8:$XB)), 1408 (XVF64GERNN $ATi, $XA, RCCp.BToVSRC)>; 1409 1410 def : Pat<(v512i1 (int_ppc_mma_xvbf16ger2 v16i8:$XA, v16i8:$XB)), 1411 (XVBF16GER2 RCCp.AToVSRC, RCCp.BToVSRC)>; 1412 def : Pat<(v512i1 (int_ppc_mma_xvbf16ger2pp v512i1:$ATi, v16i8:$XA, v16i8:$XB)), 1413 (XVBF16GER2PP $ATi, RCCp.AToVSRC, RCCp.BToVSRC)>; 1414 def : Pat<(v512i1 (int_ppc_mma_xvbf16ger2pn v512i1:$ATi, v16i8:$XA, v16i8:$XB)), 1415 (XVBF16GER2PN $ATi, RCCp.AToVSRC, RCCp.BToVSRC)>; 1416 def : Pat<(v512i1 (int_ppc_mma_xvbf16ger2np v512i1:$ATi, v16i8:$XA, v16i8:$XB)), 1417 (XVBF16GER2NP $ATi, RCCp.AToVSRC, RCCp.BToVSRC)>; 1418 def : Pat<(v512i1 (int_ppc_mma_xvbf16ger2nn v512i1:$ATi, v16i8:$XA, v16i8:$XB)), 1419 (XVBF16GER2NN $ATi, RCCp.AToVSRC, RCCp.BToVSRC)>; 1420 def : Pat<(v512i1 (int_ppc_mma_xvi16ger2 v16i8:$XA, v16i8:$XB)), 1421 (XVI16GER2 RCCp.AToVSRC, RCCp.BToVSRC)>; 1422 def : Pat<(v512i1 (int_ppc_mma_xvi16ger2pp v512i1:$ATi, v16i8:$XA, v16i8:$XB)), 1423 (XVI16GER2PP $ATi, RCCp.AToVSRC, RCCp.BToVSRC)>; 1424 def : Pat<(v512i1 (int_ppc_mma_xvi8ger4spp v512i1:$ATi, v16i8:$XA, v16i8:$XB)), 1425 (XVI8GER4SPP $ATi, RCCp.AToVSRC, RCCp.BToVSRC)>; 1426} 1427 1428// MMA Intrinsics 1429let Predicates = [MMA, PrefixInstrs] in { 1430 def : Pat<(v512i1 (int_ppc_mma_pmxvi4ger8 v16i8:$XA, v16i8:$XB, Msk4Imm:$XMSK, 1431 Msk4Imm:$YMSK, Msk8Imm:$PMSK)), 1432 (PMXVI4GER8 RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK, 1433 Msk4Imm:$YMSK, Msk8Imm:$PMSK)>; 1434 def : Pat<(v512i1 (int_ppc_mma_pmxvi4ger8pp v512i1:$ATi, v16i8:$XA, v16i8:$XB, 1435 Msk4Imm:$XMSK, Msk4Imm:$YMSK, 1436 Msk8Imm:$PMSK)), 1437 (PMXVI4GER8PP $ATi, RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK, 1438 Msk4Imm:$YMSK, Msk8Imm:$PMSK)>; 1439 1440 def : Pat<(v512i1 (int_ppc_mma_pmxvi8ger4 v16i8:$XA, v16i8:$XB, Msk4Imm:$XMSK, 1441 Msk4Imm:$YMSK, Msk4Imm:$PMSK)), 1442 (PMXVI8GER4 RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK, 1443 Msk4Imm:$YMSK, Msk4Imm:$PMSK)>; 1444 def : Pat<(v512i1 (int_ppc_mma_pmxvi8ger4pp v512i1:$ATi, v16i8:$XA, v16i8:$XB, 1445 Msk4Imm:$XMSK, Msk4Imm:$YMSK, 1446 Msk4Imm:$PMSK)), 1447 (PMXVI8GER4PP $ATi, RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK, 1448 Msk4Imm:$YMSK, Msk4Imm:$PMSK)>; 1449 1450 def : Pat<(v512i1 (int_ppc_mma_pmxvi16ger2s v16i8:$XA, v16i8:$XB, Msk4Imm:$XMSK, 1451 Msk4Imm:$YMSK, Msk2Imm:$PMSK)), 1452 (PMXVI16GER2S RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK, 1453 Msk4Imm:$YMSK, Msk2Imm:$PMSK)>; 1454 def : Pat<(v512i1 (int_ppc_mma_pmxvi16ger2spp v512i1:$ATi, v16i8:$XA, v16i8:$XB, 1455 Msk4Imm:$XMSK, Msk4Imm:$YMSK, 1456 Msk2Imm:$PMSK)), 1457 (PMXVI16GER2SPP $ATi, RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK, 1458 Msk4Imm:$YMSK, Msk2Imm:$PMSK)>; 1459 def : Pat<(v512i1 (int_ppc_mma_pmxvf16ger2 v16i8:$XA, v16i8:$XB, Msk4Imm:$XMSK, 1460 Msk4Imm:$YMSK, Msk2Imm:$PMSK)), 1461 (PMXVF16GER2 RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK, 1462 Msk4Imm:$YMSK, Msk2Imm:$PMSK)>; 1463 def : Pat<(v512i1 (int_ppc_mma_pmxvf16ger2pp v512i1:$ATi, v16i8:$XA, v16i8:$XB, 1464 Msk4Imm:$XMSK, Msk4Imm:$YMSK, 1465 Msk2Imm:$PMSK)), 1466 (PMXVF16GER2PP $ATi, RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK, 1467 Msk4Imm:$YMSK, Msk2Imm:$PMSK)>; 1468 def : Pat<(v512i1 (int_ppc_mma_pmxvf16ger2pn v512i1:$ATi, v16i8:$XA, v16i8:$XB, 1469 Msk4Imm:$XMSK, Msk4Imm:$YMSK, 1470 Msk2Imm:$PMSK)), 1471 (PMXVF16GER2PN $ATi, RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK, 1472 Msk4Imm:$YMSK, Msk2Imm:$PMSK)>; 1473 def : Pat<(v512i1 (int_ppc_mma_pmxvf16ger2np v512i1:$ATi, v16i8:$XA, v16i8:$XB, 1474 Msk4Imm:$XMSK, Msk4Imm:$YMSK, 1475 Msk2Imm:$PMSK)), 1476 (PMXVF16GER2NP $ATi, RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK, 1477 Msk4Imm:$YMSK, Msk2Imm:$PMSK)>; 1478 def : Pat<(v512i1 (int_ppc_mma_pmxvf16ger2pn v512i1:$ATi, v16i8:$XA, v16i8:$XB, 1479 Msk4Imm:$XMSK, Msk4Imm:$YMSK, 1480 Msk2Imm:$PMSK)), 1481 (PMXVF16GER2PN $ATi, RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK, 1482 Msk4Imm:$YMSK, Msk2Imm:$PMSK)>; 1483 def : Pat<(v512i1 (int_ppc_mma_pmxvf16ger2np v512i1:$ATi, v16i8:$XA, v16i8:$XB, 1484 Msk4Imm:$XMSK, Msk4Imm:$YMSK, 1485 Msk2Imm:$PMSK)), 1486 (PMXVF16GER2NP $ATi, RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK, 1487 Msk4Imm:$YMSK, Msk2Imm:$PMSK)>; 1488 def : Pat<(v512i1 (int_ppc_mma_pmxvf16ger2nn v512i1:$ATi, v16i8:$XA, v16i8:$XB, 1489 Msk4Imm:$XMSK, Msk4Imm:$YMSK, 1490 Msk2Imm:$PMSK)), 1491 (PMXVF16GER2NN $ATi, RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK, 1492 Msk4Imm:$YMSK, Msk2Imm:$PMSK)>; 1493 1494 def : Pat<(v512i1 (int_ppc_mma_pmxvf32ger v16i8:$XA, v16i8:$XB, Msk4Imm:$XMSK, 1495 Msk4Imm:$YMSK)), 1496 (PMXVF32GER RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK, 1497 Msk4Imm:$YMSK)>; 1498 def : Pat<(v512i1 (int_ppc_mma_pmxvf32gerpp v512i1:$ATi, v16i8:$XA, v16i8:$XB, 1499 Msk4Imm:$XMSK, Msk4Imm:$YMSK)), 1500 (PMXVF32GERPP $ATi, RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK, 1501 Msk4Imm:$YMSK)>; 1502 def : Pat<(v512i1 (int_ppc_mma_pmxvf32gerpn v512i1:$ATi, v16i8:$XA, v16i8:$XB, 1503 Msk4Imm:$XMSK, Msk4Imm:$YMSK)), 1504 (PMXVF32GERPN $ATi, RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK, 1505 Msk4Imm:$YMSK)>; 1506 def : Pat<(v512i1 (int_ppc_mma_pmxvf32gernp v512i1:$ATi, v16i8:$XA, v16i8:$XB, 1507 Msk4Imm:$XMSK, Msk4Imm:$YMSK)), 1508 (PMXVF32GERNP $ATi, RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK, 1509 Msk4Imm:$YMSK)>; 1510 def : Pat<(v512i1 (int_ppc_mma_pmxvf32gernn v512i1:$ATi, v16i8:$XA, v16i8:$XB, 1511 Msk4Imm:$XMSK, Msk4Imm:$YMSK)), 1512 (PMXVF32GERNN $ATi, RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK, 1513 Msk4Imm:$YMSK)>; 1514 1515 def : Pat<(v512i1 (int_ppc_mma_pmxvf64ger v256i1:$XA, v16i8:$XB, Msk4Imm:$XMSK, 1516 Msk2Imm:$YMSK)), 1517 (PMXVF64GER $XA, RCCp.BToVSRC, Msk4Imm:$XMSK, Msk2Imm:$YMSK)>; 1518 def : Pat<(v512i1 (int_ppc_mma_pmxvf64gerpp v512i1:$ATi, v256i1:$XA, v16i8:$XB, 1519 Msk4Imm:$XMSK, Msk2Imm:$YMSK)), 1520 (PMXVF64GERPP $ATi, $XA, RCCp.BToVSRC, Msk4Imm:$XMSK, 1521 Msk2Imm:$YMSK)>; 1522 def : Pat<(v512i1 (int_ppc_mma_pmxvf64gerpn v512i1:$ATi, v256i1:$XA, v16i8:$XB, 1523 Msk4Imm:$XMSK, Msk2Imm:$YMSK)), 1524 (PMXVF64GERPN $ATi, $XA, RCCp.BToVSRC, Msk4Imm:$XMSK, 1525 Msk2Imm:$YMSK)>; 1526 def : Pat<(v512i1 (int_ppc_mma_pmxvf64gernp v512i1:$ATi, v256i1:$XA, v16i8:$XB, 1527 Msk4Imm:$XMSK, Msk2Imm:$YMSK)), 1528 (PMXVF64GERNP $ATi, $XA, RCCp.BToVSRC, Msk4Imm:$XMSK, 1529 Msk2Imm:$YMSK)>; 1530 def : Pat<(v512i1 (int_ppc_mma_pmxvf64gernn v512i1:$ATi, v256i1:$XA, v16i8:$XB, 1531 Msk4Imm:$XMSK, Msk2Imm:$YMSK)), 1532 (PMXVF64GERNN $ATi, $XA, RCCp.BToVSRC, Msk4Imm:$XMSK, 1533 Msk2Imm:$YMSK)>; 1534 1535 def : Pat<(v512i1 (int_ppc_mma_pmxvbf16ger2 v16i8:$XA, v16i8:$XB, Msk4Imm:$XMSK, 1536 Msk4Imm:$YMSK, Msk2Imm:$PMSK)), 1537 (PMXVBF16GER2 RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK, 1538 Msk4Imm:$YMSK, Msk2Imm:$PMSK)>; 1539 def : Pat<(v512i1 (int_ppc_mma_pmxvbf16ger2pp v512i1:$ATi, v16i8:$XA, v16i8:$XB, 1540 Msk4Imm:$XMSK, Msk4Imm:$YMSK, 1541 Msk2Imm:$PMSK)), 1542 (PMXVBF16GER2PP $ATi, RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK, 1543 Msk4Imm:$YMSK, Msk2Imm:$PMSK)>; 1544 def : Pat<(v512i1 (int_ppc_mma_pmxvbf16ger2pn v512i1:$ATi, v16i8:$XA, v16i8:$XB, 1545 Msk4Imm:$XMSK, Msk4Imm:$YMSK, 1546 Msk2Imm:$PMSK)), 1547 (PMXVBF16GER2PN $ATi, RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK, 1548 Msk4Imm:$YMSK, Msk2Imm:$PMSK)>; 1549 def : Pat<(v512i1 (int_ppc_mma_pmxvbf16ger2np v512i1:$ATi, v16i8:$XA, v16i8:$XB, 1550 Msk4Imm:$XMSK, Msk4Imm:$YMSK, 1551 Msk2Imm:$PMSK)), 1552 (PMXVBF16GER2NP $ATi, RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK, 1553 Msk4Imm:$YMSK, Msk2Imm:$PMSK)>; 1554 def : Pat<(v512i1 (int_ppc_mma_pmxvbf16ger2nn v512i1:$ATi, v16i8:$XA, v16i8:$XB, 1555 Msk4Imm:$XMSK, Msk4Imm:$YMSK, 1556 Msk2Imm:$PMSK)), 1557 (PMXVBF16GER2NN $ATi, RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK, 1558 Msk4Imm:$YMSK, Msk2Imm:$PMSK)>; 1559 def : Pat<(v512i1 (int_ppc_mma_pmxvi16ger2 v16i8:$XA, v16i8:$XB, Msk4Imm:$XMSK, 1560 Msk4Imm:$YMSK, Msk2Imm:$PMSK)), 1561 (PMXVI16GER2 RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK, 1562 Msk4Imm:$YMSK, Msk2Imm:$PMSK)>; 1563 def : Pat<(v512i1 (int_ppc_mma_pmxvi8ger4spp v512i1:$ATi, v16i8:$XA, v16i8:$XB, 1564 Msk4Imm:$XMSK, Msk4Imm:$YMSK, 1565 Msk2Imm:$PMSK)), 1566 (PMXVI8GER4SPP $ATi, RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK, 1567 Msk4Imm:$YMSK, Msk2Imm:$PMSK)>; 1568 def : Pat<(v512i1 (int_ppc_mma_pmxvi16ger2pp v512i1:$ATi, v16i8:$XA, v16i8:$XB, 1569 Msk4Imm:$XMSK, Msk4Imm:$YMSK, 1570 Msk2Imm:$PMSK)), 1571 (PMXVI16GER2PP $ATi, RCCp.AToVSRC, RCCp.BToVSRC, Msk4Imm:$XMSK, 1572 Msk4Imm:$YMSK, Msk2Imm:$PMSK)>; 1573} 1574 1575def Concats { 1576 dag VecsToVecPair0 = 1577 (v256i1 (INSERT_SUBREG 1578 (INSERT_SUBREG (IMPLICIT_DEF), $vs0, sub_vsx1), 1579 $vs1, sub_vsx0)); 1580 dag VecsToVecPair1 = 1581 (v256i1 (INSERT_SUBREG 1582 (INSERT_SUBREG (IMPLICIT_DEF), $vs2, sub_vsx1), 1583 $vs3, sub_vsx0)); 1584 dag VecsToVecQuad = 1585 (BUILD_UACC (INSERT_SUBREG 1586 (INSERT_SUBREG (v512i1 (IMPLICIT_DEF)), 1587 (KILL_PAIR VecsToVecPair0), sub_pair0), 1588 (KILL_PAIR VecsToVecPair1), sub_pair1)); 1589} 1590 1591def Extracts { 1592 dag Pair0 = (v256i1 (EXTRACT_SUBREG $v, sub_pair0)); 1593 dag Pair1 = (v256i1 (EXTRACT_SUBREG $v, sub_pair1)); 1594 dag Vec0 = (v4i32 (EXTRACT_SUBREG Pair0, sub_vsx0)); 1595 dag Vec1 = (v4i32 (EXTRACT_SUBREG Pair0, sub_vsx1)); 1596 dag Vec2 = (v4i32 (EXTRACT_SUBREG Pair1, sub_vsx0)); 1597 dag Vec3 = (v4i32 (EXTRACT_SUBREG Pair1, sub_vsx1)); 1598} 1599 1600let Predicates = [MMA] in { 1601 def : Pat<(v512i1 (PPCAccBuild v4i32:$vs1, v4i32:$vs0, v4i32:$vs3, v4i32:$vs2)), 1602 (XXMTACC Concats.VecsToVecQuad)>; 1603 def : Pat<(v512i1 (int_ppc_mma_assemble_acc v16i8:$vs1, v16i8:$vs0, 1604 v16i8:$vs3, v16i8:$vs2)), 1605 (XXMTACC Concats.VecsToVecQuad)>; 1606 def : Pat<(v512i1 (PPCxxmfacc v512i1:$AS)), (XXMFACC acc:$AS)>; 1607 def : Pat<(v4i32 (PPCAccExtractVsx acc:$v, (i64 0))), 1608 Extracts.Vec0>; 1609 def : Pat<(v4i32 (PPCAccExtractVsx acc:$v, (i64 1))), 1610 Extracts.Vec1>; 1611 def : Pat<(v4i32 (PPCAccExtractVsx acc:$v, (i64 2))), 1612 Extracts.Vec2>; 1613 def : Pat<(v4i32 (PPCAccExtractVsx acc:$v, (i64 3))), 1614 Extracts.Vec3>; 1615} 1616 1617let Predicates = [PairedVectorMemops] in { 1618 def : Pat<(v256i1 (PPCPairBuild v4i32:$vs1, v4i32:$vs0)), 1619 Concats.VecsToVecPair0>; 1620 def : Pat<(v256i1 (int_ppc_vsx_assemble_pair v16i8:$vs1, v16i8:$vs0)), 1621 Concats.VecsToVecPair0>; 1622 def : Pat<(v4i32 (PPCPairExtractVsx vsrpevenrc:$v, (i64 0))), 1623 (v4i32 (EXTRACT_SUBREG $v, sub_vsx0))>; 1624 def : Pat<(v4i32 (PPCPairExtractVsx vsrpevenrc:$v, (i64 1))), 1625 (v4i32 (EXTRACT_SUBREG $v, sub_vsx1))>; 1626} 1627 1628let mayLoad = 1, mayStore = 0, Predicates = [PairedVectorMemops] in { 1629 def LXVP : DQForm_XTp5_RA17_MEM<6, 0, (outs vsrprc:$XTp), 1630 (ins memrix16:$DQ_RA), "lxvp $XTp, $DQ_RA", 1631 IIC_LdStLFD, []>; 1632 def LXVPX : XForm_XTp5_XAB5<31, 333, (outs vsrprc:$XTp), (ins memrr:$src), 1633 "lxvpx $XTp, $src", IIC_LdStLFD, 1634 []>; 1635} 1636 1637let mayLoad = 0, mayStore = 1, Predicates = [PairedVectorMemops] in { 1638 def STXVP : DQForm_XTp5_RA17_MEM<6, 1, (outs), (ins vsrprc:$XTp, 1639 memrix16:$DQ_RA), "stxvp $XTp, $DQ_RA", 1640 IIC_LdStLFD, []>; 1641 def STXVPX : XForm_XTp5_XAB5<31, 461, (outs), (ins vsrprc:$XTp, memrr:$dst), 1642 "stxvpx $XTp, $dst", IIC_LdStLFD, 1643 []>; 1644} 1645 1646let mayLoad = 1, mayStore = 0, Predicates = [PairedVectorMemops, PrefixInstrs] in { 1647 defm PLXVP : 1648 8LS_DForm_R_XTp5_SI34_MEM_p<1, 58, (outs vsrprc:$XTp), (ins memri34:$D_RA), 1649 (ins memri34_pcrel:$D_RA), "plxvp $XTp, $D_RA", 1650 IIC_LdStLFD>; 1651} 1652 1653let mayLoad = 0, mayStore = 1, Predicates = [PairedVectorMemops, PrefixInstrs] in { 1654 defm PSTXVP : 1655 8LS_DForm_R_XTp5_SI34_MEM_p<1, 62, (outs), (ins vsrprc:$XTp, memri34:$D_RA), 1656 (ins vsrprc:$XTp, memri34_pcrel:$D_RA), 1657 "pstxvp $XTp, $D_RA", IIC_LdStLFD>; 1658} 1659 1660let Predicates = [PairedVectorMemops] in { 1661 // Intrinsics for Paired Vector Loads. 1662 def : Pat<(v256i1 (int_ppc_vsx_lxvp iaddrX16:$src)), (LXVP memrix16:$src)>; 1663 def : Pat<(v256i1 (int_ppc_vsx_lxvp xaddrX16:$src)), (LXVPX xaddrX16:$src)>; 1664 let Predicates = [PairedVectorMemops, PrefixInstrs] in { 1665 def : Pat<(v256i1 (int_ppc_vsx_lxvp iaddrX34:$src)), (PLXVP memri34:$src)>; 1666 } 1667 // Intrinsics for Paired Vector Stores. 1668 def : Pat<(int_ppc_vsx_stxvp v256i1:$XSp, iaddrX16:$dst), 1669 (STXVP $XSp, memrix16:$dst)>; 1670 def : Pat<(int_ppc_vsx_stxvp v256i1:$XSp, xaddrX16:$dst), 1671 (STXVPX $XSp, xaddrX16:$dst)>; 1672 let Predicates = [PairedVectorMemops, PrefixInstrs] in { 1673 def : Pat<(int_ppc_vsx_stxvp v256i1:$XSp, iaddrX34:$dst), 1674 (PSTXVP $XSp, memri34:$dst)>; 1675 } 1676} 1677 1678// TODO: We have an added complexity of 500 here. This is only a temporary 1679// solution to have tablegen consider these patterns first. The way we do 1680// addressing for PowerPC is complex depending on available D form, X form, or 1681// aligned D form loads/stores like DS and DQ forms. The prefixed 1682// instructions in this file also add additional PC Relative loads/stores 1683// and D form loads/stores with 34 bit immediates. It is very difficult to force 1684// instruction selection to consistently pick these first without the current 1685// added complexity. Once pc-relative implementation is complete, a set of 1686// follow-up patches will address this refactoring and the AddedComplexity will 1687// be removed. 1688let Predicates = [PCRelativeMemops], AddedComplexity = 500 in { 1689 // Load i32 1690 def : Pat<(i32 (zextloadi8 (PPCmatpcreladdr pcreladdr:$ga))), 1691 (PLBZpc $ga, 0)>; 1692 def : Pat<(i32 (extloadi8 (PPCmatpcreladdr pcreladdr:$ga))), 1693 (PLBZpc $ga, 0)>; 1694 def : Pat<(i32 (sextloadi16 (PPCmatpcreladdr pcreladdr:$ga))), 1695 (PLHApc $ga, 0)>; 1696 def : Pat<(i32 (zextloadi16 (PPCmatpcreladdr pcreladdr:$ga))), 1697 (PLHZpc $ga, 0)>; 1698 def : Pat<(i32 (extloadi16 (PPCmatpcreladdr pcreladdr:$ga))), 1699 (PLHZpc $ga, 0)>; 1700 def : Pat<(i32 (load (PPCmatpcreladdr pcreladdr:$ga))), (PLWZpc $ga, 0)>; 1701 1702 // Store i32 1703 def : Pat<(truncstorei8 i32:$RS, (PPCmatpcreladdr pcreladdr:$ga)), 1704 (PSTBpc $RS, $ga, 0)>; 1705 def : Pat<(truncstorei16 i32:$RS, (PPCmatpcreladdr pcreladdr:$ga)), 1706 (PSTHpc $RS, $ga, 0)>; 1707 def : Pat<(store i32:$RS, (PPCmatpcreladdr pcreladdr:$ga)), 1708 (PSTWpc $RS, $ga, 0)>; 1709 1710 // Load i64 1711 def : Pat<(i64 (zextloadi8 (PPCmatpcreladdr pcreladdr:$ga))), 1712 (PLBZ8pc $ga, 0)>; 1713 def : Pat<(i64 (extloadi8 (PPCmatpcreladdr pcreladdr:$ga))), 1714 (PLBZ8pc $ga, 0)>; 1715 def : Pat<(i64 (sextloadi16 (PPCmatpcreladdr pcreladdr:$ga))), 1716 (PLHA8pc $ga, 0)>; 1717 def : Pat<(i64 (zextloadi16 (PPCmatpcreladdr pcreladdr:$ga))), 1718 (PLHZ8pc $ga, 0)>; 1719 def : Pat<(i64 (extloadi16 (PPCmatpcreladdr pcreladdr:$ga))), 1720 (PLHZ8pc $ga, 0)>; 1721 def : Pat<(i64 (zextloadi32 (PPCmatpcreladdr pcreladdr:$ga))), 1722 (PLWZ8pc $ga, 0)>; 1723 def : Pat<(i64 (sextloadi32 (PPCmatpcreladdr pcreladdr:$ga))), 1724 (PLWA8pc $ga, 0)>; 1725 def : Pat<(i64 (extloadi32 (PPCmatpcreladdr pcreladdr:$ga))), 1726 (PLWZ8pc $ga, 0)>; 1727 def : Pat<(i64 (load (PPCmatpcreladdr pcreladdr:$ga))), (PLDpc $ga, 0)>; 1728 1729 // Store i64 1730 def : Pat<(truncstorei8 i64:$RS, (PPCmatpcreladdr pcreladdr:$ga)), 1731 (PSTB8pc $RS, $ga, 0)>; 1732 def : Pat<(truncstorei16 i64:$RS, (PPCmatpcreladdr pcreladdr:$ga)), 1733 (PSTH8pc $RS, $ga, 0)>; 1734 def : Pat<(truncstorei32 i64:$RS, (PPCmatpcreladdr pcreladdr:$ga)), 1735 (PSTW8pc $RS, $ga, 0)>; 1736 def : Pat<(store i64:$RS, (PPCmatpcreladdr pcreladdr:$ga)), 1737 (PSTDpc $RS, $ga, 0)>; 1738 1739 // Load f32 1740 def : Pat<(f32 (load (PPCmatpcreladdr pcreladdr:$addr))), (PLFSpc $addr, 0)>; 1741 1742 // Store f32 1743 def : Pat<(store f32:$FRS, (PPCmatpcreladdr pcreladdr:$ga)), 1744 (PSTFSpc $FRS, $ga, 0)>; 1745 1746 // Load f64 1747 def : Pat<(f64 (extloadf32 (PPCmatpcreladdr pcreladdr:$addr))), 1748 (COPY_TO_REGCLASS (PLFSpc $addr, 0), VSFRC)>; 1749 def : Pat<(f64 (load (PPCmatpcreladdr pcreladdr:$addr))), (PLFDpc $addr, 0)>; 1750 1751 // Store f64 1752 def : Pat<(store f64:$FRS, (PPCmatpcreladdr pcreladdr:$ga)), 1753 (PSTFDpc $FRS, $ga, 0)>; 1754 1755 // Load f128 1756 def : Pat<(f128 (load (PPCmatpcreladdr pcreladdr:$addr))), 1757 (COPY_TO_REGCLASS (PLXVpc $addr, 0), VRRC)>; 1758 1759 // Store f128 1760 def : Pat<(store f128:$XS, (PPCmatpcreladdr pcreladdr:$ga)), 1761 (PSTXVpc (COPY_TO_REGCLASS $XS, VSRC), $ga, 0)>; 1762 1763 // Load v4i32 1764 def : Pat<(v4i32 (load (PPCmatpcreladdr pcreladdr:$addr))), (PLXVpc $addr, 0)>; 1765 1766 // Store v4i32 1767 def : Pat<(store v4i32:$XS, (PPCmatpcreladdr pcreladdr:$ga)), 1768 (PSTXVpc $XS, $ga, 0)>; 1769 1770 // Load v2i64 1771 def : Pat<(v2i64 (load (PPCmatpcreladdr pcreladdr:$addr))), (PLXVpc $addr, 0)>; 1772 1773 // Store v2i64 1774 def : Pat<(store v2i64:$XS, (PPCmatpcreladdr pcreladdr:$ga)), 1775 (PSTXVpc $XS, $ga, 0)>; 1776 1777 // Load v4f32 1778 def : Pat<(v4f32 (load (PPCmatpcreladdr pcreladdr:$addr))), (PLXVpc $addr, 0)>; 1779 1780 // Store v4f32 1781 def : Pat<(store v4f32:$XS, (PPCmatpcreladdr pcreladdr:$ga)), 1782 (PSTXVpc $XS, $ga, 0)>; 1783 1784 // Load v2f64 1785 def : Pat<(v2f64 (load (PPCmatpcreladdr pcreladdr:$addr))), (PLXVpc $addr, 0)>; 1786 1787 // Store v2f64 1788 def : Pat<(store v2f64:$XS, (PPCmatpcreladdr pcreladdr:$ga)), 1789 (PSTXVpc $XS, $ga, 0)>; 1790 1791 // Atomic Load 1792 def : Pat<(atomic_load_8 (PPCmatpcreladdr pcreladdr:$ga)), 1793 (PLBZpc $ga, 0)>; 1794 def : Pat<(atomic_load_16 (PPCmatpcreladdr pcreladdr:$ga)), 1795 (PLHZpc $ga, 0)>; 1796 def : Pat<(atomic_load_32 (PPCmatpcreladdr pcreladdr:$ga)), 1797 (PLWZpc $ga, 0)>; 1798 def : Pat<(atomic_load_64 (PPCmatpcreladdr pcreladdr:$ga)), 1799 (PLDpc $ga, 0)>; 1800 1801 // Atomic Store 1802 def : Pat<(atomic_store_8 (PPCmatpcreladdr pcreladdr:$ga), i32:$RS), 1803 (PSTBpc $RS, $ga, 0)>; 1804 def : Pat<(atomic_store_16 (PPCmatpcreladdr pcreladdr:$ga), i32:$RS), 1805 (PSTHpc $RS, $ga, 0)>; 1806 def : Pat<(atomic_store_32 (PPCmatpcreladdr pcreladdr:$ga), i32:$RS), 1807 (PSTWpc $RS, $ga, 0)>; 1808 def : Pat<(atomic_store_8 (PPCmatpcreladdr pcreladdr:$ga), i64:$RS), 1809 (PSTB8pc $RS, $ga, 0)>; 1810 def : Pat<(atomic_store_16 (PPCmatpcreladdr pcreladdr:$ga), i64:$RS), 1811 (PSTH8pc $RS, $ga, 0)>; 1812 def : Pat<(atomic_store_32 (PPCmatpcreladdr pcreladdr:$ga), i64:$RS), 1813 (PSTW8pc $RS, $ga, 0)>; 1814 def : Pat<(atomic_store_64 (PPCmatpcreladdr pcreladdr:$ga), i64:$RS), 1815 (PSTDpc $RS, $ga, 0)>; 1816 1817 // Special Cases For PPCstore_scal_int_from_vsr 1818 def : Pat<(PPCstore_scal_int_from_vsr 1819 (f64 (PPCcv_fp_to_sint_in_vsr f64:$src)), 1820 (PPCmatpcreladdr pcreladdr:$dst), 8), 1821 (PSTXSDpc (XSCVDPSXDS f64:$src), $dst, 0)>; 1822 def : Pat<(PPCstore_scal_int_from_vsr 1823 (f64 (PPCcv_fp_to_sint_in_vsr f128:$src)), 1824 (PPCmatpcreladdr pcreladdr:$dst), 8), 1825 (PSTXSDpc (COPY_TO_REGCLASS (XSCVQPSDZ f128:$src), VFRC), $dst, 0)>; 1826 1827 def : Pat<(PPCstore_scal_int_from_vsr 1828 (f64 (PPCcv_fp_to_uint_in_vsr f64:$src)), 1829 (PPCmatpcreladdr pcreladdr:$dst), 8), 1830 (PSTXSDpc (XSCVDPUXDS f64:$src), $dst, 0)>; 1831 def : Pat<(PPCstore_scal_int_from_vsr 1832 (f64 (PPCcv_fp_to_uint_in_vsr f128:$src)), 1833 (PPCmatpcreladdr pcreladdr:$dst), 8), 1834 (PSTXSDpc (COPY_TO_REGCLASS (XSCVQPUDZ f128:$src), VFRC), $dst, 0)>; 1835 1836 // If the PPCmatpcreladdr node is not caught by any other pattern it should be 1837 // caught here and turned into a paddi instruction to materialize the address. 1838 def : Pat<(PPCmatpcreladdr pcreladdr:$addr), (PADDI8pc 0, $addr)>; 1839 // PPCtlsdynamatpcreladdr node is used for TLS dynamic models to materialize 1840 // tls global address with paddi instruction. 1841 def : Pat<(PPCtlsdynamatpcreladdr pcreladdr:$addr), (PADDI8pc 0, $addr)>; 1842 // PPCtlslocalexecmataddr node is used for TLS local exec models to 1843 // materialize tls global address with paddi instruction. 1844 def : Pat<(PPCaddTls i64:$in, (PPCtlslocalexecmataddr tglobaltlsaddr:$addr)), 1845 (PADDI8 $in, $addr)>; 1846} 1847 1848let Predicates = [PrefixInstrs] in { 1849 def XXSPLTIW : 8RR_DForm_IMM32_XT6<32, 3, (outs vsrc:$XT), 1850 (ins i32imm:$IMM32), 1851 "xxspltiw $XT, $IMM32", IIC_VecGeneral, 1852 []>; 1853 def XXSPLTIDP : 8RR_DForm_IMM32_XT6<32, 2, (outs vsrc:$XT), 1854 (ins i32imm:$IMM32), 1855 "xxspltidp $XT, $IMM32", IIC_VecGeneral, 1856 [(set v2f64:$XT, 1857 (PPCxxspltidp i32:$IMM32))]>; 1858 def XXSPLTI32DX : 1859 8RR_DForm_IMM32_XT6_IX<32, 0, (outs vsrc:$XT), 1860 (ins vsrc:$XTi, u1imm:$IX, i32imm:$IMM32), 1861 "xxsplti32dx $XT, $IX, $IMM32", IIC_VecGeneral, 1862 [(set v2i64:$XT, 1863 (PPCxxsplti32dx v2i64:$XTi, i32:$IX, 1864 i32:$IMM32))]>, 1865 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">; 1866 def XXPERMX : 1867 8RR_XX4Form_IMM3_XTABC6<34, 0, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB, 1868 vsrc:$XC, u3imm:$UIM), 1869 "xxpermx $XT, $XA, $XB, $XC, $UIM", 1870 IIC_VecPerm, []>; 1871 def XXBLENDVB : 1872 8RR_XX4Form_XTABC6<33, 0, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB, 1873 vsrc:$XC), "xxblendvb $XT, $XA, $XB, $XC", 1874 IIC_VecGeneral, []>; 1875 def XXBLENDVH : 1876 8RR_XX4Form_XTABC6<33, 1, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB, 1877 vsrc:$XC), "xxblendvh $XT, $XA, $XB, $XC", 1878 IIC_VecGeneral, []>; 1879 def XXBLENDVW : 1880 8RR_XX4Form_XTABC6<33, 2, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB, 1881 vsrc:$XC), "xxblendvw $XT, $XA, $XB, $XC", 1882 IIC_VecGeneral, []>; 1883 def XXBLENDVD : 1884 8RR_XX4Form_XTABC6<33, 3, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB, 1885 vsrc:$XC), "xxblendvd $XT, $XA, $XB, $XC", 1886 IIC_VecGeneral, []>; 1887} 1888 1889let Predicates = [IsISA3_1] in { 1890 def SETBC : XForm_XT5_BI5<31, 384, (outs gprc:$RT), (ins crbitrc:$BI), 1891 "setbc $RT, $BI", IIC_IntCompare, []>; 1892 def SETBCR : XForm_XT5_BI5<31, 416, (outs gprc:$RT), (ins crbitrc:$BI), 1893 "setbcr $RT, $BI", IIC_IntCompare, []>; 1894 def SETNBC : XForm_XT5_BI5<31, 448, (outs gprc:$RT), (ins crbitrc:$BI), 1895 "setnbc $RT, $BI", IIC_IntCompare, []>; 1896 def SETNBCR : XForm_XT5_BI5<31, 480, (outs gprc:$RT), (ins crbitrc:$BI), 1897 "setnbcr $RT, $BI", IIC_IntCompare, []>; 1898 1899 let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 1900 def SETBC8 : XForm_XT5_BI5<31, 384, (outs g8rc:$RT), (ins crbitrc:$BI), 1901 "setbc $RT, $BI", IIC_IntCompare, []>; 1902 def SETBCR8 : XForm_XT5_BI5<31, 416, (outs g8rc:$RT), (ins crbitrc:$BI), 1903 "setbcr $RT, $BI", IIC_IntCompare, []>; 1904 def SETNBC8 : XForm_XT5_BI5<31, 448, (outs g8rc:$RT), (ins crbitrc:$BI), 1905 "setnbc $RT, $BI", IIC_IntCompare, []>; 1906 def SETNBCR8 : XForm_XT5_BI5<31, 480, (outs g8rc:$RT), (ins crbitrc:$BI), 1907 "setnbcr $RT, $BI", IIC_IntCompare, []>; 1908 } 1909 1910 def VSLDBI : VNForm_VTAB5_SD3<22, 0, (outs vrrc:$VRT), 1911 (ins vrrc:$VRA, vrrc:$VRB, u3imm:$SH), 1912 "vsldbi $VRT, $VRA, $VRB, $SH", 1913 IIC_VecGeneral, 1914 [(set v16i8:$VRT, 1915 (int_ppc_altivec_vsldbi v16i8:$VRA, 1916 v16i8:$VRB, 1917 i32:$SH))]>; 1918 def VSRDBI : VNForm_VTAB5_SD3<22, 1, (outs vrrc:$VRT), 1919 (ins vrrc:$VRA, vrrc:$VRB, u3imm:$SH), 1920 "vsrdbi $VRT, $VRA, $VRB, $SH", 1921 IIC_VecGeneral, 1922 [(set v16i8:$VRT, 1923 (int_ppc_altivec_vsrdbi v16i8:$VRA, 1924 v16i8:$VRB, 1925 i32:$SH))]>; 1926 defm VSTRIBR : VXForm_VTB5_RCr<13, 1, (outs vrrc:$vT), (ins vrrc:$vB), 1927 "vstribr", "$vT, $vB", IIC_VecGeneral, 1928 [(set v16i8:$vT, 1929 (int_ppc_altivec_vstribr v16i8:$vB))]>; 1930 defm VSTRIBL : VXForm_VTB5_RCr<13, 0, (outs vrrc:$vT), (ins vrrc:$vB), 1931 "vstribl", "$vT, $vB", IIC_VecGeneral, 1932 [(set v16i8:$vT, 1933 (int_ppc_altivec_vstribl v16i8:$vB))]>; 1934 defm VSTRIHR : VXForm_VTB5_RCr<13, 3, (outs vrrc:$vT), (ins vrrc:$vB), 1935 "vstrihr", "$vT, $vB", IIC_VecGeneral, 1936 [(set v8i16:$vT, 1937 (int_ppc_altivec_vstrihr v8i16:$vB))]>; 1938 defm VSTRIHL : VXForm_VTB5_RCr<13, 2, (outs vrrc:$vT), (ins vrrc:$vB), 1939 "vstrihl", "$vT, $vB", IIC_VecGeneral, 1940 [(set v8i16:$vT, 1941 (int_ppc_altivec_vstrihl v8i16:$vB))]>; 1942 def VINSW : 1943 VXForm_1<207, (outs vrrc:$vD), (ins vrrc:$vDi, u4imm:$UIM, gprc:$rB), 1944 "vinsw $vD, $rB, $UIM", IIC_VecGeneral, 1945 [(set v4i32:$vD, 1946 (int_ppc_altivec_vinsw v4i32:$vDi, i32:$rB, timm:$UIM))]>, 1947 RegConstraint<"$vDi = $vD">, NoEncode<"$vDi">; 1948 def VINSD : 1949 VXForm_1<463, (outs vrrc:$vD), (ins vrrc:$vDi, u4imm:$UIM, g8rc:$rB), 1950 "vinsd $vD, $rB, $UIM", IIC_VecGeneral, 1951 [(set v2i64:$vD, 1952 (int_ppc_altivec_vinsd v2i64:$vDi, i64:$rB, timm:$UIM))]>, 1953 RegConstraint<"$vDi = $vD">, NoEncode<"$vDi">; 1954 def VINSBVLX : 1955 VXForm_VTB5_RA5_ins<15, "vinsbvlx", 1956 [(set v16i8:$vD, 1957 (int_ppc_altivec_vinsbvlx v16i8:$vDi, i32:$rA, 1958 v16i8:$vB))]>; 1959 def VINSBVRX : 1960 VXForm_VTB5_RA5_ins<271, "vinsbvrx", 1961 [(set v16i8:$vD, 1962 (int_ppc_altivec_vinsbvrx v16i8:$vDi, i32:$rA, 1963 v16i8:$vB))]>; 1964 def VINSHVLX : 1965 VXForm_VTB5_RA5_ins<79, "vinshvlx", 1966 [(set v8i16:$vD, 1967 (int_ppc_altivec_vinshvlx v8i16:$vDi, i32:$rA, 1968 v8i16:$vB))]>; 1969 def VINSHVRX : 1970 VXForm_VTB5_RA5_ins<335, "vinshvrx", 1971 [(set v8i16:$vD, 1972 (int_ppc_altivec_vinshvrx v8i16:$vDi, i32:$rA, 1973 v8i16:$vB))]>; 1974 def VINSWVLX : 1975 VXForm_VTB5_RA5_ins<143, "vinswvlx", 1976 [(set v4i32:$vD, 1977 (int_ppc_altivec_vinswvlx v4i32:$vDi, i32:$rA, 1978 v4i32:$vB))]>; 1979 def VINSWVRX : 1980 VXForm_VTB5_RA5_ins<399, "vinswvrx", 1981 [(set v4i32:$vD, 1982 (int_ppc_altivec_vinswvrx v4i32:$vDi, i32:$rA, 1983 v4i32:$vB))]>; 1984 def VINSBLX : 1985 VXForm_VRT5_RAB5_ins<527, "vinsblx", 1986 [(set v16i8:$vD, 1987 (int_ppc_altivec_vinsblx v16i8:$vDi, i32:$rA, 1988 i32:$rB))]>; 1989 def VINSBRX : 1990 VXForm_VRT5_RAB5_ins<783, "vinsbrx", 1991 [(set v16i8:$vD, 1992 (int_ppc_altivec_vinsbrx v16i8:$vDi, i32:$rA, 1993 i32:$rB))]>; 1994 def VINSHLX : 1995 VXForm_VRT5_RAB5_ins<591, "vinshlx", 1996 [(set v8i16:$vD, 1997 (int_ppc_altivec_vinshlx v8i16:$vDi, i32:$rA, 1998 i32:$rB))]>; 1999 def VINSHRX : 2000 VXForm_VRT5_RAB5_ins<847, "vinshrx", 2001 [(set v8i16:$vD, 2002 (int_ppc_altivec_vinshrx v8i16:$vDi, i32:$rA, 2003 i32:$rB))]>; 2004 def VINSWLX : 2005 VXForm_VRT5_RAB5_ins<655, "vinswlx", 2006 [(set v4i32:$vD, 2007 (int_ppc_altivec_vinswlx v4i32:$vDi, i32:$rA, 2008 i32:$rB))]>; 2009 def VINSWRX : 2010 VXForm_VRT5_RAB5_ins<911, "vinswrx", 2011 [(set v4i32:$vD, 2012 (int_ppc_altivec_vinswrx v4i32:$vDi, i32:$rA, 2013 i32:$rB))]>; 2014 def VINSDLX : 2015 VXForm_1<719, (outs vrrc:$vD), (ins vrrc:$vDi, g8rc:$rA, g8rc:$rB), 2016 "vinsdlx $vD, $rA, $rB", IIC_VecGeneral, 2017 [(set v2i64:$vD, 2018 (int_ppc_altivec_vinsdlx v2i64:$vDi, i64:$rA, i64:$rB))]>, 2019 RegConstraint<"$vDi = $vD">, NoEncode<"$vDi">; 2020 def VINSDRX : 2021 VXForm_1<975, (outs vrrc:$vD), (ins vrrc:$vDi, g8rc:$rA, g8rc:$rB), 2022 "vinsdrx $vD, $rA, $rB", IIC_VecGeneral, 2023 [(set v2i64:$vD, 2024 (int_ppc_altivec_vinsdrx v2i64:$vDi, i64:$rA, i64:$rB))]>, 2025 RegConstraint<"$vDi = $vD">, NoEncode<"$vDi">; 2026 def VEXTRACTBM : VXForm_RD5_XO5_RS5<1602, 8, (outs gprc:$rD), (ins vrrc:$vB), 2027 "vextractbm $rD, $vB", IIC_VecGeneral, 2028 [(set i32:$rD, 2029 (int_ppc_altivec_vextractbm v16i8:$vB))]>; 2030 def VEXTRACTHM : VXForm_RD5_XO5_RS5<1602, 9, (outs gprc:$rD), (ins vrrc:$vB), 2031 "vextracthm $rD, $vB", IIC_VecGeneral, 2032 [(set i32:$rD, 2033 (int_ppc_altivec_vextracthm v8i16:$vB))]>; 2034 def VEXTRACTWM : VXForm_RD5_XO5_RS5<1602, 10, (outs gprc:$rD), (ins vrrc:$vB), 2035 "vextractwm $rD, $vB", IIC_VecGeneral, 2036 [(set i32:$rD, 2037 (int_ppc_altivec_vextractwm v4i32:$vB))]>; 2038 def VEXTRACTDM : VXForm_RD5_XO5_RS5<1602, 11, (outs gprc:$rD), (ins vrrc:$vB), 2039 "vextractdm $rD, $vB", IIC_VecGeneral, 2040 [(set i32:$rD, 2041 (int_ppc_altivec_vextractdm v2i64:$vB))]>; 2042 def VEXTRACTQM : VXForm_RD5_XO5_RS5<1602, 12, (outs gprc:$rD), (ins vrrc:$vB), 2043 "vextractqm $rD, $vB", IIC_VecGeneral, 2044 [(set i32:$rD, 2045 (int_ppc_altivec_vextractqm v1i128:$vB))]>; 2046 def VEXPANDBM : VXForm_RD5_XO5_RS5<1602, 0, (outs vrrc:$vD), (ins vrrc:$vB), 2047 "vexpandbm $vD, $vB", IIC_VecGeneral, 2048 [(set v16i8:$vD, (int_ppc_altivec_vexpandbm 2049 v16i8:$vB))]>; 2050 def VEXPANDHM : VXForm_RD5_XO5_RS5<1602, 1, (outs vrrc:$vD), (ins vrrc:$vB), 2051 "vexpandhm $vD, $vB", IIC_VecGeneral, 2052 [(set v8i16:$vD, (int_ppc_altivec_vexpandhm 2053 v8i16:$vB))]>; 2054 def VEXPANDWM : VXForm_RD5_XO5_RS5<1602, 2, (outs vrrc:$vD), (ins vrrc:$vB), 2055 "vexpandwm $vD, $vB", IIC_VecGeneral, 2056 [(set v4i32:$vD, (int_ppc_altivec_vexpandwm 2057 v4i32:$vB))]>; 2058 def VEXPANDDM : VXForm_RD5_XO5_RS5<1602, 3, (outs vrrc:$vD), (ins vrrc:$vB), 2059 "vexpanddm $vD, $vB", IIC_VecGeneral, 2060 [(set v2i64:$vD, (int_ppc_altivec_vexpanddm 2061 v2i64:$vB))]>; 2062 def VEXPANDQM : VXForm_RD5_XO5_RS5<1602, 4, (outs vrrc:$vD), (ins vrrc:$vB), 2063 "vexpandqm $vD, $vB", IIC_VecGeneral, 2064 [(set v1i128:$vD, (int_ppc_altivec_vexpandqm 2065 v1i128:$vB))]>; 2066 def MTVSRBM : VXForm_RD5_XO5_RS5<1602, 16, (outs vrrc:$vD), (ins g8rc:$rB), 2067 "mtvsrbm $vD, $rB", IIC_VecGeneral, 2068 [(set v16i8:$vD, 2069 (int_ppc_altivec_mtvsrbm i64:$rB))]>; 2070 def MTVSRHM : VXForm_RD5_XO5_RS5<1602, 17, (outs vrrc:$vD), (ins g8rc:$rB), 2071 "mtvsrhm $vD, $rB", IIC_VecGeneral, 2072 [(set v8i16:$vD, 2073 (int_ppc_altivec_mtvsrhm i64:$rB))]>; 2074 def MTVSRWM : VXForm_RD5_XO5_RS5<1602, 18, (outs vrrc:$vD), (ins g8rc:$rB), 2075 "mtvsrwm $vD, $rB", IIC_VecGeneral, 2076 [(set v4i32:$vD, 2077 (int_ppc_altivec_mtvsrwm i64:$rB))]>; 2078 def MTVSRDM : VXForm_RD5_XO5_RS5<1602, 19, (outs vrrc:$vD), (ins g8rc:$rB), 2079 "mtvsrdm $vD, $rB", IIC_VecGeneral, 2080 [(set v2i64:$vD, 2081 (int_ppc_altivec_mtvsrdm i64:$rB))]>; 2082 def MTVSRQM : VXForm_RD5_XO5_RS5<1602, 20, (outs vrrc:$vD), (ins g8rc:$rB), 2083 "mtvsrqm $vD, $rB", IIC_VecGeneral, 2084 [(set v1i128:$vD, 2085 (int_ppc_altivec_mtvsrqm i64:$rB))]>; 2086 def MTVSRBMI : DXForm<4, 10, (outs vrrc:$vD), (ins u16imm64:$D), 2087 "mtvsrbmi $vD, $D", IIC_VecGeneral, 2088 [(set v16i8:$vD, 2089 (int_ppc_altivec_mtvsrbm imm:$D))]>; 2090 def VCNTMBB : VXForm_RD5_MP_VB5<1602, 12, (outs g8rc:$rD), 2091 (ins vrrc:$vB, u1imm:$MP), 2092 "vcntmbb $rD, $vB, $MP", IIC_VecGeneral, 2093 [(set i64:$rD, (int_ppc_altivec_vcntmbb 2094 v16i8:$vB, timm:$MP))]>; 2095 def VCNTMBH : VXForm_RD5_MP_VB5<1602, 13, (outs g8rc:$rD), 2096 (ins vrrc:$vB, u1imm:$MP), 2097 "vcntmbh $rD, $vB, $MP", IIC_VecGeneral, 2098 [(set i64:$rD, (int_ppc_altivec_vcntmbh 2099 v8i16:$vB, timm:$MP))]>; 2100 def VCNTMBW : VXForm_RD5_MP_VB5<1602, 14, (outs g8rc:$rD), 2101 (ins vrrc:$vB, u1imm:$MP), 2102 "vcntmbw $rD, $vB, $MP", IIC_VecGeneral, 2103 [(set i64:$rD, (int_ppc_altivec_vcntmbw 2104 v4i32:$vB, timm:$MP))]>; 2105 def VCNTMBD : VXForm_RD5_MP_VB5<1602, 15, (outs g8rc:$rD), 2106 (ins vrrc:$vB, u1imm:$MP), 2107 "vcntmbd $rD, $vB, $MP", IIC_VecGeneral, 2108 [(set i64:$rD, (int_ppc_altivec_vcntmbd 2109 v2i64:$vB, timm:$MP))]>; 2110 def VEXTDUBVLX : VAForm_1a<24, (outs vrrc:$vD), 2111 (ins vrrc:$vA, vrrc:$vB, gprc:$rC), 2112 "vextdubvlx $vD, $vA, $vB, $rC", 2113 IIC_VecGeneral, 2114 [(set v2i64:$vD, 2115 (int_ppc_altivec_vextdubvlx v16i8:$vA, 2116 v16i8:$vB, 2117 i32:$rC))]>; 2118 def VEXTDUBVRX : VAForm_1a<25, (outs vrrc:$vD), 2119 (ins vrrc:$vA, vrrc:$vB, gprc:$rC), 2120 "vextdubvrx $vD, $vA, $vB, $rC", 2121 IIC_VecGeneral, 2122 [(set v2i64:$vD, 2123 (int_ppc_altivec_vextdubvrx v16i8:$vA, 2124 v16i8:$vB, 2125 i32:$rC))]>; 2126 def VEXTDUHVLX : VAForm_1a<26, (outs vrrc:$vD), 2127 (ins vrrc:$vA, vrrc:$vB, gprc:$rC), 2128 "vextduhvlx $vD, $vA, $vB, $rC", 2129 IIC_VecGeneral, 2130 [(set v2i64:$vD, 2131 (int_ppc_altivec_vextduhvlx v8i16:$vA, 2132 v8i16:$vB, 2133 i32:$rC))]>; 2134 def VEXTDUHVRX : VAForm_1a<27, (outs vrrc:$vD), 2135 (ins vrrc:$vA, vrrc:$vB, gprc:$rC), 2136 "vextduhvrx $vD, $vA, $vB, $rC", 2137 IIC_VecGeneral, 2138 [(set v2i64:$vD, 2139 (int_ppc_altivec_vextduhvrx v8i16:$vA, 2140 v8i16:$vB, 2141 i32:$rC))]>; 2142 def VEXTDUWVLX : VAForm_1a<28, (outs vrrc:$vD), 2143 (ins vrrc:$vA, vrrc:$vB, gprc:$rC), 2144 "vextduwvlx $vD, $vA, $vB, $rC", 2145 IIC_VecGeneral, 2146 [(set v2i64:$vD, 2147 (int_ppc_altivec_vextduwvlx v4i32:$vA, 2148 v4i32:$vB, 2149 i32:$rC))]>; 2150 def VEXTDUWVRX : VAForm_1a<29, (outs vrrc:$vD), 2151 (ins vrrc:$vA, vrrc:$vB, gprc:$rC), 2152 "vextduwvrx $vD, $vA, $vB, $rC", 2153 IIC_VecGeneral, 2154 [(set v2i64:$vD, 2155 (int_ppc_altivec_vextduwvrx v4i32:$vA, 2156 v4i32:$vB, 2157 i32:$rC))]>; 2158 def VEXTDDVLX : VAForm_1a<30, (outs vrrc:$vD), 2159 (ins vrrc:$vA, vrrc:$vB, gprc:$rC), 2160 "vextddvlx $vD, $vA, $vB, $rC", 2161 IIC_VecGeneral, 2162 [(set v2i64:$vD, 2163 (int_ppc_altivec_vextddvlx v2i64:$vA, 2164 v2i64:$vB, 2165 i32:$rC))]>; 2166 def VEXTDDVRX : VAForm_1a<31, (outs vrrc:$vD), 2167 (ins vrrc:$vA, vrrc:$vB, gprc:$rC), 2168 "vextddvrx $vD, $vA, $vB, $rC", 2169 IIC_VecGeneral, 2170 [(set v2i64:$vD, 2171 (int_ppc_altivec_vextddvrx v2i64:$vA, 2172 v2i64:$vB, 2173 i32:$rC))]>; 2174 def VPDEPD : VXForm_1<1485, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 2175 "vpdepd $vD, $vA, $vB", IIC_VecGeneral, 2176 [(set v2i64:$vD, 2177 (int_ppc_altivec_vpdepd v2i64:$vA, v2i64:$vB))]>; 2178 def VPEXTD : VXForm_1<1421, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 2179 "vpextd $vD, $vA, $vB", IIC_VecGeneral, 2180 [(set v2i64:$vD, 2181 (int_ppc_altivec_vpextd v2i64:$vA, v2i64:$vB))]>; 2182 def PDEPD : XForm_6<31, 156, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 2183 "pdepd $rA, $rS, $rB", IIC_IntGeneral, 2184 [(set i64:$rA, (int_ppc_pdepd i64:$rS, i64:$rB))]>; 2185 def PEXTD : XForm_6<31, 188, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 2186 "pextd $rA, $rS, $rB", IIC_IntGeneral, 2187 [(set i64:$rA, (int_ppc_pextd i64:$rS, i64:$rB))]>; 2188 def VCFUGED : VXForm_1<1357, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 2189 "vcfuged $vD, $vA, $vB", IIC_VecGeneral, 2190 [(set v2i64:$vD, 2191 (int_ppc_altivec_vcfuged v2i64:$vA, v2i64:$vB))]>; 2192 def VGNB : VXForm_RD5_N3_VB5<1228, (outs g8rc:$rD), (ins vrrc:$vB, u3imm:$N), 2193 "vgnb $rD, $vB, $N", IIC_VecGeneral, 2194 [(set i64:$rD, 2195 (int_ppc_altivec_vgnb v1i128:$vB, timm:$N))]>; 2196 def CFUGED : XForm_6<31, 220, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 2197 "cfuged $rA, $rS, $rB", IIC_IntGeneral, 2198 [(set i64:$rA, (int_ppc_cfuged i64:$rS, i64:$rB))]>; 2199 def XXEVAL : 2200 8RR_XX4Form_IMM8_XTAB6<34, 1, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB, 2201 vsrc:$XC, u8imm:$IMM), 2202 "xxeval $XT, $XA, $XB, $XC, $IMM", IIC_VecGeneral, 2203 [(set v2i64:$XT, (int_ppc_vsx_xxeval v2i64:$XA, 2204 v2i64:$XB, v2i64:$XC, timm:$IMM))]>; 2205 def VCLZDM : VXForm_1<1924, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 2206 "vclzdm $vD, $vA, $vB", IIC_VecGeneral, 2207 [(set v2i64:$vD, 2208 (int_ppc_altivec_vclzdm v2i64:$vA, v2i64:$vB))]>; 2209 def VCTZDM : VXForm_1<1988, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 2210 "vctzdm $vD, $vA, $vB", IIC_VecGeneral, 2211 [(set v2i64:$vD, 2212 (int_ppc_altivec_vctzdm v2i64:$vA, v2i64:$vB))]>; 2213 def CNTLZDM : XForm_6<31, 59, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 2214 "cntlzdm $rA, $rS, $rB", IIC_IntGeneral, 2215 [(set i64:$rA, 2216 (int_ppc_cntlzdm i64:$rS, i64:$rB))]>; 2217 def CNTTZDM : XForm_6<31, 571, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 2218 "cnttzdm $rA, $rS, $rB", IIC_IntGeneral, 2219 [(set i64:$rA, 2220 (int_ppc_cnttzdm i64:$rS, i64:$rB))]>; 2221 def XXGENPCVBM : 2222 XForm_XT6_IMM5_VB5<60, 916, (outs vsrc:$XT), (ins vrrc:$VRB, s5imm:$IMM), 2223 "xxgenpcvbm $XT, $VRB, $IMM", IIC_VecGeneral, []>; 2224 def XXGENPCVHM : 2225 XForm_XT6_IMM5_VB5<60, 917, (outs vsrc:$XT), (ins vrrc:$VRB, s5imm:$IMM), 2226 "xxgenpcvhm $XT, $VRB, $IMM", IIC_VecGeneral, []>; 2227 def XXGENPCVWM : 2228 XForm_XT6_IMM5_VB5<60, 948, (outs vsrc:$XT), (ins vrrc:$VRB, s5imm:$IMM), 2229 "xxgenpcvwm $XT, $VRB, $IMM", IIC_VecGeneral, []>; 2230 def XXGENPCVDM : 2231 XForm_XT6_IMM5_VB5<60, 949, (outs vsrc:$XT), (ins vrrc:$VRB, s5imm:$IMM), 2232 "xxgenpcvdm $XT, $VRB, $IMM", IIC_VecGeneral, []>; 2233 def VCLRLB : VXForm_1<397, (outs vrrc:$vD), (ins vrrc:$vA, gprc:$rB), 2234 "vclrlb $vD, $vA, $rB", IIC_VecGeneral, 2235 [(set v16i8:$vD, 2236 (int_ppc_altivec_vclrlb v16i8:$vA, i32:$rB))]>; 2237 def VCLRRB : VXForm_1<461, (outs vrrc:$vD), (ins vrrc:$vA, gprc:$rB), 2238 "vclrrb $vD, $vA, $rB", IIC_VecGeneral, 2239 [(set v16i8:$vD, 2240 (int_ppc_altivec_vclrrb v16i8:$vA, i32:$rB))]>; 2241 def VMULLD : VXForm_1<457, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 2242 "vmulld $vD, $vA, $vB", IIC_VecGeneral, 2243 [(set v2i64:$vD, (mul v2i64:$vA, v2i64:$vB))]>; 2244 def VMULHSW : VXForm_1<905, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 2245 "vmulhsw $vD, $vA, $vB", IIC_VecGeneral, 2246 [(set v4i32:$vD, (mulhs v4i32:$vA, v4i32:$vB))]>; 2247 def VMULHUW : VXForm_1<649, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 2248 "vmulhuw $vD, $vA, $vB", IIC_VecGeneral, 2249 [(set v4i32:$vD, (mulhu v4i32:$vA, v4i32:$vB))]>; 2250 def VMULHSD : VXForm_1<969, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 2251 "vmulhsd $vD, $vA, $vB", IIC_VecGeneral, 2252 [(set v2i64:$vD, (mulhs v2i64:$vA, v2i64:$vB))]>; 2253 def VMULHUD : VXForm_1<713, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 2254 "vmulhud $vD, $vA, $vB", IIC_VecGeneral, 2255 [(set v2i64:$vD, (mulhu v2i64:$vA, v2i64:$vB))]>; 2256 def VMODSW : VXForm_1<1931, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 2257 "vmodsw $vD, $vA, $vB", IIC_VecGeneral, 2258 [(set v4i32:$vD, (srem v4i32:$vA, v4i32:$vB))]>; 2259 def VMODUW : VXForm_1<1675, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 2260 "vmoduw $vD, $vA, $vB", IIC_VecGeneral, 2261 [(set v4i32:$vD, (urem v4i32:$vA, v4i32:$vB))]>; 2262 def VMODSD : VXForm_1<1995, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 2263 "vmodsd $vD, $vA, $vB", IIC_VecGeneral, 2264 [(set v2i64:$vD, (srem v2i64:$vA, v2i64:$vB))]>; 2265 def VMODUD : VXForm_1<1739, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 2266 "vmodud $vD, $vA, $vB", IIC_VecGeneral, 2267 [(set v2i64:$vD, (urem v2i64:$vA, v2i64:$vB))]>; 2268 def VDIVSW : VXForm_1<395, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 2269 "vdivsw $vD, $vA, $vB", IIC_VecGeneral, 2270 [(set v4i32:$vD, (sdiv v4i32:$vA, v4i32:$vB))]>; 2271 def VDIVUW : VXForm_1<139, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 2272 "vdivuw $vD, $vA, $vB", IIC_VecGeneral, 2273 [(set v4i32:$vD, (udiv v4i32:$vA, v4i32:$vB))]>; 2274 def VDIVSD : VXForm_1<459, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 2275 "vdivsd $vD, $vA, $vB", IIC_VecGeneral, 2276 [(set v2i64:$vD, (sdiv v2i64:$vA, v2i64:$vB))]>; 2277 def VDIVUD : VXForm_1<203, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 2278 "vdivud $vD, $vA, $vB", IIC_VecGeneral, 2279 [(set v2i64:$vD, (udiv v2i64:$vA, v2i64:$vB))]>; 2280 def VDIVESW : VXForm_1<907, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 2281 "vdivesw $vD, $vA, $vB", IIC_VecGeneral, 2282 [(set v4i32:$vD, (int_ppc_altivec_vdivesw v4i32:$vA, 2283 v4i32:$vB))]>; 2284 def VDIVEUW : VXForm_1<651, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 2285 "vdiveuw $vD, $vA, $vB", IIC_VecGeneral, 2286 [(set v4i32:$vD, (int_ppc_altivec_vdiveuw v4i32:$vA, 2287 v4i32:$vB))]>; 2288 def VDIVESD : VXForm_1<971, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 2289 "vdivesd $vD, $vA, $vB", IIC_VecGeneral, 2290 [(set v2i64:$vD, (int_ppc_altivec_vdivesd v2i64:$vA, 2291 v2i64:$vB))]>; 2292 def VDIVEUD : VXForm_1<715, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 2293 "vdiveud $vD, $vA, $vB", IIC_VecGeneral, 2294 [(set v2i64:$vD, (int_ppc_altivec_vdiveud v2i64:$vA, 2295 v2i64:$vB))]>; 2296 def XVTLSBB : XX2_BF3_XO5_XB6_XO9<60, 2, 475, (outs crrc:$BF), (ins vsrc:$XB), 2297 "xvtlsbb $BF, $XB", IIC_VecGeneral, []>; 2298 2299 // The XFormMemOp flag for the following 8 instructions is set on 2300 // the instruction format. 2301 let mayLoad = 1, mayStore = 0 in { 2302 def LXVRBX : X_XT6_RA5_RB5<31, 13, "lxvrbx", vsrc, []>; 2303 def LXVRHX : X_XT6_RA5_RB5<31, 45, "lxvrhx", vsrc, []>; 2304 def LXVRWX : X_XT6_RA5_RB5<31, 77, "lxvrwx", vsrc, []>; 2305 def LXVRDX : X_XT6_RA5_RB5<31, 109, "lxvrdx", vsrc, []>; 2306 } 2307 2308 let mayLoad = 0, mayStore = 1 in { 2309 def STXVRBX : X_XS6_RA5_RB5<31, 141, "stxvrbx", vsrc, []>; 2310 def STXVRHX : X_XS6_RA5_RB5<31, 173, "stxvrhx", vsrc, []>; 2311 def STXVRWX : X_XS6_RA5_RB5<31, 205, "stxvrwx", vsrc, []>; 2312 def STXVRDX : X_XS6_RA5_RB5<31, 237, "stxvrdx", vsrc, []>; 2313 } 2314 2315 def VMULESD : VXForm_1<968, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 2316 "vmulesd $vD, $vA, $vB", IIC_VecGeneral, 2317 [(set v1i128:$vD, (int_ppc_altivec_vmulesd v2i64:$vA, 2318 v2i64:$vB))]>; 2319 def VMULEUD : VXForm_1<712, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 2320 "vmuleud $vD, $vA, $vB", IIC_VecGeneral, 2321 [(set v1i128:$vD, (int_ppc_altivec_vmuleud v2i64:$vA, 2322 v2i64:$vB))]>; 2323 def VMULOSD : VXForm_1<456, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 2324 "vmulosd $vD, $vA, $vB", IIC_VecGeneral, 2325 [(set v1i128:$vD, (int_ppc_altivec_vmulosd v2i64:$vA, 2326 v2i64:$vB))]>; 2327 def VMULOUD : VXForm_1<200, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 2328 "vmuloud $vD, $vA, $vB", IIC_VecGeneral, 2329 [(set v1i128:$vD, (int_ppc_altivec_vmuloud v2i64:$vA, 2330 v2i64:$vB))]>; 2331 def VMSUMCUD : VAForm_1a<23, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, vrrc:$vC), 2332 "vmsumcud $vD, $vA, $vB, $vC", IIC_VecGeneral, 2333 [(set v1i128:$vD, (int_ppc_altivec_vmsumcud 2334 v2i64:$vA, v2i64:$vB, v1i128:$vC))]>; 2335 def VDIVSQ : VXForm_1<267, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 2336 "vdivsq $vD, $vA, $vB", IIC_VecGeneral, 2337 [(set v1i128:$vD, (sdiv v1i128:$vA, v1i128:$vB))]>; 2338 def VDIVUQ : VXForm_1<11, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 2339 "vdivuq $vD, $vA, $vB", IIC_VecGeneral, 2340 [(set v1i128:$vD, (udiv v1i128:$vA, v1i128:$vB))]>; 2341 def VDIVESQ : VXForm_1<779, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 2342 "vdivesq $vD, $vA, $vB", IIC_VecGeneral, 2343 [(set v1i128:$vD, (int_ppc_altivec_vdivesq v1i128:$vA, 2344 v1i128:$vB))]>; 2345 def VDIVEUQ : VXForm_1<523, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 2346 "vdiveuq $vD, $vA, $vB", IIC_VecGeneral, 2347 [(set v1i128:$vD, (int_ppc_altivec_vdiveuq v1i128:$vA, 2348 v1i128:$vB))]>; 2349 def VCMPEQUQ : VCMP <455, "vcmpequq $vD, $vA, $vB" , v1i128>; 2350 def VCMPGTSQ : VCMP <903, "vcmpgtsq $vD, $vA, $vB" , v1i128>; 2351 def VCMPGTUQ : VCMP <647, "vcmpgtuq $vD, $vA, $vB" , v1i128>; 2352 def VCMPEQUQ_rec : VCMP_rec <455, "vcmpequq. $vD, $vA, $vB" , v1i128>; 2353 def VCMPGTSQ_rec : VCMP_rec <903, "vcmpgtsq. $vD, $vA, $vB" , v1i128>; 2354 def VCMPGTUQ_rec : VCMP_rec <647, "vcmpgtuq. $vD, $vA, $vB" , v1i128>; 2355 def VMODSQ : VXForm_1<1803, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 2356 "vmodsq $vD, $vA, $vB", IIC_VecGeneral, 2357 [(set v1i128:$vD, (srem v1i128:$vA, v1i128:$vB))]>; 2358 def VMODUQ : VXForm_1<1547, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 2359 "vmoduq $vD, $vA, $vB", IIC_VecGeneral, 2360 [(set v1i128:$vD, (urem v1i128:$vA, v1i128:$vB))]>; 2361 def VEXTSD2Q : VXForm_RD5_XO5_RS5<1538, 27, (outs vrrc:$vD), (ins vrrc:$vB), 2362 "vextsd2q $vD, $vB", IIC_VecGeneral, 2363 [(set v1i128:$vD, (int_ppc_altivec_vextsd2q v2i64:$vB))]>; 2364 def VCMPUQ : VXForm_BF3_VAB5<257, (outs crrc:$BF), (ins vrrc:$vA, vrrc:$vB), 2365 "vcmpuq $BF, $vA, $vB", IIC_VecGeneral, []>; 2366 def VCMPSQ : VXForm_BF3_VAB5<321, (outs crrc:$BF), (ins vrrc:$vA, vrrc:$vB), 2367 "vcmpsq $BF, $vA, $vB", IIC_VecGeneral, []>; 2368 def VRLQNM : VX1_VT5_VA5_VB5<325, "vrlqnm", 2369 [(set v1i128:$vD, 2370 (int_ppc_altivec_vrlqnm v1i128:$vA, 2371 v1i128:$vB))]>; 2372 def VRLQMI : VXForm_1<69, (outs vrrc:$vD), 2373 (ins vrrc:$vA, vrrc:$vB, vrrc:$vDi), 2374 "vrlqmi $vD, $vA, $vB", IIC_VecFP, 2375 [(set v1i128:$vD, 2376 (int_ppc_altivec_vrlqmi v1i128:$vA, v1i128:$vB, 2377 v1i128:$vDi))]>, 2378 RegConstraint<"$vDi = $vD">, NoEncode<"$vDi">; 2379 def VSLQ : VX1_VT5_VA5_VB5<261, "vslq", []>; 2380 def VSRAQ : VX1_VT5_VA5_VB5<773, "vsraq", []>; 2381 def VSRQ : VX1_VT5_VA5_VB5<517, "vsrq", []>; 2382 def VRLQ : VX1_VT5_VA5_VB5<5, "vrlq", []>; 2383 def XSCVQPUQZ : X_VT5_XO5_VB5<63, 0, 836, "xscvqpuqz", []>; 2384 def XSCVQPSQZ : X_VT5_XO5_VB5<63, 8, 836, "xscvqpsqz", []>; 2385 def XSCVUQQP : X_VT5_XO5_VB5<63, 3, 836, "xscvuqqp", []>; 2386 def XSCVSQQP : X_VT5_XO5_VB5<63, 11, 836, "xscvsqqp", []>; 2387} 2388 2389let Predicates = [IsISA3_1, HasVSX] in { 2390 def XVCVSPBF16 : XX2_XT6_XO5_XB6<60, 17, 475, "xvcvspbf16", vsrc, []>; 2391 def XVCVBF16SPN : XX2_XT6_XO5_XB6<60, 16, 475, "xvcvbf16spn", vsrc, []>; 2392} 2393 2394// Multiclass defining patterns for Set Boolean Extension Reverse Instructions. 2395// This is analogous to the CRNotPat multiclass but specifically for Power10 2396// and newer subtargets since the extended forms use Set Boolean instructions. 2397// The first two anonymous patterns defined are actually a duplicate of those 2398// in CRNotPat, but it is preferable to define both multiclasses as complete 2399// ones rather than pulling that small common section out. 2400multiclass P10ReverseSetBool<dag pattern, dag result> { 2401 def : Pat<pattern, (crnot result)>; 2402 def : Pat<(not pattern), result>; 2403 2404 def : Pat<(i32 (zext pattern)), 2405 (SETBCR result)>; 2406 def : Pat<(i64 (zext pattern)), 2407 (SETBCR8 result)>; 2408 2409 def : Pat<(i32 (sext pattern)), 2410 (SETNBCR result)>; 2411 def : Pat<(i64 (sext pattern)), 2412 (SETNBCR8 result)>; 2413 2414 def : Pat<(i32 (anyext pattern)), 2415 (SETBCR result)>; 2416 def : Pat<(i64 (anyext pattern)), 2417 (SETBCR8 result)>; 2418} 2419 2420multiclass IntSetP10RevSetBool<SDNode SetCC, ValueType Ty, ImmLeaf ZExtTy, 2421 ImmLeaf SExtTy, PatLeaf Cmpi, PatLeaf Cmpli, 2422 PatLeaf Cmp, PatLeaf Cmpl> { 2423 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETUGE)), 2424 (EXTRACT_SUBREG (Cmpl $s1, $s2), sub_lt)>; 2425 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETGE)), 2426 (EXTRACT_SUBREG (Cmp $s1, $s2), sub_lt)>; 2427 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETULE)), 2428 (EXTRACT_SUBREG (Cmpl $s1, $s2), sub_gt)>; 2429 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETLE)), 2430 (EXTRACT_SUBREG (Cmp $s1, $s2), sub_gt)>; 2431 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETNE)), 2432 (EXTRACT_SUBREG (Cmp $s1, $s2), sub_eq)>; 2433 2434 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, ZExtTy:$imm, SETUGE)), 2435 (EXTRACT_SUBREG (Cmpli $s1, imm:$imm), sub_lt)>; 2436 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, SExtTy:$imm, SETGE)), 2437 (EXTRACT_SUBREG (Cmpi $s1, imm:$imm), sub_lt)>; 2438 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, ZExtTy:$imm, SETULE)), 2439 (EXTRACT_SUBREG (Cmpli $s1, imm:$imm), sub_gt)>; 2440 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, SExtTy:$imm, SETLE)), 2441 (EXTRACT_SUBREG (Cmpi $s1, imm:$imm), sub_gt)>; 2442 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, SExtTy:$imm, SETNE)), 2443 (EXTRACT_SUBREG (Cmpi $s1, imm:$imm), sub_eq)>; 2444 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, ZExtTy:$imm, SETNE)), 2445 (EXTRACT_SUBREG (Cmpli $s1, imm:$imm), sub_eq)>; 2446} 2447 2448multiclass FSetP10RevSetBool<SDNode SetCC, ValueType Ty, PatLeaf FCmp> { 2449 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETUGE)), 2450 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_lt)>; 2451 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETGE)), 2452 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_lt)>; 2453 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETULE)), 2454 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_gt)>; 2455 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETLE)), 2456 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_gt)>; 2457 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETUNE)), 2458 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_eq)>; 2459 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETNE)), 2460 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_eq)>; 2461 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETO)), 2462 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_un)>; 2463} 2464 2465let Predicates = [IsISA3_1] in { 2466 def : Pat<(i32 (zext i1:$in)), 2467 (SETBC $in)>; 2468 def : Pat<(i64 (zext i1:$in)), 2469 (SETBC8 $in)>; 2470 def : Pat<(i32 (sext i1:$in)), 2471 (SETNBC $in)>; 2472 def : Pat<(i64 (sext i1:$in)), 2473 (SETNBC8 $in)>; 2474 def : Pat<(i32 (anyext i1:$in)), 2475 (SETBC $in)>; 2476 def : Pat<(i64 (anyext i1:$in)), 2477 (SETBC8 $in)>; 2478 2479 // Instantiation of the set boolean reverse patterns for 32-bit integers. 2480 defm : IntSetP10RevSetBool<setcc, i32, immZExt16, imm32SExt16, 2481 CMPWI, CMPLWI, CMPW, CMPLW>; 2482 defm : P10ReverseSetBool<(i1 (setcc i32:$s1, imm:$imm, SETNE)), 2483 (EXTRACT_SUBREG (CMPLWI (XORIS $s1, (HI16 imm:$imm)), 2484 (LO16 imm:$imm)), sub_eq)>; 2485 2486 // Instantiation of the set boolean reverse patterns for 64-bit integers. 2487 defm : IntSetP10RevSetBool<setcc, i64, immZExt16, imm64SExt16, 2488 CMPDI, CMPLDI, CMPD, CMPLD>; 2489 defm : P10ReverseSetBool<(i1 (setcc i64:$s1, imm64ZExt32:$imm, SETNE)), 2490 (EXTRACT_SUBREG (CMPLDI (XORIS8 $s1, (HI16 imm:$imm)), 2491 (LO16 imm:$imm)), sub_eq)>; 2492} 2493 2494// Instantiation of the set boolean reverse patterns for f32, f64, f128. 2495let Predicates = [IsISA3_1, HasFPU] in { 2496 defm : FSetP10RevSetBool<setcc, f32, FCMPUS>; 2497 defm : FSetP10RevSetBool<setcc, f64, FCMPUD>; 2498 defm : FSetP10RevSetBool<setcc, f128, XSCMPUQP>; 2499} 2500 2501//---------------------------- Anonymous Patterns ----------------------------// 2502let Predicates = [IsISA3_1] in { 2503 // Exploit the vector multiply high instructions using intrinsics. 2504 def : Pat<(v4i32 (int_ppc_altivec_vmulhsw v4i32:$vA, v4i32:$vB)), 2505 (v4i32 (VMULHSW $vA, $vB))>; 2506 def : Pat<(v4i32 (int_ppc_altivec_vmulhuw v4i32:$vA, v4i32:$vB)), 2507 (v4i32 (VMULHUW $vA, $vB))>; 2508 def : Pat<(v2i64 (int_ppc_altivec_vmulhsd v2i64:$vA, v2i64:$vB)), 2509 (v2i64 (VMULHSD $vA, $vB))>; 2510 def : Pat<(v2i64 (int_ppc_altivec_vmulhud v2i64:$vA, v2i64:$vB)), 2511 (v2i64 (VMULHUD $vA, $vB))>; 2512 def : Pat<(v16i8 (int_ppc_vsx_xxgenpcvbm v16i8:$VRB, imm:$IMM)), 2513 (v16i8 (COPY_TO_REGCLASS (XXGENPCVBM $VRB, imm:$IMM), VRRC))>; 2514 def : Pat<(v8i16 (int_ppc_vsx_xxgenpcvhm v8i16:$VRB, imm:$IMM)), 2515 (v8i16 (COPY_TO_REGCLASS (XXGENPCVHM $VRB, imm:$IMM), VRRC))>; 2516 def : Pat<(v4i32 (int_ppc_vsx_xxgenpcvwm v4i32:$VRB, imm:$IMM)), 2517 (v4i32 (COPY_TO_REGCLASS (XXGENPCVWM $VRB, imm:$IMM), VRRC))>; 2518 def : Pat<(v2i64 (int_ppc_vsx_xxgenpcvdm v2i64:$VRB, imm:$IMM)), 2519 (v2i64 (COPY_TO_REGCLASS (XXGENPCVDM $VRB, imm:$IMM), VRRC))>; 2520 def : Pat<(i32 (int_ppc_vsx_xvtlsbb v16i8:$XB, 1)), 2521 (EXTRACT_SUBREG (XVTLSBB (COPY_TO_REGCLASS $XB, VSRC)), sub_lt)>; 2522 def : Pat<(i32 (int_ppc_vsx_xvtlsbb v16i8:$XB, 0)), 2523 (EXTRACT_SUBREG (XVTLSBB (COPY_TO_REGCLASS $XB, VSRC)), sub_eq)>; 2524 2525 def : Pat <(v1i128 (PPClxvrzx xoaddr:$src, 8)), 2526 (v1i128 (COPY_TO_REGCLASS (LXVRBX xoaddr:$src), VRRC))>; 2527 def : Pat <(v1i128 (PPClxvrzx xoaddr:$src, 16)), 2528 (v1i128 (COPY_TO_REGCLASS (LXVRHX xoaddr:$src), VRRC))>; 2529 def : Pat <(v1i128 (PPClxvrzx xoaddr:$src, 32)), 2530 (v1i128 (COPY_TO_REGCLASS (LXVRWX xoaddr:$src), VRRC))>; 2531 def : Pat <(v1i128 (PPClxvrzx xoaddr:$src, 64)), 2532 (v1i128 (COPY_TO_REGCLASS (LXVRDX xoaddr:$src), VRRC))>; 2533 2534 def : Pat<(v1i128 (rotl v1i128:$vA, v1i128:$vB)), 2535 (v1i128 (VRLQ v1i128:$vA, v1i128:$vB))>; 2536 2537 def : Pat <(v2i64 (PPCxxsplti32dx v2i64:$XT, i32:$XI, i32:$IMM32)), 2538 (v2i64 (XXSPLTI32DX v2i64:$XT, i32:$XI, i32:$IMM32))>; 2539} 2540 2541let Predicates = [IsISA3_1, HasVSX] in { 2542 def : Pat<(v16i8 (int_ppc_vsx_xvcvspbf16 v16i8:$XA)), 2543 (COPY_TO_REGCLASS (XVCVSPBF16 RCCp.AToVSRC), VRRC)>; 2544 def : Pat<(v16i8 (int_ppc_vsx_xvcvbf16spn v16i8:$XA)), 2545 (COPY_TO_REGCLASS (XVCVBF16SPN RCCp.AToVSRC), VRRC)>; 2546} 2547 2548let AddedComplexity = 400, Predicates = [IsISA3_1, IsLittleEndian] in { 2549 // Store element 0 of a VSX register to memory 2550 def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$src, 0)), xoaddr:$dst), 2551 (STXVRBX (COPY_TO_REGCLASS v16i8:$src, VSRC), xoaddr:$dst)>; 2552 def : Pat<(truncstorei16 (i32 (vector_extract v8i16:$src, 0)), xoaddr:$dst), 2553 (STXVRHX (COPY_TO_REGCLASS v8i16:$src, VSRC), xoaddr:$dst)>; 2554 def : Pat<(store (i32 (extractelt v4i32:$src, 0)), xoaddr:$dst), 2555 (STXVRWX $src, xoaddr:$dst)>; 2556 def : Pat<(store (f32 (extractelt v4f32:$src, 0)), xoaddr:$dst), 2557 (STXVRWX $src, xoaddr:$dst)>; 2558 def : Pat<(store (i64 (extractelt v2i64:$src, 0)), xoaddr:$dst), 2559 (STXVRDX $src, xoaddr:$dst)>; 2560 def : Pat<(store (f64 (extractelt v2f64:$src, 0)), xoaddr:$dst), 2561 (STXVRDX $src, xoaddr:$dst)>; 2562 } 2563 2564// FIXME: The swap is overkill when the shift amount is a constant. 2565// We should just fix the constant in the DAG. 2566let AddedComplexity = 400, Predicates = [IsISA3_1, HasVSX] in { 2567 def : Pat<(v1i128 (shl v1i128:$VRA, v1i128:$VRB)), 2568 (v1i128 (VSLQ v1i128:$VRA, 2569 (XXPERMDI (COPY_TO_REGCLASS $VRB, VSRC), 2570 (COPY_TO_REGCLASS $VRB, VSRC), 2)))>; 2571 def : Pat<(v1i128 (PPCshl v1i128:$VRA, v1i128:$VRB)), 2572 (v1i128 (VSLQ v1i128:$VRA, 2573 (XXPERMDI (COPY_TO_REGCLASS $VRB, VSRC), 2574 (COPY_TO_REGCLASS $VRB, VSRC), 2)))>; 2575 def : Pat<(v1i128 (srl v1i128:$VRA, v1i128:$VRB)), 2576 (v1i128 (VSRQ v1i128:$VRA, 2577 (XXPERMDI (COPY_TO_REGCLASS $VRB, VSRC), 2578 (COPY_TO_REGCLASS $VRB, VSRC), 2)))>; 2579 def : Pat<(v1i128 (PPCsrl v1i128:$VRA, v1i128:$VRB)), 2580 (v1i128 (VSRQ v1i128:$VRA, 2581 (XXPERMDI (COPY_TO_REGCLASS $VRB, VSRC), 2582 (COPY_TO_REGCLASS $VRB, VSRC), 2)))>; 2583 def : Pat<(v1i128 (sra v1i128:$VRA, v1i128:$VRB)), 2584 (v1i128 (VSRAQ v1i128:$VRA, 2585 (XXPERMDI (COPY_TO_REGCLASS $VRB, VSRC), 2586 (COPY_TO_REGCLASS $VRB, VSRC), 2)))>; 2587 def : Pat<(v1i128 (PPCsra v1i128:$VRA, v1i128:$VRB)), 2588 (v1i128 (VSRAQ v1i128:$VRA, 2589 (XXPERMDI (COPY_TO_REGCLASS $VRB, VSRC), 2590 (COPY_TO_REGCLASS $VRB, VSRC), 2)))>; 2591} 2592 2593class xxevalPattern <dag pattern, bits<8> imm> : 2594 Pat<(v4i32 pattern), (XXEVAL $vA, $vB, $vC, imm)> {} 2595 2596let AddedComplexity = 400, Predicates = [PrefixInstrs] in { 2597 def : Pat<(v4i32 (build_vector i32immNonAllOneNonZero:$A, 2598 i32immNonAllOneNonZero:$A, 2599 i32immNonAllOneNonZero:$A, 2600 i32immNonAllOneNonZero:$A)), 2601 (v4i32 (XXSPLTIW imm:$A))>; 2602 def : Pat<(f32 nzFPImmAsi32:$A), 2603 (COPY_TO_REGCLASS (XXSPLTIDP (getFPAs32BitInt fpimm:$A)), 2604 VSFRC)>; 2605 def : Pat<(f64 nzFPImmAsi32:$A), 2606 (COPY_TO_REGCLASS (XXSPLTIDP (getFPAs32BitInt fpimm:$A)), 2607 VSFRC)>; 2608 2609 // Anonymous patterns for XXEVAL 2610 // AND 2611 // and(A, B, C) 2612 def : xxevalPattern<(and v4i32:$vA, (and v4i32:$vB, v4i32:$vC)), 1>; 2613 // and(A, xor(B, C)) 2614 def : xxevalPattern<(and v4i32:$vA, (xor v4i32:$vB, v4i32:$vC)), 6>; 2615 // and(A, or(B, C)) 2616 def : xxevalPattern<(and v4i32:$vA, (or v4i32:$vB, v4i32:$vC)), 7>; 2617 // and(A, nor(B, C)) 2618 def : xxevalPattern<(and v4i32:$vA, (vnot_ppc (or v4i32:$vB, v4i32:$vC))), 2619 8>; 2620 // and(A, eqv(B, C)) 2621 def : xxevalPattern<(and v4i32:$vA, (vnot_ppc (xor v4i32:$vB, v4i32:$vC))), 2622 9>; 2623 // and(A, nand(B, C)) 2624 def : xxevalPattern<(and v4i32:$vA, (vnot_ppc (and v4i32:$vB, v4i32:$vC))), 2625 14>; 2626 2627 // NAND 2628 // nand(A, B, C) 2629 def : xxevalPattern<(vnot_ppc (and v4i32:$vA, (and v4i32:$vB, v4i32:$vC))), 2630 !sub(255, 1)>; 2631 // nand(A, xor(B, C)) 2632 def : xxevalPattern<(vnot_ppc (and v4i32:$vA, (xor v4i32:$vB, v4i32:$vC))), 2633 !sub(255, 6)>; 2634 // nand(A, or(B, C)) 2635 def : xxevalPattern<(vnot_ppc (and v4i32:$vA, (or v4i32:$vB, v4i32:$vC))), 2636 !sub(255, 7)>; 2637 // nand(A, nor(B, C)) 2638 def : xxevalPattern<(or (vnot_ppc v4i32:$vA), (or v4i32:$vB, v4i32:$vC)), 2639 !sub(255, 8)>; 2640 // nand(A, eqv(B, C)) 2641 def : xxevalPattern<(or (vnot_ppc v4i32:$vA), (xor v4i32:$vB, v4i32:$vC)), 2642 !sub(255, 9)>; 2643 // nand(A, nand(B, C)) 2644 def : xxevalPattern<(or (vnot_ppc v4i32:$vA), (and v4i32:$vB, v4i32:$vC)), 2645 !sub(255, 14)>; 2646} 2647 2648let Predicates = [PrefixInstrs] in { 2649 def : Pat<(v16i8 (int_ppc_vsx_xxpermx v16i8:$A, v16i8:$B, v16i8:$C, timm:$D)), 2650 (COPY_TO_REGCLASS (XXPERMX (COPY_TO_REGCLASS $A, VSRC), 2651 (COPY_TO_REGCLASS $B, VSRC), 2652 (COPY_TO_REGCLASS $C, VSRC), $D), VSRC)>; 2653 def : Pat<(v16i8 (int_ppc_vsx_xxblendvb v16i8:$A, v16i8:$B, v16i8:$C)), 2654 (COPY_TO_REGCLASS 2655 (XXBLENDVB (COPY_TO_REGCLASS $A, VSRC), 2656 (COPY_TO_REGCLASS $B, VSRC), 2657 (COPY_TO_REGCLASS $C, VSRC)), VSRC)>; 2658 def : Pat<(v8i16 (int_ppc_vsx_xxblendvh v8i16:$A, v8i16:$B, v8i16:$C)), 2659 (COPY_TO_REGCLASS 2660 (XXBLENDVH (COPY_TO_REGCLASS $A, VSRC), 2661 (COPY_TO_REGCLASS $B, VSRC), 2662 (COPY_TO_REGCLASS $C, VSRC)), VSRC)>; 2663 def : Pat<(int_ppc_vsx_xxblendvw v4i32:$A, v4i32:$B, v4i32:$C), 2664 (XXBLENDVW $A, $B, $C)>; 2665 def : Pat<(int_ppc_vsx_xxblendvd v2i64:$A, v2i64:$B, v2i64:$C), 2666 (XXBLENDVD $A, $B, $C)>; 2667} 2668 2669