1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=mips-mti-linux-gnu -mcpu=mips32r2 < %s -asm-show-inst | FileCheck %s --check-prefix=MIPS32
3; RUN: llc -mtriple=mips-mti-linux-gnu -mcpu=mips32r2 -mattr=+micromips < %s -asm-show-inst | FileCheck %s --check-prefix=MMR3
4; RUN: llc -mtriple=mips-img-linux-gnu -mcpu=mips32r6 < %s -asm-show-inst | FileCheck %s --check-prefix=MIPS32R6
5; RUN: llc -mtriple=mips-img-linux-gnu -mcpu=mips32r6 -mattr=+micromips < %s -asm-show-inst | FileCheck %s --check-prefix=MMR6
6; RUN: llc -mtriple=mips64-mti-linux-gnu -mcpu=mips4 < %s -asm-show-inst | FileCheck %s --check-prefix=MIPS4
7; RUN: llc -mtriple=mips64-img-linux-gnu -mcpu=mips64r6 < %s -asm-show-inst | FileCheck %s --check-prefix=MIPS64R6
8
9; Test subword and word stores.
10
11@a = common global i8 0, align 4
12@b = common global i16 0, align 4
13@c = common global i32 0, align 4
14@d = common global i64 0, align 8
15
16define void @f1(i8 %a) {
17; MIPS32-LABEL: f1:
18; MIPS32:       # %bb.0:
19; MIPS32-NEXT:    lui $1, %hi(a) # <MCInst #{{[0-9]+}} LUi
20; MIPS32-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
21; MIPS32-NEXT:    # <MCOperand Expr:(%hi(a))>>
22; MIPS32-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
23; MIPS32-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
24; MIPS32-NEXT:    sb $4, %lo(a)($1) # <MCInst #{{[0-9]+}} SB
25; MIPS32-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
26; MIPS32-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
27; MIPS32-NEXT:    # <MCOperand Expr:(%lo(a))>>
28;
29; MMR3-LABEL: f1:
30; MMR3:       # %bb.0:
31; MMR3-NEXT:    lui $1, %hi(a) # <MCInst #{{[0-9]+}} LUi
32; MMR3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
33; MMR3-NEXT:    # <MCOperand Expr:(%hi(a))>>
34; MMR3-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR_MM
35; MMR3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
36; MMR3-NEXT:    sb $4, %lo(a)($1) # <MCInst #{{[0-9]+}} SB_MM
37; MMR3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
38; MMR3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
39; MMR3-NEXT:    # <MCOperand Expr:(%lo(a))>>
40;
41; MIPS32R6-LABEL: f1:
42; MIPS32R6:       # %bb.0:
43; MIPS32R6-NEXT:    lui $1, %hi(a) # <MCInst #{{[0-9]+}} LUi
44; MIPS32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
45; MIPS32R6-NEXT:    # <MCOperand Expr:(%hi(a))>>
46; MIPS32R6-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JALR
47; MIPS32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
48; MIPS32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
49; MIPS32R6-NEXT:    sb $4, %lo(a)($1) # <MCInst #{{[0-9]+}} SB
50; MIPS32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
51; MIPS32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
52; MIPS32R6-NEXT:    # <MCOperand Expr:(%lo(a))>>
53;
54; MMR6-LABEL: f1:
55; MMR6:       # %bb.0:
56; MMR6-NEXT:    lui $1, %hi(a) # <MCInst #{{[0-9]+}} LUi
57; MMR6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
58; MMR6-NEXT:    # <MCOperand Expr:(%hi(a))>>
59; MMR6-NEXT:    sb $4, %lo(a)($1) # <MCInst #{{[0-9]+}} SB_MM
60; MMR6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
61; MMR6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
62; MMR6-NEXT:    # <MCOperand Expr:(%lo(a))>>
63; MMR6-NEXT:    jrc $ra # <MCInst #{{[0-9]+}} JRC16_MM
64; MMR6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
65;
66; MIPS4-LABEL: f1:
67; MIPS4:       # %bb.0:
68; MIPS4-NEXT:    lui $1, %highest(a) # <MCInst #{{[0-9]+}} LUi64
69; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
70; MIPS4-NEXT:    # <MCOperand Expr:(%highest(a))>>
71; MIPS4-NEXT:    daddiu $1, $1, %higher(a) # <MCInst #{{[0-9]+}} DADDiu
72; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
73; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
74; MIPS4-NEXT:    # <MCOperand Expr:(%higher(a))>>
75; MIPS4-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
76; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
77; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
78; MIPS4-NEXT:    # <MCOperand Imm:16>>
79; MIPS4-NEXT:    daddiu $1, $1, %hi(a) # <MCInst #{{[0-9]+}} DADDiu
80; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
81; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
82; MIPS4-NEXT:    # <MCOperand Expr:(%hi(a))>>
83; MIPS4-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
84; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
85; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
86; MIPS4-NEXT:    # <MCOperand Imm:16>>
87; MIPS4-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
88; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
89; MIPS4-NEXT:    sb $4, %lo(a)($1) # <MCInst #{{[0-9]+}} SB64
90; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
91; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
92; MIPS4-NEXT:    # <MCOperand Expr:(%lo(a))>>
93;
94; MIPS64R6-LABEL: f1:
95; MIPS64R6:       # %bb.0:
96; MIPS64R6-NEXT:    lui $1, %highest(a) # <MCInst #{{[0-9]+}} LUi64
97; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
98; MIPS64R6-NEXT:    # <MCOperand Expr:(%highest(a))>>
99; MIPS64R6-NEXT:    daddiu $1, $1, %higher(a) # <MCInst #{{[0-9]+}} DADDiu
100; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
101; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
102; MIPS64R6-NEXT:    # <MCOperand Expr:(%higher(a))>>
103; MIPS64R6-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
104; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
105; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
106; MIPS64R6-NEXT:    # <MCOperand Imm:16>>
107; MIPS64R6-NEXT:    daddiu $1, $1, %hi(a) # <MCInst #{{[0-9]+}} DADDiu
108; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
109; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
110; MIPS64R6-NEXT:    # <MCOperand Expr:(%hi(a))>>
111; MIPS64R6-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
112; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
113; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
114; MIPS64R6-NEXT:    # <MCOperand Imm:16>>
115; MIPS64R6-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JALR64
116; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
117; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
118; MIPS64R6-NEXT:    sb $4, %lo(a)($1) # <MCInst #{{[0-9]+}} SB64
119; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
120; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
121; MIPS64R6-NEXT:    # <MCOperand Expr:(%lo(a))>>
122  store i8 %a, i8 * @a
123  ret void
124}
125
126define void @f2(i16 %a) {
127; MIPS32-LABEL: f2:
128; MIPS32:       # %bb.0:
129; MIPS32-NEXT:    lui $1, %hi(b) # <MCInst #{{[0-9]+}} LUi
130; MIPS32-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
131; MIPS32-NEXT:    # <MCOperand Expr:(%hi(b))>>
132; MIPS32-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
133; MIPS32-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
134; MIPS32-NEXT:    sh $4, %lo(b)($1) # <MCInst #{{[0-9]+}} SH
135; MIPS32-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
136; MIPS32-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
137; MIPS32-NEXT:    # <MCOperand Expr:(%lo(b))>>
138;
139; MMR3-LABEL: f2:
140; MMR3:       # %bb.0:
141; MMR3-NEXT:    lui $1, %hi(b) # <MCInst #{{[0-9]+}} LUi
142; MMR3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
143; MMR3-NEXT:    # <MCOperand Expr:(%hi(b))>>
144; MMR3-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR_MM
145; MMR3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
146; MMR3-NEXT:    sh $4, %lo(b)($1) # <MCInst #{{[0-9]+}} SH_MM
147; MMR3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
148; MMR3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
149; MMR3-NEXT:    # <MCOperand Expr:(%lo(b))>>
150;
151; MIPS32R6-LABEL: f2:
152; MIPS32R6:       # %bb.0:
153; MIPS32R6-NEXT:    lui $1, %hi(b) # <MCInst #{{[0-9]+}} LUi
154; MIPS32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
155; MIPS32R6-NEXT:    # <MCOperand Expr:(%hi(b))>>
156; MIPS32R6-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JALR
157; MIPS32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
158; MIPS32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
159; MIPS32R6-NEXT:    sh $4, %lo(b)($1) # <MCInst #{{[0-9]+}} SH
160; MIPS32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
161; MIPS32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
162; MIPS32R6-NEXT:    # <MCOperand Expr:(%lo(b))>>
163;
164; MMR6-LABEL: f2:
165; MMR6:       # %bb.0:
166; MMR6-NEXT:    lui $1, %hi(b) # <MCInst #{{[0-9]+}} LUi
167; MMR6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
168; MMR6-NEXT:    # <MCOperand Expr:(%hi(b))>>
169; MMR6-NEXT:    sh $4, %lo(b)($1) # <MCInst #{{[0-9]+}} SH_MM
170; MMR6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
171; MMR6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
172; MMR6-NEXT:    # <MCOperand Expr:(%lo(b))>>
173; MMR6-NEXT:    jrc $ra # <MCInst #{{[0-9]+}} JRC16_MM
174; MMR6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
175;
176; MIPS4-LABEL: f2:
177; MIPS4:       # %bb.0:
178; MIPS4-NEXT:    lui $1, %highest(b) # <MCInst #{{[0-9]+}} LUi64
179; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
180; MIPS4-NEXT:    # <MCOperand Expr:(%highest(b))>>
181; MIPS4-NEXT:    daddiu $1, $1, %higher(b) # <MCInst #{{[0-9]+}} DADDiu
182; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
183; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
184; MIPS4-NEXT:    # <MCOperand Expr:(%higher(b))>>
185; MIPS4-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
186; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
187; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
188; MIPS4-NEXT:    # <MCOperand Imm:16>>
189; MIPS4-NEXT:    daddiu $1, $1, %hi(b) # <MCInst #{{[0-9]+}} DADDiu
190; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
191; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
192; MIPS4-NEXT:    # <MCOperand Expr:(%hi(b))>>
193; MIPS4-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
194; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
195; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
196; MIPS4-NEXT:    # <MCOperand Imm:16>>
197; MIPS4-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
198; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
199; MIPS4-NEXT:    sh $4, %lo(b)($1) # <MCInst #{{[0-9]+}} SH64
200; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
201; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
202; MIPS4-NEXT:    # <MCOperand Expr:(%lo(b))>>
203;
204; MIPS64R6-LABEL: f2:
205; MIPS64R6:       # %bb.0:
206; MIPS64R6-NEXT:    lui $1, %highest(b) # <MCInst #{{[0-9]+}} LUi64
207; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
208; MIPS64R6-NEXT:    # <MCOperand Expr:(%highest(b))>>
209; MIPS64R6-NEXT:    daddiu $1, $1, %higher(b) # <MCInst #{{[0-9]+}} DADDiu
210; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
211; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
212; MIPS64R6-NEXT:    # <MCOperand Expr:(%higher(b))>>
213; MIPS64R6-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
214; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
215; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
216; MIPS64R6-NEXT:    # <MCOperand Imm:16>>
217; MIPS64R6-NEXT:    daddiu $1, $1, %hi(b) # <MCInst #{{[0-9]+}} DADDiu
218; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
219; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
220; MIPS64R6-NEXT:    # <MCOperand Expr:(%hi(b))>>
221; MIPS64R6-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
222; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
223; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
224; MIPS64R6-NEXT:    # <MCOperand Imm:16>>
225; MIPS64R6-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JALR64
226; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
227; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
228; MIPS64R6-NEXT:    sh $4, %lo(b)($1) # <MCInst #{{[0-9]+}} SH64
229; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
230; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
231; MIPS64R6-NEXT:    # <MCOperand Expr:(%lo(b))>>
232  store i16 %a, i16 * @b
233  ret void
234}
235
236define void @f3(i32 %a) {
237; MIPS32-LABEL: f3:
238; MIPS32:       # %bb.0:
239; MIPS32-NEXT:    lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi
240; MIPS32-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
241; MIPS32-NEXT:    # <MCOperand Expr:(%hi(c))>>
242; MIPS32-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
243; MIPS32-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
244; MIPS32-NEXT:    sw $4, %lo(c)($1) # <MCInst #{{[0-9]+}} SW
245; MIPS32-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
246; MIPS32-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
247; MIPS32-NEXT:    # <MCOperand Expr:(%lo(c))>>
248;
249; MMR3-LABEL: f3:
250; MMR3:       # %bb.0:
251; MMR3-NEXT:    lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi
252; MMR3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
253; MMR3-NEXT:    # <MCOperand Expr:(%hi(c))>>
254; MMR3-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR_MM
255; MMR3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
256; MMR3-NEXT:    sw $4, %lo(c)($1) # <MCInst #{{[0-9]+}} SW_MM
257; MMR3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
258; MMR3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
259; MMR3-NEXT:    # <MCOperand Expr:(%lo(c))>>
260;
261; MIPS32R6-LABEL: f3:
262; MIPS32R6:       # %bb.0:
263; MIPS32R6-NEXT:    lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi
264; MIPS32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
265; MIPS32R6-NEXT:    # <MCOperand Expr:(%hi(c))>>
266; MIPS32R6-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JALR
267; MIPS32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
268; MIPS32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
269; MIPS32R6-NEXT:    sw $4, %lo(c)($1) # <MCInst #{{[0-9]+}} SW
270; MIPS32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
271; MIPS32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
272; MIPS32R6-NEXT:    # <MCOperand Expr:(%lo(c))>>
273;
274; MMR6-LABEL: f3:
275; MMR6:       # %bb.0:
276; MMR6-NEXT:    lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi
277; MMR6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
278; MMR6-NEXT:    # <MCOperand Expr:(%hi(c))>>
279; MMR6-NEXT:    sw $4, %lo(c)($1) # <MCInst #{{[0-9]+}} SW_MM
280; MMR6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
281; MMR6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
282; MMR6-NEXT:    # <MCOperand Expr:(%lo(c))>>
283; MMR6-NEXT:    jrc $ra # <MCInst #{{[0-9]+}} JRC16_MM
284; MMR6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
285;
286; MIPS4-LABEL: f3:
287; MIPS4:       # %bb.0:
288; MIPS4-NEXT:    sll $1, $4, 0 # <MCInst #{{[0-9]+}} SLL
289; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
290; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
291; MIPS4-NEXT:    # <MCOperand Imm:0>>
292; MIPS4-NEXT:    lui $2, %highest(c) # <MCInst #{{[0-9]+}} LUi64
293; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
294; MIPS4-NEXT:    # <MCOperand Expr:(%highest(c))>>
295; MIPS4-NEXT:    daddiu $2, $2, %higher(c) # <MCInst #{{[0-9]+}} DADDiu
296; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
297; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
298; MIPS4-NEXT:    # <MCOperand Expr:(%higher(c))>>
299; MIPS4-NEXT:    dsll $2, $2, 16 # <MCInst #{{[0-9]+}} DSLL
300; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
301; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
302; MIPS4-NEXT:    # <MCOperand Imm:16>>
303; MIPS4-NEXT:    daddiu $2, $2, %hi(c) # <MCInst #{{[0-9]+}} DADDiu
304; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
305; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
306; MIPS4-NEXT:    # <MCOperand Expr:(%hi(c))>>
307; MIPS4-NEXT:    dsll $2, $2, 16 # <MCInst #{{[0-9]+}} DSLL
308; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
309; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
310; MIPS4-NEXT:    # <MCOperand Imm:16>>
311; MIPS4-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
312; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
313; MIPS4-NEXT:    sw $1, %lo(c)($2) # <MCInst #{{[0-9]+}} SW
314; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
315; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
316; MIPS4-NEXT:    # <MCOperand Expr:(%lo(c))>>
317;
318; MIPS64R6-LABEL: f3:
319; MIPS64R6:       # %bb.0:
320; MIPS64R6-NEXT:    sll $1, $4, 0 # <MCInst #{{[0-9]+}} SLL
321; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
322; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
323; MIPS64R6-NEXT:    # <MCOperand Imm:0>>
324; MIPS64R6-NEXT:    lui $2, %highest(c) # <MCInst #{{[0-9]+}} LUi64
325; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
326; MIPS64R6-NEXT:    # <MCOperand Expr:(%highest(c))>>
327; MIPS64R6-NEXT:    daddiu $2, $2, %higher(c) # <MCInst #{{[0-9]+}} DADDiu
328; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
329; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
330; MIPS64R6-NEXT:    # <MCOperand Expr:(%higher(c))>>
331; MIPS64R6-NEXT:    dsll $2, $2, 16 # <MCInst #{{[0-9]+}} DSLL
332; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
333; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
334; MIPS64R6-NEXT:    # <MCOperand Imm:16>>
335; MIPS64R6-NEXT:    daddiu $2, $2, %hi(c) # <MCInst #{{[0-9]+}} DADDiu
336; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
337; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
338; MIPS64R6-NEXT:    # <MCOperand Expr:(%hi(c))>>
339; MIPS64R6-NEXT:    dsll $2, $2, 16 # <MCInst #{{[0-9]+}} DSLL
340; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
341; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
342; MIPS64R6-NEXT:    # <MCOperand Imm:16>>
343; MIPS64R6-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JALR64
344; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
345; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
346; MIPS64R6-NEXT:    sw $1, %lo(c)($2) # <MCInst #{{[0-9]+}} SW
347; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
348; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
349; MIPS64R6-NEXT:    # <MCOperand Expr:(%lo(c))>>
350  store i32 %a, i32 * @c
351  ret void
352}
353
354define void @f4(i64 %a) {
355; MIPS32-LABEL: f4:
356; MIPS32:       # %bb.0:
357; MIPS32-NEXT:    lui $1, %hi(d) # <MCInst #{{[0-9]+}} LUi
358; MIPS32-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
359; MIPS32-NEXT:    # <MCOperand Expr:(%hi(d))>>
360; MIPS32-NEXT:    sw $4, %lo(d)($1) # <MCInst #{{[0-9]+}} SW
361; MIPS32-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
362; MIPS32-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
363; MIPS32-NEXT:    # <MCOperand Expr:(%lo(d))>>
364; MIPS32-NEXT:    addiu $1, $1, %lo(d) # <MCInst #{{[0-9]+}} ADDiu
365; MIPS32-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
366; MIPS32-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
367; MIPS32-NEXT:    # <MCOperand Expr:(%lo(d))>>
368; MIPS32-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
369; MIPS32-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
370; MIPS32-NEXT:    sw $5, 4($1) # <MCInst #{{[0-9]+}} SW
371; MIPS32-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
372; MIPS32-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
373; MIPS32-NEXT:    # <MCOperand Imm:4>>
374;
375; MMR3-LABEL: f4:
376; MMR3:       # %bb.0:
377; MMR3-NEXT:    lui $1, %hi(d) # <MCInst #{{[0-9]+}} LUi
378; MMR3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
379; MMR3-NEXT:    # <MCOperand Expr:(%hi(d))>>
380; MMR3-NEXT:    sw $4, %lo(d)($1) # <MCInst #{{[0-9]+}} SW_MM
381; MMR3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
382; MMR3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
383; MMR3-NEXT:    # <MCOperand Expr:(%lo(d))>>
384; MMR3-NEXT:    addiu $2, $1, %lo(d) # <MCInst #{{[0-9]+}} ADDiu
385; MMR3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
386; MMR3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
387; MMR3-NEXT:    # <MCOperand Expr:(%lo(d))>>
388; MMR3-NEXT:    sw16 $5, 4($2) # <MCInst #{{[0-9]+}} SW16_MM
389; MMR3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
390; MMR3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
391; MMR3-NEXT:    # <MCOperand Imm:4>>
392; MMR3-NEXT:    jrc $ra # <MCInst #{{[0-9]+}} JRC16_MM
393; MMR3-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
394;
395; MIPS32R6-LABEL: f4:
396; MIPS32R6:       # %bb.0:
397; MIPS32R6-NEXT:    lui $1, %hi(d) # <MCInst #{{[0-9]+}} LUi
398; MIPS32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
399; MIPS32R6-NEXT:    # <MCOperand Expr:(%hi(d))>>
400; MIPS32R6-NEXT:    sw $4, %lo(d)($1) # <MCInst #{{[0-9]+}} SW
401; MIPS32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
402; MIPS32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
403; MIPS32R6-NEXT:    # <MCOperand Expr:(%lo(d))>>
404; MIPS32R6-NEXT:    addiu $1, $1, %lo(d) # <MCInst #{{[0-9]+}} ADDiu
405; MIPS32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
406; MIPS32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
407; MIPS32R6-NEXT:    # <MCOperand Expr:(%lo(d))>>
408; MIPS32R6-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JALR
409; MIPS32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
410; MIPS32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
411; MIPS32R6-NEXT:    sw $5, 4($1) # <MCInst #{{[0-9]+}} SW
412; MIPS32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
413; MIPS32R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
414; MIPS32R6-NEXT:    # <MCOperand Imm:4>>
415;
416; MMR6-LABEL: f4:
417; MMR6:       # %bb.0:
418; MMR6-NEXT:    lui $1, %hi(d) # <MCInst #{{[0-9]+}} LUi
419; MMR6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
420; MMR6-NEXT:    # <MCOperand Expr:(%hi(d))>>
421; MMR6-NEXT:    sw $4, %lo(d)($1) # <MCInst #{{[0-9]+}} SW_MM
422; MMR6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
423; MMR6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
424; MMR6-NEXT:    # <MCOperand Expr:(%lo(d))>>
425; MMR6-NEXT:    addiu $2, $1, %lo(d) # <MCInst #{{[0-9]+}} ADDiu
426; MMR6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
427; MMR6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
428; MMR6-NEXT:    # <MCOperand Expr:(%lo(d))>>
429; MMR6-NEXT:    sw16 $5, 4($2) # <MCInst #{{[0-9]+}} SW16_MM
430; MMR6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
431; MMR6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
432; MMR6-NEXT:    # <MCOperand Imm:4>>
433; MMR6-NEXT:    jrc $ra # <MCInst #{{[0-9]+}} JRC16_MM
434; MMR6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
435;
436; MIPS4-LABEL: f4:
437; MIPS4:       # %bb.0:
438; MIPS4-NEXT:    lui $1, %highest(d) # <MCInst #{{[0-9]+}} LUi64
439; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
440; MIPS4-NEXT:    # <MCOperand Expr:(%highest(d))>>
441; MIPS4-NEXT:    daddiu $1, $1, %higher(d) # <MCInst #{{[0-9]+}} DADDiu
442; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
443; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
444; MIPS4-NEXT:    # <MCOperand Expr:(%higher(d))>>
445; MIPS4-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
446; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
447; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
448; MIPS4-NEXT:    # <MCOperand Imm:16>>
449; MIPS4-NEXT:    daddiu $1, $1, %hi(d) # <MCInst #{{[0-9]+}} DADDiu
450; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
451; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
452; MIPS4-NEXT:    # <MCOperand Expr:(%hi(d))>>
453; MIPS4-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
454; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
455; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
456; MIPS4-NEXT:    # <MCOperand Imm:16>>
457; MIPS4-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JR
458; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
459; MIPS4-NEXT:    sd $4, %lo(d)($1) # <MCInst #{{[0-9]+}} SD
460; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
461; MIPS4-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
462; MIPS4-NEXT:    # <MCOperand Expr:(%lo(d))>>
463;
464; MIPS64R6-LABEL: f4:
465; MIPS64R6:       # %bb.0:
466; MIPS64R6-NEXT:    lui $1, %highest(d) # <MCInst #{{[0-9]+}} LUi64
467; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
468; MIPS64R6-NEXT:    # <MCOperand Expr:(%highest(d))>>
469; MIPS64R6-NEXT:    daddiu $1, $1, %higher(d) # <MCInst #{{[0-9]+}} DADDiu
470; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
471; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
472; MIPS64R6-NEXT:    # <MCOperand Expr:(%higher(d))>>
473; MIPS64R6-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
474; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
475; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
476; MIPS64R6-NEXT:    # <MCOperand Imm:16>>
477; MIPS64R6-NEXT:    daddiu $1, $1, %hi(d) # <MCInst #{{[0-9]+}} DADDiu
478; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
479; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
480; MIPS64R6-NEXT:    # <MCOperand Expr:(%hi(d))>>
481; MIPS64R6-NEXT:    dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
482; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
483; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
484; MIPS64R6-NEXT:    # <MCOperand Imm:16>>
485; MIPS64R6-NEXT:    jr $ra # <MCInst #{{[0-9]+}} JALR64
486; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
487; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>>
488; MIPS64R6-NEXT:    sd $4, %lo(d)($1) # <MCInst #{{[0-9]+}} SD
489; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
490; MIPS64R6-NEXT:    # <MCOperand Reg:{{[0-9]+}}>
491; MIPS64R6-NEXT:    # <MCOperand Expr:(%lo(d))>>
492  store i64 %a, i64 * @d
493  ret void
494}
495