1; FIXME: FastISel currently returns false if it hits code that uses VSX 2; registers and with -fast-isel-abort=1 turned on the test case will then fail. 3; When fastisel better supports VSX fix up this test case. 4; 5; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=-vsx | FileCheck %s 6; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 -mattr=-vsx | FileCheck %s 7; RUN: llc < %s -O0 -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=970 -mattr=-vsx | FileCheck %s --check-prefix=PPC970 8; RUN: llc < %s -O0 -verify-machineinstrs -mtriple=powerpc-unknown-linux-gnu -mcpu=e500 -mattr=spe | FileCheck %s --check-prefix=SPE 9 10;; Tests for 970 don't use -fast-isel-abort=1 because we intentionally punt 11;; to SelectionDAG in some cases. 12 13; Test sitofp 14 15define void @sitofp_single_i64(i64 %a, float %b) nounwind { 16entry: 17; CHECK: sitofp_single_i64 18; PPC970: sitofp_single_i64 19 %b.addr = alloca float, align 4 20 %conv = sitofp i64 %a to float 21; CHECK: std 22; CHECK: lfd 23; CHECK: fcfids 24; PPC970: std 25; PPC970: lfd 26; PPC970: fcfid 27; PPC970: frsp 28 store float %conv, float* %b.addr, align 4 29 ret void 30} 31 32define void @sitofp_single_i32(i32 %a, float %b) nounwind { 33entry: 34; CHECK: sitofp_single_i32 35; PPC970: sitofp_single_i32 36 %b.addr = alloca float, align 4 37 %conv = sitofp i32 %a to float 38; CHECK: std 39; CHECK-NEXT: li 40; CHECK-NEXT: lfiwax 41; CHECK-NEXT: fcfids 42; PPC970: std 43; PPC970: lfd 44; PPC970: fcfid 45; PPC970: frsp 46; SPE: efscfsi 47 store float %conv, float* %b.addr, align 4 48 ret void 49} 50 51define void @sitofp_single_i16(i16 %a, float %b) nounwind { 52entry: 53; CHECK: sitofp_single_i16 54; PPC970: sitofp_single_i16 55 %b.addr = alloca float, align 4 56 %conv = sitofp i16 %a to float 57; CHECK: extsh 58; CHECK: std 59; CHECK: lfd 60; CHECK: fcfids 61; PPC970: extsh 62; PPC970: std 63; PPC970: lfd 64; PPC970: fcfid 65; PPC970: frsp 66; SPE: extsh 67; SPE: efscfsi 68 store float %conv, float* %b.addr, align 4 69 ret void 70} 71 72define void @sitofp_single_i8(i8 %a) nounwind { 73entry: 74; CHECK: sitofp_single_i8 75; PPC970: sitofp_single_i8 76 %b.addr = alloca float, align 4 77 %conv = sitofp i8 %a to float 78; CHECK: extsb 79; CHECK: std 80; CHECK: lfd 81; CHECK: fcfids 82; PPC970: extsb 83; PPC970: std 84; PPC970: lfd 85; PPC970: fcfid 86; PPC970: frsp 87; SPE: extsb 88; SPE: efscfsi 89 store float %conv, float* %b.addr, align 4 90 ret void 91} 92 93define void @sitofp_double_i32(i32 %a, double %b) nounwind { 94entry: 95; CHECK: sitofp_double_i32 96; PPC970: sitofp_double_i32 97 %b.addr = alloca double, align 8 98 %conv = sitofp i32 %a to double 99; CHECK: std 100; CHECK-NOT: ori 101; CHECK: li 102; CHECK-NOT: ori 103; CHECK: lfiwax 104; CHECK: fcfid 105; PPC970: std 106; PPC970: lfd 107; PPC970: fcfid 108; SPE: efdcfsi 109 store double %conv, double* %b.addr, align 8 110 ret void 111} 112 113define void @sitofp_double_i64(i64 %a, double %b) nounwind { 114entry: 115; CHECK: sitofp_double_i64 116; PPC970: sitofp_double_i64 117 %b.addr = alloca double, align 8 118 %conv = sitofp i64 %a to double 119; CHECK: std 120; CHECK: lfd 121; CHECK: fcfid 122; PPC970: std 123; PPC970: lfd 124; PPC970: fcfid 125 store double %conv, double* %b.addr, align 8 126 ret void 127} 128 129define void @sitofp_double_i16(i16 %a, double %b) nounwind { 130entry: 131; CHECK: sitofp_double_i16 132; PPC970: sitofp_double_i16 133 %b.addr = alloca double, align 8 134 %conv = sitofp i16 %a to double 135; CHECK: extsh 136; CHECK: std 137; CHECK: lfd 138; CHECK: fcfid 139; PPC970: extsh 140; PPC970: std 141; PPC970: lfd 142; PPC970: fcfid 143; SPE: extsh 144; SPE: efdcfsi 145 store double %conv, double* %b.addr, align 8 146 ret void 147} 148 149define void @sitofp_double_i8(i8 %a, double %b) nounwind { 150entry: 151; CHECK: sitofp_double_i8 152; PPC970: sitofp_double_i8 153 %b.addr = alloca double, align 8 154 %conv = sitofp i8 %a to double 155; CHECK: extsb 156; CHECK: std 157; CHECK: lfd 158; CHECK: fcfid 159; PPC970: extsb 160; PPC970: std 161; PPC970: lfd 162; PPC970: fcfid 163; SPE: extsb 164; SPE: efdcfsi 165 store double %conv, double* %b.addr, align 8 166 ret void 167} 168 169; Test uitofp 170 171define void @uitofp_single_i64(i64 %a, float %b) nounwind { 172entry: 173; CHECK: uitofp_single_i64 174; PPC970: uitofp_single_i64 175 %b.addr = alloca float, align 4 176 %conv = uitofp i64 %a to float 177; CHECK: std 178; CHECK: lfd 179; CHECK: fcfidus 180; PPC970-NOT: fcfidus 181 store float %conv, float* %b.addr, align 4 182 ret void 183} 184 185define void @uitofp_single_i32(i32 %a, float %b) nounwind { 186entry: 187; CHECK: uitofp_single_i32 188; PPC970: uitofp_single_i32 189 %b.addr = alloca float, align 4 190 %conv = uitofp i32 %a to float 191; CHECK: std 192; CHECK-NOT: ori 193; CHECK: li 194; CHECK-NOT: ori 195; CHECK: lfiwzx 196; CHECK: fcfidus 197; PPC970-NOT: lfiwzx 198; PPC970-NOT: fcfidus 199; SPE: efscfui 200 store float %conv, float* %b.addr, align 4 201 ret void 202} 203 204define void @uitofp_single_i16(i16 %a, float %b) nounwind { 205entry: 206; CHECK: uitofp_single_i16 207; PPC970: uitofp_single_i16 208 %b.addr = alloca float, align 4 209 %conv = uitofp i16 %a to float 210; CHECK: clrldi {{[0-9]+}}, {{[0-9]+}}, 48 211; CHECK: std 212; CHECK: lfd 213; CHECK: fcfidus 214; PPC970: clrlwi {{[0-9]+}}, {{[0-9]+}}, 16 215; PPC970: std 216; PPC970: lfd 217; PPC970: fcfid 218; PPC970: frsp 219; SPE: clrlwi {{[0-9]+}}, {{[0-9]+}}, 16 220; SPE: efscfui 221 store float %conv, float* %b.addr, align 4 222 ret void 223} 224 225define void @uitofp_single_i8(i8 %a) nounwind { 226entry: 227; CHECK: uitofp_single_i8 228; PPC970: uitofp_single_i8 229 %b.addr = alloca float, align 4 230 %conv = uitofp i8 %a to float 231; CHECK: clrldi {{[0-9]+}}, {{[0-9]+}}, 56 232; CHECK: std 233; CHECK: lfd 234; CHECK: fcfidus 235; PPC970: clrlwi {{[0-9]+}}, {{[0-9]+}}, 24 236; PPC970: std 237; PPC970: lfd 238; PPC970: fcfid 239; PPC970: frsp 240; SPE: clrlwi {{[0-9]+}}, {{[0-9]+}}, 24 241; SPE: efscfui 242 store float %conv, float* %b.addr, align 4 243 ret void 244} 245 246define void @uitofp_double_i64(i64 %a, double %b) nounwind { 247entry: 248; CHECK: uitofp_double_i64 249; PPC970: uitofp_double_i64 250 %b.addr = alloca double, align 8 251 %conv = uitofp i64 %a to double 252; CHECK: std 253; CHECK: lfd 254; CHECK: fcfidu 255; PPC970-NOT: fcfidu 256 store double %conv, double* %b.addr, align 8 257 ret void 258} 259 260define void @uitofp_double_i32(i32 %a, double %b) nounwind { 261entry: 262; CHECK: uitofp_double_i32 263; PPC970: uitofp_double_i32 264 %b.addr = alloca double, align 8 265 %conv = uitofp i32 %a to double 266; CHECK: std 267; CHECK-NEXT: li 268; CHECK-NEXT: lfiwzx 269; CHECK-NEXT: fcfidu 270; CHECKLE: fcfidu 271; PPC970-NOT: lfiwzx 272; PPC970-NOT: fcfidu 273; SPE: efdcfui 274 store double %conv, double* %b.addr, align 8 275 ret void 276} 277 278define void @uitofp_double_i16(i16 %a, double %b) nounwind { 279entry: 280; CHECK: uitofp_double_i16 281; PPC970: uitofp_double_i16 282 %b.addr = alloca double, align 8 283 %conv = uitofp i16 %a to double 284; CHECK: clrldi {{[0-9]+}}, {{[0-9]+}}, 48 285; CHECK: std 286; CHECK: lfd 287; CHECK: fcfidu 288; PPC970: clrlwi {{[0-9]+}}, {{[0-9]+}}, 16 289; PPC970: std 290; PPC970: lfd 291; PPC970: fcfid 292; SPE: clrlwi {{[0-9]+}}, {{[0-9]+}}, 16 293; SPE: efdcfui 294 store double %conv, double* %b.addr, align 8 295 ret void 296} 297 298define void @uitofp_double_i8(i8 %a, double %b) nounwind { 299entry: 300; CHECK: uitofp_double_i8 301; PPC970: uitofp_double_i8 302 %b.addr = alloca double, align 8 303 %conv = uitofp i8 %a to double 304; CHECK: clrldi {{[0-9]+}}, {{[0-9]+}}, 56 305; CHECK: std 306; CHECK: lfd 307; CHECK: fcfidu 308; PPC970: clrlwi {{[0-9]+}}, {{[0-9]+}}, 24 309; PPC970: std 310; PPC970: lfd 311; PPC970: fcfid 312; SPE: clrlwi {{[0-9]+}}, {{[0-9]+}}, 24 313; SPE: efdcfui 314 store double %conv, double* %b.addr, align 8 315 ret void 316} 317 318; Test fptosi 319 320define void @fptosi_float_i32(float %a) nounwind { 321entry: 322; CHECK: fptosi_float_i32 323; PPC970: fptosi_float_i32 324 %b.addr = alloca i32, align 4 325 %conv = fptosi float %a to i32 326; CHECK: fctiwz 327; CHECK: stfd 328; CHECK: lwa 329; PPC970: fctiwz 330; PPC970: stfd 331; PPC970: lwa 332; SPE: efsctsi 333 store i32 %conv, i32* %b.addr, align 4 334 ret void 335} 336 337define void @fptosi_float_i64(float %a) nounwind { 338entry: 339; CHECK: fptosi_float_i64 340; PPC970: fptosi_float_i64 341 %b.addr = alloca i64, align 4 342 %conv = fptosi float %a to i64 343; CHECK: fctidz 344; CHECK: stfd 345; CHECK: ld 346; PPC970: fctidz 347; PPC970: stfd 348; PPC970: ld 349 store i64 %conv, i64* %b.addr, align 4 350 ret void 351} 352 353define void @fptosi_double_i32(double %a) nounwind { 354entry: 355; CHECK: fptosi_double_i32 356; PPC970: fptosi_double_i32 357 %b.addr = alloca i32, align 8 358 %conv = fptosi double %a to i32 359; CHECK: fctiwz 360; CHECK: stfd 361; CHECK: lwa 362; PPC970: fctiwz 363; PPC970: stfd 364; PPC970: lwa 365; SPE: efdctsi 366 store i32 %conv, i32* %b.addr, align 8 367 ret void 368} 369 370define void @fptosi_double_i64(double %a) nounwind { 371entry: 372; CHECK: fptosi_double_i64 373; PPC970: fptosi_double_i64 374 %b.addr = alloca i64, align 8 375 %conv = fptosi double %a to i64 376; CHECK: fctidz 377; CHECK: stfd 378; CHECK: ld 379; PPC970: fctidz 380; PPC970: stfd 381; PPC970: ld 382 store i64 %conv, i64* %b.addr, align 8 383 ret void 384} 385 386; Test fptoui 387 388define void @fptoui_float_i32(float %a) nounwind { 389entry: 390; CHECK: fptoui_float_i32 391; PPC970: fptoui_float_i32 392 %b.addr = alloca i32, align 4 393 %conv = fptoui float %a to i32 394; CHECK: fctiwuz 395; CHECK: stfd 396; CHECK: lwz 397; PPC970: fctidz 398; PPC970: stfd 399; PPC970: lwz 400; SPE: efsctui 401 store i32 %conv, i32* %b.addr, align 4 402 ret void 403} 404 405define void @fptoui_float_i64(float %a) nounwind { 406entry: 407; CHECK: fptoui_float_i64 408; PPC970: fptoui_float_i64 409 %b.addr = alloca i64, align 4 410 %conv = fptoui float %a to i64 411; CHECK: fctiduz 412; CHECK: stfd 413; CHECK: ld 414; PPC970-NOT: fctiduz 415 store i64 %conv, i64* %b.addr, align 4 416 ret void 417} 418 419define void @fptoui_double_i32(double %a) nounwind { 420entry: 421; CHECK: fptoui_double_i32 422; PPC970: fptoui_double_i32 423 %b.addr = alloca i32, align 8 424 %conv = fptoui double %a to i32 425; CHECK: fctiwuz 426; CHECK: stfd 427; CHECK: lwz 428; PPC970: fctidz 429; PPC970: stfd 430; PPC970: lwz 431; SPE: efdctui 432 store i32 %conv, i32* %b.addr, align 8 433 ret void 434} 435 436define void @fptoui_double_i64(double %a) nounwind { 437entry: 438; CHECK: fptoui_double_i64 439; PPC970: fptoui_double_i64 440 %b.addr = alloca i64, align 8 441 %conv = fptoui double %a to i64 442; CHECK: fctiduz 443; CHECK: stfd 444; CHECK: ld 445; PPC970-NOT: fctiduz 446 store i64 %conv, i64* %b.addr, align 8 447 ret void 448} 449