1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
3; RUN:   -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
4; RUN:   FileCheck %s
5; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
6; RUN:   -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
7; RUN:   FileCheck %s
8
9; This test case aims to test the vector modulo instructions on Power10.
10; The vector modulo instructions operate on signed and unsigned words
11; and doublewords.
12
13; The vector modulo instructions operate on signed and unsigned words,
14; doublewords and 128-bit values.
15
16
17define <1 x i128> @test_vmodsq(<1 x i128> %x, <1 x i128> %y) nounwind readnone {
18; CHECK-LABEL: test_vmodsq:
19; CHECK:       # %bb.0:
20; CHECK-NEXT:    vmodsq v2, v2, v3
21; CHECK-NEXT:    blr
22  %tmp = srem <1 x i128> %x, %y
23  ret <1 x i128> %tmp
24}
25
26define <1 x i128> @test_vmoduq(<1 x i128> %x, <1 x i128> %y) nounwind readnone {
27; CHECK-LABEL: test_vmoduq:
28; CHECK:       # %bb.0:
29; CHECK-NEXT:    vmoduq v2, v2, v3
30; CHECK-NEXT:    blr
31  %tmp = urem <1 x i128> %x, %y
32  ret <1 x i128> %tmp
33}
34
35define <2 x i64> @test_vmodud(<2 x i64> %a, <2 x i64> %b) {
36; CHECK-LABEL: test_vmodud:
37; CHECK:       # %bb.0: # %entry
38; CHECK-NEXT:    vmodud v2, v2, v3
39; CHECK-NEXT:    blr
40entry:
41  %rem = urem <2 x i64> %a, %b
42  ret <2 x i64> %rem
43}
44
45define <2 x i64> @test_vmodsd(<2 x i64> %a, <2 x i64> %b) {
46; CHECK-LABEL: test_vmodsd:
47; CHECK:       # %bb.0: # %entry
48; CHECK-NEXT:    vmodsd v2, v2, v3
49; CHECK-NEXT:    blr
50entry:
51  %rem = srem <2 x i64> %a, %b
52  ret <2 x i64> %rem
53}
54
55define <4 x i32> @test_vmoduw(<4 x i32> %a, <4 x i32> %b) {
56; CHECK-LABEL: test_vmoduw:
57; CHECK:       # %bb.0: # %entry
58; CHECK-NEXT:    vmoduw v2, v2, v3
59; CHECK-NEXT:    blr
60entry:
61  %rem = urem <4 x i32> %a, %b
62  ret <4 x i32> %rem
63}
64
65define <4 x i32> @test_vmodsw(<4 x i32> %a, <4 x i32> %b) {
66; CHECK-LABEL: test_vmodsw:
67; CHECK:       # %bb.0: # %entry
68; CHECK-NEXT:    vmodsw v2, v2, v3
69; CHECK-NEXT:    blr
70entry:
71  %rem = srem <4 x i32> %a, %b
72  ret <4 x i32> %rem
73}
74
75define <2 x i64> @test_vmodud_with_div(<2 x i64> %a, <2 x i64> %b) {
76; CHECK-LABEL: test_vmodud_with_div:
77; CHECK:       # %bb.0: # %entry
78; CHECK-NEXT:    vmodud v4, v2, v3
79; CHECK-NEXT:    vdivud v2, v2, v3
80; CHECK-NEXT:    vaddudm v2, v4, v2
81; CHECK-NEXT:    blr
82entry:
83  %rem = urem <2 x i64> %a, %b
84  %div = udiv <2 x i64> %a, %b
85  %add = add <2 x i64> %rem, %div
86  ret <2 x i64> %add
87}
88
89define <2 x i64> @test_vmodsd_with_div(<2 x i64> %a, <2 x i64> %b) {
90; CHECK-LABEL: test_vmodsd_with_div:
91; CHECK:       # %bb.0: # %entry
92; CHECK-NEXT:    vmodsd v4, v2, v3
93; CHECK-NEXT:    vdivsd v2, v2, v3
94; CHECK-NEXT:    vaddudm v2, v4, v2
95; CHECK-NEXT:    blr
96entry:
97  %rem = srem <2 x i64> %a, %b
98  %div = sdiv <2 x i64> %a, %b
99  %add = add <2 x i64> %rem, %div
100  ret <2 x i64> %add
101}
102
103define <4 x i32> @test_vmoduw_with_div(<4 x i32> %a, <4 x i32> %b) {
104; CHECK-LABEL: test_vmoduw_with_div:
105; CHECK:       # %bb.0: # %entry
106; CHECK-NEXT:    vmoduw v4, v2, v3
107; CHECK-NEXT:    vdivuw v2, v2, v3
108; CHECK-NEXT:    vadduwm v2, v4, v2
109; CHECK-NEXT:    blr
110entry:
111  %rem = urem <4 x i32> %a, %b
112  %div = udiv <4 x i32> %a, %b
113  %add = add <4 x i32> %rem, %div
114  ret <4 x i32> %add
115}
116
117define <4 x i32> @test_vmodsw_div(<4 x i32> %a, <4 x i32> %b) {
118; CHECK-LABEL: test_vmodsw_div:
119; CHECK:       # %bb.0: # %entry
120; CHECK-NEXT:    vmodsw v4, v2, v3
121; CHECK-NEXT:    vdivsw v2, v2, v3
122; CHECK-NEXT:    vadduwm v2, v4, v2
123; CHECK-NEXT:    blr
124entry:
125  %rem = srem <4 x i32> %a, %b
126  %div = sdiv <4 x i32> %a, %b
127  %add = add <4 x i32> %rem, %div
128  ret <4 x i32> %add
129}
130