1; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown \
2; RUN:   -ppc-asm-full-reg-names < %s | FileCheck %s
3; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mtriple=powerpc64le-unknown-unknown \
4; RUN:   -ppc-asm-full-reg-names < %s | FileCheck %s -check-prefix=CHECK-PWR8    \
5; RUN:   -implicit-check-not "\<setb\>"
6
7; Test different patterns with type i64
8
9; select_cc lhs, rhs, -1, (zext (setcc lhs, rhs, setne)), setlt
10define i64 @setb1(i64 %a, i64 %b) {
11  %t1 = icmp slt i64 %a, %b
12  %t2 = icmp ne i64 %a, %b
13  %t3 = zext i1 %t2 to i64
14  %t4 = select i1 %t1, i64 -1, i64 %t3
15  ret i64 %t4
16; CHECK-LABEL: setb1:
17; CHECK-NOT: xor
18; CHECK-NOT: li
19; CHECK: cmpd {{c?r?(0, )?}}r3, r4
20; CHECK-NEXT: setb r3, cr0
21; CHECK-NOT: addic
22; CHECK-NOT: subfe
23; CHECK-NOT: isel
24; CHECK: blr
25; CHECK-PWR8-LABEL: setb1
26; CHECK-PWR8-DAG: xor
27; CHECK-PWR8-DAG: li
28; CHECK-PWR8-DAG: cmpd
29; CHECK-PWR8-DAG: addic
30; CHECK-PWR8-DAG: subfe
31; CHECK-PWR8: isel
32; CHECK-PWR8: blr
33}
34
35; select_cc lhs, rhs, -1, (zext (setcc rhs, lhs, setne)), setgt
36define i64 @setb2(i64 %a, i64 %b) {
37  %t1 = icmp sgt i64 %b, %a
38  %t2 = icmp ne i64 %a, %b
39  %t3 = zext i1 %t2 to i64
40  %t4 = select i1 %t1, i64 -1, i64 %t3
41  ret i64 %t4
42; CHECK-LABEL: setb2:
43; CHECK-NOT: xor
44; CHECK-NOT: li
45; CHECK: cmpd {{c?r?(0, )?}}r3, r4
46; CHECK-NEXT: setb r3, cr0
47; CHECK-NOT: addic
48; CHECK-NOT: subfe
49; CHECK-NOT: isel
50; CHECK: blr
51; CHECK-PWR8-LABEL: setb2
52; CHECK-PWR8-DAG: xor
53; CHECK-PWR8-DAG: li
54; CHECK-PWR8-DAG: cmpd
55; CHECK-PWR8-DAG: addic
56; CHECK-PWR8-DAG: subfe
57; CHECK-PWR8: isel
58; CHECK-PWR8: blr
59}
60
61; select_cc lhs, rhs, -1, (zext (setcc rhs, lhs, setne)), setlt
62define i64 @setb3(i64 %a, i64 %b) {
63  %t1 = icmp slt i64 %a, %b
64  %t2 = icmp ne i64 %b, %a
65  %t3 = zext i1 %t2 to i64
66  %t4 = select i1 %t1, i64 -1, i64 %t3
67  ret i64 %t4
68; CHECK-LABEL: setb3:
69; CHECK-NOT: xor
70; CHECK-NOT: li
71; CHECK: cmpd {{c?r?(0, )?}}r3, r4
72; CHECK-NEXT: setb r3, cr0
73; CHECK-NOT: addic
74; CHECK-NOT: subfe
75; CHECK-NOT: isel
76; CHECK: blr
77; CHECK-PWR8-LABEL: setb3
78; CHECK-PWR8-DAG: xor
79; CHECK-PWR8-DAG: li
80; CHECK-PWR8-DAG: cmpd
81; CHECK-PWR8-DAG: addic
82; CHECK-PWR8-DAG: subfe
83; CHECK-PWR8: isel
84; CHECK-PWR8: blr
85}
86
87; select_cc lhs, rhs, -1, (zext (setcc lhs, rhs, setne)), setgt
88define i64 @setb4(i64 %a, i64 %b) {
89  %t1 = icmp sgt i64 %b, %a
90  %t2 = icmp ne i64 %b, %a
91  %t3 = zext i1 %t2 to i64
92  %t4 = select i1 %t1, i64 -1, i64 %t3
93  ret i64 %t4
94; CHECK-LABEL: setb4:
95; CHECK-NOT: xor
96; CHECK-NOT: li
97; CHECK: cmpd {{c?r?(0, )?}}r3, r4
98; CHECK-NEXT: setb r3, cr0
99; CHECK-NOT: addic
100; CHECK-NOT: subfe
101; CHECK-NOT: isel
102; CHECK: blr
103; CHECK-PWR8-LABEL: setb4
104; CHECK-PWR8-DAG: xor
105; CHECK-PWR8-DAG: li
106; CHECK-PWR8-DAG: cmpd
107; CHECK-PWR8-DAG: addic
108; CHECK-PWR8-DAG: subfe
109; CHECK-PWR8: isel
110; CHECK-PWR8: blr
111}
112
113; select_cc lhs, rhs, -1, (zext (setcc lhs, rhs, setgt)), setlt
114define i64 @setb5(i64 %a, i64 %b) {
115  %t1 = icmp slt i64 %a, %b
116  %t2 = icmp sgt i64 %a, %b
117  %t3 = zext i1 %t2 to i64
118  %t4 = select i1 %t1, i64 -1, i64 %t3
119  ret i64 %t4
120; CHECK-LABEL: setb5:
121; CHECK-NOT: sradi
122; CHECK-NOT: rldicl
123; CHECK-NOT: li
124; CHECK: cmpd {{c?r?(0, )?}}r3, r4
125; CHECK-NEXT: setb r3, cr0
126; CHECK-NOT: subc
127; CHECK-NOT: adde
128; CHECK-NOT: xori
129; CHECK-NOT: isel
130; CHECK: blr
131; CHECK-PWR8-LABEL: setb5
132; CHECK-PWR8-DAG: sradi
133; CHECK-PWR8-DAG: rldicl
134; CHECK-PWR8-DAG: li
135; CHECK-PWR8-DAG: cmpd
136; CHECK-PWR8-DAG: subc
137; CHECK-PWR8-DAG: adde
138; CHECK-PWR8-DAG: xori
139; CHECK-PWR8: isel
140; CHECK-PWR8: blr
141}
142
143; select_cc lhs, rhs, -1, (zext (setcc rhs, lhs, setgt)), setgt
144define i64 @setb6(i64 %a, i64 %b) {
145  %t1 = icmp sgt i64 %b, %a
146  %t2 = icmp sgt i64 %a, %b
147  %t3 = zext i1 %t2 to i64
148  %t4 = select i1 %t1, i64 -1, i64 %t3
149  ret i64 %t4
150; CHECK-LABEL: setb6:
151; CHECK-NOT: sradi
152; CHECK-NOT: rldicl
153; CHECK-NOT: li
154; CHECK: cmpd {{c?r?(0, )?}}r3, r4
155; CHECK-NEXT: setb r3, cr0
156; CHECK-NOT: subc
157; CHECK-NOT: adde
158; CHECK-NOT: xori
159; CHECK-NOT: isel
160; CHECK: blr
161; CHECK-PWR8-LABEL: setb6
162; CHECK-PWR8-DAG: sradi
163; CHECK-PWR8-DAG: rldicl
164; CHECK-PWR8-DAG: li
165; CHECK-PWR8-DAG: cmpd
166; CHECK-PWR8-DAG: subc
167; CHECK-PWR8-DAG: adde
168; CHECK-PWR8-DAG: xori
169; CHECK-PWR8: isel
170; CHECK-PWR8: blr
171}
172
173; select_cc lhs, rhs, -1, (zext (setcc rhs, lhs, setlt)), setlt
174define i64 @setb7(i64 %a, i64 %b) {
175  %t1 = icmp slt i64 %a, %b
176  %t2 = icmp slt i64 %b, %a
177  %t3 = zext i1 %t2 to i64
178  %t4 = select i1 %t1, i64 -1, i64 %t3
179  ret i64 %t4
180; CHECK-LABEL: setb7:
181; CHECK-NOT: sradi
182; CHECK-NOT: rldicl
183; CHECK-NOT: li
184; CHECK: cmpd {{c?r?(0, )?}}r3, r4
185; CHECK-NEXT: setb r3, cr0
186; CHECK-NOT: subc
187; CHECK-NOT: adde
188; CHECK-NOT: xori
189; CHECK-NOT: isel
190; CHECK: blr
191; CHECK-PWR8-LABEL: setb7
192; CHECK-PWR8-DAG: sradi
193; CHECK-PWR8-DAG: rldicl
194; CHECK-PWR8-DAG: li
195; CHECK-PWR8-DAG: cmpd
196; CHECK-PWR8-DAG: subc
197; CHECK-PWR8-DAG: adde
198; CHECK-PWR8-DAG: xori
199; CHECK-PWR8: isel
200; CHECK-PWR8: blr
201}
202
203; select_cc lhs, rhs, -1, (zext (setcc lhs, rhs, setlt)), setgt
204define i64 @setb8(i64 %a, i64 %b) {
205  %t1 = icmp sgt i64 %b, %a
206  %t2 = icmp slt i64 %b, %a
207  %t3 = zext i1 %t2 to i64
208  %t4 = select i1 %t1, i64 -1, i64 %t3
209  ret i64 %t4
210; CHECK-LABEL: setb8:
211; CHECK-NOT: sradi
212; CHECK-NOT: rldicl
213; CHECK-NOT: li
214; CHECK: cmpd {{c?r?(0, )?}}r3, r4
215; CHECK-NEXT: setb r3, cr0
216; CHECK-NOT: subc
217; CHECK-NOT: adde
218; CHECK-NOT: xori
219; CHECK-NOT: isel
220; CHECK: blr
221; CHECK-PWR8-LABEL: setb8
222; CHECK-PWR8-DAG: sradi
223; CHECK-PWR8-DAG: rldicl
224; CHECK-PWR8-DAG: li
225; CHECK-PWR8-DAG: cmpd
226; CHECK-PWR8-DAG: subc
227; CHECK-PWR8-DAG: adde
228; CHECK-PWR8-DAG: xori
229; CHECK-PWR8: isel
230; CHECK-PWR8: blr
231}
232
233; select_cc lhs, rhs, 1, (sext (setcc lhs, rhs, setne)), setgt
234define i64 @setb9(i64 %a, i64 %b) {
235  %t1 = icmp sgt i64 %a, %b
236  %t2 = icmp ne i64 %a, %b
237  %t3 = sext i1 %t2 to i64
238  %t4 = select i1 %t1, i64 1, i64 %t3
239  ret i64 %t4
240; CHECK-LABEL: setb9:
241; CHECK-NOT: xor
242; CHECK-NOT: li
243; CHECK: cmpd {{c?r?(0, )?}}r3, r4
244; CHECK-NEXT: setb r3, cr0
245; CHECK-NOT: subfic
246; CHECK-NOT: subfe
247; CHECK-NOT: isel
248; CHECK: blr
249; CHECK-PWR8-LABEL: setb9
250; CHECK-PWR8-DAG: xor
251; CHECK-PWR8-DAG: li
252; CHECK-PWR8-DAG: cmpd
253; CHECK-PWR8-DAG: subfic
254; CHECK-PWR8-DAG: subfe
255; CHECK-PWR8: isel
256; CHECK-PWR8: blr
257}
258
259; select_cc lhs, rhs, 1, (sext (setcc rhs, lhs, setne)), setlt
260define i64 @setb10(i64 %a, i64 %b) {
261  %t1 = icmp slt i64 %b, %a
262  %t2 = icmp ne i64 %a, %b
263  %t3 = sext i1 %t2 to i64
264  %t4 = select i1 %t1, i64 1, i64 %t3
265  ret i64 %t4
266; CHECK-LABEL: setb10:
267; CHECK-NOT: xor
268; CHECK-NOT: li
269; CHECK: cmpd {{c?r?(0, )?}}r3, r4
270; CHECK-NEXT: setb r3, cr0
271; CHECK-NOT: subfic
272; CHECK-NOT: subfe
273; CHECK-NOT: isel
274; CHECK: blr
275; CHECK-PWR8-LABEL: setb10
276; CHECK-PWR8-DAG: xor
277; CHECK-PWR8-DAG: li
278; CHECK-PWR8-DAG: cmpd
279; CHECK-PWR8-DAG: subfic
280; CHECK-PWR8-DAG: subfe
281; CHECK-PWR8: isel
282; CHECK-PWR8: blr
283}
284
285; select_cc lhs, rhs, 1, (sext (setcc rhs, lhs, setne)), setgt
286define i64 @setb11(i64 %a, i64 %b) {
287  %t1 = icmp sgt i64 %a, %b
288  %t2 = icmp ne i64 %b, %a
289  %t3 = sext i1 %t2 to i64
290  %t4 = select i1 %t1, i64 1, i64 %t3
291  ret i64 %t4
292; CHECK-LABEL: setb11:
293; CHECK-NOT: xor
294; CHECK-NOT: li
295; CHECK: cmpd {{c?r?(0, )?}}r3, r4
296; CHECK-NEXT: setb r3, cr0
297; CHECK-NOT: subfic
298; CHECK-NOT: subfe
299; CHECK-NOT: isel
300; CHECK: blr
301; CHECK-PWR8-LABEL: setb11
302; CHECK-PWR8-DAG: xor
303; CHECK-PWR8-DAG: li
304; CHECK-PWR8-DAG: cmpd
305; CHECK-PWR8-DAG: subfic
306; CHECK-PWR8-DAG: subfe
307; CHECK-PWR8: isel
308; CHECK-PWR8: blr
309}
310
311; select_cc lhs, rhs, 1, (sext (setcc lhs, rhs, setne)), setlt
312define i64 @setb12(i64 %a, i64 %b) {
313  %t1 = icmp slt i64 %b, %a
314  %t2 = icmp ne i64 %b, %a
315  %t3 = sext i1 %t2 to i64
316  %t4 = select i1 %t1, i64 1, i64 %t3
317  ret i64 %t4
318; CHECK-LABEL: setb12:
319; CHECK-NOT: xor
320; CHECK-NOT: li
321; CHECK: cmpd {{c?r?(0, )?}}r3, r4
322; CHECK-NEXT: setb r3, cr0
323; CHECK-NOT: subfic
324; CHECK-NOT: subfe
325; CHECK-NOT: isel
326; CHECK: blr
327; CHECK-PWR8-LABEL: setb12
328; CHECK-PWR8-DAG: xor
329; CHECK-PWR8-DAG: li
330; CHECK-PWR8-DAG: cmpd
331; CHECK-PWR8-DAG: subfic
332; CHECK-PWR8-DAG: subfe
333; CHECK-PWR8: isel
334; CHECK-PWR8: blr
335}
336
337; select_cc lhs, rhs, 1, (sext (setcc lhs, rhs, setlt)), setgt
338define i64 @setb13(i64 %a, i64 %b) {
339  %t1 = icmp sgt i64 %a, %b
340  %t2 = icmp slt i64 %a, %b
341  %t3 = sext i1 %t2 to i64
342  %t4 = select i1 %t1, i64 1, i64 %t3
343  ret i64 %t4
344; CHECK-LABEL: setb13:
345; CHECK-NOT: sradi
346; CHECK-NOT: rldicl
347; CHECK-NOT: li
348; CHECK: cmpd {{c?r?(0, )?}}r3, r4
349; CHECK-NEXT: setb r3, cr0
350; CHECK-NOT: subc
351; CHECK-NOT: adde
352; CHECK-NOT: xori
353; CHECK-NOT: neg
354; CHECK-NOT: isel
355; CHECK: blr
356; CHECK-PWR8-LABEL: setb13
357; CHECK-PWR8-DAG: sradi
358; CHECK-PWR8-DAG: rldicl
359; CHECK-PWR8-DAG: li
360; CHECK-PWR8-DAG: cmpd
361; CHECK-PWR8-DAG: subc
362; CHECK-PWR8-DAG: adde
363; CHECK-PWR8-DAG: xori
364; CHECK-PWR8-DAG: neg
365; CHECK-PWR8: isel
366; CHECK-PWR8: blr
367}
368
369; select_cc lhs, rhs, 1, (sext (setcc rhs, lhs, setlt)), setlt
370define i64 @setb14(i64 %a, i64 %b) {
371  %t1 = icmp slt i64 %b, %a
372  %t2 = icmp slt i64 %a, %b
373  %t3 = sext i1 %t2 to i64
374  %t4 = select i1 %t1, i64 1, i64 %t3
375  ret i64 %t4
376; CHECK-LABEL: setb14:
377; CHECK-NOT: sradi
378; CHECK-NOT: rldicl
379; CHECK-NOT: li
380; CHECK: cmpd {{c?r?(0, )?}}r3, r4
381; CHECK-NEXT: setb r3, cr0
382; CHECK-NOT: subc
383; CHECK-NOT: adde
384; CHECK-NOT: xori
385; CHECK-NOT: neg
386; CHECK-NOT: isel
387; CHECK: blr
388; CHECK-PWR8-LABEL: setb14
389; CHECK-PWR8-DAG: sradi
390; CHECK-PWR8-DAG: rldicl
391; CHECK-PWR8-DAG: li
392; CHECK-PWR8-DAG: cmpd
393; CHECK-PWR8-DAG: subc
394; CHECK-PWR8-DAG: adde
395; CHECK-PWR8-DAG: xori
396; CHECK-PWR8-DAG: neg
397; CHECK-PWR8: isel
398; CHECK-PWR8: blr
399}
400
401; select_cc lhs, rhs, 1, (sext (setcc rhs, lhs, setgt)), setgt
402define i64 @setb15(i64 %a, i64 %b) {
403  %t1 = icmp sgt i64 %a, %b
404  %t2 = icmp sgt i64 %b, %a
405  %t3 = sext i1 %t2 to i64
406  %t4 = select i1 %t1, i64 1, i64 %t3
407  ret i64 %t4
408; CHECK-LABEL: setb15:
409; CHECK-NOT: sradi
410; CHECK-NOT: rldicl
411; CHECK-NOT: li
412; CHECK: cmpd {{c?r?(0, )?}}r3, r4
413; CHECK-NEXT: setb r3, cr0
414; CHECK-NOT: subc
415; CHECK-NOT: adde
416; CHECK-NOT: xori
417; CHECK-NOT: neg
418; CHECK-NOT: isel
419; CHECK: blr
420; CHECK-PWR8-LABEL: setb15
421; CHECK-PWR8-DAG: sradi
422; CHECK-PWR8-DAG: rldicl
423; CHECK-PWR8-DAG: li
424; CHECK-PWR8-DAG: cmpd
425; CHECK-PWR8-DAG: subc
426; CHECK-PWR8-DAG: adde
427; CHECK-PWR8-DAG: xori
428; CHECK-PWR8-DAG: neg
429; CHECK-PWR8: isel
430; CHECK-PWR8: blr
431}
432
433; select_cc lhs, rhs, 1, (sext (setcc lhs, rhs, setgt)), setlt
434define i64 @setb16(i64 %a, i64 %b) {
435  %t1 = icmp slt i64 %b, %a
436  %t2 = icmp sgt i64 %b, %a
437  %t3 = sext i1 %t2 to i64
438  %t4 = select i1 %t1, i64 1, i64 %t3
439  ret i64 %t4
440; CHECK-LABEL: setb16:
441; CHECK-NOT: sradi
442; CHECK-NOT: rldicl
443; CHECK-NOT: li
444; CHECK: cmpd {{c?r?(0, )?}}r3, r4
445; CHECK-NEXT: setb r3, cr0
446; CHECK-NOT: subc
447; CHECK-NOT: adde
448; CHECK-NOT: xori
449; CHECK-NOT: neg
450; CHECK-NOT: isel
451; CHECK: blr
452; CHECK-PWR8-LABEL: setb16
453; CHECK-PWR8-DAG: sradi
454; CHECK-PWR8-DAG: rldicl
455; CHECK-PWR8-DAG: li
456; CHECK-PWR8-DAG: cmpd
457; CHECK-PWR8-DAG: subc
458; CHECK-PWR8-DAG: adde
459; CHECK-PWR8-DAG: xori
460; CHECK-PWR8-DAG: neg
461; CHECK-PWR8: isel
462; CHECK-PWR8: blr
463}
464
465; select_cc lhs, rhs, 0, (select_cc lhs, rhs, 1, -1, setgt), seteq
466define i64 @setb17(i64 %a, i64 %b) {
467  %t1 = icmp eq i64 %a, %b
468  %t2 = icmp sgt i64 %a, %b
469  %t3 = select i1 %t2, i64 1, i64 -1
470  %t4 = select i1 %t1, i64 0, i64 %t3
471  ret i64 %t4
472; CHECK-LABEL: setb17:
473; CHECK-NOT: li
474; CHECK-NOT: cmpld
475; CHECK-NOT: isel
476; CHECK: cmpd {{c?r?(0, )?}}r3, r4
477; CHECK-NEXT: setb r3, cr0
478; CHECK-NOT: isel
479; CHECK: blr
480; CHECK-PWR8-LABEL: setb17
481; CHECK-PWR8: cmpd
482; CHECK-PWR8: isel
483; CHECK-PWR8: cmpld
484; CHECK-PWR8: isel
485; CHECK-PWR8: blr
486}
487
488; select_cc lhs, rhs, 0, (select_cc rhs, lhs, 1, -1, setgt), seteq
489define i64 @setb18(i64 %a, i64 %b) {
490  %t1 = icmp eq i64 %b, %a
491  %t2 = icmp sgt i64 %a, %b
492  %t3 = select i1 %t2, i64 1, i64 -1
493  %t4 = select i1 %t1, i64 0, i64 %t3
494  ret i64 %t4
495; CHECK-LABEL: setb18:
496; CHECK-NOT: li
497; CHECK-NOT: cmpld
498; CHECK-NOT: isel
499; CHECK: cmpd {{c?r?(0, )?}}r3, r4
500; CHECK-NEXT: setb r3, cr0
501; CHECK-NOT: isel
502; CHECK: blr
503; CHECK-PWR8-LABEL: setb18
504; CHECK-PWR8: cmpd
505; CHECK-PWR8: isel
506; CHECK-PWR8: cmpld
507; CHECK-PWR8: isel
508; CHECK-PWR8: blr
509}
510
511; select_cc lhs, rhs, 0, (select_cc rhs, lhs, 1, -1, setlt), seteq
512define i64 @setb19(i64 %a, i64 %b) {
513  %t1 = icmp eq i64 %a, %b
514  %t2 = icmp slt i64 %b, %a
515  %t3 = select i1 %t2, i64 1, i64 -1
516  %t4 = select i1 %t1, i64 0, i64 %t3
517  ret i64 %t4
518; CHECK-LABEL: setb19:
519; CHECK-NOT: li
520; CHECK-NOT: cmpld
521; CHECK-NOT: isel
522; CHECK: cmpd {{c?r?(0, )?}}r3, r4
523; CHECK-NEXT: setb r3, cr0
524; CHECK-NOT: isel
525; CHECK: blr
526; CHECK-PWR8-LABEL: setb19
527; CHECK-PWR8: cmpd
528; CHECK-PWR8: isel
529; CHECK-PWR8: cmpld
530; CHECK-PWR8: isel
531; CHECK-PWR8: blr
532}
533
534; select_cc lhs, rhs, 0, (select_cc lhs, rhs, 1, -1, setlt), seteq
535define i64 @setb20(i64 %a, i64 %b) {
536  %t1 = icmp eq i64 %b, %a
537  %t2 = icmp slt i64 %b, %a
538  %t3 = select i1 %t2, i64 1, i64 -1
539  %t4 = select i1 %t1, i64 0, i64 %t3
540  ret i64 %t4
541; CHECK-LABEL: setb20:
542; CHECK-NOT: li
543; CHECK-NOT: cmpld
544; CHECK-NOT: isel
545; CHECK: cmpd {{c?r?(0, )?}}r3, r4
546; CHECK-NEXT: setb r3, cr0
547; CHECK-NOT: isel
548; CHECK: blr
549; CHECK-PWR8-LABEL: setb20
550; CHECK-PWR8: cmpd
551; CHECK-PWR8: isel
552; CHECK-PWR8: cmpld
553; CHECK-PWR8: isel
554; CHECK-PWR8: blr
555}
556
557; select_cc lhs, rhs, 0, (select_cc lhs, rhs, -1, 1, setlt), seteq
558define i64 @setb21(i64 %a, i64 %b) {
559  %t1 = icmp eq i64 %a, %b
560  %t2 = icmp slt i64 %a, %b
561  %t3 = select i1 %t2, i64 -1, i64 1
562  %t4 = select i1 %t1, i64 0, i64 %t3
563  ret i64 %t4
564; CHECK-LABEL: setb21:
565; CHECK-NOT: li
566; CHECK-NOT: cmpld
567; CHECK-NOT: isel
568; CHECK: cmpd {{c?r?(0, )?}}r3, r4
569; CHECK-NEXT: setb r3, cr0
570; CHECK-NOT: isel
571; CHECK: blr
572; CHECK-PWR8-LABEL: setb21
573; CHECK-PWR8: cmpd
574; CHECK-PWR8: isel
575; CHECK-PWR8: cmpld
576; CHECK-PWR8: isel
577; CHECK-PWR8: blr
578}
579
580; select_cc lhs, rhs, 0, (select_cc rhs, lhs, -1, 1, setlt), seteq
581define i64 @setb22(i64 %a, i64 %b) {
582  %t1 = icmp eq i64 %b, %a
583  %t2 = icmp slt i64 %a, %b
584  %t3 = select i1 %t2, i64 -1, i64 1
585  %t4 = select i1 %t1, i64 0, i64 %t3
586  ret i64 %t4
587; CHECK-LABEL: setb22:
588; CHECK-NOT: li
589; CHECK-NOT: cmpld
590; CHECK-NOT: isel
591; CHECK: cmpd {{c?r?(0, )?}}r3, r4
592; CHECK-NEXT: setb r3, cr0
593; CHECK-NOT: isel
594; CHECK: blr
595; CHECK-PWR8-LABEL: setb22
596; CHECK-PWR8: cmpd
597; CHECK-PWR8: isel
598; CHECK-PWR8: cmpld
599; CHECK-PWR8: isel
600; CHECK-PWR8: blr
601}
602
603; select_cc lhs, rhs, 0, (select_cc rhs, lhs, -1, 1, setgt), seteq
604define i64 @setb23(i64 %a, i64 %b) {
605  %t1 = icmp eq i64 %a, %b
606  %t2 = icmp sgt i64 %b, %a
607  %t3 = select i1 %t2, i64 -1, i64 1
608  %t4 = select i1 %t1, i64 0, i64 %t3
609  ret i64 %t4
610; CHECK-LABEL: setb23:
611; CHECK-NOT: li
612; CHECK-NOT: cmpld
613; CHECK-NOT: isel
614; CHECK: cmpd {{c?r?(0, )?}}r3, r4
615; CHECK-NEXT: setb r3, cr0
616; CHECK-NOT: isel
617; CHECK: blr
618; CHECK-PWR8-LABEL: setb23
619; CHECK-PWR8: cmpd
620; CHECK-PWR8: isel
621; CHECK-PWR8: cmpld
622; CHECK-PWR8: isel
623; CHECK-PWR8: blr
624}
625
626; select_cc lhs, rhs, 0, (select_cc lhs, rhs, -1, 1, setgt), seteq
627define i64 @setb24(i64 %a, i64 %b) {
628  %t1 = icmp eq i64 %b, %a
629  %t2 = icmp sgt i64 %b, %a
630  %t3 = select i1 %t2, i64 -1, i64 1
631  %t4 = select i1 %t1, i64 0, i64 %t3
632  ret i64 %t4
633; CHECK-LABEL: setb24:
634; CHECK-NOT: li
635; CHECK-NOT: cmpld
636; CHECK-NOT: isel
637; CHECK: cmpd {{c?r?(0, )?}}r3, r4
638; CHECK-NEXT: setb r3, cr0
639; CHECK-NOT: isel
640; CHECK: blr
641; CHECK-PWR8-LABEL: setb24
642; CHECK-PWR8: cmpd
643; CHECK-PWR8: isel
644; CHECK-PWR8: cmpld
645; CHECK-PWR8: isel
646; CHECK-PWR8: blr
647}
648; end all patterns testing for i64
649
650; Test with swapping the input parameters
651
652; select_cc lhs, rhs, -1, (zext (setcc lhs, rhs, setne)), setlt
653define i64 @setb25(i64 %a, i64 %b) {
654  %t1 = icmp slt i64 %b, %a
655  %t2 = icmp ne i64 %b, %a
656  %t3 = zext i1 %t2 to i64
657  %t4 = select i1 %t1, i64 -1, i64 %t3
658  ret i64 %t4
659; CHECK-LABEL: setb25:
660; CHECK-NOT: xor
661; CHECK-NOT: li
662; CHECK-NOT: cmpd
663; CHECK: cmpd {{c?r?(0, )?}}r4, r3
664; CHECK-NEXT: setb r3, cr0
665; CHECK-NOT: addic
666; CHECK-NOT: subfe
667; CHECK-NOT: isel
668; CHECK: blr
669; CHECK-PWR8-LABEL: setb25
670; CHECK-PWR8-DAG: cmpd
671; CHECK-PWR8-DAG: addic
672; CHECK-PWR8-DAG: subfe
673; CHECK-PWR8: isel
674; CHECK-PWR8: blr
675}
676
677; select_cc lhs, rhs, -1, (zext (setcc rhs, lhs, setne)), setgt
678define i64 @setb26(i64 %a, i64 %b) {
679  %t1 = icmp sgt i64 %a, %b
680  %t2 = icmp ne i64 %b, %a
681  %t3 = zext i1 %t2 to i64
682  %t4 = select i1 %t1, i64 -1, i64 %t3
683  ret i64 %t4
684; CHECK-LABEL: setb26:
685; CHECK-NOT: xor
686; CHECK-NOT: li
687; CHECK: cmpd {{c?r?(0, )?}}r4, r3
688; CHECK-NEXT: setb r3, cr0
689; CHECK-NOT: addic
690; CHECK-NOT: subfe
691; CHECK-NOT: isel
692; CHECK: blr
693; CHECK-PWR8-LABEL: setb26
694; CHECK-PWR8-DAG: cmpd
695; CHECK-PWR8-DAG: addic
696; CHECK-PWR8-DAG: subfe
697; CHECK-PWR8: isel
698; CHECK-PWR8: blr
699}
700
701; Test with different scalar integer type for selected value
702; i32/i16/i8 rather than i64 above
703
704; select_cc lhs, rhs, -1, (zext (setcc rhs, lhs, setne)), setlt
705define i64 @setb27(i64 %a, i64 %b) {
706  %t1 = icmp slt i64 %a, %b
707  %t2 = icmp ne i64 %b, %a
708  %t3 = zext i1 %t2 to i32
709  %t4 = select i1 %t1, i32 -1, i32 %t3
710  %t5 = sext i32 %t4 to i64
711  ret i64 %t5
712; CHECK-LABEL: setb27:
713; CHECK-NOT: xor
714; CHECK-NOT: li
715; CHECK: cmpd {{c?r?(0, )?}}r3, r4
716; CHECK-NEXT: setb r3, cr0
717; CHECK-NOT: addic
718; CHECK-NOT: subfe
719; CHECK-NOT: isel
720; CHECK: extsw
721; CHECK: blr
722; CHECK-PWR8-LABEL: setb27
723; CHECK-PWR8-DAG: cmpd
724; CHECK-PWR8-DAG: addic
725; CHECK-PWR8-DAG: subfe
726; CHECK-PWR8: isel
727; CHECK-PWR8: extsw
728; CHECK-PWR8: blr
729}
730
731; select_cc lhs, rhs, -1, (zext (setcc lhs, rhs, setne)), setgt
732define i64 @setb28(i64 %a, i64 %b) {
733  %t1 = icmp sgt i64 %b, %a
734  %t2 = icmp ne i64 %b, %a
735  %t3 = zext i1 %t2 to i16
736  %t4 = select i1 %t1, i16 -1, i16 %t3
737  %t5 = sext i16 %t4 to i64
738  ret i64 %t5
739; CHECK-LABEL: setb28:
740; CHECK-NOT: xor
741; CHECK-NOT: li
742; CHECK: cmpd {{c?r?(0, )?}}r3, r4
743; CHECK-NEXT: setb r3, cr0
744; CHECK-NOT: addic
745; CHECK-NOT: subfe
746; CHECK-NOT: isel
747; CHECK: extsw
748; CHECK: blr
749; CHECK-PWR8-LABEL: setb28
750; CHECK-PWR8-DAG: cmpd
751; CHECK-PWR8-DAG: addic
752; CHECK-PWR8-DAG: subfe
753; CHECK-PWR8: isel
754; CHECK-PWR8: extsw
755; CHECK-PWR8: blr
756}
757
758; select_cc lhs, rhs, -1, (zext (setcc lhs, rhs, setgt)), setlt
759define i64 @setb29(i64 %a, i64 %b) {
760  %t1 = icmp slt i64 %a, %b
761  %t2 = icmp sgt i64 %a, %b
762  %t3 = zext i1 %t2 to i8
763  %t4 = select i1 %t1, i8 -1, i8 %t3
764  %t5 = zext i8 %t4 to i64
765  ret i64 %t5
766; CHECK-LABEL: setb29:
767; CHECK-NOT: sradi
768; CHECK-NOT: rldicl
769; CHECK-NOT: li
770; CHECK: cmpd {{c?r?(0, )?}}r3, r4
771; CHECK-NEXT: setb r3, cr0
772; CHECK-NOT: subc
773; CHECK-NOT: adde
774; CHECK-NOT: xori
775; CHECK-NOT: isel
776; CHECK: blr
777; CHECK-PWR8-LABEL: setb29
778; CHECK-PWR8-DAG: cmpd
779; CHECK-PWR8-DAG: subc
780; CHECK-PWR8-DAG: adde
781; CHECK-PWR8: isel
782; CHECK-PWR8: blr
783}
784
785; Testings to cover different comparison opcodes
786; Test with integer type i32/i16/i8 for input parameter
787
788; select_cc lhs, rhs, -1, (zext (setcc lhs, rhs, setne)), setlt
789define i64 @setbsw1(i32 %a, i32 %b) {
790  %t1 = icmp slt i32 %a, %b
791  %t2 = icmp ne i32 %a, %b
792  %t3 = zext i1 %t2 to i64
793  %t4 = select i1 %t1, i64 -1, i64 %t3
794  ret i64 %t4
795; CHECK-LABEL: setbsw1:
796; CHECK-NOT: xor
797; CHECK-NOT: li
798; CHECK: cmpw {{c?r?(0, )?}}r3, r4
799; CHECK-NEXT: setb r3, cr0
800; CHECK-NOT: cntlzw
801; CHECK-NOT: srwi
802; CHECK-NOT: xori
803; CHECK-NOT: isel
804; CHECK: blr
805; CHECK-PWR8-LABEL: setbsw1
806; CHECK-PWR8-DAG: cntlzw
807; CHECK-PWR8-DAG: cmpw
808; CHECK-PWR8-DAG: srwi
809; CHECK-PWR8-DAG: xori
810; CHECK-PWR8: isel
811; CHECK-PWR8: blr
812}
813
814; select_cc lhs, rhs, -1, (zext (setcc rhs, lhs, setne)), setgt
815define i64 @setbsw2(i32 %a, i32 %b) {
816  %t1 = icmp sgt i32 %b, %a
817  %t2 = icmp ne i32 %a, %b
818  %t3 = zext i1 %t2 to i64
819  %t4 = select i1 %t1, i64 -1, i64 %t3
820  ret i64 %t4
821; CHECK-LABEL: setbsw2:
822; CHECK-NOT: xor
823; CHECK-NOT: li
824; CHECK: cmpw {{c?r?(0, )?}}r3, r4
825; CHECK-NEXT: setb r3, cr0
826; CHECK-NOT: cntlzw
827; CHECK-NOT: srwi
828; CHECK-NOT: xori
829; CHECK-NOT: isel
830; CHECK: blr
831; CHECK-PWR8-LABEL: setbsw2
832; CHECK-PWR8-DAG: cntlzw
833; CHECK-PWR8-DAG: cmpw
834; CHECK-PWR8-DAG: srwi
835; CHECK-PWR8-DAG: xori
836; CHECK-PWR8: isel
837; CHECK-PWR8: blr
838}
839
840; select_cc lhs, rhs, 0, (select_cc rhs, lhs, -1, 1, setgt), seteq
841define i64 @setbsw3(i32 %a, i32 %b) {
842  %t1 = icmp eq i32 %a, %b
843  %t2 = icmp sgt i32 %b, %a
844  %t3 = select i1 %t2, i64 -1, i64 1
845  %t4 = select i1 %t1, i64 0, i64 %t3
846  ret i64 %t4
847; CHECK-LABEL: setbsw3:
848; CHECK-NOT: li
849; CHECK: cmpw {{c?r?(0, )?}}r3, r4
850; CHECK-NEXT: setb r3, cr0
851; CHECK-NOT: isel
852; CHECK-NOT: cmplw
853; CHECK-NOT: isel
854; CHECK: blr
855; CHECK-PWR8-LABEL: setbsw3
856; CHECK-PWR8: cmpw
857; CHECK-PWR8: isel
858; CHECK-PWR8: cmplw
859; CHECK-PWR8: isel
860; CHECK-PWR8: blr
861}
862
863; select_cc lhs, rhs, -1, (zext (setcc rhs, lhs, setne)), setlt
864define i64 @setbsh1(i16 signext %a, i16 signext %b) {
865  %t1 = icmp slt i16 %a, %b
866  %t2 = icmp ne i16 %b, %a
867  %t3 = zext i1 %t2 to i64
868  %t4 = select i1 %t1, i64 -1, i64 %t3
869  ret i64 %t4
870; CHECK-LABEL: setbsh1:
871; CHECK-NOT: xor
872; CHECK-NOT: li
873; CHECK: cmpw {{c?r?(0, )?}}r3, r4
874; CHECK-NEXT: setb r3, cr0
875; CHECK-NOT: cntlzw
876; CHECK-NOT: srwi
877; CHECK-NOT: xori
878; CHECK-NOT: isel
879; CHECK: blr
880; CHECK-PWR8-LABEL: setbsh1
881; CHECK-PWR8-DAG: cntlzw
882; CHECK-PWR8-DAG: cmpw
883; CHECK-PWR8-DAG: srwi
884; CHECK-PWR8-DAG: xori
885; CHECK-PWR8: isel
886; CHECK-PWR8: blr
887}
888
889; select_cc lhs, rhs, -1, (zext (setcc lhs, rhs, setne)), setgt
890define i64 @setbsh2(i16 signext %a, i16 signext %b) {
891  %t1 = icmp sgt i16 %b, %a
892  %t2 = icmp ne i16 %b, %a
893  %t3 = zext i1 %t2 to i64
894  %t4 = select i1 %t1, i64 -1, i64 %t3
895  ret i64 %t4
896; CHECK-LABEL: setbsh2:
897; CHECK-NOT: xor
898; CHECK-NOT: li
899; CHECK: cmpw {{c?r?(0, )?}}r3, r4
900; CHECK-NEXT: setb r3, cr0
901; CHECK-NOT: cntlzw
902; CHECK-NOT: srwi
903; CHECK-NOT: xori
904; CHECK-NOT: isel
905; CHECK: blr
906; CHECK-PWR8-LABEL: setbsh2
907; CHECK-PWR8-DAG: cmpw
908; CHECK-PWR8-DAG: cntlzw
909; CHECK-PWR8-DAG: srwi
910; CHECK-PWR8-DAG: xori
911; CHECK-PWR8: isel
912; CHECK-PWR8: blr
913}
914
915; select_cc lhs, rhs, -1, (zext (setcc lhs, rhs, setgt)), setlt
916define i64 @setbsc1(i8 %a, i8 %b) {
917  %t1 = icmp slt i8 %a, %b
918  %t2 = icmp sgt i8 %a, %b
919  %t3 = zext i1 %t2 to i64
920  %t4 = select i1 %t1, i64 -1, i64 %t3
921  ret i64 %t4
922; CHECK-LABEL: setbsc1:
923; CHECK-DAG: extsb [[RA:r[0-9]+]], r3
924; CHECK-DAG: extsb [[RB:r[0-9]+]], r4
925; CHECK-NOT: li
926; CHECK-NOT: sub
927; CHECK: cmpw {{c?r?(0, )?}}[[RA]], [[RB]]
928; CHECK-NEXT: setb r3, cr0
929; CHECK-NOT: rldicl
930; CHECK-NOT: isel
931; CHECK: blr
932; CHECK-PWR8-LABEL: setbsc1
933; CHECK-PWR8-DAG: extsb
934; CHECK-PWR8-DAG: extsb
935; CHECK-PWR8-DAG: extsw
936; CHECK-PWR8-DAG: extsw
937; CHECK-PWR8-DAG: cmpw
938; CHECK-PWR8-DAG: rldicl
939; CHECK-PWR8: isel
940; CHECK-PWR8: blr
941}
942
943; select_cc lhs, rhs, -1, (zext (setcc rhs, lhs, setgt)), setgt
944define i64 @setbsc2(i8 %a, i8 %b) {
945  %t1 = icmp sgt i8 %b, %a
946  %t2 = icmp sgt i8 %a, %b
947  %t3 = zext i1 %t2 to i64
948  %t4 = select i1 %t1, i64 -1, i64 %t3
949  ret i64 %t4
950; CHECK-LABEL: setbsc2:
951; CHECK-DAG: extsb [[RA:r[0-9]+]], r3
952; CHECK-DAG: extsb [[RB:r[0-9]+]], r4
953; CHECK-NOT: li
954; CHECK-NOT: sub
955; CHECK: cmpw {{c?r?(0, )?}}[[RA]], [[RB]]
956; CHECK-NEXT: setb r3, cr0
957; CHECK-NOT: rldicl
958; CHECK-NOT: isel
959; CHECK: blr
960; CHECK-PWR8-LABEL: setbsc2
961; CHECK-PWR8-DAG: extsb
962; CHECK-PWR8-DAG: extsb
963; CHECK-PWR8-DAG: extsw
964; CHECK-PWR8-DAG: extsw
965; CHECK-PWR8-DAG: cmpw
966; CHECK-PWR8-DAG: rldicl
967; CHECK-PWR8: isel
968; CHECK-PWR8: blr
969}
970
971; select_cc lhs, rhs, -1, (zext (setcc rhs, lhs, setlt)), setlt
972define i64 @setbsc3(i4 %a, i4 %b) {
973  %t1 = icmp slt i4 %a, %b
974  %t2 = icmp slt i4 %b, %a
975  %t3 = zext i1 %t2 to i64
976  %t4 = select i1 %t1, i64 -1, i64 %t3
977  ret i64 %t4
978; CHECK-LABEL: setbsc3:
979; CHECK-DAG: slwi [[RA:r[0-9]+]], r3, 28
980; CHECK-DAG: slwi [[RB:r[0-9]+]], r4, 28
981; CHECK-NOT: li
982; CHECK-DAG: srawi [[RA1:r[0-9]+]], [[RA]], 28
983; CHECK-DAG: srawi [[RB1:r[0-9]+]], [[RB]], 28
984; CHECK-NOT: sub
985; CHECK: cmpw {{c?r?(0, )?}}[[RA1]], [[RB1]]
986; CHECK-NEXT: setb r3, cr0
987; CHECK-NOT: rldicl
988; CHECK-NOT: isel
989; CHECK: blr
990; CHECK-PWR8-LABEL: setbsc3
991; CHECK-PWR8-DAG: slwi
992; CHECK-PWR8-DAG: slwi
993; CHECK-PWR8-DAG: srawi
994; CHECK-PWR8-DAG: srawi
995; CHECK-PWR8-DAG: extsw
996; CHECK-PWR8-DAG: extsw
997; CHECK-PWR8-DAG: cmpw
998; CHECK-PWR8-DAG: rldicl
999; CHECK-PWR8: isel
1000; CHECK-PWR8: blr
1001}
1002
1003; Test with unsigned integer type i64/i32/i16/i8 for input parameter
1004
1005; select_cc lhs, rhs, -1, (zext (setcc lhs, rhs, setult)), setugt
1006define i64 @setbud1(i64 %a, i64 %b) {
1007  %t1 = icmp ugt i64 %b, %a
1008  %t2 = icmp ult i64 %b, %a
1009  %t3 = zext i1 %t2 to i64
1010  %t4 = select i1 %t1, i64 -1, i64 %t3
1011  ret i64 %t4
1012; CHECK-LABEL: setbud1:
1013; CHECK-NOT: li
1014; CHECK: cmpld {{c?r?(0, )?}}r3, r4
1015; CHECK-NEXT: setb r3, cr0
1016; CHECK-NOT: subc
1017; CHECK-NOT: subfe
1018; CHECK-NOT: neg
1019; CHECK-NOT: isel
1020; CHECK: blr
1021; CHECK-PWR8-LABEL: setbud1
1022; CHECK-PWR8-DAG: subc
1023; CHECK-PWR8-DAG: subfe
1024; CHECK-PWR8-DAG: cmpld
1025; CHECK-PWR8-DAG: neg
1026; CHECK-PWR8: isel
1027; CHECK-PWR8: blr
1028}
1029
1030; select_cc lhs, rhs, 1, (sext (setcc lhs, rhs, setne)), setugt
1031define i64 @setbud2(i64 %a, i64 %b) {
1032  %t1 = icmp ugt i64 %a, %b
1033  %t2 = icmp ne i64 %a, %b
1034  %t3 = sext i1 %t2 to i64
1035  %t4 = select i1 %t1, i64 1, i64 %t3
1036  ret i64 %t4
1037; CHECK-LABEL: setbud2:
1038; CHECK-NOT: xor
1039; CHECK-NOT: li
1040; CHECK: cmpld {{c?r?(0, )?}}r3, r4
1041; CHECK-NEXT: setb r3, cr0
1042; CHECK-NOT: subfic
1043; CHECK-NOT: subfe
1044; CHECK-NOT: isel
1045; CHECK: blr
1046; CHECK-PWR8-LABEL: setbud2
1047; CHECK-PWR8-DAG: cmpld
1048; CHECK-PWR8-DAG: subfic
1049; CHECK-PWR8-DAG: subfe
1050; CHECK-PWR8: isel
1051; CHECK-PWR8: blr
1052}
1053
1054; select_cc lhs, rhs, 0, (select_cc lhs, rhs, -1, 1, setugt), seteq
1055define i64 @setbud3(i64 %a, i64 %b) {
1056  %t1 = icmp eq i64 %b, %a
1057  %t2 = icmp ugt i64 %b, %a
1058  %t3 = select i1 %t2, i64 -1, i64 1
1059  %t4 = select i1 %t1, i64 0, i64 %t3
1060  ret i64 %t4
1061; CHECK-LABEL: setbud3:
1062; CHECK-NOT: li
1063; CHECK: cmpld {{c?r?(0, )?}}r3, r4
1064; CHECK-NEXT: setb r3, cr0
1065; CHECK-NOT: li
1066; CHECK-NOT: isel
1067; CHECK: blr
1068; CHECK-PWR8-LABEL: setbud3
1069; CHECK-PWR8-DAG: cmpld
1070; CHECK-PWR8-DAG: li
1071; CHECK-PWR8-DAG: li
1072; CHECK-PWR8: isel
1073; CHECK-PWR8: isel
1074; CHECK-PWR8: blr
1075}
1076
1077; select_cc lhs, rhs, 1, (sext (setcc rhs, lhs, setne)), setult
1078define i64 @setbuw1(i32 %a, i32 %b) {
1079  %t1 = icmp ult i32 %b, %a
1080  %t2 = icmp ne i32 %a, %b
1081  %t3 = sext i1 %t2 to i64
1082  %t4 = select i1 %t1, i64 1, i64 %t3
1083  ret i64 %t4
1084; CHECK-LABEL: setbuw1:
1085; CHECK-NOT: xor
1086; CHECK-NOT: li
1087; CHECK: cmplw {{c?r?(0, )?}}r3, r4
1088; CHECK-NEXT: setb r3, cr0
1089; CHECK-NOT: cntlzw
1090; CHECK-NOT: srwi
1091; CHECK-NOT: xori
1092; CHECK-NOT: neg
1093; CHECK-NOT: isel
1094; CHECK: blr
1095; CHECK-PWR8-LABEL: setbuw1
1096; CHECK-PWR8-DAG: cntlzw
1097; CHECK-PWR8-DAG: cmplw
1098; CHECK-PWR8-DAG: srwi
1099; CHECK-PWR8-DAG: xori
1100; CHECK-PWR8-DAG: neg
1101; CHECK-PWR8: isel
1102; CHECK-PWR8: blr
1103}
1104
1105; select_cc lhs, rhs, 1, (sext (setcc rhs, lhs, setne)), setugt
1106define i64 @setbuw2(i32 %a, i32 %b) {
1107  %t1 = icmp ugt i32 %a, %b
1108  %t2 = icmp ne i32 %b, %a
1109  %t3 = sext i1 %t2 to i64
1110  %t4 = select i1 %t1, i64 1, i64 %t3
1111  ret i64 %t4
1112; CHECK-LABEL: setbuw2:
1113; CHECK-NOT: xor
1114; CHECK-NOT: li
1115; CHECK: cmplw {{c?r?(0, )?}}r3, r4
1116; CHECK-NEXT: setb r3, cr0
1117; CHECK-NOT: cntlzw
1118; CHECK-NOT: srwi
1119; CHECK-NOT: xori
1120; CHECK-NOT: neg
1121; CHECK-NOT: isel
1122; CHECK: blr
1123; CHECK-PWR8-LABEL: setbuw2
1124; CHECK-PWR8-DAG: cntlzw
1125; CHECK-PWR8-DAG: cmplw
1126; CHECK-PWR8-DAG: srwi
1127; CHECK-PWR8-DAG: xori
1128; CHECK-PWR8-DAG: neg
1129; CHECK-PWR8: isel
1130; CHECK-PWR8: blr
1131}
1132
1133; select_cc lhs, rhs, 1, (sext (setcc lhs, rhs, setne)), setult
1134define i64 @setbuh(i16 %a, i16 %b) {
1135  %t1 = icmp ult i16 %b, %a
1136  %t2 = icmp ne i16 %b, %a
1137  %t3 = sext i1 %t2 to i64
1138  %t4 = select i1 %t1, i64 1, i64 %t3
1139  ret i64 %t4
1140; CHECK-LABEL: setbuh:
1141; CHECK-DAG: clrlwi [[RA:r[0-9]+]], r3, 16
1142; CHECK-DAG: clrlwi [[RB:r[0-9]+]], r4, 16
1143; CHECK-NOT: li
1144; CHECK-NOT: xor
1145; CHECK: cmplw {{c?r?(0, )?}}[[RA]], [[RB]]
1146; CHECK-NEXT: setb r3, cr0
1147; CHECK-NOT: cntlzw
1148; CHECK-NOT: srwi
1149; CHECK-NOT: xori
1150; CHECK-NOT: neg
1151; CHECK-NOT: isel
1152; CHECK: blr
1153; CHECK-PWR8-LABEL: setbuh
1154; CHECK-PWR8: clrlwi
1155; CHECK-PWR8: clrlwi
1156; CHECK-PWR8-DAG: cmplw
1157; CHECK-PWR8-DAG: cntlzw
1158; CHECK-PWR8: srwi
1159; CHECK-PWR8: xori
1160; CHECK-PWR8: neg
1161; CHECK-PWR8: isel
1162; CHECK-PWR8: blr
1163}
1164
1165; select_cc lhs, rhs, 1, (sext (setcc lhs, rhs, setult)), setugt
1166define i64 @setbuc(i8 %a, i8 %b) {
1167  %t1 = icmp ugt i8 %a, %b
1168  %t2 = icmp ult i8 %a, %b
1169  %t3 = sext i1 %t2 to i64
1170  %t4 = select i1 %t1, i64 1, i64 %t3
1171  ret i64 %t4
1172; CHECK-LABEL: setbuc:
1173; CHECK-DAG: clrlwi [[RA:r[0-9]+]], r3, 24
1174; CHECK-DAG: clrlwi [[RB:r[0-9]+]], r4, 24
1175; CHECK-NOT: li
1176; CHECK-NOT: clrldi
1177; CHECK: cmplw {{c?r?(0, )?}}[[RA]], [[RB]]
1178; CHECK-NEXT: setb r3, cr0
1179; CHECK-NOT: sub
1180; CHECK-NOT: sradi
1181; CHECK-NOT: isel
1182; CHECK: blr
1183; CHECK-PWR8-LABEL: setbuc
1184; CHECK-PWR8: clrlwi
1185; CHECK-PWR8: clrlwi
1186; CHECK-PWR8-DAG: clrldi
1187; CHECK-PWR8-DAG: clrldi
1188; CHECK-PWR8-DAG: cmplw
1189; CHECK-PWR8: sradi
1190; CHECK-PWR8: isel
1191; CHECK-PWR8: blr
1192}
1193
1194; Test with float/double/float128 for input parameter
1195
1196; select_cc lhs, rhs, -1, (zext (setcc rhs, lhs, setlt)), setlt
1197define i64 @setbf1(float %a, float %b) {
1198  %t1 = fcmp nnan olt float %a, %b
1199  %t2 = fcmp nnan olt float %b, %a
1200  %t3 = zext i1 %t2 to i64
1201  %t4 = select i1 %t1, i64 -1, i64 %t3
1202  ret i64 %t4
1203; CHECK-LABEL: setbf1:
1204; CHECK-NOT: li
1205; CHECK: fcmpu cr0, f1, f2
1206; CHECK-NEXT: setb r3, cr0
1207; CHECK-NOT: isel
1208; CHECK-NOT: li
1209; CHECK: blr
1210; CHECK-PWR8-LABEL: setbf1
1211; CHECK-PWR8: isel
1212; CHECK-PWR8: isel
1213; CHECK-PWR8: blr
1214}
1215
1216; select_cc lhs, rhs, -1, (zext (setcc lhs, rhs, setlt)), setgt
1217define i64 @setbf2(float %a, float %b) {
1218  %t1 = fcmp nnan ogt float %b, %a
1219  %t2 = fcmp nnan olt float %b, %a
1220  %t3 = zext i1 %t2 to i64
1221  %t4 = select i1 %t1, i64 -1, i64 %t3
1222  ret i64 %t4
1223; CHECK-LABEL: setbf2:
1224; CHECK-NOT: li
1225; CHECK: fcmpu cr0, f1, f2
1226; CHECK-NEXT: setb r3, cr0
1227; CHECK-NOT: isel
1228; CHECK-NOT: li
1229; CHECK: blr
1230; CHECK-PWR8-LABEL: setbf2
1231; CHECK-PWR8: isel
1232; CHECK-PWR8: isel
1233; CHECK-PWR8: blr
1234}
1235
1236; select_cc lhs, rhs, 0, (select_cc lhs, rhs, -1, 1, setgt), seteq
1237define i64 @setbdf1(double %a, double %b) {
1238  %t1 = fcmp nnan oeq double %b, %a
1239  %t2 = fcmp nnan ogt double %b, %a
1240  %t3 = select i1 %t2, i64 -1, i64 1
1241  %t4 = select i1 %t1, i64 0, i64 %t3
1242  ret i64 %t4
1243; CHECK-LABEL: setbdf1:
1244; CHECK: xscmpudp cr0, f1, f2
1245; CHECK-NEXT: setb r3, cr0
1246; CHECK-NOT: li
1247; CHECK-NOT: isel
1248; CHECK: blr
1249; CHECK-PWR8-LABEL: setbdf1
1250; CHECK-PWR8: isel
1251; CHECK-PWR8: isel
1252; CHECK-PWR8: blr
1253}
1254
1255; select_cc lhs, rhs, 1, (sext (setcc lhs, rhs, setgt)), setlt
1256define i64 @setbdf2(double %a, double %b) {
1257  %t1 = fcmp nnan olt double %b, %a
1258  %t2 = fcmp nnan ogt double %b, %a
1259  %t3 = sext i1 %t2 to i64
1260  %t4 = select i1 %t1, i64 1, i64 %t3
1261  ret i64 %t4
1262; CHECK-LABEL: setbdf2:
1263; CHECK-NOT: fcmpu
1264; CHECK-NOT: li
1265; CHECK: xscmpudp cr0, f1, f2
1266; CHECK-NEXT: setb r3, cr0
1267; CHECK-NOT: li
1268; CHECK-NOT: isel
1269; CHECK: blr
1270; CHECK-PWR8-LABEL: setbdf2
1271; CHECK-PWR8: isel
1272; CHECK-PWR8: isel
1273; CHECK-PWR8: blr
1274}
1275
1276define i64 @setbf128(fp128 %a, fp128 %b) {
1277  %t1 = fcmp nnan ogt fp128 %a, %b
1278  %t2 = fcmp nnan olt fp128 %a, %b
1279  %t3 = sext i1 %t2 to i64
1280  %t4 = select i1 %t1, i64 1, i64 %t3
1281  ret i64 %t4
1282; CHECK-LABEL: setbf128:
1283; CHECK-NOT: li
1284; CHECK: xscmpuqp cr0, v2, v3
1285; CHECK-NEXT: setb r3, cr0
1286; CHECK-NOT: isel
1287; CHECK-NOT: li
1288; CHECK: blr
1289; CHECK-PWR8-LABEL: setbf128
1290; CHECK-PWR8: isel
1291; CHECK-PWR8: blr
1292}
1293
1294; Some cases we can't leverage setb
1295
1296define i64 @setbn1(i64 %a, i64 %b) {
1297  %t1 = icmp slt i64 %a, %b
1298  %t2 = icmp eq i64 %a, %b
1299  %t3 = zext i1 %t2 to i64
1300  %t4 = select i1 %t1, i64 -1, i64 %t3
1301  ret i64 %t4
1302; CHECK-LABEL: setbn1:
1303; CHECK-NOT: {{\<setb\>}}
1304; CHECK: isel
1305; CHECK: blr
1306}
1307
1308define i64 @setbn2(double %a, double %b) {
1309  %t1 = fcmp olt double %a, %b
1310  %t2 = fcmp one double %a, %b
1311  %t3 = zext i1 %t2 to i64
1312  %t4 = select i1 %t1, i64 -1, i64 %t3
1313  ret i64 %t4
1314; CHECK-LABEL: setbn2:
1315; CHECK-NOT: {{\<setb\>}}
1316; CHECK: isel
1317; CHECK: blr
1318}
1319
1320define i64 @setbn3(float %a, float %b) {
1321  %t1 = fcmp ult float %a, %b
1322  %t2 = fcmp une float %a, %b
1323  %t3 = zext i1 %t2 to i64
1324  %t4 = select i1 %t1, i64 -1, i64 %t3
1325  ret i64 %t4
1326; CHECK-LABEL: setbn3:
1327; CHECK-NOT: {{\<setb\>}}
1328; CHECK: isel
1329; CHECK: blr
1330}
1331
1332; Verify this case doesn't crash
1333define void @setbn4(i128 %0, i32* %sel.out) {
1334entry:
1335; CHECK-LABEL: setbn4:
1336; CHECK-NOT: {{\<setb\>}}
1337; CHECK: isel
1338; CHECK: blr
1339  %c1 = icmp ult i128 %0, 5192296858534827628530496329220096
1340  %c2 = icmp ugt i128 %0, 5192296858534827628530496329220096
1341  %ext = zext i1 %c2 to i32
1342  %sel = select i1 %c1, i32 -1, i32 %ext
1343  store i32 %sel, i32* %sel.out, align 4
1344  ret void
1345}
1346