1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ 3; RUN: -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \ 4; RUN: FileCheck %s --check-prefix=CHECK-P8 5; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ 6; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \ 7; RUN: FileCheck %s --check-prefix=CHECK-P9 8; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \ 9; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \ 10; RUN: FileCheck %s --check-prefix=CHECK-BE 11 12define <2 x double> @test2elt(i32 %a.coerce) local_unnamed_addr #0 { 13; CHECK-P8-LABEL: test2elt: 14; CHECK-P8: # %bb.0: # %entry 15; CHECK-P8-NEXT: addis r4, r2, .LCPI0_0@toc@ha 16; CHECK-P8-NEXT: mtvsrwz v2, r3 17; CHECK-P8-NEXT: addi r4, r4, .LCPI0_0@toc@l 18; CHECK-P8-NEXT: xxlxor v4, v4, v4 19; CHECK-P8-NEXT: lvx v3, 0, r4 20; CHECK-P8-NEXT: vperm v2, v4, v2, v3 21; CHECK-P8-NEXT: xvcvuxddp v2, v2 22; CHECK-P8-NEXT: blr 23; 24; CHECK-P9-LABEL: test2elt: 25; CHECK-P9: # %bb.0: # %entry 26; CHECK-P9-NEXT: mtvsrws v2, r3 27; CHECK-P9-NEXT: addis r3, r2, .LCPI0_0@toc@ha 28; CHECK-P9-NEXT: xxlxor v4, v4, v4 29; CHECK-P9-NEXT: addi r3, r3, .LCPI0_0@toc@l 30; CHECK-P9-NEXT: lxvx v3, 0, r3 31; CHECK-P9-NEXT: vperm v2, v4, v2, v3 32; CHECK-P9-NEXT: xvcvuxddp v2, v2 33; CHECK-P9-NEXT: blr 34; 35; CHECK-BE-LABEL: test2elt: 36; CHECK-BE: # %bb.0: # %entry 37; CHECK-BE-NEXT: mtvsrws v2, r3 38; CHECK-BE-NEXT: addis r3, r2, .LCPI0_0@toc@ha 39; CHECK-BE-NEXT: xxlxor v4, v4, v4 40; CHECK-BE-NEXT: addi r3, r3, .LCPI0_0@toc@l 41; CHECK-BE-NEXT: lxvx v3, 0, r3 42; CHECK-BE-NEXT: vperm v2, v2, v4, v3 43; CHECK-BE-NEXT: xvcvuxddp v2, v2 44; CHECK-BE-NEXT: blr 45entry: 46 %0 = bitcast i32 %a.coerce to <2 x i16> 47 %1 = uitofp <2 x i16> %0 to <2 x double> 48 ret <2 x double> %1 49} 50 51define void @test4elt(<4 x double>* noalias nocapture sret(<4 x double>) %agg.result, i64 %a.coerce) local_unnamed_addr #1 { 52; CHECK-P8-LABEL: test4elt: 53; CHECK-P8: # %bb.0: # %entry 54; CHECK-P8-NEXT: addis r5, r2, .LCPI1_0@toc@ha 55; CHECK-P8-NEXT: addis r6, r2, .LCPI1_1@toc@ha 56; CHECK-P8-NEXT: mtvsrd v2, r4 57; CHECK-P8-NEXT: addi r5, r5, .LCPI1_0@toc@l 58; CHECK-P8-NEXT: addi r4, r6, .LCPI1_1@toc@l 59; CHECK-P8-NEXT: xxlxor v4, v4, v4 60; CHECK-P8-NEXT: lvx v3, 0, r5 61; CHECK-P8-NEXT: lvx v5, 0, r4 62; CHECK-P8-NEXT: li r4, 16 63; CHECK-P8-NEXT: vperm v3, v4, v2, v3 64; CHECK-P8-NEXT: vperm v2, v4, v2, v5 65; CHECK-P8-NEXT: xvcvuxddp vs0, v3 66; CHECK-P8-NEXT: xvcvuxddp vs1, v2 67; CHECK-P8-NEXT: xxswapd vs0, vs0 68; CHECK-P8-NEXT: xxswapd vs1, vs1 69; CHECK-P8-NEXT: stxvd2x vs1, r3, r4 70; CHECK-P8-NEXT: stxvd2x vs0, 0, r3 71; CHECK-P8-NEXT: blr 72; 73; CHECK-P9-LABEL: test4elt: 74; CHECK-P9: # %bb.0: # %entry 75; CHECK-P9-NEXT: mtvsrd v2, r4 76; CHECK-P9-NEXT: addis r4, r2, .LCPI1_0@toc@ha 77; CHECK-P9-NEXT: xxlxor v4, v4, v4 78; CHECK-P9-NEXT: addi r4, r4, .LCPI1_0@toc@l 79; CHECK-P9-NEXT: lxvx v3, 0, r4 80; CHECK-P9-NEXT: addis r4, r2, .LCPI1_1@toc@ha 81; CHECK-P9-NEXT: addi r4, r4, .LCPI1_1@toc@l 82; CHECK-P9-NEXT: vperm v3, v4, v2, v3 83; CHECK-P9-NEXT: xvcvuxddp vs0, v3 84; CHECK-P9-NEXT: lxvx v3, 0, r4 85; CHECK-P9-NEXT: vperm v2, v4, v2, v3 86; CHECK-P9-NEXT: stxv vs0, 0(r3) 87; CHECK-P9-NEXT: xvcvuxddp vs1, v2 88; CHECK-P9-NEXT: stxv vs1, 16(r3) 89; CHECK-P9-NEXT: blr 90; 91; CHECK-BE-LABEL: test4elt: 92; CHECK-BE: # %bb.0: # %entry 93; CHECK-BE-NEXT: mtvsrd v2, r4 94; CHECK-BE-NEXT: addis r4, r2, .LCPI1_0@toc@ha 95; CHECK-BE-NEXT: xxlxor v4, v4, v4 96; CHECK-BE-NEXT: addi r4, r4, .LCPI1_0@toc@l 97; CHECK-BE-NEXT: lxvx v3, 0, r4 98; CHECK-BE-NEXT: addis r4, r2, .LCPI1_1@toc@ha 99; CHECK-BE-NEXT: addi r4, r4, .LCPI1_1@toc@l 100; CHECK-BE-NEXT: vperm v3, v2, v4, v3 101; CHECK-BE-NEXT: xvcvuxddp vs0, v3 102; CHECK-BE-NEXT: lxvx v3, 0, r4 103; CHECK-BE-NEXT: vperm v2, v4, v2, v3 104; CHECK-BE-NEXT: stxv vs0, 0(r3) 105; CHECK-BE-NEXT: xvcvuxddp vs1, v2 106; CHECK-BE-NEXT: stxv vs1, 16(r3) 107; CHECK-BE-NEXT: blr 108entry: 109 %0 = bitcast i64 %a.coerce to <4 x i16> 110 %1 = uitofp <4 x i16> %0 to <4 x double> 111 store <4 x double> %1, <4 x double>* %agg.result, align 32 112 ret void 113} 114 115define void @test8elt(<8 x double>* noalias nocapture sret(<8 x double>) %agg.result, <8 x i16> %a) local_unnamed_addr #2 { 116; CHECK-P8-LABEL: test8elt: 117; CHECK-P8: # %bb.0: # %entry 118; CHECK-P8-NEXT: addis r4, r2, .LCPI2_0@toc@ha 119; CHECK-P8-NEXT: addis r5, r2, .LCPI2_2@toc@ha 120; CHECK-P8-NEXT: xxlxor v4, v4, v4 121; CHECK-P8-NEXT: addi r4, r4, .LCPI2_0@toc@l 122; CHECK-P8-NEXT: addi r5, r5, .LCPI2_2@toc@l 123; CHECK-P8-NEXT: lvx v3, 0, r4 124; CHECK-P8-NEXT: addis r4, r2, .LCPI2_3@toc@ha 125; CHECK-P8-NEXT: lvx v5, 0, r5 126; CHECK-P8-NEXT: addis r5, r2, .LCPI2_1@toc@ha 127; CHECK-P8-NEXT: addi r4, r4, .LCPI2_3@toc@l 128; CHECK-P8-NEXT: addi r5, r5, .LCPI2_1@toc@l 129; CHECK-P8-NEXT: lvx v0, 0, r4 130; CHECK-P8-NEXT: lvx v1, 0, r5 131; CHECK-P8-NEXT: li r4, 48 132; CHECK-P8-NEXT: li r5, 32 133; CHECK-P8-NEXT: vperm v3, v4, v2, v3 134; CHECK-P8-NEXT: vperm v5, v4, v2, v5 135; CHECK-P8-NEXT: vperm v0, v4, v2, v0 136; CHECK-P8-NEXT: vperm v2, v4, v2, v1 137; CHECK-P8-NEXT: xvcvuxddp vs0, v3 138; CHECK-P8-NEXT: xvcvuxddp vs1, v5 139; CHECK-P8-NEXT: xvcvuxddp vs2, v0 140; CHECK-P8-NEXT: xvcvuxddp vs3, v2 141; CHECK-P8-NEXT: xxswapd vs0, vs0 142; CHECK-P8-NEXT: xxswapd vs1, vs1 143; CHECK-P8-NEXT: xxswapd vs2, vs2 144; CHECK-P8-NEXT: xxswapd vs3, vs3 145; CHECK-P8-NEXT: stxvd2x vs2, r3, r4 146; CHECK-P8-NEXT: li r4, 16 147; CHECK-P8-NEXT: stxvd2x vs1, r3, r5 148; CHECK-P8-NEXT: stxvd2x vs3, r3, r4 149; CHECK-P8-NEXT: stxvd2x vs0, 0, r3 150; CHECK-P8-NEXT: blr 151; 152; CHECK-P9-LABEL: test8elt: 153; CHECK-P9: # %bb.0: # %entry 154; CHECK-P9-NEXT: addis r4, r2, .LCPI2_0@toc@ha 155; CHECK-P9-NEXT: xxlxor v4, v4, v4 156; CHECK-P9-NEXT: addi r4, r4, .LCPI2_0@toc@l 157; CHECK-P9-NEXT: lxvx v3, 0, r4 158; CHECK-P9-NEXT: addis r4, r2, .LCPI2_1@toc@ha 159; CHECK-P9-NEXT: addi r4, r4, .LCPI2_1@toc@l 160; CHECK-P9-NEXT: vperm v3, v4, v2, v3 161; CHECK-P9-NEXT: xvcvuxddp vs0, v3 162; CHECK-P9-NEXT: lxvx v3, 0, r4 163; CHECK-P9-NEXT: addis r4, r2, .LCPI2_2@toc@ha 164; CHECK-P9-NEXT: addi r4, r4, .LCPI2_2@toc@l 165; CHECK-P9-NEXT: vperm v3, v4, v2, v3 166; CHECK-P9-NEXT: stxv vs0, 0(r3) 167; CHECK-P9-NEXT: xvcvuxddp vs1, v3 168; CHECK-P9-NEXT: lxvx v3, 0, r4 169; CHECK-P9-NEXT: addis r4, r2, .LCPI2_3@toc@ha 170; CHECK-P9-NEXT: addi r4, r4, .LCPI2_3@toc@l 171; CHECK-P9-NEXT: vperm v3, v4, v2, v3 172; CHECK-P9-NEXT: stxv vs1, 16(r3) 173; CHECK-P9-NEXT: xvcvuxddp vs2, v3 174; CHECK-P9-NEXT: lxvx v3, 0, r4 175; CHECK-P9-NEXT: vperm v2, v4, v2, v3 176; CHECK-P9-NEXT: stxv vs2, 32(r3) 177; CHECK-P9-NEXT: xvcvuxddp vs3, v2 178; CHECK-P9-NEXT: stxv vs3, 48(r3) 179; CHECK-P9-NEXT: blr 180; 181; CHECK-BE-LABEL: test8elt: 182; CHECK-BE: # %bb.0: # %entry 183; CHECK-BE-NEXT: addis r4, r2, .LCPI2_0@toc@ha 184; CHECK-BE-NEXT: xxlxor v4, v4, v4 185; CHECK-BE-NEXT: addi r4, r4, .LCPI2_0@toc@l 186; CHECK-BE-NEXT: lxvx v3, 0, r4 187; CHECK-BE-NEXT: addis r4, r2, .LCPI2_1@toc@ha 188; CHECK-BE-NEXT: addi r4, r4, .LCPI2_1@toc@l 189; CHECK-BE-NEXT: vperm v3, v2, v4, v3 190; CHECK-BE-NEXT: xvcvuxddp vs0, v3 191; CHECK-BE-NEXT: lxvx v3, 0, r4 192; CHECK-BE-NEXT: addis r4, r2, .LCPI2_2@toc@ha 193; CHECK-BE-NEXT: addi r4, r4, .LCPI2_2@toc@l 194; CHECK-BE-NEXT: vperm v3, v4, v2, v3 195; CHECK-BE-NEXT: stxv vs0, 0(r3) 196; CHECK-BE-NEXT: xvcvuxddp vs1, v3 197; CHECK-BE-NEXT: lxvx v3, 0, r4 198; CHECK-BE-NEXT: addis r4, r2, .LCPI2_3@toc@ha 199; CHECK-BE-NEXT: addi r4, r4, .LCPI2_3@toc@l 200; CHECK-BE-NEXT: vperm v3, v4, v2, v3 201; CHECK-BE-NEXT: stxv vs1, 16(r3) 202; CHECK-BE-NEXT: xvcvuxddp vs2, v3 203; CHECK-BE-NEXT: lxvx v3, 0, r4 204; CHECK-BE-NEXT: vperm v2, v4, v2, v3 205; CHECK-BE-NEXT: stxv vs2, 32(r3) 206; CHECK-BE-NEXT: xvcvuxddp vs3, v2 207; CHECK-BE-NEXT: stxv vs3, 48(r3) 208; CHECK-BE-NEXT: blr 209entry: 210 %0 = uitofp <8 x i16> %a to <8 x double> 211 store <8 x double> %0, <8 x double>* %agg.result, align 64 212 ret void 213} 214 215define void @test16elt(<16 x double>* noalias nocapture sret(<16 x double>) %agg.result, <16 x i16>* nocapture readonly) local_unnamed_addr #3 { 216; CHECK-P8-LABEL: test16elt: 217; CHECK-P8: # %bb.0: # %entry 218; CHECK-P8-NEXT: addis r6, r2, .LCPI3_2@toc@ha 219; CHECK-P8-NEXT: addis r5, r2, .LCPI3_0@toc@ha 220; CHECK-P8-NEXT: lvx v4, 0, r4 221; CHECK-P8-NEXT: xxlxor v3, v3, v3 222; CHECK-P8-NEXT: addi r6, r6, .LCPI3_2@toc@l 223; CHECK-P8-NEXT: addi r5, r5, .LCPI3_0@toc@l 224; CHECK-P8-NEXT: lvx v5, 0, r6 225; CHECK-P8-NEXT: li r6, 16 226; CHECK-P8-NEXT: lvx v2, 0, r5 227; CHECK-P8-NEXT: addis r5, r2, .LCPI3_1@toc@ha 228; CHECK-P8-NEXT: lvx v0, r4, r6 229; CHECK-P8-NEXT: addis r4, r2, .LCPI3_3@toc@ha 230; CHECK-P8-NEXT: addi r5, r5, .LCPI3_1@toc@l 231; CHECK-P8-NEXT: addi r4, r4, .LCPI3_3@toc@l 232; CHECK-P8-NEXT: lvx v1, 0, r5 233; CHECK-P8-NEXT: li r5, 96 234; CHECK-P8-NEXT: lvx v8, 0, r4 235; CHECK-P8-NEXT: vperm v6, v3, v4, v2 236; CHECK-P8-NEXT: li r4, 112 237; CHECK-P8-NEXT: vperm v7, v3, v4, v5 238; CHECK-P8-NEXT: vperm v2, v3, v0, v2 239; CHECK-P8-NEXT: vperm v9, v3, v0, v1 240; CHECK-P8-NEXT: vperm v5, v3, v0, v5 241; CHECK-P8-NEXT: vperm v0, v3, v0, v8 242; CHECK-P8-NEXT: vperm v1, v3, v4, v1 243; CHECK-P8-NEXT: vperm v3, v3, v4, v8 244; CHECK-P8-NEXT: xvcvuxddp vs1, v2 245; CHECK-P8-NEXT: xvcvuxddp vs4, v9 246; CHECK-P8-NEXT: xvcvuxddp vs2, v5 247; CHECK-P8-NEXT: xvcvuxddp vs3, v0 248; CHECK-P8-NEXT: xvcvuxddp vs0, v7 249; CHECK-P8-NEXT: xvcvuxddp vs5, v3 250; CHECK-P8-NEXT: xvcvuxddp vs6, v6 251; CHECK-P8-NEXT: xxswapd vs1, vs1 252; CHECK-P8-NEXT: xvcvuxddp vs7, v1 253; CHECK-P8-NEXT: xxswapd vs4, vs4 254; CHECK-P8-NEXT: xxswapd vs2, vs2 255; CHECK-P8-NEXT: xxswapd vs3, vs3 256; CHECK-P8-NEXT: xxswapd vs0, vs0 257; CHECK-P8-NEXT: xxswapd vs5, vs5 258; CHECK-P8-NEXT: stxvd2x vs3, r3, r4 259; CHECK-P8-NEXT: stxvd2x vs2, r3, r5 260; CHECK-P8-NEXT: li r4, 80 261; CHECK-P8-NEXT: li r5, 64 262; CHECK-P8-NEXT: xxswapd vs2, vs7 263; CHECK-P8-NEXT: xxswapd vs3, vs6 264; CHECK-P8-NEXT: stxvd2x vs4, r3, r4 265; CHECK-P8-NEXT: li r4, 48 266; CHECK-P8-NEXT: stxvd2x vs1, r3, r5 267; CHECK-P8-NEXT: li r5, 32 268; CHECK-P8-NEXT: stxvd2x vs5, r3, r4 269; CHECK-P8-NEXT: stxvd2x vs0, r3, r5 270; CHECK-P8-NEXT: stxvd2x vs2, r3, r6 271; CHECK-P8-NEXT: stxvd2x vs3, 0, r3 272; CHECK-P8-NEXT: blr 273; 274; CHECK-P9-LABEL: test16elt: 275; CHECK-P9: # %bb.0: # %entry 276; CHECK-P9-NEXT: lxv v2, 16(r4) 277; CHECK-P9-NEXT: lxv v3, 0(r4) 278; CHECK-P9-NEXT: addis r4, r2, .LCPI3_0@toc@ha 279; CHECK-P9-NEXT: xxlxor v5, v5, v5 280; CHECK-P9-NEXT: addi r4, r4, .LCPI3_0@toc@l 281; CHECK-P9-NEXT: lxvx v4, 0, r4 282; CHECK-P9-NEXT: addis r4, r2, .LCPI3_1@toc@ha 283; CHECK-P9-NEXT: addi r4, r4, .LCPI3_1@toc@l 284; CHECK-P9-NEXT: vperm v0, v5, v3, v4 285; CHECK-P9-NEXT: xvcvuxddp vs0, v0 286; CHECK-P9-NEXT: lxvx v0, 0, r4 287; CHECK-P9-NEXT: addis r4, r2, .LCPI3_2@toc@ha 288; CHECK-P9-NEXT: addi r4, r4, .LCPI3_2@toc@l 289; CHECK-P9-NEXT: vperm v1, v5, v3, v0 290; CHECK-P9-NEXT: stxv vs0, 0(r3) 291; CHECK-P9-NEXT: xvcvuxddp vs1, v1 292; CHECK-P9-NEXT: lxvx v1, 0, r4 293; CHECK-P9-NEXT: addis r4, r2, .LCPI3_3@toc@ha 294; CHECK-P9-NEXT: addi r4, r4, .LCPI3_3@toc@l 295; CHECK-P9-NEXT: vperm v6, v5, v3, v1 296; CHECK-P9-NEXT: stxv vs1, 16(r3) 297; CHECK-P9-NEXT: xvcvuxddp vs2, v6 298; CHECK-P9-NEXT: lxvx v6, 0, r4 299; CHECK-P9-NEXT: vperm v3, v5, v3, v6 300; CHECK-P9-NEXT: stxv vs2, 32(r3) 301; CHECK-P9-NEXT: xvcvuxddp vs3, v3 302; CHECK-P9-NEXT: vperm v3, v5, v2, v4 303; CHECK-P9-NEXT: xvcvuxddp vs4, v3 304; CHECK-P9-NEXT: vperm v3, v5, v2, v0 305; CHECK-P9-NEXT: xvcvuxddp vs5, v3 306; CHECK-P9-NEXT: vperm v3, v5, v2, v1 307; CHECK-P9-NEXT: vperm v2, v5, v2, v6 308; CHECK-P9-NEXT: stxv vs3, 48(r3) 309; CHECK-P9-NEXT: xvcvuxddp vs6, v3 310; CHECK-P9-NEXT: xvcvuxddp vs7, v2 311; CHECK-P9-NEXT: stxv vs4, 64(r3) 312; CHECK-P9-NEXT: stxv vs5, 80(r3) 313; CHECK-P9-NEXT: stxv vs7, 112(r3) 314; CHECK-P9-NEXT: stxv vs6, 96(r3) 315; CHECK-P9-NEXT: blr 316; 317; CHECK-BE-LABEL: test16elt: 318; CHECK-BE: # %bb.0: # %entry 319; CHECK-BE-NEXT: lxv v2, 16(r4) 320; CHECK-BE-NEXT: lxv v3, 0(r4) 321; CHECK-BE-NEXT: addis r4, r2, .LCPI3_0@toc@ha 322; CHECK-BE-NEXT: xxlxor v5, v5, v5 323; CHECK-BE-NEXT: addi r4, r4, .LCPI3_0@toc@l 324; CHECK-BE-NEXT: lxvx v4, 0, r4 325; CHECK-BE-NEXT: addis r4, r2, .LCPI3_1@toc@ha 326; CHECK-BE-NEXT: addi r4, r4, .LCPI3_1@toc@l 327; CHECK-BE-NEXT: vperm v0, v3, v5, v4 328; CHECK-BE-NEXT: xvcvuxddp vs0, v0 329; CHECK-BE-NEXT: lxvx v0, 0, r4 330; CHECK-BE-NEXT: addis r4, r2, .LCPI3_2@toc@ha 331; CHECK-BE-NEXT: addi r4, r4, .LCPI3_2@toc@l 332; CHECK-BE-NEXT: vperm v1, v5, v3, v0 333; CHECK-BE-NEXT: stxv vs0, 0(r3) 334; CHECK-BE-NEXT: xvcvuxddp vs1, v1 335; CHECK-BE-NEXT: lxvx v1, 0, r4 336; CHECK-BE-NEXT: addis r4, r2, .LCPI3_3@toc@ha 337; CHECK-BE-NEXT: addi r4, r4, .LCPI3_3@toc@l 338; CHECK-BE-NEXT: vperm v6, v5, v3, v1 339; CHECK-BE-NEXT: stxv vs1, 16(r3) 340; CHECK-BE-NEXT: xvcvuxddp vs2, v6 341; CHECK-BE-NEXT: lxvx v6, 0, r4 342; CHECK-BE-NEXT: vperm v3, v5, v3, v6 343; CHECK-BE-NEXT: stxv vs2, 32(r3) 344; CHECK-BE-NEXT: xvcvuxddp vs3, v3 345; CHECK-BE-NEXT: vperm v3, v2, v5, v4 346; CHECK-BE-NEXT: xvcvuxddp vs4, v3 347; CHECK-BE-NEXT: vperm v3, v5, v2, v0 348; CHECK-BE-NEXT: xvcvuxddp vs5, v3 349; CHECK-BE-NEXT: vperm v3, v5, v2, v1 350; CHECK-BE-NEXT: vperm v2, v5, v2, v6 351; CHECK-BE-NEXT: stxv vs3, 48(r3) 352; CHECK-BE-NEXT: xvcvuxddp vs6, v3 353; CHECK-BE-NEXT: xvcvuxddp vs7, v2 354; CHECK-BE-NEXT: stxv vs4, 64(r3) 355; CHECK-BE-NEXT: stxv vs5, 80(r3) 356; CHECK-BE-NEXT: stxv vs7, 112(r3) 357; CHECK-BE-NEXT: stxv vs6, 96(r3) 358; CHECK-BE-NEXT: blr 359entry: 360 %a = load <16 x i16>, <16 x i16>* %0, align 32 361 %1 = uitofp <16 x i16> %a to <16 x double> 362 store <16 x double> %1, <16 x double>* %agg.result, align 128 363 ret void 364} 365 366define <2 x double> @test2elt_signed(i32 %a.coerce) local_unnamed_addr #0 { 367; CHECK-P8-LABEL: test2elt_signed: 368; CHECK-P8: # %bb.0: # %entry 369; CHECK-P8-NEXT: addis r4, r2, .LCPI4_0@toc@ha 370; CHECK-P8-NEXT: mtvsrwz v3, r3 371; CHECK-P8-NEXT: addis r3, r2, .LCPI4_1@toc@ha 372; CHECK-P8-NEXT: addi r4, r4, .LCPI4_0@toc@l 373; CHECK-P8-NEXT: addi r3, r3, .LCPI4_1@toc@l 374; CHECK-P8-NEXT: lvx v2, 0, r4 375; CHECK-P8-NEXT: lxvd2x vs0, 0, r3 376; CHECK-P8-NEXT: vperm v2, v3, v3, v2 377; CHECK-P8-NEXT: xxswapd v3, vs0 378; CHECK-P8-NEXT: vsld v2, v2, v3 379; CHECK-P8-NEXT: vsrad v2, v2, v3 380; CHECK-P8-NEXT: xvcvsxddp v2, v2 381; CHECK-P8-NEXT: blr 382; 383; CHECK-P9-LABEL: test2elt_signed: 384; CHECK-P9: # %bb.0: # %entry 385; CHECK-P9-NEXT: mtvsrws v2, r3 386; CHECK-P9-NEXT: addis r3, r2, .LCPI4_0@toc@ha 387; CHECK-P9-NEXT: addi r3, r3, .LCPI4_0@toc@l 388; CHECK-P9-NEXT: lxvx v3, 0, r3 389; CHECK-P9-NEXT: vperm v2, v2, v2, v3 390; CHECK-P9-NEXT: vextsh2d v2, v2 391; CHECK-P9-NEXT: xvcvsxddp v2, v2 392; CHECK-P9-NEXT: blr 393; 394; CHECK-BE-LABEL: test2elt_signed: 395; CHECK-BE: # %bb.0: # %entry 396; CHECK-BE-NEXT: mtvsrws v2, r3 397; CHECK-BE-NEXT: addis r3, r2, .LCPI4_0@toc@ha 398; CHECK-BE-NEXT: addi r3, r3, .LCPI4_0@toc@l 399; CHECK-BE-NEXT: lxvx v3, 0, r3 400; CHECK-BE-NEXT: vperm v2, v2, v2, v3 401; CHECK-BE-NEXT: vextsh2d v2, v2 402; CHECK-BE-NEXT: xvcvsxddp v2, v2 403; CHECK-BE-NEXT: blr 404entry: 405 %0 = bitcast i32 %a.coerce to <2 x i16> 406 %1 = sitofp <2 x i16> %0 to <2 x double> 407 ret <2 x double> %1 408} 409 410define void @test4elt_signed(<4 x double>* noalias nocapture sret(<4 x double>) %agg.result, i64 %a.coerce) local_unnamed_addr #1 { 411; CHECK-P8-LABEL: test4elt_signed: 412; CHECK-P8: # %bb.0: # %entry 413; CHECK-P8-NEXT: addis r5, r2, .LCPI5_0@toc@ha 414; CHECK-P8-NEXT: addis r6, r2, .LCPI5_2@toc@ha 415; CHECK-P8-NEXT: mtvsrd v3, r4 416; CHECK-P8-NEXT: addis r4, r2, .LCPI5_1@toc@ha 417; CHECK-P8-NEXT: addi r5, r5, .LCPI5_0@toc@l 418; CHECK-P8-NEXT: addi r4, r4, .LCPI5_1@toc@l 419; CHECK-P8-NEXT: lvx v2, 0, r5 420; CHECK-P8-NEXT: addi r5, r6, .LCPI5_2@toc@l 421; CHECK-P8-NEXT: lxvd2x vs0, 0, r4 422; CHECK-P8-NEXT: li r4, 16 423; CHECK-P8-NEXT: lvx v4, 0, r5 424; CHECK-P8-NEXT: vperm v2, v3, v3, v2 425; CHECK-P8-NEXT: vperm v3, v3, v3, v4 426; CHECK-P8-NEXT: xxswapd v4, vs0 427; CHECK-P8-NEXT: vsld v2, v2, v4 428; CHECK-P8-NEXT: vsld v3, v3, v4 429; CHECK-P8-NEXT: vsrad v2, v2, v4 430; CHECK-P8-NEXT: vsrad v3, v3, v4 431; CHECK-P8-NEXT: xvcvsxddp vs0, v2 432; CHECK-P8-NEXT: xvcvsxddp vs1, v3 433; CHECK-P8-NEXT: xxswapd vs0, vs0 434; CHECK-P8-NEXT: xxswapd vs1, vs1 435; CHECK-P8-NEXT: stxvd2x vs1, r3, r4 436; CHECK-P8-NEXT: stxvd2x vs0, 0, r3 437; CHECK-P8-NEXT: blr 438; 439; CHECK-P9-LABEL: test4elt_signed: 440; CHECK-P9: # %bb.0: # %entry 441; CHECK-P9-NEXT: mtvsrd v2, r4 442; CHECK-P9-NEXT: addis r4, r2, .LCPI5_0@toc@ha 443; CHECK-P9-NEXT: addi r4, r4, .LCPI5_0@toc@l 444; CHECK-P9-NEXT: lxvx v3, 0, r4 445; CHECK-P9-NEXT: addis r4, r2, .LCPI5_1@toc@ha 446; CHECK-P9-NEXT: addi r4, r4, .LCPI5_1@toc@l 447; CHECK-P9-NEXT: vperm v3, v2, v2, v3 448; CHECK-P9-NEXT: vextsh2d v3, v3 449; CHECK-P9-NEXT: xvcvsxddp vs0, v3 450; CHECK-P9-NEXT: lxvx v3, 0, r4 451; CHECK-P9-NEXT: vperm v2, v2, v2, v3 452; CHECK-P9-NEXT: stxv vs0, 0(r3) 453; CHECK-P9-NEXT: vextsh2d v2, v2 454; CHECK-P9-NEXT: xvcvsxddp vs1, v2 455; CHECK-P9-NEXT: stxv vs1, 16(r3) 456; CHECK-P9-NEXT: blr 457; 458; CHECK-BE-LABEL: test4elt_signed: 459; CHECK-BE: # %bb.0: # %entry 460; CHECK-BE-NEXT: mtvsrd v2, r4 461; CHECK-BE-NEXT: addis r4, r2, .LCPI5_0@toc@ha 462; CHECK-BE-NEXT: xxlxor v3, v3, v3 463; CHECK-BE-NEXT: addi r4, r4, .LCPI5_0@toc@l 464; CHECK-BE-NEXT: lxvx v4, 0, r4 465; CHECK-BE-NEXT: addis r4, r2, .LCPI5_1@toc@ha 466; CHECK-BE-NEXT: addi r4, r4, .LCPI5_1@toc@l 467; CHECK-BE-NEXT: vperm v3, v3, v2, v4 468; CHECK-BE-NEXT: vextsh2d v3, v3 469; CHECK-BE-NEXT: xvcvsxddp vs0, v3 470; CHECK-BE-NEXT: lxvx v3, 0, r4 471; CHECK-BE-NEXT: vperm v2, v2, v2, v3 472; CHECK-BE-NEXT: stxv vs0, 16(r3) 473; CHECK-BE-NEXT: vextsh2d v2, v2 474; CHECK-BE-NEXT: xvcvsxddp vs1, v2 475; CHECK-BE-NEXT: stxv vs1, 0(r3) 476; CHECK-BE-NEXT: blr 477entry: 478 %0 = bitcast i64 %a.coerce to <4 x i16> 479 %1 = sitofp <4 x i16> %0 to <4 x double> 480 store <4 x double> %1, <4 x double>* %agg.result, align 32 481 ret void 482} 483 484define void @test8elt_signed(<8 x double>* noalias nocapture sret(<8 x double>) %agg.result, <8 x i16> %a) local_unnamed_addr #2 { 485; CHECK-P8-LABEL: test8elt_signed: 486; CHECK-P8: # %bb.0: # %entry 487; CHECK-P8-NEXT: addis r5, r2, .LCPI6_2@toc@ha 488; CHECK-P8-NEXT: addis r4, r2, .LCPI6_0@toc@ha 489; CHECK-P8-NEXT: addis r6, r2, .LCPI6_3@toc@ha 490; CHECK-P8-NEXT: addi r5, r5, .LCPI6_2@toc@l 491; CHECK-P8-NEXT: addi r4, r4, .LCPI6_0@toc@l 492; CHECK-P8-NEXT: addi r6, r6, .LCPI6_3@toc@l 493; CHECK-P8-NEXT: lvx v4, 0, r5 494; CHECK-P8-NEXT: addis r5, r2, .LCPI6_4@toc@ha 495; CHECK-P8-NEXT: lvx v3, 0, r4 496; CHECK-P8-NEXT: lvx v5, 0, r6 497; CHECK-P8-NEXT: addis r4, r2, .LCPI6_1@toc@ha 498; CHECK-P8-NEXT: addi r5, r5, .LCPI6_4@toc@l 499; CHECK-P8-NEXT: addi r4, r4, .LCPI6_1@toc@l 500; CHECK-P8-NEXT: lvx v0, 0, r5 501; CHECK-P8-NEXT: lxvd2x vs0, 0, r4 502; CHECK-P8-NEXT: li r4, 48 503; CHECK-P8-NEXT: li r5, 32 504; CHECK-P8-NEXT: vperm v3, v2, v2, v3 505; CHECK-P8-NEXT: vperm v4, v2, v2, v4 506; CHECK-P8-NEXT: vperm v5, v2, v2, v5 507; CHECK-P8-NEXT: vperm v2, v2, v2, v0 508; CHECK-P8-NEXT: xxswapd v0, vs0 509; CHECK-P8-NEXT: vsld v3, v3, v0 510; CHECK-P8-NEXT: vsld v4, v4, v0 511; CHECK-P8-NEXT: vsld v5, v5, v0 512; CHECK-P8-NEXT: vsld v2, v2, v0 513; CHECK-P8-NEXT: vsrad v3, v3, v0 514; CHECK-P8-NEXT: vsrad v2, v2, v0 515; CHECK-P8-NEXT: vsrad v4, v4, v0 516; CHECK-P8-NEXT: vsrad v5, v5, v0 517; CHECK-P8-NEXT: xvcvsxddp vs2, v2 518; CHECK-P8-NEXT: xvcvsxddp vs0, v3 519; CHECK-P8-NEXT: xvcvsxddp vs1, v5 520; CHECK-P8-NEXT: xvcvsxddp vs3, v4 521; CHECK-P8-NEXT: xxswapd vs2, vs2 522; CHECK-P8-NEXT: xxswapd vs0, vs0 523; CHECK-P8-NEXT: xxswapd vs1, vs1 524; CHECK-P8-NEXT: xxswapd vs3, vs3 525; CHECK-P8-NEXT: stxvd2x vs2, r3, r4 526; CHECK-P8-NEXT: li r4, 16 527; CHECK-P8-NEXT: stxvd2x vs1, r3, r5 528; CHECK-P8-NEXT: stxvd2x vs3, r3, r4 529; CHECK-P8-NEXT: stxvd2x vs0, 0, r3 530; CHECK-P8-NEXT: blr 531; 532; CHECK-P9-LABEL: test8elt_signed: 533; CHECK-P9: # %bb.0: # %entry 534; CHECK-P9-NEXT: addis r4, r2, .LCPI6_0@toc@ha 535; CHECK-P9-NEXT: addi r4, r4, .LCPI6_0@toc@l 536; CHECK-P9-NEXT: lxvx v3, 0, r4 537; CHECK-P9-NEXT: addis r4, r2, .LCPI6_1@toc@ha 538; CHECK-P9-NEXT: addi r4, r4, .LCPI6_1@toc@l 539; CHECK-P9-NEXT: vperm v3, v2, v2, v3 540; CHECK-P9-NEXT: vextsh2d v3, v3 541; CHECK-P9-NEXT: xvcvsxddp vs0, v3 542; CHECK-P9-NEXT: lxvx v3, 0, r4 543; CHECK-P9-NEXT: addis r4, r2, .LCPI6_2@toc@ha 544; CHECK-P9-NEXT: addi r4, r4, .LCPI6_2@toc@l 545; CHECK-P9-NEXT: vperm v3, v2, v2, v3 546; CHECK-P9-NEXT: stxv vs0, 0(r3) 547; CHECK-P9-NEXT: vextsh2d v3, v3 548; CHECK-P9-NEXT: xvcvsxddp vs1, v3 549; CHECK-P9-NEXT: lxvx v3, 0, r4 550; CHECK-P9-NEXT: addis r4, r2, .LCPI6_3@toc@ha 551; CHECK-P9-NEXT: addi r4, r4, .LCPI6_3@toc@l 552; CHECK-P9-NEXT: vperm v3, v2, v2, v3 553; CHECK-P9-NEXT: stxv vs1, 16(r3) 554; CHECK-P9-NEXT: vextsh2d v3, v3 555; CHECK-P9-NEXT: xvcvsxddp vs2, v3 556; CHECK-P9-NEXT: lxvx v3, 0, r4 557; CHECK-P9-NEXT: vperm v2, v2, v2, v3 558; CHECK-P9-NEXT: stxv vs2, 32(r3) 559; CHECK-P9-NEXT: vextsh2d v2, v2 560; CHECK-P9-NEXT: xvcvsxddp vs3, v2 561; CHECK-P9-NEXT: stxv vs3, 48(r3) 562; CHECK-P9-NEXT: blr 563; 564; CHECK-BE-LABEL: test8elt_signed: 565; CHECK-BE: # %bb.0: # %entry 566; CHECK-BE-NEXT: addis r4, r2, .LCPI6_0@toc@ha 567; CHECK-BE-NEXT: xxlxor v4, v4, v4 568; CHECK-BE-NEXT: addi r4, r4, .LCPI6_0@toc@l 569; CHECK-BE-NEXT: lxvx v3, 0, r4 570; CHECK-BE-NEXT: addis r4, r2, .LCPI6_1@toc@ha 571; CHECK-BE-NEXT: addi r4, r4, .LCPI6_1@toc@l 572; CHECK-BE-NEXT: vperm v3, v4, v2, v3 573; CHECK-BE-NEXT: vextsh2d v3, v3 574; CHECK-BE-NEXT: xvcvsxddp vs0, v3 575; CHECK-BE-NEXT: lxvx v3, 0, r4 576; CHECK-BE-NEXT: addis r4, r2, .LCPI6_2@toc@ha 577; CHECK-BE-NEXT: addi r4, r4, .LCPI6_2@toc@l 578; CHECK-BE-NEXT: vperm v3, v4, v2, v3 579; CHECK-BE-NEXT: stxv vs0, 16(r3) 580; CHECK-BE-NEXT: vextsh2d v3, v3 581; CHECK-BE-NEXT: xvcvsxddp vs1, v3 582; CHECK-BE-NEXT: lxvx v3, 0, r4 583; CHECK-BE-NEXT: addis r4, r2, .LCPI6_3@toc@ha 584; CHECK-BE-NEXT: addi r4, r4, .LCPI6_3@toc@l 585; CHECK-BE-NEXT: vperm v3, v2, v2, v3 586; CHECK-BE-NEXT: stxv vs1, 48(r3) 587; CHECK-BE-NEXT: vextsh2d v3, v3 588; CHECK-BE-NEXT: xvcvsxddp vs2, v3 589; CHECK-BE-NEXT: lxvx v3, 0, r4 590; CHECK-BE-NEXT: vperm v2, v2, v2, v3 591; CHECK-BE-NEXT: stxv vs2, 0(r3) 592; CHECK-BE-NEXT: vextsh2d v2, v2 593; CHECK-BE-NEXT: xvcvsxddp vs3, v2 594; CHECK-BE-NEXT: stxv vs3, 32(r3) 595; CHECK-BE-NEXT: blr 596entry: 597 %0 = sitofp <8 x i16> %a to <8 x double> 598 store <8 x double> %0, <8 x double>* %agg.result, align 64 599 ret void 600} 601 602define void @test16elt_signed(<16 x double>* noalias nocapture sret(<16 x double>) %agg.result, <16 x i16>* nocapture readonly) local_unnamed_addr #3 { 603; CHECK-P8-LABEL: test16elt_signed: 604; CHECK-P8: # %bb.0: # %entry 605; CHECK-P8-NEXT: addis r5, r2, .LCPI7_0@toc@ha 606; CHECK-P8-NEXT: addis r6, r2, .LCPI7_2@toc@ha 607; CHECK-P8-NEXT: lvx v4, 0, r4 608; CHECK-P8-NEXT: addi r5, r5, .LCPI7_0@toc@l 609; CHECK-P8-NEXT: addi r6, r6, .LCPI7_2@toc@l 610; CHECK-P8-NEXT: lvx v2, 0, r5 611; CHECK-P8-NEXT: addis r5, r2, .LCPI7_3@toc@ha 612; CHECK-P8-NEXT: lvx v3, 0, r6 613; CHECK-P8-NEXT: addis r6, r2, .LCPI7_4@toc@ha 614; CHECK-P8-NEXT: addi r5, r5, .LCPI7_3@toc@l 615; CHECK-P8-NEXT: addi r6, r6, .LCPI7_4@toc@l 616; CHECK-P8-NEXT: lvx v5, 0, r5 617; CHECK-P8-NEXT: lvx v0, 0, r6 618; CHECK-P8-NEXT: li r6, 16 619; CHECK-P8-NEXT: addis r5, r2, .LCPI7_1@toc@ha 620; CHECK-P8-NEXT: lvx v7, r4, r6 621; CHECK-P8-NEXT: addi r5, r5, .LCPI7_1@toc@l 622; CHECK-P8-NEXT: vperm v1, v4, v4, v2 623; CHECK-P8-NEXT: li r4, 112 624; CHECK-P8-NEXT: vperm v6, v4, v4, v3 625; CHECK-P8-NEXT: lxvd2x vs0, 0, r5 626; CHECK-P8-NEXT: li r5, 96 627; CHECK-P8-NEXT: vperm v8, v4, v4, v5 628; CHECK-P8-NEXT: vperm v4, v4, v4, v0 629; CHECK-P8-NEXT: vperm v5, v7, v7, v5 630; CHECK-P8-NEXT: xxswapd v9, vs0 631; CHECK-P8-NEXT: vperm v0, v7, v7, v0 632; CHECK-P8-NEXT: vperm v2, v7, v7, v2 633; CHECK-P8-NEXT: vperm v3, v7, v7, v3 634; CHECK-P8-NEXT: vsld v1, v1, v9 635; CHECK-P8-NEXT: vsld v6, v6, v9 636; CHECK-P8-NEXT: vsld v5, v5, v9 637; CHECK-P8-NEXT: vsld v0, v0, v9 638; CHECK-P8-NEXT: vsld v2, v2, v9 639; CHECK-P8-NEXT: vsld v3, v3, v9 640; CHECK-P8-NEXT: vsrad v5, v5, v9 641; CHECK-P8-NEXT: vsrad v0, v0, v9 642; CHECK-P8-NEXT: vsld v7, v8, v9 643; CHECK-P8-NEXT: vsld v4, v4, v9 644; CHECK-P8-NEXT: vsrad v2, v2, v9 645; CHECK-P8-NEXT: vsrad v3, v3, v9 646; CHECK-P8-NEXT: xvcvsxddp vs2, v5 647; CHECK-P8-NEXT: xvcvsxddp vs3, v0 648; CHECK-P8-NEXT: vsrad v1, v1, v9 649; CHECK-P8-NEXT: vsrad v6, v6, v9 650; CHECK-P8-NEXT: vsrad v7, v7, v9 651; CHECK-P8-NEXT: vsrad v4, v4, v9 652; CHECK-P8-NEXT: xvcvsxddp vs1, v2 653; CHECK-P8-NEXT: xxswapd vs2, vs2 654; CHECK-P8-NEXT: xvcvsxddp vs4, v3 655; CHECK-P8-NEXT: xxswapd vs3, vs3 656; CHECK-P8-NEXT: xvcvsxddp vs0, v7 657; CHECK-P8-NEXT: xvcvsxddp vs5, v4 658; CHECK-P8-NEXT: xvcvsxddp vs6, v1 659; CHECK-P8-NEXT: stxvd2x vs3, r3, r4 660; CHECK-P8-NEXT: li r4, 80 661; CHECK-P8-NEXT: xvcvsxddp vs7, v6 662; CHECK-P8-NEXT: stxvd2x vs2, r3, r5 663; CHECK-P8-NEXT: li r5, 64 664; CHECK-P8-NEXT: xxswapd vs1, vs1 665; CHECK-P8-NEXT: xxswapd vs4, vs4 666; CHECK-P8-NEXT: xxswapd vs0, vs0 667; CHECK-P8-NEXT: xxswapd vs5, vs5 668; CHECK-P8-NEXT: xxswapd vs3, vs6 669; CHECK-P8-NEXT: stxvd2x vs4, r3, r4 670; CHECK-P8-NEXT: li r4, 48 671; CHECK-P8-NEXT: xxswapd vs2, vs7 672; CHECK-P8-NEXT: stxvd2x vs1, r3, r5 673; CHECK-P8-NEXT: li r5, 32 674; CHECK-P8-NEXT: stxvd2x vs5, r3, r4 675; CHECK-P8-NEXT: stxvd2x vs0, r3, r5 676; CHECK-P8-NEXT: stxvd2x vs2, r3, r6 677; CHECK-P8-NEXT: stxvd2x vs3, 0, r3 678; CHECK-P8-NEXT: blr 679; 680; CHECK-P9-LABEL: test16elt_signed: 681; CHECK-P9: # %bb.0: # %entry 682; CHECK-P9-NEXT: addis r5, r2, .LCPI7_0@toc@ha 683; CHECK-P9-NEXT: lxv v2, 0(r4) 684; CHECK-P9-NEXT: addi r5, r5, .LCPI7_0@toc@l 685; CHECK-P9-NEXT: lxvx v3, 0, r5 686; CHECK-P9-NEXT: addis r5, r2, .LCPI7_1@toc@ha 687; CHECK-P9-NEXT: addi r5, r5, .LCPI7_1@toc@l 688; CHECK-P9-NEXT: lxvx v5, 0, r5 689; CHECK-P9-NEXT: addis r5, r2, .LCPI7_2@toc@ha 690; CHECK-P9-NEXT: vperm v4, v2, v2, v3 691; CHECK-P9-NEXT: addi r5, r5, .LCPI7_2@toc@l 692; CHECK-P9-NEXT: vextsh2d v4, v4 693; CHECK-P9-NEXT: lxvx v0, 0, r5 694; CHECK-P9-NEXT: addis r5, r2, .LCPI7_3@toc@ha 695; CHECK-P9-NEXT: xvcvsxddp vs0, v4 696; CHECK-P9-NEXT: vperm v4, v2, v2, v5 697; CHECK-P9-NEXT: addi r5, r5, .LCPI7_3@toc@l 698; CHECK-P9-NEXT: lxvx v1, 0, r5 699; CHECK-P9-NEXT: vextsh2d v4, v4 700; CHECK-P9-NEXT: xvcvsxddp vs1, v4 701; CHECK-P9-NEXT: vperm v4, v2, v2, v0 702; CHECK-P9-NEXT: vperm v2, v2, v2, v1 703; CHECK-P9-NEXT: stxv vs0, 0(r3) 704; CHECK-P9-NEXT: vextsh2d v4, v4 705; CHECK-P9-NEXT: xvcvsxddp vs2, v4 706; CHECK-P9-NEXT: lxv v4, 16(r4) 707; CHECK-P9-NEXT: stxv vs1, 16(r3) 708; CHECK-P9-NEXT: vextsh2d v2, v2 709; CHECK-P9-NEXT: xvcvsxddp vs3, v2 710; CHECK-P9-NEXT: vperm v2, v4, v4, v3 711; CHECK-P9-NEXT: stxv vs2, 32(r3) 712; CHECK-P9-NEXT: vextsh2d v2, v2 713; CHECK-P9-NEXT: stxv vs3, 48(r3) 714; CHECK-P9-NEXT: xvcvsxddp vs4, v2 715; CHECK-P9-NEXT: vperm v2, v4, v4, v5 716; CHECK-P9-NEXT: vextsh2d v2, v2 717; CHECK-P9-NEXT: xvcvsxddp vs5, v2 718; CHECK-P9-NEXT: vperm v2, v4, v4, v0 719; CHECK-P9-NEXT: stxv vs4, 64(r3) 720; CHECK-P9-NEXT: vextsh2d v2, v2 721; CHECK-P9-NEXT: xvcvsxddp vs6, v2 722; CHECK-P9-NEXT: vperm v2, v4, v4, v1 723; CHECK-P9-NEXT: stxv vs5, 80(r3) 724; CHECK-P9-NEXT: vextsh2d v2, v2 725; CHECK-P9-NEXT: xvcvsxddp vs7, v2 726; CHECK-P9-NEXT: stxv vs6, 96(r3) 727; CHECK-P9-NEXT: stxv vs7, 112(r3) 728; CHECK-P9-NEXT: blr 729; 730; CHECK-BE-LABEL: test16elt_signed: 731; CHECK-BE: # %bb.0: # %entry 732; CHECK-BE-NEXT: addis r5, r2, .LCPI7_0@toc@ha 733; CHECK-BE-NEXT: lxv v4, 0(r4) 734; CHECK-BE-NEXT: lxv v1, 16(r4) 735; CHECK-BE-NEXT: xxlxor v5, v5, v5 736; CHECK-BE-NEXT: addis r4, r2, .LCPI7_2@toc@ha 737; CHECK-BE-NEXT: addi r5, r5, .LCPI7_0@toc@l 738; CHECK-BE-NEXT: addi r4, r4, .LCPI7_2@toc@l 739; CHECK-BE-NEXT: lxvx v2, 0, r5 740; CHECK-BE-NEXT: addis r5, r2, .LCPI7_1@toc@ha 741; CHECK-BE-NEXT: addi r5, r5, .LCPI7_1@toc@l 742; CHECK-BE-NEXT: lxvx v3, 0, r5 743; CHECK-BE-NEXT: vperm v0, v5, v4, v2 744; CHECK-BE-NEXT: vperm v2, v5, v1, v2 745; CHECK-BE-NEXT: vextsh2d v2, v2 746; CHECK-BE-NEXT: vextsh2d v0, v0 747; CHECK-BE-NEXT: xvcvsxddp vs2, v2 748; CHECK-BE-NEXT: vperm v2, v5, v1, v3 749; CHECK-BE-NEXT: xvcvsxddp vs0, v0 750; CHECK-BE-NEXT: vperm v0, v5, v4, v3 751; CHECK-BE-NEXT: vextsh2d v2, v2 752; CHECK-BE-NEXT: vextsh2d v0, v0 753; CHECK-BE-NEXT: xvcvsxddp vs3, v2 754; CHECK-BE-NEXT: lxvx v2, 0, r4 755; CHECK-BE-NEXT: addis r4, r2, .LCPI7_3@toc@ha 756; CHECK-BE-NEXT: xvcvsxddp vs1, v0 757; CHECK-BE-NEXT: addi r4, r4, .LCPI7_3@toc@l 758; CHECK-BE-NEXT: stxv vs2, 80(r3) 759; CHECK-BE-NEXT: stxv vs0, 16(r3) 760; CHECK-BE-NEXT: vperm v3, v4, v4, v2 761; CHECK-BE-NEXT: vperm v2, v1, v1, v2 762; CHECK-BE-NEXT: stxv vs3, 112(r3) 763; CHECK-BE-NEXT: stxv vs1, 48(r3) 764; CHECK-BE-NEXT: vextsh2d v3, v3 765; CHECK-BE-NEXT: vextsh2d v2, v2 766; CHECK-BE-NEXT: xvcvsxddp vs4, v3 767; CHECK-BE-NEXT: lxvx v3, 0, r4 768; CHECK-BE-NEXT: xvcvsxddp vs6, v2 769; CHECK-BE-NEXT: vperm v4, v4, v4, v3 770; CHECK-BE-NEXT: vperm v2, v1, v1, v3 771; CHECK-BE-NEXT: stxv vs6, 64(r3) 772; CHECK-BE-NEXT: stxv vs4, 0(r3) 773; CHECK-BE-NEXT: vextsh2d v4, v4 774; CHECK-BE-NEXT: vextsh2d v2, v2 775; CHECK-BE-NEXT: xvcvsxddp vs5, v4 776; CHECK-BE-NEXT: xvcvsxddp vs7, v2 777; CHECK-BE-NEXT: stxv vs7, 96(r3) 778; CHECK-BE-NEXT: stxv vs5, 32(r3) 779; CHECK-BE-NEXT: blr 780entry: 781 %a = load <16 x i16>, <16 x i16>* %0, align 32 782 %1 = sitofp <16 x i16> %a to <16 x double> 783 store <16 x double> %1, <16 x double>* %agg.result, align 128 784 ret void 785} 786