1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
2; RUN: opt < %s -basic-aa -slp-vectorizer -S | FileCheck %s -check-prefix=SSE
3; RUN: opt < %s -basic-aa -slp-vectorizer -S -mattr=+avx | FileCheck %s -check-prefix=AVX
4
5target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
6target triple = "x86_64-apple-macosx10.10.0"
7
8define void @testfunc(float* nocapture %dest, float* nocapture readonly %src) {
9; SSE-LABEL: @testfunc(
10; SSE-NEXT:  entry:
11; SSE-NEXT:    br label [[FOR_BODY:%.*]]
12; SSE:       for.body:
13; SSE-NEXT:    [[INDVARS_IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[INDVARS_IV_NEXT:%.*]], [[FOR_BODY]] ]
14; SSE-NEXT:    [[ACC1_056:%.*]] = phi float [ 0.000000e+00, [[ENTRY]] ], [ [[ADD13:%.*]], [[FOR_BODY]] ]
15; SSE-NEXT:    [[S1_055:%.*]] = phi float [ 0.000000e+00, [[ENTRY]] ], [ [[COND_I40:%.*]], [[FOR_BODY]] ]
16; SSE-NEXT:    [[S0_054:%.*]] = phi float [ 0.000000e+00, [[ENTRY]] ], [ [[COND_I44:%.*]], [[FOR_BODY]] ]
17; SSE-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[SRC:%.*]], i64 [[INDVARS_IV]]
18; SSE-NEXT:    [[TMP0:%.*]] = load float, float* [[ARRAYIDX]], align 4
19; SSE-NEXT:    [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 1
20; SSE-NEXT:    [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[DEST:%.*]], i64 [[INDVARS_IV]]
21; SSE-NEXT:    store float [[ACC1_056]], float* [[ARRAYIDX2]], align 4
22; SSE-NEXT:    [[ADD:%.*]] = fadd float [[S0_054]], [[TMP0]]
23; SSE-NEXT:    [[ADD3:%.*]] = fadd float [[S1_055]], [[TMP0]]
24; SSE-NEXT:    [[MUL:%.*]] = fmul float [[S0_054]], 0.000000e+00
25; SSE-NEXT:    [[ADD4:%.*]] = fadd float [[MUL]], [[ADD3]]
26; SSE-NEXT:    [[MUL5:%.*]] = fmul float [[S1_055]], 0.000000e+00
27; SSE-NEXT:    [[ADD6:%.*]] = fadd float [[MUL5]], [[ADD]]
28; SSE-NEXT:    [[CMP_I:%.*]] = fcmp olt float [[ADD6]], 1.000000e+00
29; SSE-NEXT:    [[COND_I:%.*]] = select i1 [[CMP_I]], float [[ADD6]], float 1.000000e+00
30; SSE-NEXT:    [[CMP_I51:%.*]] = fcmp olt float [[COND_I]], -1.000000e+00
31; SSE-NEXT:    [[CMP_I49:%.*]] = fcmp olt float [[ADD4]], 1.000000e+00
32; SSE-NEXT:    [[COND_I50:%.*]] = select i1 [[CMP_I49]], float [[ADD4]], float 1.000000e+00
33; SSE-NEXT:    [[CMP_I47:%.*]] = fcmp olt float [[COND_I50]], -1.000000e+00
34; SSE-NEXT:    [[COND_I_OP:%.*]] = fmul float [[COND_I]], 0.000000e+00
35; SSE-NEXT:    [[MUL10:%.*]] = select i1 [[CMP_I51]], float -0.000000e+00, float [[COND_I_OP]]
36; SSE-NEXT:    [[COND_I50_OP:%.*]] = fmul float [[COND_I50]], 0.000000e+00
37; SSE-NEXT:    [[MUL11:%.*]] = select i1 [[CMP_I47]], float -0.000000e+00, float [[COND_I50_OP]]
38; SSE-NEXT:    [[ADD13]] = fadd float [[MUL10]], [[MUL11]]
39; SSE-NEXT:    [[CMP_I45:%.*]] = fcmp olt float [[ADD13]], 1.000000e+00
40; SSE-NEXT:    [[COND_I46:%.*]] = select i1 [[CMP_I45]], float [[ADD13]], float 1.000000e+00
41; SSE-NEXT:    [[CMP_I43:%.*]] = fcmp olt float [[COND_I46]], -1.000000e+00
42; SSE-NEXT:    [[COND_I44]] = select i1 [[CMP_I43]], float -1.000000e+00, float [[COND_I46]]
43; SSE-NEXT:    [[CMP_I41:%.*]] = fcmp olt float [[MUL11]], 1.000000e+00
44; SSE-NEXT:    [[COND_I42:%.*]] = select i1 [[CMP_I41]], float [[MUL11]], float 1.000000e+00
45; SSE-NEXT:    [[CMP_I39:%.*]] = fcmp olt float [[COND_I42]], -1.000000e+00
46; SSE-NEXT:    [[COND_I40]] = select i1 [[CMP_I39]], float -1.000000e+00, float [[COND_I42]]
47; SSE-NEXT:    [[EXITCOND:%.*]] = icmp eq i64 [[INDVARS_IV_NEXT]], 32
48; SSE-NEXT:    br i1 [[EXITCOND]], label [[FOR_END:%.*]], label [[FOR_BODY]]
49; SSE:       for.end:
50; SSE-NEXT:    ret void
51;
52; AVX-LABEL: @testfunc(
53; AVX-NEXT:  entry:
54; AVX-NEXT:    br label [[FOR_BODY:%.*]]
55; AVX:       for.body:
56; AVX-NEXT:    [[INDVARS_IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[INDVARS_IV_NEXT:%.*]], [[FOR_BODY]] ]
57; AVX-NEXT:    [[ACC1_056:%.*]] = phi float [ 0.000000e+00, [[ENTRY]] ], [ [[ADD13:%.*]], [[FOR_BODY]] ]
58; AVX-NEXT:    [[TMP0:%.*]] = phi <2 x float> [ zeroinitializer, [[ENTRY]] ], [ [[TMP23:%.*]], [[FOR_BODY]] ]
59; AVX-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[SRC:%.*]], i64 [[INDVARS_IV]]
60; AVX-NEXT:    [[TMP1:%.*]] = load float, float* [[ARRAYIDX]], align 4
61; AVX-NEXT:    [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 1
62; AVX-NEXT:    [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[DEST:%.*]], i64 [[INDVARS_IV]]
63; AVX-NEXT:    store float [[ACC1_056]], float* [[ARRAYIDX2]], align 4
64; AVX-NEXT:    [[TMP2:%.*]] = extractelement <2 x float> [[TMP0]], i32 1
65; AVX-NEXT:    [[TMP3:%.*]] = insertelement <2 x float> poison, float [[TMP2]], i32 0
66; AVX-NEXT:    [[TMP4:%.*]] = extractelement <2 x float> [[TMP0]], i32 0
67; AVX-NEXT:    [[TMP5:%.*]] = insertelement <2 x float> [[TMP3]], float [[TMP4]], i32 1
68; AVX-NEXT:    [[TMP6:%.*]] = insertelement <2 x float> poison, float [[TMP1]], i32 0
69; AVX-NEXT:    [[TMP7:%.*]] = insertelement <2 x float> [[TMP6]], float [[TMP1]], i32 1
70; AVX-NEXT:    [[TMP8:%.*]] = fadd <2 x float> [[TMP5]], [[TMP7]]
71; AVX-NEXT:    [[TMP9:%.*]] = fmul <2 x float> [[TMP0]], zeroinitializer
72; AVX-NEXT:    [[TMP10:%.*]] = fadd <2 x float> [[TMP9]], [[TMP8]]
73; AVX-NEXT:    [[TMP11:%.*]] = fcmp olt <2 x float> [[TMP10]], <float 1.000000e+00, float 1.000000e+00>
74; AVX-NEXT:    [[TMP12:%.*]] = select <2 x i1> [[TMP11]], <2 x float> [[TMP10]], <2 x float> <float 1.000000e+00, float 1.000000e+00>
75; AVX-NEXT:    [[TMP13:%.*]] = fcmp olt <2 x float> [[TMP12]], <float -1.000000e+00, float -1.000000e+00>
76; AVX-NEXT:    [[TMP14:%.*]] = fmul <2 x float> [[TMP12]], zeroinitializer
77; AVX-NEXT:    [[TMP15:%.*]] = select <2 x i1> [[TMP13]], <2 x float> <float -0.000000e+00, float -0.000000e+00>, <2 x float> [[TMP14]]
78; AVX-NEXT:    [[TMP16:%.*]] = extractelement <2 x float> [[TMP15]], i32 0
79; AVX-NEXT:    [[TMP17:%.*]] = extractelement <2 x float> [[TMP15]], i32 1
80; AVX-NEXT:    [[ADD13]] = fadd float [[TMP16]], [[TMP17]]
81; AVX-NEXT:    [[TMP18:%.*]] = insertelement <2 x float> poison, float [[TMP17]], i32 0
82; AVX-NEXT:    [[TMP19:%.*]] = insertelement <2 x float> [[TMP18]], float [[ADD13]], i32 1
83; AVX-NEXT:    [[TMP20:%.*]] = fcmp olt <2 x float> [[TMP19]], <float 1.000000e+00, float 1.000000e+00>
84; AVX-NEXT:    [[TMP21:%.*]] = select <2 x i1> [[TMP20]], <2 x float> [[TMP19]], <2 x float> <float 1.000000e+00, float 1.000000e+00>
85; AVX-NEXT:    [[TMP22:%.*]] = fcmp olt <2 x float> [[TMP21]], <float -1.000000e+00, float -1.000000e+00>
86; AVX-NEXT:    [[TMP23]] = select <2 x i1> [[TMP22]], <2 x float> <float -1.000000e+00, float -1.000000e+00>, <2 x float> [[TMP21]]
87; AVX-NEXT:    [[EXITCOND:%.*]] = icmp eq i64 [[INDVARS_IV_NEXT]], 32
88; AVX-NEXT:    br i1 [[EXITCOND]], label [[FOR_END:%.*]], label [[FOR_BODY]]
89; AVX:       for.end:
90; AVX-NEXT:    ret void
91;
92entry:
93  br label %for.body
94
95for.body:
96  %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
97  %acc1.056 = phi float [ 0.000000e+00, %entry ], [ %add13, %for.body ]
98  %s1.055 = phi float [ 0.000000e+00, %entry ], [ %cond.i40, %for.body ]
99  %s0.054 = phi float [ 0.000000e+00, %entry ], [ %cond.i44, %for.body ]
100  %arrayidx = getelementptr inbounds float, float* %src, i64 %indvars.iv
101  %0 = load float, float* %arrayidx, align 4
102  %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
103  %arrayidx2 = getelementptr inbounds float, float* %dest, i64 %indvars.iv
104  store float %acc1.056, float* %arrayidx2, align 4
105  %add = fadd float %s0.054, %0
106  %add3 = fadd float %s1.055, %0
107  %mul = fmul float %s0.054, 0.000000e+00
108  %add4 = fadd float %mul, %add3
109  %mul5 = fmul float %s1.055, 0.000000e+00
110  %add6 = fadd float %mul5, %add
111  %cmp.i = fcmp olt float %add6, 1.000000e+00
112  %cond.i = select i1 %cmp.i, float %add6, float 1.000000e+00
113  %cmp.i51 = fcmp olt float %cond.i, -1.000000e+00
114  %cmp.i49 = fcmp olt float %add4, 1.000000e+00
115  %cond.i50 = select i1 %cmp.i49, float %add4, float 1.000000e+00
116  %cmp.i47 = fcmp olt float %cond.i50, -1.000000e+00
117  %cond.i.op = fmul float %cond.i, 0.000000e+00
118  %mul10 = select i1 %cmp.i51, float -0.000000e+00, float %cond.i.op
119  %cond.i50.op = fmul float %cond.i50, 0.000000e+00
120  %mul11 = select i1 %cmp.i47, float -0.000000e+00, float %cond.i50.op
121  %add13 = fadd float %mul10, %mul11
122
123  ; The SLPVectorizer crashed in vectorizeChainsInBlock() because it tried
124  ; to access the second operand of the following cmp after the cmp itself
125  ; was already vectorized and deleted.
126  %cmp.i45 = fcmp olt float %add13, 1.000000e+00
127
128  %cond.i46 = select i1 %cmp.i45, float %add13, float 1.000000e+00
129  %cmp.i43 = fcmp olt float %cond.i46, -1.000000e+00
130  %cond.i44 = select i1 %cmp.i43, float -1.000000e+00, float %cond.i46
131  %cmp.i41 = fcmp olt float %mul11, 1.000000e+00
132  %cond.i42 = select i1 %cmp.i41, float %mul11, float 1.000000e+00
133  %cmp.i39 = fcmp olt float %cond.i42, -1.000000e+00
134  %cond.i40 = select i1 %cmp.i39, float -1.000000e+00, float %cond.i42
135  %exitcond = icmp eq i64 %indvars.iv.next, 32
136  br i1 %exitcond, label %for.end, label %for.body
137
138for.end:
139  ret void
140}
141
142