1 //===-- SparcISelLowering.h - Sparc DAG Lowering Interface ------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file defines the interfaces that Sparc uses to lower LLVM code into a 10 // selection DAG. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef LLVM_LIB_TARGET_SPARC_SPARCISELLOWERING_H 15 #define LLVM_LIB_TARGET_SPARC_SPARCISELLOWERING_H 16 17 #include "Sparc.h" 18 #include "llvm/CodeGen/TargetLowering.h" 19 20 namespace llvm { 21 class SparcSubtarget; 22 23 namespace SPISD { 24 enum NodeType : unsigned { 25 FIRST_NUMBER = ISD::BUILTIN_OP_END, 26 CMPICC, // Compare two GPR operands, set icc+xcc. 27 CMPFCC, // Compare two FP operands, set fcc. 28 BRICC, // Branch to dest on icc condition 29 BRXCC, // Branch to dest on xcc condition (64-bit only). 30 BRFCC, // Branch to dest on fcc condition 31 SELECT_ICC, // Select between two values using the current ICC flags. 32 SELECT_XCC, // Select between two values using the current XCC flags. 33 SELECT_FCC, // Select between two values using the current FCC flags. 34 35 Hi, Lo, // Hi/Lo operations, typically on a global address. 36 37 FTOI, // FP to Int within a FP register. 38 ITOF, // Int to FP within a FP register. 39 FTOX, // FP to Int64 within a FP register. 40 XTOF, // Int64 to FP within a FP register. 41 42 CALL, // A call instruction. 43 RET_FLAG, // Return with a flag operand. 44 GLOBAL_BASE_REG, // Global base reg for PIC. 45 FLUSHW, // FLUSH register windows to stack. 46 47 TLS_ADD, // For Thread Local Storage (TLS). 48 TLS_LD, 49 TLS_CALL 50 }; 51 } 52 53 class SparcTargetLowering : public TargetLowering { 54 const SparcSubtarget *Subtarget; 55 public: 56 SparcTargetLowering(const TargetMachine &TM, const SparcSubtarget &STI); 57 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; 58 59 bool useSoftFloat() const override; 60 61 /// computeKnownBitsForTargetNode - Determine which of the bits specified 62 /// in Mask are known to be either zero or one and return them in the 63 /// KnownZero/KnownOne bitsets. 64 void computeKnownBitsForTargetNode(const SDValue Op, 65 KnownBits &Known, 66 const APInt &DemandedElts, 67 const SelectionDAG &DAG, 68 unsigned Depth = 0) const override; 69 70 MachineBasicBlock * 71 EmitInstrWithCustomInserter(MachineInstr &MI, 72 MachineBasicBlock *MBB) const override; 73 74 const char *getTargetNodeName(unsigned Opcode) const override; 75 76 ConstraintType getConstraintType(StringRef Constraint) const override; 77 ConstraintWeight 78 getSingleConstraintMatchWeight(AsmOperandInfo &info, 79 const char *constraint) const override; 80 void LowerAsmOperandForConstraint(SDValue Op, 81 std::string &Constraint, 82 std::vector<SDValue> &Ops, 83 SelectionDAG &DAG) const override; 84 85 std::pair<unsigned, const TargetRegisterClass *> 86 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, 87 StringRef Constraint, MVT VT) const override; 88 89 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override; getScalarShiftAmountTy(const DataLayout &,EVT)90 MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override { 91 return MVT::i32; 92 } 93 94 Register getRegisterByName(const char* RegName, LLT VT, 95 const MachineFunction &MF) const override; 96 97 /// If a physical register, this returns the register that receives the 98 /// exception address on entry to an EH pad. 99 Register getExceptionPointerRegister(const Constant * PersonalityFn)100 getExceptionPointerRegister(const Constant *PersonalityFn) const override { 101 return SP::I0; 102 } 103 104 /// If a physical register, this returns the register that receives the 105 /// exception typeid on entry to a landing pad. 106 Register getExceptionSelectorRegister(const Constant * PersonalityFn)107 getExceptionSelectorRegister(const Constant *PersonalityFn) const override { 108 return SP::I1; 109 } 110 111 /// Override to support customized stack guard loading. 112 bool useLoadStackGuardNode() const override; 113 void insertSSPDeclarations(Module &M) const override; 114 115 /// getSetCCResultType - Return the ISD::SETCC ValueType 116 EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, 117 EVT VT) const override; 118 119 SDValue 120 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, 121 const SmallVectorImpl<ISD::InputArg> &Ins, 122 const SDLoc &dl, SelectionDAG &DAG, 123 SmallVectorImpl<SDValue> &InVals) const override; 124 SDValue LowerFormalArguments_32(SDValue Chain, CallingConv::ID CallConv, 125 bool isVarArg, 126 const SmallVectorImpl<ISD::InputArg> &Ins, 127 const SDLoc &dl, SelectionDAG &DAG, 128 SmallVectorImpl<SDValue> &InVals) const; 129 SDValue LowerFormalArguments_64(SDValue Chain, CallingConv::ID CallConv, 130 bool isVarArg, 131 const SmallVectorImpl<ISD::InputArg> &Ins, 132 const SDLoc &dl, SelectionDAG &DAG, 133 SmallVectorImpl<SDValue> &InVals) const; 134 135 SDValue 136 LowerCall(TargetLowering::CallLoweringInfo &CLI, 137 SmallVectorImpl<SDValue> &InVals) const override; 138 SDValue LowerCall_32(TargetLowering::CallLoweringInfo &CLI, 139 SmallVectorImpl<SDValue> &InVals) const; 140 SDValue LowerCall_64(TargetLowering::CallLoweringInfo &CLI, 141 SmallVectorImpl<SDValue> &InVals) const; 142 143 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, 144 const SmallVectorImpl<ISD::OutputArg> &Outs, 145 const SmallVectorImpl<SDValue> &OutVals, 146 const SDLoc &dl, SelectionDAG &DAG) const override; 147 SDValue LowerReturn_32(SDValue Chain, CallingConv::ID CallConv, 148 bool IsVarArg, 149 const SmallVectorImpl<ISD::OutputArg> &Outs, 150 const SmallVectorImpl<SDValue> &OutVals, 151 const SDLoc &DL, SelectionDAG &DAG) const; 152 SDValue LowerReturn_64(SDValue Chain, CallingConv::ID CallConv, 153 bool IsVarArg, 154 const SmallVectorImpl<ISD::OutputArg> &Outs, 155 const SmallVectorImpl<SDValue> &OutVals, 156 const SDLoc &DL, SelectionDAG &DAG) const; 157 158 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const; 159 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const; 160 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const; 161 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const; 162 163 SDValue withTargetFlags(SDValue Op, unsigned TF, SelectionDAG &DAG) const; 164 SDValue makeHiLoPair(SDValue Op, unsigned HiTF, unsigned LoTF, 165 SelectionDAG &DAG) const; 166 SDValue makeAddress(SDValue Op, SelectionDAG &DAG) const; 167 168 SDValue LowerF128_LibCallArg(SDValue Chain, ArgListTy &Args, SDValue Arg, 169 const SDLoc &DL, SelectionDAG &DAG) const; 170 SDValue LowerF128Op(SDValue Op, SelectionDAG &DAG, 171 const char *LibFuncName, 172 unsigned numArgs) const; 173 SDValue LowerF128Compare(SDValue LHS, SDValue RHS, unsigned &SPCC, 174 const SDLoc &DL, SelectionDAG &DAG) const; 175 176 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const; 177 178 SDValue PerformBITCASTCombine(SDNode *N, DAGCombinerInfo &DCI) const; 179 180 SDValue bitcastConstantFPToInt(ConstantFPSDNode *C, const SDLoc &DL, 181 SelectionDAG &DAG) const; 182 183 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override; 184 ShouldShrinkFPConstant(EVT VT)185 bool ShouldShrinkFPConstant(EVT VT) const override { 186 // Do not shrink FP constpool if VT == MVT::f128. 187 // (ldd, call _Q_fdtoq) is more expensive than two ldds. 188 return VT != MVT::f128; 189 } 190 shouldInsertFencesForAtomic(const Instruction * I)191 bool shouldInsertFencesForAtomic(const Instruction *I) const override { 192 // FIXME: We insert fences for each atomics and generate 193 // sub-optimal code for PSO/TSO. (Approximately nobody uses any 194 // mode but TSO, which makes this even more silly) 195 return true; 196 } 197 198 AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override; 199 200 void ReplaceNodeResults(SDNode *N, 201 SmallVectorImpl<SDValue>& Results, 202 SelectionDAG &DAG) const override; 203 204 MachineBasicBlock *expandSelectCC(MachineInstr &MI, MachineBasicBlock *BB, 205 unsigned BROpcode) const; 206 }; 207 } // end namespace llvm 208 209 #endif // SPARC_ISELLOWERING_H 210