1//=- X86SchedSkylake.td - X86 Skylake Server Scheduling ------*- tablegen -*-=// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file defines the machine model for Skylake Server to support 10// instruction scheduling and other instruction cost heuristics. 11// 12//===----------------------------------------------------------------------===// 13 14def SkylakeServerModel : SchedMachineModel { 15 // All x86 instructions are modeled as a single micro-op, and SKylake can 16 // decode 6 instructions per cycle. 17 let IssueWidth = 6; 18 let MicroOpBufferSize = 224; // Based on the reorder buffer. 19 let LoadLatency = 5; 20 let MispredictPenalty = 14; 21 22 // Based on the LSD (loop-stream detector) queue size and benchmarking data. 23 let LoopMicroOpBufferSize = 50; 24 25 // This flag is set to allow the scheduler to assign a default model to 26 // unrecognized opcodes. 27 let CompleteModel = 0; 28} 29 30let SchedModel = SkylakeServerModel in { 31 32// Skylake Server can issue micro-ops to 8 different ports in one cycle. 33 34// Ports 0, 1, 5, and 6 handle all computation. 35// Port 4 gets the data half of stores. Store data can be available later than 36// the store address, but since we don't model the latency of stores, we can 37// ignore that. 38// Ports 2 and 3 are identical. They handle loads and the address half of 39// stores. Port 7 can handle address calculations. 40def SKXPort0 : ProcResource<1>; 41def SKXPort1 : ProcResource<1>; 42def SKXPort2 : ProcResource<1>; 43def SKXPort3 : ProcResource<1>; 44def SKXPort4 : ProcResource<1>; 45def SKXPort5 : ProcResource<1>; 46def SKXPort6 : ProcResource<1>; 47def SKXPort7 : ProcResource<1>; 48 49// Many micro-ops are capable of issuing on multiple ports. 50def SKXPort01 : ProcResGroup<[SKXPort0, SKXPort1]>; 51def SKXPort23 : ProcResGroup<[SKXPort2, SKXPort3]>; 52def SKXPort237 : ProcResGroup<[SKXPort2, SKXPort3, SKXPort7]>; 53def SKXPort04 : ProcResGroup<[SKXPort0, SKXPort4]>; 54def SKXPort05 : ProcResGroup<[SKXPort0, SKXPort5]>; 55def SKXPort06 : ProcResGroup<[SKXPort0, SKXPort6]>; 56def SKXPort15 : ProcResGroup<[SKXPort1, SKXPort5]>; 57def SKXPort16 : ProcResGroup<[SKXPort1, SKXPort6]>; 58def SKXPort56 : ProcResGroup<[SKXPort5, SKXPort6]>; 59def SKXPort015 : ProcResGroup<[SKXPort0, SKXPort1, SKXPort5]>; 60def SKXPort056 : ProcResGroup<[SKXPort0, SKXPort5, SKXPort6]>; 61def SKXPort0156: ProcResGroup<[SKXPort0, SKXPort1, SKXPort5, SKXPort6]>; 62 63def SKXDivider : ProcResource<1>; // Integer division issued on port 0. 64// FP division and sqrt on port 0. 65def SKXFPDivider : ProcResource<1>; 66 67// 60 Entry Unified Scheduler 68def SKXPortAny : ProcResGroup<[SKXPort0, SKXPort1, SKXPort2, SKXPort3, SKXPort4, 69 SKXPort5, SKXPort6, SKXPort7]> { 70 let BufferSize=60; 71} 72 73// Integer loads are 5 cycles, so ReadAfterLd registers needn't be available until 5 74// cycles after the memory operand. 75def : ReadAdvance<ReadAfterLd, 5>; 76 77// Vector loads are 5/6/7 cycles, so ReadAfterVec*Ld registers needn't be available 78// until 5/6/7 cycles after the memory operand. 79def : ReadAdvance<ReadAfterVecLd, 5>; 80def : ReadAdvance<ReadAfterVecXLd, 6>; 81def : ReadAdvance<ReadAfterVecYLd, 7>; 82 83def : ReadAdvance<ReadInt2Fpu, 0>; 84 85// Many SchedWrites are defined in pairs with and without a folded load. 86// Instructions with folded loads are usually micro-fused, so they only appear 87// as two micro-ops when queued in the reservation station. 88// This multiclass defines the resource usage for variants with and without 89// folded loads. 90multiclass SKXWriteResPair<X86FoldableSchedWrite SchedRW, 91 list<ProcResourceKind> ExePorts, 92 int Lat, list<int> Res = [1], int UOps = 1, 93 int LoadLat = 5> { 94 // Register variant is using a single cycle on ExePort. 95 def : WriteRes<SchedRW, ExePorts> { 96 let Latency = Lat; 97 let ResourceCycles = Res; 98 let NumMicroOps = UOps; 99 } 100 101 // Memory variant also uses a cycle on port 2/3 and adds LoadLat cycles to 102 // the latency (default = 5). 103 def : WriteRes<SchedRW.Folded, !listconcat([SKXPort23], ExePorts)> { 104 let Latency = !add(Lat, LoadLat); 105 let ResourceCycles = !listconcat([1], Res); 106 let NumMicroOps = !add(UOps, 1); 107 } 108} 109 110// A folded store needs a cycle on port 4 for the store data, and an extra port 111// 2/3/7 cycle to recompute the address. 112def : WriteRes<WriteRMW, [SKXPort237,SKXPort4]>; 113 114// Arithmetic. 115defm : SKXWriteResPair<WriteALU, [SKXPort0156], 1>; // Simple integer ALU op. 116defm : SKXWriteResPair<WriteADC, [SKXPort06], 1>; // Integer ALU + flags op. 117 118// Integer multiplication. 119defm : SKXWriteResPair<WriteIMul8, [SKXPort1], 3>; 120defm : SKXWriteResPair<WriteIMul16, [SKXPort1,SKXPort06,SKXPort0156], 4, [1,1,2], 4>; 121defm : X86WriteRes<WriteIMul16Imm, [SKXPort1,SKXPort0156], 4, [1,1], 2>; 122defm : X86WriteRes<WriteIMul16ImmLd, [SKXPort1,SKXPort0156,SKXPort23], 8, [1,1,1], 3>; 123defm : X86WriteRes<WriteIMul16Reg, [SKXPort1], 3, [1], 1>; 124defm : X86WriteRes<WriteIMul16RegLd, [SKXPort1,SKXPort0156,SKXPort23], 8, [1,1,1], 3>; 125defm : SKXWriteResPair<WriteIMul32, [SKXPort1,SKXPort06,SKXPort0156], 4, [1,1,1], 3>; 126defm : SKXWriteResPair<WriteIMul32Imm, [SKXPort1], 3>; 127defm : SKXWriteResPair<WriteIMul32Reg, [SKXPort1], 3>; 128defm : SKXWriteResPair<WriteIMul64, [SKXPort1,SKXPort5], 4, [1,1], 2>; 129defm : SKXWriteResPair<WriteIMul64Imm, [SKXPort1], 3>; 130defm : SKXWriteResPair<WriteIMul64Reg, [SKXPort1], 3>; 131def : WriteRes<WriteIMulH, []> { let Latency = 3; } 132 133defm : X86WriteRes<WriteBSWAP32, [SKXPort15], 1, [1], 1>; 134defm : X86WriteRes<WriteBSWAP64, [SKXPort06, SKXPort15], 2, [1,1], 2>; 135defm : X86WriteRes<WriteCMPXCHG,[SKXPort06, SKXPort0156], 5, [2,3], 5>; 136defm : X86WriteRes<WriteCMPXCHGRMW,[SKXPort23,SKXPort06,SKXPort0156,SKXPort237,SKXPort4], 8, [1,2,1,1,1], 6>; 137defm : X86WriteRes<WriteXCHG, [SKXPort0156], 2, [3], 3>; 138 139// TODO: Why isn't the SKXDivider used? 140defm : SKXWriteResPair<WriteDiv8, [SKXPort0, SKXDivider], 25, [1,10], 1, 4>; 141defm : X86WriteRes<WriteDiv16, [SKXPort0,SKXPort1,SKXPort5,SKXPort6,SKXPort05,SKXPort0156], 76, [7,2,8,3,1,11], 32>; 142defm : X86WriteRes<WriteDiv32, [SKXPort0,SKXPort1,SKXPort5,SKXPort6,SKXPort05,SKXPort0156], 76, [7,2,8,3,1,11], 32>; 143defm : X86WriteRes<WriteDiv64, [SKXPort0,SKXPort1,SKXPort5,SKXPort6,SKXPort05,SKXPort0156], 76, [7,2,8,3,1,11], 32>; 144defm : X86WriteRes<WriteDiv16Ld, [SKXPort0,SKXPort23,SKXDivider], 29, [1,1,10], 2>; 145defm : X86WriteRes<WriteDiv32Ld, [SKXPort0,SKXPort23,SKXDivider], 29, [1,1,10], 2>; 146defm : X86WriteRes<WriteDiv64Ld, [SKXPort0,SKXPort23,SKXDivider], 29, [1,1,10], 2>; 147 148defm : X86WriteRes<WriteIDiv8, [SKXPort0, SKXDivider], 25, [1,10], 1>; 149defm : X86WriteRes<WriteIDiv16, [SKXPort0,SKXPort1,SKXPort5,SKXPort6,SKXPort06,SKXPort0156], 102, [4,2,4,8,14,34], 66>; 150defm : X86WriteRes<WriteIDiv32, [SKXPort0,SKXPort1,SKXPort5,SKXPort6,SKXPort06,SKXPort0156], 102, [4,2,4,8,14,34], 66>; 151defm : X86WriteRes<WriteIDiv64, [SKXPort0,SKXPort1,SKXPort5,SKXPort6,SKXPort06,SKXPort0156], 102, [4,2,4,8,14,34], 66>; 152defm : X86WriteRes<WriteIDiv8Ld, [SKXPort0,SKXPort5,SKXPort23,SKXPort0156], 28, [2,4,1,1], 8>; 153defm : X86WriteRes<WriteIDiv16Ld, [SKXPort0,SKXPort5,SKXPort23,SKXPort0156], 28, [2,4,1,1], 8>; 154defm : X86WriteRes<WriteIDiv32Ld, [SKXPort0,SKXPort5,SKXPort23,SKXPort0156], 28, [2,4,1,1], 8>; 155defm : X86WriteRes<WriteIDiv64Ld, [SKXPort0,SKXPort5,SKXPort23,SKXPort0156], 28, [2,4,1,1], 8>; 156 157defm : SKXWriteResPair<WriteCRC32, [SKXPort1], 3>; 158 159def : WriteRes<WriteLEA, [SKXPort15]>; // LEA instructions can't fold loads. 160 161defm : SKXWriteResPair<WriteCMOV, [SKXPort06], 1, [1], 1>; // Conditional move. 162defm : X86WriteRes<WriteFCMOV, [SKXPort1], 3, [1], 1>; // x87 conditional move. 163def : WriteRes<WriteSETCC, [SKXPort06]>; // Setcc. 164def : WriteRes<WriteSETCCStore, [SKXPort06,SKXPort4,SKXPort237]> { 165 let Latency = 2; 166 let NumMicroOps = 3; 167} 168defm : X86WriteRes<WriteLAHFSAHF, [SKXPort06], 1, [1], 1>; 169defm : X86WriteRes<WriteBitTest, [SKXPort06], 1, [1], 1>; 170defm : X86WriteRes<WriteBitTestImmLd, [SKXPort06,SKXPort23], 6, [1,1], 2>; 171defm : X86WriteRes<WriteBitTestRegLd, [SKXPort0156,SKXPort23], 6, [1,1], 2>; 172defm : X86WriteRes<WriteBitTestSet, [SKXPort06], 1, [1], 1>; 173defm : X86WriteRes<WriteBitTestSetImmLd, [SKXPort06,SKXPort23], 5, [1,1], 3>; 174defm : X86WriteRes<WriteBitTestSetRegLd, [SKXPort0156,SKXPort23], 5, [1,1], 2>; 175 176// Integer shifts and rotates. 177defm : SKXWriteResPair<WriteShift, [SKXPort06], 1>; 178defm : SKXWriteResPair<WriteShiftCL, [SKXPort06], 3, [3], 3>; 179defm : SKXWriteResPair<WriteRotate, [SKXPort06], 1, [1], 1>; 180defm : SKXWriteResPair<WriteRotateCL, [SKXPort06], 3, [3], 3>; 181 182// SHLD/SHRD. 183defm : X86WriteRes<WriteSHDrri, [SKXPort1], 3, [1], 1>; 184defm : X86WriteRes<WriteSHDrrcl,[SKXPort1,SKXPort06,SKXPort0156], 6, [1, 2, 1], 4>; 185defm : X86WriteRes<WriteSHDmri, [SKXPort1,SKXPort23,SKXPort237,SKXPort0156], 9, [1, 1, 1, 1], 4>; 186defm : X86WriteRes<WriteSHDmrcl,[SKXPort1,SKXPort23,SKXPort237,SKXPort06,SKXPort0156], 11, [1, 1, 1, 2, 1], 6>; 187 188// Bit counts. 189defm : SKXWriteResPair<WriteBSF, [SKXPort1], 3>; 190defm : SKXWriteResPair<WriteBSR, [SKXPort1], 3>; 191defm : SKXWriteResPair<WriteLZCNT, [SKXPort1], 3>; 192defm : SKXWriteResPair<WriteTZCNT, [SKXPort1], 3>; 193defm : SKXWriteResPair<WritePOPCNT, [SKXPort1], 3>; 194 195// BMI1 BEXTR/BLS, BMI2 BZHI 196defm : SKXWriteResPair<WriteBEXTR, [SKXPort06,SKXPort15], 2, [1,1], 2>; 197defm : SKXWriteResPair<WriteBLS, [SKXPort15], 1>; 198defm : SKXWriteResPair<WriteBZHI, [SKXPort15], 1>; 199 200// Loads, stores, and moves, not folded with other operations. 201defm : X86WriteRes<WriteLoad, [SKXPort23], 5, [1], 1>; 202defm : X86WriteRes<WriteStore, [SKXPort237, SKXPort4], 1, [1,1], 1>; 203defm : X86WriteRes<WriteStoreNT, [SKXPort237, SKXPort4], 1, [1,1], 2>; 204defm : X86WriteRes<WriteMove, [SKXPort0156], 1, [1], 1>; 205 206// Model the effect of clobbering the read-write mask operand of the GATHER operation. 207// Does not cost anything by itself, only has latency, matching that of the WriteLoad, 208defm : X86WriteRes<WriteVecMaskedGatherWriteback, [], 5, [], 0>; 209 210// Idioms that clear a register, like xorps %xmm0, %xmm0. 211// These can often bypass execution ports completely. 212def : WriteRes<WriteZero, []>; 213 214// Branches don't produce values, so they have no latency, but they still 215// consume resources. Indirect branches can fold loads. 216defm : SKXWriteResPair<WriteJump, [SKXPort06], 1>; 217 218// Floating point. This covers both scalar and vector operations. 219defm : X86WriteRes<WriteFLD0, [SKXPort05], 1, [1], 1>; 220defm : X86WriteRes<WriteFLD1, [SKXPort05], 1, [2], 2>; 221defm : X86WriteRes<WriteFLDC, [SKXPort05], 1, [2], 2>; 222defm : X86WriteRes<WriteFLoad, [SKXPort23], 5, [1], 1>; 223defm : X86WriteRes<WriteFLoadX, [SKXPort23], 6, [1], 1>; 224defm : X86WriteRes<WriteFLoadY, [SKXPort23], 7, [1], 1>; 225defm : X86WriteRes<WriteFMaskedLoad, [SKXPort23,SKXPort015], 7, [1,1], 2>; 226defm : X86WriteRes<WriteFMaskedLoadY, [SKXPort23,SKXPort015], 8, [1,1], 2>; 227defm : X86WriteRes<WriteFStore, [SKXPort237,SKXPort4], 1, [1,1], 2>; 228defm : X86WriteRes<WriteFStoreX, [SKXPort237,SKXPort4], 1, [1,1], 2>; 229defm : X86WriteRes<WriteFStoreY, [SKXPort237,SKXPort4], 1, [1,1], 2>; 230defm : X86WriteRes<WriteFStoreNT, [SKXPort237,SKXPort4], 1, [1,1], 2>; 231defm : X86WriteRes<WriteFStoreNTX, [SKXPort237,SKXPort4], 1, [1,1], 2>; 232defm : X86WriteRes<WriteFStoreNTY, [SKXPort237,SKXPort4], 1, [1,1], 2>; 233 234defm : X86WriteRes<WriteFMaskedStore32, [SKXPort237,SKXPort0], 2, [1,1], 2>; 235defm : X86WriteRes<WriteFMaskedStore32Y, [SKXPort237,SKXPort0], 2, [1,1], 2>; 236defm : X86WriteRes<WriteFMaskedStore64, [SKXPort237,SKXPort0], 2, [1,1], 2>; 237defm : X86WriteRes<WriteFMaskedStore64Y, [SKXPort237,SKXPort0], 2, [1,1], 2>; 238 239defm : X86WriteRes<WriteFMove, [SKXPort015], 1, [1], 1>; 240defm : X86WriteRes<WriteFMoveX, [SKXPort015], 1, [1], 1>; 241defm : X86WriteRes<WriteFMoveY, [SKXPort015], 1, [1], 1>; 242defm : X86WriteRes<WriteEMMS, [SKXPort05,SKXPort0156], 10, [9,1], 10>; 243 244defm : SKXWriteResPair<WriteFAdd, [SKXPort01], 4, [1], 1, 5>; // Floating point add/sub. 245defm : SKXWriteResPair<WriteFAddX, [SKXPort01], 4, [1], 1, 6>; 246defm : SKXWriteResPair<WriteFAddY, [SKXPort01], 4, [1], 1, 7>; 247defm : SKXWriteResPair<WriteFAddZ, [SKXPort05], 4, [1], 1, 7>; 248defm : SKXWriteResPair<WriteFAdd64, [SKXPort01], 4, [1], 1, 5>; // Floating point double add/sub. 249defm : SKXWriteResPair<WriteFAdd64X, [SKXPort01], 4, [1], 1, 6>; 250defm : SKXWriteResPair<WriteFAdd64Y, [SKXPort01], 4, [1], 1, 7>; 251defm : SKXWriteResPair<WriteFAdd64Z, [SKXPort05], 4, [1], 1, 7>; 252 253defm : SKXWriteResPair<WriteFCmp, [SKXPort01], 4, [1], 1, 5>; // Floating point compare. 254defm : SKXWriteResPair<WriteFCmpX, [SKXPort01], 4, [1], 1, 6>; 255defm : SKXWriteResPair<WriteFCmpY, [SKXPort01], 4, [1], 1, 7>; 256defm : SKXWriteResPair<WriteFCmpZ, [SKXPort05], 4, [1], 1, 7>; 257defm : SKXWriteResPair<WriteFCmp64, [SKXPort01], 4, [1], 1, 5>; // Floating point double compare. 258defm : SKXWriteResPair<WriteFCmp64X, [SKXPort01], 4, [1], 1, 6>; 259defm : SKXWriteResPair<WriteFCmp64Y, [SKXPort01], 4, [1], 1, 7>; 260defm : SKXWriteResPair<WriteFCmp64Z, [SKXPort05], 4, [1], 1, 7>; 261 262defm : SKXWriteResPair<WriteFCom, [SKXPort0], 2>; // Floating point compare to flags (X87). 263defm : SKXWriteResPair<WriteFComX, [SKXPort0], 2>; // Floating point compare to flags (SSE). 264 265defm : SKXWriteResPair<WriteFMul, [SKXPort01], 4, [1], 1, 5>; // Floating point multiplication. 266defm : SKXWriteResPair<WriteFMulX, [SKXPort01], 4, [1], 1, 6>; 267defm : SKXWriteResPair<WriteFMulY, [SKXPort01], 4, [1], 1, 7>; 268defm : SKXWriteResPair<WriteFMulZ, [SKXPort05], 4, [1], 1, 7>; 269defm : SKXWriteResPair<WriteFMul64, [SKXPort01], 4, [1], 1, 5>; // Floating point double multiplication. 270defm : SKXWriteResPair<WriteFMul64X, [SKXPort01], 4, [1], 1, 6>; 271defm : SKXWriteResPair<WriteFMul64Y, [SKXPort01], 4, [1], 1, 7>; 272defm : SKXWriteResPair<WriteFMul64Z, [SKXPort05], 4, [1], 1, 7>; 273 274defm : SKXWriteResPair<WriteFDiv, [SKXPort0,SKXFPDivider], 11, [1,3], 1, 5>; // 10-14 cycles. // Floating point division. 275//defm : SKXWriteResPair<WriteFDivX, [SKXPort0,SKXFPDivider], 11, [1,3], 1, 6>; // 10-14 cycles. 276defm : SKXWriteResPair<WriteFDivY, [SKXPort0,SKXFPDivider], 11, [1,5], 1, 7>; // 10-14 cycles. 277defm : SKXWriteResPair<WriteFDivZ, [SKXPort0,SKXPort5,SKXFPDivider], 18, [2,1,10], 3, 7>; // 10-14 cycles. 278//defm : SKXWriteResPair<WriteFDiv64, [SKXPort0,SKXFPDivider], 14, [1,3], 1, 5>; // 10-14 cycles. // Floating point division. 279//defm : SKXWriteResPair<WriteFDiv64X, [SKXPort0,SKXFPDivider], 14, [1,3], 1, 6>; // 10-14 cycles. 280//defm : SKXWriteResPair<WriteFDiv64Y, [SKXPort0,SKXFPDivider], 14, [1,5], 1, 7>; // 10-14 cycles. 281defm : SKXWriteResPair<WriteFDiv64Z, [SKXPort0,SKXPort5,SKXFPDivider], 23, [2,1,16], 3, 7>; // 10-14 cycles. 282 283defm : SKXWriteResPair<WriteFSqrt, [SKXPort0,SKXFPDivider], 12, [1,3], 1, 5>; // Floating point square root. 284defm : SKXWriteResPair<WriteFSqrtX, [SKXPort0,SKXFPDivider], 12, [1,3], 1, 6>; 285defm : SKXWriteResPair<WriteFSqrtY, [SKXPort0,SKXFPDivider], 12, [1,6], 1, 7>; 286defm : SKXWriteResPair<WriteFSqrtZ, [SKXPort0,SKXPort5,SKXFPDivider], 20, [2,1,12], 3, 7>; 287defm : SKXWriteResPair<WriteFSqrt64, [SKXPort0,SKXFPDivider], 18, [1,6], 1, 5>; // Floating point double square root. 288defm : SKXWriteResPair<WriteFSqrt64X, [SKXPort0,SKXFPDivider], 18, [1,6], 1, 6>; 289defm : SKXWriteResPair<WriteFSqrt64Y, [SKXPort0,SKXFPDivider], 18, [1,12],1, 7>; 290defm : SKXWriteResPair<WriteFSqrt64Z, [SKXPort0,SKXPort5,SKXFPDivider], 32, [2,1,24], 3, 7>; 291defm : SKXWriteResPair<WriteFSqrt80, [SKXPort0,SKXFPDivider], 21, [1,7]>; // Floating point long double square root. 292 293defm : SKXWriteResPair<WriteFRcp, [SKXPort0], 4, [1], 1, 5>; // Floating point reciprocal estimate. 294defm : SKXWriteResPair<WriteFRcpX, [SKXPort0], 4, [1], 1, 6>; 295defm : SKXWriteResPair<WriteFRcpY, [SKXPort0], 4, [1], 1, 7>; 296defm : SKXWriteResPair<WriteFRcpZ, [SKXPort0,SKXPort5], 4, [2,1], 3, 7>; 297 298defm : SKXWriteResPair<WriteFRsqrt, [SKXPort0], 4, [1], 1, 5>; // Floating point reciprocal square root estimate. 299defm : SKXWriteResPair<WriteFRsqrtX,[SKXPort0], 4, [1], 1, 6>; 300defm : SKXWriteResPair<WriteFRsqrtY,[SKXPort0], 4, [1], 1, 7>; 301defm : SKXWriteResPair<WriteFRsqrtZ,[SKXPort0,SKXPort5], 9, [2,1], 3, 7>; 302 303defm : SKXWriteResPair<WriteFMA, [SKXPort01], 4, [1], 1, 5>; // Fused Multiply Add. 304defm : SKXWriteResPair<WriteFMAX, [SKXPort01], 4, [1], 1, 6>; 305defm : SKXWriteResPair<WriteFMAY, [SKXPort01], 4, [1], 1, 7>; 306defm : SKXWriteResPair<WriteFMAZ, [SKXPort05], 4, [1], 1, 7>; 307defm : SKXWriteResPair<WriteDPPD, [SKXPort5,SKXPort015], 9, [1,2], 3, 6>; // Floating point double dot product. 308defm : SKXWriteResPair<WriteDPPS, [SKXPort5,SKXPort015], 13, [1,3], 4, 6>; 309defm : SKXWriteResPair<WriteDPPSY,[SKXPort5,SKXPort015], 13, [1,3], 4, 7>; 310defm : SKXWriteResPair<WriteDPPSZ,[SKXPort5,SKXPort015], 13, [1,3], 4, 7>; 311defm : SKXWriteResPair<WriteFSign, [SKXPort0], 1>; // Floating point fabs/fchs. 312defm : SKXWriteResPair<WriteFRnd, [SKXPort01], 8, [2], 2, 6>; // Floating point rounding. 313defm : SKXWriteResPair<WriteFRndY, [SKXPort01], 8, [2], 2, 7>; 314defm : SKXWriteResPair<WriteFRndZ, [SKXPort05], 8, [2], 2, 7>; 315defm : SKXWriteResPair<WriteFLogic, [SKXPort015], 1, [1], 1, 6>; // Floating point and/or/xor logicals. 316defm : SKXWriteResPair<WriteFLogicY, [SKXPort015], 1, [1], 1, 7>; 317defm : SKXWriteResPair<WriteFLogicZ, [SKXPort05], 1, [1], 1, 7>; 318defm : SKXWriteResPair<WriteFTest, [SKXPort0], 2, [1], 1, 6>; // Floating point TEST instructions. 319defm : SKXWriteResPair<WriteFTestY, [SKXPort0], 2, [1], 1, 7>; 320defm : SKXWriteResPair<WriteFTestZ, [SKXPort0], 2, [1], 1, 7>; 321defm : SKXWriteResPair<WriteFShuffle, [SKXPort5], 1, [1], 1, 6>; // Floating point vector shuffles. 322defm : SKXWriteResPair<WriteFShuffleY, [SKXPort5], 1, [1], 1, 7>; 323defm : SKXWriteResPair<WriteFShuffleZ, [SKXPort5], 1, [1], 1, 7>; 324defm : SKXWriteResPair<WriteFVarShuffle, [SKXPort5], 1, [1], 1, 6>; // Floating point vector variable shuffles. 325defm : SKXWriteResPair<WriteFVarShuffleY, [SKXPort5], 1, [1], 1, 7>; 326defm : SKXWriteResPair<WriteFVarShuffleZ, [SKXPort5], 1, [1], 1, 7>; 327defm : SKXWriteResPair<WriteFBlend, [SKXPort015], 1, [1], 1, 6>; // Floating point vector blends. 328defm : SKXWriteResPair<WriteFBlendY,[SKXPort015], 1, [1], 1, 7>; 329defm : SKXWriteResPair<WriteFBlendZ,[SKXPort015], 1, [1], 1, 7>; 330defm : SKXWriteResPair<WriteFVarBlend, [SKXPort015], 2, [2], 2, 6>; // Fp vector variable blends. 331defm : SKXWriteResPair<WriteFVarBlendY,[SKXPort015], 2, [2], 2, 7>; 332defm : SKXWriteResPair<WriteFVarBlendZ,[SKXPort015], 2, [2], 2, 7>; 333 334// FMA Scheduling helper class. 335// class FMASC { X86FoldableSchedWrite Sched = WriteFAdd; } 336 337// Vector integer operations. 338defm : X86WriteRes<WriteVecLoad, [SKXPort23], 5, [1], 1>; 339defm : X86WriteRes<WriteVecLoadX, [SKXPort23], 6, [1], 1>; 340defm : X86WriteRes<WriteVecLoadY, [SKXPort23], 7, [1], 1>; 341defm : X86WriteRes<WriteVecLoadNT, [SKXPort23], 6, [1], 1>; 342defm : X86WriteRes<WriteVecLoadNTY, [SKXPort23], 7, [1], 1>; 343defm : X86WriteRes<WriteVecMaskedLoad, [SKXPort23,SKXPort015], 7, [1,1], 2>; 344defm : X86WriteRes<WriteVecMaskedLoadY, [SKXPort23,SKXPort015], 8, [1,1], 2>; 345defm : X86WriteRes<WriteVecStore, [SKXPort237,SKXPort4], 1, [1,1], 2>; 346defm : X86WriteRes<WriteVecStoreX, [SKXPort237,SKXPort4], 1, [1,1], 2>; 347defm : X86WriteRes<WriteVecStoreY, [SKXPort237,SKXPort4], 1, [1,1], 2>; 348defm : X86WriteRes<WriteVecStoreNT, [SKXPort237,SKXPort4], 1, [1,1], 2>; 349defm : X86WriteRes<WriteVecStoreNTY, [SKXPort237,SKXPort4], 1, [1,1], 2>; 350defm : X86WriteRes<WriteVecMaskedStore32, [SKXPort237,SKXPort0], 2, [1,1], 2>; 351defm : X86WriteRes<WriteVecMaskedStore32Y, [SKXPort237,SKXPort0], 2, [1,1], 2>; 352defm : X86WriteRes<WriteVecMaskedStore64, [SKXPort237,SKXPort0], 2, [1,1], 2>; 353defm : X86WriteRes<WriteVecMaskedStore64Y, [SKXPort237,SKXPort0], 2, [1,1], 2>; 354defm : X86WriteRes<WriteVecMove, [SKXPort05], 1, [1], 1>; 355defm : X86WriteRes<WriteVecMoveX, [SKXPort015], 1, [1], 1>; 356defm : X86WriteRes<WriteVecMoveY, [SKXPort015], 1, [1], 1>; 357defm : X86WriteRes<WriteVecMoveToGpr, [SKXPort0], 2, [1], 1>; 358defm : X86WriteRes<WriteVecMoveFromGpr, [SKXPort5], 1, [1], 1>; 359 360defm : SKXWriteResPair<WriteVecALU, [SKXPort05], 1, [1], 1, 5>; // Vector integer ALU op, no logicals. 361defm : SKXWriteResPair<WriteVecALUX, [SKXPort01], 1, [1], 1, 6>; 362defm : SKXWriteResPair<WriteVecALUY, [SKXPort01], 1, [1], 1, 7>; 363defm : SKXWriteResPair<WriteVecALUZ, [SKXPort0], 1, [1], 1, 7>; 364defm : SKXWriteResPair<WriteVecLogic, [SKXPort05], 1, [1], 1, 5>; // Vector integer and/or/xor. 365defm : SKXWriteResPair<WriteVecLogicX,[SKXPort015], 1, [1], 1, 6>; 366defm : SKXWriteResPair<WriteVecLogicY,[SKXPort015], 1, [1], 1, 7>; 367defm : SKXWriteResPair<WriteVecLogicZ,[SKXPort05], 1, [1], 1, 7>; 368defm : SKXWriteResPair<WriteVecTest, [SKXPort0,SKXPort5], 3, [1,1], 2, 6>; // Vector integer TEST instructions. 369defm : SKXWriteResPair<WriteVecTestY, [SKXPort0,SKXPort5], 3, [1,1], 2, 7>; 370defm : SKXWriteResPair<WriteVecTestZ, [SKXPort0,SKXPort5], 3, [1,1], 2, 7>; 371defm : SKXWriteResPair<WriteVecIMul, [SKXPort0], 5, [1], 1, 5>; // Vector integer multiply. 372defm : SKXWriteResPair<WriteVecIMulX, [SKXPort01], 5, [1], 1, 6>; 373defm : SKXWriteResPair<WriteVecIMulY, [SKXPort01], 5, [1], 1, 7>; 374defm : SKXWriteResPair<WriteVecIMulZ, [SKXPort05], 5, [1], 1, 7>; 375defm : SKXWriteResPair<WritePMULLD, [SKXPort01], 10, [2], 2, 6>; // Vector PMULLD. 376defm : SKXWriteResPair<WritePMULLDY, [SKXPort01], 10, [2], 2, 7>; 377defm : SKXWriteResPair<WritePMULLDZ, [SKXPort05], 10, [2], 2, 7>; 378defm : SKXWriteResPair<WriteShuffle, [SKXPort5], 1, [1], 1, 5>; // Vector shuffles. 379defm : SKXWriteResPair<WriteShuffleX, [SKXPort5], 1, [1], 1, 6>; 380defm : SKXWriteResPair<WriteShuffleY, [SKXPort5], 1, [1], 1, 7>; 381defm : SKXWriteResPair<WriteShuffleZ, [SKXPort5], 1, [1], 1, 7>; 382defm : SKXWriteResPair<WriteVarShuffle, [SKXPort5], 1, [1], 1, 5>; // Vector variable shuffles. 383defm : SKXWriteResPair<WriteVarShuffleX, [SKXPort5], 1, [1], 1, 6>; 384defm : SKXWriteResPair<WriteVarShuffleY, [SKXPort5], 1, [1], 1, 7>; 385defm : SKXWriteResPair<WriteVarShuffleZ, [SKXPort5], 1, [1], 1, 7>; 386defm : SKXWriteResPair<WriteBlend, [SKXPort5], 1, [1], 1, 6>; // Vector blends. 387defm : SKXWriteResPair<WriteBlendY,[SKXPort5], 1, [1], 1, 7>; 388defm : SKXWriteResPair<WriteBlendZ,[SKXPort5], 1, [1], 1, 7>; 389defm : SKXWriteResPair<WriteVarBlend, [SKXPort015], 2, [2], 2, 6>; // Vector variable blends. 390defm : SKXWriteResPair<WriteVarBlendY,[SKXPort015], 2, [2], 2, 6>; 391defm : SKXWriteResPair<WriteVarBlendZ,[SKXPort05], 2, [1], 1, 6>; 392defm : SKXWriteResPair<WriteMPSAD, [SKXPort5], 4, [2], 2, 6>; // Vector MPSAD. 393defm : SKXWriteResPair<WriteMPSADY, [SKXPort5], 4, [2], 2, 7>; 394defm : SKXWriteResPair<WriteMPSADZ, [SKXPort5], 4, [2], 2, 7>; 395defm : SKXWriteResPair<WritePSADBW, [SKXPort5], 3, [1], 1, 5>; // Vector PSADBW. 396defm : SKXWriteResPair<WritePSADBWX, [SKXPort5], 3, [1], 1, 6>; 397defm : SKXWriteResPair<WritePSADBWY, [SKXPort5], 3, [1], 1, 7>; 398defm : SKXWriteResPair<WritePSADBWZ, [SKXPort5], 3, [1], 1, 7>; 399defm : SKXWriteResPair<WritePHMINPOS, [SKXPort0], 4, [1], 1, 6>; // Vector PHMINPOS. 400 401// Vector integer shifts. 402defm : SKXWriteResPair<WriteVecShift, [SKXPort0], 1, [1], 1, 5>; 403defm : X86WriteRes<WriteVecShiftX, [SKXPort5,SKXPort01], 2, [1,1], 2>; 404defm : X86WriteRes<WriteVecShiftY, [SKXPort5,SKXPort01], 4, [1,1], 2>; 405defm : X86WriteRes<WriteVecShiftZ, [SKXPort5,SKXPort0], 4, [1,1], 2>; 406defm : X86WriteRes<WriteVecShiftXLd, [SKXPort01,SKXPort23], 7, [1,1], 2>; 407defm : X86WriteRes<WriteVecShiftYLd, [SKXPort01,SKXPort23], 8, [1,1], 2>; 408defm : X86WriteRes<WriteVecShiftZLd, [SKXPort0,SKXPort23], 8, [1,1], 2>; 409 410defm : SKXWriteResPair<WriteVecShiftImm, [SKXPort0], 1, [1], 1, 5>; 411defm : SKXWriteResPair<WriteVecShiftImmX, [SKXPort01], 1, [1], 1, 6>; // Vector integer immediate shifts. 412defm : SKXWriteResPair<WriteVecShiftImmY, [SKXPort01], 1, [1], 1, 7>; 413defm : SKXWriteResPair<WriteVecShiftImmZ, [SKXPort0], 1, [1], 1, 7>; 414defm : SKXWriteResPair<WriteVarVecShift, [SKXPort01], 1, [1], 1, 6>; // Variable vector shifts. 415defm : SKXWriteResPair<WriteVarVecShiftY, [SKXPort01], 1, [1], 1, 7>; 416defm : SKXWriteResPair<WriteVarVecShiftZ, [SKXPort0], 1, [1], 1, 7>; 417 418// Vector insert/extract operations. 419def : WriteRes<WriteVecInsert, [SKXPort5]> { 420 let Latency = 2; 421 let NumMicroOps = 2; 422 let ResourceCycles = [2]; 423} 424def : WriteRes<WriteVecInsertLd, [SKXPort5,SKXPort23]> { 425 let Latency = 6; 426 let NumMicroOps = 2; 427} 428def: InstRW<[WriteVecInsertLd], (instregex "(V?)MOV(H|L)(PD|PS)rm")>; 429 430def : WriteRes<WriteVecExtract, [SKXPort0,SKXPort5]> { 431 let Latency = 3; 432 let NumMicroOps = 2; 433} 434def : WriteRes<WriteVecExtractSt, [SKXPort4,SKXPort5,SKXPort237]> { 435 let Latency = 2; 436 let NumMicroOps = 3; 437} 438 439// Conversion between integer and float. 440defm : SKXWriteResPair<WriteCvtSS2I, [SKXPort01], 6, [2], 2>; // Needs more work: DD vs DQ. 441defm : SKXWriteResPair<WriteCvtPS2I, [SKXPort01], 3>; 442defm : SKXWriteResPair<WriteCvtPS2IY, [SKXPort01], 3>; 443defm : SKXWriteResPair<WriteCvtPS2IZ, [SKXPort05], 3>; 444defm : SKXWriteResPair<WriteCvtSD2I, [SKXPort01], 6, [2], 2>; 445defm : SKXWriteResPair<WriteCvtPD2I, [SKXPort01], 3>; 446defm : SKXWriteResPair<WriteCvtPD2IY, [SKXPort01], 3>; 447defm : SKXWriteResPair<WriteCvtPD2IZ, [SKXPort05], 3>; 448 449defm : SKXWriteResPair<WriteCvtI2SS, [SKXPort1], 4>; 450defm : SKXWriteResPair<WriteCvtI2PS, [SKXPort01], 4>; 451defm : SKXWriteResPair<WriteCvtI2PSY, [SKXPort01], 4>; 452defm : SKXWriteResPair<WriteCvtI2PSZ, [SKXPort05], 4>; // Needs more work: DD vs DQ. 453defm : SKXWriteResPair<WriteCvtI2SD, [SKXPort1], 4>; 454defm : SKXWriteResPair<WriteCvtI2PD, [SKXPort01], 4>; 455defm : SKXWriteResPair<WriteCvtI2PDY, [SKXPort01], 4>; 456defm : SKXWriteResPair<WriteCvtI2PDZ, [SKXPort05], 4>; 457 458defm : SKXWriteResPair<WriteCvtSS2SD, [SKXPort1], 3>; 459defm : SKXWriteResPair<WriteCvtPS2PD, [SKXPort1], 3>; 460defm : SKXWriteResPair<WriteCvtPS2PDY, [SKXPort5,SKXPort01], 3, [1,1], 2>; 461defm : SKXWriteResPair<WriteCvtPS2PDZ, [SKXPort05], 3, [2], 2>; 462defm : SKXWriteResPair<WriteCvtSD2SS, [SKXPort1], 3>; 463defm : SKXWriteResPair<WriteCvtPD2PS, [SKXPort1], 3>; 464defm : SKXWriteResPair<WriteCvtPD2PSY, [SKXPort5,SKXPort01], 3, [1,1], 2>; 465defm : SKXWriteResPair<WriteCvtPD2PSZ, [SKXPort05], 3, [2], 2>; 466 467defm : X86WriteRes<WriteCvtPH2PS, [SKXPort5,SKXPort01], 5, [1,1], 2>; 468defm : X86WriteRes<WriteCvtPH2PSY, [SKXPort5,SKXPort01], 7, [1,1], 2>; 469defm : X86WriteRes<WriteCvtPH2PSZ, [SKXPort5,SKXPort0], 7, [1,1], 2>; 470defm : X86WriteRes<WriteCvtPH2PSLd, [SKXPort23,SKXPort01], 9, [1,1], 2>; 471defm : X86WriteRes<WriteCvtPH2PSYLd, [SKXPort23,SKXPort01], 10, [1,1], 2>; 472defm : X86WriteRes<WriteCvtPH2PSZLd, [SKXPort23,SKXPort05], 10, [1,1], 2>; 473 474defm : X86WriteRes<WriteCvtPS2PH, [SKXPort5,SKXPort01], 5, [1,1], 2>; 475defm : X86WriteRes<WriteCvtPS2PHY, [SKXPort5,SKXPort01], 7, [1,1], 2>; 476defm : X86WriteRes<WriteCvtPS2PHZ, [SKXPort5,SKXPort05], 7, [1,1], 2>; 477defm : X86WriteRes<WriteCvtPS2PHSt, [SKXPort4,SKXPort5,SKXPort237,SKXPort01], 6, [1,1,1,1], 4>; 478defm : X86WriteRes<WriteCvtPS2PHYSt, [SKXPort4,SKXPort5,SKXPort237,SKXPort01], 8, [1,1,1,1], 4>; 479defm : X86WriteRes<WriteCvtPS2PHZSt, [SKXPort4,SKXPort5,SKXPort237,SKXPort05], 8, [1,1,1,1], 4>; 480 481// Strings instructions. 482 483// Packed Compare Implicit Length Strings, Return Mask 484def : WriteRes<WritePCmpIStrM, [SKXPort0]> { 485 let Latency = 10; 486 let NumMicroOps = 3; 487 let ResourceCycles = [3]; 488} 489def : WriteRes<WritePCmpIStrMLd, [SKXPort0, SKXPort23]> { 490 let Latency = 16; 491 let NumMicroOps = 4; 492 let ResourceCycles = [3,1]; 493} 494 495// Packed Compare Explicit Length Strings, Return Mask 496def : WriteRes<WritePCmpEStrM, [SKXPort0, SKXPort5, SKXPort015, SKXPort0156]> { 497 let Latency = 19; 498 let NumMicroOps = 9; 499 let ResourceCycles = [4,3,1,1]; 500} 501def : WriteRes<WritePCmpEStrMLd, [SKXPort0, SKXPort5, SKXPort23, SKXPort015, SKXPort0156]> { 502 let Latency = 25; 503 let NumMicroOps = 10; 504 let ResourceCycles = [4,3,1,1,1]; 505} 506 507// Packed Compare Implicit Length Strings, Return Index 508def : WriteRes<WritePCmpIStrI, [SKXPort0]> { 509 let Latency = 10; 510 let NumMicroOps = 3; 511 let ResourceCycles = [3]; 512} 513def : WriteRes<WritePCmpIStrILd, [SKXPort0, SKXPort23]> { 514 let Latency = 16; 515 let NumMicroOps = 4; 516 let ResourceCycles = [3,1]; 517} 518 519// Packed Compare Explicit Length Strings, Return Index 520def : WriteRes<WritePCmpEStrI, [SKXPort0,SKXPort5,SKXPort0156]> { 521 let Latency = 18; 522 let NumMicroOps = 8; 523 let ResourceCycles = [4,3,1]; 524} 525def : WriteRes<WritePCmpEStrILd, [SKXPort0, SKXPort5, SKXPort23, SKXPort0156]> { 526 let Latency = 24; 527 let NumMicroOps = 9; 528 let ResourceCycles = [4,3,1,1]; 529} 530 531// MOVMSK Instructions. 532def : WriteRes<WriteFMOVMSK, [SKXPort0]> { let Latency = 2; } 533def : WriteRes<WriteVecMOVMSK, [SKXPort0]> { let Latency = 2; } 534def : WriteRes<WriteVecMOVMSKY, [SKXPort0]> { let Latency = 2; } 535def : WriteRes<WriteMMXMOVMSK, [SKXPort0]> { let Latency = 2; } 536 537// AES instructions. 538def : WriteRes<WriteAESDecEnc, [SKXPort0]> { // Decryption, encryption. 539 let Latency = 4; 540 let NumMicroOps = 1; 541 let ResourceCycles = [1]; 542} 543def : WriteRes<WriteAESDecEncLd, [SKXPort0, SKXPort23]> { 544 let Latency = 10; 545 let NumMicroOps = 2; 546 let ResourceCycles = [1,1]; 547} 548 549def : WriteRes<WriteAESIMC, [SKXPort0]> { // InvMixColumn. 550 let Latency = 8; 551 let NumMicroOps = 2; 552 let ResourceCycles = [2]; 553} 554def : WriteRes<WriteAESIMCLd, [SKXPort0, SKXPort23]> { 555 let Latency = 14; 556 let NumMicroOps = 3; 557 let ResourceCycles = [2,1]; 558} 559 560def : WriteRes<WriteAESKeyGen, [SKXPort0,SKXPort5,SKXPort015]> { // Key Generation. 561 let Latency = 20; 562 let NumMicroOps = 11; 563 let ResourceCycles = [3,6,2]; 564} 565def : WriteRes<WriteAESKeyGenLd, [SKXPort0,SKXPort5,SKXPort23,SKXPort015]> { 566 let Latency = 25; 567 let NumMicroOps = 11; 568 let ResourceCycles = [3,6,1,1]; 569} 570 571// Carry-less multiplication instructions. 572def : WriteRes<WriteCLMul, [SKXPort5]> { 573 let Latency = 6; 574 let NumMicroOps = 1; 575 let ResourceCycles = [1]; 576} 577def : WriteRes<WriteCLMulLd, [SKXPort5, SKXPort23]> { 578 let Latency = 12; 579 let NumMicroOps = 2; 580 let ResourceCycles = [1,1]; 581} 582 583// Catch-all for expensive system instructions. 584def : WriteRes<WriteSystem, [SKXPort0156]> { let Latency = 100; } // def WriteSystem : SchedWrite; 585 586// AVX2. 587defm : SKXWriteResPair<WriteFShuffle256, [SKXPort5], 3, [1], 1, 7>; // Fp 256-bit width vector shuffles. 588defm : SKXWriteResPair<WriteFVarShuffle256, [SKXPort5], 3, [1], 1, 7>; // Fp 256-bit width vector variable shuffles. 589defm : SKXWriteResPair<WriteShuffle256, [SKXPort5], 3, [1], 1, 7>; // 256-bit width vector shuffles. 590defm : SKXWriteResPair<WriteVPMOV256, [SKXPort5], 3, [1], 1, 7>; // 256-bit width packed vector width-changing move. 591defm : SKXWriteResPair<WriteVarShuffle256, [SKXPort5], 3, [1], 1, 7>; // 256-bit width vector variable shuffles. 592 593// Old microcoded instructions that nobody use. 594def : WriteRes<WriteMicrocoded, [SKXPort0156]> { let Latency = 100; } // def WriteMicrocoded : SchedWrite; 595 596// Fence instructions. 597def : WriteRes<WriteFence, [SKXPort23, SKXPort4]>; 598 599// Load/store MXCSR. 600def : WriteRes<WriteLDMXCSR, [SKXPort0,SKXPort23,SKXPort0156]> { let Latency = 7; let NumMicroOps = 3; let ResourceCycles = [1,1,1]; } 601def : WriteRes<WriteSTMXCSR, [SKXPort4,SKXPort5,SKXPort237]> { let Latency = 2; let NumMicroOps = 3; let ResourceCycles = [1,1,1]; } 602 603// Nop, not very useful expect it provides a model for nops! 604def : WriteRes<WriteNop, []>; 605 606//////////////////////////////////////////////////////////////////////////////// 607// Horizontal add/sub instructions. 608//////////////////////////////////////////////////////////////////////////////// 609 610defm : SKXWriteResPair<WriteFHAdd, [SKXPort5,SKXPort015], 6, [2,1], 3, 6>; 611defm : SKXWriteResPair<WriteFHAddY, [SKXPort5,SKXPort015], 6, [2,1], 3, 7>; 612defm : SKXWriteResPair<WritePHAdd, [SKXPort5,SKXPort05], 3, [2,1], 3, 5>; 613defm : SKXWriteResPair<WritePHAddX, [SKXPort5,SKXPort015], 3, [2,1], 3, 6>; 614defm : SKXWriteResPair<WritePHAddY, [SKXPort5,SKXPort015], 3, [2,1], 3, 7>; 615 616// Remaining instrs. 617 618def SKXWriteResGroup1 : SchedWriteRes<[SKXPort0]> { 619 let Latency = 1; 620 let NumMicroOps = 1; 621 let ResourceCycles = [1]; 622} 623def: InstRW<[SKXWriteResGroup1], (instregex "KAND(B|D|Q|W)rr", 624 "KANDN(B|D|Q|W)rr", 625 "KMOV(B|D|Q|W)kk", 626 "KNOT(B|D|Q|W)rr", 627 "KOR(B|D|Q|W)rr", 628 "KXNOR(B|D|Q|W)rr", 629 "KXOR(B|D|Q|W)rr", 630 "KSET0(B|D|Q|W)", // Same as KXOR 631 "KSET1(B|D|Q|W)", // Same as KXNOR 632 "MMX_PADDS(B|W)irr", 633 "MMX_PADDUS(B|W)irr", 634 "MMX_PAVG(B|W)irr", 635 "MMX_PCMPEQ(B|D|W)irr", 636 "MMX_PCMPGT(B|D|W)irr", 637 "MMX_P(MAX|MIN)SWirr", 638 "MMX_P(MAX|MIN)UBirr", 639 "MMX_PSUBS(B|W)irr", 640 "MMX_PSUBUS(B|W)irr", 641 "VPMOVB2M(Z|Z128|Z256)rr", 642 "VPMOVD2M(Z|Z128|Z256)rr", 643 "VPMOVQ2M(Z|Z128|Z256)rr", 644 "VPMOVW2M(Z|Z128|Z256)rr")>; 645 646def SKXWriteResGroup3 : SchedWriteRes<[SKXPort5]> { 647 let Latency = 1; 648 let NumMicroOps = 1; 649 let ResourceCycles = [1]; 650} 651def: InstRW<[SKXWriteResGroup3], (instregex "COM(P?)_FST0r", 652 "KMOV(B|D|Q|W)kr", 653 "UCOM_F(P?)r")>; 654 655def SKXWriteResGroup4 : SchedWriteRes<[SKXPort6]> { 656 let Latency = 1; 657 let NumMicroOps = 1; 658 let ResourceCycles = [1]; 659} 660def: InstRW<[SKXWriteResGroup4], (instregex "JMP(16|32|64)r")>; 661 662def SKXWriteResGroup6 : SchedWriteRes<[SKXPort05]> { 663 let Latency = 1; 664 let NumMicroOps = 1; 665 let ResourceCycles = [1]; 666} 667def: InstRW<[SKXWriteResGroup6], (instrs FINCSTP, FNOP)>; 668 669def SKXWriteResGroup7 : SchedWriteRes<[SKXPort06]> { 670 let Latency = 1; 671 let NumMicroOps = 1; 672 let ResourceCycles = [1]; 673} 674def: InstRW<[SKXWriteResGroup7], (instrs CDQ, CQO, CLAC, STAC)>; 675 676def SKXWriteResGroup8 : SchedWriteRes<[SKXPort15]> { 677 let Latency = 1; 678 let NumMicroOps = 1; 679 let ResourceCycles = [1]; 680} 681def: InstRW<[SKXWriteResGroup8], (instregex "ANDN(32|64)rr")>; 682 683def SKXWriteResGroup9 : SchedWriteRes<[SKXPort015]> { 684 let Latency = 1; 685 let NumMicroOps = 1; 686 let ResourceCycles = [1]; 687} 688def: InstRW<[SKXWriteResGroup9], (instregex "VBLENDMPD(Z128|Z256)rr", 689 "VBLENDMPS(Z128|Z256)rr", 690 "VPADD(B|D|Q|W)(Y|Z|Z128|Z256)rr", 691 "(V?)PADD(B|D|Q|W)rr", 692 "VPBLENDD(Y?)rri", 693 "VPBLENDMB(Z128|Z256)rr", 694 "VPBLENDMD(Z128|Z256)rr", 695 "VPBLENDMQ(Z128|Z256)rr", 696 "VPBLENDMW(Z128|Z256)rr", 697 "VPSUB(B|D|Q|W)(Y|Z|Z128|Z256)rrk", 698 "VPTERNLOGD(Z|Z128|Z256)rri", 699 "VPTERNLOGQ(Z|Z128|Z256)rri")>; 700 701def SKXWriteResGroup10 : SchedWriteRes<[SKXPort0156]> { 702 let Latency = 1; 703 let NumMicroOps = 1; 704 let ResourceCycles = [1]; 705} 706def: InstRW<[SKXWriteResGroup10], (instrs CBW, CWDE, CDQE, 707 CMC, STC, 708 SGDT64m, 709 SIDT64m, 710 SMSW16m, 711 STRm, 712 SYSCALL)>; 713 714def SKXWriteResGroup11 : SchedWriteRes<[SKXPort4,SKXPort237]> { 715 let Latency = 1; 716 let NumMicroOps = 2; 717 let ResourceCycles = [1,1]; 718} 719def: InstRW<[SKXWriteResGroup11], (instrs FBSTPm, VMPTRSTm)>; 720def: InstRW<[SKXWriteResGroup11], (instregex "KMOV(B|D|Q|W)mk", 721 "ST_FP(32|64|80)m")>; 722 723def SKXWriteResGroup13 : SchedWriteRes<[SKXPort5]> { 724 let Latency = 2; 725 let NumMicroOps = 2; 726 let ResourceCycles = [2]; 727} 728def: InstRW<[SKXWriteResGroup13], (instrs MMX_MOVQ2DQrr)>; 729 730def SKXWriteResGroup14 : SchedWriteRes<[SKXPort05]> { 731 let Latency = 2; 732 let NumMicroOps = 2; 733 let ResourceCycles = [2]; 734} 735def: InstRW<[SKXWriteResGroup14], (instrs FDECSTP, 736 MMX_MOVDQ2Qrr)>; 737 738def SKXWriteResGroup17 : SchedWriteRes<[SKXPort0156]> { 739 let Latency = 2; 740 let NumMicroOps = 2; 741 let ResourceCycles = [2]; 742} 743def: InstRW<[SKXWriteResGroup17], (instrs LFENCE, 744 WAIT, 745 XGETBV)>; 746 747def SKXWriteResGroup20 : SchedWriteRes<[SKXPort6,SKXPort0156]> { 748 let Latency = 2; 749 let NumMicroOps = 2; 750 let ResourceCycles = [1,1]; 751} 752def: InstRW<[SKXWriteResGroup20], (instregex "CLFLUSH")>; 753 754def SKXWriteResGroup21 : SchedWriteRes<[SKXPort237,SKXPort0156]> { 755 let Latency = 2; 756 let NumMicroOps = 2; 757 let ResourceCycles = [1,1]; 758} 759def: InstRW<[SKXWriteResGroup21], (instrs SFENCE)>; 760 761def SKXWriteResGroup23 : SchedWriteRes<[SKXPort06,SKXPort0156]> { 762 let Latency = 2; 763 let NumMicroOps = 2; 764 let ResourceCycles = [1,1]; 765} 766def: InstRW<[SKXWriteResGroup23], (instrs CWD, 767 JCXZ, JECXZ, JRCXZ, 768 ADC8i8, SBB8i8, 769 ADC16i16, SBB16i16, 770 ADC32i32, SBB32i32, 771 ADC64i32, SBB64i32)>; 772 773def SKXWriteResGroup25 : SchedWriteRes<[SKXPort4,SKXPort6,SKXPort237]> { 774 let Latency = 2; 775 let NumMicroOps = 3; 776 let ResourceCycles = [1,1,1]; 777} 778def: InstRW<[SKXWriteResGroup25], (instrs FNSTCW16m)>; 779 780def SKXWriteResGroup27 : SchedWriteRes<[SKXPort4,SKXPort237,SKXPort15]> { 781 let Latency = 2; 782 let NumMicroOps = 3; 783 let ResourceCycles = [1,1,1]; 784} 785def: InstRW<[SKXWriteResGroup27], (instregex "MOVBE(16|32|64)mr")>; 786 787def SKXWriteResGroup28 : SchedWriteRes<[SKXPort4,SKXPort237,SKXPort0156]> { 788 let Latency = 2; 789 let NumMicroOps = 3; 790 let ResourceCycles = [1,1,1]; 791} 792def: InstRW<[SKXWriteResGroup28], (instrs PUSH16r, PUSH32r, PUSH64r, PUSH64i8, 793 STOSB, STOSL, STOSQ, STOSW)>; 794def: InstRW<[SKXWriteResGroup28], (instregex "PUSH(16|32|64)rmr")>; 795 796def SKXWriteResGroup29 : SchedWriteRes<[SKXPort4,SKXPort237,SKXPort15]> { 797 let Latency = 2; 798 let NumMicroOps = 5; 799 let ResourceCycles = [2,2,1]; 800} 801def: InstRW<[SKXWriteResGroup29], (instregex "VMOVDQU8Zmr(b?)")>; 802 803def SKXWriteResGroup30 : SchedWriteRes<[SKXPort0]> { 804 let Latency = 3; 805 let NumMicroOps = 1; 806 let ResourceCycles = [1]; 807} 808def: InstRW<[SKXWriteResGroup30], (instregex "KMOV(B|D|Q|W)rk", 809 "KORTEST(B|D|Q|W)rr", 810 "KTEST(B|D|Q|W)rr")>; 811 812def SKXWriteResGroup31 : SchedWriteRes<[SKXPort1]> { 813 let Latency = 3; 814 let NumMicroOps = 1; 815 let ResourceCycles = [1]; 816} 817def: InstRW<[SKXWriteResGroup31], (instregex "PDEP(32|64)rr", 818 "PEXT(32|64)rr")>; 819 820def SKXWriteResGroup32 : SchedWriteRes<[SKXPort5]> { 821 let Latency = 3; 822 let NumMicroOps = 1; 823 let ResourceCycles = [1]; 824} 825def: InstRW<[SKXWriteResGroup32], (instrs VPSADBWZrr)>; // TODO: 512-bit ops require ports 0/1 to be joined. 826def: InstRW<[SKXWriteResGroup32], (instregex "(ADD|SUB|SUBR)_(FPrST0|FST0r|FrST0)", 827 "VALIGND(Z|Z128|Z256)rri", 828 "VALIGNQ(Z|Z128|Z256)rri", 829 "VDBPSADBWZrri", // TODO: 512-bit ops require ports 0/1 to be joined. 830 "VPBROADCAST(B|W)rr", 831 "VP(MAX|MIN)(S|U)Q(Z|Z128|Z256)rr")>; 832 833def SKXWriteResGroup33 : SchedWriteRes<[SKXPort5]> { 834 let Latency = 4; 835 let NumMicroOps = 1; 836 let ResourceCycles = [1]; 837} 838def: InstRW<[SKXWriteResGroup33], (instregex "KADD(B|D|Q|W)rr", 839 "KSHIFTL(B|D|Q|W)ri", 840 "KSHIFTR(B|D|Q|W)ri", 841 "KUNPCK(BW|DQ|WD)rr", 842 "VCMPPD(Z|Z128|Z256)rri", 843 "VCMPPS(Z|Z128|Z256)rri", 844 "VCMP(SD|SS)Zrr", 845 "VFPCLASS(PD|PS)(Z|Z128|Z256)rr", 846 "VFPCLASS(SD|SS)Zrr", 847 "VPCMPB(Z|Z128|Z256)rri", 848 "VPCMPD(Z|Z128|Z256)rri", 849 "VPCMPEQ(B|D|Q|W)(Z|Z128|Z256)rr", 850 "VPCMPGT(B|D|Q|W)(Z|Z128|Z256)rr", 851 "VPCMPQ(Z|Z128|Z256)rri", 852 "VPCMPU(B|D|Q|W)(Z|Z128|Z256)rri", 853 "VPCMPW(Z|Z128|Z256)rri", 854 "VPTEST(N?)M(B|D|Q|W)(Z|Z128|Z256)rr")>; 855 856def SKXWriteResGroup34 : SchedWriteRes<[SKXPort0,SKXPort0156]> { 857 let Latency = 3; 858 let NumMicroOps = 2; 859 let ResourceCycles = [1,1]; 860} 861def: InstRW<[SKXWriteResGroup34], (instrs FNSTSW16r)>; 862 863def SKXWriteResGroup37 : SchedWriteRes<[SKXPort0,SKXPort5]> { 864 let Latency = 3; 865 let NumMicroOps = 3; 866 let ResourceCycles = [1,2]; 867} 868def: InstRW<[SKXWriteResGroup37], (instregex "MMX_PH(ADD|SUB)SWrr")>; 869 870def SKXWriteResGroup38 : SchedWriteRes<[SKXPort5,SKXPort01]> { 871 let Latency = 3; 872 let NumMicroOps = 3; 873 let ResourceCycles = [2,1]; 874} 875def: InstRW<[SKXWriteResGroup38], (instregex "(V?)PH(ADD|SUB)SW(Y?)rr")>; 876 877def SKXWriteResGroup41 : SchedWriteRes<[SKXPort5,SKXPort0156]> { 878 let Latency = 3; 879 let NumMicroOps = 3; 880 let ResourceCycles = [2,1]; 881} 882def: InstRW<[SKXWriteResGroup41], (instrs MMX_PACKSSDWirr, 883 MMX_PACKSSWBirr, 884 MMX_PACKUSWBirr)>; 885 886def SKXWriteResGroup42 : SchedWriteRes<[SKXPort6,SKXPort0156]> { 887 let Latency = 3; 888 let NumMicroOps = 3; 889 let ResourceCycles = [1,2]; 890} 891def: InstRW<[SKXWriteResGroup42], (instregex "CLD")>; 892 893def SKXWriteResGroup43 : SchedWriteRes<[SKXPort237,SKXPort0156]> { 894 let Latency = 3; 895 let NumMicroOps = 3; 896 let ResourceCycles = [1,2]; 897} 898def: InstRW<[SKXWriteResGroup43], (instrs MFENCE)>; 899 900def SKXWriteResGroup44 : SchedWriteRes<[SKXPort06,SKXPort0156]> { 901 let Latency = 3; 902 let NumMicroOps = 3; 903 let ResourceCycles = [1,2]; 904} 905def: InstRW<[SKXWriteResGroup44], (instregex "RCL(8|16|32|64)r(1|i)", 906 "RCR(8|16|32|64)r(1|i)")>; 907 908def SKXWriteResGroup45 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort237]> { 909 let Latency = 3; 910 let NumMicroOps = 3; 911 let ResourceCycles = [1,1,1]; 912} 913def: InstRW<[SKXWriteResGroup45], (instrs FNSTSWm)>; 914 915def SKXWriteResGroup47 : SchedWriteRes<[SKXPort4,SKXPort6,SKXPort237,SKXPort0156]> { 916 let Latency = 3; 917 let NumMicroOps = 4; 918 let ResourceCycles = [1,1,1,1]; 919} 920def: InstRW<[SKXWriteResGroup47], (instregex "CALL(16|32|64)r")>; 921 922def SKXWriteResGroup48 : SchedWriteRes<[SKXPort4,SKXPort237,SKXPort06,SKXPort0156]> { 923 let Latency = 3; 924 let NumMicroOps = 4; 925 let ResourceCycles = [1,1,1,1]; 926} 927def: InstRW<[SKXWriteResGroup48], (instrs CALL64pcrel32)>; 928 929def SKXWriteResGroup49 : SchedWriteRes<[SKXPort0]> { 930 let Latency = 4; 931 let NumMicroOps = 1; 932 let ResourceCycles = [1]; 933} 934def: InstRW<[SKXWriteResGroup49], (instregex "MUL_(FPrST0|FST0r|FrST0)")>; 935 936def SKXWriteResGroup50 : SchedWriteRes<[SKXPort01]> { 937 let Latency = 4; 938 let NumMicroOps = 1; 939 let ResourceCycles = [1]; 940} 941def: InstRW<[SKXWriteResGroup50], (instregex "VCVTDQ2PS(Y|Z128|Z256)rr", 942 "(V?)CVTDQ2PSrr", 943 "VCVTPD2QQ(Z128|Z256)rr", 944 "VCVTPD2UQQ(Z128|Z256)rr", 945 "VCVTPS2DQ(Y|Z128|Z256)rr", 946 "(V?)CVTPS2DQrr", 947 "VCVTPS2UDQ(Z128|Z256)rr", 948 "VCVTQQ2PD(Z128|Z256)rr", 949 "VCVTTPD2QQ(Z128|Z256)rr", 950 "VCVTTPD2UQQ(Z128|Z256)rr", 951 "VCVTTPS2DQ(Z128|Z256)rr", 952 "(V?)CVTTPS2DQrr", 953 "VCVTTPS2UDQ(Z128|Z256)rr", 954 "VCVTUDQ2PS(Z128|Z256)rr", 955 "VCVTUQQ2PD(Z128|Z256)rr")>; 956 957def SKXWriteResGroup50z : SchedWriteRes<[SKXPort05]> { 958 let Latency = 4; 959 let NumMicroOps = 1; 960 let ResourceCycles = [1]; 961} 962def: InstRW<[SKXWriteResGroup50z], (instrs VCVTDQ2PSZrr, 963 VCVTPD2QQZrr, 964 VCVTPD2UQQZrr, 965 VCVTPS2DQZrr, 966 VCVTPS2UDQZrr, 967 VCVTQQ2PDZrr, 968 VCVTTPD2QQZrr, 969 VCVTTPD2UQQZrr, 970 VCVTTPS2DQZrr, 971 VCVTTPS2UDQZrr, 972 VCVTUDQ2PSZrr, 973 VCVTUQQ2PDZrr)>; 974 975def SKXWriteResGroup51 : SchedWriteRes<[SKXPort5]> { 976 let Latency = 4; 977 let NumMicroOps = 2; 978 let ResourceCycles = [2]; 979} 980def: InstRW<[SKXWriteResGroup51], (instregex "VEXPANDPD(Z|Z128|Z256)rr", 981 "VEXPANDPS(Z|Z128|Z256)rr", 982 "VPEXPANDD(Z|Z128|Z256)rr", 983 "VPEXPANDQ(Z|Z128|Z256)rr", 984 "VPMOVDB(Z|Z128|Z256)rr", 985 "VPMOVDW(Z|Z128|Z256)rr", 986 "VPMOVQB(Z|Z128|Z256)rr", 987 "VPMOVQW(Z|Z128|Z256)rr", 988 "VPMOVSDB(Z|Z128|Z256)rr", 989 "VPMOVSDW(Z|Z128|Z256)rr", 990 "VPMOVSQB(Z|Z128|Z256)rr", 991 "VPMOVSQD(Z|Z128|Z256)rr", 992 "VPMOVSQW(Z|Z128|Z256)rr", 993 "VPMOVSWB(Z|Z128|Z256)rr", 994 "VPMOVUSDB(Z|Z128|Z256)rr", 995 "VPMOVUSDW(Z|Z128|Z256)rr", 996 "VPMOVUSQB(Z|Z128|Z256)rr", 997 "VPMOVUSQD(Z|Z128|Z256)rr", 998 "VPMOVUSWB(Z|Z128|Z256)rr", 999 "VPMOVWB(Z|Z128|Z256)rr")>; 1000 1001def SKXWriteResGroup54 : SchedWriteRes<[SKXPort4,SKXPort5,SKXPort237]> { 1002 let Latency = 4; 1003 let NumMicroOps = 3; 1004 let ResourceCycles = [1,1,1]; 1005} 1006def: InstRW<[SKXWriteResGroup54], (instregex "IST(T?)_FP(16|32|64)m", 1007 "IST_F(16|32)m", 1008 "VPMOVQD(Z|Z128|Z256)mr(b?)")>; 1009 1010def SKXWriteResGroup55 : SchedWriteRes<[SKXPort0156]> { 1011 let Latency = 4; 1012 let NumMicroOps = 4; 1013 let ResourceCycles = [4]; 1014} 1015def: InstRW<[SKXWriteResGroup55], (instrs FNCLEX)>; 1016 1017def SKXWriteResGroup56 : SchedWriteRes<[]> { 1018 let Latency = 0; 1019 let NumMicroOps = 4; 1020 let ResourceCycles = []; 1021} 1022def: InstRW<[SKXWriteResGroup56], (instrs VZEROUPPER)>; 1023 1024def SKXWriteResGroup57 : SchedWriteRes<[SKXPort1,SKXPort6,SKXPort0156]> { 1025 let Latency = 4; 1026 let NumMicroOps = 4; 1027 let ResourceCycles = [1,1,2]; 1028} 1029def: InstRW<[SKXWriteResGroup57], (instregex "LAR(16|32|64)rr")>; 1030 1031def SKXWriteResGroup58 : SchedWriteRes<[SKXPort23]> { 1032 let Latency = 5; 1033 let NumMicroOps = 1; 1034 let ResourceCycles = [1]; 1035} 1036def: InstRW<[SKXWriteResGroup58], (instregex "MOVSX(16|32|64)rm(8|16|32)", 1037 "MOVZX(16|32|64)rm(8|16)", 1038 "(V?)MOVDDUPrm")>; // TODO: Should this be SKXWriteResGroup71? 1039 1040def SKXWriteResGroup61 : SchedWriteRes<[SKXPort5,SKXPort015]> { 1041 let Latency = 5; 1042 let NumMicroOps = 2; 1043 let ResourceCycles = [1,1]; 1044} 1045def: InstRW<[SKXWriteResGroup61], (instregex "MMX_CVT(T?)PD2PIirr", 1046 "MMX_CVT(T?)PS2PIirr", 1047 "VCVTDQ2PDZ128rr", 1048 "VCVTPD2DQZ128rr", 1049 "(V?)CVT(T?)PD2DQrr", 1050 "VCVTPD2PSZ128rr", 1051 "(V?)CVTPD2PSrr", 1052 "VCVTPD2UDQZ128rr", 1053 "VCVTPS2PDZ128rr", 1054 "(V?)CVTPS2PDrr", 1055 "VCVTPS2QQZ128rr", 1056 "VCVTPS2UQQZ128rr", 1057 "VCVTQQ2PSZ128rr", 1058 "(V?)CVTSD2SS(Z?)rr", 1059 "(V?)CVTSI(64)?2SDrr", 1060 "VCVTSI2SSZrr", 1061 "(V?)CVTSI2SSrr", 1062 "VCVTSI(64)?2SDZrr", 1063 "VCVTSS2SDZrr", 1064 "(V?)CVTSS2SDrr", 1065 "VCVTTPD2DQZ128rr", 1066 "VCVTTPD2UDQZ128rr", 1067 "VCVTTPS2QQZ128rr", 1068 "VCVTTPS2UQQZ128rr", 1069 "VCVTUDQ2PDZ128rr", 1070 "VCVTUQQ2PSZ128rr", 1071 "VCVTUSI2SSZrr", 1072 "VCVTUSI(64)?2SDZrr")>; 1073 1074def SKXWriteResGroup62 : SchedWriteRes<[SKXPort5,SKXPort015]> { 1075 let Latency = 5; 1076 let NumMicroOps = 3; 1077 let ResourceCycles = [2,1]; 1078} 1079def: InstRW<[SKXWriteResGroup62], (instregex "VPCONFLICTQZ128rr")>; 1080 1081def SKXWriteResGroup63 : SchedWriteRes<[SKXPort1,SKXPort6,SKXPort06]> { 1082 let Latency = 5; 1083 let NumMicroOps = 3; 1084 let ResourceCycles = [1,1,1]; 1085} 1086def: InstRW<[SKXWriteResGroup63], (instregex "STR(16|32|64)r")>; 1087 1088def SKXWriteResGroup65 : SchedWriteRes<[SKXPort4,SKXPort237,SKXPort015]> { 1089 let Latency = 5; 1090 let NumMicroOps = 3; 1091 let ResourceCycles = [1,1,1]; 1092} 1093def: InstRW<[SKXWriteResGroup65], (instregex "VCVTPS2PHZ128mr(b?)", 1094 "VCVTPS2PHZ256mr(b?)", 1095 "VCVTPS2PHZmr(b?)")>; 1096 1097def SKXWriteResGroup66 : SchedWriteRes<[SKXPort4,SKXPort5,SKXPort237]> { 1098 let Latency = 5; 1099 let NumMicroOps = 4; 1100 let ResourceCycles = [1,2,1]; 1101} 1102def: InstRW<[SKXWriteResGroup66], (instregex "VPMOVDB(Z|Z128|Z256)mr(b?)", 1103 "VPMOVDW(Z|Z128|Z256)mr(b?)", 1104 "VPMOVQB(Z|Z128|Z256)mr(b?)", 1105 "VPMOVQW(Z|Z128|Z256)mr(b?)", 1106 "VPMOVSDB(Z|Z128|Z256)mr(b?)", 1107 "VPMOVSDW(Z|Z128|Z256)mr(b?)", 1108 "VPMOVSQB(Z|Z128|Z256)mr(b?)", 1109 "VPMOVSQD(Z|Z128|Z256)mr(b?)", 1110 "VPMOVSQW(Z|Z128|Z256)mr(b?)", 1111 "VPMOVSWB(Z|Z128|Z256)mr(b?)", 1112 "VPMOVUSDB(Z|Z128|Z256)mr(b?)", 1113 "VPMOVUSDW(Z|Z128|Z256)mr(b?)", 1114 "VPMOVUSQB(Z|Z128|Z256)mr(b?)", 1115 "VPMOVUSQD(Z|Z128|Z256)mr(b?)", 1116 "VPMOVUSQW(Z|Z128|Z256)mr(b?)", 1117 "VPMOVUSWB(Z|Z128|Z256)mr(b?)", 1118 "VPMOVWB(Z|Z128|Z256)mr(b?)")>; 1119 1120def SKXWriteResGroup67 : SchedWriteRes<[SKXPort06,SKXPort0156]> { 1121 let Latency = 5; 1122 let NumMicroOps = 5; 1123 let ResourceCycles = [1,4]; 1124} 1125def: InstRW<[SKXWriteResGroup67], (instrs XSETBV)>; 1126 1127def SKXWriteResGroup69 : SchedWriteRes<[SKXPort4,SKXPort237,SKXPort0156]> { 1128 let Latency = 5; 1129 let NumMicroOps = 6; 1130 let ResourceCycles = [1,1,4]; 1131} 1132def: InstRW<[SKXWriteResGroup69], (instregex "PUSHF(16|64)")>; 1133 1134def SKXWriteResGroup71 : SchedWriteRes<[SKXPort23]> { 1135 let Latency = 6; 1136 let NumMicroOps = 1; 1137 let ResourceCycles = [1]; 1138} 1139def: InstRW<[SKXWriteResGroup71], (instrs VBROADCASTSSrm, 1140 VPBROADCASTDrm, 1141 VPBROADCASTQrm, 1142 VMOVSHDUPrm, 1143 VMOVSLDUPrm, 1144 MOVSHDUPrm, 1145 MOVSLDUPrm)>; 1146 1147def SKXWriteResGroup72 : SchedWriteRes<[SKXPort5]> { 1148 let Latency = 6; 1149 let NumMicroOps = 2; 1150 let ResourceCycles = [2]; 1151} 1152def: InstRW<[SKXWriteResGroup72], (instrs MMX_CVTPI2PSirr)>; 1153def: InstRW<[SKXWriteResGroup72], (instregex "VCOMPRESSPD(Z|Z128|Z256)rr", 1154 "VCOMPRESSPS(Z|Z128|Z256)rr", 1155 "VPCOMPRESSD(Z|Z128|Z256)rr", 1156 "VPCOMPRESSQ(Z|Z128|Z256)rr", 1157 "VPERMW(Z|Z128|Z256)rr")>; 1158 1159def SKXWriteResGroup73 : SchedWriteRes<[SKXPort0,SKXPort23]> { 1160 let Latency = 6; 1161 let NumMicroOps = 2; 1162 let ResourceCycles = [1,1]; 1163} 1164def: InstRW<[SKXWriteResGroup73], (instrs MMX_PADDSBirm, 1165 MMX_PADDSWirm, 1166 MMX_PADDUSBirm, 1167 MMX_PADDUSWirm, 1168 MMX_PAVGBirm, 1169 MMX_PAVGWirm, 1170 MMX_PCMPEQBirm, 1171 MMX_PCMPEQDirm, 1172 MMX_PCMPEQWirm, 1173 MMX_PCMPGTBirm, 1174 MMX_PCMPGTDirm, 1175 MMX_PCMPGTWirm, 1176 MMX_PMAXSWirm, 1177 MMX_PMAXUBirm, 1178 MMX_PMINSWirm, 1179 MMX_PMINUBirm, 1180 MMX_PSUBSBirm, 1181 MMX_PSUBSWirm, 1182 MMX_PSUBUSBirm, 1183 MMX_PSUBUSWirm)>; 1184 1185def SKXWriteResGroup76 : SchedWriteRes<[SKXPort6,SKXPort23]> { 1186 let Latency = 6; 1187 let NumMicroOps = 2; 1188 let ResourceCycles = [1,1]; 1189} 1190def: InstRW<[SKXWriteResGroup76], (instrs FARJMP64m)>; 1191def: InstRW<[SKXWriteResGroup76], (instregex "JMP(16|32|64)m")>; 1192 1193def SKXWriteResGroup79 : SchedWriteRes<[SKXPort23,SKXPort15]> { 1194 let Latency = 6; 1195 let NumMicroOps = 2; 1196 let ResourceCycles = [1,1]; 1197} 1198def: InstRW<[SKXWriteResGroup79], (instregex "ANDN(32|64)rm", 1199 "MOVBE(16|32|64)rm")>; 1200 1201def SKXWriteResGroup80 : SchedWriteRes<[SKXPort23,SKXPort015]> { 1202 let Latency = 6; 1203 let NumMicroOps = 2; 1204 let ResourceCycles = [1,1]; 1205} 1206def: InstRW<[SKXWriteResGroup80], (instregex "VMOV(64to|QI2)PQIZrm(b?)")>; 1207def: InstRW<[SKXWriteResGroup80], (instrs VMOVDI2PDIZrm)>; 1208 1209def SKXWriteResGroup81 : SchedWriteRes<[SKXPort23,SKXPort0156]> { 1210 let Latency = 6; 1211 let NumMicroOps = 2; 1212 let ResourceCycles = [1,1]; 1213} 1214def: InstRW<[SKXWriteResGroup81], (instrs POP16r, POP32r, POP64r)>; 1215def: InstRW<[SKXWriteResGroup81], (instregex "POP(16|32|64)rmr")>; 1216 1217def SKXWriteResGroup82 : SchedWriteRes<[SKXPort5,SKXPort015]> { 1218 let Latency = 6; 1219 let NumMicroOps = 3; 1220 let ResourceCycles = [2,1]; 1221} 1222def: InstRW<[SKXWriteResGroup82], (instregex "(V?)CVTSI642SSrr", 1223 "VCVTSI642SSZrr", 1224 "VCVTUSI642SSZrr")>; 1225 1226def SKXWriteResGroup84 : SchedWriteRes<[SKXPort1,SKXPort6,SKXPort06,SKXPort0156]> { 1227 let Latency = 6; 1228 let NumMicroOps = 4; 1229 let ResourceCycles = [1,1,1,1]; 1230} 1231def: InstRW<[SKXWriteResGroup84], (instregex "SLDT(16|32|64)r")>; 1232 1233def SKXWriteResGroup86 : SchedWriteRes<[SKXPort4,SKXPort23,SKXPort237,SKXPort06]> { 1234 let Latency = 6; 1235 let NumMicroOps = 4; 1236 let ResourceCycles = [1,1,1,1]; 1237} 1238def: InstRW<[SKXWriteResGroup86], (instregex "SAR(8|16|32|64)m(1|i)", 1239 "SHL(8|16|32|64)m(1|i)", 1240 "SHR(8|16|32|64)m(1|i)")>; 1241 1242def SKXWriteResGroup87 : SchedWriteRes<[SKXPort4,SKXPort23,SKXPort237,SKXPort0156]> { 1243 let Latency = 6; 1244 let NumMicroOps = 4; 1245 let ResourceCycles = [1,1,1,1]; 1246} 1247def: InstRW<[SKXWriteResGroup87], (instregex "POP(16|32|64)rmm", 1248 "PUSH(16|32|64)rmm")>; 1249 1250def SKXWriteResGroup88 : SchedWriteRes<[SKXPort6,SKXPort0156]> { 1251 let Latency = 6; 1252 let NumMicroOps = 6; 1253 let ResourceCycles = [1,5]; 1254} 1255def: InstRW<[SKXWriteResGroup88], (instrs STD)>; 1256 1257def SKXWriteResGroup89 : SchedWriteRes<[SKXPort23]> { 1258 let Latency = 7; 1259 let NumMicroOps = 1; 1260 let ResourceCycles = [1]; 1261} 1262def: InstRW<[SKXWriteResGroup89], (instregex "LD_F(32|64|80)m")>; 1263def: InstRW<[SKXWriteResGroup89], (instrs VBROADCASTF128, 1264 VBROADCASTI128, 1265 VBROADCASTSDYrm, 1266 VBROADCASTSSYrm, 1267 VMOVDDUPYrm, 1268 VMOVSHDUPYrm, 1269 VMOVSLDUPYrm, 1270 VPBROADCASTDYrm, 1271 VPBROADCASTQYrm)>; 1272 1273def SKXWriteResGroup90 : SchedWriteRes<[SKXPort01,SKXPort5]> { 1274 let Latency = 7; 1275 let NumMicroOps = 2; 1276 let ResourceCycles = [1,1]; 1277} 1278def: InstRW<[SKXWriteResGroup90], (instrs VCVTDQ2PDYrr)>; 1279 1280def SKXWriteResGroup92 : SchedWriteRes<[SKXPort5,SKXPort23]> { 1281 let Latency = 7; 1282 let NumMicroOps = 2; 1283 let ResourceCycles = [1,1]; 1284} 1285def: InstRW<[SKXWriteResGroup92], (instregex "VMOVSDZrm(b?)", 1286 "VMOVSSZrm(b?)")>; 1287 1288def SKXWriteResGroup92a : SchedWriteRes<[SKXPort5,SKXPort23]> { 1289 let Latency = 6; 1290 let NumMicroOps = 2; 1291 let ResourceCycles = [1,1]; 1292} 1293def: InstRW<[SKXWriteResGroup92a], (instregex "(V?)PMOV(SX|ZX)BDrm", 1294 "(V?)PMOV(SX|ZX)BQrm", 1295 "(V?)PMOV(SX|ZX)BWrm", 1296 "(V?)PMOV(SX|ZX)DQrm", 1297 "(V?)PMOV(SX|ZX)WDrm", 1298 "(V?)PMOV(SX|ZX)WQrm")>; 1299 1300def SKXWriteResGroup93 : SchedWriteRes<[SKXPort5,SKXPort015]> { 1301 let Latency = 7; 1302 let NumMicroOps = 2; 1303 let ResourceCycles = [1,1]; 1304} 1305def: InstRW<[SKXWriteResGroup93], (instregex "VCVTDQ2PDZ256rr", 1306 "VCVTPD2DQ(Y|Z256)rr", 1307 "VCVTPD2PS(Y|Z256)rr", 1308 "VCVTPD2UDQZ256rr", 1309 "VCVTPS2PD(Y|Z256)rr", 1310 "VCVTPS2QQZ256rr", 1311 "VCVTPS2UQQZ256rr", 1312 "VCVTQQ2PSZ256rr", 1313 "VCVTTPD2DQ(Y|Z256)rr", 1314 "VCVTTPD2UDQZ256rr", 1315 "VCVTTPS2QQZ256rr", 1316 "VCVTTPS2UQQZ256rr", 1317 "VCVTUDQ2PDZ256rr", 1318 "VCVTUQQ2PSZ256rr")>; 1319 1320def SKXWriteResGroup93z : SchedWriteRes<[SKXPort5,SKXPort05]> { 1321 let Latency = 7; 1322 let NumMicroOps = 2; 1323 let ResourceCycles = [1,1]; 1324} 1325def: InstRW<[SKXWriteResGroup93z], (instrs VCVTDQ2PDZrr, 1326 VCVTPD2DQZrr, 1327 VCVTPD2PSZrr, 1328 VCVTPD2UDQZrr, 1329 VCVTPS2PDZrr, 1330 VCVTPS2QQZrr, 1331 VCVTPS2UQQZrr, 1332 VCVTQQ2PSZrr, 1333 VCVTTPD2DQZrr, 1334 VCVTTPD2UDQZrr, 1335 VCVTTPS2QQZrr, 1336 VCVTTPS2UQQZrr, 1337 VCVTUDQ2PDZrr, 1338 VCVTUQQ2PSZrr)>; 1339 1340def SKXWriteResGroup95 : SchedWriteRes<[SKXPort23,SKXPort015]> { 1341 let Latency = 7; 1342 let NumMicroOps = 2; 1343 let ResourceCycles = [1,1]; 1344} 1345def: InstRW<[SKXWriteResGroup95], (instrs VMOVNTDQAZ128rm, 1346 VPBLENDDrmi)>; 1347def: InstRW<[SKXWriteResGroup95, ReadAfterVecXLd], 1348 (instregex "VBLENDMPDZ128rm(b?)", 1349 "VBLENDMPSZ128rm(b?)", 1350 "VBROADCASTI32X2Z128rm(b?)", 1351 "VBROADCASTSSZ128rm(b?)", 1352 "VINSERT(F|I)128rm", 1353 "VMOVAPDZ128rm(b?)", 1354 "VMOVAPSZ128rm(b?)", 1355 "VMOVDDUPZ128rm(b?)", 1356 "VMOVDQA32Z128rm(b?)", 1357 "VMOVDQA64Z128rm(b?)", 1358 "VMOVDQU16Z128rm(b?)", 1359 "VMOVDQU32Z128rm(b?)", 1360 "VMOVDQU64Z128rm(b?)", 1361 "VMOVDQU8Z128rm(b?)", 1362 "VMOVSHDUPZ128rm(b?)", 1363 "VMOVSLDUPZ128rm(b?)", 1364 "VMOVUPDZ128rm(b?)", 1365 "VMOVUPSZ128rm(b?)", 1366 "VPADD(B|D|Q|W)Z128rm(b?)", 1367 "(V?)PADD(B|D|Q|W)rm", 1368 "VPBLENDM(B|D|Q|W)Z128rm(b?)", 1369 "VPBROADCASTDZ128rm(b?)", 1370 "VPBROADCASTQZ128rm(b?)", 1371 "VPSUB(B|D|Q|W)Z128rm(b?)", 1372 "(V?)PSUB(B|D|Q|W)rm", 1373 "VPTERNLOGDZ128rm(b?)i", 1374 "VPTERNLOGQZ128rm(b?)i")>; 1375 1376def SKXWriteResGroup96 : SchedWriteRes<[SKXPort5,SKXPort23]> { 1377 let Latency = 7; 1378 let NumMicroOps = 3; 1379 let ResourceCycles = [2,1]; 1380} 1381def: InstRW<[SKXWriteResGroup96], (instrs MMX_PACKSSDWirm, 1382 MMX_PACKSSWBirm, 1383 MMX_PACKUSWBirm)>; 1384 1385def SKXWriteResGroup97 : SchedWriteRes<[SKXPort5,SKXPort015]> { 1386 let Latency = 7; 1387 let NumMicroOps = 3; 1388 let ResourceCycles = [2,1]; 1389} 1390def: InstRW<[SKXWriteResGroup97], (instregex "VPERMI2W128rr", 1391 "VPERMI2W256rr", 1392 "VPERMI2Wrr", 1393 "VPERMT2W128rr", 1394 "VPERMT2W256rr", 1395 "VPERMT2Wrr")>; 1396 1397def SKXWriteResGroup99 : SchedWriteRes<[SKXPort23,SKXPort0156]> { 1398 let Latency = 7; 1399 let NumMicroOps = 3; 1400 let ResourceCycles = [1,2]; 1401} 1402def: InstRW<[SKXWriteResGroup99], (instrs LEAVE, LEAVE64, 1403 SCASB, SCASL, SCASQ, SCASW)>; 1404 1405def SKXWriteResGroup100 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort015]> { 1406 let Latency = 7; 1407 let NumMicroOps = 3; 1408 let ResourceCycles = [1,1,1]; 1409} 1410def: InstRW<[SKXWriteResGroup100], (instregex "VCVTSS2USI64Zrr", 1411 "(V?)CVTSS2SI64(Z?)rr", 1412 "(V?)CVTTSS2SI64(Z?)rr", 1413 "VCVTTSS2USI64Zrr")>; 1414 1415def SKXWriteResGroup101 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort05]> { 1416 let Latency = 7; 1417 let NumMicroOps = 3; 1418 let ResourceCycles = [1,1,1]; 1419} 1420def: InstRW<[SKXWriteResGroup101], (instrs FLDCW16m)>; 1421 1422def SKXWriteResGroup103 : SchedWriteRes<[SKXPort5,SKXPort23,SKXPort0156]> { 1423 let Latency = 7; 1424 let NumMicroOps = 3; 1425 let ResourceCycles = [1,1,1]; 1426} 1427def: InstRW<[SKXWriteResGroup103], (instregex "KMOV(B|D|Q|W)km")>; 1428 1429def SKXWriteResGroup104 : SchedWriteRes<[SKXPort6,SKXPort23,SKXPort0156]> { 1430 let Latency = 7; 1431 let NumMicroOps = 3; 1432 let ResourceCycles = [1,1,1]; 1433} 1434def: InstRW<[SKXWriteResGroup104], (instrs LRETQ, RETQ)>; 1435 1436def SKXWriteResGroup106 : SchedWriteRes<[SKXPort4,SKXPort5,SKXPort237]> { 1437 let Latency = 7; 1438 let NumMicroOps = 4; 1439 let ResourceCycles = [1,2,1]; 1440} 1441def: InstRW<[SKXWriteResGroup106], (instregex "VCOMPRESSPD(Z|Z128|Z256)mr(b?)", 1442 "VCOMPRESSPS(Z|Z128|Z256)mr(b?)", 1443 "VPCOMPRESSD(Z|Z128|Z256)mr(b?)", 1444 "VPCOMPRESSQ(Z|Z128|Z256)mr(b?)")>; 1445 1446def SKXWriteResGroup107 : SchedWriteRes<[SKXPort4,SKXPort23,SKXPort237,SKXPort06]> { 1447 let Latency = 7; 1448 let NumMicroOps = 5; 1449 let ResourceCycles = [1,1,1,2]; 1450} 1451def: InstRW<[SKXWriteResGroup107], (instregex "ROL(8|16|32|64)m(1|i)", 1452 "ROR(8|16|32|64)m(1|i)")>; 1453 1454def SKXWriteResGroup107_1 : SchedWriteRes<[SKXPort06]> { 1455 let Latency = 2; 1456 let NumMicroOps = 2; 1457 let ResourceCycles = [2]; 1458} 1459def: InstRW<[SKXWriteResGroup107_1], (instrs ROL8r1, ROL16r1, ROL32r1, ROL64r1, 1460 ROR8r1, ROR16r1, ROR32r1, ROR64r1)>; 1461 1462def SKXWriteResGroup108 : SchedWriteRes<[SKXPort4,SKXPort23,SKXPort237,SKXPort0156]> { 1463 let Latency = 7; 1464 let NumMicroOps = 5; 1465 let ResourceCycles = [1,1,1,2]; 1466} 1467def: InstRW<[SKXWriteResGroup108], (instregex "XADD(8|16|32|64)rm")>; 1468 1469def SKXWriteResGroup109 : SchedWriteRes<[SKXPort4,SKXPort6,SKXPort23,SKXPort237,SKXPort0156]> { 1470 let Latency = 7; 1471 let NumMicroOps = 5; 1472 let ResourceCycles = [1,1,1,1,1]; 1473} 1474def: InstRW<[SKXWriteResGroup109], (instregex "CALL(16|32|64)m")>; 1475def: InstRW<[SKXWriteResGroup109], (instrs FARCALL64m)>; 1476 1477def SKXWriteResGroup110 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort237,SKXPort0156]> { 1478 let Latency = 7; 1479 let NumMicroOps = 7; 1480 let ResourceCycles = [1,2,2,2]; 1481} 1482def: InstRW<[SKXWriteResGroup110], (instrs VPSCATTERDQZ128mr, 1483 VPSCATTERQQZ128mr, 1484 VSCATTERDPDZ128mr, 1485 VSCATTERQPDZ128mr)>; 1486 1487def SKXWriteResGroup111 : SchedWriteRes<[SKXPort6,SKXPort06,SKXPort15,SKXPort0156]> { 1488 let Latency = 7; 1489 let NumMicroOps = 7; 1490 let ResourceCycles = [1,3,1,2]; 1491} 1492def: InstRW<[SKXWriteResGroup111], (instrs LOOP)>; 1493 1494def SKXWriteResGroup112 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort237,SKXPort0156]> { 1495 let Latency = 7; 1496 let NumMicroOps = 11; 1497 let ResourceCycles = [1,4,4,2]; 1498} 1499def: InstRW<[SKXWriteResGroup112], (instrs VPSCATTERDQZ256mr, 1500 VPSCATTERQQZ256mr, 1501 VSCATTERDPDZ256mr, 1502 VSCATTERQPDZ256mr)>; 1503 1504def SKXWriteResGroup113 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort237,SKXPort0156]> { 1505 let Latency = 7; 1506 let NumMicroOps = 19; 1507 let ResourceCycles = [1,8,8,2]; 1508} 1509def: InstRW<[SKXWriteResGroup113], (instrs VPSCATTERDQZmr, 1510 VPSCATTERQQZmr, 1511 VSCATTERDPDZmr, 1512 VSCATTERQPDZmr)>; 1513 1514def SKXWriteResGroup114 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort5,SKXPort237,SKXPort0156]> { 1515 let Latency = 7; 1516 let NumMicroOps = 36; 1517 let ResourceCycles = [1,16,1,16,2]; 1518} 1519def: InstRW<[SKXWriteResGroup114], (instrs VSCATTERDPSZmr)>; 1520 1521def SKXWriteResGroup118 : SchedWriteRes<[SKXPort1,SKXPort23]> { 1522 let Latency = 8; 1523 let NumMicroOps = 2; 1524 let ResourceCycles = [1,1]; 1525} 1526def: InstRW<[SKXWriteResGroup118], (instregex "PDEP(32|64)rm", 1527 "PEXT(32|64)rm")>; 1528 1529def SKXWriteResGroup119 : SchedWriteRes<[SKXPort5,SKXPort23]> { 1530 let Latency = 8; 1531 let NumMicroOps = 2; 1532 let ResourceCycles = [1,1]; 1533} 1534def: InstRW<[SKXWriteResGroup119], (instregex "FCOM(P?)(32|64)m", 1535 "VPBROADCASTB(Z|Z256)rm(b?)", 1536 "VPBROADCASTW(Z|Z256)rm(b?)")>; 1537def: InstRW<[SKXWriteResGroup119], (instrs VPBROADCASTBYrm, 1538 VPBROADCASTWYrm, 1539 VPMOVSXBDYrm, 1540 VPMOVSXBQYrm, 1541 VPMOVSXWQYrm)>; 1542 1543def SKXWriteResGroup121 : SchedWriteRes<[SKXPort23,SKXPort015]> { 1544 let Latency = 8; 1545 let NumMicroOps = 2; 1546 let ResourceCycles = [1,1]; 1547} 1548def: InstRW<[SKXWriteResGroup121], (instrs VMOVNTDQAZ256rm, 1549 VPBLENDDYrmi)>; 1550def: InstRW<[SKXWriteResGroup121, ReadAfterVecYLd], 1551 (instregex "VBLENDMPD(Z|Z256)rm(b?)", 1552 "VBLENDMPS(Z|Z256)rm(b?)", 1553 "VBROADCASTF32X2Z256rm(b?)", 1554 "VBROADCASTF32X2Zrm(b?)", 1555 "VBROADCASTF32X4Z256rm(b?)", 1556 "VBROADCASTF32X4rm(b?)", 1557 "VBROADCASTF32X8rm(b?)", 1558 "VBROADCASTF64X2Z128rm(b?)", 1559 "VBROADCASTF64X2rm(b?)", 1560 "VBROADCASTF64X4rm(b?)", 1561 "VBROADCASTI32X2Z256rm(b?)", 1562 "VBROADCASTI32X2Zrm(b?)", 1563 "VBROADCASTI32X4Z256rm(b?)", 1564 "VBROADCASTI32X4rm(b?)", 1565 "VBROADCASTI32X8rm(b?)", 1566 "VBROADCASTI64X2Z128rm(b?)", 1567 "VBROADCASTI64X2rm(b?)", 1568 "VBROADCASTI64X4rm(b?)", 1569 "VBROADCASTSD(Z|Z256)rm(b?)", 1570 "VBROADCASTSS(Z|Z256)rm(b?)", 1571 "VINSERTF32x4(Z|Z256)rm(b?)", 1572 "VINSERTF32x8Zrm(b?)", 1573 "VINSERTF64x2(Z|Z256)rm(b?)", 1574 "VINSERTF64x4Zrm(b?)", 1575 "VINSERTI32x4(Z|Z256)rm(b?)", 1576 "VINSERTI32x8Zrm(b?)", 1577 "VINSERTI64x2(Z|Z256)rm(b?)", 1578 "VINSERTI64x4Zrm(b?)", 1579 "VMOVAPD(Z|Z256)rm(b?)", 1580 "VMOVAPS(Z|Z256)rm(b?)", 1581 "VMOVDDUP(Z|Z256)rm(b?)", 1582 "VMOVDQA32(Z|Z256)rm(b?)", 1583 "VMOVDQA64(Z|Z256)rm(b?)", 1584 "VMOVDQU16(Z|Z256)rm(b?)", 1585 "VMOVDQU32(Z|Z256)rm(b?)", 1586 "VMOVDQU64(Z|Z256)rm(b?)", 1587 "VMOVDQU8(Z|Z256)rm(b?)", 1588 "VMOVSHDUP(Z|Z256)rm(b?)", 1589 "VMOVSLDUP(Z|Z256)rm(b?)", 1590 "VMOVUPD(Z|Z256)rm(b?)", 1591 "VMOVUPS(Z|Z256)rm(b?)", 1592 "VPADD(B|D|Q|W)Yrm", 1593 "VPADD(B|D|Q|W)(Z|Z256)rm(b?)", 1594 "VPBLENDM(B|D|Q|W)(Z|Z256)rm(b?)", 1595 "VPBROADCASTD(Z|Z256)rm(b?)", 1596 "VPBROADCASTQ(Z|Z256)rm(b?)", 1597 "VPSUB(B|D|Q|W)Yrm", 1598 "VPSUB(B|D|Q|W)(Z|Z256)rm(b?)", 1599 "VPTERNLOGD(Z|Z256)rm(b?)i", 1600 "VPTERNLOGQ(Z|Z256)rm(b?)i")>; 1601 1602def SKXWriteResGroup123 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort23]> { 1603 let Latency = 8; 1604 let NumMicroOps = 4; 1605 let ResourceCycles = [1,2,1]; 1606} 1607def: InstRW<[SKXWriteResGroup123], (instregex "MMX_PH(ADD|SUB)SWrm")>; 1608 1609def SKXWriteResGroup127 : SchedWriteRes<[SKXPort23,SKXPort237,SKXPort06,SKXPort0156]> { 1610 let Latency = 8; 1611 let NumMicroOps = 5; 1612 let ResourceCycles = [1,1,1,2]; 1613} 1614def: InstRW<[SKXWriteResGroup127], (instregex "RCL(8|16|32|64)m(1|i)", 1615 "RCR(8|16|32|64)m(1|i)")>; 1616 1617def SKXWriteResGroup128 : SchedWriteRes<[SKXPort4,SKXPort23,SKXPort237,SKXPort06]> { 1618 let Latency = 8; 1619 let NumMicroOps = 6; 1620 let ResourceCycles = [1,1,1,3]; 1621} 1622def: InstRW<[SKXWriteResGroup128], (instregex "ROL(8|16|32|64)mCL", 1623 "ROR(8|16|32|64)mCL", 1624 "SAR(8|16|32|64)mCL", 1625 "SHL(8|16|32|64)mCL", 1626 "SHR(8|16|32|64)mCL")>; 1627 1628def SKXWriteResGroup130 : SchedWriteRes<[SKXPort4,SKXPort23,SKXPort237,SKXPort06,SKXPort0156]> { 1629 let Latency = 8; 1630 let NumMicroOps = 6; 1631 let ResourceCycles = [1,1,1,2,1]; 1632} 1633def: SchedAlias<WriteADCRMW, SKXWriteResGroup130>; 1634 1635def SKXWriteResGroup131 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort5,SKXPort237,SKXPort0156]> { 1636 let Latency = 8; 1637 let NumMicroOps = 8; 1638 let ResourceCycles = [1,2,1,2,2]; 1639} 1640def: InstRW<[SKXWriteResGroup131], (instrs VPSCATTERQDZ128mr, 1641 VPSCATTERQDZ256mr, 1642 VSCATTERQPSZ128mr, 1643 VSCATTERQPSZ256mr)>; 1644 1645def SKXWriteResGroup132 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort5,SKXPort237,SKXPort0156]> { 1646 let Latency = 8; 1647 let NumMicroOps = 12; 1648 let ResourceCycles = [1,4,1,4,2]; 1649} 1650def: InstRW<[SKXWriteResGroup132], (instrs VPSCATTERDDZ128mr, 1651 VSCATTERDPSZ128mr)>; 1652 1653def SKXWriteResGroup133 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort5,SKXPort237,SKXPort0156]> { 1654 let Latency = 8; 1655 let NumMicroOps = 20; 1656 let ResourceCycles = [1,8,1,8,2]; 1657} 1658def: InstRW<[SKXWriteResGroup133], (instrs VPSCATTERDDZ256mr, 1659 VSCATTERDPSZ256mr)>; 1660 1661def SKXWriteResGroup134 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort5,SKXPort237,SKXPort0156]> { 1662 let Latency = 8; 1663 let NumMicroOps = 36; 1664 let ResourceCycles = [1,16,1,16,2]; 1665} 1666def: InstRW<[SKXWriteResGroup134], (instrs VPSCATTERDDZmr)>; 1667 1668def SKXWriteResGroup135 : SchedWriteRes<[SKXPort0,SKXPort23]> { 1669 let Latency = 9; 1670 let NumMicroOps = 2; 1671 let ResourceCycles = [1,1]; 1672} 1673def: InstRW<[SKXWriteResGroup135], (instrs MMX_CVTPI2PSirm)>; 1674 1675def SKXWriteResGroup136 : SchedWriteRes<[SKXPort5,SKXPort23]> { 1676 let Latency = 9; 1677 let NumMicroOps = 2; 1678 let ResourceCycles = [1,1]; 1679} 1680def: InstRW<[SKXWriteResGroup136], (instrs VPMOVSXBWYrm, 1681 VPMOVSXDQYrm, 1682 VPMOVSXWDYrm, 1683 VPMOVZXWDYrm)>; 1684def: InstRW<[SKXWriteResGroup136], (instregex "VALIGN(D|Q)Z128rm(b?)i", 1685 "VFPCLASSSDZrm(b?)", 1686 "VFPCLASSSSZrm(b?)", 1687 "(V?)PCMPGTQrm", 1688 "VPERMI2D128rm(b?)", 1689 "VPERMI2PD128rm(b?)", 1690 "VPERMI2PS128rm(b?)", 1691 "VPERMI2Q128rm(b?)", 1692 "VPERMT2D128rm(b?)", 1693 "VPERMT2PD128rm(b?)", 1694 "VPERMT2PS128rm(b?)", 1695 "VPERMT2Q128rm(b?)", 1696 "VPMAXSQZ128rm(b?)", 1697 "VPMAXUQZ128rm(b?)", 1698 "VPMINSQZ128rm(b?)", 1699 "VPMINUQZ128rm(b?)", 1700 "VPMOVSXBDZ128rm(b?)", 1701 "VPMOVSXBQZ128rm(b?)", 1702 "VPMOVSXBWZ128rm(b?)", 1703 "VPMOVSXDQZ128rm(b?)", 1704 "VPMOVSXWDZ128rm(b?)", 1705 "VPMOVSXWQZ128rm(b?)", 1706 "VPMOVZXBDZ128rm(b?)", 1707 "VPMOVZXBQZ128rm(b?)", 1708 "VPMOVZXBWZ128rm(b?)", 1709 "VPMOVZXDQZ128rm(b?)", 1710 "VPMOVZXWDZ128rm(b?)", 1711 "VPMOVZXWQZ128rm(b?)")>; 1712 1713def SKXWriteResGroup136_2 : SchedWriteRes<[SKXPort5,SKXPort23]> { 1714 let Latency = 10; 1715 let NumMicroOps = 2; 1716 let ResourceCycles = [1,1]; 1717} 1718def: InstRW<[SKXWriteResGroup136_2], (instregex "VCMP(PD|PS)Z128rm(b?)i", 1719 "VCMP(SD|SS)Zrm", 1720 "VFPCLASSPDZ128rm(b?)", 1721 "VFPCLASSPSZ128rm(b?)", 1722 "VPCMPBZ128rmi(b?)", 1723 "VPCMPDZ128rmi(b?)", 1724 "VPCMPEQ(B|D|Q|W)Z128rm(b?)", 1725 "VPCMPGT(B|D|Q|W)Z128rm(b?)", 1726 "VPCMPQZ128rmi(b?)", 1727 "VPCMPU(B|D|Q|W)Z128rmi(b?)", 1728 "VPCMPWZ128rmi(b?)", 1729 "VPTESTMBZ128rm(b?)", 1730 "VPTESTMDZ128rm(b?)", 1731 "VPTESTMQZ128rm(b?)", 1732 "VPTESTMWZ128rm(b?)", 1733 "VPTESTNMBZ128rm(b?)", 1734 "VPTESTNMDZ128rm(b?)", 1735 "VPTESTNMQZ128rm(b?)", 1736 "VPTESTNMWZ128rm(b?)")>; 1737 1738def SKXWriteResGroup137 : SchedWriteRes<[SKXPort23,SKXPort015]> { 1739 let Latency = 9; 1740 let NumMicroOps = 2; 1741 let ResourceCycles = [1,1]; 1742} 1743def: InstRW<[SKXWriteResGroup137], (instregex "MMX_CVT(T?)PS2PIirm", 1744 "(V?)CVTPS2PDrm")>; 1745 1746def SKXWriteResGroup143 : SchedWriteRes<[SKXPort5,SKXPort01,SKXPort23]> { 1747 let Latency = 9; 1748 let NumMicroOps = 4; 1749 let ResourceCycles = [2,1,1]; 1750} 1751def: InstRW<[SKXWriteResGroup143], (instregex "(V?)PHADDSWrm", 1752 "(V?)PHSUBSWrm")>; 1753 1754def SKXWriteResGroup146 : SchedWriteRes<[SKXPort1,SKXPort6,SKXPort23,SKXPort0156]> { 1755 let Latency = 9; 1756 let NumMicroOps = 5; 1757 let ResourceCycles = [1,2,1,1]; 1758} 1759def: InstRW<[SKXWriteResGroup146], (instregex "LAR(16|32|64)rm", 1760 "LSL(16|32|64)rm")>; 1761 1762def SKXWriteResGroup148 : SchedWriteRes<[SKXPort5,SKXPort23]> { 1763 let Latency = 10; 1764 let NumMicroOps = 2; 1765 let ResourceCycles = [1,1]; 1766} 1767def: InstRW<[SKXWriteResGroup148], (instrs VPCMPGTQYrm)>; 1768def: InstRW<[SKXWriteResGroup148], (instregex "(ADD|SUB|SUBR)_F(32|64)m", 1769 "ILD_F(16|32|64)m", 1770 "VALIGND(Z|Z256)rm(b?)i", 1771 "VALIGNQ(Z|Z256)rm(b?)i", 1772 "VPMAXSQ(Z|Z256)rm(b?)", 1773 "VPMAXUQ(Z|Z256)rm(b?)", 1774 "VPMINSQ(Z|Z256)rm(b?)", 1775 "VPMINUQ(Z|Z256)rm(b?)")>; 1776 1777def SKXWriteResGroup148_2 : SchedWriteRes<[SKXPort5,SKXPort23]> { 1778 let Latency = 11; 1779 let NumMicroOps = 2; 1780 let ResourceCycles = [1,1]; 1781} 1782def: InstRW<[SKXWriteResGroup148_2], (instregex "VCMPPD(Z|Z256)rm(b?)i", 1783 "VCMPPS(Z|Z256)rm(b?)i", 1784 "VFPCLASSPD(Z|Z256)rm(b?)", 1785 "VFPCLASSPS(Z|Z256)rm(b?)", 1786 "VPCMPB(Z|Z256)rmi(b?)", 1787 "VPCMPD(Z|Z256)rmi(b?)", 1788 "VPCMPEQB(Z|Z256)rm(b?)", 1789 "VPCMPEQD(Z|Z256)rm(b?)", 1790 "VPCMPEQQ(Z|Z256)rm(b?)", 1791 "VPCMPEQW(Z|Z256)rm(b?)", 1792 "VPCMPGTB(Z|Z256)rm(b?)", 1793 "VPCMPGTD(Z|Z256)rm(b?)", 1794 "VPCMPGTQ(Z|Z256)rm(b?)", 1795 "VPCMPGTW(Z|Z256)rm(b?)", 1796 "VPCMPQ(Z|Z256)rmi(b?)", 1797 "VPCMPU(B|D|Q|W)Z256rmi(b?)", 1798 "VPCMPU(B|D|Q|W)Zrmi(b?)", 1799 "VPCMPW(Z|Z256)rmi(b?)", 1800 "VPTESTM(B|D|Q|W)Z256rm(b?)", 1801 "VPTESTM(B|D|Q|W)Zrm(b?)", 1802 "VPTESTNM(B|D|Q|W)Z256rm(b?)", 1803 "VPTESTNM(B|D|Q|W)Zrm(b?)")>; 1804 1805def SKXWriteResGroup149 : SchedWriteRes<[SKXPort23,SKXPort015]> { 1806 let Latency = 10; 1807 let NumMicroOps = 2; 1808 let ResourceCycles = [1,1]; 1809} 1810def: InstRW<[SKXWriteResGroup149], (instregex "VCVTDQ2PDZ128rm(b?)", 1811 "VCVTDQ2PSZ128rm(b?)", 1812 "(V?)CVTDQ2PSrm", 1813 "VCVTPD2QQZ128rm(b?)", 1814 "VCVTPD2UQQZ128rm(b?)", 1815 "VCVTPH2PSZ128rm(b?)", 1816 "VCVTPS2DQZ128rm(b?)", 1817 "(V?)CVTPS2DQrm", 1818 "VCVTPS2PDZ128rm(b?)", 1819 "VCVTPS2QQZ128rm(b?)", 1820 "VCVTPS2UDQZ128rm(b?)", 1821 "VCVTPS2UQQZ128rm(b?)", 1822 "VCVTQQ2PDZ128rm(b?)", 1823 "VCVTQQ2PSZ128rm(b?)", 1824 "VCVTSS2SDZrm", 1825 "(V?)CVTSS2SDrm", 1826 "VCVTTPD2QQZ128rm(b?)", 1827 "VCVTTPD2UQQZ128rm(b?)", 1828 "VCVTTPS2DQZ128rm(b?)", 1829 "(V?)CVTTPS2DQrm", 1830 "VCVTTPS2QQZ128rm(b?)", 1831 "VCVTTPS2UDQZ128rm(b?)", 1832 "VCVTTPS2UQQZ128rm(b?)", 1833 "VCVTUDQ2PDZ128rm(b?)", 1834 "VCVTUDQ2PSZ128rm(b?)", 1835 "VCVTUQQ2PDZ128rm(b?)", 1836 "VCVTUQQ2PSZ128rm(b?)")>; 1837 1838def SKXWriteResGroup151 : SchedWriteRes<[SKXPort5,SKXPort23]> { 1839 let Latency = 10; 1840 let NumMicroOps = 3; 1841 let ResourceCycles = [2,1]; 1842} 1843def: InstRW<[SKXWriteResGroup151], (instregex "VEXPANDPDZ128rm(b?)", 1844 "VEXPANDPSZ128rm(b?)", 1845 "VPEXPANDDZ128rm(b?)", 1846 "VPEXPANDQZ128rm(b?)")>; 1847 1848def SKXWriteResGroup153 : SchedWriteRes<[SKXPort5,SKXPort23,SKXPort015]> { 1849 let Latency = 10; 1850 let NumMicroOps = 3; 1851 let ResourceCycles = [1,1,1]; 1852} 1853def: InstRW<[SKXWriteResGroup153], (instregex "(V?)CVTSD2SSrm")>; 1854 1855def SKXWriteResGroup154 : SchedWriteRes<[SKXPort5,SKXPort01,SKXPort23]> { 1856 let Latency = 10; 1857 let NumMicroOps = 4; 1858 let ResourceCycles = [2,1,1]; 1859} 1860def: InstRW<[SKXWriteResGroup154], (instrs VPHADDSWYrm, 1861 VPHSUBSWYrm)>; 1862 1863def SKXWriteResGroup157 : SchedWriteRes<[SKXPort4,SKXPort6,SKXPort23,SKXPort237,SKXPort06,SKXPort0156]> { 1864 let Latency = 10; 1865 let NumMicroOps = 8; 1866 let ResourceCycles = [1,1,1,1,1,3]; 1867} 1868def: InstRW<[SKXWriteResGroup157], (instregex "XCHG(8|16|32|64)rm")>; 1869 1870def SKXWriteResGroup159 : SchedWriteRes<[SKXPort0,SKXFPDivider]> { 1871 let Latency = 11; 1872 let NumMicroOps = 1; 1873 let ResourceCycles = [1,3]; 1874} 1875def : SchedAlias<WriteFDivX, SKXWriteResGroup159>; // TODO - convert to ZnWriteResFpuPair 1876 1877def SKXWriteResGroup160 : SchedWriteRes<[SKXPort0,SKXPort23]> { 1878 let Latency = 11; 1879 let NumMicroOps = 2; 1880 let ResourceCycles = [1,1]; 1881} 1882def: InstRW<[SKXWriteResGroup160], (instregex "MUL_F(32|64)m")>; 1883 1884def SKXWriteResGroup161 : SchedWriteRes<[SKXPort23,SKXPort015]> { 1885 let Latency = 11; 1886 let NumMicroOps = 2; 1887 let ResourceCycles = [1,1]; 1888} 1889def: InstRW<[SKXWriteResGroup161], (instrs VCVTDQ2PSYrm, 1890 VCVTPS2PDYrm)>; 1891def: InstRW<[SKXWriteResGroup161], (instregex "VCVTDQ2(PD|PS)(Z|Z256)rm(b?)", 1892 "VCVTPH2PS(Z|Z256)rm(b?)", 1893 "VCVTPS2PD(Z|Z256)rm(b?)", 1894 "VCVTQQ2PD(Z|Z256)rm(b?)", 1895 "VCVTQQ2PSZ256rm(b?)", 1896 "VCVT(T?)PD2QQ(Z|Z256)rm(b?)", 1897 "VCVT(T?)PD2UQQ(Z|Z256)rm(b?)", 1898 "VCVT(T?)PS2DQYrm", 1899 "VCVT(T?)PS2DQ(Z|Z256)rm(b?)", 1900 "VCVT(T?)PS2QQZ256rm(b?)", 1901 "VCVT(T?)PS2UDQ(Z|Z256)rm(b?)", 1902 "VCVT(T?)PS2UQQZ256rm(b?)", 1903 "VCVTUDQ2(PD|PS)(Z|Z256)rm(b?)", 1904 "VCVTUQQ2PD(Z|Z256)rm(b?)", 1905 "VCVTUQQ2PSZ256rm(b?)")>; 1906 1907def SKXWriteResGroup162 : SchedWriteRes<[SKXPort5,SKXPort23]> { 1908 let Latency = 11; 1909 let NumMicroOps = 3; 1910 let ResourceCycles = [2,1]; 1911} 1912def: InstRW<[SKXWriteResGroup162], (instregex "FICOM(P?)(16|32)m", 1913 "VEXPANDPD(Z|Z256)rm(b?)", 1914 "VEXPANDPS(Z|Z256)rm(b?)", 1915 "VPEXPANDD(Z|Z256)rm(b?)", 1916 "VPEXPANDQ(Z|Z256)rm(b?)")>; 1917 1918def SKXWriteResGroup163 : SchedWriteRes<[SKXPort23,SKXPort015]> { 1919 let Latency = 11; 1920 let NumMicroOps = 3; 1921 let ResourceCycles = [1,2]; 1922} 1923def: InstRW<[SKXWriteResGroup163], (instregex "VCVTSD2SSZrm")>; 1924 1925def SKXWriteResGroup164 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort23]> { 1926 let Latency = 11; 1927 let NumMicroOps = 3; 1928 let ResourceCycles = [1,1,1]; 1929} 1930def: InstRW<[SKXWriteResGroup164], (instregex "(V?)CVTDQ2PDrm")>; 1931 1932def SKXWriteResGroup166 : SchedWriteRes<[SKXPort5,SKXPort23,SKXPort015]> { 1933 let Latency = 11; 1934 let NumMicroOps = 3; 1935 let ResourceCycles = [1,1,1]; 1936} 1937def: InstRW<[SKXWriteResGroup166], (instrs CVTPD2PSrm, 1938 CVTPD2DQrm, 1939 CVTTPD2DQrm, 1940 MMX_CVTPD2PIirm, 1941 MMX_CVTTPD2PIirm)>; 1942 1943def SKXWriteResGroup167 : SchedWriteRes<[SKXPort5,SKXPort23,SKXPort015]> { 1944 let Latency = 11; 1945 let NumMicroOps = 4; 1946 let ResourceCycles = [2,1,1]; 1947} 1948def: InstRW<[SKXWriteResGroup167], (instregex "VPCONFLICTQZ128rm(b?)")>; 1949 1950def SKXWriteResGroup169 : SchedWriteRes<[SKXPort1,SKXPort06,SKXPort0156]> { 1951 let Latency = 11; 1952 let NumMicroOps = 7; 1953 let ResourceCycles = [2,3,2]; 1954} 1955def: InstRW<[SKXWriteResGroup169], (instregex "RCL(16|32|64)rCL", 1956 "RCR(16|32|64)rCL")>; 1957 1958def SKXWriteResGroup170 : SchedWriteRes<[SKXPort1,SKXPort06,SKXPort15,SKXPort0156]> { 1959 let Latency = 11; 1960 let NumMicroOps = 9; 1961 let ResourceCycles = [1,5,1,2]; 1962} 1963def: InstRW<[SKXWriteResGroup170], (instrs RCL8rCL)>; 1964 1965def SKXWriteResGroup171 : SchedWriteRes<[SKXPort06,SKXPort0156]> { 1966 let Latency = 11; 1967 let NumMicroOps = 11; 1968 let ResourceCycles = [2,9]; 1969} 1970def: InstRW<[SKXWriteResGroup171], (instrs LOOPE, LOOPNE)>; 1971 1972def SKXWriteResGroup174 : SchedWriteRes<[SKXPort01]> { 1973 let Latency = 15; 1974 let NumMicroOps = 3; 1975 let ResourceCycles = [3]; 1976} 1977def: InstRW<[SKXWriteResGroup174], (instregex "VPMULLQ(Z128|Z256)rr")>; 1978 1979def SKXWriteResGroup174z : SchedWriteRes<[SKXPort05]> { 1980 let Latency = 15; 1981 let NumMicroOps = 3; 1982 let ResourceCycles = [3]; 1983} 1984def: InstRW<[SKXWriteResGroup174z], (instregex "VPMULLQZrr")>; 1985 1986def SKXWriteResGroup175 : SchedWriteRes<[SKXPort5,SKXPort23]> { 1987 let Latency = 12; 1988 let NumMicroOps = 3; 1989 let ResourceCycles = [2,1]; 1990} 1991def: InstRW<[SKXWriteResGroup175], (instregex "VPERMWZ128rm(b?)")>; 1992 1993def SKXWriteResGroup176 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort015]> { 1994 let Latency = 12; 1995 let NumMicroOps = 3; 1996 let ResourceCycles = [1,1,1]; 1997} 1998def: InstRW<[SKXWriteResGroup176], (instregex "VCVT(T?)SD2USIZrm(b?)", 1999 "VCVT(T?)SS2USI64Zrm(b?)")>; 2000 2001def SKXWriteResGroup177 : SchedWriteRes<[SKXPort5,SKXPort23,SKXPort015]> { 2002 let Latency = 12; 2003 let NumMicroOps = 3; 2004 let ResourceCycles = [1,1,1]; 2005} 2006def: InstRW<[SKXWriteResGroup177], (instregex "VCVT(T?)PS2QQZrm(b?)", 2007 "VCVT(T?)PS2UQQZrm(b?)")>; 2008 2009def SKXWriteResGroup179 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort23,SKXPort015]> { 2010 let Latency = 12; 2011 let NumMicroOps = 4; 2012 let ResourceCycles = [1,1,1,1]; 2013} 2014def: InstRW<[SKXWriteResGroup179], (instregex "CVTTSS2SI64rm")>; 2015 2016def SKXWriteResGroup180 : SchedWriteRes<[SKXPort5,SKXPort23]> { 2017 let Latency = 13; 2018 let NumMicroOps = 3; 2019 let ResourceCycles = [2,1]; 2020} 2021def: InstRW<[SKXWriteResGroup180], (instregex "(ADD|SUB|SUBR)_FI(16|32)m", 2022 "VPERMWZ256rm(b?)", 2023 "VPERMWZrm(b?)")>; 2024 2025def SKXWriteResGroup181 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort23]> { 2026 let Latency = 13; 2027 let NumMicroOps = 3; 2028 let ResourceCycles = [1,1,1]; 2029} 2030def: InstRW<[SKXWriteResGroup181], (instrs VCVTDQ2PDYrm)>; 2031 2032def SKXWriteResGroup183 : SchedWriteRes<[SKXPort5,SKXPort23,SKXPort015]> { 2033 let Latency = 13; 2034 let NumMicroOps = 4; 2035 let ResourceCycles = [2,1,1]; 2036} 2037def: InstRW<[SKXWriteResGroup183], (instregex "VPERMI2W128rm(b?)", 2038 "VPERMT2W128rm(b?)")>; 2039 2040def SKXWriteResGroup184 : SchedWriteRes<[SKXPort0,SKXFPDivider]> { 2041 let Latency = 14; 2042 let NumMicroOps = 1; 2043 let ResourceCycles = [1,3]; 2044} 2045def : SchedAlias<WriteFDiv64, SKXWriteResGroup184>; // TODO - convert to ZnWriteResFpuPair 2046def : SchedAlias<WriteFDiv64X, SKXWriteResGroup184>; // TODO - convert to ZnWriteResFpuPair 2047 2048def SKXWriteResGroup184_1 : SchedWriteRes<[SKXPort0,SKXFPDivider]> { 2049 let Latency = 14; 2050 let NumMicroOps = 1; 2051 let ResourceCycles = [1,5]; 2052} 2053def : SchedAlias<WriteFDiv64Y, SKXWriteResGroup184_1>; // TODO - convert to ZnWriteResFpuPair 2054 2055def SKXWriteResGroup187 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort23]> { 2056 let Latency = 14; 2057 let NumMicroOps = 3; 2058 let ResourceCycles = [1,1,1]; 2059} 2060def: InstRW<[SKXWriteResGroup187], (instregex "MUL_FI(16|32)m")>; 2061 2062def SKXWriteResGroup188 : SchedWriteRes<[SKXPort5,SKXPort23,SKXPort015]> { 2063 let Latency = 14; 2064 let NumMicroOps = 3; 2065 let ResourceCycles = [1,1,1]; 2066} 2067def: InstRW<[SKXWriteResGroup188], (instregex "VCVTPD2DQZrm(b?)", 2068 "VCVTPD2PSZrm(b?)", 2069 "VCVTPD2UDQZrm(b?)", 2070 "VCVTQQ2PSZrm(b?)", 2071 "VCVTTPD2DQZrm(b?)", 2072 "VCVTTPD2UDQZrm(b?)", 2073 "VCVTUQQ2PSZrm(b?)")>; 2074 2075def SKXWriteResGroup189 : SchedWriteRes<[SKXPort5,SKXPort23,SKXPort015]> { 2076 let Latency = 14; 2077 let NumMicroOps = 4; 2078 let ResourceCycles = [2,1,1]; 2079} 2080def: InstRW<[SKXWriteResGroup189], (instregex "VPERMI2W256rm(b?)", 2081 "VPERMI2Wrm(b?)", 2082 "VPERMT2W256rm(b?)", 2083 "VPERMT2Wrm(b?)")>; 2084 2085def SKXWriteResGroup190 : SchedWriteRes<[SKXPort1,SKXPort06,SKXPort15,SKXPort0156]> { 2086 let Latency = 14; 2087 let NumMicroOps = 10; 2088 let ResourceCycles = [2,4,1,3]; 2089} 2090def: InstRW<[SKXWriteResGroup190], (instrs RCR8rCL)>; 2091 2092def SKXWriteResGroup191 : SchedWriteRes<[SKXPort0]> { 2093 let Latency = 15; 2094 let NumMicroOps = 1; 2095 let ResourceCycles = [1]; 2096} 2097def: InstRW<[SKXWriteResGroup191], (instregex "DIVR_(FPrST0|FST0r|FrST0)")>; 2098 2099def SKXWriteResGroup194 : SchedWriteRes<[SKXPort1,SKXPort5,SKXPort01,SKXPort23,SKXPort015]> { 2100 let Latency = 15; 2101 let NumMicroOps = 8; 2102 let ResourceCycles = [1,2,2,1,2]; 2103} 2104def: InstRW<[SKXWriteResGroup194], (instregex "VPCONFLICTDZ128rm(b?)")>; 2105 2106def SKXWriteResGroup195 : SchedWriteRes<[SKXPort1,SKXPort23,SKXPort237,SKXPort06,SKXPort15,SKXPort0156]> { 2107 let Latency = 15; 2108 let NumMicroOps = 10; 2109 let ResourceCycles = [1,1,1,5,1,1]; 2110} 2111def: InstRW<[SKXWriteResGroup195], (instregex "RCL(8|16|32|64)mCL")>; 2112 2113def SKXWriteResGroup199 : SchedWriteRes<[SKXPort4,SKXPort23,SKXPort237,SKXPort06,SKXPort15,SKXPort0156]> { 2114 let Latency = 16; 2115 let NumMicroOps = 14; 2116 let ResourceCycles = [1,1,1,4,2,5]; 2117} 2118def: InstRW<[SKXWriteResGroup199], (instrs CMPXCHG8B)>; 2119 2120def SKXWriteResGroup200 : SchedWriteRes<[SKXPort1, SKXPort05, SKXPort6]> { 2121 let Latency = 12; 2122 let NumMicroOps = 34; 2123 let ResourceCycles = [1, 4, 5]; 2124} 2125def: InstRW<[SKXWriteResGroup200], (instrs VZEROALL)>; 2126 2127def SKXWriteResGroup201 : SchedWriteRes<[SKXPort0,SKXPort23,SKXFPDivider]> { 2128 let Latency = 17; 2129 let NumMicroOps = 2; 2130 let ResourceCycles = [1,1,5]; 2131} 2132def : SchedAlias<WriteFDivXLd, SKXWriteResGroup201>; // TODO - convert to ZnWriteResFpuPair 2133 2134def SKXWriteResGroup202 : SchedWriteRes<[SKXPort0,SKXPort1,SKXPort5,SKXPort6,SKXPort05,SKXPort0156]> { 2135 let Latency = 17; 2136 let NumMicroOps = 15; 2137 let ResourceCycles = [2,1,2,4,2,4]; 2138} 2139def: InstRW<[SKXWriteResGroup202], (instrs XCH_F)>; 2140 2141def SKXWriteResGroup205 : SchedWriteRes<[SKXPort23,SKXPort01]> { 2142 let Latency = 21; 2143 let NumMicroOps = 4; 2144 let ResourceCycles = [1,3]; 2145} 2146def: InstRW<[SKXWriteResGroup205], (instregex "VPMULLQZ128rm(b?)")>; 2147 2148def SKXWriteResGroup207 : SchedWriteRes<[SKXPort5,SKXPort6,SKXPort06,SKXPort0156]> { 2149 let Latency = 18; 2150 let NumMicroOps = 8; 2151 let ResourceCycles = [1,1,1,5]; 2152} 2153def: InstRW<[SKXWriteResGroup207], (instrs CPUID, RDTSC)>; 2154 2155def SKXWriteResGroup208 : SchedWriteRes<[SKXPort1,SKXPort23,SKXPort237,SKXPort06,SKXPort15,SKXPort0156]> { 2156 let Latency = 18; 2157 let NumMicroOps = 11; 2158 let ResourceCycles = [2,1,1,4,1,2]; 2159} 2160def: InstRW<[SKXWriteResGroup208], (instregex "RCR(8|16|32|64)mCL")>; 2161 2162def SKXWriteResGroup209 : SchedWriteRes<[SKXPort0,SKXPort23,SKXFPDivider]> { 2163 let Latency = 19; 2164 let NumMicroOps = 2; 2165 let ResourceCycles = [1,1,4]; 2166} 2167def : SchedAlias<WriteFDiv64Ld, SKXWriteResGroup209>; // TODO - convert to ZnWriteResFpuPair 2168 2169def SKXWriteResGroup211 : SchedWriteRes<[SKXPort23,SKXPort01]> { 2170 let Latency = 22; 2171 let NumMicroOps = 4; 2172 let ResourceCycles = [1,3]; 2173} 2174def: InstRW<[SKXWriteResGroup211], (instregex "VPMULLQZ256rm(b?)")>; 2175 2176def SKXWriteResGroup211_1 : SchedWriteRes<[SKXPort23,SKXPort05]> { 2177 let Latency = 22; 2178 let NumMicroOps = 4; 2179 let ResourceCycles = [1,3]; 2180} 2181def: InstRW<[SKXWriteResGroup211_1], (instregex "VPMULLQZrm(b?)")>; 2182 2183def SKXWriteResGroup215 : SchedWriteRes<[SKXPort0]> { 2184 let Latency = 20; 2185 let NumMicroOps = 1; 2186 let ResourceCycles = [1]; 2187} 2188def: InstRW<[SKXWriteResGroup215], (instregex "DIV_(FPrST0|FST0r|FrST0)")>; 2189 2190def SKXWriteResGroup216 : SchedWriteRes<[SKXPort0,SKXPort23,SKXFPDivider]> { 2191 let Latency = 20; 2192 let NumMicroOps = 2; 2193 let ResourceCycles = [1,1,4]; 2194} 2195def : SchedAlias<WriteFDiv64XLd, SKXWriteResGroup216>; // TODO - convert to ZnWriteResFpuPair 2196 2197def SKXWriteGatherEVEX2 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort015,SKXPort0156]> { 2198 let Latency = 17; 2199 let NumMicroOps = 5; // 2 uops perform multiple loads 2200 let ResourceCycles = [1,2,1,1]; 2201} 2202def: InstRW<[SKXWriteGatherEVEX2], (instrs VGATHERQPSZ128rm, VPGATHERQDZ128rm, 2203 VGATHERDPDZ128rm, VPGATHERDQZ128rm, 2204 VGATHERQPDZ128rm, VPGATHERQQZ128rm)>; 2205 2206def SKXWriteGatherEVEX4 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort015,SKXPort0156]> { 2207 let Latency = 19; 2208 let NumMicroOps = 5; // 2 uops perform multiple loads 2209 let ResourceCycles = [1,4,1,1]; 2210} 2211def: InstRW<[SKXWriteGatherEVEX4], (instrs VGATHERQPSZ256rm, VPGATHERQDZ256rm, 2212 VGATHERQPDZ256rm, VPGATHERQQZ256rm, 2213 VGATHERDPSZ128rm, VPGATHERDDZ128rm, 2214 VGATHERDPDZ256rm, VPGATHERDQZ256rm)>; 2215 2216def SKXWriteGatherEVEX8 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort015,SKXPort0156]> { 2217 let Latency = 21; 2218 let NumMicroOps = 5; // 2 uops perform multiple loads 2219 let ResourceCycles = [1,8,1,1]; 2220} 2221def: InstRW<[SKXWriteGatherEVEX8], (instrs VGATHERDPSZ256rm, VPGATHERDDZ256rm, 2222 VGATHERDPDZrm, VPGATHERDQZrm, 2223 VGATHERQPDZrm, VPGATHERQQZrm, 2224 VGATHERQPSZrm, VPGATHERQDZrm)>; 2225 2226def SKXWriteGatherEVEX16 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort015,SKXPort0156]> { 2227 let Latency = 25; 2228 let NumMicroOps = 5; // 2 uops perform multiple loads 2229 let ResourceCycles = [1,16,1,1]; 2230} 2231def: InstRW<[SKXWriteGatherEVEX16], (instrs VGATHERDPSZrm, VPGATHERDDZrm)>; 2232 2233def SKXWriteResGroup219 : SchedWriteRes<[SKXPort4,SKXPort5,SKXPort6,SKXPort23,SKXPort237,SKXPort06,SKXPort0156]> { 2234 let Latency = 20; 2235 let NumMicroOps = 8; 2236 let ResourceCycles = [1,1,1,1,1,1,2]; 2237} 2238def: InstRW<[SKXWriteResGroup219], (instrs INSB, INSL, INSW)>; 2239 2240def SKXWriteResGroup220 : SchedWriteRes<[SKXPort5,SKXPort6,SKXPort0156]> { 2241 let Latency = 20; 2242 let NumMicroOps = 10; 2243 let ResourceCycles = [1,2,7]; 2244} 2245def: InstRW<[SKXWriteResGroup220], (instrs MWAITrr)>; 2246 2247def SKXWriteResGroup222 : SchedWriteRes<[SKXPort0,SKXPort23,SKXFPDivider]> { 2248 let Latency = 21; 2249 let NumMicroOps = 2; 2250 let ResourceCycles = [1,1,8]; 2251} 2252def : SchedAlias<WriteFDiv64YLd, SKXWriteResGroup222>; // TODO - convert to ZnWriteResFpuPair 2253 2254def SKXWriteResGroup223 : SchedWriteRes<[SKXPort0,SKXPort23]> { 2255 let Latency = 22; 2256 let NumMicroOps = 2; 2257 let ResourceCycles = [1,1]; 2258} 2259def: InstRW<[SKXWriteResGroup223], (instregex "DIV_F(32|64)m")>; 2260 2261def SKXWriteResGroupVEX2 : SchedWriteRes<[SKXPort0, SKXPort23, SKXPort5, SKXPort015]> { 2262 let Latency = 18; 2263 let NumMicroOps = 5; // 2 uops perform multiple loads 2264 let ResourceCycles = [1,2,1,1]; 2265} 2266def: InstRW<[SKXWriteResGroupVEX2], (instrs VGATHERDPDrm, VPGATHERDQrm, 2267 VGATHERQPDrm, VPGATHERQQrm, 2268 VGATHERQPSrm, VPGATHERQDrm)>; 2269 2270def SKXWriteResGroupVEX4 : SchedWriteRes<[SKXPort0, SKXPort23, SKXPort5, SKXPort015]> { 2271 let Latency = 20; 2272 let NumMicroOps = 5; // 2 uops peform multiple loads 2273 let ResourceCycles = [1,4,1,1]; 2274} 2275def: InstRW<[SKXWriteResGroupVEX4], (instrs VGATHERDPDYrm, VPGATHERDQYrm, 2276 VGATHERDPSrm, VPGATHERDDrm, 2277 VGATHERQPDYrm, VPGATHERQQYrm, 2278 VGATHERQPSYrm, VPGATHERQDYrm)>; 2279 2280def SKXWriteResGroupVEX8 : SchedWriteRes<[SKXPort0, SKXPort23, SKXPort5, SKXPort015]> { 2281 let Latency = 22; 2282 let NumMicroOps = 5; // 2 uops perform multiple loads 2283 let ResourceCycles = [1,8,1,1]; 2284} 2285def: InstRW<[SKXWriteResGroupVEX8], (instrs VGATHERDPSYrm, VPGATHERDDYrm)>; 2286 2287def SKXWriteResGroup225 : SchedWriteRes<[SKXPort5,SKXPort01,SKXPort015]> { 2288 let Latency = 22; 2289 let NumMicroOps = 14; 2290 let ResourceCycles = [5,5,4]; 2291} 2292def: InstRW<[SKXWriteResGroup225], (instregex "VPCONFLICTDZ128rr", 2293 "VPCONFLICTQZ256rr")>; 2294 2295def SKXWriteResGroup228 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort5,SKXPort23,SKXPort237,SKXPort06,SKXPort0156]> { 2296 let Latency = 23; 2297 let NumMicroOps = 19; 2298 let ResourceCycles = [2,1,4,1,1,4,6]; 2299} 2300def: InstRW<[SKXWriteResGroup228], (instrs CMPXCHG16B)>; 2301 2302def SKXWriteResGroup233 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort23]> { 2303 let Latency = 25; 2304 let NumMicroOps = 3; 2305 let ResourceCycles = [1,1,1]; 2306} 2307def: InstRW<[SKXWriteResGroup233], (instregex "DIV_FI(16|32)m")>; 2308 2309def SKXWriteResGroup239 : SchedWriteRes<[SKXPort0,SKXPort23]> { 2310 let Latency = 27; 2311 let NumMicroOps = 2; 2312 let ResourceCycles = [1,1]; 2313} 2314def: InstRW<[SKXWriteResGroup239], (instregex "DIVR_F(32|64)m")>; 2315 2316def SKXWriteResGroup242 : SchedWriteRes<[SKXPort5,SKXPort01,SKXPort23,SKXPort015]> { 2317 let Latency = 29; 2318 let NumMicroOps = 15; 2319 let ResourceCycles = [5,5,1,4]; 2320} 2321def: InstRW<[SKXWriteResGroup242], (instregex "VPCONFLICTQZ256rm(b?)")>; 2322 2323def SKXWriteResGroup243 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort23]> { 2324 let Latency = 30; 2325 let NumMicroOps = 3; 2326 let ResourceCycles = [1,1,1]; 2327} 2328def: InstRW<[SKXWriteResGroup243], (instregex "DIVR_FI(16|32)m")>; 2329 2330def SKXWriteResGroup247 : SchedWriteRes<[SKXPort5,SKXPort6,SKXPort23,SKXPort06,SKXPort0156]> { 2331 let Latency = 35; 2332 let NumMicroOps = 23; 2333 let ResourceCycles = [1,5,3,4,10]; 2334} 2335def: InstRW<[SKXWriteResGroup247], (instregex "IN(8|16|32)ri", 2336 "IN(8|16|32)rr")>; 2337 2338def SKXWriteResGroup248 : SchedWriteRes<[SKXPort5,SKXPort6,SKXPort23,SKXPort237,SKXPort06,SKXPort0156]> { 2339 let Latency = 35; 2340 let NumMicroOps = 23; 2341 let ResourceCycles = [1,5,2,1,4,10]; 2342} 2343def: InstRW<[SKXWriteResGroup248], (instregex "OUT(8|16|32)ir", 2344 "OUT(8|16|32)rr")>; 2345 2346def SKXWriteResGroup249 : SchedWriteRes<[SKXPort5,SKXPort01,SKXPort015]> { 2347 let Latency = 37; 2348 let NumMicroOps = 21; 2349 let ResourceCycles = [9,7,5]; 2350} 2351def: InstRW<[SKXWriteResGroup249], (instregex "VPCONFLICTDZ256rr", 2352 "VPCONFLICTQZrr")>; 2353 2354def SKXWriteResGroup250 : SchedWriteRes<[SKXPort1,SKXPort6,SKXPort23,SKXPort0156]> { 2355 let Latency = 37; 2356 let NumMicroOps = 31; 2357 let ResourceCycles = [1,8,1,21]; 2358} 2359def: InstRW<[SKXWriteResGroup250], (instregex "XRSTOR(64)?")>; 2360 2361def SKXWriteResGroup252 : SchedWriteRes<[SKXPort1,SKXPort4,SKXPort5,SKXPort6,SKXPort23,SKXPort237,SKXPort15,SKXPort0156]> { 2362 let Latency = 40; 2363 let NumMicroOps = 18; 2364 let ResourceCycles = [1,1,2,3,1,1,1,8]; 2365} 2366def: InstRW<[SKXWriteResGroup252], (instrs VMCLEARm)>; 2367 2368def SKXWriteResGroup253 : SchedWriteRes<[SKXPort4,SKXPort6,SKXPort23,SKXPort237,SKXPort0156]> { 2369 let Latency = 41; 2370 let NumMicroOps = 39; 2371 let ResourceCycles = [1,10,1,1,26]; 2372} 2373def: InstRW<[SKXWriteResGroup253], (instrs XSAVE64)>; 2374 2375def SKXWriteResGroup254 : SchedWriteRes<[SKXPort5,SKXPort0156]> { 2376 let Latency = 42; 2377 let NumMicroOps = 22; 2378 let ResourceCycles = [2,20]; 2379} 2380def: InstRW<[SKXWriteResGroup254], (instrs RDTSCP)>; 2381 2382def SKXWriteResGroup255 : SchedWriteRes<[SKXPort4,SKXPort6,SKXPort23,SKXPort237,SKXPort0156]> { 2383 let Latency = 42; 2384 let NumMicroOps = 40; 2385 let ResourceCycles = [1,11,1,1,26]; 2386} 2387def: InstRW<[SKXWriteResGroup255], (instrs XSAVE)>; 2388def: InstRW<[SKXWriteResGroup255], (instregex "XSAVEC", "XSAVES", "XSAVEOPT")>; 2389 2390def SKXWriteResGroup256 : SchedWriteRes<[SKXPort5,SKXPort01,SKXPort23,SKXPort015]> { 2391 let Latency = 44; 2392 let NumMicroOps = 22; 2393 let ResourceCycles = [9,7,1,5]; 2394} 2395def: InstRW<[SKXWriteResGroup256], (instregex "VPCONFLICTDZ256rm(b?)", 2396 "VPCONFLICTQZrm(b?)")>; 2397 2398def SKXWriteResGroup258 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort05,SKXPort06,SKXPort0156]> { 2399 let Latency = 62; 2400 let NumMicroOps = 64; 2401 let ResourceCycles = [2,8,5,10,39]; 2402} 2403def: InstRW<[SKXWriteResGroup258], (instrs FLDENVm)>; 2404 2405def SKXWriteResGroup259 : SchedWriteRes<[SKXPort0,SKXPort6,SKXPort23,SKXPort05,SKXPort06,SKXPort15,SKXPort0156]> { 2406 let Latency = 63; 2407 let NumMicroOps = 88; 2408 let ResourceCycles = [4,4,31,1,2,1,45]; 2409} 2410def: InstRW<[SKXWriteResGroup259], (instrs FXRSTOR64)>; 2411 2412def SKXWriteResGroup260 : SchedWriteRes<[SKXPort0,SKXPort6,SKXPort23,SKXPort05,SKXPort06,SKXPort15,SKXPort0156]> { 2413 let Latency = 63; 2414 let NumMicroOps = 90; 2415 let ResourceCycles = [4,2,33,1,2,1,47]; 2416} 2417def: InstRW<[SKXWriteResGroup260], (instrs FXRSTOR)>; 2418 2419def SKXWriteResGroup261 : SchedWriteRes<[SKXPort5,SKXPort01,SKXPort015]> { 2420 let Latency = 67; 2421 let NumMicroOps = 35; 2422 let ResourceCycles = [17,11,7]; 2423} 2424def: InstRW<[SKXWriteResGroup261], (instregex "VPCONFLICTDZrr")>; 2425 2426def SKXWriteResGroup262 : SchedWriteRes<[SKXPort5,SKXPort01,SKXPort23,SKXPort015]> { 2427 let Latency = 74; 2428 let NumMicroOps = 36; 2429 let ResourceCycles = [17,11,1,7]; 2430} 2431def: InstRW<[SKXWriteResGroup262], (instregex "VPCONFLICTDZrm(b?)")>; 2432 2433def SKXWriteResGroup263 : SchedWriteRes<[SKXPort5,SKXPort05,SKXPort0156]> { 2434 let Latency = 75; 2435 let NumMicroOps = 15; 2436 let ResourceCycles = [6,3,6]; 2437} 2438def: InstRW<[SKXWriteResGroup263], (instrs FNINIT)>; 2439 2440def SKXWriteResGroup266 : SchedWriteRes<[SKXPort0,SKXPort1,SKXPort4,SKXPort5,SKXPort6,SKXPort237,SKXPort06,SKXPort0156]> { 2441 let Latency = 106; 2442 let NumMicroOps = 100; 2443 let ResourceCycles = [9,1,11,16,1,11,21,30]; 2444} 2445def: InstRW<[SKXWriteResGroup266], (instrs FSTENVm)>; 2446 2447def SKXWriteResGroup267 : SchedWriteRes<[SKXPort6,SKXPort0156]> { 2448 let Latency = 140; 2449 let NumMicroOps = 4; 2450 let ResourceCycles = [1,3]; 2451} 2452def: InstRW<[SKXWriteResGroup267], (instrs PAUSE)>; 2453 2454def: InstRW<[WriteZero], (instrs CLC)>; 2455 2456 2457// Instruction variants handled by the renamer. These might not need execution 2458// ports in certain conditions. 2459// See Agner's Fog "The microarchitecture of Intel, AMD and VIA CPUs", 2460// section "Skylake Pipeline" > "Register allocation and renaming". 2461// These can be investigated with llvm-exegesis, e.g. 2462// echo 'pxor %mm0, %mm0' | /tmp/llvm-exegesis -mode=uops -snippets-file=- 2463// echo 'vxorpd %xmm0, %xmm0, %xmm1' | /tmp/llvm-exegesis -mode=uops -snippets-file=- 2464 2465def SKXWriteZeroLatency : SchedWriteRes<[]> { 2466 let Latency = 0; 2467} 2468 2469def SKXWriteZeroIdiom : SchedWriteVariant<[ 2470 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKXWriteZeroLatency]>, 2471 SchedVar<NoSchedPred, [WriteALU]> 2472]>; 2473def : InstRW<[SKXWriteZeroIdiom], (instrs SUB32rr, SUB64rr, 2474 XOR32rr, XOR64rr)>; 2475 2476def SKXWriteFZeroIdiom : SchedWriteVariant<[ 2477 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKXWriteZeroLatency]>, 2478 SchedVar<NoSchedPred, [WriteFLogic]> 2479]>; 2480def : InstRW<[SKXWriteFZeroIdiom], (instrs XORPSrr, VXORPSrr, 2481 XORPDrr, VXORPDrr, 2482 VXORPSZ128rr, 2483 VXORPDZ128rr)>; 2484 2485def SKXWriteFZeroIdiomY : SchedWriteVariant<[ 2486 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKXWriteZeroLatency]>, 2487 SchedVar<NoSchedPred, [WriteFLogicY]> 2488]>; 2489def : InstRW<[SKXWriteFZeroIdiomY], (instrs VXORPSYrr, VXORPDYrr, 2490 VXORPSZ256rr, VXORPDZ256rr)>; 2491 2492def SKXWriteFZeroIdiomZ : SchedWriteVariant<[ 2493 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKXWriteZeroLatency]>, 2494 SchedVar<NoSchedPred, [WriteFLogicZ]> 2495]>; 2496def : InstRW<[SKXWriteFZeroIdiomZ], (instrs VXORPSZrr, VXORPDZrr)>; 2497 2498def SKXWriteVZeroIdiomLogicX : SchedWriteVariant<[ 2499 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKXWriteZeroLatency]>, 2500 SchedVar<NoSchedPred, [WriteVecLogicX]> 2501]>; 2502def : InstRW<[SKXWriteVZeroIdiomLogicX], (instrs PXORrr, VPXORrr, 2503 VPXORDZ128rr, VPXORQZ128rr)>; 2504 2505def SKXWriteVZeroIdiomLogicY : SchedWriteVariant<[ 2506 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKXWriteZeroLatency]>, 2507 SchedVar<NoSchedPred, [WriteVecLogicY]> 2508]>; 2509def : InstRW<[SKXWriteVZeroIdiomLogicY], (instrs VPXORYrr, 2510 VPXORDZ256rr, VPXORQZ256rr)>; 2511 2512def SKXWriteVZeroIdiomLogicZ : SchedWriteVariant<[ 2513 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKXWriteZeroLatency]>, 2514 SchedVar<NoSchedPred, [WriteVecLogicZ]> 2515]>; 2516def : InstRW<[SKXWriteVZeroIdiomLogicZ], (instrs VPXORDZrr, VPXORQZrr)>; 2517 2518def SKXWriteVZeroIdiomALUX : SchedWriteVariant<[ 2519 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKXWriteZeroLatency]>, 2520 SchedVar<NoSchedPred, [WriteVecALUX]> 2521]>; 2522def : InstRW<[SKXWriteVZeroIdiomALUX], (instrs PCMPGTBrr, VPCMPGTBrr, 2523 PCMPGTDrr, VPCMPGTDrr, 2524 PCMPGTWrr, VPCMPGTWrr)>; 2525 2526def SKXWriteVZeroIdiomALUY : SchedWriteVariant<[ 2527 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKXWriteZeroLatency]>, 2528 SchedVar<NoSchedPred, [WriteVecALUY]> 2529]>; 2530def : InstRW<[SKXWriteVZeroIdiomALUY], (instrs VPCMPGTBYrr, 2531 VPCMPGTDYrr, 2532 VPCMPGTWYrr)>; 2533 2534def SKXWritePSUB : SchedWriteRes<[SKXPort015]> { 2535 let Latency = 1; 2536 let NumMicroOps = 1; 2537 let ResourceCycles = [1]; 2538} 2539 2540def SKXWriteVZeroIdiomPSUB : SchedWriteVariant<[ 2541 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKXWriteZeroLatency]>, 2542 SchedVar<NoSchedPred, [SKXWritePSUB]> 2543]>; 2544 2545def : InstRW<[SKXWriteVZeroIdiomPSUB], (instrs PSUBBrr, VPSUBBrr, VPSUBBZ128rr, 2546 PSUBDrr, VPSUBDrr, VPSUBDZ128rr, 2547 PSUBQrr, VPSUBQrr, VPSUBQZ128rr, 2548 PSUBWrr, VPSUBWrr, VPSUBWZ128rr, 2549 VPSUBBYrr, VPSUBBZ256rr, 2550 VPSUBDYrr, VPSUBDZ256rr, 2551 VPSUBQYrr, VPSUBQZ256rr, 2552 VPSUBWYrr, VPSUBWZ256rr, 2553 VPSUBBZrr, 2554 VPSUBDZrr, 2555 VPSUBQZrr, 2556 VPSUBWZrr)>; 2557def SKXWritePCMPGTQ : SchedWriteRes<[SKXPort5]> { 2558 let Latency = 3; 2559 let NumMicroOps = 1; 2560 let ResourceCycles = [1]; 2561} 2562 2563def SKXWriteVZeroIdiomPCMPGTQ : SchedWriteVariant<[ 2564 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKXWriteZeroLatency]>, 2565 SchedVar<NoSchedPred, [SKXWritePCMPGTQ]> 2566]>; 2567def : InstRW<[SKXWriteVZeroIdiomPCMPGTQ], (instrs PCMPGTQrr, VPCMPGTQrr, 2568 VPCMPGTQYrr)>; 2569 2570 2571// CMOVs that use both Z and C flag require an extra uop. 2572def SKXWriteCMOVA_CMOVBErr : SchedWriteRes<[SKXPort06]> { 2573 let Latency = 2; 2574 let ResourceCycles = [2]; 2575 let NumMicroOps = 2; 2576} 2577 2578def SKXWriteCMOVA_CMOVBErm : SchedWriteRes<[SKXPort23,SKXPort06]> { 2579 let Latency = 7; 2580 let ResourceCycles = [1,2]; 2581 let NumMicroOps = 3; 2582} 2583 2584def SKXCMOVA_CMOVBErr : SchedWriteVariant<[ 2585 SchedVar<MCSchedPredicate<IsCMOVArr_Or_CMOVBErr>, [SKXWriteCMOVA_CMOVBErr]>, 2586 SchedVar<NoSchedPred, [WriteCMOV]> 2587]>; 2588 2589def SKXCMOVA_CMOVBErm : SchedWriteVariant<[ 2590 SchedVar<MCSchedPredicate<IsCMOVArm_Or_CMOVBErm>, [SKXWriteCMOVA_CMOVBErm]>, 2591 SchedVar<NoSchedPred, [WriteCMOV.Folded]> 2592]>; 2593 2594def : InstRW<[SKXCMOVA_CMOVBErr], (instrs CMOV16rr, CMOV32rr, CMOV64rr)>; 2595def : InstRW<[SKXCMOVA_CMOVBErm], (instrs CMOV16rm, CMOV32rm, CMOV64rm)>; 2596 2597// SETCCs that use both Z and C flag require an extra uop. 2598def SKXWriteSETA_SETBEr : SchedWriteRes<[SKXPort06]> { 2599 let Latency = 2; 2600 let ResourceCycles = [2]; 2601 let NumMicroOps = 2; 2602} 2603 2604def SKXWriteSETA_SETBEm : SchedWriteRes<[SKXPort4,SKXPort237,SKXPort06]> { 2605 let Latency = 3; 2606 let ResourceCycles = [1,1,2]; 2607 let NumMicroOps = 4; 2608} 2609 2610def SKXSETA_SETBErr : SchedWriteVariant<[ 2611 SchedVar<MCSchedPredicate<IsSETAr_Or_SETBEr>, [SKXWriteSETA_SETBEr]>, 2612 SchedVar<NoSchedPred, [WriteSETCC]> 2613]>; 2614 2615def SKXSETA_SETBErm : SchedWriteVariant<[ 2616 SchedVar<MCSchedPredicate<IsSETAm_Or_SETBEm>, [SKXWriteSETA_SETBEm]>, 2617 SchedVar<NoSchedPred, [WriteSETCCStore]> 2618]>; 2619 2620def : InstRW<[SKXSETA_SETBErr], (instrs SETCCr)>; 2621def : InstRW<[SKXSETA_SETBErm], (instrs SETCCm)>; 2622 2623} // SchedModel 2624