1; ## Full FP16 support enabled by default. 2; RUN: llc < %s -mtriple=nvptx64-nvidia-cuda -mcpu=sm_53 -asm-verbose=false \ 3; RUN: -O0 -disable-post-ra -frame-pointer=all -verify-machineinstrs \ 4; RUN: | FileCheck -check-prefixes CHECK,CHECK-NOFTZ,CHECK-F16-NOFTZ %s 5; ## Full FP16 with FTZ 6; RUN: llc < %s -mtriple=nvptx64-nvidia-cuda -mcpu=sm_53 -asm-verbose=false \ 7; RUN: -O0 -disable-post-ra -frame-pointer=all -verify-machineinstrs \ 8; RUN: -denormal-fp-math-f32=preserve-sign \ 9; RUN: | FileCheck -check-prefixes CHECK,CHECK-F16-FTZ %s 10; ## FP16 support explicitly disabled. 11; RUN: llc < %s -mtriple=nvptx64-nvidia-cuda -mcpu=sm_53 -asm-verbose=false \ 12; RUN: -O0 -disable-post-ra -frame-pointer=all --nvptx-no-f16-math \ 13; RUN: -verify-machineinstrs \ 14; RUN: | FileCheck -check-prefixes CHECK,CHECK-NOFTZ,CHECK-NOF16 %s 15; ## FP16 is not supported by hardware. 16; RUN: llc < %s -O0 -mtriple=nvptx64-nvidia-cuda -mcpu=sm_52 -asm-verbose=false \ 17; RUN: -disable-post-ra -frame-pointer=all -verify-machineinstrs \ 18; RUN: | FileCheck -check-prefixes CHECK,CHECK-NOFTZ,CHECK-NOF16 %s 19 20target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" 21 22; CHECK-LABEL: test_ret_const( 23; CHECK: mov.b16 [[R:%h[0-9]+]], 0x3C00; 24; CHECK-NEXT: st.param.b16 [func_retval0+0], [[R]]; 25; CHECK-NEXT: ret; 26define half @test_ret_const() #0 { 27 ret half 1.0 28} 29 30; CHECK-LABEL: test_fadd( 31; CHECK-DAG: ld.param.b16 [[A:%h[0-9]+]], [test_fadd_param_0]; 32; CHECK-DAG: ld.param.b16 [[B:%h[0-9]+]], [test_fadd_param_1]; 33; CHECK-F16-NOFTZ-NEXT: add.rn.f16 [[R:%h[0-9]+]], [[A]], [[B]]; 34; CHECK-F16-FTZ-NEXT: add.rn.ftz.f16 [[R:%h[0-9]+]], [[A]], [[B]]; 35; CHECK-NOF16-DAG: cvt.f32.f16 [[A32:%f[0-9]+]], [[A]] 36; CHECK-NOF16-DAG: cvt.f32.f16 [[B32:%f[0-9]+]], [[B]] 37; CHECK-NOF16-NEXT: add.rn.f32 [[R32:%f[0-9]+]], [[A32]], [[B32]]; 38; CHECK-NOF16-NEXT: cvt.rn.f16.f32 [[R:%h[0-9]+]], [[R32]] 39; CHECK-NEXT: st.param.b16 [func_retval0+0], [[R]]; 40; CHECK-NEXT: ret; 41define half @test_fadd(half %a, half %b) #0 { 42 %r = fadd half %a, %b 43 ret half %r 44} 45 46; CHECK-LABEL: test_fadd_v1f16( 47; CHECK-DAG: ld.param.b16 [[A:%h[0-9]+]], [test_fadd_v1f16_param_0]; 48; CHECK-DAG: ld.param.b16 [[B:%h[0-9]+]], [test_fadd_v1f16_param_1]; 49; CHECK-F16-NOFTZ-NEXT: add.rn.f16 [[R:%h[0-9]+]], [[A]], [[B]]; 50; CHECK-F16-FTZ-NEXT: add.rn.ftz.f16 [[R:%h[0-9]+]], [[A]], [[B]]; 51; CHECK-NOF16-DAG: cvt.f32.f16 [[A32:%f[0-9]+]], [[A]] 52; CHECK-NOF16-DAG: cvt.f32.f16 [[B32:%f[0-9]+]], [[B]] 53; CHECK-NOF16-NEXT: add.rn.f32 [[R32:%f[0-9]+]], [[A32]], [[B32]]; 54; CHECK-NOF16-NEXT: cvt.rn.f16.f32 [[R:%h[0-9]+]], [[R32]] 55; CHECK-NEXT: st.param.b16 [func_retval0+0], [[R]]; 56; CHECK-NEXT: ret; 57define <1 x half> @test_fadd_v1f16(<1 x half> %a, <1 x half> %b) #0 { 58 %r = fadd <1 x half> %a, %b 59 ret <1 x half> %r 60} 61 62; Check that we can lower fadd with immediate arguments. 63; CHECK-LABEL: test_fadd_imm_0( 64; CHECK-DAG: ld.param.b16 [[B:%h[0-9]+]], [test_fadd_imm_0_param_0]; 65; CHECK-F16-NOFTZ-DAG: mov.b16 [[A:%h[0-9]+]], 0x3C00; 66; CHECK-F16-NOFTZ-NEXT: add.rn.f16 [[R:%h[0-9]+]], [[B]], [[A]]; 67; CHECK-F16-FTZ-DAG: mov.b16 [[A:%h[0-9]+]], 0x3C00; 68; CHECK-F16-FTZ-NEXT: add.rn.ftz.f16 [[R:%h[0-9]+]], [[B]], [[A]]; 69; CHECK-NOF16-DAG: cvt.f32.f16 [[B32:%f[0-9]+]], [[B]] 70; CHECK-NOF16-NEXT: add.rn.f32 [[R32:%f[0-9]+]], [[B32]], 0f3F800000; 71; CHECK-NOF16-NEXT: cvt.rn.f16.f32 [[R:%h[0-9]+]], [[R32]] 72; CHECK-NEXT: st.param.b16 [func_retval0+0], [[R]]; 73; CHECK-NEXT: ret; 74define half @test_fadd_imm_0(half %b) #0 { 75 %r = fadd half 1.0, %b 76 ret half %r 77} 78 79; CHECK-LABEL: test_fadd_imm_1( 80; CHECK-DAG: ld.param.b16 [[B:%h[0-9]+]], [test_fadd_imm_1_param_0]; 81; CHECK-F16-NOFTZ-DAG: mov.b16 [[A:%h[0-9]+]], 0x3C00; 82; CHECK-F16-NOFTZ-NEXT: add.rn.f16 [[R:%h[0-9]+]], [[B]], [[A]]; 83; CHECK-F16-FTZ-DAG: mov.b16 [[A:%h[0-9]+]], 0x3C00; 84; CHECK-F16-FTZ-NEXT: add.rn.ftz.f16 [[R:%h[0-9]+]], [[B]], [[A]]; 85; CHECK-NOF16-DAG: cvt.f32.f16 [[B32:%f[0-9]+]], [[B]] 86; CHECK-NOF16-NEXT: add.rn.f32 [[R32:%f[0-9]+]], [[B32]], 0f3F800000; 87; CHECK-NOF16-NEXT: cvt.rn.f16.f32 [[R:%h[0-9]+]], [[R32]] 88; CHECK-NEXT: st.param.b16 [func_retval0+0], [[R]]; 89; CHECK-NEXT: ret; 90define half @test_fadd_imm_1(half %a) #0 { 91 %r = fadd half %a, 1.0 92 ret half %r 93} 94 95; CHECK-LABEL: test_fsub( 96; CHECK-DAG: ld.param.b16 [[A:%h[0-9]+]], [test_fsub_param_0]; 97; CHECK-DAG: ld.param.b16 [[B:%h[0-9]+]], [test_fsub_param_1]; 98; CHECK-F16-NOFTZ-NEXT: sub.rn.f16 [[R:%h[0-9]+]], [[A]], [[B]]; 99; CHECK-F16-FTZ-NEXT: sub.rn.ftz.f16 [[R:%h[0-9]+]], [[A]], [[B]]; 100; CHECK-NOF16-DAG: cvt.f32.f16 [[A32:%f[0-9]+]], [[A]] 101; CHECK-NOF16-DAG: cvt.f32.f16 [[B32:%f[0-9]+]], [[B]] 102; CHECK-NOF16-NEXT: sub.rn.f32 [[R32:%f[0-9]+]], [[A32]], [[B32]]; 103; CHECK-NOF16-NEXT: cvt.rn.f16.f32 [[R:%h[0-9]+]], [[R32]] 104; CHECK-NEXT: st.param.b16 [func_retval0+0], [[R]]; 105; CHECK-NEXT: ret; 106define half @test_fsub(half %a, half %b) #0 { 107 %r = fsub half %a, %b 108 ret half %r 109} 110 111; CHECK-LABEL: test_fneg( 112; CHECK-DAG: ld.param.b16 [[A:%h[0-9]+]], [test_fneg_param_0]; 113; CHECK-F16-NOFTZ-NEXT: mov.b16 [[Z:%h[0-9]+]], 0x0000 114; CHECK-F16-NOFTZ-NEXT: sub.rn.f16 [[R:%h[0-9]+]], [[Z]], [[A]]; 115; CHECK-F16-FTZ-NEXT: mov.b16 [[Z:%h[0-9]+]], 0x0000 116; CHECK-F16-FTZ-NEXT: sub.rn.ftz.f16 [[R:%h[0-9]+]], [[Z]], [[A]]; 117; CHECK-NOF16-DAG: cvt.f32.f16 [[A32:%f[0-9]+]], [[A]] 118; CHECK-NOF16-DAG: mov.f32 [[Z:%f[0-9]+]], 0f00000000; 119; CHECK-NOF16-NEXT: sub.rn.f32 [[R32:%f[0-9]+]], [[Z]], [[A32]]; 120; CHECK-NOF16-NEXT: cvt.rn.f16.f32 [[R:%h[0-9]+]], [[R32]] 121; CHECK-NEXT: st.param.b16 [func_retval0+0], [[R]]; 122; CHECK-NEXT: ret; 123define half @test_fneg(half %a) #0 { 124 %r = fsub half 0.0, %a 125 ret half %r 126} 127 128; CHECK-LABEL: test_fmul( 129; CHECK-DAG: ld.param.b16 [[A:%h[0-9]+]], [test_fmul_param_0]; 130; CHECK-DAG: ld.param.b16 [[B:%h[0-9]+]], [test_fmul_param_1]; 131; CHECK-F16-NOFTZ-NEXT: mul.rn.f16 [[R:%h[0-9]+]], [[A]], [[B]]; 132; CHECK-F16-FTZ-NEXT: mul.rn.ftz.f16 [[R:%h[0-9]+]], [[A]], [[B]]; 133; CHECK-NOF16-DAG: cvt.f32.f16 [[A32:%f[0-9]+]], [[A]] 134; CHECK-NOF16-DAG: cvt.f32.f16 [[B32:%f[0-9]+]], [[B]] 135; CHECK-NOF16-NEXT: mul.rn.f32 [[R32:%f[0-9]+]], [[A32]], [[B32]]; 136; CHECK-NOF16-NEXT: cvt.rn.f16.f32 [[R:%h[0-9]+]], [[R32]] 137; CHECK-NEXT: st.param.b16 [func_retval0+0], [[R]]; 138; CHECK-NEXT: ret; 139define half @test_fmul(half %a, half %b) #0 { 140 %r = fmul half %a, %b 141 ret half %r 142} 143 144; CHECK-LABEL: test_fdiv( 145; CHECK-DAG: ld.param.b16 [[A:%h[0-9]+]], [test_fdiv_param_0]; 146; CHECK-DAG: ld.param.b16 [[B:%h[0-9]+]], [test_fdiv_param_1]; 147; CHECK-NOFTZ-DAG: cvt.f32.f16 [[F0:%f[0-9]+]], [[A]]; 148; CHECK-NOFTZ-DAG: cvt.f32.f16 [[F1:%f[0-9]+]], [[B]]; 149; CHECK-NOFTZ-NEXT: div.rn.f32 [[FR:%f[0-9]+]], [[F0]], [[F1]]; 150; CHECK-F16-FTZ-DAG: cvt.ftz.f32.f16 [[F0:%f[0-9]+]], [[A]]; 151; CHECK-F16-FTZ-DAG: cvt.ftz.f32.f16 [[F1:%f[0-9]+]], [[B]]; 152; CHECK-F16-FTZ-NEXT: div.rn.ftz.f32 [[FR:%f[0-9]+]], [[F0]], [[F1]]; 153; CHECK-NEXT: cvt.rn.f16.f32 [[R:%h[0-9]+]], [[FR]]; 154; CHECK-NEXT: st.param.b16 [func_retval0+0], [[R]]; 155; CHECK-NEXT: ret; 156define half @test_fdiv(half %a, half %b) #0 { 157 %r = fdiv half %a, %b 158 ret half %r 159} 160 161; CHECK-LABEL: test_frem( 162; CHECK-DAG: ld.param.b16 [[A:%h[0-9]+]], [test_frem_param_0]; 163; CHECK-DAG: ld.param.b16 [[B:%h[0-9]+]], [test_frem_param_1]; 164; CHECK-NOFTZ-DAG: cvt.f32.f16 [[FA:%f[0-9]+]], [[A]]; 165; CHECK-NOFTZ-DAG: cvt.f32.f16 [[FB:%f[0-9]+]], [[B]]; 166; CHECK-NOFTZ-NEXT: div.rn.f32 [[D:%f[0-9]+]], [[FA]], [[FB]]; 167; CHECK-NOFTZ-NEXT: cvt.rzi.f32.f32 [[DI:%f[0-9]+]], [[D]]; 168; CHECK-NOFTZ-NEXT: mul.f32 [[RI:%f[0-9]+]], [[DI]], [[FB]]; 169; CHECK-NOFTZ-NEXT: sub.f32 [[RF:%f[0-9]+]], [[FA]], [[RI]]; 170; CHECK-F16-FTZ-DAG: cvt.ftz.f32.f16 [[FA:%f[0-9]+]], [[A]]; 171; CHECK-F16-FTZ-DAG: cvt.ftz.f32.f16 [[FB:%f[0-9]+]], [[B]]; 172; CHECK-F16-FTZ-NEXT: div.rn.ftz.f32 [[D:%f[0-9]+]], [[FA]], [[FB]]; 173; CHECK-F16-FTZ-NEXT: cvt.rzi.ftz.f32.f32 [[DI:%f[0-9]+]], [[D]]; 174; CHECK-F16-FTZ-NEXT: mul.ftz.f32 [[RI:%f[0-9]+]], [[DI]], [[FB]]; 175; CHECK-F16-FTZ-NEXT: sub.ftz.f32 [[RF:%f[0-9]+]], [[FA]], [[RI]]; 176; CHECK-NEXT: cvt.rn.f16.f32 [[R:%h[0-9]+]], [[RF]]; 177; CHECK-NEXT: st.param.b16 [func_retval0+0], [[R]]; 178; CHECK-NEXT: ret; 179define half @test_frem(half %a, half %b) #0 { 180 %r = frem half %a, %b 181 ret half %r 182} 183 184; CHECK-LABEL: test_store( 185; CHECK-DAG: ld.param.b16 [[A:%h[0-9]+]], [test_store_param_0]; 186; CHECK-DAG: ld.param.u64 %[[PTR:rd[0-9]+]], [test_store_param_1]; 187; CHECK-NEXT: st.b16 [%[[PTR]]], [[A]]; 188; CHECK-NEXT: ret; 189define void @test_store(half %a, half* %b) #0 { 190 store half %a, half* %b 191 ret void 192} 193 194; CHECK-LABEL: test_load( 195; CHECK: ld.param.u64 %[[PTR:rd[0-9]+]], [test_load_param_0]; 196; CHECK-NEXT: ld.b16 [[R:%h[0-9]+]], [%[[PTR]]]; 197; CHECK-NEXT: st.param.b16 [func_retval0+0], [[R]]; 198; CHECK-NEXT: ret; 199define half @test_load(half* %a) #0 { 200 %r = load half, half* %a 201 ret half %r 202} 203 204; CHECK-LABEL: .visible .func test_halfp0a1( 205; CHECK-DAG: ld.param.u64 %[[FROM:rd?[0-9]+]], [test_halfp0a1_param_0]; 206; CHECK-DAG: ld.param.u64 %[[TO:rd?[0-9]+]], [test_halfp0a1_param_1]; 207; CHECK-DAG: ld.u8 [[B0:%r[sd]?[0-9]+]], [%[[FROM]]] 208; CHECK-DAG: st.u8 [%[[TO]]], [[B0]] 209; CHECK-DAG: ld.u8 [[B1:%r[sd]?[0-9]+]], [%[[FROM]]+1] 210; CHECK-DAG: st.u8 [%[[TO]]+1], [[B1]] 211; CHECK: ret 212define void @test_halfp0a1(half * noalias readonly %from, half * %to) { 213 %1 = load half, half * %from , align 1 214 store half %1, half * %to , align 1 215 ret void 216} 217 218declare half @test_callee(half %a, half %b) #0 219 220; CHECK-LABEL: test_call( 221; CHECK-DAG: ld.param.b16 [[A:%h[0-9]+]], [test_call_param_0]; 222; CHECK-DAG: ld.param.b16 [[B:%h[0-9]+]], [test_call_param_1]; 223; CHECK: { 224; CHECK-DAG: .param .b32 param0; 225; CHECK-DAG: .param .b32 param1; 226; CHECK-DAG: st.param.b16 [param0+0], [[A]]; 227; CHECK-DAG: st.param.b16 [param1+0], [[B]]; 228; CHECK-DAG: .param .b32 retval0; 229; CHECK: call.uni (retval0), 230; CHECK-NEXT: test_callee, 231; CHECK: ); 232; CHECK-NEXT: ld.param.b16 [[R:%h[0-9]+]], [retval0+0]; 233; CHECK-NEXT: } 234; CHECK-NEXT: st.param.b16 [func_retval0+0], [[R]]; 235; CHECK-NEXT: ret; 236define half @test_call(half %a, half %b) #0 { 237 %r = call half @test_callee(half %a, half %b) 238 ret half %r 239} 240 241; CHECK-LABEL: test_call_flipped( 242; CHECK-DAG: ld.param.b16 [[A:%h[0-9]+]], [test_call_flipped_param_0]; 243; CHECK-DAG: ld.param.b16 [[B:%h[0-9]+]], [test_call_flipped_param_1]; 244; CHECK: { 245; CHECK-DAG: .param .b32 param0; 246; CHECK-DAG: .param .b32 param1; 247; CHECK-DAG: st.param.b16 [param0+0], [[B]]; 248; CHECK-DAG: st.param.b16 [param1+0], [[A]]; 249; CHECK-DAG: .param .b32 retval0; 250; CHECK: call.uni (retval0), 251; CHECK-NEXT: test_callee, 252; CHECK: ); 253; CHECK-NEXT: ld.param.b16 [[R:%h[0-9]+]], [retval0+0]; 254; CHECK-NEXT: } 255; CHECK-NEXT: st.param.b16 [func_retval0+0], [[R]]; 256; CHECK-NEXT: ret; 257define half @test_call_flipped(half %a, half %b) #0 { 258 %r = call half @test_callee(half %b, half %a) 259 ret half %r 260} 261 262; CHECK-LABEL: test_tailcall_flipped( 263; CHECK-DAG: ld.param.b16 [[A:%h[0-9]+]], [test_tailcall_flipped_param_0]; 264; CHECK-DAG: ld.param.b16 [[B:%h[0-9]+]], [test_tailcall_flipped_param_1]; 265; CHECK: { 266; CHECK-DAG: .param .b32 param0; 267; CHECK-DAG: .param .b32 param1; 268; CHECK-DAG: st.param.b16 [param0+0], [[B]]; 269; CHECK-DAG: st.param.b16 [param1+0], [[A]]; 270; CHECK-DAG: .param .b32 retval0; 271; CHECK: call.uni (retval0), 272; CHECK-NEXT: test_callee, 273; CHECK: ); 274; CHECK-NEXT: ld.param.b16 [[R:%h[0-9]+]], [retval0+0]; 275; CHECK-NEXT: } 276; CHECK-NEXT: st.param.b16 [func_retval0+0], [[R]]; 277; CHECK-NEXT: ret; 278define half @test_tailcall_flipped(half %a, half %b) #0 { 279 %r = tail call half @test_callee(half %b, half %a) 280 ret half %r 281} 282 283; CHECK-LABEL: test_select( 284; CHECK-DAG: ld.param.b16 [[A:%h[0-9]+]], [test_select_param_0]; 285; CHECK-DAG: ld.param.b16 [[B:%h[0-9]+]], [test_select_param_1]; 286; CHECK-DAG: setp.eq.b16 [[PRED:%p[0-9]+]], %rs{{.*}}, 1; 287; CHECK-NEXT: selp.b16 [[R:%h[0-9]+]], [[A]], [[B]], [[PRED]]; 288; CHECK-NEXT: st.param.b16 [func_retval0+0], [[R]]; 289; CHECK-NEXT: ret; 290define half @test_select(half %a, half %b, i1 zeroext %c) #0 { 291 %r = select i1 %c, half %a, half %b 292 ret half %r 293} 294 295; CHECK-LABEL: test_select_cc( 296; CHECK-DAG: ld.param.b16 [[A:%h[0-9]+]], [test_select_cc_param_0]; 297; CHECK-DAG: ld.param.b16 [[B:%h[0-9]+]], [test_select_cc_param_1]; 298; CHECK-DAG: ld.param.b16 [[C:%h[0-9]+]], [test_select_cc_param_2]; 299; CHECK-DAG: ld.param.b16 [[D:%h[0-9]+]], [test_select_cc_param_3]; 300; CHECK-F16-NOFTZ: setp.neu.f16 [[PRED:%p[0-9]+]], [[C]], [[D]] 301; CHECK-NOF16-DAG: cvt.f32.f16 [[DF:%f[0-9]+]], [[D]]; 302; CHECK-NOF16-DAG: cvt.f32.f16 [[CF:%f[0-9]+]], [[C]]; 303; CHECK-NOF16: setp.neu.f32 [[PRED:%p[0-9]+]], [[CF]], [[DF]] 304; CHECK: selp.b16 [[R:%h[0-9]+]], [[A]], [[B]], [[PRED]]; 305; CHECK-NEXT: st.param.b16 [func_retval0+0], [[R]]; 306; CHECK-NEXT: ret; 307define half @test_select_cc(half %a, half %b, half %c, half %d) #0 { 308 %cc = fcmp une half %c, %d 309 %r = select i1 %cc, half %a, half %b 310 ret half %r 311} 312 313; CHECK-LABEL: test_select_cc_f32_f16( 314; CHECK-DAG: ld.param.f32 [[A:%f[0-9]+]], [test_select_cc_f32_f16_param_0]; 315; CHECK-DAG: ld.param.f32 [[B:%f[0-9]+]], [test_select_cc_f32_f16_param_1]; 316; CHECK-DAG: ld.param.b16 [[C:%h[0-9]+]], [test_select_cc_f32_f16_param_2]; 317; CHECK-DAG: ld.param.b16 [[D:%h[0-9]+]], [test_select_cc_f32_f16_param_3]; 318; CHECK-F16-NOFTZ: setp.neu.f16 [[PRED:%p[0-9]+]], [[C]], [[D]] 319; CHECK-F16-FTZ: setp.neu.ftz.f16 [[PRED:%p[0-9]+]], [[C]], [[D]] 320; CHECK-NOF16-DAG: cvt.f32.f16 [[DF:%f[0-9]+]], [[D]]; 321; CHECK-NOF16-DAG: cvt.f32.f16 [[CF:%f[0-9]+]], [[C]]; 322; CHECK-NOF16: setp.neu.f32 [[PRED:%p[0-9]+]], [[CF]], [[DF]] 323; CHECK-NEXT: selp.f32 [[R:%f[0-9]+]], [[A]], [[B]], [[PRED]]; 324; CHECK-NEXT: st.param.f32 [func_retval0+0], [[R]]; 325; CHECK-NEXT: ret; 326define float @test_select_cc_f32_f16(float %a, float %b, half %c, half %d) #0 { 327 %cc = fcmp une half %c, %d 328 %r = select i1 %cc, float %a, float %b 329 ret float %r 330} 331 332; CHECK-LABEL: test_select_cc_f16_f32( 333; CHECK-DAG: ld.param.b16 [[A:%h[0-9]+]], [test_select_cc_f16_f32_param_0]; 334; CHECK-DAG: ld.param.f32 [[C:%f[0-9]+]], [test_select_cc_f16_f32_param_2]; 335; CHECK-DAG: ld.param.f32 [[D:%f[0-9]+]], [test_select_cc_f16_f32_param_3]; 336; CHECK-NOFTZ-DAG: setp.neu.f32 [[PRED:%p[0-9]+]], [[C]], [[D]] 337; CHECK-F16-FTZ-DAG: setp.neu.ftz.f32 [[PRED:%p[0-9]+]], [[C]], [[D]] 338; CHECK-DAG: ld.param.b16 [[B:%h[0-9]+]], [test_select_cc_f16_f32_param_1]; 339; CHECK-NEXT: selp.b16 [[R:%h[0-9]+]], [[A]], [[B]], [[PRED]]; 340; CHECK-NEXT: st.param.b16 [func_retval0+0], [[R]]; 341; CHECK-NEXT: ret; 342define half @test_select_cc_f16_f32(half %a, half %b, float %c, float %d) #0 { 343 %cc = fcmp une float %c, %d 344 %r = select i1 %cc, half %a, half %b 345 ret half %r 346} 347 348; CHECK-LABEL: test_fcmp_une( 349; CHECK-DAG: ld.param.b16 [[A:%h[0-9]+]], [test_fcmp_une_param_0]; 350; CHECK-DAG: ld.param.b16 [[B:%h[0-9]+]], [test_fcmp_une_param_1]; 351; CHECK-F16-NOFTZ: setp.neu.f16 [[PRED:%p[0-9]+]], [[A]], [[B]] 352; CHECK-F16-FTZ: setp.neu.ftz.f16 [[PRED:%p[0-9]+]], [[A]], [[B]] 353; CHECK-NOF16-DAG: cvt.f32.f16 [[AF:%f[0-9]+]], [[A]]; 354; CHECK-NOF16-DAG: cvt.f32.f16 [[BF:%f[0-9]+]], [[B]]; 355; CHECK-NOF16: setp.neu.f32 [[PRED:%p[0-9]+]], [[AF]], [[BF]] 356; CHECK-NEXT: selp.u32 [[R:%r[0-9]+]], 1, 0, [[PRED]]; 357; CHECK-NEXT: st.param.b32 [func_retval0+0], [[R]]; 358; CHECK-NEXT: ret; 359define i1 @test_fcmp_une(half %a, half %b) #0 { 360 %r = fcmp une half %a, %b 361 ret i1 %r 362} 363 364; CHECK-LABEL: test_fcmp_ueq( 365; CHECK-DAG: ld.param.b16 [[A:%h[0-9]+]], [test_fcmp_ueq_param_0]; 366; CHECK-DAG: ld.param.b16 [[B:%h[0-9]+]], [test_fcmp_ueq_param_1]; 367; CHECK-F16-NOFTZ: setp.equ.f16 [[PRED:%p[0-9]+]], [[A]], [[B]] 368; CHECK-F16-FTZ: setp.equ.ftz.f16 [[PRED:%p[0-9]+]], [[A]], [[B]] 369; CHECK-NOF16-DAG: cvt.f32.f16 [[AF:%f[0-9]+]], [[A]]; 370; CHECK-NOF16-DAG: cvt.f32.f16 [[BF:%f[0-9]+]], [[B]]; 371; CHECK-NOF16: setp.equ.f32 [[PRED:%p[0-9]+]], [[AF]], [[BF]] 372; CHECK-NEXT: selp.u32 [[R:%r[0-9]+]], 1, 0, [[PRED]]; 373; CHECK-NEXT: st.param.b32 [func_retval0+0], [[R]]; 374; CHECK-NEXT: ret; 375define i1 @test_fcmp_ueq(half %a, half %b) #0 { 376 %r = fcmp ueq half %a, %b 377 ret i1 %r 378} 379 380; CHECK-LABEL: test_fcmp_ugt( 381; CHECK-DAG: ld.param.b16 [[A:%h[0-9]+]], [test_fcmp_ugt_param_0]; 382; CHECK-DAG: ld.param.b16 [[B:%h[0-9]+]], [test_fcmp_ugt_param_1]; 383; CHECK-F16-NOFTZ: setp.gtu.f16 [[PRED:%p[0-9]+]], [[A]], [[B]] 384; CHECK-F16-FTZ: setp.gtu.ftz.f16 [[PRED:%p[0-9]+]], [[A]], [[B]] 385; CHECK-NOF16-DAG: cvt.f32.f16 [[AF:%f[0-9]+]], [[A]]; 386; CHECK-NOF16-DAG: cvt.f32.f16 [[BF:%f[0-9]+]], [[B]]; 387; CHECK-NOF16: setp.gtu.f32 [[PRED:%p[0-9]+]], [[AF]], [[BF]] 388; CHECK-NEXT: selp.u32 [[R:%r[0-9]+]], 1, 0, [[PRED]]; 389; CHECK-NEXT: st.param.b32 [func_retval0+0], [[R]]; 390; CHECK-NEXT: ret; 391define i1 @test_fcmp_ugt(half %a, half %b) #0 { 392 %r = fcmp ugt half %a, %b 393 ret i1 %r 394} 395 396; CHECK-LABEL: test_fcmp_uge( 397; CHECK-DAG: ld.param.b16 [[A:%h[0-9]+]], [test_fcmp_uge_param_0]; 398; CHECK-DAG: ld.param.b16 [[B:%h[0-9]+]], [test_fcmp_uge_param_1]; 399; CHECK-F16-NOFTZ: setp.geu.f16 [[PRED:%p[0-9]+]], [[A]], [[B]] 400; CHECK-F16-FTZ: setp.geu.ftz.f16 [[PRED:%p[0-9]+]], [[A]], [[B]] 401; CHECK-NOF16-DAG: cvt.f32.f16 [[AF:%f[0-9]+]], [[A]]; 402; CHECK-NOF16-DAG: cvt.f32.f16 [[BF:%f[0-9]+]], [[B]]; 403; CHECK-NOF16: setp.geu.f32 [[PRED:%p[0-9]+]], [[AF]], [[BF]] 404; CHECK-NEXT: selp.u32 [[R:%r[0-9]+]], 1, 0, [[PRED]]; 405; CHECK-NEXT: st.param.b32 [func_retval0+0], [[R]]; 406; CHECK-NEXT: ret; 407define i1 @test_fcmp_uge(half %a, half %b) #0 { 408 %r = fcmp uge half %a, %b 409 ret i1 %r 410} 411 412; CHECK-LABEL: test_fcmp_ult( 413; CHECK-DAG: ld.param.b16 [[A:%h[0-9]+]], [test_fcmp_ult_param_0]; 414; CHECK-DAG: ld.param.b16 [[B:%h[0-9]+]], [test_fcmp_ult_param_1]; 415; CHECK-F16-NOFTZ: setp.ltu.f16 [[PRED:%p[0-9]+]], [[A]], [[B]] 416; CHECK-F16-FTZ: setp.ltu.ftz.f16 [[PRED:%p[0-9]+]], [[A]], [[B]] 417; CHECK-NOF16-DAG: cvt.f32.f16 [[AF:%f[0-9]+]], [[A]]; 418; CHECK-NOF16-DAG: cvt.f32.f16 [[BF:%f[0-9]+]], [[B]]; 419; CHECK-NOF16: setp.ltu.f32 [[PRED:%p[0-9]+]], [[AF]], [[BF]] 420; CHECK-NEXT: selp.u32 [[R:%r[0-9]+]], 1, 0, [[PRED]]; 421; CHECK-NEXT: st.param.b32 [func_retval0+0], [[R]]; 422; CHECK-NEXT: ret; 423define i1 @test_fcmp_ult(half %a, half %b) #0 { 424 %r = fcmp ult half %a, %b 425 ret i1 %r 426} 427 428; CHECK-LABEL: test_fcmp_ule( 429; CHECK-DAG: ld.param.b16 [[A:%h[0-9]+]], [test_fcmp_ule_param_0]; 430; CHECK-DAG: ld.param.b16 [[B:%h[0-9]+]], [test_fcmp_ule_param_1]; 431; CHECK-F16-NOFTZ: setp.leu.f16 [[PRED:%p[0-9]+]], [[A]], [[B]] 432; CHECK-F16-FTZ: setp.leu.ftz.f16 [[PRED:%p[0-9]+]], [[A]], [[B]] 433; CHECK-NOF16-DAG: cvt.f32.f16 [[AF:%f[0-9]+]], [[A]]; 434; CHECK-NOF16-DAG: cvt.f32.f16 [[BF:%f[0-9]+]], [[B]]; 435; CHECK-NOF16: setp.leu.f32 [[PRED:%p[0-9]+]], [[AF]], [[BF]] 436; CHECK-NEXT: selp.u32 [[R:%r[0-9]+]], 1, 0, [[PRED]]; 437; CHECK-NEXT: st.param.b32 [func_retval0+0], [[R]]; 438; CHECK-NEXT: ret; 439define i1 @test_fcmp_ule(half %a, half %b) #0 { 440 %r = fcmp ule half %a, %b 441 ret i1 %r 442} 443 444 445; CHECK-LABEL: test_fcmp_uno( 446; CHECK-DAG: ld.param.b16 [[A:%h[0-9]+]], [test_fcmp_uno_param_0]; 447; CHECK-DAG: ld.param.b16 [[B:%h[0-9]+]], [test_fcmp_uno_param_1]; 448; CHECK-F16-NOFTZ: setp.nan.f16 [[PRED:%p[0-9]+]], [[A]], [[B]] 449; CHECK-F16-FTZ: setp.nan.ftz.f16 [[PRED:%p[0-9]+]], [[A]], [[B]] 450; CHECK-NOF16-DAG: cvt.f32.f16 [[AF:%f[0-9]+]], [[A]]; 451; CHECK-NOF16-DAG: cvt.f32.f16 [[BF:%f[0-9]+]], [[B]]; 452; CHECK-NOF16: setp.nan.f32 [[PRED:%p[0-9]+]], [[AF]], [[BF]] 453; CHECK-NEXT: selp.u32 [[R:%r[0-9]+]], 1, 0, [[PRED]]; 454; CHECK-NEXT: st.param.b32 [func_retval0+0], [[R]]; 455; CHECK-NEXT: ret; 456define i1 @test_fcmp_uno(half %a, half %b) #0 { 457 %r = fcmp uno half %a, %b 458 ret i1 %r 459} 460 461; CHECK-LABEL: test_fcmp_one( 462; CHECK-DAG: ld.param.b16 [[A:%h[0-9]+]], [test_fcmp_one_param_0]; 463; CHECK-DAG: ld.param.b16 [[B:%h[0-9]+]], [test_fcmp_one_param_1]; 464; CHECK-F16-NOFTZ: setp.ne.f16 [[PRED:%p[0-9]+]], [[A]], [[B]] 465; CHECK-F16-FTZ: setp.ne.ftz.f16 [[PRED:%p[0-9]+]], [[A]], [[B]] 466; CHECK-NOF16-DAG: cvt.f32.f16 [[AF:%f[0-9]+]], [[A]]; 467; CHECK-NOF16-DAG: cvt.f32.f16 [[BF:%f[0-9]+]], [[B]]; 468; CHECK-NOF16: setp.ne.f32 [[PRED:%p[0-9]+]], [[AF]], [[BF]] 469; CHECK-NEXT: selp.u32 [[R:%r[0-9]+]], 1, 0, [[PRED]]; 470; CHECK-NEXT: st.param.b32 [func_retval0+0], [[R]]; 471; CHECK-NEXT: ret; 472define i1 @test_fcmp_one(half %a, half %b) #0 { 473 %r = fcmp one half %a, %b 474 ret i1 %r 475} 476 477; CHECK-LABEL: test_fcmp_oeq( 478; CHECK-DAG: ld.param.b16 [[A:%h[0-9]+]], [test_fcmp_oeq_param_0]; 479; CHECK-DAG: ld.param.b16 [[B:%h[0-9]+]], [test_fcmp_oeq_param_1]; 480; CHECK-F16-NOFTZ: setp.eq.f16 [[PRED:%p[0-9]+]], [[A]], [[B]] 481; CHECK-F16-FTZ: setp.eq.ftz.f16 [[PRED:%p[0-9]+]], [[A]], [[B]] 482; CHECK-NOF16-DAG: cvt.f32.f16 [[AF:%f[0-9]+]], [[A]]; 483; CHECK-NOF16-DAG: cvt.f32.f16 [[BF:%f[0-9]+]], [[B]]; 484; CHECK-NOF16: setp.eq.f32 [[PRED:%p[0-9]+]], [[AF]], [[BF]] 485; CHECK-NEXT: selp.u32 [[R:%r[0-9]+]], 1, 0, [[PRED]]; 486; CHECK-NEXT: st.param.b32 [func_retval0+0], [[R]]; 487; CHECK-NEXT: ret; 488define i1 @test_fcmp_oeq(half %a, half %b) #0 { 489 %r = fcmp oeq half %a, %b 490 ret i1 %r 491} 492 493; CHECK-LABEL: test_fcmp_ogt( 494; CHECK-DAG: ld.param.b16 [[A:%h[0-9]+]], [test_fcmp_ogt_param_0]; 495; CHECK-DAG: ld.param.b16 [[B:%h[0-9]+]], [test_fcmp_ogt_param_1]; 496; CHECK-F16-NOFTZ: setp.gt.f16 [[PRED:%p[0-9]+]], [[A]], [[B]] 497; CHECK-F16-FTZ: setp.gt.ftz.f16 [[PRED:%p[0-9]+]], [[A]], [[B]] 498; CHECK-NOF16-DAG: cvt.f32.f16 [[AF:%f[0-9]+]], [[A]]; 499; CHECK-NOF16-DAG: cvt.f32.f16 [[BF:%f[0-9]+]], [[B]]; 500; CHECK-NOF16: setp.gt.f32 [[PRED:%p[0-9]+]], [[AF]], [[BF]] 501; CHECK-NEXT: selp.u32 [[R:%r[0-9]+]], 1, 0, [[PRED]]; 502; CHECK-NEXT: st.param.b32 [func_retval0+0], [[R]]; 503; CHECK-NEXT: ret; 504define i1 @test_fcmp_ogt(half %a, half %b) #0 { 505 %r = fcmp ogt half %a, %b 506 ret i1 %r 507} 508 509; CHECK-LABEL: test_fcmp_oge( 510; CHECK-DAG: ld.param.b16 [[A:%h[0-9]+]], [test_fcmp_oge_param_0]; 511; CHECK-DAG: ld.param.b16 [[B:%h[0-9]+]], [test_fcmp_oge_param_1]; 512; CHECK-F16-NOFTZ: setp.ge.f16 [[PRED:%p[0-9]+]], [[A]], [[B]] 513; CHECK-F16-FTZ: setp.ge.ftz.f16 [[PRED:%p[0-9]+]], [[A]], [[B]] 514; CHECK-NOF16-DAG: cvt.f32.f16 [[AF:%f[0-9]+]], [[A]]; 515; CHECK-NOF16-DAG: cvt.f32.f16 [[BF:%f[0-9]+]], [[B]]; 516; CHECK-NOF16: setp.ge.f32 [[PRED:%p[0-9]+]], [[AF]], [[BF]] 517; CHECK-NEXT: selp.u32 [[R:%r[0-9]+]], 1, 0, [[PRED]]; 518; CHECK-NEXT: st.param.b32 [func_retval0+0], [[R]]; 519; CHECK-NEXT: ret; 520define i1 @test_fcmp_oge(half %a, half %b) #0 { 521 %r = fcmp oge half %a, %b 522 ret i1 %r 523} 524 525; XCHECK-LABEL: test_fcmp_olt( 526; CHECK-DAG: ld.param.b16 [[A:%h[0-9]+]], [test_fcmp_olt_param_0]; 527; CHECK-DAG: ld.param.b16 [[B:%h[0-9]+]], [test_fcmp_olt_param_1]; 528; CHECK-F16-NOFTZ: setp.lt.f16 [[PRED:%p[0-9]+]], [[A]], [[B]] 529; CHECK-F16-FTZ: setp.lt.ftz.f16 [[PRED:%p[0-9]+]], [[A]], [[B]] 530; CHECK-NOF16-DAG: cvt.f32.f16 [[AF:%f[0-9]+]], [[A]]; 531; CHECK-NOF16-DAG: cvt.f32.f16 [[BF:%f[0-9]+]], [[B]]; 532; CHECK-NOF16: setp.lt.f32 [[PRED:%p[0-9]+]], [[AF]], [[BF]] 533; CHECK-NEXT: selp.u32 [[R:%r[0-9]+]], 1, 0, [[PRED]]; 534; CHECK-NEXT: st.param.b32 [func_retval0+0], [[R]]; 535; CHECK-NEXT: ret; 536define i1 @test_fcmp_olt(half %a, half %b) #0 { 537 %r = fcmp olt half %a, %b 538 ret i1 %r 539} 540 541; XCHECK-LABEL: test_fcmp_ole( 542; CHECK-DAG: ld.param.b16 [[A:%h[0-9]+]], [test_fcmp_ole_param_0]; 543; CHECK-DAG: ld.param.b16 [[B:%h[0-9]+]], [test_fcmp_ole_param_1]; 544; CHECK-F16-NOFTZ: setp.le.f16 [[PRED:%p[0-9]+]], [[A]], [[B]] 545; CHECK-F16-FTZ: setp.le.ftz.f16 [[PRED:%p[0-9]+]], [[A]], [[B]] 546; CHECK-NOF16-DAG: cvt.f32.f16 [[AF:%f[0-9]+]], [[A]]; 547; CHECK-NOF16-DAG: cvt.f32.f16 [[BF:%f[0-9]+]], [[B]]; 548; CHECK-NOF16: setp.le.f32 [[PRED:%p[0-9]+]], [[AF]], [[BF]] 549; CHECK-NEXT: selp.u32 [[R:%r[0-9]+]], 1, 0, [[PRED]]; 550; CHECK-NEXT: st.param.b32 [func_retval0+0], [[R]]; 551; CHECK-NEXT: ret; 552define i1 @test_fcmp_ole(half %a, half %b) #0 { 553 %r = fcmp ole half %a, %b 554 ret i1 %r 555} 556 557; CHECK-LABEL: test_fcmp_ord( 558; CHECK-DAG: ld.param.b16 [[A:%h[0-9]+]], [test_fcmp_ord_param_0]; 559; CHECK-DAG: ld.param.b16 [[B:%h[0-9]+]], [test_fcmp_ord_param_1]; 560; CHECK-F16-NOFTZ: setp.num.f16 [[PRED:%p[0-9]+]], [[A]], [[B]] 561; CHECK-F16-FTZ: setp.num.ftz.f16 [[PRED:%p[0-9]+]], [[A]], [[B]] 562; CHECK-NOF16-DAG: cvt.f32.f16 [[AF:%f[0-9]+]], [[A]]; 563; CHECK-NOF16-DAG: cvt.f32.f16 [[BF:%f[0-9]+]], [[B]]; 564; CHECK-NOF16: setp.num.f32 [[PRED:%p[0-9]+]], [[AF]], [[BF]] 565; CHECK-NEXT: selp.u32 [[R:%r[0-9]+]], 1, 0, [[PRED]]; 566; CHECK-NEXT: st.param.b32 [func_retval0+0], [[R]]; 567; CHECK-NEXT: ret; 568define i1 @test_fcmp_ord(half %a, half %b) #0 { 569 %r = fcmp ord half %a, %b 570 ret i1 %r 571} 572 573; CHECK-LABEL: test_br_cc( 574; CHECK-DAG: ld.param.b16 [[A:%h[0-9]+]], [test_br_cc_param_0]; 575; CHECK-DAG: ld.param.b16 [[B:%h[0-9]+]], [test_br_cc_param_1]; 576; CHECK-DAG: ld.param.u64 %[[C:rd[0-9]+]], [test_br_cc_param_2]; 577; CHECK-DAG: ld.param.u64 %[[D:rd[0-9]+]], [test_br_cc_param_3]; 578; CHECK-F16-NOFTZ: setp.lt.f16 [[PRED:%p[0-9]+]], [[A]], [[B]] 579; CHECK-F16-FTZ: setp.lt.ftz.f16 [[PRED:%p[0-9]+]], [[A]], [[B]] 580; CHECK-NOF16-DAG: cvt.f32.f16 [[AF:%f[0-9]+]], [[A]]; 581; CHECK-NOF16-DAG: cvt.f32.f16 [[BF:%f[0-9]+]], [[B]]; 582; CHECK-NOF16: setp.lt.f32 [[PRED:%p[0-9]+]], [[AF]], [[BF]] 583; CHECK-NEXT: @[[PRED]] bra [[LABEL:LBB.*]]; 584; CHECK: st.u32 [%[[C]]], 585; CHECK: [[LABEL]]: 586; CHECK: st.u32 [%[[D]]], 587; CHECK: ret; 588define void @test_br_cc(half %a, half %b, i32* %p1, i32* %p2) #0 { 589 %c = fcmp uge half %a, %b 590 br i1 %c, label %then, label %else 591then: 592 store i32 0, i32* %p1 593 ret void 594else: 595 store i32 0, i32* %p2 596 ret void 597} 598 599; CHECK-LABEL: test_phi( 600; CHECK: ld.param.u64 %[[P1:rd[0-9]+]], [test_phi_param_0]; 601; CHECK: ld.b16 {{%h[0-9]+}}, [%[[P1]]]; 602; CHECK: [[LOOP:LBB[0-9_]+]]: 603; CHECK: mov.b16 [[R:%h[0-9]+]], [[AB:%h[0-9]+]]; 604; CHECK: ld.b16 [[AB:%h[0-9]+]], [%[[P1]]]; 605; CHECK: { 606; CHECK: st.param.b64 [param0+0], %[[P1]]; 607; CHECK: call.uni (retval0), 608; CHECK-NEXT: test_dummy 609; CHECK: } 610; CHECK: setp.eq.b32 [[PRED:%p[0-9]+]], %r{{[0-9]+}}, 1; 611; CHECK: @[[PRED]] bra [[LOOP]]; 612; CHECK: st.param.b16 [func_retval0+0], [[R]]; 613; CHECK: ret; 614define half @test_phi(half* %p1) #0 { 615entry: 616 %a = load half, half* %p1 617 br label %loop 618loop: 619 %r = phi half [%a, %entry], [%b, %loop] 620 %b = load half, half* %p1 621 %c = call i1 @test_dummy(half* %p1) 622 br i1 %c, label %loop, label %return 623return: 624 ret half %r 625} 626declare i1 @test_dummy(half* %p1) #0 627 628; CHECK-LABEL: test_fptosi_i32( 629; CHECK: ld.param.b16 [[A:%h[0-9]+]], [test_fptosi_i32_param_0]; 630; CHECK: cvt.rzi.s32.f16 [[R:%r[0-9]+]], [[A]]; 631; CHECK: st.param.b32 [func_retval0+0], [[R]]; 632; CHECK: ret; 633define i32 @test_fptosi_i32(half %a) #0 { 634 %r = fptosi half %a to i32 635 ret i32 %r 636} 637 638; CHECK-LABEL: test_fptosi_i64( 639; CHECK: ld.param.b16 [[A:%h[0-9]+]], [test_fptosi_i64_param_0]; 640; CHECK: cvt.rzi.s64.f16 [[R:%rd[0-9]+]], [[A]]; 641; CHECK: st.param.b64 [func_retval0+0], [[R]]; 642; CHECK: ret; 643define i64 @test_fptosi_i64(half %a) #0 { 644 %r = fptosi half %a to i64 645 ret i64 %r 646} 647 648; CHECK-LABEL: test_fptoui_i32( 649; CHECK: ld.param.b16 [[A:%h[0-9]+]], [test_fptoui_i32_param_0]; 650; CHECK: cvt.rzi.u32.f16 [[R:%r[0-9]+]], [[A]]; 651; CHECK: st.param.b32 [func_retval0+0], [[R]]; 652; CHECK: ret; 653define i32 @test_fptoui_i32(half %a) #0 { 654 %r = fptoui half %a to i32 655 ret i32 %r 656} 657 658; CHECK-LABEL: test_fptoui_i64( 659; CHECK: ld.param.b16 [[A:%h[0-9]+]], [test_fptoui_i64_param_0]; 660; CHECK: cvt.rzi.u64.f16 [[R:%rd[0-9]+]], [[A]]; 661; CHECK: st.param.b64 [func_retval0+0], [[R]]; 662; CHECK: ret; 663define i64 @test_fptoui_i64(half %a) #0 { 664 %r = fptoui half %a to i64 665 ret i64 %r 666} 667 668; CHECK-LABEL: test_uitofp_i32( 669; CHECK: ld.param.u32 [[A:%r[0-9]+]], [test_uitofp_i32_param_0]; 670; CHECK: cvt.rn.f16.u32 [[R:%h[0-9]+]], [[A]]; 671; CHECK: st.param.b16 [func_retval0+0], [[R]]; 672; CHECK: ret; 673define half @test_uitofp_i32(i32 %a) #0 { 674 %r = uitofp i32 %a to half 675 ret half %r 676} 677 678; CHECK-LABEL: test_uitofp_i64( 679; CHECK: ld.param.u64 [[A:%rd[0-9]+]], [test_uitofp_i64_param_0]; 680; CHECK: cvt.rn.f16.u64 [[R:%h[0-9]+]], [[A]]; 681; CHECK: st.param.b16 [func_retval0+0], [[R]]; 682; CHECK: ret; 683define half @test_uitofp_i64(i64 %a) #0 { 684 %r = uitofp i64 %a to half 685 ret half %r 686} 687 688; CHECK-LABEL: test_sitofp_i32( 689; CHECK: ld.param.u32 [[A:%r[0-9]+]], [test_sitofp_i32_param_0]; 690; CHECK: cvt.rn.f16.s32 [[R:%h[0-9]+]], [[A]]; 691; CHECK: st.param.b16 [func_retval0+0], [[R]]; 692; CHECK: ret; 693define half @test_sitofp_i32(i32 %a) #0 { 694 %r = sitofp i32 %a to half 695 ret half %r 696} 697 698; CHECK-LABEL: test_sitofp_i64( 699; CHECK: ld.param.u64 [[A:%rd[0-9]+]], [test_sitofp_i64_param_0]; 700; CHECK: cvt.rn.f16.s64 [[R:%h[0-9]+]], [[A]]; 701; CHECK: st.param.b16 [func_retval0+0], [[R]]; 702; CHECK: ret; 703define half @test_sitofp_i64(i64 %a) #0 { 704 %r = sitofp i64 %a to half 705 ret half %r 706} 707 708; CHECK-LABEL: test_uitofp_i32_fadd( 709; CHECK-DAG: ld.param.u32 [[A:%r[0-9]+]], [test_uitofp_i32_fadd_param_0]; 710; CHECK-DAG: cvt.rn.f16.u32 [[C:%h[0-9]+]], [[A]]; 711; CHECK-DAG: ld.param.b16 [[B:%h[0-9]+]], [test_uitofp_i32_fadd_param_1]; 712; CHECK-F16-NOFTZ: add.rn.f16 [[R:%h[0-9]+]], [[B]], [[C]]; 713; CHECK-F16-FTZ: add.rn.ftz.f16 [[R:%h[0-9]+]], [[B]], [[C]]; 714; CHECK-NOF16-DAG: cvt.f32.f16 [[B32:%f[0-9]+]], [[B]] 715; CHECK-NOF16-DAG: cvt.f32.f16 [[C32:%f[0-9]+]], [[C]] 716; CHECK-NOF16-NEXT: add.rn.f32 [[R32:%f[0-9]+]], [[B32]], [[C32]]; 717; CHECK-NOF16-NEXT: cvt.rn.f16.f32 [[R:%h[0-9]+]], [[R32]] 718; CHECK: st.param.b16 [func_retval0+0], [[R]]; 719; CHECK: ret; 720define half @test_uitofp_i32_fadd(i32 %a, half %b) #0 { 721 %c = uitofp i32 %a to half 722 %r = fadd half %b, %c 723 ret half %r 724} 725 726; CHECK-LABEL: test_sitofp_i32_fadd( 727; CHECK-DAG: ld.param.u32 [[A:%r[0-9]+]], [test_sitofp_i32_fadd_param_0]; 728; CHECK-DAG: cvt.rn.f16.s32 [[C:%h[0-9]+]], [[A]]; 729; CHECK-DAG: ld.param.b16 [[B:%h[0-9]+]], [test_sitofp_i32_fadd_param_1]; 730; CHECK-F16-NOFTZ: add.rn.f16 [[R:%h[0-9]+]], [[B]], [[C]]; 731; CHECK-F16-FTZ: add.rn.ftz.f16 [[R:%h[0-9]+]], [[B]], [[C]]; 732; XCHECK-NOF16-DAG: cvt.f32.f16 [[B32:%f[0-9]+]], [[B]] 733; XCHECK-NOF16-DAG: cvt.f32.f16 [[C32:%f[0-9]+]], [[C]] 734; XCHECK-NOF16-NEXT: add.rn.f32 [[R32:%f[0-9]+]], [[B32]], [[C32]]; 735; XCHECK-NOF16-NEXT: cvt.rn.f16.f32 [[R:%h[0-9]+]], [[R32]] 736; CHECK: st.param.b16 [func_retval0+0], [[R]]; 737; CHECK: ret; 738define half @test_sitofp_i32_fadd(i32 %a, half %b) #0 { 739 %c = sitofp i32 %a to half 740 %r = fadd half %b, %c 741 ret half %r 742} 743 744; CHECK-LABEL: test_fptrunc_float( 745; CHECK: ld.param.f32 [[A:%f[0-9]+]], [test_fptrunc_float_param_0]; 746; CHECK: cvt.rn.f16.f32 [[R:%h[0-9]+]], [[A]]; 747; CHECK: st.param.b16 [func_retval0+0], [[R]]; 748; CHECK: ret; 749define half @test_fptrunc_float(float %a) #0 { 750 %r = fptrunc float %a to half 751 ret half %r 752} 753 754; CHECK-LABEL: test_fptrunc_double( 755; CHECK: ld.param.f64 [[A:%fd[0-9]+]], [test_fptrunc_double_param_0]; 756; CHECK: cvt.rn.f16.f64 [[R:%h[0-9]+]], [[A]]; 757; CHECK: st.param.b16 [func_retval0+0], [[R]]; 758; CHECK: ret; 759define half @test_fptrunc_double(double %a) #0 { 760 %r = fptrunc double %a to half 761 ret half %r 762} 763 764; CHECK-LABEL: test_fpext_float( 765; CHECK: ld.param.b16 [[A:%h[0-9]+]], [test_fpext_float_param_0]; 766; CHECK-NOFTZ: cvt.f32.f16 [[R:%f[0-9]+]], [[A]]; 767; CHECK-F16-FTZ: cvt.ftz.f32.f16 [[R:%f[0-9]+]], [[A]]; 768; CHECK: st.param.f32 [func_retval0+0], [[R]]; 769; CHECK: ret; 770define float @test_fpext_float(half %a) #0 { 771 %r = fpext half %a to float 772 ret float %r 773} 774 775; CHECK-LABEL: test_fpext_double( 776; CHECK: ld.param.b16 [[A:%h[0-9]+]], [test_fpext_double_param_0]; 777; CHECK: cvt.f64.f16 [[R:%fd[0-9]+]], [[A]]; 778; CHECK: st.param.f64 [func_retval0+0], [[R]]; 779; CHECK: ret; 780define double @test_fpext_double(half %a) #0 { 781 %r = fpext half %a to double 782 ret double %r 783} 784 785 786; CHECK-LABEL: test_bitcast_halftoi16( 787; CHECK: ld.param.b16 [[AH:%h[0-9]+]], [test_bitcast_halftoi16_param_0]; 788; CHECK: mov.b16 [[AS:%rs[0-9]+]], [[AH]] 789; CHECK: cvt.u32.u16 [[R:%r[0-9]+]], [[AS]] 790; CHECK: st.param.b32 [func_retval0+0], [[R]]; 791; CHECK: ret; 792define i16 @test_bitcast_halftoi16(half %a) #0 { 793 %r = bitcast half %a to i16 794 ret i16 %r 795} 796 797; CHECK-LABEL: test_bitcast_i16tohalf( 798; CHECK: ld.param.u16 [[AS:%rs[0-9]+]], [test_bitcast_i16tohalf_param_0]; 799; CHECK: mov.b16 [[AH:%h[0-9]+]], [[AS]] 800; CHECK: st.param.b16 [func_retval0+0], [[AH]]; 801; CHECK: ret; 802define half @test_bitcast_i16tohalf(i16 %a) #0 { 803 %r = bitcast i16 %a to half 804 ret half %r 805} 806 807 808declare half @llvm.sqrt.f16(half %a) #0 809declare half @llvm.powi.f16.i32(half %a, i32 %b) #0 810declare half @llvm.sin.f16(half %a) #0 811declare half @llvm.cos.f16(half %a) #0 812declare half @llvm.pow.f16(half %a, half %b) #0 813declare half @llvm.exp.f16(half %a) #0 814declare half @llvm.exp2.f16(half %a) #0 815declare half @llvm.log.f16(half %a) #0 816declare half @llvm.log10.f16(half %a) #0 817declare half @llvm.log2.f16(half %a) #0 818declare half @llvm.fma.f16(half %a, half %b, half %c) #0 819declare half @llvm.fabs.f16(half %a) #0 820declare half @llvm.minnum.f16(half %a, half %b) #0 821declare half @llvm.maxnum.f16(half %a, half %b) #0 822declare half @llvm.copysign.f16(half %a, half %b) #0 823declare half @llvm.floor.f16(half %a) #0 824declare half @llvm.ceil.f16(half %a) #0 825declare half @llvm.trunc.f16(half %a) #0 826declare half @llvm.rint.f16(half %a) #0 827declare half @llvm.nearbyint.f16(half %a) #0 828declare half @llvm.round.f16(half %a) #0 829declare half @llvm.fmuladd.f16(half %a, half %b, half %c) #0 830 831; CHECK-LABEL: test_sqrt( 832; CHECK: ld.param.b16 [[A:%h[0-9]+]], [test_sqrt_param_0]; 833; CHECK-NOFTZ: cvt.f32.f16 [[AF:%f[0-9]+]], [[A]]; 834; CHECK-NOFTZ: sqrt.rn.f32 [[RF:%f[0-9]+]], [[AF]]; 835; CHECK-F16-FTZ: cvt.ftz.f32.f16 [[AF:%f[0-9]+]], [[A]]; 836; CHECK-F16-FTZ: sqrt.rn.ftz.f32 [[RF:%f[0-9]+]], [[AF]]; 837; CHECK: cvt.rn.f16.f32 [[R:%h[0-9]+]], [[RF]]; 838; CHECK: st.param.b16 [func_retval0+0], [[R]]; 839; CHECK: ret; 840define half @test_sqrt(half %a) #0 { 841 %r = call half @llvm.sqrt.f16(half %a) 842 ret half %r 843} 844 845;;; Can't do this yet: requires libcall. 846; XCHECK-LABEL: test_powi( 847;define half @test_powi(half %a, i32 %b) #0 { 848; %r = call half @llvm.powi.f16.i32(half %a, i32 %b) 849; ret half %r 850;} 851 852; CHECK-LABEL: test_sin( 853; CHECK: ld.param.b16 [[A:%h[0-9]+]], [test_sin_param_0]; 854; CHECK-NOFTZ: cvt.f32.f16 [[AF:%f[0-9]+]], [[A]]; 855; CHECK-F16-FTZ: cvt.ftz.f32.f16 [[AF:%f[0-9]+]], [[A]]; 856; CHECK: sin.approx.f32 [[RF:%f[0-9]+]], [[AF]]; 857; CHECK: cvt.rn.f16.f32 [[R:%h[0-9]+]], [[RF]]; 858; CHECK: st.param.b16 [func_retval0+0], [[R]]; 859; CHECK: ret; 860define half @test_sin(half %a) #0 #1 { 861 %r = call half @llvm.sin.f16(half %a) 862 ret half %r 863} 864 865; CHECK-LABEL: test_cos( 866; CHECK: ld.param.b16 [[A:%h[0-9]+]], [test_cos_param_0]; 867; CHECK-NOFTZ: cvt.f32.f16 [[AF:%f[0-9]+]], [[A]]; 868; CHECK-F16-FTZ: cvt.ftz.f32.f16 [[AF:%f[0-9]+]], [[A]]; 869; CHECK: cos.approx.f32 [[RF:%f[0-9]+]], [[AF]]; 870; CHECK: cvt.rn.f16.f32 [[R:%h[0-9]+]], [[RF]]; 871; CHECK: st.param.b16 [func_retval0+0], [[R]]; 872; CHECK: ret; 873define half @test_cos(half %a) #0 #1 { 874 %r = call half @llvm.cos.f16(half %a) 875 ret half %r 876} 877 878;;; Can't do this yet: requires libcall. 879; XCHECK-LABEL: test_pow( 880;define half @test_pow(half %a, half %b) #0 { 881; %r = call half @llvm.pow.f16(half %a, half %b) 882; ret half %r 883;} 884 885;;; Can't do this yet: requires libcall. 886; XCHECK-LABEL: test_exp( 887;define half @test_exp(half %a) #0 { 888; %r = call half @llvm.exp.f16(half %a) 889; ret half %r 890;} 891 892;;; Can't do this yet: requires libcall. 893; XCHECK-LABEL: test_exp2( 894;define half @test_exp2(half %a) #0 { 895; %r = call half @llvm.exp2.f16(half %a) 896; ret half %r 897;} 898 899;;; Can't do this yet: requires libcall. 900; XCHECK-LABEL: test_log( 901;define half @test_log(half %a) #0 { 902; %r = call half @llvm.log.f16(half %a) 903; ret half %r 904;} 905 906;;; Can't do this yet: requires libcall. 907; XCHECK-LABEL: test_log10( 908;define half @test_log10(half %a) #0 { 909; %r = call half @llvm.log10.f16(half %a) 910; ret half %r 911;} 912 913;;; Can't do this yet: requires libcall. 914; XCHECK-LABEL: test_log2( 915;define half @test_log2(half %a) #0 { 916; %r = call half @llvm.log2.f16(half %a) 917; ret half %r 918;} 919 920; CHECK-LABEL: test_fma( 921; CHECK-DAG: ld.param.b16 [[A:%h[0-9]+]], [test_fma_param_0]; 922; CHECK-DAG: ld.param.b16 [[B:%h[0-9]+]], [test_fma_param_1]; 923; CHECK-DAG: ld.param.b16 [[C:%h[0-9]+]], [test_fma_param_2]; 924; CHECK-F16-NOFTZ: fma.rn.f16 [[R:%h[0-9]+]], [[A]], [[B]], [[C]]; 925; CHECK-F16-FTZ: fma.rn.ftz.f16 [[R:%h[0-9]+]], [[A]], [[B]], [[C]]; 926; CHECK-NOF16-DAG: cvt.f32.f16 [[A32:%f[0-9]+]], [[A]] 927; CHECK-NOF16-DAG: cvt.f32.f16 [[B32:%f[0-9]+]], [[B]] 928; CHECK-NOF16-DAG: cvt.f32.f16 [[C32:%f[0-9]+]], [[C]] 929; CHECK-NOF16-NEXT: fma.rn.f32 [[R32:%f[0-9]+]], [[A32]], [[B32]], [[C32]]; 930; CHECK-NOF16-NEXT: cvt.rn.f16.f32 [[R:%h[0-9]+]], [[R32]] 931; CHECK: st.param.b16 [func_retval0+0], [[R]]; 932; CHECK: ret 933define half @test_fma(half %a, half %b, half %c) #0 { 934 %r = call half @llvm.fma.f16(half %a, half %b, half %c) 935 ret half %r 936} 937 938; CHECK-LABEL: test_fabs( 939; CHECK: ld.param.b16 [[A:%h[0-9]+]], [test_fabs_param_0]; 940; CHECK-NOFTZ: cvt.f32.f16 [[AF:%f[0-9]+]], [[A]]; 941; CHECK-NOFTZ: abs.f32 [[RF:%f[0-9]+]], [[AF]]; 942; CHECK-F16-FTZ: cvt.ftz.f32.f16 [[AF:%f[0-9]+]], [[A]]; 943; CHECK-F16-FTZ: abs.ftz.f32 [[RF:%f[0-9]+]], [[AF]]; 944; CHECK: cvt.rn.f16.f32 [[R:%h[0-9]+]], [[RF]]; 945; CHECK: st.param.b16 [func_retval0+0], [[R]]; 946; CHECK: ret; 947define half @test_fabs(half %a) #0 { 948 %r = call half @llvm.fabs.f16(half %a) 949 ret half %r 950} 951 952; CHECK-LABEL: test_minnum( 953; CHECK-DAG: ld.param.b16 [[A:%h[0-9]+]], [test_minnum_param_0]; 954; CHECK-DAG: ld.param.b16 [[B:%h[0-9]+]], [test_minnum_param_1]; 955; CHECK-NOFTZ-DAG: cvt.f32.f16 [[AF:%f[0-9]+]], [[A]]; 956; CHECK-NOFTZ-DAG: cvt.f32.f16 [[BF:%f[0-9]+]], [[B]]; 957; CHECK-NOFTZ: min.f32 [[RF:%f[0-9]+]], [[AF]], [[BF]]; 958; CHECK-F16-FTZ-DAG: cvt.ftz.f32.f16 [[AF:%f[0-9]+]], [[A]]; 959; CHECK-F16-FTZ-DAG: cvt.ftz.f32.f16 [[BF:%f[0-9]+]], [[B]]; 960; CHECK-F16-FTZ: min.ftz.f32 [[RF:%f[0-9]+]], [[AF]], [[BF]]; 961; CHECK: cvt.rn.f16.f32 [[R:%h[0-9]+]], [[RF]]; 962; CHECK: st.param.b16 [func_retval0+0], [[R]]; 963; CHECK: ret; 964define half @test_minnum(half %a, half %b) #0 { 965 %r = call half @llvm.minnum.f16(half %a, half %b) 966 ret half %r 967} 968 969; CHECK-LABEL: test_maxnum( 970; CHECK-DAG: ld.param.b16 [[A:%h[0-9]+]], [test_maxnum_param_0]; 971; CHECK-DAG: ld.param.b16 [[B:%h[0-9]+]], [test_maxnum_param_1]; 972; CHECK-NOFTZ-DAG: cvt.f32.f16 [[AF:%f[0-9]+]], [[A]]; 973; CHECK-NOFTZ-DAG: cvt.f32.f16 [[BF:%f[0-9]+]], [[B]]; 974; CHECK-NOFTZ: max.f32 [[RF:%f[0-9]+]], [[AF]], [[BF]]; 975; CHECK-F16-FTZ-DAG: cvt.ftz.f32.f16 [[AF:%f[0-9]+]], [[A]]; 976; CHECK-F16-FTZ-DAG: cvt.ftz.f32.f16 [[BF:%f[0-9]+]], [[B]]; 977; CHECK-F16-FTZ: max.ftz.f32 [[RF:%f[0-9]+]], [[AF]], [[BF]]; 978; CHECK: cvt.rn.f16.f32 [[R:%h[0-9]+]], [[RF]]; 979; CHECK: st.param.b16 [func_retval0+0], [[R]]; 980; CHECK: ret; 981define half @test_maxnum(half %a, half %b) #0 { 982 %r = call half @llvm.maxnum.f16(half %a, half %b) 983 ret half %r 984} 985 986; CHECK-LABEL: test_copysign( 987; CHECK-DAG: ld.param.b16 [[AH:%h[0-9]+]], [test_copysign_param_0]; 988; CHECK-DAG: ld.param.b16 [[BH:%h[0-9]+]], [test_copysign_param_1]; 989; CHECK-DAG: mov.b16 [[AS:%rs[0-9]+]], [[AH]]; 990; CHECK-DAG: mov.b16 [[BS:%rs[0-9]+]], [[BH]]; 991; CHECK-DAG: and.b16 [[AX:%rs[0-9]+]], [[AS]], 32767; 992; CHECK-DAG: and.b16 [[BX:%rs[0-9]+]], [[BS]], -32768; 993; CHECK: or.b16 [[RX:%rs[0-9]+]], [[AX]], [[BX]]; 994; CHECK: mov.b16 [[R:%h[0-9]+]], [[RX]]; 995; CHECK: st.param.b16 [func_retval0+0], [[R]]; 996; CHECK: ret; 997define half @test_copysign(half %a, half %b) #0 { 998 %r = call half @llvm.copysign.f16(half %a, half %b) 999 ret half %r 1000} 1001 1002; CHECK-LABEL: test_copysign_f32( 1003; CHECK-DAG: ld.param.b16 [[AH:%h[0-9]+]], [test_copysign_f32_param_0]; 1004; CHECK-DAG: ld.param.f32 [[BF:%f[0-9]+]], [test_copysign_f32_param_1]; 1005; CHECK-DAG: mov.b16 [[A:%rs[0-9]+]], [[AH]]; 1006; CHECK-DAG: mov.b32 [[B:%r[0-9]+]], [[BF]]; 1007; CHECK-DAG: and.b16 [[AX:%rs[0-9]+]], [[A]], 32767; 1008; CHECK-DAG: and.b32 [[BX0:%r[0-9]+]], [[B]], -2147483648; 1009; CHECK-DAG: shr.u32 [[BX1:%r[0-9]+]], [[BX0]], 16; 1010; CHECK-DAG: cvt.u16.u32 [[BX2:%rs[0-9]+]], [[BX1]]; 1011; CHECK: or.b16 [[RX:%rs[0-9]+]], [[AX]], [[BX2]]; 1012; CHECK: mov.b16 [[R:%h[0-9]+]], [[RX]]; 1013; CHECK: st.param.b16 [func_retval0+0], [[R]]; 1014; CHECK: ret; 1015define half @test_copysign_f32(half %a, float %b) #0 { 1016 %tb = fptrunc float %b to half 1017 %r = call half @llvm.copysign.f16(half %a, half %tb) 1018 ret half %r 1019} 1020 1021; CHECK-LABEL: test_copysign_f64( 1022; CHECK-DAG: ld.param.b16 [[AH:%h[0-9]+]], [test_copysign_f64_param_0]; 1023; CHECK-DAG: ld.param.f64 [[BD:%fd[0-9]+]], [test_copysign_f64_param_1]; 1024; CHECK-DAG: mov.b16 [[A:%rs[0-9]+]], [[AH]]; 1025; CHECK-DAG: mov.b64 [[B:%rd[0-9]+]], [[BD]]; 1026; CHECK-DAG: and.b16 [[AX:%rs[0-9]+]], [[A]], 32767; 1027; CHECK-DAG: and.b64 [[BX0:%rd[0-9]+]], [[B]], -9223372036854775808; 1028; CHECK-DAG: shr.u64 [[BX1:%rd[0-9]+]], [[BX0]], 48; 1029; CHECK-DAG: cvt.u16.u64 [[BX2:%rs[0-9]+]], [[BX1]]; 1030; CHECK: or.b16 [[RX:%rs[0-9]+]], [[AX]], [[BX2]]; 1031; CHECK: mov.b16 [[R:%h[0-9]+]], [[RX]]; 1032; CHECK: st.param.b16 [func_retval0+0], [[R]]; 1033; CHECK: ret; 1034define half @test_copysign_f64(half %a, double %b) #0 { 1035 %tb = fptrunc double %b to half 1036 %r = call half @llvm.copysign.f16(half %a, half %tb) 1037 ret half %r 1038} 1039 1040; CHECK-LABEL: test_copysign_extended( 1041; CHECK-DAG: ld.param.b16 [[AH:%h[0-9]+]], [test_copysign_extended_param_0]; 1042; CHECK-DAG: ld.param.b16 [[BH:%h[0-9]+]], [test_copysign_extended_param_1]; 1043; CHECK-DAG: mov.b16 [[AS:%rs[0-9]+]], [[AH]]; 1044; CHECK-DAG: mov.b16 [[BS:%rs[0-9]+]], [[BH]]; 1045; CHECK-DAG: and.b16 [[AX:%rs[0-9]+]], [[AS]], 32767; 1046; CHECK-DAG: and.b16 [[BX:%rs[0-9]+]], [[BS]], -32768; 1047; CHECK: or.b16 [[RX:%rs[0-9]+]], [[AX]], [[BX]]; 1048; CHECK: mov.b16 [[R:%h[0-9]+]], [[RX]]; 1049; CHECK-NOFTZ: cvt.f32.f16 [[XR:%f[0-9]+]], [[R]]; 1050; CHECK-F16-FTZ: cvt.ftz.f32.f16 [[XR:%f[0-9]+]], [[R]]; 1051; CHECK: st.param.f32 [func_retval0+0], [[XR]]; 1052; CHECK: ret; 1053define float @test_copysign_extended(half %a, half %b) #0 { 1054 %r = call half @llvm.copysign.f16(half %a, half %b) 1055 %xr = fpext half %r to float 1056 ret float %xr 1057} 1058 1059; CHECK-LABEL: test_floor( 1060; CHECK: ld.param.b16 [[A:%h[0-9]+]], [test_floor_param_0]; 1061; CHECK: cvt.rmi.f16.f16 [[R:%h[0-9]+]], [[A]]; 1062; CHECK: st.param.b16 [func_retval0+0], [[R]]; 1063; CHECK: ret; 1064define half @test_floor(half %a) #0 { 1065 %r = call half @llvm.floor.f16(half %a) 1066 ret half %r 1067} 1068 1069; CHECK-LABEL: test_ceil( 1070; CHECK: ld.param.b16 [[A:%h[0-9]+]], [test_ceil_param_0]; 1071; CHECK: cvt.rpi.f16.f16 [[R:%h[0-9]+]], [[A]]; 1072; CHECK: st.param.b16 [func_retval0+0], [[R]]; 1073; CHECK: ret; 1074define half @test_ceil(half %a) #0 { 1075 %r = call half @llvm.ceil.f16(half %a) 1076 ret half %r 1077} 1078 1079; CHECK-LABEL: test_trunc( 1080; CHECK: ld.param.b16 [[A:%h[0-9]+]], [test_trunc_param_0]; 1081; CHECK: cvt.rzi.f16.f16 [[R:%h[0-9]+]], [[A]]; 1082; CHECK: st.param.b16 [func_retval0+0], [[R]]; 1083; CHECK: ret; 1084define half @test_trunc(half %a) #0 { 1085 %r = call half @llvm.trunc.f16(half %a) 1086 ret half %r 1087} 1088 1089; CHECK-LABEL: test_rint( 1090; CHECK: ld.param.b16 [[A:%h[0-9]+]], [test_rint_param_0]; 1091; CHECK: cvt.rni.f16.f16 [[R:%h[0-9]+]], [[A]]; 1092; CHECK: st.param.b16 [func_retval0+0], [[R]]; 1093; CHECK: ret; 1094define half @test_rint(half %a) #0 { 1095 %r = call half @llvm.rint.f16(half %a) 1096 ret half %r 1097} 1098 1099; CHECK-LABEL: test_nearbyint( 1100; CHECK: ld.param.b16 [[A:%h[0-9]+]], [test_nearbyint_param_0]; 1101; CHECK: cvt.rni.f16.f16 [[R:%h[0-9]+]], [[A]]; 1102; CHECK: st.param.b16 [func_retval0+0], [[R]]; 1103; CHECK: ret; 1104define half @test_nearbyint(half %a) #0 { 1105 %r = call half @llvm.nearbyint.f16(half %a) 1106 ret half %r 1107} 1108 1109; CHECK-LABEL: test_round( 1110; CHECK: ld.param.b16 {{.*}}, [test_round_param_0]; 1111; check the use of sign mask and 0.5 to implement round 1112; CHECK: and.b32 [[R:%r[0-9]+]], {{.*}}, -2147483648; 1113; CHECK: or.b32 {{.*}}, [[R]], 1056964608; 1114; CHECK: st.param.b16 [func_retval0+0], {{.*}}; 1115; CHECK: ret; 1116define half @test_round(half %a) #0 { 1117 %r = call half @llvm.round.f16(half %a) 1118 ret half %r 1119} 1120 1121; CHECK-LABEL: test_fmuladd( 1122; CHECK-DAG: ld.param.b16 [[A:%h[0-9]+]], [test_fmuladd_param_0]; 1123; CHECK-DAG: ld.param.b16 [[B:%h[0-9]+]], [test_fmuladd_param_1]; 1124; CHECK-DAG: ld.param.b16 [[C:%h[0-9]+]], [test_fmuladd_param_2]; 1125; CHECK-F16-NOFTZ: fma.rn.f16 [[R:%h[0-9]+]], [[A]], [[B]], [[C]]; 1126; CHECK-F16-FTZ: fma.rn.ftz.f16 [[R:%h[0-9]+]], [[A]], [[B]], [[C]]; 1127; CHECK-NOF16-DAG: cvt.f32.f16 [[A32:%f[0-9]+]], [[A]] 1128; CHECK-NOF16-DAG: cvt.f32.f16 [[B32:%f[0-9]+]], [[B]] 1129; CHECK-NOF16-DAG: cvt.f32.f16 [[C32:%f[0-9]+]], [[C]] 1130; CHECK-NOF16-NEXT: fma.rn.f32 [[R32:%f[0-9]+]], [[A32]], [[B32]], [[C32]]; 1131; CHECK-NOF16-NEXT: cvt.rn.f16.f32 [[R:%h[0-9]+]], [[R32]] 1132; CHECK: st.param.b16 [func_retval0+0], [[R]]; 1133; CHECK: ret; 1134define half @test_fmuladd(half %a, half %b, half %c) #0 { 1135 %r = call half @llvm.fmuladd.f16(half %a, half %b, half %c) 1136 ret half %r 1137} 1138 1139attributes #0 = { nounwind } 1140attributes #1 = { "unsafe-fp-math" = "true" } 1141