1; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s 2 3; <256 x i32> 4 5; Function Attrs: nounwind 6define fastcc <256 x i32> @add_vv_v256i32(<256 x i32> %x, <256 x i32> %y) { 7; CHECK-LABEL: add_vv_v256i32: 8; CHECK: # %bb.0: 9; CHECK-NEXT: lea %s0, 256 10; CHECK-NEXT: lvl %s0 11; CHECK-NEXT: vadds.w.sx %v0, %v0, %v1 12; CHECK-NEXT: b.l.t (, %s10) 13 %z = add <256 x i32> %x, %y 14 ret <256 x i32> %z 15} 16 17; Function Attrs: nounwind 18define fastcc <256 x i32> @add_sv_v256i32(i32 %x, <256 x i32> %y) { 19; CHECK-LABEL: add_sv_v256i32: 20; CHECK: # %bb.0: 21; CHECK-NEXT: and %s0, %s0, (32)0 22; CHECK-NEXT: lea %s1, 256 23; CHECK-NEXT: lvl %s1 24; CHECK-NEXT: vadds.w.sx %v0, %s0, %v0 25; CHECK-NEXT: b.l.t (, %s10) 26 %xins = insertelement <256 x i32> undef, i32 %x, i32 0 27 %vx = shufflevector <256 x i32> %xins, <256 x i32> undef, <256 x i32> zeroinitializer 28 %z = add <256 x i32> %vx, %y 29 ret <256 x i32> %z 30} 31 32; Function Attrs: nounwind 33define fastcc <256 x i32> @add_vs_v256i32(<256 x i32> %x, i32 %y) { 34; CHECK-LABEL: add_vs_v256i32: 35; CHECK: # %bb.0: 36; CHECK-NEXT: and %s0, %s0, (32)0 37; CHECK-NEXT: lea %s1, 256 38; CHECK-NEXT: lvl %s1 39; CHECK-NEXT: vadds.w.sx %v0, %s0, %v0 40; CHECK-NEXT: b.l.t (, %s10) 41 %yins = insertelement <256 x i32> undef, i32 %y, i32 0 42 %vy = shufflevector <256 x i32> %yins, <256 x i32> undef, <256 x i32> zeroinitializer 43 %z = add <256 x i32> %x, %vy 44 ret <256 x i32> %z 45} 46 47 48 49; <256 x i64> 50 51; Function Attrs: nounwind 52define fastcc <256 x i64> @add_vv_v256i64(<256 x i64> %x, <256 x i64> %y) { 53; CHECK-LABEL: add_vv_v256i64: 54; CHECK: # %bb.0: 55; CHECK-NEXT: lea %s0, 256 56; CHECK-NEXT: lvl %s0 57; CHECK-NEXT: vadds.l %v0, %v0, %v1 58; CHECK-NEXT: b.l.t (, %s10) 59 %z = add <256 x i64> %x, %y 60 ret <256 x i64> %z 61} 62 63; Function Attrs: nounwind 64define fastcc <256 x i64> @add_sv_v256i64(i64 %x, <256 x i64> %y) { 65; CHECK-LABEL: add_sv_v256i64: 66; CHECK: # %bb.0: 67; CHECK-NEXT: lea %s1, 256 68; CHECK-NEXT: lvl %s1 69; CHECK-NEXT: vadds.l %v0, %s0, %v0 70; CHECK-NEXT: b.l.t (, %s10) 71 %xins = insertelement <256 x i64> undef, i64 %x, i32 0 72 %vx = shufflevector <256 x i64> %xins, <256 x i64> undef, <256 x i32> zeroinitializer 73 %z = add <256 x i64> %vx, %y 74 ret <256 x i64> %z 75} 76 77; Function Attrs: nounwind 78define fastcc <256 x i64> @add_vs_v256i64(<256 x i64> %x, i64 %y) { 79; CHECK-LABEL: add_vs_v256i64: 80; CHECK: # %bb.0: 81; CHECK-NEXT: lea %s1, 256 82; CHECK-NEXT: lvl %s1 83; CHECK-NEXT: vadds.l %v0, %s0, %v0 84; CHECK-NEXT: b.l.t (, %s10) 85 %yins = insertelement <256 x i64> undef, i64 %y, i32 0 86 %vy = shufflevector <256 x i64> %yins, <256 x i64> undef, <256 x i32> zeroinitializer 87 %z = add <256 x i64> %x, %vy 88 ret <256 x i64> %z 89} 90 91; <128 x i64> 92; We expect this to be widened. 93 94; Function Attrs: nounwind 95define fastcc <128 x i64> @add_vv_v128i64(<128 x i64> %x, <128 x i64> %y) { 96; CHECK-LABEL: add_vv_v128i64: 97; CHECK: # %bb.0: 98; CHECK-NEXT: lea %s0, 256 99; CHECK-NEXT: lvl %s0 100; CHECK-NEXT: vadds.l %v0, %v0, %v1 101; CHECK-NEXT: b.l.t (, %s10) 102 %z = add <128 x i64> %x, %y 103 ret <128 x i64> %z 104} 105 106; <256 x i16> 107; We expect promotion. 108 109; Function Attrs: nounwind 110define fastcc <256 x i16> @add_vv_v256i16(<256 x i16> %x, <256 x i16> %y) { 111; CHECK-LABEL: add_vv_v256i16: 112; CHECK: # %bb.0: 113; CHECK-NEXT: lea %s0, 256 114; CHECK-NEXT: lvl %s0 115; CHECK-NEXT: vadds.w.sx %v0, %v0, %v1 116; CHECK-NEXT: b.l.t (, %s10) 117 %z = add <256 x i16> %x, %y 118 ret <256 x i16> %z 119} 120 121; <128 x i16> 122; We expect this to be scalarized (for now). 123 124; Function Attrs: nounwind 125define fastcc <128 x i16> @add_vv_v128i16(<128 x i16> %x, <128 x i16> %y) { 126; CHECK-LABEL: add_vv_v128i16: 127; CHECK-NOT: vadd 128 %z = add <128 x i16> %x, %y 129 ret <128 x i16> %z 130} 131 132