1 // REQUIRES: aarch64-registered-target
2 // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s
3 // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - -x c++ %s | FileCheck %s
4 // RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s
5 // RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - -x c++ %s | FileCheck %s
6 // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -o - %s >/dev/null
7 #include <arm_sve.h>
8
9 #ifdef SVE_OVERLOADED_FORMS
10 // A simple used,unused... macro, long enough to represent any SVE builtin.
11 #define SVE_ACLE_FUNC(A1,A2_UNUSED,A3,A4_UNUSED) A1##A3
12 #else
13 #define SVE_ACLE_FUNC(A1,A2,A3,A4) A1##A2##A3##A4
14 #endif
15
test_svnmad_f16_z(svbool_t pg,svfloat16_t op1,svfloat16_t op2,svfloat16_t op3)16 svfloat16_t test_svnmad_f16_z(svbool_t pg, svfloat16_t op1, svfloat16_t op2, svfloat16_t op3)
17 {
18 // CHECK-LABEL: test_svnmad_f16_z
19 // CHECK-DAG: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
20 // CHECK-DAG: %[[SEL:.*]] = call <vscale x 8 x half> @llvm.aarch64.sve.sel.nxv8f16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x half> %op1, <vscale x 8 x half> zeroinitializer)
21 // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x half> @llvm.aarch64.sve.fnmad.nxv8f16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x half> %[[SEL]], <vscale x 8 x half> %op2, <vscale x 8 x half> %op3)
22 // CHECK: ret <vscale x 8 x half> %[[INTRINSIC]]
23 return SVE_ACLE_FUNC(svnmad,_f16,_z,)(pg, op1, op2, op3);
24 }
25
test_svnmad_f32_z(svbool_t pg,svfloat32_t op1,svfloat32_t op2,svfloat32_t op3)26 svfloat32_t test_svnmad_f32_z(svbool_t pg, svfloat32_t op1, svfloat32_t op2, svfloat32_t op3)
27 {
28 // CHECK-LABEL: test_svnmad_f32_z
29 // CHECK-DAG: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
30 // CHECK-DAG: %[[SEL:.*]] = call <vscale x 4 x float> @llvm.aarch64.sve.sel.nxv4f32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x float> %op1, <vscale x 4 x float> zeroinitializer)
31 // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x float> @llvm.aarch64.sve.fnmad.nxv4f32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x float> %[[SEL]], <vscale x 4 x float> %op2, <vscale x 4 x float> %op3)
32 // CHECK: ret <vscale x 4 x float> %[[INTRINSIC]]
33 return SVE_ACLE_FUNC(svnmad,_f32,_z,)(pg, op1, op2, op3);
34 }
35
test_svnmad_f64_z(svbool_t pg,svfloat64_t op1,svfloat64_t op2,svfloat64_t op3)36 svfloat64_t test_svnmad_f64_z(svbool_t pg, svfloat64_t op1, svfloat64_t op2, svfloat64_t op3)
37 {
38 // CHECK-LABEL: test_svnmad_f64_z
39 // CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
40 // CHECK-DAG: %[[SEL:.*]] = call <vscale x 2 x double> @llvm.aarch64.sve.sel.nxv2f64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x double> %op1, <vscale x 2 x double> zeroinitializer)
41 // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x double> @llvm.aarch64.sve.fnmad.nxv2f64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x double> %[[SEL]], <vscale x 2 x double> %op2, <vscale x 2 x double> %op3)
42 // CHECK: ret <vscale x 2 x double> %[[INTRINSIC]]
43 return SVE_ACLE_FUNC(svnmad,_f64,_z,)(pg, op1, op2, op3);
44 }
45
test_svnmad_f16_m(svbool_t pg,svfloat16_t op1,svfloat16_t op2,svfloat16_t op3)46 svfloat16_t test_svnmad_f16_m(svbool_t pg, svfloat16_t op1, svfloat16_t op2, svfloat16_t op3)
47 {
48 // CHECK-LABEL: test_svnmad_f16_m
49 // CHECK: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
50 // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x half> @llvm.aarch64.sve.fnmad.nxv8f16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, <vscale x 8 x half> %op3)
51 // CHECK: ret <vscale x 8 x half> %[[INTRINSIC]]
52 return SVE_ACLE_FUNC(svnmad,_f16,_m,)(pg, op1, op2, op3);
53 }
54
test_svnmad_f32_m(svbool_t pg,svfloat32_t op1,svfloat32_t op2,svfloat32_t op3)55 svfloat32_t test_svnmad_f32_m(svbool_t pg, svfloat32_t op1, svfloat32_t op2, svfloat32_t op3)
56 {
57 // CHECK-LABEL: test_svnmad_f32_m
58 // CHECK: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
59 // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x float> @llvm.aarch64.sve.fnmad.nxv4f32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x float> %op1, <vscale x 4 x float> %op2, <vscale x 4 x float> %op3)
60 // CHECK: ret <vscale x 4 x float> %[[INTRINSIC]]
61 return SVE_ACLE_FUNC(svnmad,_f32,_m,)(pg, op1, op2, op3);
62 }
63
test_svnmad_f64_m(svbool_t pg,svfloat64_t op1,svfloat64_t op2,svfloat64_t op3)64 svfloat64_t test_svnmad_f64_m(svbool_t pg, svfloat64_t op1, svfloat64_t op2, svfloat64_t op3)
65 {
66 // CHECK-LABEL: test_svnmad_f64_m
67 // CHECK: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
68 // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x double> @llvm.aarch64.sve.fnmad.nxv2f64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x double> %op1, <vscale x 2 x double> %op2, <vscale x 2 x double> %op3)
69 // CHECK: ret <vscale x 2 x double> %[[INTRINSIC]]
70 return SVE_ACLE_FUNC(svnmad,_f64,_m,)(pg, op1, op2, op3);
71 }
72
test_svnmad_f16_x(svbool_t pg,svfloat16_t op1,svfloat16_t op2,svfloat16_t op3)73 svfloat16_t test_svnmad_f16_x(svbool_t pg, svfloat16_t op1, svfloat16_t op2, svfloat16_t op3)
74 {
75 // CHECK-LABEL: test_svnmad_f16_x
76 // CHECK: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
77 // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x half> @llvm.aarch64.sve.fnmad.nxv8f16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, <vscale x 8 x half> %op3)
78 // CHECK: ret <vscale x 8 x half> %[[INTRINSIC]]
79 return SVE_ACLE_FUNC(svnmad,_f16,_x,)(pg, op1, op2, op3);
80 }
81
test_svnmad_f32_x(svbool_t pg,svfloat32_t op1,svfloat32_t op2,svfloat32_t op3)82 svfloat32_t test_svnmad_f32_x(svbool_t pg, svfloat32_t op1, svfloat32_t op2, svfloat32_t op3)
83 {
84 // CHECK-LABEL: test_svnmad_f32_x
85 // CHECK: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
86 // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x float> @llvm.aarch64.sve.fnmad.nxv4f32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x float> %op1, <vscale x 4 x float> %op2, <vscale x 4 x float> %op3)
87 // CHECK: ret <vscale x 4 x float> %[[INTRINSIC]]
88 return SVE_ACLE_FUNC(svnmad,_f32,_x,)(pg, op1, op2, op3);
89 }
90
test_svnmad_f64_x(svbool_t pg,svfloat64_t op1,svfloat64_t op2,svfloat64_t op3)91 svfloat64_t test_svnmad_f64_x(svbool_t pg, svfloat64_t op1, svfloat64_t op2, svfloat64_t op3)
92 {
93 // CHECK-LABEL: test_svnmad_f64_x
94 // CHECK: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
95 // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x double> @llvm.aarch64.sve.fnmad.nxv2f64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x double> %op1, <vscale x 2 x double> %op2, <vscale x 2 x double> %op3)
96 // CHECK: ret <vscale x 2 x double> %[[INTRINSIC]]
97 return SVE_ACLE_FUNC(svnmad,_f64,_x,)(pg, op1, op2, op3);
98 }
99
test_svnmad_n_f16_z(svbool_t pg,svfloat16_t op1,svfloat16_t op2,float16_t op3)100 svfloat16_t test_svnmad_n_f16_z(svbool_t pg, svfloat16_t op1, svfloat16_t op2, float16_t op3)
101 {
102 // CHECK-LABEL: test_svnmad_n_f16_z
103 // CHECK-DAG: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
104 // CHECK-DAG: %[[DUP:.*]] = call <vscale x 8 x half> @llvm.aarch64.sve.dup.x.nxv8f16(half %op3)
105 // CHECK-DAG: %[[SEL:.*]] = call <vscale x 8 x half> @llvm.aarch64.sve.sel.nxv8f16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x half> %op1, <vscale x 8 x half> zeroinitializer)
106 // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x half> @llvm.aarch64.sve.fnmad.nxv8f16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x half> %[[SEL]], <vscale x 8 x half> %op2, <vscale x 8 x half> %[[DUP]])
107 // CHECK: ret <vscale x 8 x half> %[[INTRINSIC]]
108 return SVE_ACLE_FUNC(svnmad,_n_f16,_z,)(pg, op1, op2, op3);
109 }
110
test_svnmad_n_f32_z(svbool_t pg,svfloat32_t op1,svfloat32_t op2,float32_t op3)111 svfloat32_t test_svnmad_n_f32_z(svbool_t pg, svfloat32_t op1, svfloat32_t op2, float32_t op3)
112 {
113 // CHECK-LABEL: test_svnmad_n_f32_z
114 // CHECK-DAG: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
115 // CHECK-DAG: %[[DUP:.*]] = call <vscale x 4 x float> @llvm.aarch64.sve.dup.x.nxv4f32(float %op3)
116 // CHECK-DAG: %[[SEL:.*]] = call <vscale x 4 x float> @llvm.aarch64.sve.sel.nxv4f32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x float> %op1, <vscale x 4 x float> zeroinitializer)
117 // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x float> @llvm.aarch64.sve.fnmad.nxv4f32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x float> %[[SEL]], <vscale x 4 x float> %op2, <vscale x 4 x float> %[[DUP]])
118 // CHECK: ret <vscale x 4 x float> %[[INTRINSIC]]
119 return SVE_ACLE_FUNC(svnmad,_n_f32,_z,)(pg, op1, op2, op3);
120 }
121
test_svnmad_n_f64_z(svbool_t pg,svfloat64_t op1,svfloat64_t op2,float64_t op3)122 svfloat64_t test_svnmad_n_f64_z(svbool_t pg, svfloat64_t op1, svfloat64_t op2, float64_t op3)
123 {
124 // CHECK-LABEL: test_svnmad_n_f64_z
125 // CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
126 // CHECK-DAG: %[[DUP:.*]] = call <vscale x 2 x double> @llvm.aarch64.sve.dup.x.nxv2f64(double %op3)
127 // CHECK-DAG: %[[SEL:.*]] = call <vscale x 2 x double> @llvm.aarch64.sve.sel.nxv2f64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x double> %op1, <vscale x 2 x double> zeroinitializer)
128 // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x double> @llvm.aarch64.sve.fnmad.nxv2f64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x double> %[[SEL]], <vscale x 2 x double> %op2, <vscale x 2 x double> %[[DUP]])
129 // CHECK: ret <vscale x 2 x double> %[[INTRINSIC]]
130 return SVE_ACLE_FUNC(svnmad,_n_f64,_z,)(pg, op1, op2, op3);
131 }
132
test_svnmad_n_f16_m(svbool_t pg,svfloat16_t op1,svfloat16_t op2,float16_t op3)133 svfloat16_t test_svnmad_n_f16_m(svbool_t pg, svfloat16_t op1, svfloat16_t op2, float16_t op3)
134 {
135 // CHECK-LABEL: test_svnmad_n_f16_m
136 // CHECK-DAG: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
137 // CHECK-DAG: %[[DUP:.*]] = call <vscale x 8 x half> @llvm.aarch64.sve.dup.x.nxv8f16(half %op3)
138 // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x half> @llvm.aarch64.sve.fnmad.nxv8f16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, <vscale x 8 x half> %[[DUP]])
139 // CHECK: ret <vscale x 8 x half> %[[INTRINSIC]]
140 return SVE_ACLE_FUNC(svnmad,_n_f16,_m,)(pg, op1, op2, op3);
141 }
142
test_svnmad_n_f32_m(svbool_t pg,svfloat32_t op1,svfloat32_t op2,float32_t op3)143 svfloat32_t test_svnmad_n_f32_m(svbool_t pg, svfloat32_t op1, svfloat32_t op2, float32_t op3)
144 {
145 // CHECK-LABEL: test_svnmad_n_f32_m
146 // CHECK-DAG: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
147 // CHECK-DAG: %[[DUP:.*]] = call <vscale x 4 x float> @llvm.aarch64.sve.dup.x.nxv4f32(float %op3)
148 // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x float> @llvm.aarch64.sve.fnmad.nxv4f32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x float> %op1, <vscale x 4 x float> %op2, <vscale x 4 x float> %[[DUP]])
149 // CHECK: ret <vscale x 4 x float> %[[INTRINSIC]]
150 return SVE_ACLE_FUNC(svnmad,_n_f32,_m,)(pg, op1, op2, op3);
151 }
152
test_svnmad_n_f64_m(svbool_t pg,svfloat64_t op1,svfloat64_t op2,float64_t op3)153 svfloat64_t test_svnmad_n_f64_m(svbool_t pg, svfloat64_t op1, svfloat64_t op2, float64_t op3)
154 {
155 // CHECK-LABEL: test_svnmad_n_f64_m
156 // CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
157 // CHECK-DAG: %[[DUP:.*]] = call <vscale x 2 x double> @llvm.aarch64.sve.dup.x.nxv2f64(double %op3)
158 // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x double> @llvm.aarch64.sve.fnmad.nxv2f64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x double> %op1, <vscale x 2 x double> %op2, <vscale x 2 x double> %[[DUP]])
159 // CHECK: ret <vscale x 2 x double> %[[INTRINSIC]]
160 return SVE_ACLE_FUNC(svnmad,_n_f64,_m,)(pg, op1, op2, op3);
161 }
162
test_svnmad_n_f16_x(svbool_t pg,svfloat16_t op1,svfloat16_t op2,float16_t op3)163 svfloat16_t test_svnmad_n_f16_x(svbool_t pg, svfloat16_t op1, svfloat16_t op2, float16_t op3)
164 {
165 // CHECK-LABEL: test_svnmad_n_f16_x
166 // CHECK-DAG: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
167 // CHECK-DAG: %[[DUP:.*]] = call <vscale x 8 x half> @llvm.aarch64.sve.dup.x.nxv8f16(half %op3)
168 // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x half> @llvm.aarch64.sve.fnmad.nxv8f16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, <vscale x 8 x half> %[[DUP]])
169 // CHECK: ret <vscale x 8 x half> %[[INTRINSIC]]
170 return SVE_ACLE_FUNC(svnmad,_n_f16,_x,)(pg, op1, op2, op3);
171 }
172
test_svnmad_n_f32_x(svbool_t pg,svfloat32_t op1,svfloat32_t op2,float32_t op3)173 svfloat32_t test_svnmad_n_f32_x(svbool_t pg, svfloat32_t op1, svfloat32_t op2, float32_t op3)
174 {
175 // CHECK-LABEL: test_svnmad_n_f32_x
176 // CHECK-DAG: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
177 // CHECK-DAG: %[[DUP:.*]] = call <vscale x 4 x float> @llvm.aarch64.sve.dup.x.nxv4f32(float %op3)
178 // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x float> @llvm.aarch64.sve.fnmad.nxv4f32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x float> %op1, <vscale x 4 x float> %op2, <vscale x 4 x float> %[[DUP]])
179 // CHECK: ret <vscale x 4 x float> %[[INTRINSIC]]
180 return SVE_ACLE_FUNC(svnmad,_n_f32,_x,)(pg, op1, op2, op3);
181 }
182
test_svnmad_n_f64_x(svbool_t pg,svfloat64_t op1,svfloat64_t op2,float64_t op3)183 svfloat64_t test_svnmad_n_f64_x(svbool_t pg, svfloat64_t op1, svfloat64_t op2, float64_t op3)
184 {
185 // CHECK-LABEL: test_svnmad_n_f64_x
186 // CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
187 // CHECK-DAG: %[[DUP:.*]] = call <vscale x 2 x double> @llvm.aarch64.sve.dup.x.nxv2f64(double %op3)
188 // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x double> @llvm.aarch64.sve.fnmad.nxv2f64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x double> %op1, <vscale x 2 x double> %op2, <vscale x 2 x double> %[[DUP]])
189 // CHECK: ret <vscale x 2 x double> %[[INTRINSIC]]
190 return SVE_ACLE_FUNC(svnmad,_n_f64,_x,)(pg, op1, op2, op3);
191 }
192