1// REQUIRES: aarch64
2// RUN: llvm-mc -filetype=obj -triple=aarch64-none-linux %s -o %t.o
3// RUN: ld.lld --image-base=0x10000000 %t.o -o %t
4// RUN: llvm-objdump -d --no-show-raw-insn %t | FileCheck %s
5
6// Check that the ARM 64-bit ABI rules for undefined weak symbols are applied.
7// Branch instructions are resolved to the next instruction. Undefined
8// Symbols in relative are resolved to the place so S - P + A = A.
9// We place the image-base at 0x10000000 to test that a range extensions thunk
10// is not generated.
11 .weak target
12
13 .text
14 .global _start
15_start:
16// R_AARCH64_JUMP26
17 b target
18// R_AARCH64_CALL26
19 bl target
20// R_AARCH64_CONDBR19
21 b.eq target
22// R_AARCH64_TSTBR14
23 cbz x1, target
24// R_AARCH64_ADR_PREL_LO21
25 adr x0, target
26// R_AARCH64_ADR_PREL_PG_HI21
27 adrp x0, target
28// R_AARCH64_LD_PREL_LO19
29 ldr x8, target
30// R_AARCH64_PREL32
31 .word target - .
32// R_AARCH64_PREL64
33 .xword target - .
34// R_AARCH64_PREL16
35 .hword target - .
36// R_AARCH64_PLT32
37 .word target@PLT - .
38
39// CHECK: Disassembly of section .text:
40// CHECK-EMPTY:
41// CHECK-NEXT: 0000000010010120 <_start>:
42// CHECK-NEXT: 10010120: b       0x10010124
43// CHECK-NEXT: 10010124: bl      0x10010128
44// CHECK-NEXT: 10010128: b.eq    0x1001012c
45// CHECK-NEXT: 1001012c: cbz     x1, 0x10010130
46// CHECK-NEXT: 10010130: adr     x0, #0
47// CHECK-NEXT: 10010134: adrp    x0, 0x10010000
48// CHECK-NEXT: 10010138: ldr     x8, 0x10010138
49// CHECK:      1001013c: 00 00 00 00     .word   0x00000000
50// CHECK-NEXT: 10010140: 00 00 00 00     .word   0x00000000
51// CHECK-NEXT: 10010144: 00 00 00 00     .word   0x00000000
52// CHECK-NEXT: 10010148: 00 00 00 00     .word   0x00000000
53// CHECK-NEXT: 1001014c: 00 00           .short  0x0000
54