1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d -mattr=+d -O0 < %s \
3; RUN:    | FileCheck --check-prefix=SPILL-O0 %s
4; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d -mattr=+d -O2 < %s \
5; RUN:    | FileCheck --check-prefix=SPILL-O2 %s
6
7@.str = private unnamed_addr constant [6 x i8] c"hello\00", align 1
8
9define <vscale x 1 x double> @foo(<vscale x 1 x double> %a, <vscale x 1 x double> %b, <vscale x 1 x double> %c, i64 %gvl) nounwind
10; SPILL-O0-LABEL: foo:
11; SPILL-O0:       # %bb.0:
12; SPILL-O0-NEXT:    addi sp, sp, -32
13; SPILL-O0-NEXT:    sd ra, 24(sp) # 8-byte Folded Spill
14; SPILL-O0-NEXT:    csrr a1, vlenb
15; SPILL-O0-NEXT:    slli a1, a1, 1
16; SPILL-O0-NEXT:    sub sp, sp, a1
17; SPILL-O0-NEXT:    sd a0, 16(sp) # 8-byte Folded Spill
18; SPILL-O0-NEXT:    csrr a1, vlenb
19; SPILL-O0-NEXT:    add a1, sp, a1
20; SPILL-O0-NEXT:    addi a1, a1, 24
21; SPILL-O0-NEXT:    vs1r.v v8, (a1) # Unknown-size Folded Spill
22; SPILL-O0-NEXT:    vsetvli zero, a0, e64, m1, ta, mu
23; SPILL-O0-NEXT:    vfadd.vv v25, v8, v9
24; SPILL-O0-NEXT:    addi a0, sp, 24
25; SPILL-O0-NEXT:    vs1r.v v25, (a0) # Unknown-size Folded Spill
26; SPILL-O0-NEXT:    lui a0, %hi(.L.str)
27; SPILL-O0-NEXT:    addi a0, a0, %lo(.L.str)
28; SPILL-O0-NEXT:    call puts@plt
29; SPILL-O0-NEXT:    addi a1, sp, 24
30; SPILL-O0-NEXT:    vl1r.v v25, (a1) # Unknown-size Folded Reload
31; SPILL-O0-NEXT:    csrr a1, vlenb
32; SPILL-O0-NEXT:    add a1, sp, a1
33; SPILL-O0-NEXT:    addi a1, a1, 24
34; SPILL-O0-NEXT:    vl1r.v v8, (a1) # Unknown-size Folded Reload
35; SPILL-O0-NEXT:    # kill: def $x11 killed $x10
36; SPILL-O0-NEXT:    ld a0, 16(sp) # 8-byte Folded Reload
37; SPILL-O0-NEXT:    vsetvli zero, a0, e64, m1, ta, mu
38; SPILL-O0-NEXT:    vfadd.vv v8, v8, v25
39; SPILL-O0-NEXT:    csrr a0, vlenb
40; SPILL-O0-NEXT:    slli a0, a0, 1
41; SPILL-O0-NEXT:    add sp, sp, a0
42; SPILL-O0-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
43; SPILL-O0-NEXT:    addi sp, sp, 32
44; SPILL-O0-NEXT:    ret
45;
46; SPILL-O2-LABEL: foo:
47; SPILL-O2:       # %bb.0:
48; SPILL-O2-NEXT:    addi sp, sp, -32
49; SPILL-O2-NEXT:    sd ra, 24(sp) # 8-byte Folded Spill
50; SPILL-O2-NEXT:    sd s0, 16(sp) # 8-byte Folded Spill
51; SPILL-O2-NEXT:    csrr a1, vlenb
52; SPILL-O2-NEXT:    slli a1, a1, 1
53; SPILL-O2-NEXT:    sub sp, sp, a1
54; SPILL-O2-NEXT:    mv s0, a0
55; SPILL-O2-NEXT:    addi a1, sp, 16
56; SPILL-O2-NEXT:    vs1r.v v8, (a1) # Unknown-size Folded Spill
57; SPILL-O2-NEXT:    vsetvli zero, a0, e64, m1, ta, mu
58; SPILL-O2-NEXT:    vfadd.vv v25, v8, v9
59; SPILL-O2-NEXT:    csrr a0, vlenb
60; SPILL-O2-NEXT:    add a0, sp, a0
61; SPILL-O2-NEXT:    addi a0, a0, 16
62; SPILL-O2-NEXT:    vs1r.v v25, (a0) # Unknown-size Folded Spill
63; SPILL-O2-NEXT:    lui a0, %hi(.L.str)
64; SPILL-O2-NEXT:    addi a0, a0, %lo(.L.str)
65; SPILL-O2-NEXT:    call puts@plt
66; SPILL-O2-NEXT:    vsetvli zero, s0, e64, m1, ta, mu
67; SPILL-O2-NEXT:    csrr a0, vlenb
68; SPILL-O2-NEXT:    add a0, sp, a0
69; SPILL-O2-NEXT:    addi a0, a0, 16
70; SPILL-O2-NEXT:    vl1r.v v25, (a0) # Unknown-size Folded Reload
71; SPILL-O2-NEXT:    addi a0, sp, 16
72; SPILL-O2-NEXT:    vl1r.v v26, (a0) # Unknown-size Folded Reload
73; SPILL-O2-NEXT:    vfadd.vv v8, v26, v25
74; SPILL-O2-NEXT:    csrr a0, vlenb
75; SPILL-O2-NEXT:    slli a0, a0, 1
76; SPILL-O2-NEXT:    add sp, sp, a0
77; SPILL-O2-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
78; SPILL-O2-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
79; SPILL-O2-NEXT:    addi sp, sp, 32
80; SPILL-O2-NEXT:    ret
81{
82   %x = call <vscale x 1 x double> @llvm.riscv.vfadd.nxv1f64.nxv1f64(<vscale x 1 x double> %a, <vscale x 1 x double> %b, i64 %gvl)
83   %call = call signext i32 @puts(i8* getelementptr inbounds ([6 x i8], [6 x i8]* @.str, i64 0, i64 0))
84   %z = call <vscale x 1 x double> @llvm.riscv.vfadd.nxv1f64.nxv1f64(<vscale x 1 x double> %a, <vscale x 1 x double> %x, i64 %gvl)
85   ret <vscale x 1 x double> %z
86}
87
88declare <vscale x 1 x double> @llvm.riscv.vfadd.nxv1f64.nxv1f64(<vscale x 1 x double> %a, <vscale x 1 x double> %b, i64 %gvl)
89declare i32 @puts(i8*);
90