1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \
3; RUN:   < %s | FileCheck %s
4declare <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1f16.nxv1f16(
5  <vscale x 1 x half>,
6  <vscale x 1 x half>,
7  i32);
8
9define <vscale x 1 x float> @intrinsic_vfwsub_vv_nxv1f32_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i32 %2) nounwind {
10; CHECK-LABEL: intrinsic_vfwsub_vv_nxv1f32_nxv1f16_nxv1f16:
11; CHECK:       # %bb.0: # %entry
12; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, mu
13; CHECK-NEXT:    vfwsub.vv v25, v8, v9
14; CHECK-NEXT:    vmv1r.v v8, v25
15; CHECK-NEXT:    ret
16entry:
17  %a = call <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1f16.nxv1f16(
18    <vscale x 1 x half> %0,
19    <vscale x 1 x half> %1,
20    i32 %2)
21
22  ret <vscale x 1 x float> %a
23}
24
25declare <vscale x 1 x float> @llvm.riscv.vfwsub.mask.nxv1f32.nxv1f16.nxv1f16(
26  <vscale x 1 x float>,
27  <vscale x 1 x half>,
28  <vscale x 1 x half>,
29  <vscale x 1 x i1>,
30  i32);
31
32define <vscale x 1 x float> @intrinsic_vfwsub_mask_vv_nxv1f32_nxv1f16_nxv1f16(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
33; CHECK-LABEL: intrinsic_vfwsub_mask_vv_nxv1f32_nxv1f16_nxv1f16:
34; CHECK:       # %bb.0: # %entry
35; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, tu, mu
36; CHECK-NEXT:    vfwsub.vv v8, v9, v10, v0.t
37; CHECK-NEXT:    ret
38entry:
39  %a = call <vscale x 1 x float> @llvm.riscv.vfwsub.mask.nxv1f32.nxv1f16.nxv1f16(
40    <vscale x 1 x float> %0,
41    <vscale x 1 x half> %1,
42    <vscale x 1 x half> %2,
43    <vscale x 1 x i1> %3,
44    i32 %4)
45
46  ret <vscale x 1 x float> %a
47}
48
49declare <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2f16.nxv2f16(
50  <vscale x 2 x half>,
51  <vscale x 2 x half>,
52  i32);
53
54define <vscale x 2 x float> @intrinsic_vfwsub_vv_nxv2f32_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i32 %2) nounwind {
55; CHECK-LABEL: intrinsic_vfwsub_vv_nxv2f32_nxv2f16_nxv2f16:
56; CHECK:       # %bb.0: # %entry
57; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, mu
58; CHECK-NEXT:    vfwsub.vv v25, v8, v9
59; CHECK-NEXT:    vmv1r.v v8, v25
60; CHECK-NEXT:    ret
61entry:
62  %a = call <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2f16.nxv2f16(
63    <vscale x 2 x half> %0,
64    <vscale x 2 x half> %1,
65    i32 %2)
66
67  ret <vscale x 2 x float> %a
68}
69
70declare <vscale x 2 x float> @llvm.riscv.vfwsub.mask.nxv2f32.nxv2f16.nxv2f16(
71  <vscale x 2 x float>,
72  <vscale x 2 x half>,
73  <vscale x 2 x half>,
74  <vscale x 2 x i1>,
75  i32);
76
77define <vscale x 2 x float> @intrinsic_vfwsub_mask_vv_nxv2f32_nxv2f16_nxv2f16(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
78; CHECK-LABEL: intrinsic_vfwsub_mask_vv_nxv2f32_nxv2f16_nxv2f16:
79; CHECK:       # %bb.0: # %entry
80; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, tu, mu
81; CHECK-NEXT:    vfwsub.vv v8, v9, v10, v0.t
82; CHECK-NEXT:    ret
83entry:
84  %a = call <vscale x 2 x float> @llvm.riscv.vfwsub.mask.nxv2f32.nxv2f16.nxv2f16(
85    <vscale x 2 x float> %0,
86    <vscale x 2 x half> %1,
87    <vscale x 2 x half> %2,
88    <vscale x 2 x i1> %3,
89    i32 %4)
90
91  ret <vscale x 2 x float> %a
92}
93
94declare <vscale x 4 x float> @llvm.riscv.vfwsub.nxv4f32.nxv4f16.nxv4f16(
95  <vscale x 4 x half>,
96  <vscale x 4 x half>,
97  i32);
98
99define <vscale x 4 x float> @intrinsic_vfwsub_vv_nxv4f32_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i32 %2) nounwind {
100; CHECK-LABEL: intrinsic_vfwsub_vv_nxv4f32_nxv4f16_nxv4f16:
101; CHECK:       # %bb.0: # %entry
102; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, mu
103; CHECK-NEXT:    vfwsub.vv v26, v8, v9
104; CHECK-NEXT:    vmv2r.v v8, v26
105; CHECK-NEXT:    ret
106entry:
107  %a = call <vscale x 4 x float> @llvm.riscv.vfwsub.nxv4f32.nxv4f16.nxv4f16(
108    <vscale x 4 x half> %0,
109    <vscale x 4 x half> %1,
110    i32 %2)
111
112  ret <vscale x 4 x float> %a
113}
114
115declare <vscale x 4 x float> @llvm.riscv.vfwsub.mask.nxv4f32.nxv4f16.nxv4f16(
116  <vscale x 4 x float>,
117  <vscale x 4 x half>,
118  <vscale x 4 x half>,
119  <vscale x 4 x i1>,
120  i32);
121
122define <vscale x 4 x float> @intrinsic_vfwsub_mask_vv_nxv4f32_nxv4f16_nxv4f16(<vscale x 4 x float> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
123; CHECK-LABEL: intrinsic_vfwsub_mask_vv_nxv4f32_nxv4f16_nxv4f16:
124; CHECK:       # %bb.0: # %entry
125; CHECK-NEXT:    vsetvli zero, a0, e16, m1, tu, mu
126; CHECK-NEXT:    vfwsub.vv v8, v10, v11, v0.t
127; CHECK-NEXT:    ret
128entry:
129  %a = call <vscale x 4 x float> @llvm.riscv.vfwsub.mask.nxv4f32.nxv4f16.nxv4f16(
130    <vscale x 4 x float> %0,
131    <vscale x 4 x half> %1,
132    <vscale x 4 x half> %2,
133    <vscale x 4 x i1> %3,
134    i32 %4)
135
136  ret <vscale x 4 x float> %a
137}
138
139declare <vscale x 8 x float> @llvm.riscv.vfwsub.nxv8f32.nxv8f16.nxv8f16(
140  <vscale x 8 x half>,
141  <vscale x 8 x half>,
142  i32);
143
144define <vscale x 8 x float> @intrinsic_vfwsub_vv_nxv8f32_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i32 %2) nounwind {
145; CHECK-LABEL: intrinsic_vfwsub_vv_nxv8f32_nxv8f16_nxv8f16:
146; CHECK:       # %bb.0: # %entry
147; CHECK-NEXT:    vsetvli zero, a0, e16, m2, ta, mu
148; CHECK-NEXT:    vfwsub.vv v28, v8, v10
149; CHECK-NEXT:    vmv4r.v v8, v28
150; CHECK-NEXT:    ret
151entry:
152  %a = call <vscale x 8 x float> @llvm.riscv.vfwsub.nxv8f32.nxv8f16.nxv8f16(
153    <vscale x 8 x half> %0,
154    <vscale x 8 x half> %1,
155    i32 %2)
156
157  ret <vscale x 8 x float> %a
158}
159
160declare <vscale x 8 x float> @llvm.riscv.vfwsub.mask.nxv8f32.nxv8f16.nxv8f16(
161  <vscale x 8 x float>,
162  <vscale x 8 x half>,
163  <vscale x 8 x half>,
164  <vscale x 8 x i1>,
165  i32);
166
167define <vscale x 8 x float> @intrinsic_vfwsub_mask_vv_nxv8f32_nxv8f16_nxv8f16(<vscale x 8 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
168; CHECK-LABEL: intrinsic_vfwsub_mask_vv_nxv8f32_nxv8f16_nxv8f16:
169; CHECK:       # %bb.0: # %entry
170; CHECK-NEXT:    vsetvli zero, a0, e16, m2, tu, mu
171; CHECK-NEXT:    vfwsub.vv v8, v12, v14, v0.t
172; CHECK-NEXT:    ret
173entry:
174  %a = call <vscale x 8 x float> @llvm.riscv.vfwsub.mask.nxv8f32.nxv8f16.nxv8f16(
175    <vscale x 8 x float> %0,
176    <vscale x 8 x half> %1,
177    <vscale x 8 x half> %2,
178    <vscale x 8 x i1> %3,
179    i32 %4)
180
181  ret <vscale x 8 x float> %a
182}
183
184declare <vscale x 16 x float> @llvm.riscv.vfwsub.nxv16f32.nxv16f16.nxv16f16(
185  <vscale x 16 x half>,
186  <vscale x 16 x half>,
187  i32);
188
189define <vscale x 16 x float> @intrinsic_vfwsub_vv_nxv16f32_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i32 %2) nounwind {
190; CHECK-LABEL: intrinsic_vfwsub_vv_nxv16f32_nxv16f16_nxv16f16:
191; CHECK:       # %bb.0: # %entry
192; CHECK-NEXT:    vsetvli zero, a0, e16, m4, ta, mu
193; CHECK-NEXT:    vfwsub.vv v16, v8, v12
194; CHECK-NEXT:    vmv8r.v v8, v16
195; CHECK-NEXT:    ret
196entry:
197  %a = call <vscale x 16 x float> @llvm.riscv.vfwsub.nxv16f32.nxv16f16.nxv16f16(
198    <vscale x 16 x half> %0,
199    <vscale x 16 x half> %1,
200    i32 %2)
201
202  ret <vscale x 16 x float> %a
203}
204
205declare <vscale x 16 x float> @llvm.riscv.vfwsub.mask.nxv16f32.nxv16f16.nxv16f16(
206  <vscale x 16 x float>,
207  <vscale x 16 x half>,
208  <vscale x 16 x half>,
209  <vscale x 16 x i1>,
210  i32);
211
212define <vscale x 16 x float> @intrinsic_vfwsub_mask_vv_nxv16f32_nxv16f16_nxv16f16(<vscale x 16 x float> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
213; CHECK-LABEL: intrinsic_vfwsub_mask_vv_nxv16f32_nxv16f16_nxv16f16:
214; CHECK:       # %bb.0: # %entry
215; CHECK-NEXT:    vsetvli zero, a0, e16, m4, tu, mu
216; CHECK-NEXT:    vfwsub.vv v8, v16, v20, v0.t
217; CHECK-NEXT:    ret
218entry:
219  %a = call <vscale x 16 x float> @llvm.riscv.vfwsub.mask.nxv16f32.nxv16f16.nxv16f16(
220    <vscale x 16 x float> %0,
221    <vscale x 16 x half> %1,
222    <vscale x 16 x half> %2,
223    <vscale x 16 x i1> %3,
224    i32 %4)
225
226  ret <vscale x 16 x float> %a
227}
228
229declare <vscale x 1 x double> @llvm.riscv.vfwsub.nxv1f64.nxv1f32.nxv1f32(
230  <vscale x 1 x float>,
231  <vscale x 1 x float>,
232  i32);
233
234define <vscale x 1 x double> @intrinsic_vfwsub_vv_nxv1f64_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, i32 %2) nounwind {
235; CHECK-LABEL: intrinsic_vfwsub_vv_nxv1f64_nxv1f32_nxv1f32:
236; CHECK:       # %bb.0: # %entry
237; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, ta, mu
238; CHECK-NEXT:    vfwsub.vv v25, v8, v9
239; CHECK-NEXT:    vmv1r.v v8, v25
240; CHECK-NEXT:    ret
241entry:
242  %a = call <vscale x 1 x double> @llvm.riscv.vfwsub.nxv1f64.nxv1f32.nxv1f32(
243    <vscale x 1 x float> %0,
244    <vscale x 1 x float> %1,
245    i32 %2)
246
247  ret <vscale x 1 x double> %a
248}
249
250declare <vscale x 1 x double> @llvm.riscv.vfwsub.mask.nxv1f64.nxv1f32.nxv1f32(
251  <vscale x 1 x double>,
252  <vscale x 1 x float>,
253  <vscale x 1 x float>,
254  <vscale x 1 x i1>,
255  i32);
256
257define <vscale x 1 x double> @intrinsic_vfwsub_mask_vv_nxv1f64_nxv1f32_nxv1f32(<vscale x 1 x double> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
258; CHECK-LABEL: intrinsic_vfwsub_mask_vv_nxv1f64_nxv1f32_nxv1f32:
259; CHECK:       # %bb.0: # %entry
260; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, tu, mu
261; CHECK-NEXT:    vfwsub.vv v8, v9, v10, v0.t
262; CHECK-NEXT:    ret
263entry:
264  %a = call <vscale x 1 x double> @llvm.riscv.vfwsub.mask.nxv1f64.nxv1f32.nxv1f32(
265    <vscale x 1 x double> %0,
266    <vscale x 1 x float> %1,
267    <vscale x 1 x float> %2,
268    <vscale x 1 x i1> %3,
269    i32 %4)
270
271  ret <vscale x 1 x double> %a
272}
273
274declare <vscale x 2 x double> @llvm.riscv.vfwsub.nxv2f64.nxv2f32.nxv2f32(
275  <vscale x 2 x float>,
276  <vscale x 2 x float>,
277  i32);
278
279define <vscale x 2 x double> @intrinsic_vfwsub_vv_nxv2f64_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, i32 %2) nounwind {
280; CHECK-LABEL: intrinsic_vfwsub_vv_nxv2f64_nxv2f32_nxv2f32:
281; CHECK:       # %bb.0: # %entry
282; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, mu
283; CHECK-NEXT:    vfwsub.vv v26, v8, v9
284; CHECK-NEXT:    vmv2r.v v8, v26
285; CHECK-NEXT:    ret
286entry:
287  %a = call <vscale x 2 x double> @llvm.riscv.vfwsub.nxv2f64.nxv2f32.nxv2f32(
288    <vscale x 2 x float> %0,
289    <vscale x 2 x float> %1,
290    i32 %2)
291
292  ret <vscale x 2 x double> %a
293}
294
295declare <vscale x 2 x double> @llvm.riscv.vfwsub.mask.nxv2f64.nxv2f32.nxv2f32(
296  <vscale x 2 x double>,
297  <vscale x 2 x float>,
298  <vscale x 2 x float>,
299  <vscale x 2 x i1>,
300  i32);
301
302define <vscale x 2 x double> @intrinsic_vfwsub_mask_vv_nxv2f64_nxv2f32_nxv2f32(<vscale x 2 x double> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
303; CHECK-LABEL: intrinsic_vfwsub_mask_vv_nxv2f64_nxv2f32_nxv2f32:
304; CHECK:       # %bb.0: # %entry
305; CHECK-NEXT:    vsetvli zero, a0, e32, m1, tu, mu
306; CHECK-NEXT:    vfwsub.vv v8, v10, v11, v0.t
307; CHECK-NEXT:    ret
308entry:
309  %a = call <vscale x 2 x double> @llvm.riscv.vfwsub.mask.nxv2f64.nxv2f32.nxv2f32(
310    <vscale x 2 x double> %0,
311    <vscale x 2 x float> %1,
312    <vscale x 2 x float> %2,
313    <vscale x 2 x i1> %3,
314    i32 %4)
315
316  ret <vscale x 2 x double> %a
317}
318
319declare <vscale x 4 x double> @llvm.riscv.vfwsub.nxv4f64.nxv4f32.nxv4f32(
320  <vscale x 4 x float>,
321  <vscale x 4 x float>,
322  i32);
323
324define <vscale x 4 x double> @intrinsic_vfwsub_vv_nxv4f64_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, i32 %2) nounwind {
325; CHECK-LABEL: intrinsic_vfwsub_vv_nxv4f64_nxv4f32_nxv4f32:
326; CHECK:       # %bb.0: # %entry
327; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, mu
328; CHECK-NEXT:    vfwsub.vv v28, v8, v10
329; CHECK-NEXT:    vmv4r.v v8, v28
330; CHECK-NEXT:    ret
331entry:
332  %a = call <vscale x 4 x double> @llvm.riscv.vfwsub.nxv4f64.nxv4f32.nxv4f32(
333    <vscale x 4 x float> %0,
334    <vscale x 4 x float> %1,
335    i32 %2)
336
337  ret <vscale x 4 x double> %a
338}
339
340declare <vscale x 4 x double> @llvm.riscv.vfwsub.mask.nxv4f64.nxv4f32.nxv4f32(
341  <vscale x 4 x double>,
342  <vscale x 4 x float>,
343  <vscale x 4 x float>,
344  <vscale x 4 x i1>,
345  i32);
346
347define <vscale x 4 x double> @intrinsic_vfwsub_mask_vv_nxv4f64_nxv4f32_nxv4f32(<vscale x 4 x double> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
348; CHECK-LABEL: intrinsic_vfwsub_mask_vv_nxv4f64_nxv4f32_nxv4f32:
349; CHECK:       # %bb.0: # %entry
350; CHECK-NEXT:    vsetvli zero, a0, e32, m2, tu, mu
351; CHECK-NEXT:    vfwsub.vv v8, v12, v14, v0.t
352; CHECK-NEXT:    ret
353entry:
354  %a = call <vscale x 4 x double> @llvm.riscv.vfwsub.mask.nxv4f64.nxv4f32.nxv4f32(
355    <vscale x 4 x double> %0,
356    <vscale x 4 x float> %1,
357    <vscale x 4 x float> %2,
358    <vscale x 4 x i1> %3,
359    i32 %4)
360
361  ret <vscale x 4 x double> %a
362}
363
364declare <vscale x 8 x double> @llvm.riscv.vfwsub.nxv8f64.nxv8f32.nxv8f32(
365  <vscale x 8 x float>,
366  <vscale x 8 x float>,
367  i32);
368
369define <vscale x 8 x double> @intrinsic_vfwsub_vv_nxv8f64_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, i32 %2) nounwind {
370; CHECK-LABEL: intrinsic_vfwsub_vv_nxv8f64_nxv8f32_nxv8f32:
371; CHECK:       # %bb.0: # %entry
372; CHECK-NEXT:    vsetvli zero, a0, e32, m4, ta, mu
373; CHECK-NEXT:    vfwsub.vv v16, v8, v12
374; CHECK-NEXT:    vmv8r.v v8, v16
375; CHECK-NEXT:    ret
376entry:
377  %a = call <vscale x 8 x double> @llvm.riscv.vfwsub.nxv8f64.nxv8f32.nxv8f32(
378    <vscale x 8 x float> %0,
379    <vscale x 8 x float> %1,
380    i32 %2)
381
382  ret <vscale x 8 x double> %a
383}
384
385declare <vscale x 8 x double> @llvm.riscv.vfwsub.mask.nxv8f64.nxv8f32.nxv8f32(
386  <vscale x 8 x double>,
387  <vscale x 8 x float>,
388  <vscale x 8 x float>,
389  <vscale x 8 x i1>,
390  i32);
391
392define <vscale x 8 x double> @intrinsic_vfwsub_mask_vv_nxv8f64_nxv8f32_nxv8f32(<vscale x 8 x double> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
393; CHECK-LABEL: intrinsic_vfwsub_mask_vv_nxv8f64_nxv8f32_nxv8f32:
394; CHECK:       # %bb.0: # %entry
395; CHECK-NEXT:    vsetvli zero, a0, e32, m4, tu, mu
396; CHECK-NEXT:    vfwsub.vv v8, v16, v20, v0.t
397; CHECK-NEXT:    ret
398entry:
399  %a = call <vscale x 8 x double> @llvm.riscv.vfwsub.mask.nxv8f64.nxv8f32.nxv8f32(
400    <vscale x 8 x double> %0,
401    <vscale x 8 x float> %1,
402    <vscale x 8 x float> %2,
403    <vscale x 8 x i1> %3,
404    i32 %4)
405
406  ret <vscale x 8 x double> %a
407}
408
409declare <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1f16.f16(
410  <vscale x 1 x half>,
411  half,
412  i32);
413
414define <vscale x 1 x float> @intrinsic_vfwsub_vf_nxv1f32_nxv1f16_f16(<vscale x 1 x half> %0, half %1, i32 %2) nounwind {
415; CHECK-LABEL: intrinsic_vfwsub_vf_nxv1f32_nxv1f16_f16:
416; CHECK:       # %bb.0: # %entry
417; CHECK-NEXT:    fmv.h.x ft0, a0
418; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, mu
419; CHECK-NEXT:    vfwsub.vf v25, v8, ft0
420; CHECK-NEXT:    vmv1r.v v8, v25
421; CHECK-NEXT:    ret
422entry:
423  %a = call <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1f16.f16(
424    <vscale x 1 x half> %0,
425    half %1,
426    i32 %2)
427
428  ret <vscale x 1 x float> %a
429}
430
431declare <vscale x 1 x float> @llvm.riscv.vfwsub.mask.nxv1f32.nxv1f16.f16(
432  <vscale x 1 x float>,
433  <vscale x 1 x half>,
434  half,
435  <vscale x 1 x i1>,
436  i32);
437
438define <vscale x 1 x float> @intrinsic_vfwsub_mask_vf_nxv1f32_nxv1f16_f16(<vscale x 1 x float> %0, <vscale x 1 x half> %1, half %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
439; CHECK-LABEL: intrinsic_vfwsub_mask_vf_nxv1f32_nxv1f16_f16:
440; CHECK:       # %bb.0: # %entry
441; CHECK-NEXT:    fmv.h.x ft0, a0
442; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, tu, mu
443; CHECK-NEXT:    vfwsub.vf v8, v9, ft0, v0.t
444; CHECK-NEXT:    ret
445entry:
446  %a = call <vscale x 1 x float> @llvm.riscv.vfwsub.mask.nxv1f32.nxv1f16.f16(
447    <vscale x 1 x float> %0,
448    <vscale x 1 x half> %1,
449    half %2,
450    <vscale x 1 x i1> %3,
451    i32 %4)
452
453  ret <vscale x 1 x float> %a
454}
455
456declare <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2f16.f16(
457  <vscale x 2 x half>,
458  half,
459  i32);
460
461define <vscale x 2 x float> @intrinsic_vfwsub_vf_nxv2f32_nxv2f16_f16(<vscale x 2 x half> %0, half %1, i32 %2) nounwind {
462; CHECK-LABEL: intrinsic_vfwsub_vf_nxv2f32_nxv2f16_f16:
463; CHECK:       # %bb.0: # %entry
464; CHECK-NEXT:    fmv.h.x ft0, a0
465; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, mu
466; CHECK-NEXT:    vfwsub.vf v25, v8, ft0
467; CHECK-NEXT:    vmv1r.v v8, v25
468; CHECK-NEXT:    ret
469entry:
470  %a = call <vscale x 2 x float> @llvm.riscv.vfwsub.nxv2f32.nxv2f16.f16(
471    <vscale x 2 x half> %0,
472    half %1,
473    i32 %2)
474
475  ret <vscale x 2 x float> %a
476}
477
478declare <vscale x 2 x float> @llvm.riscv.vfwsub.mask.nxv2f32.nxv2f16.f16(
479  <vscale x 2 x float>,
480  <vscale x 2 x half>,
481  half,
482  <vscale x 2 x i1>,
483  i32);
484
485define <vscale x 2 x float> @intrinsic_vfwsub_mask_vf_nxv2f32_nxv2f16_f16(<vscale x 2 x float> %0, <vscale x 2 x half> %1, half %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
486; CHECK-LABEL: intrinsic_vfwsub_mask_vf_nxv2f32_nxv2f16_f16:
487; CHECK:       # %bb.0: # %entry
488; CHECK-NEXT:    fmv.h.x ft0, a0
489; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, tu, mu
490; CHECK-NEXT:    vfwsub.vf v8, v9, ft0, v0.t
491; CHECK-NEXT:    ret
492entry:
493  %a = call <vscale x 2 x float> @llvm.riscv.vfwsub.mask.nxv2f32.nxv2f16.f16(
494    <vscale x 2 x float> %0,
495    <vscale x 2 x half> %1,
496    half %2,
497    <vscale x 2 x i1> %3,
498    i32 %4)
499
500  ret <vscale x 2 x float> %a
501}
502
503declare <vscale x 4 x float> @llvm.riscv.vfwsub.nxv4f32.nxv4f16.f16(
504  <vscale x 4 x half>,
505  half,
506  i32);
507
508define <vscale x 4 x float> @intrinsic_vfwsub_vf_nxv4f32_nxv4f16_f16(<vscale x 4 x half> %0, half %1, i32 %2) nounwind {
509; CHECK-LABEL: intrinsic_vfwsub_vf_nxv4f32_nxv4f16_f16:
510; CHECK:       # %bb.0: # %entry
511; CHECK-NEXT:    fmv.h.x ft0, a0
512; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, mu
513; CHECK-NEXT:    vfwsub.vf v26, v8, ft0
514; CHECK-NEXT:    vmv2r.v v8, v26
515; CHECK-NEXT:    ret
516entry:
517  %a = call <vscale x 4 x float> @llvm.riscv.vfwsub.nxv4f32.nxv4f16.f16(
518    <vscale x 4 x half> %0,
519    half %1,
520    i32 %2)
521
522  ret <vscale x 4 x float> %a
523}
524
525declare <vscale x 4 x float> @llvm.riscv.vfwsub.mask.nxv4f32.nxv4f16.f16(
526  <vscale x 4 x float>,
527  <vscale x 4 x half>,
528  half,
529  <vscale x 4 x i1>,
530  i32);
531
532define <vscale x 4 x float> @intrinsic_vfwsub_mask_vf_nxv4f32_nxv4f16_f16(<vscale x 4 x float> %0, <vscale x 4 x half> %1, half %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
533; CHECK-LABEL: intrinsic_vfwsub_mask_vf_nxv4f32_nxv4f16_f16:
534; CHECK:       # %bb.0: # %entry
535; CHECK-NEXT:    fmv.h.x ft0, a0
536; CHECK-NEXT:    vsetvli zero, a1, e16, m1, tu, mu
537; CHECK-NEXT:    vfwsub.vf v8, v10, ft0, v0.t
538; CHECK-NEXT:    ret
539entry:
540  %a = call <vscale x 4 x float> @llvm.riscv.vfwsub.mask.nxv4f32.nxv4f16.f16(
541    <vscale x 4 x float> %0,
542    <vscale x 4 x half> %1,
543    half %2,
544    <vscale x 4 x i1> %3,
545    i32 %4)
546
547  ret <vscale x 4 x float> %a
548}
549
550declare <vscale x 8 x float> @llvm.riscv.vfwsub.nxv8f32.nxv8f16.f16(
551  <vscale x 8 x half>,
552  half,
553  i32);
554
555define <vscale x 8 x float> @intrinsic_vfwsub_vf_nxv8f32_nxv8f16_f16(<vscale x 8 x half> %0, half %1, i32 %2) nounwind {
556; CHECK-LABEL: intrinsic_vfwsub_vf_nxv8f32_nxv8f16_f16:
557; CHECK:       # %bb.0: # %entry
558; CHECK-NEXT:    fmv.h.x ft0, a0
559; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, mu
560; CHECK-NEXT:    vfwsub.vf v28, v8, ft0
561; CHECK-NEXT:    vmv4r.v v8, v28
562; CHECK-NEXT:    ret
563entry:
564  %a = call <vscale x 8 x float> @llvm.riscv.vfwsub.nxv8f32.nxv8f16.f16(
565    <vscale x 8 x half> %0,
566    half %1,
567    i32 %2)
568
569  ret <vscale x 8 x float> %a
570}
571
572declare <vscale x 8 x float> @llvm.riscv.vfwsub.mask.nxv8f32.nxv8f16.f16(
573  <vscale x 8 x float>,
574  <vscale x 8 x half>,
575  half,
576  <vscale x 8 x i1>,
577  i32);
578
579define <vscale x 8 x float> @intrinsic_vfwsub_mask_vf_nxv8f32_nxv8f16_f16(<vscale x 8 x float> %0, <vscale x 8 x half> %1, half %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
580; CHECK-LABEL: intrinsic_vfwsub_mask_vf_nxv8f32_nxv8f16_f16:
581; CHECK:       # %bb.0: # %entry
582; CHECK-NEXT:    fmv.h.x ft0, a0
583; CHECK-NEXT:    vsetvli zero, a1, e16, m2, tu, mu
584; CHECK-NEXT:    vfwsub.vf v8, v12, ft0, v0.t
585; CHECK-NEXT:    ret
586entry:
587  %a = call <vscale x 8 x float> @llvm.riscv.vfwsub.mask.nxv8f32.nxv8f16.f16(
588    <vscale x 8 x float> %0,
589    <vscale x 8 x half> %1,
590    half %2,
591    <vscale x 8 x i1> %3,
592    i32 %4)
593
594  ret <vscale x 8 x float> %a
595}
596
597declare <vscale x 16 x float> @llvm.riscv.vfwsub.nxv16f32.nxv16f16.f16(
598  <vscale x 16 x half>,
599  half,
600  i32);
601
602define <vscale x 16 x float> @intrinsic_vfwsub_vf_nxv16f32_nxv16f16_f16(<vscale x 16 x half> %0, half %1, i32 %2) nounwind {
603; CHECK-LABEL: intrinsic_vfwsub_vf_nxv16f32_nxv16f16_f16:
604; CHECK:       # %bb.0: # %entry
605; CHECK-NEXT:    fmv.h.x ft0, a0
606; CHECK-NEXT:    vsetvli zero, a1, e16, m4, ta, mu
607; CHECK-NEXT:    vfwsub.vf v16, v8, ft0
608; CHECK-NEXT:    vmv8r.v v8, v16
609; CHECK-NEXT:    ret
610entry:
611  %a = call <vscale x 16 x float> @llvm.riscv.vfwsub.nxv16f32.nxv16f16.f16(
612    <vscale x 16 x half> %0,
613    half %1,
614    i32 %2)
615
616  ret <vscale x 16 x float> %a
617}
618
619declare <vscale x 16 x float> @llvm.riscv.vfwsub.mask.nxv16f32.nxv16f16.f16(
620  <vscale x 16 x float>,
621  <vscale x 16 x half>,
622  half,
623  <vscale x 16 x i1>,
624  i32);
625
626define <vscale x 16 x float> @intrinsic_vfwsub_mask_vf_nxv16f32_nxv16f16_f16(<vscale x 16 x float> %0, <vscale x 16 x half> %1, half %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
627; CHECK-LABEL: intrinsic_vfwsub_mask_vf_nxv16f32_nxv16f16_f16:
628; CHECK:       # %bb.0: # %entry
629; CHECK-NEXT:    fmv.h.x ft0, a0
630; CHECK-NEXT:    vsetvli zero, a1, e16, m4, tu, mu
631; CHECK-NEXT:    vfwsub.vf v8, v16, ft0, v0.t
632; CHECK-NEXT:    ret
633entry:
634  %a = call <vscale x 16 x float> @llvm.riscv.vfwsub.mask.nxv16f32.nxv16f16.f16(
635    <vscale x 16 x float> %0,
636    <vscale x 16 x half> %1,
637    half %2,
638    <vscale x 16 x i1> %3,
639    i32 %4)
640
641  ret <vscale x 16 x float> %a
642}
643
644declare <vscale x 1 x double> @llvm.riscv.vfwsub.nxv1f64.nxv1f32.f32(
645  <vscale x 1 x float>,
646  float,
647  i32);
648
649define <vscale x 1 x double> @intrinsic_vfwsub_vf_nxv1f64_nxv1f32_f32(<vscale x 1 x float> %0, float %1, i32 %2) nounwind {
650; CHECK-LABEL: intrinsic_vfwsub_vf_nxv1f64_nxv1f32_f32:
651; CHECK:       # %bb.0: # %entry
652; CHECK-NEXT:    fmv.w.x ft0, a0
653; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, mu
654; CHECK-NEXT:    vfwsub.vf v25, v8, ft0
655; CHECK-NEXT:    vmv1r.v v8, v25
656; CHECK-NEXT:    ret
657entry:
658  %a = call <vscale x 1 x double> @llvm.riscv.vfwsub.nxv1f64.nxv1f32.f32(
659    <vscale x 1 x float> %0,
660    float %1,
661    i32 %2)
662
663  ret <vscale x 1 x double> %a
664}
665
666declare <vscale x 1 x double> @llvm.riscv.vfwsub.mask.nxv1f64.nxv1f32.f32(
667  <vscale x 1 x double>,
668  <vscale x 1 x float>,
669  float,
670  <vscale x 1 x i1>,
671  i32);
672
673define <vscale x 1 x double> @intrinsic_vfwsub_mask_vf_nxv1f64_nxv1f32_f32(<vscale x 1 x double> %0, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
674; CHECK-LABEL: intrinsic_vfwsub_mask_vf_nxv1f64_nxv1f32_f32:
675; CHECK:       # %bb.0: # %entry
676; CHECK-NEXT:    fmv.w.x ft0, a0
677; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, tu, mu
678; CHECK-NEXT:    vfwsub.vf v8, v9, ft0, v0.t
679; CHECK-NEXT:    ret
680entry:
681  %a = call <vscale x 1 x double> @llvm.riscv.vfwsub.mask.nxv1f64.nxv1f32.f32(
682    <vscale x 1 x double> %0,
683    <vscale x 1 x float> %1,
684    float %2,
685    <vscale x 1 x i1> %3,
686    i32 %4)
687
688  ret <vscale x 1 x double> %a
689}
690
691declare <vscale x 2 x double> @llvm.riscv.vfwsub.nxv2f64.nxv2f32.f32(
692  <vscale x 2 x float>,
693  float,
694  i32);
695
696define <vscale x 2 x double> @intrinsic_vfwsub_vf_nxv2f64_nxv2f32_f32(<vscale x 2 x float> %0, float %1, i32 %2) nounwind {
697; CHECK-LABEL: intrinsic_vfwsub_vf_nxv2f64_nxv2f32_f32:
698; CHECK:       # %bb.0: # %entry
699; CHECK-NEXT:    fmv.w.x ft0, a0
700; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, mu
701; CHECK-NEXT:    vfwsub.vf v26, v8, ft0
702; CHECK-NEXT:    vmv2r.v v8, v26
703; CHECK-NEXT:    ret
704entry:
705  %a = call <vscale x 2 x double> @llvm.riscv.vfwsub.nxv2f64.nxv2f32.f32(
706    <vscale x 2 x float> %0,
707    float %1,
708    i32 %2)
709
710  ret <vscale x 2 x double> %a
711}
712
713declare <vscale x 2 x double> @llvm.riscv.vfwsub.mask.nxv2f64.nxv2f32.f32(
714  <vscale x 2 x double>,
715  <vscale x 2 x float>,
716  float,
717  <vscale x 2 x i1>,
718  i32);
719
720define <vscale x 2 x double> @intrinsic_vfwsub_mask_vf_nxv2f64_nxv2f32_f32(<vscale x 2 x double> %0, <vscale x 2 x float> %1, float %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
721; CHECK-LABEL: intrinsic_vfwsub_mask_vf_nxv2f64_nxv2f32_f32:
722; CHECK:       # %bb.0: # %entry
723; CHECK-NEXT:    fmv.w.x ft0, a0
724; CHECK-NEXT:    vsetvli zero, a1, e32, m1, tu, mu
725; CHECK-NEXT:    vfwsub.vf v8, v10, ft0, v0.t
726; CHECK-NEXT:    ret
727entry:
728  %a = call <vscale x 2 x double> @llvm.riscv.vfwsub.mask.nxv2f64.nxv2f32.f32(
729    <vscale x 2 x double> %0,
730    <vscale x 2 x float> %1,
731    float %2,
732    <vscale x 2 x i1> %3,
733    i32 %4)
734
735  ret <vscale x 2 x double> %a
736}
737
738declare <vscale x 4 x double> @llvm.riscv.vfwsub.nxv4f64.nxv4f32.f32(
739  <vscale x 4 x float>,
740  float,
741  i32);
742
743define <vscale x 4 x double> @intrinsic_vfwsub_vf_nxv4f64_nxv4f32_f32(<vscale x 4 x float> %0, float %1, i32 %2) nounwind {
744; CHECK-LABEL: intrinsic_vfwsub_vf_nxv4f64_nxv4f32_f32:
745; CHECK:       # %bb.0: # %entry
746; CHECK-NEXT:    fmv.w.x ft0, a0
747; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, mu
748; CHECK-NEXT:    vfwsub.vf v28, v8, ft0
749; CHECK-NEXT:    vmv4r.v v8, v28
750; CHECK-NEXT:    ret
751entry:
752  %a = call <vscale x 4 x double> @llvm.riscv.vfwsub.nxv4f64.nxv4f32.f32(
753    <vscale x 4 x float> %0,
754    float %1,
755    i32 %2)
756
757  ret <vscale x 4 x double> %a
758}
759
760declare <vscale x 4 x double> @llvm.riscv.vfwsub.mask.nxv4f64.nxv4f32.f32(
761  <vscale x 4 x double>,
762  <vscale x 4 x float>,
763  float,
764  <vscale x 4 x i1>,
765  i32);
766
767define <vscale x 4 x double> @intrinsic_vfwsub_mask_vf_nxv4f64_nxv4f32_f32(<vscale x 4 x double> %0, <vscale x 4 x float> %1, float %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
768; CHECK-LABEL: intrinsic_vfwsub_mask_vf_nxv4f64_nxv4f32_f32:
769; CHECK:       # %bb.0: # %entry
770; CHECK-NEXT:    fmv.w.x ft0, a0
771; CHECK-NEXT:    vsetvli zero, a1, e32, m2, tu, mu
772; CHECK-NEXT:    vfwsub.vf v8, v12, ft0, v0.t
773; CHECK-NEXT:    ret
774entry:
775  %a = call <vscale x 4 x double> @llvm.riscv.vfwsub.mask.nxv4f64.nxv4f32.f32(
776    <vscale x 4 x double> %0,
777    <vscale x 4 x float> %1,
778    float %2,
779    <vscale x 4 x i1> %3,
780    i32 %4)
781
782  ret <vscale x 4 x double> %a
783}
784
785declare <vscale x 8 x double> @llvm.riscv.vfwsub.nxv8f64.nxv8f32.f32(
786  <vscale x 8 x float>,
787  float,
788  i32);
789
790define <vscale x 8 x double> @intrinsic_vfwsub_vf_nxv8f64_nxv8f32_f32(<vscale x 8 x float> %0, float %1, i32 %2) nounwind {
791; CHECK-LABEL: intrinsic_vfwsub_vf_nxv8f64_nxv8f32_f32:
792; CHECK:       # %bb.0: # %entry
793; CHECK-NEXT:    fmv.w.x ft0, a0
794; CHECK-NEXT:    vsetvli zero, a1, e32, m4, ta, mu
795; CHECK-NEXT:    vfwsub.vf v16, v8, ft0
796; CHECK-NEXT:    vmv8r.v v8, v16
797; CHECK-NEXT:    ret
798entry:
799  %a = call <vscale x 8 x double> @llvm.riscv.vfwsub.nxv8f64.nxv8f32.f32(
800    <vscale x 8 x float> %0,
801    float %1,
802    i32 %2)
803
804  ret <vscale x 8 x double> %a
805}
806
807declare <vscale x 8 x double> @llvm.riscv.vfwsub.mask.nxv8f64.nxv8f32.f32(
808  <vscale x 8 x double>,
809  <vscale x 8 x float>,
810  float,
811  <vscale x 8 x i1>,
812  i32);
813
814define <vscale x 8 x double> @intrinsic_vfwsub_mask_vf_nxv8f64_nxv8f32_f32(<vscale x 8 x double> %0, <vscale x 8 x float> %1, float %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
815; CHECK-LABEL: intrinsic_vfwsub_mask_vf_nxv8f64_nxv8f32_f32:
816; CHECK:       # %bb.0: # %entry
817; CHECK-NEXT:    fmv.w.x ft0, a0
818; CHECK-NEXT:    vsetvli zero, a1, e32, m4, tu, mu
819; CHECK-NEXT:    vfwsub.vf v8, v16, ft0, v0.t
820; CHECK-NEXT:    ret
821entry:
822  %a = call <vscale x 8 x double> @llvm.riscv.vfwsub.mask.nxv8f64.nxv8f32.f32(
823    <vscale x 8 x double> %0,
824    <vscale x 8 x float> %1,
825    float %2,
826    <vscale x 8 x i1> %3,
827    i32 %4)
828
829  ret <vscale x 8 x double> %a
830}
831