1
2/* Capstone Disassembly Engine, http://www.capstone-engine.org */
3/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
4
5/*===- TableGen'erated file -------------------------------------*- C++ -*-===*|*                                                                            *|
6|* Target Instruction Enum Values and Descriptors                             *|
7|*                                                                            *|
8|* Automatically generated file, do not edit!                                 *|
9|*                                                                            *|
10\*===----------------------------------------------------------------------===*/
11
12#ifdef GET_INSTRINFO_ENUM
13#undef GET_INSTRINFO_ENUM
14
15enum {
16	ARM_PHI	= 0,
17	ARM_INLINEASM	= 1,
18	ARM_CFI_INSTRUCTION	= 2,
19	ARM_EH_LABEL	= 3,
20	ARM_GC_LABEL	= 4,
21	ARM_ANNOTATION_LABEL	= 5,
22	ARM_KILL	= 6,
23	ARM_EXTRACT_SUBREG	= 7,
24	ARM_INSERT_SUBREG	= 8,
25	ARM_IMPLICIT_DEF	= 9,
26	ARM_SUBREG_TO_REG	= 10,
27	ARM_COPY_TO_REGCLASS	= 11,
28	ARM_DBG_VALUE	= 12,
29	ARM_DBG_LABEL	= 13,
30	ARM_REG_SEQUENCE	= 14,
31	ARM_COPY	= 15,
32	ARM_BUNDLE	= 16,
33	ARM_LIFETIME_START	= 17,
34	ARM_LIFETIME_END	= 18,
35	ARM_STACKMAP	= 19,
36	ARM_FENTRY_CALL	= 20,
37	ARM_PATCHPOINT	= 21,
38	ARM_LOAD_STACK_GUARD	= 22,
39	ARM_STATEPOINT	= 23,
40	ARM_LOCAL_ESCAPE	= 24,
41	ARM_FAULTING_OP	= 25,
42	ARM_PATCHABLE_OP	= 26,
43	ARM_PATCHABLE_FUNCTION_ENTER	= 27,
44	ARM_PATCHABLE_RET	= 28,
45	ARM_PATCHABLE_FUNCTION_EXIT	= 29,
46	ARM_PATCHABLE_TAIL_CALL	= 30,
47	ARM_PATCHABLE_EVENT_CALL	= 31,
48	ARM_PATCHABLE_TYPED_EVENT_CALL	= 32,
49	ARM_ICALL_BRANCH_FUNNEL	= 33,
50	ARM_G_ADD	= 34,
51	ARM_G_SUB	= 35,
52	ARM_G_MUL	= 36,
53	ARM_G_SDIV	= 37,
54	ARM_G_UDIV	= 38,
55	ARM_G_SREM	= 39,
56	ARM_G_UREM	= 40,
57	ARM_G_AND	= 41,
58	ARM_G_OR	= 42,
59	ARM_G_XOR	= 43,
60	ARM_G_IMPLICIT_DEF	= 44,
61	ARM_G_PHI	= 45,
62	ARM_G_FRAME_INDEX	= 46,
63	ARM_G_GLOBAL_VALUE	= 47,
64	ARM_G_EXTRACT	= 48,
65	ARM_G_UNMERGE_VALUES	= 49,
66	ARM_G_INSERT	= 50,
67	ARM_G_MERGE_VALUES	= 51,
68	ARM_G_PTRTOINT	= 52,
69	ARM_G_INTTOPTR	= 53,
70	ARM_G_BITCAST	= 54,
71	ARM_G_LOAD	= 55,
72	ARM_G_SEXTLOAD	= 56,
73	ARM_G_ZEXTLOAD	= 57,
74	ARM_G_STORE	= 58,
75	ARM_G_ATOMIC_CMPXCHG_WITH_SUCCESS	= 59,
76	ARM_G_ATOMIC_CMPXCHG	= 60,
77	ARM_G_ATOMICRMW_XCHG	= 61,
78	ARM_G_ATOMICRMW_ADD	= 62,
79	ARM_G_ATOMICRMW_SUB	= 63,
80	ARM_G_ATOMICRMW_AND	= 64,
81	ARM_G_ATOMICRMW_NAND	= 65,
82	ARM_G_ATOMICRMW_OR	= 66,
83	ARM_G_ATOMICRMW_XOR	= 67,
84	ARM_G_ATOMICRMW_MAX	= 68,
85	ARM_G_ATOMICRMW_MIN	= 69,
86	ARM_G_ATOMICRMW_UMAX	= 70,
87	ARM_G_ATOMICRMW_UMIN	= 71,
88	ARM_G_BRCOND	= 72,
89	ARM_G_BRINDIRECT	= 73,
90	ARM_G_INTRINSIC	= 74,
91	ARM_G_INTRINSIC_W_SIDE_EFFECTS	= 75,
92	ARM_G_ANYEXT	= 76,
93	ARM_G_TRUNC	= 77,
94	ARM_G_CONSTANT	= 78,
95	ARM_G_FCONSTANT	= 79,
96	ARM_G_VASTART	= 80,
97	ARM_G_VAARG	= 81,
98	ARM_G_SEXT	= 82,
99	ARM_G_ZEXT	= 83,
100	ARM_G_SHL	= 84,
101	ARM_G_LSHR	= 85,
102	ARM_G_ASHR	= 86,
103	ARM_G_ICMP	= 87,
104	ARM_G_FCMP	= 88,
105	ARM_G_SELECT	= 89,
106	ARM_G_UADDE	= 90,
107	ARM_G_USUBE	= 91,
108	ARM_G_SADDO	= 92,
109	ARM_G_SSUBO	= 93,
110	ARM_G_UMULO	= 94,
111	ARM_G_SMULO	= 95,
112	ARM_G_UMULH	= 96,
113	ARM_G_SMULH	= 97,
114	ARM_G_FADD	= 98,
115	ARM_G_FSUB	= 99,
116	ARM_G_FMUL	= 100,
117	ARM_G_FMA	= 101,
118	ARM_G_FDIV	= 102,
119	ARM_G_FREM	= 103,
120	ARM_G_FPOW	= 104,
121	ARM_G_FEXP	= 105,
122	ARM_G_FEXP2	= 106,
123	ARM_G_FLOG	= 107,
124	ARM_G_FLOG2	= 108,
125	ARM_G_FNEG	= 109,
126	ARM_G_FPEXT	= 110,
127	ARM_G_FPTRUNC	= 111,
128	ARM_G_FPTOSI	= 112,
129	ARM_G_FPTOUI	= 113,
130	ARM_G_SITOFP	= 114,
131	ARM_G_UITOFP	= 115,
132	ARM_G_FABS	= 116,
133	ARM_G_GEP	= 117,
134	ARM_G_PTR_MASK	= 118,
135	ARM_G_BR	= 119,
136	ARM_G_INSERT_VECTOR_ELT	= 120,
137	ARM_G_EXTRACT_VECTOR_ELT	= 121,
138	ARM_G_SHUFFLE_VECTOR	= 122,
139	ARM_G_BSWAP	= 123,
140	ARM_G_ADDRSPACE_CAST	= 124,
141	ARM_G_BLOCK_ADDR	= 125,
142	ARM_ABS	= 126,
143	ARM_ADDSri	= 127,
144	ARM_ADDSrr	= 128,
145	ARM_ADDSrsi	= 129,
146	ARM_ADDSrsr	= 130,
147	ARM_ADJCALLSTACKDOWN	= 131,
148	ARM_ADJCALLSTACKUP	= 132,
149	ARM_ASRi	= 133,
150	ARM_ASRr	= 134,
151	ARM_B	= 135,
152	ARM_BCCZi64	= 136,
153	ARM_BCCi64	= 137,
154	ARM_BMOVPCB_CALL	= 138,
155	ARM_BMOVPCRX_CALL	= 139,
156	ARM_BR_JTadd	= 140,
157	ARM_BR_JTm_i12	= 141,
158	ARM_BR_JTm_rs	= 142,
159	ARM_BR_JTr	= 143,
160	ARM_BX_CALL	= 144,
161	ARM_CMP_SWAP_16	= 145,
162	ARM_CMP_SWAP_32	= 146,
163	ARM_CMP_SWAP_64	= 147,
164	ARM_CMP_SWAP_8	= 148,
165	ARM_CONSTPOOL_ENTRY	= 149,
166	ARM_COPY_STRUCT_BYVAL_I32	= 150,
167	ARM_CompilerBarrier	= 151,
168	ARM_ITasm	= 152,
169	ARM_Int_eh_sjlj_dispatchsetup	= 153,
170	ARM_Int_eh_sjlj_setup_dispatch	= 157,
171	ARM_JUMPTABLE_ADDRS	= 158,
172	ARM_JUMPTABLE_INSTS	= 159,
173	ARM_JUMPTABLE_TBB	= 160,
174	ARM_JUMPTABLE_TBH	= 161,
175	ARM_LDMIA_RET	= 162,
176	ARM_LDRBT_POST	= 163,
177	ARM_LDRConstPool	= 164,
178	ARM_LDRLIT_ga_abs	= 165,
179	ARM_LDRLIT_ga_pcrel	= 166,
180	ARM_LDRLIT_ga_pcrel_ldr	= 167,
181	ARM_LDRT_POST	= 168,
182	ARM_LEApcrel	= 169,
183	ARM_LEApcrelJT	= 170,
184	ARM_LSLi	= 171,
185	ARM_LSLr	= 172,
186	ARM_LSRi	= 173,
187	ARM_LSRr	= 174,
188	ARM_MEMCPY	= 175,
189	ARM_MLAv5	= 176,
190	ARM_MOVCCi	= 177,
191	ARM_MOVCCi16	= 178,
192	ARM_MOVCCi32imm	= 179,
193	ARM_MOVCCr	= 180,
194	ARM_MOVCCsi	= 181,
195	ARM_MOVCCsr	= 182,
196	ARM_MOVPCRX	= 183,
197	ARM_MOVTi16_ga_pcrel	= 184,
198	ARM_MOV_ga_pcrel	= 185,
199	ARM_MOV_ga_pcrel_ldr	= 186,
200	ARM_MOVi16_ga_pcrel	= 187,
201	ARM_MOVi32imm	= 188,
202	ARM_MOVsra_flag	= 189,
203	ARM_MOVsrl_flag	= 190,
204	ARM_MULv5	= 191,
205	ARM_MVNCCi	= 192,
206	ARM_PICADD	= 193,
207	ARM_PICLDR	= 194,
208	ARM_PICLDRB	= 195,
209	ARM_PICLDRH	= 196,
210	ARM_PICLDRSB	= 197,
211	ARM_PICLDRSH	= 198,
212	ARM_PICSTR	= 199,
213	ARM_PICSTRB	= 200,
214	ARM_PICSTRH	= 201,
215	ARM_RORi	= 202,
216	ARM_RORr	= 203,
217	ARM_RRX	= 204,
218	ARM_RRXi	= 205,
219	ARM_RSBSri	= 206,
220	ARM_RSBSrsi	= 207,
221	ARM_RSBSrsr	= 208,
222	ARM_SMLALv5	= 209,
223	ARM_SMULLv5	= 210,
224	ARM_SPACE	= 211,
225	ARM_STRBT_POST	= 212,
226	ARM_STRBi_preidx	= 213,
227	ARM_STRBr_preidx	= 214,
228	ARM_STRH_preidx	= 215,
229	ARM_STRT_POST	= 216,
230	ARM_STRi_preidx	= 217,
231	ARM_STRr_preidx	= 218,
232	ARM_SUBS_PC_LR	= 219,
233	ARM_SUBSri	= 220,
234	ARM_SUBSrr	= 221,
235	ARM_SUBSrsi	= 222,
236	ARM_SUBSrsr	= 223,
237	ARM_TAILJMPd	= 224,
238	ARM_TAILJMPr	= 225,
239	ARM_TAILJMPr4	= 226,
240	ARM_TCRETURNdi	= 227,
241	ARM_TCRETURNri	= 228,
242	ARM_TPsoft	= 229,
243	ARM_UMLALv5	= 230,
244	ARM_UMULLv5	= 231,
245	ARM_VLD1LNdAsm_16	= 232,
246	ARM_VLD1LNdAsm_32	= 233,
247	ARM_VLD1LNdAsm_8	= 234,
248	ARM_VLD1LNdWB_fixed_Asm_16	= 235,
249	ARM_VLD1LNdWB_fixed_Asm_32	= 236,
250	ARM_VLD1LNdWB_fixed_Asm_8	= 237,
251	ARM_VLD1LNdWB_register_Asm_16	= 238,
252	ARM_VLD1LNdWB_register_Asm_32	= 239,
253	ARM_VLD1LNdWB_register_Asm_8	= 240,
254	ARM_VLD2LNdAsm_16	= 241,
255	ARM_VLD2LNdAsm_32	= 242,
256	ARM_VLD2LNdAsm_8	= 243,
257	ARM_VLD2LNdWB_fixed_Asm_16	= 244,
258	ARM_VLD2LNdWB_fixed_Asm_32	= 245,
259	ARM_VLD2LNdWB_fixed_Asm_8	= 246,
260	ARM_VLD2LNdWB_register_Asm_16	= 247,
261	ARM_VLD2LNdWB_register_Asm_32	= 248,
262	ARM_VLD2LNdWB_register_Asm_8	= 249,
263	ARM_VLD2LNqAsm_16	= 250,
264	ARM_VLD2LNqAsm_32	= 251,
265	ARM_VLD2LNqWB_fixed_Asm_16	= 252,
266	ARM_VLD2LNqWB_fixed_Asm_32	= 253,
267	ARM_VLD2LNqWB_register_Asm_16	= 254,
268	ARM_VLD2LNqWB_register_Asm_32	= 255,
269	ARM_VLD3DUPdAsm_16	= 256,
270	ARM_VLD3DUPdAsm_32	= 257,
271	ARM_VLD3DUPdAsm_8	= 258,
272	ARM_VLD3DUPdWB_fixed_Asm_16	= 259,
273	ARM_VLD3DUPdWB_fixed_Asm_32	= 260,
274	ARM_VLD3DUPdWB_fixed_Asm_8	= 261,
275	ARM_VLD3DUPdWB_register_Asm_16	= 262,
276	ARM_VLD3DUPdWB_register_Asm_32	= 263,
277	ARM_VLD3DUPdWB_register_Asm_8	= 264,
278	ARM_VLD3DUPqAsm_16	= 265,
279	ARM_VLD3DUPqAsm_32	= 266,
280	ARM_VLD3DUPqAsm_8	= 267,
281	ARM_VLD3DUPqWB_fixed_Asm_16	= 268,
282	ARM_VLD3DUPqWB_fixed_Asm_32	= 269,
283	ARM_VLD3DUPqWB_fixed_Asm_8	= 270,
284	ARM_VLD3DUPqWB_register_Asm_16	= 271,
285	ARM_VLD3DUPqWB_register_Asm_32	= 272,
286	ARM_VLD3DUPqWB_register_Asm_8	= 273,
287	ARM_VLD3LNdAsm_16	= 274,
288	ARM_VLD3LNdAsm_32	= 275,
289	ARM_VLD3LNdAsm_8	= 276,
290	ARM_VLD3LNdWB_fixed_Asm_16	= 277,
291	ARM_VLD3LNdWB_fixed_Asm_32	= 278,
292	ARM_VLD3LNdWB_fixed_Asm_8	= 279,
293	ARM_VLD3LNdWB_register_Asm_16	= 280,
294	ARM_VLD3LNdWB_register_Asm_32	= 281,
295	ARM_VLD3LNdWB_register_Asm_8	= 282,
296	ARM_VLD3LNqAsm_16	= 283,
297	ARM_VLD3LNqAsm_32	= 284,
298	ARM_VLD3LNqWB_fixed_Asm_16	= 285,
299	ARM_VLD3LNqWB_fixed_Asm_32	= 286,
300	ARM_VLD3LNqWB_register_Asm_16	= 287,
301	ARM_VLD3LNqWB_register_Asm_32	= 288,
302	ARM_VLD3dAsm_16	= 289,
303	ARM_VLD3dAsm_32	= 290,
304	ARM_VLD3dAsm_8	= 291,
305	ARM_VLD3dWB_fixed_Asm_16	= 292,
306	ARM_VLD3dWB_fixed_Asm_32	= 293,
307	ARM_VLD3dWB_fixed_Asm_8	= 294,
308	ARM_VLD3dWB_register_Asm_16	= 295,
309	ARM_VLD3dWB_register_Asm_32	= 296,
310	ARM_VLD3dWB_register_Asm_8	= 297,
311	ARM_VLD3qAsm_16	= 298,
312	ARM_VLD3qAsm_32	= 299,
313	ARM_VLD3qAsm_8	= 300,
314	ARM_VLD3qWB_fixed_Asm_16	= 301,
315	ARM_VLD3qWB_fixed_Asm_32	= 302,
316	ARM_VLD3qWB_fixed_Asm_8	= 303,
317	ARM_VLD3qWB_register_Asm_16	= 304,
318	ARM_VLD3qWB_register_Asm_32	= 305,
319	ARM_VLD3qWB_register_Asm_8	= 306,
320	ARM_VLD4DUPdAsm_16	= 307,
321	ARM_VLD4DUPdAsm_32	= 308,
322	ARM_VLD4DUPdAsm_8	= 309,
323	ARM_VLD4DUPdWB_fixed_Asm_16	= 310,
324	ARM_VLD4DUPdWB_fixed_Asm_32	= 311,
325	ARM_VLD4DUPdWB_fixed_Asm_8	= 312,
326	ARM_VLD4DUPdWB_register_Asm_16	= 313,
327	ARM_VLD4DUPdWB_register_Asm_32	= 314,
328	ARM_VLD4DUPdWB_register_Asm_8	= 315,
329	ARM_VLD4DUPqAsm_16	= 316,
330	ARM_VLD4DUPqAsm_32	= 317,
331	ARM_VLD4DUPqAsm_8	= 318,
332	ARM_VLD4DUPqWB_fixed_Asm_16	= 319,
333	ARM_VLD4DUPqWB_fixed_Asm_32	= 320,
334	ARM_VLD4DUPqWB_fixed_Asm_8	= 321,
335	ARM_VLD4DUPqWB_register_Asm_16	= 322,
336	ARM_VLD4DUPqWB_register_Asm_32	= 323,
337	ARM_VLD4DUPqWB_register_Asm_8	= 324,
338	ARM_VLD4LNdAsm_16	= 325,
339	ARM_VLD4LNdAsm_32	= 326,
340	ARM_VLD4LNdAsm_8	= 327,
341	ARM_VLD4LNdWB_fixed_Asm_16	= 328,
342	ARM_VLD4LNdWB_fixed_Asm_32	= 329,
343	ARM_VLD4LNdWB_fixed_Asm_8	= 330,
344	ARM_VLD4LNdWB_register_Asm_16	= 331,
345	ARM_VLD4LNdWB_register_Asm_32	= 332,
346	ARM_VLD4LNdWB_register_Asm_8	= 333,
347	ARM_VLD4LNqAsm_16	= 334,
348	ARM_VLD4LNqAsm_32	= 335,
349	ARM_VLD4LNqWB_fixed_Asm_16	= 336,
350	ARM_VLD4LNqWB_fixed_Asm_32	= 337,
351	ARM_VLD4LNqWB_register_Asm_16	= 338,
352	ARM_VLD4LNqWB_register_Asm_32	= 339,
353	ARM_VLD4dAsm_16	= 340,
354	ARM_VLD4dAsm_32	= 341,
355	ARM_VLD4dAsm_8	= 342,
356	ARM_VLD4dWB_fixed_Asm_16	= 343,
357	ARM_VLD4dWB_fixed_Asm_32	= 344,
358	ARM_VLD4dWB_fixed_Asm_8	= 345,
359	ARM_VLD4dWB_register_Asm_16	= 346,
360	ARM_VLD4dWB_register_Asm_32	= 347,
361	ARM_VLD4dWB_register_Asm_8	= 348,
362	ARM_VLD4qAsm_16	= 349,
363	ARM_VLD4qAsm_32	= 350,
364	ARM_VLD4qAsm_8	= 351,
365	ARM_VLD4qWB_fixed_Asm_16	= 352,
366	ARM_VLD4qWB_fixed_Asm_32	= 353,
367	ARM_VLD4qWB_fixed_Asm_8	= 354,
368	ARM_VLD4qWB_register_Asm_16	= 355,
369	ARM_VLD4qWB_register_Asm_32	= 356,
370	ARM_VLD4qWB_register_Asm_8	= 357,
371	ARM_VMOVD0	= 358,
372	ARM_VMOVDcc	= 359,
373	ARM_VMOVQ0	= 360,
374	ARM_VMOVScc	= 361,
375	ARM_VST1LNdAsm_16	= 362,
376	ARM_VST1LNdAsm_32	= 363,
377	ARM_VST1LNdAsm_8	= 364,
378	ARM_VST1LNdWB_fixed_Asm_16	= 365,
379	ARM_VST1LNdWB_fixed_Asm_32	= 366,
380	ARM_VST1LNdWB_fixed_Asm_8	= 367,
381	ARM_VST1LNdWB_register_Asm_16	= 368,
382	ARM_VST1LNdWB_register_Asm_32	= 369,
383	ARM_VST1LNdWB_register_Asm_8	= 370,
384	ARM_VST2LNdAsm_16	= 371,
385	ARM_VST2LNdAsm_32	= 372,
386	ARM_VST2LNdAsm_8	= 373,
387	ARM_VST2LNdWB_fixed_Asm_16	= 374,
388	ARM_VST2LNdWB_fixed_Asm_32	= 375,
389	ARM_VST2LNdWB_fixed_Asm_8	= 376,
390	ARM_VST2LNdWB_register_Asm_16	= 377,
391	ARM_VST2LNdWB_register_Asm_32	= 378,
392	ARM_VST2LNdWB_register_Asm_8	= 379,
393	ARM_VST2LNqAsm_16	= 380,
394	ARM_VST2LNqAsm_32	= 381,
395	ARM_VST2LNqWB_fixed_Asm_16	= 382,
396	ARM_VST2LNqWB_fixed_Asm_32	= 383,
397	ARM_VST2LNqWB_register_Asm_16	= 384,
398	ARM_VST2LNqWB_register_Asm_32	= 385,
399	ARM_VST3LNdAsm_16	= 386,
400	ARM_VST3LNdAsm_32	= 387,
401	ARM_VST3LNdAsm_8	= 388,
402	ARM_VST3LNdWB_fixed_Asm_16	= 389,
403	ARM_VST3LNdWB_fixed_Asm_32	= 390,
404	ARM_VST3LNdWB_fixed_Asm_8	= 391,
405	ARM_VST3LNdWB_register_Asm_16	= 392,
406	ARM_VST3LNdWB_register_Asm_32	= 393,
407	ARM_VST3LNdWB_register_Asm_8	= 394,
408	ARM_VST3LNqAsm_16	= 395,
409	ARM_VST3LNqAsm_32	= 396,
410	ARM_VST3LNqWB_fixed_Asm_16	= 397,
411	ARM_VST3LNqWB_fixed_Asm_32	= 398,
412	ARM_VST3LNqWB_register_Asm_16	= 399,
413	ARM_VST3LNqWB_register_Asm_32	= 400,
414	ARM_VST3dAsm_16	= 401,
415	ARM_VST3dAsm_32	= 402,
416	ARM_VST3dAsm_8	= 403,
417	ARM_VST3dWB_fixed_Asm_16	= 404,
418	ARM_VST3dWB_fixed_Asm_32	= 405,
419	ARM_VST3dWB_fixed_Asm_8	= 406,
420	ARM_VST3dWB_register_Asm_16	= 407,
421	ARM_VST3dWB_register_Asm_32	= 408,
422	ARM_VST3dWB_register_Asm_8	= 409,
423	ARM_VST3qAsm_16	= 410,
424	ARM_VST3qAsm_32	= 411,
425	ARM_VST3qAsm_8	= 412,
426	ARM_VST3qWB_fixed_Asm_16	= 413,
427	ARM_VST3qWB_fixed_Asm_32	= 414,
428	ARM_VST3qWB_fixed_Asm_8	= 415,
429	ARM_VST3qWB_register_Asm_16	= 416,
430	ARM_VST3qWB_register_Asm_32	= 417,
431	ARM_VST3qWB_register_Asm_8	= 418,
432	ARM_VST4LNdAsm_16	= 419,
433	ARM_VST4LNdAsm_32	= 420,
434	ARM_VST4LNdAsm_8	= 421,
435	ARM_VST4LNdWB_fixed_Asm_16	= 422,
436	ARM_VST4LNdWB_fixed_Asm_32	= 423,
437	ARM_VST4LNdWB_fixed_Asm_8	= 424,
438	ARM_VST4LNdWB_register_Asm_16	= 425,
439	ARM_VST4LNdWB_register_Asm_32	= 426,
440	ARM_VST4LNdWB_register_Asm_8	= 427,
441	ARM_VST4LNqAsm_16	= 428,
442	ARM_VST4LNqAsm_32	= 429,
443	ARM_VST4LNqWB_fixed_Asm_16	= 430,
444	ARM_VST4LNqWB_fixed_Asm_32	= 431,
445	ARM_VST4LNqWB_register_Asm_16	= 432,
446	ARM_VST4LNqWB_register_Asm_32	= 433,
447	ARM_VST4dAsm_16	= 434,
448	ARM_VST4dAsm_32	= 435,
449	ARM_VST4dAsm_8	= 436,
450	ARM_VST4dWB_fixed_Asm_16	= 437,
451	ARM_VST4dWB_fixed_Asm_32	= 438,
452	ARM_VST4dWB_fixed_Asm_8	= 439,
453	ARM_VST4dWB_register_Asm_16	= 440,
454	ARM_VST4dWB_register_Asm_32	= 441,
455	ARM_VST4dWB_register_Asm_8	= 442,
456	ARM_VST4qAsm_16	= 443,
457	ARM_VST4qAsm_32	= 444,
458	ARM_VST4qAsm_8	= 445,
459	ARM_VST4qWB_fixed_Asm_16	= 446,
460	ARM_VST4qWB_fixed_Asm_32	= 447,
461	ARM_VST4qWB_fixed_Asm_8	= 448,
462	ARM_VST4qWB_register_Asm_16	= 449,
463	ARM_VST4qWB_register_Asm_32	= 450,
464	ARM_VST4qWB_register_Asm_8	= 451,
465	ARM_t2ABS	= 454,
466	ARM_t2ADDSri	= 455,
467	ARM_t2ADDSrr	= 456,
468	ARM_t2ADDSrs	= 457,
469	ARM_t2BR_JT	= 458,
470	ARM_t2LDMIA_RET	= 459,
471	ARM_t2LDRBpcrel	= 460,
472	ARM_t2LDRConstPool	= 461,
473	ARM_t2LDRHpcrel	= 462,
474	ARM_t2LDRSBpcrel	= 463,
475	ARM_t2LDRSHpcrel	= 464,
476	ARM_t2LDRpci_pic	= 465,
477	ARM_t2LDRpcrel	= 466,
478	ARM_t2LEApcrel	= 467,
479	ARM_t2LEApcrelJT	= 468,
480	ARM_t2MOVCCasr	= 469,
481	ARM_t2MOVCCi	= 470,
482	ARM_t2MOVCCi16	= 471,
483	ARM_t2MOVCCi32imm	= 472,
484	ARM_t2MOVCClsl	= 473,
485	ARM_t2MOVCClsr	= 474,
486	ARM_t2MOVCCr	= 475,
487	ARM_t2MOVCCror	= 476,
488	ARM_t2MOVSsi	= 477,
489	ARM_t2MOVSsr	= 478,
490	ARM_t2MOVTi16_ga_pcrel	= 479,
491	ARM_t2MOV_ga_pcrel	= 480,
492	ARM_t2MOVi16_ga_pcrel	= 481,
493	ARM_t2MOVi32imm	= 482,
494	ARM_t2MOVsi	= 483,
495	ARM_t2MOVsr	= 484,
496	ARM_t2MVNCCi	= 485,
497	ARM_t2RSBSri	= 486,
498	ARM_t2RSBSrs	= 487,
499	ARM_t2STRB_preidx	= 488,
500	ARM_t2STRH_preidx	= 489,
501	ARM_t2STR_preidx	= 490,
502	ARM_t2SUBSri	= 491,
503	ARM_t2SUBSrr	= 492,
504	ARM_t2SUBSrs	= 493,
505	ARM_t2TBB_JT	= 494,
506	ARM_t2TBH_JT	= 495,
507	ARM_tADCS	= 496,
508	ARM_tADDSi3	= 497,
509	ARM_tADDSi8	= 498,
510	ARM_tADDSrr	= 499,
511	ARM_tADDframe	= 500,
512	ARM_tADJCALLSTACKDOWN	= 501,
513	ARM_tADJCALLSTACKUP	= 502,
514	ARM_tBRIND	= 503,
515	ARM_tBR_JTr	= 504,
516	ARM_tBX_CALL	= 505,
517	ARM_tBX_RET	= 506,
518	ARM_tBX_RET_vararg	= 507,
519	ARM_tBfar	= 508,
520	ARM_tLDMIA_UPD	= 509,
521	ARM_tLDRConstPool	= 510,
522	ARM_tLDRLIT_ga_abs	= 511,
523	ARM_tLDRLIT_ga_pcrel	= 512,
524	ARM_tLDR_postidx	= 513,
525	ARM_tLDRpci_pic	= 514,
526	ARM_tLEApcrel	= 515,
527	ARM_tLEApcrelJT	= 516,
528	ARM_tMOVCCr_pseudo	= 517,
529	ARM_tPOP_RET	= 518,
530	ARM_tSBCS	= 519,
531	ARM_tSUBSi3	= 520,
532	ARM_tSUBSi8	= 521,
533	ARM_tSUBSrr	= 522,
534	ARM_tTAILJMPd	= 523,
535	ARM_tTAILJMPdND	= 524,
536	ARM_tTAILJMPr	= 525,
537	ARM_tTBB_JT	= 526,
538	ARM_tTBH_JT	= 527,
539	ARM_tTPsoft	= 528,
540	ARM_ADCri	= 529,
541	ARM_ADCrr	= 530,
542	ARM_ADCrsi	= 531,
543	ARM_ADCrsr	= 532,
544	ARM_ADDri	= 533,
545	ARM_ADDrr	= 534,
546	ARM_ADDrsi	= 535,
547	ARM_ADDrsr	= 536,
548	ARM_ADR	= 537,
549	ARM_AESD	= 538,
550	ARM_AESE	= 539,
551	ARM_AESIMC	= 540,
552	ARM_AESMC	= 541,
553	ARM_ANDri	= 542,
554	ARM_ANDrr	= 543,
555	ARM_ANDrsi	= 544,
556	ARM_ANDrsr	= 545,
557	ARM_BFC	= 546,
558	ARM_BFI	= 547,
559	ARM_BICri	= 548,
560	ARM_BICrr	= 549,
561	ARM_BICrsi	= 550,
562	ARM_BICrsr	= 551,
563	ARM_BKPT	= 552,
564	ARM_BL	= 553,
565	ARM_BLX	= 554,
566	ARM_BLX_pred	= 555,
567	ARM_BLXi	= 556,
568	ARM_BL_pred	= 557,
569	ARM_BX	= 558,
570	ARM_BXJ	= 559,
571	ARM_BX_RET	= 560,
572	ARM_BX_pred	= 561,
573	ARM_Bcc	= 562,
574	ARM_CDP	= 563,
575	ARM_CDP2	= 564,
576	ARM_CLREX	= 565,
577	ARM_CLZ	= 566,
578	ARM_CMNri	= 567,
579	ARM_CMNzrr	= 568,
580	ARM_CMNzrsi	= 569,
581	ARM_CMNzrsr	= 570,
582	ARM_CMPri	= 571,
583	ARM_CMPrr	= 572,
584	ARM_CMPrsi	= 573,
585	ARM_CMPrsr	= 574,
586	ARM_CPS1p	= 575,
587	ARM_CPS2p	= 576,
588	ARM_CPS3p	= 577,
589	ARM_CRC32B	= 578,
590	ARM_CRC32CB	= 579,
591	ARM_CRC32CH	= 580,
592	ARM_CRC32CW	= 581,
593	ARM_CRC32H	= 582,
594	ARM_CRC32W	= 583,
595	ARM_DBG	= 584,
596	ARM_DMB	= 585,
597	ARM_DSB	= 586,
598	ARM_EORri	= 587,
599	ARM_EORrr	= 588,
600	ARM_EORrsi	= 589,
601	ARM_EORrsr	= 590,
602	ARM_ERET	= 591,
603	ARM_FCONSTD	= 592,
604	ARM_FCONSTH	= 593,
605	ARM_FCONSTS	= 594,
606	ARM_FLDMXDB_UPD	= 595,
607	ARM_FLDMXIA	= 596,
608	ARM_FLDMXIA_UPD	= 597,
609	ARM_FMSTAT	= 598,
610	ARM_FSTMXDB_UPD	= 599,
611	ARM_FSTMXIA	= 600,
612	ARM_FSTMXIA_UPD	= 601,
613	ARM_HINT	= 602,
614	ARM_HLT	= 603,
615	ARM_HVC	= 604,
616	ARM_ISB	= 605,
617	ARM_LDA	= 606,
618	ARM_LDAB	= 607,
619	ARM_LDAEX	= 608,
620	ARM_LDAEXB	= 609,
621	ARM_LDAEXD	= 610,
622	ARM_LDAEXH	= 611,
623	ARM_LDAH	= 612,
624	ARM_LDC2L_OFFSET	= 613,
625	ARM_LDC2L_OPTION	= 614,
626	ARM_LDC2L_POST	= 615,
627	ARM_LDC2L_PRE	= 616,
628	ARM_LDC2_OFFSET	= 617,
629	ARM_LDC2_OPTION	= 618,
630	ARM_LDC2_POST	= 619,
631	ARM_LDC2_PRE	= 620,
632	ARM_LDCL_OFFSET	= 621,
633	ARM_LDCL_OPTION	= 622,
634	ARM_LDCL_POST	= 623,
635	ARM_LDCL_PRE	= 624,
636	ARM_LDC_OFFSET	= 625,
637	ARM_LDC_OPTION	= 626,
638	ARM_LDC_POST	= 627,
639	ARM_LDC_PRE	= 628,
640	ARM_LDMDA	= 629,
641	ARM_LDMDA_UPD	= 630,
642	ARM_LDMDB	= 631,
643	ARM_LDMDB_UPD	= 632,
644	ARM_LDMIA	= 633,
645	ARM_LDMIA_UPD	= 634,
646	ARM_LDMIB	= 635,
647	ARM_LDMIB_UPD	= 636,
648	ARM_LDRBT_POST_IMM	= 637,
649	ARM_LDRBT_POST_REG	= 638,
650	ARM_LDRB_POST_IMM	= 639,
651	ARM_LDRB_POST_REG	= 640,
652	ARM_LDRB_PRE_IMM	= 641,
653	ARM_LDRB_PRE_REG	= 642,
654	ARM_LDRBi12	= 643,
655	ARM_LDRBrs	= 644,
656	ARM_LDRD	= 645,
657	ARM_LDRD_POST	= 646,
658	ARM_LDRD_PRE	= 647,
659	ARM_LDREX	= 648,
660	ARM_LDREXB	= 649,
661	ARM_LDREXD	= 650,
662	ARM_LDREXH	= 651,
663	ARM_LDRH	= 652,
664	ARM_LDRHTi	= 653,
665	ARM_LDRHTr	= 654,
666	ARM_LDRH_POST	= 655,
667	ARM_LDRH_PRE	= 656,
668	ARM_LDRSB	= 657,
669	ARM_LDRSBTi	= 658,
670	ARM_LDRSBTr	= 659,
671	ARM_LDRSB_POST	= 660,
672	ARM_LDRSB_PRE	= 661,
673	ARM_LDRSH	= 662,
674	ARM_LDRSHTi	= 663,
675	ARM_LDRSHTr	= 664,
676	ARM_LDRSH_POST	= 665,
677	ARM_LDRSH_PRE	= 666,
678	ARM_LDRT_POST_IMM	= 667,
679	ARM_LDRT_POST_REG	= 668,
680	ARM_LDR_POST_IMM	= 669,
681	ARM_LDR_POST_REG	= 670,
682	ARM_LDR_PRE_IMM	= 671,
683	ARM_LDR_PRE_REG	= 672,
684	ARM_LDRcp	= 673,
685	ARM_LDRi12	= 674,
686	ARM_LDRrs	= 675,
687	ARM_MCR	= 676,
688	ARM_MCR2	= 677,
689	ARM_MCRR	= 678,
690	ARM_MCRR2	= 679,
691	ARM_MLA	= 680,
692	ARM_MLS	= 681,
693	ARM_MOVPCLR	= 682,
694	ARM_MOVTi16	= 683,
695	ARM_MOVi	= 684,
696	ARM_MOVi16	= 685,
697	ARM_MOVr	= 686,
698	ARM_MOVr_TC	= 687,
699	ARM_MOVsi	= 688,
700	ARM_MOVsr	= 689,
701	ARM_MRC	= 690,
702	ARM_MRC2	= 691,
703	ARM_MRRC	= 692,
704	ARM_MRRC2	= 693,
705	ARM_MRS	= 694,
706	ARM_MRSbanked	= 695,
707	ARM_MRSsys	= 696,
708	ARM_MSR	= 697,
709	ARM_MSRbanked	= 698,
710	ARM_MSRi	= 699,
711	ARM_MUL	= 700,
712	ARM_MVNi	= 701,
713	ARM_MVNr	= 702,
714	ARM_MVNsi	= 703,
715	ARM_MVNsr	= 704,
716	ARM_ORRri	= 705,
717	ARM_ORRrr	= 706,
718	ARM_ORRrsi	= 707,
719	ARM_ORRrsr	= 708,
720	ARM_PKHBT	= 709,
721	ARM_PKHTB	= 710,
722	ARM_PLDWi12	= 711,
723	ARM_PLDWrs	= 712,
724	ARM_PLDi12	= 713,
725	ARM_PLDrs	= 714,
726	ARM_PLIi12	= 715,
727	ARM_PLIrs	= 716,
728	ARM_QADD	= 717,
729	ARM_QADD16	= 718,
730	ARM_QADD8	= 719,
731	ARM_QASX	= 720,
732	ARM_QDADD	= 721,
733	ARM_QDSUB	= 722,
734	ARM_QSAX	= 723,
735	ARM_QSUB	= 724,
736	ARM_QSUB16	= 725,
737	ARM_QSUB8	= 726,
738	ARM_RBIT	= 727,
739	ARM_REV	= 728,
740	ARM_REV16	= 729,
741	ARM_REVSH	= 730,
742	ARM_RFEDA	= 731,
743	ARM_RFEDA_UPD	= 732,
744	ARM_RFEDB	= 733,
745	ARM_RFEDB_UPD	= 734,
746	ARM_RFEIA	= 735,
747	ARM_RFEIA_UPD	= 736,
748	ARM_RFEIB	= 737,
749	ARM_RFEIB_UPD	= 738,
750	ARM_RSBri	= 739,
751	ARM_RSBrr	= 740,
752	ARM_RSBrsi	= 741,
753	ARM_RSBrsr	= 742,
754	ARM_RSCri	= 743,
755	ARM_RSCrr	= 744,
756	ARM_RSCrsi	= 745,
757	ARM_RSCrsr	= 746,
758	ARM_SADD16	= 747,
759	ARM_SADD8	= 748,
760	ARM_SASX	= 749,
761	ARM_SBCri	= 750,
762	ARM_SBCrr	= 751,
763	ARM_SBCrsi	= 752,
764	ARM_SBCrsr	= 753,
765	ARM_SBFX	= 754,
766	ARM_SDIV	= 755,
767	ARM_SEL	= 756,
768	ARM_SETEND	= 757,
769	ARM_SETPAN	= 758,
770	ARM_SHA1C	= 759,
771	ARM_SHA1H	= 760,
772	ARM_SHA1M	= 761,
773	ARM_SHA1P	= 762,
774	ARM_SHA1SU0	= 763,
775	ARM_SHA1SU1	= 764,
776	ARM_SHA256H	= 765,
777	ARM_SHA256H2	= 766,
778	ARM_SHA256SU0	= 767,
779	ARM_SHA256SU1	= 768,
780	ARM_SHADD16	= 769,
781	ARM_SHADD8	= 770,
782	ARM_SHASX	= 771,
783	ARM_SHSAX	= 772,
784	ARM_SHSUB16	= 773,
785	ARM_SHSUB8	= 774,
786	ARM_SMC	= 775,
787	ARM_SMLABB	= 776,
788	ARM_SMLABT	= 777,
789	ARM_SMLAD	= 778,
790	ARM_SMLADX	= 779,
791	ARM_SMLAL	= 780,
792	ARM_SMLALBB	= 781,
793	ARM_SMLALBT	= 782,
794	ARM_SMLALD	= 783,
795	ARM_SMLALDX	= 784,
796	ARM_SMLALTB	= 785,
797	ARM_SMLALTT	= 786,
798	ARM_SMLATB	= 787,
799	ARM_SMLATT	= 788,
800	ARM_SMLAWB	= 789,
801	ARM_SMLAWT	= 790,
802	ARM_SMLSD	= 791,
803	ARM_SMLSDX	= 792,
804	ARM_SMLSLD	= 793,
805	ARM_SMLSLDX	= 794,
806	ARM_SMMLA	= 795,
807	ARM_SMMLAR	= 796,
808	ARM_SMMLS	= 797,
809	ARM_SMMLSR	= 798,
810	ARM_SMMUL	= 799,
811	ARM_SMMULR	= 800,
812	ARM_SMUAD	= 801,
813	ARM_SMUADX	= 802,
814	ARM_SMULBB	= 803,
815	ARM_SMULBT	= 804,
816	ARM_SMULL	= 805,
817	ARM_SMULTB	= 806,
818	ARM_SMULTT	= 807,
819	ARM_SMULWB	= 808,
820	ARM_SMULWT	= 809,
821	ARM_SMUSD	= 810,
822	ARM_SMUSDX	= 811,
823	ARM_SRSDA	= 812,
824	ARM_SRSDA_UPD	= 813,
825	ARM_SRSDB	= 814,
826	ARM_SRSDB_UPD	= 815,
827	ARM_SRSIA	= 816,
828	ARM_SRSIA_UPD	= 817,
829	ARM_SRSIB	= 818,
830	ARM_SRSIB_UPD	= 819,
831	ARM_SSAT	= 820,
832	ARM_SSAT16	= 821,
833	ARM_SSAX	= 822,
834	ARM_SSUB16	= 823,
835	ARM_SSUB8	= 824,
836	ARM_STC2L_OFFSET	= 825,
837	ARM_STC2L_OPTION	= 826,
838	ARM_STC2L_POST	= 827,
839	ARM_STC2L_PRE	= 828,
840	ARM_STC2_OFFSET	= 829,
841	ARM_STC2_OPTION	= 830,
842	ARM_STC2_POST	= 831,
843	ARM_STC2_PRE	= 832,
844	ARM_STCL_OFFSET	= 833,
845	ARM_STCL_OPTION	= 834,
846	ARM_STCL_POST	= 835,
847	ARM_STCL_PRE	= 836,
848	ARM_STC_OFFSET	= 837,
849	ARM_STC_OPTION	= 838,
850	ARM_STC_POST	= 839,
851	ARM_STC_PRE	= 840,
852	ARM_STL	= 841,
853	ARM_STLB	= 842,
854	ARM_STLEX	= 843,
855	ARM_STLEXB	= 844,
856	ARM_STLEXD	= 845,
857	ARM_STLEXH	= 846,
858	ARM_STLH	= 847,
859	ARM_STMDA	= 848,
860	ARM_STMDA_UPD	= 849,
861	ARM_STMDB	= 850,
862	ARM_STMDB_UPD	= 851,
863	ARM_STMIA	= 852,
864	ARM_STMIA_UPD	= 853,
865	ARM_STMIB	= 854,
866	ARM_STMIB_UPD	= 855,
867	ARM_STRBT_POST_IMM	= 856,
868	ARM_STRBT_POST_REG	= 857,
869	ARM_STRB_POST_IMM	= 858,
870	ARM_STRB_POST_REG	= 859,
871	ARM_STRB_PRE_IMM	= 860,
872	ARM_STRB_PRE_REG	= 861,
873	ARM_STRBi12	= 862,
874	ARM_STRBrs	= 863,
875	ARM_STRD	= 864,
876	ARM_STRD_POST	= 865,
877	ARM_STRD_PRE	= 866,
878	ARM_STREX	= 867,
879	ARM_STREXB	= 868,
880	ARM_STREXD	= 869,
881	ARM_STREXH	= 870,
882	ARM_STRH	= 871,
883	ARM_STRHTi	= 872,
884	ARM_STRHTr	= 873,
885	ARM_STRH_POST	= 874,
886	ARM_STRH_PRE	= 875,
887	ARM_STRT_POST_IMM	= 876,
888	ARM_STRT_POST_REG	= 877,
889	ARM_STR_POST_IMM	= 878,
890	ARM_STR_POST_REG	= 879,
891	ARM_STR_PRE_IMM	= 880,
892	ARM_STR_PRE_REG	= 881,
893	ARM_STRi12	= 882,
894	ARM_STRrs	= 883,
895	ARM_SUBri	= 884,
896	ARM_SUBrr	= 885,
897	ARM_SUBrsi	= 886,
898	ARM_SUBrsr	= 887,
899	ARM_SVC	= 888,
900	ARM_SWP	= 889,
901	ARM_SWPB	= 890,
902	ARM_SXTAB	= 891,
903	ARM_SXTAB16	= 892,
904	ARM_SXTAH	= 893,
905	ARM_SXTB	= 894,
906	ARM_SXTB16	= 895,
907	ARM_SXTH	= 896,
908	ARM_TEQri	= 897,
909	ARM_TEQrr	= 898,
910	ARM_TEQrsi	= 899,
911	ARM_TEQrsr	= 900,
912	ARM_TRAP	= 901,
913	ARM_TRAPNaCl	= 902,
914	ARM_TSB	= 903,
915	ARM_TSTri	= 904,
916	ARM_TSTrr	= 905,
917	ARM_TSTrsi	= 906,
918	ARM_TSTrsr	= 907,
919	ARM_UADD16	= 908,
920	ARM_UADD8	= 909,
921	ARM_UASX	= 910,
922	ARM_UBFX	= 911,
923	ARM_UDF	= 912,
924	ARM_UDIV	= 913,
925	ARM_UHADD16	= 914,
926	ARM_UHADD8	= 915,
927	ARM_UHASX	= 916,
928	ARM_UHSAX	= 917,
929	ARM_UHSUB16	= 918,
930	ARM_UHSUB8	= 919,
931	ARM_UMAAL	= 920,
932	ARM_UMLAL	= 921,
933	ARM_UMULL	= 922,
934	ARM_UQADD16	= 923,
935	ARM_UQADD8	= 924,
936	ARM_UQASX	= 925,
937	ARM_UQSAX	= 926,
938	ARM_UQSUB16	= 927,
939	ARM_UQSUB8	= 928,
940	ARM_USAD8	= 929,
941	ARM_USADA8	= 930,
942	ARM_USAT	= 931,
943	ARM_USAT16	= 932,
944	ARM_USAX	= 933,
945	ARM_USUB16	= 934,
946	ARM_USUB8	= 935,
947	ARM_UXTAB	= 936,
948	ARM_UXTAB16	= 937,
949	ARM_UXTAH	= 938,
950	ARM_UXTB	= 939,
951	ARM_UXTB16	= 940,
952	ARM_UXTH	= 941,
953	ARM_VABALsv2i64	= 942,
954	ARM_VABALsv4i32	= 943,
955	ARM_VABALsv8i16	= 944,
956	ARM_VABALuv2i64	= 945,
957	ARM_VABALuv4i32	= 946,
958	ARM_VABALuv8i16	= 947,
959	ARM_VABAsv16i8	= 948,
960	ARM_VABAsv2i32	= 949,
961	ARM_VABAsv4i16	= 950,
962	ARM_VABAsv4i32	= 951,
963	ARM_VABAsv8i16	= 952,
964	ARM_VABAsv8i8	= 953,
965	ARM_VABAuv16i8	= 954,
966	ARM_VABAuv2i32	= 955,
967	ARM_VABAuv4i16	= 956,
968	ARM_VABAuv4i32	= 957,
969	ARM_VABAuv8i16	= 958,
970	ARM_VABAuv8i8	= 959,
971	ARM_VABDLsv2i64	= 960,
972	ARM_VABDLsv4i32	= 961,
973	ARM_VABDLsv8i16	= 962,
974	ARM_VABDLuv2i64	= 963,
975	ARM_VABDLuv4i32	= 964,
976	ARM_VABDLuv8i16	= 965,
977	ARM_VABDfd	= 966,
978	ARM_VABDfq	= 967,
979	ARM_VABDhd	= 968,
980	ARM_VABDhq	= 969,
981	ARM_VABDsv16i8	= 970,
982	ARM_VABDsv2i32	= 971,
983	ARM_VABDsv4i16	= 972,
984	ARM_VABDsv4i32	= 973,
985	ARM_VABDsv8i16	= 974,
986	ARM_VABDsv8i8	= 975,
987	ARM_VABDuv16i8	= 976,
988	ARM_VABDuv2i32	= 977,
989	ARM_VABDuv4i16	= 978,
990	ARM_VABDuv4i32	= 979,
991	ARM_VABDuv8i16	= 980,
992	ARM_VABDuv8i8	= 981,
993	ARM_VABSD	= 982,
994	ARM_VABSH	= 983,
995	ARM_VABSS	= 984,
996	ARM_VABSfd	= 985,
997	ARM_VABSfq	= 986,
998	ARM_VABShd	= 987,
999	ARM_VABShq	= 988,
1000	ARM_VABSv16i8	= 989,
1001	ARM_VABSv2i32	= 990,
1002	ARM_VABSv4i16	= 991,
1003	ARM_VABSv4i32	= 992,
1004	ARM_VABSv8i16	= 993,
1005	ARM_VABSv8i8	= 994,
1006	ARM_VACGEfd	= 995,
1007	ARM_VACGEfq	= 996,
1008	ARM_VACGEhd	= 997,
1009	ARM_VACGEhq	= 998,
1010	ARM_VACGTfd	= 999,
1011	ARM_VACGTfq	= 1000,
1012	ARM_VACGThd	= 1001,
1013	ARM_VACGThq	= 1002,
1014	ARM_VADDD	= 1003,
1015	ARM_VADDH	= 1004,
1016	ARM_VADDHNv2i32	= 1005,
1017	ARM_VADDHNv4i16	= 1006,
1018	ARM_VADDHNv8i8	= 1007,
1019	ARM_VADDLsv2i64	= 1008,
1020	ARM_VADDLsv4i32	= 1009,
1021	ARM_VADDLsv8i16	= 1010,
1022	ARM_VADDLuv2i64	= 1011,
1023	ARM_VADDLuv4i32	= 1012,
1024	ARM_VADDLuv8i16	= 1013,
1025	ARM_VADDS	= 1014,
1026	ARM_VADDWsv2i64	= 1015,
1027	ARM_VADDWsv4i32	= 1016,
1028	ARM_VADDWsv8i16	= 1017,
1029	ARM_VADDWuv2i64	= 1018,
1030	ARM_VADDWuv4i32	= 1019,
1031	ARM_VADDWuv8i16	= 1020,
1032	ARM_VADDfd	= 1021,
1033	ARM_VADDfq	= 1022,
1034	ARM_VADDhd	= 1023,
1035	ARM_VADDhq	= 1024,
1036	ARM_VADDv16i8	= 1025,
1037	ARM_VADDv1i64	= 1026,
1038	ARM_VADDv2i32	= 1027,
1039	ARM_VADDv2i64	= 1028,
1040	ARM_VADDv4i16	= 1029,
1041	ARM_VADDv4i32	= 1030,
1042	ARM_VADDv8i16	= 1031,
1043	ARM_VADDv8i8	= 1032,
1044	ARM_VANDd	= 1033,
1045	ARM_VANDq	= 1034,
1046	ARM_VBICd	= 1035,
1047	ARM_VBICiv2i32	= 1036,
1048	ARM_VBICiv4i16	= 1037,
1049	ARM_VBICiv4i32	= 1038,
1050	ARM_VBICiv8i16	= 1039,
1051	ARM_VBICq	= 1040,
1052	ARM_VBIFd	= 1041,
1053	ARM_VBIFq	= 1042,
1054	ARM_VBITd	= 1043,
1055	ARM_VBITq	= 1044,
1056	ARM_VBSLd	= 1045,
1057	ARM_VBSLq	= 1046,
1058	ARM_VCADDv2f32	= 1047,
1059	ARM_VCADDv4f16	= 1048,
1060	ARM_VCADDv4f32	= 1049,
1061	ARM_VCADDv8f16	= 1050,
1062	ARM_VCEQfd	= 1051,
1063	ARM_VCEQfq	= 1052,
1064	ARM_VCEQhd	= 1053,
1065	ARM_VCEQhq	= 1054,
1066	ARM_VCEQv16i8	= 1055,
1067	ARM_VCEQv2i32	= 1056,
1068	ARM_VCEQv4i16	= 1057,
1069	ARM_VCEQv4i32	= 1058,
1070	ARM_VCEQv8i16	= 1059,
1071	ARM_VCEQv8i8	= 1060,
1072	ARM_VCEQzv16i8	= 1061,
1073	ARM_VCEQzv2f32	= 1062,
1074	ARM_VCEQzv2i32	= 1063,
1075	ARM_VCEQzv4f16	= 1064,
1076	ARM_VCEQzv4f32	= 1065,
1077	ARM_VCEQzv4i16	= 1066,
1078	ARM_VCEQzv4i32	= 1067,
1079	ARM_VCEQzv8f16	= 1068,
1080	ARM_VCEQzv8i16	= 1069,
1081	ARM_VCEQzv8i8	= 1070,
1082	ARM_VCGEfd	= 1071,
1083	ARM_VCGEfq	= 1072,
1084	ARM_VCGEhd	= 1073,
1085	ARM_VCGEhq	= 1074,
1086	ARM_VCGEsv16i8	= 1075,
1087	ARM_VCGEsv2i32	= 1076,
1088	ARM_VCGEsv4i16	= 1077,
1089	ARM_VCGEsv4i32	= 1078,
1090	ARM_VCGEsv8i16	= 1079,
1091	ARM_VCGEsv8i8	= 1080,
1092	ARM_VCGEuv16i8	= 1081,
1093	ARM_VCGEuv2i32	= 1082,
1094	ARM_VCGEuv4i16	= 1083,
1095	ARM_VCGEuv4i32	= 1084,
1096	ARM_VCGEuv8i16	= 1085,
1097	ARM_VCGEuv8i8	= 1086,
1098	ARM_VCGEzv16i8	= 1087,
1099	ARM_VCGEzv2f32	= 1088,
1100	ARM_VCGEzv2i32	= 1089,
1101	ARM_VCGEzv4f16	= 1090,
1102	ARM_VCGEzv4f32	= 1091,
1103	ARM_VCGEzv4i16	= 1092,
1104	ARM_VCGEzv4i32	= 1093,
1105	ARM_VCGEzv8f16	= 1094,
1106	ARM_VCGEzv8i16	= 1095,
1107	ARM_VCGEzv8i8	= 1096,
1108	ARM_VCGTfd	= 1097,
1109	ARM_VCGTfq	= 1098,
1110	ARM_VCGThd	= 1099,
1111	ARM_VCGThq	= 1100,
1112	ARM_VCGTsv16i8	= 1101,
1113	ARM_VCGTsv2i32	= 1102,
1114	ARM_VCGTsv4i16	= 1103,
1115	ARM_VCGTsv4i32	= 1104,
1116	ARM_VCGTsv8i16	= 1105,
1117	ARM_VCGTsv8i8	= 1106,
1118	ARM_VCGTuv16i8	= 1107,
1119	ARM_VCGTuv2i32	= 1108,
1120	ARM_VCGTuv4i16	= 1109,
1121	ARM_VCGTuv4i32	= 1110,
1122	ARM_VCGTuv8i16	= 1111,
1123	ARM_VCGTuv8i8	= 1112,
1124	ARM_VCGTzv16i8	= 1113,
1125	ARM_VCGTzv2f32	= 1114,
1126	ARM_VCGTzv2i32	= 1115,
1127	ARM_VCGTzv4f16	= 1116,
1128	ARM_VCGTzv4f32	= 1117,
1129	ARM_VCGTzv4i16	= 1118,
1130	ARM_VCGTzv4i32	= 1119,
1131	ARM_VCGTzv8f16	= 1120,
1132	ARM_VCGTzv8i16	= 1121,
1133	ARM_VCGTzv8i8	= 1122,
1134	ARM_VCLEzv16i8	= 1123,
1135	ARM_VCLEzv2f32	= 1124,
1136	ARM_VCLEzv2i32	= 1125,
1137	ARM_VCLEzv4f16	= 1126,
1138	ARM_VCLEzv4f32	= 1127,
1139	ARM_VCLEzv4i16	= 1128,
1140	ARM_VCLEzv4i32	= 1129,
1141	ARM_VCLEzv8f16	= 1130,
1142	ARM_VCLEzv8i16	= 1131,
1143	ARM_VCLEzv8i8	= 1132,
1144	ARM_VCLSv16i8	= 1133,
1145	ARM_VCLSv2i32	= 1134,
1146	ARM_VCLSv4i16	= 1135,
1147	ARM_VCLSv4i32	= 1136,
1148	ARM_VCLSv8i16	= 1137,
1149	ARM_VCLSv8i8	= 1138,
1150	ARM_VCLTzv16i8	= 1139,
1151	ARM_VCLTzv2f32	= 1140,
1152	ARM_VCLTzv2i32	= 1141,
1153	ARM_VCLTzv4f16	= 1142,
1154	ARM_VCLTzv4f32	= 1143,
1155	ARM_VCLTzv4i16	= 1144,
1156	ARM_VCLTzv4i32	= 1145,
1157	ARM_VCLTzv8f16	= 1146,
1158	ARM_VCLTzv8i16	= 1147,
1159	ARM_VCLTzv8i8	= 1148,
1160	ARM_VCLZv16i8	= 1149,
1161	ARM_VCLZv2i32	= 1150,
1162	ARM_VCLZv4i16	= 1151,
1163	ARM_VCLZv4i32	= 1152,
1164	ARM_VCLZv8i16	= 1153,
1165	ARM_VCLZv8i8	= 1154,
1166	ARM_VCMLAv2f32	= 1155,
1167	ARM_VCMLAv2f32_indexed	= 1156,
1168	ARM_VCMLAv4f16	= 1157,
1169	ARM_VCMLAv4f16_indexed	= 1158,
1170	ARM_VCMLAv4f32	= 1159,
1171	ARM_VCMLAv4f32_indexed	= 1160,
1172	ARM_VCMLAv8f16	= 1161,
1173	ARM_VCMLAv8f16_indexed	= 1162,
1174	ARM_VCMPD	= 1163,
1175	ARM_VCMPED	= 1164,
1176	ARM_VCMPEH	= 1165,
1177	ARM_VCMPES	= 1166,
1178	ARM_VCMPEZD	= 1167,
1179	ARM_VCMPEZH	= 1168,
1180	ARM_VCMPEZS	= 1169,
1181	ARM_VCMPH	= 1170,
1182	ARM_VCMPS	= 1171,
1183	ARM_VCMPZD	= 1172,
1184	ARM_VCMPZH	= 1173,
1185	ARM_VCMPZS	= 1174,
1186	ARM_VCNTd	= 1175,
1187	ARM_VCNTq	= 1176,
1188	ARM_VCVTANSDf	= 1177,
1189	ARM_VCVTANSDh	= 1178,
1190	ARM_VCVTANSQf	= 1179,
1191	ARM_VCVTANSQh	= 1180,
1192	ARM_VCVTANUDf	= 1181,
1193	ARM_VCVTANUDh	= 1182,
1194	ARM_VCVTANUQf	= 1183,
1195	ARM_VCVTANUQh	= 1184,
1196	ARM_VCVTASD	= 1185,
1197	ARM_VCVTASH	= 1186,
1198	ARM_VCVTASS	= 1187,
1199	ARM_VCVTAUD	= 1188,
1200	ARM_VCVTAUH	= 1189,
1201	ARM_VCVTAUS	= 1190,
1202	ARM_VCVTBDH	= 1191,
1203	ARM_VCVTBHD	= 1192,
1204	ARM_VCVTBHS	= 1193,
1205	ARM_VCVTBSH	= 1194,
1206	ARM_VCVTDS	= 1195,
1207	ARM_VCVTMNSDf	= 1196,
1208	ARM_VCVTMNSDh	= 1197,
1209	ARM_VCVTMNSQf	= 1198,
1210	ARM_VCVTMNSQh	= 1199,
1211	ARM_VCVTMNUDf	= 1200,
1212	ARM_VCVTMNUDh	= 1201,
1213	ARM_VCVTMNUQf	= 1202,
1214	ARM_VCVTMNUQh	= 1203,
1215	ARM_VCVTMSD	= 1204,
1216	ARM_VCVTMSH	= 1205,
1217	ARM_VCVTMSS	= 1206,
1218	ARM_VCVTMUD	= 1207,
1219	ARM_VCVTMUH	= 1208,
1220	ARM_VCVTMUS	= 1209,
1221	ARM_VCVTNNSDf	= 1210,
1222	ARM_VCVTNNSDh	= 1211,
1223	ARM_VCVTNNSQf	= 1212,
1224	ARM_VCVTNNSQh	= 1213,
1225	ARM_VCVTNNUDf	= 1214,
1226	ARM_VCVTNNUDh	= 1215,
1227	ARM_VCVTNNUQf	= 1216,
1228	ARM_VCVTNNUQh	= 1217,
1229	ARM_VCVTNSD	= 1218,
1230	ARM_VCVTNSH	= 1219,
1231	ARM_VCVTNSS	= 1220,
1232	ARM_VCVTNUD	= 1221,
1233	ARM_VCVTNUH	= 1222,
1234	ARM_VCVTNUS	= 1223,
1235	ARM_VCVTPNSDf	= 1224,
1236	ARM_VCVTPNSDh	= 1225,
1237	ARM_VCVTPNSQf	= 1226,
1238	ARM_VCVTPNSQh	= 1227,
1239	ARM_VCVTPNUDf	= 1228,
1240	ARM_VCVTPNUDh	= 1229,
1241	ARM_VCVTPNUQf	= 1230,
1242	ARM_VCVTPNUQh	= 1231,
1243	ARM_VCVTPSD	= 1232,
1244	ARM_VCVTPSH	= 1233,
1245	ARM_VCVTPSS	= 1234,
1246	ARM_VCVTPUD	= 1235,
1247	ARM_VCVTPUH	= 1236,
1248	ARM_VCVTPUS	= 1237,
1249	ARM_VCVTSD	= 1238,
1250	ARM_VCVTTDH	= 1239,
1251	ARM_VCVTTHD	= 1240,
1252	ARM_VCVTTHS	= 1241,
1253	ARM_VCVTTSH	= 1242,
1254	ARM_VCVTf2h	= 1243,
1255	ARM_VCVTf2sd	= 1244,
1256	ARM_VCVTf2sq	= 1245,
1257	ARM_VCVTf2ud	= 1246,
1258	ARM_VCVTf2uq	= 1247,
1259	ARM_VCVTf2xsd	= 1248,
1260	ARM_VCVTf2xsq	= 1249,
1261	ARM_VCVTf2xud	= 1250,
1262	ARM_VCVTf2xuq	= 1251,
1263	ARM_VCVTh2f	= 1252,
1264	ARM_VCVTh2sd	= 1253,
1265	ARM_VCVTh2sq	= 1254,
1266	ARM_VCVTh2ud	= 1255,
1267	ARM_VCVTh2uq	= 1256,
1268	ARM_VCVTh2xsd	= 1257,
1269	ARM_VCVTh2xsq	= 1258,
1270	ARM_VCVTh2xud	= 1259,
1271	ARM_VCVTh2xuq	= 1260,
1272	ARM_VCVTs2fd	= 1261,
1273	ARM_VCVTs2fq	= 1262,
1274	ARM_VCVTs2hd	= 1263,
1275	ARM_VCVTs2hq	= 1264,
1276	ARM_VCVTu2fd	= 1265,
1277	ARM_VCVTu2fq	= 1266,
1278	ARM_VCVTu2hd	= 1267,
1279	ARM_VCVTu2hq	= 1268,
1280	ARM_VCVTxs2fd	= 1269,
1281	ARM_VCVTxs2fq	= 1270,
1282	ARM_VCVTxs2hd	= 1271,
1283	ARM_VCVTxs2hq	= 1272,
1284	ARM_VCVTxu2fd	= 1273,
1285	ARM_VCVTxu2fq	= 1274,
1286	ARM_VCVTxu2hd	= 1275,
1287	ARM_VCVTxu2hq	= 1276,
1288	ARM_VDIVD	= 1277,
1289	ARM_VDIVH	= 1278,
1290	ARM_VDIVS	= 1279,
1291	ARM_VDUP16d	= 1280,
1292	ARM_VDUP16q	= 1281,
1293	ARM_VDUP32d	= 1282,
1294	ARM_VDUP32q	= 1283,
1295	ARM_VDUP8d	= 1284,
1296	ARM_VDUP8q	= 1285,
1297	ARM_VDUPLN16d	= 1286,
1298	ARM_VDUPLN16q	= 1287,
1299	ARM_VDUPLN32d	= 1288,
1300	ARM_VDUPLN32q	= 1289,
1301	ARM_VDUPLN8d	= 1290,
1302	ARM_VDUPLN8q	= 1291,
1303	ARM_VEORd	= 1292,
1304	ARM_VEORq	= 1293,
1305	ARM_VEXTd16	= 1294,
1306	ARM_VEXTd32	= 1295,
1307	ARM_VEXTd8	= 1296,
1308	ARM_VEXTq16	= 1297,
1309	ARM_VEXTq32	= 1298,
1310	ARM_VEXTq64	= 1299,
1311	ARM_VEXTq8	= 1300,
1312	ARM_VFMAD	= 1301,
1313	ARM_VFMAH	= 1302,
1314	ARM_VFMAS	= 1303,
1315	ARM_VFMAfd	= 1304,
1316	ARM_VFMAfq	= 1305,
1317	ARM_VFMAhd	= 1306,
1318	ARM_VFMAhq	= 1307,
1319	ARM_VFMSD	= 1308,
1320	ARM_VFMSH	= 1309,
1321	ARM_VFMSS	= 1310,
1322	ARM_VFMSfd	= 1311,
1323	ARM_VFMSfq	= 1312,
1324	ARM_VFMShd	= 1313,
1325	ARM_VFMShq	= 1314,
1326	ARM_VFNMAD	= 1315,
1327	ARM_VFNMAH	= 1316,
1328	ARM_VFNMAS	= 1317,
1329	ARM_VFNMSD	= 1318,
1330	ARM_VFNMSH	= 1319,
1331	ARM_VFNMSS	= 1320,
1332	ARM_VGETLNi32	= 1321,
1333	ARM_VGETLNs16	= 1322,
1334	ARM_VGETLNs8	= 1323,
1335	ARM_VGETLNu16	= 1324,
1336	ARM_VGETLNu8	= 1325,
1337	ARM_VHADDsv16i8	= 1326,
1338	ARM_VHADDsv2i32	= 1327,
1339	ARM_VHADDsv4i16	= 1328,
1340	ARM_VHADDsv4i32	= 1329,
1341	ARM_VHADDsv8i16	= 1330,
1342	ARM_VHADDsv8i8	= 1331,
1343	ARM_VHADDuv16i8	= 1332,
1344	ARM_VHADDuv2i32	= 1333,
1345	ARM_VHADDuv4i16	= 1334,
1346	ARM_VHADDuv4i32	= 1335,
1347	ARM_VHADDuv8i16	= 1336,
1348	ARM_VHADDuv8i8	= 1337,
1349	ARM_VHSUBsv16i8	= 1338,
1350	ARM_VHSUBsv2i32	= 1339,
1351	ARM_VHSUBsv4i16	= 1340,
1352	ARM_VHSUBsv4i32	= 1341,
1353	ARM_VHSUBsv8i16	= 1342,
1354	ARM_VHSUBsv8i8	= 1343,
1355	ARM_VHSUBuv16i8	= 1344,
1356	ARM_VHSUBuv2i32	= 1345,
1357	ARM_VHSUBuv4i16	= 1346,
1358	ARM_VHSUBuv4i32	= 1347,
1359	ARM_VHSUBuv8i16	= 1348,
1360	ARM_VHSUBuv8i8	= 1349,
1361	ARM_VINSH	= 1350,
1362	ARM_VJCVT	= 1351,
1363	ARM_VLD1DUPd16	= 1352,
1364	ARM_VLD1DUPd16wb_fixed	= 1353,
1365	ARM_VLD1DUPd16wb_register	= 1354,
1366	ARM_VLD1DUPd32	= 1355,
1367	ARM_VLD1DUPd32wb_fixed	= 1356,
1368	ARM_VLD1DUPd32wb_register	= 1357,
1369	ARM_VLD1DUPd8	= 1358,
1370	ARM_VLD1DUPd8wb_fixed	= 1359,
1371	ARM_VLD1DUPd8wb_register	= 1360,
1372	ARM_VLD1DUPq16	= 1361,
1373	ARM_VLD1DUPq16wb_fixed	= 1362,
1374	ARM_VLD1DUPq16wb_register	= 1363,
1375	ARM_VLD1DUPq32	= 1364,
1376	ARM_VLD1DUPq32wb_fixed	= 1365,
1377	ARM_VLD1DUPq32wb_register	= 1366,
1378	ARM_VLD1DUPq8	= 1367,
1379	ARM_VLD1DUPq8wb_fixed	= 1368,
1380	ARM_VLD1DUPq8wb_register	= 1369,
1381	ARM_VLD1LNd16	= 1370,
1382	ARM_VLD1LNd16_UPD	= 1371,
1383	ARM_VLD1LNd32	= 1372,
1384	ARM_VLD1LNd32_UPD	= 1373,
1385	ARM_VLD1LNd8	= 1374,
1386	ARM_VLD1LNd8_UPD	= 1375,
1387	ARM_VLD1d16	= 1382,
1388	ARM_VLD1d16Q	= 1383,
1389	ARM_VLD1d16Qwb_fixed	= 1385,
1390	ARM_VLD1d16Qwb_register	= 1386,
1391	ARM_VLD1d16T	= 1387,
1392	ARM_VLD1d16Twb_fixed	= 1389,
1393	ARM_VLD1d16Twb_register	= 1390,
1394	ARM_VLD1d16wb_fixed	= 1391,
1395	ARM_VLD1d16wb_register	= 1392,
1396	ARM_VLD1d32	= 1393,
1397	ARM_VLD1d32Q	= 1394,
1398	ARM_VLD1d32Qwb_fixed	= 1396,
1399	ARM_VLD1d32Qwb_register	= 1397,
1400	ARM_VLD1d32T	= 1398,
1401	ARM_VLD1d32Twb_fixed	= 1400,
1402	ARM_VLD1d32Twb_register	= 1401,
1403	ARM_VLD1d32wb_fixed	= 1402,
1404	ARM_VLD1d32wb_register	= 1403,
1405	ARM_VLD1d64	= 1404,
1406	ARM_VLD1d64Q	= 1405,
1407	ARM_VLD1d64Qwb_fixed	= 1409,
1408	ARM_VLD1d64Qwb_register	= 1410,
1409	ARM_VLD1d64T	= 1411,
1410	ARM_VLD1d64Twb_fixed	= 1415,
1411	ARM_VLD1d64Twb_register	= 1416,
1412	ARM_VLD1d64wb_fixed	= 1417,
1413	ARM_VLD1d64wb_register	= 1418,
1414	ARM_VLD1d8	= 1419,
1415	ARM_VLD1d8Q	= 1420,
1416	ARM_VLD1d8Qwb_fixed	= 1422,
1417	ARM_VLD1d8Qwb_register	= 1423,
1418	ARM_VLD1d8T	= 1424,
1419	ARM_VLD1d8Twb_fixed	= 1426,
1420	ARM_VLD1d8Twb_register	= 1427,
1421	ARM_VLD1d8wb_fixed	= 1428,
1422	ARM_VLD1d8wb_register	= 1429,
1423	ARM_VLD1q16	= 1430,
1424	ARM_VLD1q16wb_fixed	= 1435,
1425	ARM_VLD1q16wb_register	= 1436,
1426	ARM_VLD1q32	= 1437,
1427	ARM_VLD1q32wb_fixed	= 1442,
1428	ARM_VLD1q32wb_register	= 1443,
1429	ARM_VLD1q64	= 1444,
1430	ARM_VLD1q64wb_fixed	= 1449,
1431	ARM_VLD1q64wb_register	= 1450,
1432	ARM_VLD1q8	= 1451,
1433	ARM_VLD1q8wb_fixed	= 1456,
1434	ARM_VLD1q8wb_register	= 1457,
1435	ARM_VLD2DUPd16	= 1458,
1436	ARM_VLD2DUPd16wb_fixed	= 1459,
1437	ARM_VLD2DUPd16wb_register	= 1460,
1438	ARM_VLD2DUPd16x2	= 1461,
1439	ARM_VLD2DUPd16x2wb_fixed	= 1462,
1440	ARM_VLD2DUPd16x2wb_register	= 1463,
1441	ARM_VLD2DUPd32	= 1464,
1442	ARM_VLD2DUPd32wb_fixed	= 1465,
1443	ARM_VLD2DUPd32wb_register	= 1466,
1444	ARM_VLD2DUPd32x2	= 1467,
1445	ARM_VLD2DUPd32x2wb_fixed	= 1468,
1446	ARM_VLD2DUPd32x2wb_register	= 1469,
1447	ARM_VLD2DUPd8	= 1470,
1448	ARM_VLD2DUPd8wb_fixed	= 1471,
1449	ARM_VLD2DUPd8wb_register	= 1472,
1450	ARM_VLD2DUPd8x2	= 1473,
1451	ARM_VLD2DUPd8x2wb_fixed	= 1474,
1452	ARM_VLD2DUPd8x2wb_register	= 1475,
1453	ARM_VLD2LNd16	= 1482,
1454	ARM_VLD2LNd16_UPD	= 1485,
1455	ARM_VLD2LNd32	= 1486,
1456	ARM_VLD2LNd32_UPD	= 1489,
1457	ARM_VLD2LNd8	= 1490,
1458	ARM_VLD2LNd8_UPD	= 1493,
1459	ARM_VLD2LNq16	= 1494,
1460	ARM_VLD2LNq16_UPD	= 1497,
1461	ARM_VLD2LNq32	= 1498,
1462	ARM_VLD2LNq32_UPD	= 1501,
1463	ARM_VLD2b16	= 1502,
1464	ARM_VLD2b16wb_fixed	= 1503,
1465	ARM_VLD2b16wb_register	= 1504,
1466	ARM_VLD2b32	= 1505,
1467	ARM_VLD2b32wb_fixed	= 1506,
1468	ARM_VLD2b32wb_register	= 1507,
1469	ARM_VLD2b8	= 1508,
1470	ARM_VLD2b8wb_fixed	= 1509,
1471	ARM_VLD2b8wb_register	= 1510,
1472	ARM_VLD2d16	= 1511,
1473	ARM_VLD2d16wb_fixed	= 1512,
1474	ARM_VLD2d16wb_register	= 1513,
1475	ARM_VLD2d32	= 1514,
1476	ARM_VLD2d32wb_fixed	= 1515,
1477	ARM_VLD2d32wb_register	= 1516,
1478	ARM_VLD2d8	= 1517,
1479	ARM_VLD2d8wb_fixed	= 1518,
1480	ARM_VLD2d8wb_register	= 1519,
1481	ARM_VLD2q16	= 1520,
1482	ARM_VLD2q16wb_fixed	= 1524,
1483	ARM_VLD2q16wb_register	= 1525,
1484	ARM_VLD2q32	= 1526,
1485	ARM_VLD2q32wb_fixed	= 1530,
1486	ARM_VLD2q32wb_register	= 1531,
1487	ARM_VLD2q8	= 1532,
1488	ARM_VLD2q8wb_fixed	= 1536,
1489	ARM_VLD2q8wb_register	= 1537,
1490	ARM_VLD3DUPd16	= 1538,
1491	ARM_VLD3DUPd16_UPD	= 1541,
1492	ARM_VLD3DUPd32	= 1542,
1493	ARM_VLD3DUPd32_UPD	= 1545,
1494	ARM_VLD3DUPd8	= 1546,
1495	ARM_VLD3DUPd8_UPD	= 1549,
1496	ARM_VLD3DUPq16	= 1550,
1497	ARM_VLD3DUPq16_UPD	= 1553,
1498	ARM_VLD3DUPq32	= 1554,
1499	ARM_VLD3DUPq32_UPD	= 1557,
1500	ARM_VLD3DUPq8	= 1558,
1501	ARM_VLD3DUPq8_UPD	= 1561,
1502	ARM_VLD3LNd16	= 1562,
1503	ARM_VLD3LNd16_UPD	= 1565,
1504	ARM_VLD3LNd32	= 1566,
1505	ARM_VLD3LNd32_UPD	= 1569,
1506	ARM_VLD3LNd8	= 1570,
1507	ARM_VLD3LNd8_UPD	= 1573,
1508	ARM_VLD3LNq16	= 1574,
1509	ARM_VLD3LNq16_UPD	= 1577,
1510	ARM_VLD3LNq32	= 1578,
1511	ARM_VLD3LNq32_UPD	= 1581,
1512	ARM_VLD3d16	= 1582,
1513	ARM_VLD3d16_UPD	= 1585,
1514	ARM_VLD3d32	= 1586,
1515	ARM_VLD3d32_UPD	= 1589,
1516	ARM_VLD3d8	= 1590,
1517	ARM_VLD3d8_UPD	= 1593,
1518	ARM_VLD3q16	= 1594,
1519	ARM_VLD3q16_UPD	= 1596,
1520	ARM_VLD3q32	= 1599,
1521	ARM_VLD3q32_UPD	= 1601,
1522	ARM_VLD3q8	= 1604,
1523	ARM_VLD3q8_UPD	= 1606,
1524	ARM_VLD4DUPd16	= 1609,
1525	ARM_VLD4DUPd16_UPD	= 1612,
1526	ARM_VLD4DUPd32	= 1613,
1527	ARM_VLD4DUPd32_UPD	= 1616,
1528	ARM_VLD4DUPd8	= 1617,
1529	ARM_VLD4DUPd8_UPD	= 1620,
1530	ARM_VLD4DUPq16	= 1621,
1531	ARM_VLD4DUPq16_UPD	= 1624,
1532	ARM_VLD4DUPq32	= 1625,
1533	ARM_VLD4DUPq32_UPD	= 1628,
1534	ARM_VLD4DUPq8	= 1629,
1535	ARM_VLD4DUPq8_UPD	= 1632,
1536	ARM_VLD4LNd16	= 1633,
1537	ARM_VLD4LNd16_UPD	= 1636,
1538	ARM_VLD4LNd32	= 1637,
1539	ARM_VLD4LNd32_UPD	= 1640,
1540	ARM_VLD4LNd8	= 1641,
1541	ARM_VLD4LNd8_UPD	= 1644,
1542	ARM_VLD4LNq16	= 1645,
1543	ARM_VLD4LNq16_UPD	= 1648,
1544	ARM_VLD4LNq32	= 1649,
1545	ARM_VLD4LNq32_UPD	= 1652,
1546	ARM_VLD4d16	= 1653,
1547	ARM_VLD4d16_UPD	= 1656,
1548	ARM_VLD4d32	= 1657,
1549	ARM_VLD4d32_UPD	= 1660,
1550	ARM_VLD4d8	= 1661,
1551	ARM_VLD4d8_UPD	= 1664,
1552	ARM_VLD4q16	= 1665,
1553	ARM_VLD4q16_UPD	= 1667,
1554	ARM_VLD4q32	= 1670,
1555	ARM_VLD4q32_UPD	= 1672,
1556	ARM_VLD4q8	= 1675,
1557	ARM_VLD4q8_UPD	= 1677,
1558	ARM_VLDMDDB_UPD	= 1680,
1559	ARM_VLDMDIA	= 1681,
1560	ARM_VLDMDIA_UPD	= 1682,
1561	ARM_VLDMQIA	= 1683,
1562	ARM_VLDMSDB_UPD	= 1684,
1563	ARM_VLDMSIA	= 1685,
1564	ARM_VLDMSIA_UPD	= 1686,
1565	ARM_VLDRD	= 1687,
1566	ARM_VLDRH	= 1688,
1567	ARM_VLDRS	= 1689,
1568	ARM_VLLDM	= 1690,
1569	ARM_VLSTM	= 1691,
1570	ARM_VMAXNMD	= 1692,
1571	ARM_VMAXNMH	= 1693,
1572	ARM_VMAXNMNDf	= 1694,
1573	ARM_VMAXNMNDh	= 1695,
1574	ARM_VMAXNMNQf	= 1696,
1575	ARM_VMAXNMNQh	= 1697,
1576	ARM_VMAXNMS	= 1698,
1577	ARM_VMAXfd	= 1699,
1578	ARM_VMAXfq	= 1700,
1579	ARM_VMAXhd	= 1701,
1580	ARM_VMAXhq	= 1702,
1581	ARM_VMAXsv16i8	= 1703,
1582	ARM_VMAXsv2i32	= 1704,
1583	ARM_VMAXsv4i16	= 1705,
1584	ARM_VMAXsv4i32	= 1706,
1585	ARM_VMAXsv8i16	= 1707,
1586	ARM_VMAXsv8i8	= 1708,
1587	ARM_VMAXuv16i8	= 1709,
1588	ARM_VMAXuv2i32	= 1710,
1589	ARM_VMAXuv4i16	= 1711,
1590	ARM_VMAXuv4i32	= 1712,
1591	ARM_VMAXuv8i16	= 1713,
1592	ARM_VMAXuv8i8	= 1714,
1593	ARM_VMINNMD	= 1715,
1594	ARM_VMINNMH	= 1716,
1595	ARM_VMINNMNDf	= 1717,
1596	ARM_VMINNMNDh	= 1718,
1597	ARM_VMINNMNQf	= 1719,
1598	ARM_VMINNMNQh	= 1720,
1599	ARM_VMINNMS	= 1721,
1600	ARM_VMINfd	= 1722,
1601	ARM_VMINfq	= 1723,
1602	ARM_VMINhd	= 1724,
1603	ARM_VMINhq	= 1725,
1604	ARM_VMINsv16i8	= 1726,
1605	ARM_VMINsv2i32	= 1727,
1606	ARM_VMINsv4i16	= 1728,
1607	ARM_VMINsv4i32	= 1729,
1608	ARM_VMINsv8i16	= 1730,
1609	ARM_VMINsv8i8	= 1731,
1610	ARM_VMINuv16i8	= 1732,
1611	ARM_VMINuv2i32	= 1733,
1612	ARM_VMINuv4i16	= 1734,
1613	ARM_VMINuv4i32	= 1735,
1614	ARM_VMINuv8i16	= 1736,
1615	ARM_VMINuv8i8	= 1737,
1616	ARM_VMLAD	= 1738,
1617	ARM_VMLAH	= 1739,
1618	ARM_VMLALslsv2i32	= 1740,
1619	ARM_VMLALslsv4i16	= 1741,
1620	ARM_VMLALsluv2i32	= 1742,
1621	ARM_VMLALsluv4i16	= 1743,
1622	ARM_VMLALsv2i64	= 1744,
1623	ARM_VMLALsv4i32	= 1745,
1624	ARM_VMLALsv8i16	= 1746,
1625	ARM_VMLALuv2i64	= 1747,
1626	ARM_VMLALuv4i32	= 1748,
1627	ARM_VMLALuv8i16	= 1749,
1628	ARM_VMLAS	= 1750,
1629	ARM_VMLAfd	= 1751,
1630	ARM_VMLAfq	= 1752,
1631	ARM_VMLAhd	= 1753,
1632	ARM_VMLAhq	= 1754,
1633	ARM_VMLAslfd	= 1755,
1634	ARM_VMLAslfq	= 1756,
1635	ARM_VMLAslhd	= 1757,
1636	ARM_VMLAslhq	= 1758,
1637	ARM_VMLAslv2i32	= 1759,
1638	ARM_VMLAslv4i16	= 1760,
1639	ARM_VMLAslv4i32	= 1761,
1640	ARM_VMLAslv8i16	= 1762,
1641	ARM_VMLAv16i8	= 1763,
1642	ARM_VMLAv2i32	= 1764,
1643	ARM_VMLAv4i16	= 1765,
1644	ARM_VMLAv4i32	= 1766,
1645	ARM_VMLAv8i16	= 1767,
1646	ARM_VMLAv8i8	= 1768,
1647	ARM_VMLSD	= 1769,
1648	ARM_VMLSH	= 1770,
1649	ARM_VMLSLslsv2i32	= 1771,
1650	ARM_VMLSLslsv4i16	= 1772,
1651	ARM_VMLSLsluv2i32	= 1773,
1652	ARM_VMLSLsluv4i16	= 1774,
1653	ARM_VMLSLsv2i64	= 1775,
1654	ARM_VMLSLsv4i32	= 1776,
1655	ARM_VMLSLsv8i16	= 1777,
1656	ARM_VMLSLuv2i64	= 1778,
1657	ARM_VMLSLuv4i32	= 1779,
1658	ARM_VMLSLuv8i16	= 1780,
1659	ARM_VMLSS	= 1781,
1660	ARM_VMLSfd	= 1782,
1661	ARM_VMLSfq	= 1783,
1662	ARM_VMLShd	= 1784,
1663	ARM_VMLShq	= 1785,
1664	ARM_VMLSslfd	= 1786,
1665	ARM_VMLSslfq	= 1787,
1666	ARM_VMLSslhd	= 1788,
1667	ARM_VMLSslhq	= 1789,
1668	ARM_VMLSslv2i32	= 1790,
1669	ARM_VMLSslv4i16	= 1791,
1670	ARM_VMLSslv4i32	= 1792,
1671	ARM_VMLSslv8i16	= 1793,
1672	ARM_VMLSv16i8	= 1794,
1673	ARM_VMLSv2i32	= 1795,
1674	ARM_VMLSv4i16	= 1796,
1675	ARM_VMLSv4i32	= 1797,
1676	ARM_VMLSv8i16	= 1798,
1677	ARM_VMLSv8i8	= 1799,
1678	ARM_VMOVD	= 1800,
1679	ARM_VMOVDRR	= 1801,
1680	ARM_VMOVH	= 1802,
1681	ARM_VMOVHR	= 1803,
1682	ARM_VMOVLsv2i64	= 1804,
1683	ARM_VMOVLsv4i32	= 1805,
1684	ARM_VMOVLsv8i16	= 1806,
1685	ARM_VMOVLuv2i64	= 1807,
1686	ARM_VMOVLuv4i32	= 1808,
1687	ARM_VMOVLuv8i16	= 1809,
1688	ARM_VMOVNv2i32	= 1810,
1689	ARM_VMOVNv4i16	= 1811,
1690	ARM_VMOVNv8i8	= 1812,
1691	ARM_VMOVRH	= 1813,
1692	ARM_VMOVRRD	= 1814,
1693	ARM_VMOVRRS	= 1815,
1694	ARM_VMOVRS	= 1816,
1695	ARM_VMOVS	= 1817,
1696	ARM_VMOVSR	= 1818,
1697	ARM_VMOVSRR	= 1819,
1698	ARM_VMOVv16i8	= 1820,
1699	ARM_VMOVv1i64	= 1821,
1700	ARM_VMOVv2f32	= 1822,
1701	ARM_VMOVv2i32	= 1823,
1702	ARM_VMOVv2i64	= 1824,
1703	ARM_VMOVv4f32	= 1825,
1704	ARM_VMOVv4i16	= 1826,
1705	ARM_VMOVv4i32	= 1827,
1706	ARM_VMOVv8i16	= 1828,
1707	ARM_VMOVv8i8	= 1829,
1708	ARM_VMRS	= 1830,
1709	ARM_VMRS_FPEXC	= 1831,
1710	ARM_VMRS_FPINST	= 1832,
1711	ARM_VMRS_FPINST2	= 1833,
1712	ARM_VMRS_FPSID	= 1834,
1713	ARM_VMRS_MVFR0	= 1835,
1714	ARM_VMRS_MVFR1	= 1836,
1715	ARM_VMRS_MVFR2	= 1837,
1716	ARM_VMSR	= 1838,
1717	ARM_VMSR_FPEXC	= 1839,
1718	ARM_VMSR_FPINST	= 1840,
1719	ARM_VMSR_FPINST2	= 1841,
1720	ARM_VMSR_FPSID	= 1842,
1721	ARM_VMULD	= 1843,
1722	ARM_VMULH	= 1844,
1723	ARM_VMULLp64	= 1845,
1724	ARM_VMULLp8	= 1846,
1725	ARM_VMULLslsv2i32	= 1847,
1726	ARM_VMULLslsv4i16	= 1848,
1727	ARM_VMULLsluv2i32	= 1849,
1728	ARM_VMULLsluv4i16	= 1850,
1729	ARM_VMULLsv2i64	= 1851,
1730	ARM_VMULLsv4i32	= 1852,
1731	ARM_VMULLsv8i16	= 1853,
1732	ARM_VMULLuv2i64	= 1854,
1733	ARM_VMULLuv4i32	= 1855,
1734	ARM_VMULLuv8i16	= 1856,
1735	ARM_VMULS	= 1857,
1736	ARM_VMULfd	= 1858,
1737	ARM_VMULfq	= 1859,
1738	ARM_VMULhd	= 1860,
1739	ARM_VMULhq	= 1861,
1740	ARM_VMULpd	= 1862,
1741	ARM_VMULpq	= 1863,
1742	ARM_VMULslfd	= 1864,
1743	ARM_VMULslfq	= 1865,
1744	ARM_VMULslhd	= 1866,
1745	ARM_VMULslhq	= 1867,
1746	ARM_VMULslv2i32	= 1868,
1747	ARM_VMULslv4i16	= 1869,
1748	ARM_VMULslv4i32	= 1870,
1749	ARM_VMULslv8i16	= 1871,
1750	ARM_VMULv16i8	= 1872,
1751	ARM_VMULv2i32	= 1873,
1752	ARM_VMULv4i16	= 1874,
1753	ARM_VMULv4i32	= 1875,
1754	ARM_VMULv8i16	= 1876,
1755	ARM_VMULv8i8	= 1877,
1756	ARM_VMVNd	= 1878,
1757	ARM_VMVNq	= 1879,
1758	ARM_VMVNv2i32	= 1880,
1759	ARM_VMVNv4i16	= 1881,
1760	ARM_VMVNv4i32	= 1882,
1761	ARM_VMVNv8i16	= 1883,
1762	ARM_VNEGD	= 1884,
1763	ARM_VNEGH	= 1885,
1764	ARM_VNEGS	= 1886,
1765	ARM_VNEGf32q	= 1887,
1766	ARM_VNEGfd	= 1888,
1767	ARM_VNEGhd	= 1889,
1768	ARM_VNEGhq	= 1890,
1769	ARM_VNEGs16d	= 1891,
1770	ARM_VNEGs16q	= 1892,
1771	ARM_VNEGs32d	= 1893,
1772	ARM_VNEGs32q	= 1894,
1773	ARM_VNEGs8d	= 1895,
1774	ARM_VNEGs8q	= 1896,
1775	ARM_VNMLAD	= 1897,
1776	ARM_VNMLAH	= 1898,
1777	ARM_VNMLAS	= 1899,
1778	ARM_VNMLSD	= 1900,
1779	ARM_VNMLSH	= 1901,
1780	ARM_VNMLSS	= 1902,
1781	ARM_VNMULD	= 1903,
1782	ARM_VNMULH	= 1904,
1783	ARM_VNMULS	= 1905,
1784	ARM_VORNd	= 1906,
1785	ARM_VORNq	= 1907,
1786	ARM_VORRd	= 1908,
1787	ARM_VORRiv2i32	= 1909,
1788	ARM_VORRiv4i16	= 1910,
1789	ARM_VORRiv4i32	= 1911,
1790	ARM_VORRiv8i16	= 1912,
1791	ARM_VORRq	= 1913,
1792	ARM_VPADALsv16i8	= 1914,
1793	ARM_VPADALsv2i32	= 1915,
1794	ARM_VPADALsv4i16	= 1916,
1795	ARM_VPADALsv4i32	= 1917,
1796	ARM_VPADALsv8i16	= 1918,
1797	ARM_VPADALsv8i8	= 1919,
1798	ARM_VPADALuv16i8	= 1920,
1799	ARM_VPADALuv2i32	= 1921,
1800	ARM_VPADALuv4i16	= 1922,
1801	ARM_VPADALuv4i32	= 1923,
1802	ARM_VPADALuv8i16	= 1924,
1803	ARM_VPADALuv8i8	= 1925,
1804	ARM_VPADDLsv16i8	= 1926,
1805	ARM_VPADDLsv2i32	= 1927,
1806	ARM_VPADDLsv4i16	= 1928,
1807	ARM_VPADDLsv4i32	= 1929,
1808	ARM_VPADDLsv8i16	= 1930,
1809	ARM_VPADDLsv8i8	= 1931,
1810	ARM_VPADDLuv16i8	= 1932,
1811	ARM_VPADDLuv2i32	= 1933,
1812	ARM_VPADDLuv4i16	= 1934,
1813	ARM_VPADDLuv4i32	= 1935,
1814	ARM_VPADDLuv8i16	= 1936,
1815	ARM_VPADDLuv8i8	= 1937,
1816	ARM_VPADDf	= 1938,
1817	ARM_VPADDh	= 1939,
1818	ARM_VPADDi16	= 1940,
1819	ARM_VPADDi32	= 1941,
1820	ARM_VPADDi8	= 1942,
1821	ARM_VPMAXf	= 1943,
1822	ARM_VPMAXh	= 1944,
1823	ARM_VPMAXs16	= 1945,
1824	ARM_VPMAXs32	= 1946,
1825	ARM_VPMAXs8	= 1947,
1826	ARM_VPMAXu16	= 1948,
1827	ARM_VPMAXu32	= 1949,
1828	ARM_VPMAXu8	= 1950,
1829	ARM_VPMINf	= 1951,
1830	ARM_VPMINh	= 1952,
1831	ARM_VPMINs16	= 1953,
1832	ARM_VPMINs32	= 1954,
1833	ARM_VPMINs8	= 1955,
1834	ARM_VPMINu16	= 1956,
1835	ARM_VPMINu32	= 1957,
1836	ARM_VPMINu8	= 1958,
1837	ARM_VQABSv16i8	= 1959,
1838	ARM_VQABSv2i32	= 1960,
1839	ARM_VQABSv4i16	= 1961,
1840	ARM_VQABSv4i32	= 1962,
1841	ARM_VQABSv8i16	= 1963,
1842	ARM_VQABSv8i8	= 1964,
1843	ARM_VQADDsv16i8	= 1965,
1844	ARM_VQADDsv1i64	= 1966,
1845	ARM_VQADDsv2i32	= 1967,
1846	ARM_VQADDsv2i64	= 1968,
1847	ARM_VQADDsv4i16	= 1969,
1848	ARM_VQADDsv4i32	= 1970,
1849	ARM_VQADDsv8i16	= 1971,
1850	ARM_VQADDsv8i8	= 1972,
1851	ARM_VQADDuv16i8	= 1973,
1852	ARM_VQADDuv1i64	= 1974,
1853	ARM_VQADDuv2i32	= 1975,
1854	ARM_VQADDuv2i64	= 1976,
1855	ARM_VQADDuv4i16	= 1977,
1856	ARM_VQADDuv4i32	= 1978,
1857	ARM_VQADDuv8i16	= 1979,
1858	ARM_VQADDuv8i8	= 1980,
1859	ARM_VQDMLALslv2i32	= 1981,
1860	ARM_VQDMLALslv4i16	= 1982,
1861	ARM_VQDMLALv2i64	= 1983,
1862	ARM_VQDMLALv4i32	= 1984,
1863	ARM_VQDMLSLslv2i32	= 1985,
1864	ARM_VQDMLSLslv4i16	= 1986,
1865	ARM_VQDMLSLv2i64	= 1987,
1866	ARM_VQDMLSLv4i32	= 1988,
1867	ARM_VQDMULHslv2i32	= 1989,
1868	ARM_VQDMULHslv4i16	= 1990,
1869	ARM_VQDMULHslv4i32	= 1991,
1870	ARM_VQDMULHslv8i16	= 1992,
1871	ARM_VQDMULHv2i32	= 1993,
1872	ARM_VQDMULHv4i16	= 1994,
1873	ARM_VQDMULHv4i32	= 1995,
1874	ARM_VQDMULHv8i16	= 1996,
1875	ARM_VQDMULLslv2i32	= 1997,
1876	ARM_VQDMULLslv4i16	= 1998,
1877	ARM_VQDMULLv2i64	= 1999,
1878	ARM_VQDMULLv4i32	= 2000,
1879	ARM_VQMOVNsuv2i32	= 2001,
1880	ARM_VQMOVNsuv4i16	= 2002,
1881	ARM_VQMOVNsuv8i8	= 2003,
1882	ARM_VQMOVNsv2i32	= 2004,
1883	ARM_VQMOVNsv4i16	= 2005,
1884	ARM_VQMOVNsv8i8	= 2006,
1885	ARM_VQMOVNuv2i32	= 2007,
1886	ARM_VQMOVNuv4i16	= 2008,
1887	ARM_VQMOVNuv8i8	= 2009,
1888	ARM_VQNEGv16i8	= 2010,
1889	ARM_VQNEGv2i32	= 2011,
1890	ARM_VQNEGv4i16	= 2012,
1891	ARM_VQNEGv4i32	= 2013,
1892	ARM_VQNEGv8i16	= 2014,
1893	ARM_VQNEGv8i8	= 2015,
1894	ARM_VQRDMLAHslv2i32	= 2016,
1895	ARM_VQRDMLAHslv4i16	= 2017,
1896	ARM_VQRDMLAHslv4i32	= 2018,
1897	ARM_VQRDMLAHslv8i16	= 2019,
1898	ARM_VQRDMLAHv2i32	= 2020,
1899	ARM_VQRDMLAHv4i16	= 2021,
1900	ARM_VQRDMLAHv4i32	= 2022,
1901	ARM_VQRDMLAHv8i16	= 2023,
1902	ARM_VQRDMLSHslv2i32	= 2024,
1903	ARM_VQRDMLSHslv4i16	= 2025,
1904	ARM_VQRDMLSHslv4i32	= 2026,
1905	ARM_VQRDMLSHslv8i16	= 2027,
1906	ARM_VQRDMLSHv2i32	= 2028,
1907	ARM_VQRDMLSHv4i16	= 2029,
1908	ARM_VQRDMLSHv4i32	= 2030,
1909	ARM_VQRDMLSHv8i16	= 2031,
1910	ARM_VQRDMULHslv2i32	= 2032,
1911	ARM_VQRDMULHslv4i16	= 2033,
1912	ARM_VQRDMULHslv4i32	= 2034,
1913	ARM_VQRDMULHslv8i16	= 2035,
1914	ARM_VQRDMULHv2i32	= 2036,
1915	ARM_VQRDMULHv4i16	= 2037,
1916	ARM_VQRDMULHv4i32	= 2038,
1917	ARM_VQRDMULHv8i16	= 2039,
1918	ARM_VQRSHLsv16i8	= 2040,
1919	ARM_VQRSHLsv1i64	= 2041,
1920	ARM_VQRSHLsv2i32	= 2042,
1921	ARM_VQRSHLsv2i64	= 2043,
1922	ARM_VQRSHLsv4i16	= 2044,
1923	ARM_VQRSHLsv4i32	= 2045,
1924	ARM_VQRSHLsv8i16	= 2046,
1925	ARM_VQRSHLsv8i8	= 2047,
1926	ARM_VQRSHLuv16i8	= 2048,
1927	ARM_VQRSHLuv1i64	= 2049,
1928	ARM_VQRSHLuv2i32	= 2050,
1929	ARM_VQRSHLuv2i64	= 2051,
1930	ARM_VQRSHLuv4i16	= 2052,
1931	ARM_VQRSHLuv4i32	= 2053,
1932	ARM_VQRSHLuv8i16	= 2054,
1933	ARM_VQRSHLuv8i8	= 2055,
1934	ARM_VQRSHRNsv2i32	= 2056,
1935	ARM_VQRSHRNsv4i16	= 2057,
1936	ARM_VQRSHRNsv8i8	= 2058,
1937	ARM_VQRSHRNuv2i32	= 2059,
1938	ARM_VQRSHRNuv4i16	= 2060,
1939	ARM_VQRSHRNuv8i8	= 2061,
1940	ARM_VQRSHRUNv2i32	= 2062,
1941	ARM_VQRSHRUNv4i16	= 2063,
1942	ARM_VQRSHRUNv8i8	= 2064,
1943	ARM_VQSHLsiv16i8	= 2065,
1944	ARM_VQSHLsiv1i64	= 2066,
1945	ARM_VQSHLsiv2i32	= 2067,
1946	ARM_VQSHLsiv2i64	= 2068,
1947	ARM_VQSHLsiv4i16	= 2069,
1948	ARM_VQSHLsiv4i32	= 2070,
1949	ARM_VQSHLsiv8i16	= 2071,
1950	ARM_VQSHLsiv8i8	= 2072,
1951	ARM_VQSHLsuv16i8	= 2073,
1952	ARM_VQSHLsuv1i64	= 2074,
1953	ARM_VQSHLsuv2i32	= 2075,
1954	ARM_VQSHLsuv2i64	= 2076,
1955	ARM_VQSHLsuv4i16	= 2077,
1956	ARM_VQSHLsuv4i32	= 2078,
1957	ARM_VQSHLsuv8i16	= 2079,
1958	ARM_VQSHLsuv8i8	= 2080,
1959	ARM_VQSHLsv16i8	= 2081,
1960	ARM_VQSHLsv1i64	= 2082,
1961	ARM_VQSHLsv2i32	= 2083,
1962	ARM_VQSHLsv2i64	= 2084,
1963	ARM_VQSHLsv4i16	= 2085,
1964	ARM_VQSHLsv4i32	= 2086,
1965	ARM_VQSHLsv8i16	= 2087,
1966	ARM_VQSHLsv8i8	= 2088,
1967	ARM_VQSHLuiv16i8	= 2089,
1968	ARM_VQSHLuiv1i64	= 2090,
1969	ARM_VQSHLuiv2i32	= 2091,
1970	ARM_VQSHLuiv2i64	= 2092,
1971	ARM_VQSHLuiv4i16	= 2093,
1972	ARM_VQSHLuiv4i32	= 2094,
1973	ARM_VQSHLuiv8i16	= 2095,
1974	ARM_VQSHLuiv8i8	= 2096,
1975	ARM_VQSHLuv16i8	= 2097,
1976	ARM_VQSHLuv1i64	= 2098,
1977	ARM_VQSHLuv2i32	= 2099,
1978	ARM_VQSHLuv2i64	= 2100,
1979	ARM_VQSHLuv4i16	= 2101,
1980	ARM_VQSHLuv4i32	= 2102,
1981	ARM_VQSHLuv8i16	= 2103,
1982	ARM_VQSHLuv8i8	= 2104,
1983	ARM_VQSHRNsv2i32	= 2105,
1984	ARM_VQSHRNsv4i16	= 2106,
1985	ARM_VQSHRNsv8i8	= 2107,
1986	ARM_VQSHRNuv2i32	= 2108,
1987	ARM_VQSHRNuv4i16	= 2109,
1988	ARM_VQSHRNuv8i8	= 2110,
1989	ARM_VQSHRUNv2i32	= 2111,
1990	ARM_VQSHRUNv4i16	= 2112,
1991	ARM_VQSHRUNv8i8	= 2113,
1992	ARM_VQSUBsv16i8	= 2114,
1993	ARM_VQSUBsv1i64	= 2115,
1994	ARM_VQSUBsv2i32	= 2116,
1995	ARM_VQSUBsv2i64	= 2117,
1996	ARM_VQSUBsv4i16	= 2118,
1997	ARM_VQSUBsv4i32	= 2119,
1998	ARM_VQSUBsv8i16	= 2120,
1999	ARM_VQSUBsv8i8	= 2121,
2000	ARM_VQSUBuv16i8	= 2122,
2001	ARM_VQSUBuv1i64	= 2123,
2002	ARM_VQSUBuv2i32	= 2124,
2003	ARM_VQSUBuv2i64	= 2125,
2004	ARM_VQSUBuv4i16	= 2126,
2005	ARM_VQSUBuv4i32	= 2127,
2006	ARM_VQSUBuv8i16	= 2128,
2007	ARM_VQSUBuv8i8	= 2129,
2008	ARM_VRADDHNv2i32	= 2130,
2009	ARM_VRADDHNv4i16	= 2131,
2010	ARM_VRADDHNv8i8	= 2132,
2011	ARM_VRECPEd	= 2133,
2012	ARM_VRECPEfd	= 2134,
2013	ARM_VRECPEfq	= 2135,
2014	ARM_VRECPEhd	= 2136,
2015	ARM_VRECPEhq	= 2137,
2016	ARM_VRECPEq	= 2138,
2017	ARM_VRECPSfd	= 2139,
2018	ARM_VRECPSfq	= 2140,
2019	ARM_VRECPShd	= 2141,
2020	ARM_VRECPShq	= 2142,
2021	ARM_VREV16d8	= 2143,
2022	ARM_VREV16q8	= 2144,
2023	ARM_VREV32d16	= 2145,
2024	ARM_VREV32d8	= 2146,
2025	ARM_VREV32q16	= 2147,
2026	ARM_VREV32q8	= 2148,
2027	ARM_VREV64d16	= 2149,
2028	ARM_VREV64d32	= 2150,
2029	ARM_VREV64d8	= 2151,
2030	ARM_VREV64q16	= 2152,
2031	ARM_VREV64q32	= 2153,
2032	ARM_VREV64q8	= 2154,
2033	ARM_VRHADDsv16i8	= 2155,
2034	ARM_VRHADDsv2i32	= 2156,
2035	ARM_VRHADDsv4i16	= 2157,
2036	ARM_VRHADDsv4i32	= 2158,
2037	ARM_VRHADDsv8i16	= 2159,
2038	ARM_VRHADDsv8i8	= 2160,
2039	ARM_VRHADDuv16i8	= 2161,
2040	ARM_VRHADDuv2i32	= 2162,
2041	ARM_VRHADDuv4i16	= 2163,
2042	ARM_VRHADDuv4i32	= 2164,
2043	ARM_VRHADDuv8i16	= 2165,
2044	ARM_VRHADDuv8i8	= 2166,
2045	ARM_VRINTAD	= 2167,
2046	ARM_VRINTAH	= 2168,
2047	ARM_VRINTANDf	= 2169,
2048	ARM_VRINTANDh	= 2170,
2049	ARM_VRINTANQf	= 2171,
2050	ARM_VRINTANQh	= 2172,
2051	ARM_VRINTAS	= 2173,
2052	ARM_VRINTMD	= 2174,
2053	ARM_VRINTMH	= 2175,
2054	ARM_VRINTMNDf	= 2176,
2055	ARM_VRINTMNDh	= 2177,
2056	ARM_VRINTMNQf	= 2178,
2057	ARM_VRINTMNQh	= 2179,
2058	ARM_VRINTMS	= 2180,
2059	ARM_VRINTND	= 2181,
2060	ARM_VRINTNH	= 2182,
2061	ARM_VRINTNNDf	= 2183,
2062	ARM_VRINTNNDh	= 2184,
2063	ARM_VRINTNNQf	= 2185,
2064	ARM_VRINTNNQh	= 2186,
2065	ARM_VRINTNS	= 2187,
2066	ARM_VRINTPD	= 2188,
2067	ARM_VRINTPH	= 2189,
2068	ARM_VRINTPNDf	= 2190,
2069	ARM_VRINTPNDh	= 2191,
2070	ARM_VRINTPNQf	= 2192,
2071	ARM_VRINTPNQh	= 2193,
2072	ARM_VRINTPS	= 2194,
2073	ARM_VRINTRD	= 2195,
2074	ARM_VRINTRH	= 2196,
2075	ARM_VRINTRS	= 2197,
2076	ARM_VRINTXD	= 2198,
2077	ARM_VRINTXH	= 2199,
2078	ARM_VRINTXNDf	= 2200,
2079	ARM_VRINTXNDh	= 2201,
2080	ARM_VRINTXNQf	= 2202,
2081	ARM_VRINTXNQh	= 2203,
2082	ARM_VRINTXS	= 2204,
2083	ARM_VRINTZD	= 2205,
2084	ARM_VRINTZH	= 2206,
2085	ARM_VRINTZNDf	= 2207,
2086	ARM_VRINTZNDh	= 2208,
2087	ARM_VRINTZNQf	= 2209,
2088	ARM_VRINTZNQh	= 2210,
2089	ARM_VRINTZS	= 2211,
2090	ARM_VRSHLsv16i8	= 2212,
2091	ARM_VRSHLsv1i64	= 2213,
2092	ARM_VRSHLsv2i32	= 2214,
2093	ARM_VRSHLsv2i64	= 2215,
2094	ARM_VRSHLsv4i16	= 2216,
2095	ARM_VRSHLsv4i32	= 2217,
2096	ARM_VRSHLsv8i16	= 2218,
2097	ARM_VRSHLsv8i8	= 2219,
2098	ARM_VRSHLuv16i8	= 2220,
2099	ARM_VRSHLuv1i64	= 2221,
2100	ARM_VRSHLuv2i32	= 2222,
2101	ARM_VRSHLuv2i64	= 2223,
2102	ARM_VRSHLuv4i16	= 2224,
2103	ARM_VRSHLuv4i32	= 2225,
2104	ARM_VRSHLuv8i16	= 2226,
2105	ARM_VRSHLuv8i8	= 2227,
2106	ARM_VRSHRNv2i32	= 2228,
2107	ARM_VRSHRNv4i16	= 2229,
2108	ARM_VRSHRNv8i8	= 2230,
2109	ARM_VRSHRsv16i8	= 2231,
2110	ARM_VRSHRsv1i64	= 2232,
2111	ARM_VRSHRsv2i32	= 2233,
2112	ARM_VRSHRsv2i64	= 2234,
2113	ARM_VRSHRsv4i16	= 2235,
2114	ARM_VRSHRsv4i32	= 2236,
2115	ARM_VRSHRsv8i16	= 2237,
2116	ARM_VRSHRsv8i8	= 2238,
2117	ARM_VRSHRuv16i8	= 2239,
2118	ARM_VRSHRuv1i64	= 2240,
2119	ARM_VRSHRuv2i32	= 2241,
2120	ARM_VRSHRuv2i64	= 2242,
2121	ARM_VRSHRuv4i16	= 2243,
2122	ARM_VRSHRuv4i32	= 2244,
2123	ARM_VRSHRuv8i16	= 2245,
2124	ARM_VRSHRuv8i8	= 2246,
2125	ARM_VRSQRTEd	= 2247,
2126	ARM_VRSQRTEfd	= 2248,
2127	ARM_VRSQRTEfq	= 2249,
2128	ARM_VRSQRTEhd	= 2250,
2129	ARM_VRSQRTEhq	= 2251,
2130	ARM_VRSQRTEq	= 2252,
2131	ARM_VRSQRTSfd	= 2253,
2132	ARM_VRSQRTSfq	= 2254,
2133	ARM_VRSQRTShd	= 2255,
2134	ARM_VRSQRTShq	= 2256,
2135	ARM_VRSRAsv16i8	= 2257,
2136	ARM_VRSRAsv1i64	= 2258,
2137	ARM_VRSRAsv2i32	= 2259,
2138	ARM_VRSRAsv2i64	= 2260,
2139	ARM_VRSRAsv4i16	= 2261,
2140	ARM_VRSRAsv4i32	= 2262,
2141	ARM_VRSRAsv8i16	= 2263,
2142	ARM_VRSRAsv8i8	= 2264,
2143	ARM_VRSRAuv16i8	= 2265,
2144	ARM_VRSRAuv1i64	= 2266,
2145	ARM_VRSRAuv2i32	= 2267,
2146	ARM_VRSRAuv2i64	= 2268,
2147	ARM_VRSRAuv4i16	= 2269,
2148	ARM_VRSRAuv4i32	= 2270,
2149	ARM_VRSRAuv8i16	= 2271,
2150	ARM_VRSRAuv8i8	= 2272,
2151	ARM_VRSUBHNv2i32	= 2273,
2152	ARM_VRSUBHNv4i16	= 2274,
2153	ARM_VRSUBHNv8i8	= 2275,
2154	ARM_VSDOTD	= 2276,
2155	ARM_VSDOTDI	= 2277,
2156	ARM_VSDOTQ	= 2278,
2157	ARM_VSDOTQI	= 2279,
2158	ARM_VSELEQD	= 2280,
2159	ARM_VSELEQH	= 2281,
2160	ARM_VSELEQS	= 2282,
2161	ARM_VSELGED	= 2283,
2162	ARM_VSELGEH	= 2284,
2163	ARM_VSELGES	= 2285,
2164	ARM_VSELGTD	= 2286,
2165	ARM_VSELGTH	= 2287,
2166	ARM_VSELGTS	= 2288,
2167	ARM_VSELVSD	= 2289,
2168	ARM_VSELVSH	= 2290,
2169	ARM_VSELVSS	= 2291,
2170	ARM_VSETLNi16	= 2292,
2171	ARM_VSETLNi32	= 2293,
2172	ARM_VSETLNi8	= 2294,
2173	ARM_VSHLLi16	= 2295,
2174	ARM_VSHLLi32	= 2296,
2175	ARM_VSHLLi8	= 2297,
2176	ARM_VSHLLsv2i64	= 2298,
2177	ARM_VSHLLsv4i32	= 2299,
2178	ARM_VSHLLsv8i16	= 2300,
2179	ARM_VSHLLuv2i64	= 2301,
2180	ARM_VSHLLuv4i32	= 2302,
2181	ARM_VSHLLuv8i16	= 2303,
2182	ARM_VSHLiv16i8	= 2304,
2183	ARM_VSHLiv1i64	= 2305,
2184	ARM_VSHLiv2i32	= 2306,
2185	ARM_VSHLiv2i64	= 2307,
2186	ARM_VSHLiv4i16	= 2308,
2187	ARM_VSHLiv4i32	= 2309,
2188	ARM_VSHLiv8i16	= 2310,
2189	ARM_VSHLiv8i8	= 2311,
2190	ARM_VSHLsv16i8	= 2312,
2191	ARM_VSHLsv1i64	= 2313,
2192	ARM_VSHLsv2i32	= 2314,
2193	ARM_VSHLsv2i64	= 2315,
2194	ARM_VSHLsv4i16	= 2316,
2195	ARM_VSHLsv4i32	= 2317,
2196	ARM_VSHLsv8i16	= 2318,
2197	ARM_VSHLsv8i8	= 2319,
2198	ARM_VSHLuv16i8	= 2320,
2199	ARM_VSHLuv1i64	= 2321,
2200	ARM_VSHLuv2i32	= 2322,
2201	ARM_VSHLuv2i64	= 2323,
2202	ARM_VSHLuv4i16	= 2324,
2203	ARM_VSHLuv4i32	= 2325,
2204	ARM_VSHLuv8i16	= 2326,
2205	ARM_VSHLuv8i8	= 2327,
2206	ARM_VSHRNv2i32	= 2328,
2207	ARM_VSHRNv4i16	= 2329,
2208	ARM_VSHRNv8i8	= 2330,
2209	ARM_VSHRsv16i8	= 2331,
2210	ARM_VSHRsv1i64	= 2332,
2211	ARM_VSHRsv2i32	= 2333,
2212	ARM_VSHRsv2i64	= 2334,
2213	ARM_VSHRsv4i16	= 2335,
2214	ARM_VSHRsv4i32	= 2336,
2215	ARM_VSHRsv8i16	= 2337,
2216	ARM_VSHRsv8i8	= 2338,
2217	ARM_VSHRuv16i8	= 2339,
2218	ARM_VSHRuv1i64	= 2340,
2219	ARM_VSHRuv2i32	= 2341,
2220	ARM_VSHRuv2i64	= 2342,
2221	ARM_VSHRuv4i16	= 2343,
2222	ARM_VSHRuv4i32	= 2344,
2223	ARM_VSHRuv8i16	= 2345,
2224	ARM_VSHRuv8i8	= 2346,
2225	ARM_VSHTOD	= 2347,
2226	ARM_VSHTOH	= 2348,
2227	ARM_VSHTOS	= 2349,
2228	ARM_VSITOD	= 2350,
2229	ARM_VSITOH	= 2351,
2230	ARM_VSITOS	= 2352,
2231	ARM_VSLIv16i8	= 2353,
2232	ARM_VSLIv1i64	= 2354,
2233	ARM_VSLIv2i32	= 2355,
2234	ARM_VSLIv2i64	= 2356,
2235	ARM_VSLIv4i16	= 2357,
2236	ARM_VSLIv4i32	= 2358,
2237	ARM_VSLIv8i16	= 2359,
2238	ARM_VSLIv8i8	= 2360,
2239	ARM_VSLTOD	= 2361,
2240	ARM_VSLTOH	= 2362,
2241	ARM_VSLTOS	= 2363,
2242	ARM_VSQRTD	= 2364,
2243	ARM_VSQRTH	= 2365,
2244	ARM_VSQRTS	= 2366,
2245	ARM_VSRAsv16i8	= 2367,
2246	ARM_VSRAsv1i64	= 2368,
2247	ARM_VSRAsv2i32	= 2369,
2248	ARM_VSRAsv2i64	= 2370,
2249	ARM_VSRAsv4i16	= 2371,
2250	ARM_VSRAsv4i32	= 2372,
2251	ARM_VSRAsv8i16	= 2373,
2252	ARM_VSRAsv8i8	= 2374,
2253	ARM_VSRAuv16i8	= 2375,
2254	ARM_VSRAuv1i64	= 2376,
2255	ARM_VSRAuv2i32	= 2377,
2256	ARM_VSRAuv2i64	= 2378,
2257	ARM_VSRAuv4i16	= 2379,
2258	ARM_VSRAuv4i32	= 2380,
2259	ARM_VSRAuv8i16	= 2381,
2260	ARM_VSRAuv8i8	= 2382,
2261	ARM_VSRIv16i8	= 2383,
2262	ARM_VSRIv1i64	= 2384,
2263	ARM_VSRIv2i32	= 2385,
2264	ARM_VSRIv2i64	= 2386,
2265	ARM_VSRIv4i16	= 2387,
2266	ARM_VSRIv4i32	= 2388,
2267	ARM_VSRIv8i16	= 2389,
2268	ARM_VSRIv8i8	= 2390,
2269	ARM_VST1LNd16	= 2391,
2270	ARM_VST1LNd16_UPD	= 2392,
2271	ARM_VST1LNd32	= 2393,
2272	ARM_VST1LNd32_UPD	= 2394,
2273	ARM_VST1LNd8	= 2395,
2274	ARM_VST1LNd8_UPD	= 2396,
2275	ARM_VST1d16	= 2403,
2276	ARM_VST1d16Q	= 2404,
2277	ARM_VST1d16Qwb_fixed	= 2406,
2278	ARM_VST1d16Qwb_register	= 2407,
2279	ARM_VST1d16T	= 2408,
2280	ARM_VST1d16Twb_fixed	= 2410,
2281	ARM_VST1d16Twb_register	= 2411,
2282	ARM_VST1d16wb_fixed	= 2412,
2283	ARM_VST1d16wb_register	= 2413,
2284	ARM_VST1d32	= 2414,
2285	ARM_VST1d32Q	= 2415,
2286	ARM_VST1d32Qwb_fixed	= 2417,
2287	ARM_VST1d32Qwb_register	= 2418,
2288	ARM_VST1d32T	= 2419,
2289	ARM_VST1d32Twb_fixed	= 2421,
2290	ARM_VST1d32Twb_register	= 2422,
2291	ARM_VST1d32wb_fixed	= 2423,
2292	ARM_VST1d32wb_register	= 2424,
2293	ARM_VST1d64	= 2425,
2294	ARM_VST1d64Q	= 2426,
2295	ARM_VST1d64Qwb_fixed	= 2430,
2296	ARM_VST1d64Qwb_register	= 2431,
2297	ARM_VST1d64T	= 2432,
2298	ARM_VST1d64Twb_fixed	= 2436,
2299	ARM_VST1d64Twb_register	= 2437,
2300	ARM_VST1d64wb_fixed	= 2438,
2301	ARM_VST1d64wb_register	= 2439,
2302	ARM_VST1d8	= 2440,
2303	ARM_VST1d8Q	= 2441,
2304	ARM_VST1d8Qwb_fixed	= 2443,
2305	ARM_VST1d8Qwb_register	= 2444,
2306	ARM_VST1d8T	= 2445,
2307	ARM_VST1d8Twb_fixed	= 2447,
2308	ARM_VST1d8Twb_register	= 2448,
2309	ARM_VST1d8wb_fixed	= 2449,
2310	ARM_VST1d8wb_register	= 2450,
2311	ARM_VST1q16	= 2451,
2312	ARM_VST1q16wb_fixed	= 2456,
2313	ARM_VST1q16wb_register	= 2457,
2314	ARM_VST1q32	= 2458,
2315	ARM_VST1q32wb_fixed	= 2463,
2316	ARM_VST1q32wb_register	= 2464,
2317	ARM_VST1q64	= 2465,
2318	ARM_VST1q64wb_fixed	= 2470,
2319	ARM_VST1q64wb_register	= 2471,
2320	ARM_VST1q8	= 2472,
2321	ARM_VST1q8wb_fixed	= 2477,
2322	ARM_VST1q8wb_register	= 2478,
2323	ARM_VST2LNd16	= 2479,
2324	ARM_VST2LNd16_UPD	= 2482,
2325	ARM_VST2LNd32	= 2483,
2326	ARM_VST2LNd32_UPD	= 2486,
2327	ARM_VST2LNd8	= 2487,
2328	ARM_VST2LNd8_UPD	= 2490,
2329	ARM_VST2LNq16	= 2491,
2330	ARM_VST2LNq16_UPD	= 2494,
2331	ARM_VST2LNq32	= 2495,
2332	ARM_VST2LNq32_UPD	= 2498,
2333	ARM_VST2b16	= 2499,
2334	ARM_VST2b16wb_fixed	= 2500,
2335	ARM_VST2b16wb_register	= 2501,
2336	ARM_VST2b32	= 2502,
2337	ARM_VST2b32wb_fixed	= 2503,
2338	ARM_VST2b32wb_register	= 2504,
2339	ARM_VST2b8	= 2505,
2340	ARM_VST2b8wb_fixed	= 2506,
2341	ARM_VST2b8wb_register	= 2507,
2342	ARM_VST2d16	= 2508,
2343	ARM_VST2d16wb_fixed	= 2509,
2344	ARM_VST2d16wb_register	= 2510,
2345	ARM_VST2d32	= 2511,
2346	ARM_VST2d32wb_fixed	= 2512,
2347	ARM_VST2d32wb_register	= 2513,
2348	ARM_VST2d8	= 2514,
2349	ARM_VST2d8wb_fixed	= 2515,
2350	ARM_VST2d8wb_register	= 2516,
2351	ARM_VST2q16	= 2517,
2352	ARM_VST2q16wb_fixed	= 2521,
2353	ARM_VST2q16wb_register	= 2522,
2354	ARM_VST2q32	= 2523,
2355	ARM_VST2q32wb_fixed	= 2527,
2356	ARM_VST2q32wb_register	= 2528,
2357	ARM_VST2q8	= 2529,
2358	ARM_VST2q8wb_fixed	= 2533,
2359	ARM_VST2q8wb_register	= 2534,
2360	ARM_VST3LNd16	= 2535,
2361	ARM_VST3LNd16_UPD	= 2538,
2362	ARM_VST3LNd32	= 2539,
2363	ARM_VST3LNd32_UPD	= 2542,
2364	ARM_VST3LNd8	= 2543,
2365	ARM_VST3LNd8_UPD	= 2546,
2366	ARM_VST3LNq16	= 2547,
2367	ARM_VST3LNq16_UPD	= 2550,
2368	ARM_VST3LNq32	= 2551,
2369	ARM_VST3LNq32_UPD	= 2554,
2370	ARM_VST3d16	= 2555,
2371	ARM_VST3d16_UPD	= 2558,
2372	ARM_VST3d32	= 2559,
2373	ARM_VST3d32_UPD	= 2562,
2374	ARM_VST3d8	= 2563,
2375	ARM_VST3d8_UPD	= 2566,
2376	ARM_VST3q16	= 2567,
2377	ARM_VST3q16_UPD	= 2569,
2378	ARM_VST3q32	= 2572,
2379	ARM_VST3q32_UPD	= 2574,
2380	ARM_VST3q8	= 2577,
2381	ARM_VST3q8_UPD	= 2579,
2382	ARM_VST4LNd16	= 2582,
2383	ARM_VST4LNd16_UPD	= 2585,
2384	ARM_VST4LNd32	= 2586,
2385	ARM_VST4LNd32_UPD	= 2589,
2386	ARM_VST4LNd8	= 2590,
2387	ARM_VST4LNd8_UPD	= 2593,
2388	ARM_VST4LNq16	= 2594,
2389	ARM_VST4LNq16_UPD	= 2597,
2390	ARM_VST4LNq32	= 2598,
2391	ARM_VST4LNq32_UPD	= 2601,
2392	ARM_VST4d16	= 2602,
2393	ARM_VST4d16_UPD	= 2605,
2394	ARM_VST4d32	= 2606,
2395	ARM_VST4d32_UPD	= 2609,
2396	ARM_VST4d8	= 2610,
2397	ARM_VST4d8_UPD	= 2613,
2398	ARM_VST4q16	= 2614,
2399	ARM_VST4q16_UPD	= 2616,
2400	ARM_VST4q32	= 2619,
2401	ARM_VST4q32_UPD	= 2621,
2402	ARM_VST4q8	= 2624,
2403	ARM_VST4q8_UPD	= 2626,
2404	ARM_VSTMDDB_UPD	= 2629,
2405	ARM_VSTMDIA	= 2630,
2406	ARM_VSTMDIA_UPD	= 2631,
2407	ARM_VSTMQIA	= 2632,
2408	ARM_VSTMSDB_UPD	= 2633,
2409	ARM_VSTMSIA	= 2634,
2410	ARM_VSTMSIA_UPD	= 2635,
2411	ARM_VSTRD	= 2636,
2412	ARM_VSTRH	= 2637,
2413	ARM_VSTRS	= 2638,
2414	ARM_VSUBD	= 2639,
2415	ARM_VSUBH	= 2640,
2416	ARM_VSUBHNv2i32	= 2641,
2417	ARM_VSUBHNv4i16	= 2642,
2418	ARM_VSUBHNv8i8	= 2643,
2419	ARM_VSUBLsv2i64	= 2644,
2420	ARM_VSUBLsv4i32	= 2645,
2421	ARM_VSUBLsv8i16	= 2646,
2422	ARM_VSUBLuv2i64	= 2647,
2423	ARM_VSUBLuv4i32	= 2648,
2424	ARM_VSUBLuv8i16	= 2649,
2425	ARM_VSUBS	= 2650,
2426	ARM_VSUBWsv2i64	= 2651,
2427	ARM_VSUBWsv4i32	= 2652,
2428	ARM_VSUBWsv8i16	= 2653,
2429	ARM_VSUBWuv2i64	= 2654,
2430	ARM_VSUBWuv4i32	= 2655,
2431	ARM_VSUBWuv8i16	= 2656,
2432	ARM_VSUBfd	= 2657,
2433	ARM_VSUBfq	= 2658,
2434	ARM_VSUBhd	= 2659,
2435	ARM_VSUBhq	= 2660,
2436	ARM_VSUBv16i8	= 2661,
2437	ARM_VSUBv1i64	= 2662,
2438	ARM_VSUBv2i32	= 2663,
2439	ARM_VSUBv2i64	= 2664,
2440	ARM_VSUBv4i16	= 2665,
2441	ARM_VSUBv4i32	= 2666,
2442	ARM_VSUBv8i16	= 2667,
2443	ARM_VSUBv8i8	= 2668,
2444	ARM_VSWPd	= 2669,
2445	ARM_VSWPq	= 2670,
2446	ARM_VTBL1	= 2671,
2447	ARM_VTBL2	= 2672,
2448	ARM_VTBL3	= 2673,
2449	ARM_VTBL4	= 2675,
2450	ARM_VTBX1	= 2677,
2451	ARM_VTBX2	= 2678,
2452	ARM_VTBX3	= 2679,
2453	ARM_VTBX4	= 2681,
2454	ARM_VTOSHD	= 2683,
2455	ARM_VTOSHH	= 2684,
2456	ARM_VTOSHS	= 2685,
2457	ARM_VTOSIRD	= 2686,
2458	ARM_VTOSIRH	= 2687,
2459	ARM_VTOSIRS	= 2688,
2460	ARM_VTOSIZD	= 2689,
2461	ARM_VTOSIZH	= 2690,
2462	ARM_VTOSIZS	= 2691,
2463	ARM_VTOSLD	= 2692,
2464	ARM_VTOSLH	= 2693,
2465	ARM_VTOSLS	= 2694,
2466	ARM_VTOUHD	= 2695,
2467	ARM_VTOUHH	= 2696,
2468	ARM_VTOUHS	= 2697,
2469	ARM_VTOUIRD	= 2698,
2470	ARM_VTOUIRH	= 2699,
2471	ARM_VTOUIRS	= 2700,
2472	ARM_VTOUIZD	= 2701,
2473	ARM_VTOUIZH	= 2702,
2474	ARM_VTOUIZS	= 2703,
2475	ARM_VTOULD	= 2704,
2476	ARM_VTOULH	= 2705,
2477	ARM_VTOULS	= 2706,
2478	ARM_VTRNd16	= 2707,
2479	ARM_VTRNd32	= 2708,
2480	ARM_VTRNd8	= 2709,
2481	ARM_VTRNq16	= 2710,
2482	ARM_VTRNq32	= 2711,
2483	ARM_VTRNq8	= 2712,
2484	ARM_VTSTv16i8	= 2713,
2485	ARM_VTSTv2i32	= 2714,
2486	ARM_VTSTv4i16	= 2715,
2487	ARM_VTSTv4i32	= 2716,
2488	ARM_VTSTv8i16	= 2717,
2489	ARM_VTSTv8i8	= 2718,
2490	ARM_VUDOTD	= 2719,
2491	ARM_VUDOTDI	= 2720,
2492	ARM_VUDOTQ	= 2721,
2493	ARM_VUDOTQI	= 2722,
2494	ARM_VUHTOD	= 2723,
2495	ARM_VUHTOH	= 2724,
2496	ARM_VUHTOS	= 2725,
2497	ARM_VUITOD	= 2726,
2498	ARM_VUITOH	= 2727,
2499	ARM_VUITOS	= 2728,
2500	ARM_VULTOD	= 2729,
2501	ARM_VULTOH	= 2730,
2502	ARM_VULTOS	= 2731,
2503	ARM_VUZPd16	= 2732,
2504	ARM_VUZPd8	= 2733,
2505	ARM_VUZPq16	= 2734,
2506	ARM_VUZPq32	= 2735,
2507	ARM_VUZPq8	= 2736,
2508	ARM_VZIPd16	= 2737,
2509	ARM_VZIPd8	= 2738,
2510	ARM_VZIPq16	= 2739,
2511	ARM_VZIPq32	= 2740,
2512	ARM_VZIPq8	= 2741,
2513	ARM_sysLDMDA	= 2742,
2514	ARM_sysLDMDA_UPD	= 2743,
2515	ARM_sysLDMDB	= 2744,
2516	ARM_sysLDMDB_UPD	= 2745,
2517	ARM_sysLDMIA	= 2746,
2518	ARM_sysLDMIA_UPD	= 2747,
2519	ARM_sysLDMIB	= 2748,
2520	ARM_sysLDMIB_UPD	= 2749,
2521	ARM_sysSTMDA	= 2750,
2522	ARM_sysSTMDA_UPD	= 2751,
2523	ARM_sysSTMDB	= 2752,
2524	ARM_sysSTMDB_UPD	= 2753,
2525	ARM_sysSTMIA	= 2754,
2526	ARM_sysSTMIA_UPD	= 2755,
2527	ARM_sysSTMIB	= 2756,
2528	ARM_sysSTMIB_UPD	= 2757,
2529	ARM_t2ADCri	= 2758,
2530	ARM_t2ADCrr	= 2759,
2531	ARM_t2ADCrs	= 2760,
2532	ARM_t2ADDri	= 2761,
2533	ARM_t2ADDri12	= 2762,
2534	ARM_t2ADDrr	= 2763,
2535	ARM_t2ADDrs	= 2764,
2536	ARM_t2ADR	= 2765,
2537	ARM_t2ANDri	= 2766,
2538	ARM_t2ANDrr	= 2767,
2539	ARM_t2ANDrs	= 2768,
2540	ARM_t2ASRri	= 2769,
2541	ARM_t2ASRrr	= 2770,
2542	ARM_t2B	= 2771,
2543	ARM_t2BFC	= 2772,
2544	ARM_t2BFI	= 2773,
2545	ARM_t2BICri	= 2774,
2546	ARM_t2BICrr	= 2775,
2547	ARM_t2BICrs	= 2776,
2548	ARM_t2BXJ	= 2777,
2549	ARM_t2Bcc	= 2778,
2550	ARM_t2CDP	= 2779,
2551	ARM_t2CDP2	= 2780,
2552	ARM_t2CLREX	= 2781,
2553	ARM_t2CLZ	= 2782,
2554	ARM_t2CMNri	= 2783,
2555	ARM_t2CMNzrr	= 2784,
2556	ARM_t2CMNzrs	= 2785,
2557	ARM_t2CMPri	= 2786,
2558	ARM_t2CMPrr	= 2787,
2559	ARM_t2CMPrs	= 2788,
2560	ARM_t2CPS1p	= 2789,
2561	ARM_t2CPS2p	= 2790,
2562	ARM_t2CPS3p	= 2791,
2563	ARM_t2CRC32B	= 2792,
2564	ARM_t2CRC32CB	= 2793,
2565	ARM_t2CRC32CH	= 2794,
2566	ARM_t2CRC32CW	= 2795,
2567	ARM_t2CRC32H	= 2796,
2568	ARM_t2CRC32W	= 2797,
2569	ARM_t2DBG	= 2798,
2570	ARM_t2DCPS1	= 2799,
2571	ARM_t2DCPS2	= 2800,
2572	ARM_t2DCPS3	= 2801,
2573	ARM_t2DMB	= 2802,
2574	ARM_t2DSB	= 2803,
2575	ARM_t2EORri	= 2804,
2576	ARM_t2EORrr	= 2805,
2577	ARM_t2EORrs	= 2806,
2578	ARM_t2HINT	= 2807,
2579	ARM_t2HVC	= 2808,
2580	ARM_t2ISB	= 2809,
2581	ARM_t2IT	= 2810,
2582	ARM_t2LDA	= 2813,
2583	ARM_t2LDAB	= 2814,
2584	ARM_t2LDAEX	= 2815,
2585	ARM_t2LDAEXB	= 2816,
2586	ARM_t2LDAEXD	= 2817,
2587	ARM_t2LDAEXH	= 2818,
2588	ARM_t2LDAH	= 2819,
2589	ARM_t2LDC2L_OFFSET	= 2820,
2590	ARM_t2LDC2L_OPTION	= 2821,
2591	ARM_t2LDC2L_POST	= 2822,
2592	ARM_t2LDC2L_PRE	= 2823,
2593	ARM_t2LDC2_OFFSET	= 2824,
2594	ARM_t2LDC2_OPTION	= 2825,
2595	ARM_t2LDC2_POST	= 2826,
2596	ARM_t2LDC2_PRE	= 2827,
2597	ARM_t2LDCL_OFFSET	= 2828,
2598	ARM_t2LDCL_OPTION	= 2829,
2599	ARM_t2LDCL_POST	= 2830,
2600	ARM_t2LDCL_PRE	= 2831,
2601	ARM_t2LDC_OFFSET	= 2832,
2602	ARM_t2LDC_OPTION	= 2833,
2603	ARM_t2LDC_POST	= 2834,
2604	ARM_t2LDC_PRE	= 2835,
2605	ARM_t2LDMDB	= 2836,
2606	ARM_t2LDMDB_UPD	= 2837,
2607	ARM_t2LDMIA	= 2838,
2608	ARM_t2LDMIA_UPD	= 2839,
2609	ARM_t2LDRBT	= 2840,
2610	ARM_t2LDRB_POST	= 2841,
2611	ARM_t2LDRB_PRE	= 2842,
2612	ARM_t2LDRBi12	= 2843,
2613	ARM_t2LDRBi8	= 2844,
2614	ARM_t2LDRBpci	= 2845,
2615	ARM_t2LDRBs	= 2846,
2616	ARM_t2LDRD_POST	= 2847,
2617	ARM_t2LDRD_PRE	= 2848,
2618	ARM_t2LDRDi8	= 2849,
2619	ARM_t2LDREX	= 2850,
2620	ARM_t2LDREXB	= 2851,
2621	ARM_t2LDREXD	= 2852,
2622	ARM_t2LDREXH	= 2853,
2623	ARM_t2LDRHT	= 2854,
2624	ARM_t2LDRH_POST	= 2855,
2625	ARM_t2LDRH_PRE	= 2856,
2626	ARM_t2LDRHi12	= 2857,
2627	ARM_t2LDRHi8	= 2858,
2628	ARM_t2LDRHpci	= 2859,
2629	ARM_t2LDRHs	= 2860,
2630	ARM_t2LDRSBT	= 2861,
2631	ARM_t2LDRSB_POST	= 2862,
2632	ARM_t2LDRSB_PRE	= 2863,
2633	ARM_t2LDRSBi12	= 2864,
2634	ARM_t2LDRSBi8	= 2865,
2635	ARM_t2LDRSBpci	= 2866,
2636	ARM_t2LDRSBs	= 2867,
2637	ARM_t2LDRSHT	= 2868,
2638	ARM_t2LDRSH_POST	= 2869,
2639	ARM_t2LDRSH_PRE	= 2870,
2640	ARM_t2LDRSHi12	= 2871,
2641	ARM_t2LDRSHi8	= 2872,
2642	ARM_t2LDRSHpci	= 2873,
2643	ARM_t2LDRSHs	= 2874,
2644	ARM_t2LDRT	= 2875,
2645	ARM_t2LDR_POST	= 2876,
2646	ARM_t2LDR_PRE	= 2877,
2647	ARM_t2LDRi12	= 2878,
2648	ARM_t2LDRi8	= 2879,
2649	ARM_t2LDRpci	= 2880,
2650	ARM_t2LDRs	= 2881,
2651	ARM_t2LSLri	= 2882,
2652	ARM_t2LSLrr	= 2883,
2653	ARM_t2LSRri	= 2884,
2654	ARM_t2LSRrr	= 2885,
2655	ARM_t2MCR	= 2886,
2656	ARM_t2MCR2	= 2887,
2657	ARM_t2MCRR	= 2888,
2658	ARM_t2MCRR2	= 2889,
2659	ARM_t2MLA	= 2890,
2660	ARM_t2MLS	= 2891,
2661	ARM_t2MOVTi16	= 2892,
2662	ARM_t2MOVi	= 2893,
2663	ARM_t2MOVi16	= 2894,
2664	ARM_t2MOVr	= 2895,
2665	ARM_t2MOVsra_flag	= 2896,
2666	ARM_t2MOVsrl_flag	= 2897,
2667	ARM_t2MRC	= 2898,
2668	ARM_t2MRC2	= 2899,
2669	ARM_t2MRRC	= 2900,
2670	ARM_t2MRRC2	= 2901,
2671	ARM_t2MRS_AR	= 2902,
2672	ARM_t2MRS_M	= 2903,
2673	ARM_t2MRSbanked	= 2904,
2674	ARM_t2MRSsys_AR	= 2905,
2675	ARM_t2MSR_AR	= 2906,
2676	ARM_t2MSR_M	= 2907,
2677	ARM_t2MSRbanked	= 2908,
2678	ARM_t2MUL	= 2909,
2679	ARM_t2MVNi	= 2910,
2680	ARM_t2MVNr	= 2911,
2681	ARM_t2MVNs	= 2912,
2682	ARM_t2ORNri	= 2913,
2683	ARM_t2ORNrr	= 2914,
2684	ARM_t2ORNrs	= 2915,
2685	ARM_t2ORRri	= 2916,
2686	ARM_t2ORRrr	= 2917,
2687	ARM_t2ORRrs	= 2918,
2688	ARM_t2PKHBT	= 2919,
2689	ARM_t2PKHTB	= 2920,
2690	ARM_t2PLDWi12	= 2921,
2691	ARM_t2PLDWi8	= 2922,
2692	ARM_t2PLDWs	= 2923,
2693	ARM_t2PLDi12	= 2924,
2694	ARM_t2PLDi8	= 2925,
2695	ARM_t2PLDpci	= 2926,
2696	ARM_t2PLDs	= 2927,
2697	ARM_t2PLIi12	= 2928,
2698	ARM_t2PLIi8	= 2929,
2699	ARM_t2PLIpci	= 2930,
2700	ARM_t2PLIs	= 2931,
2701	ARM_t2QADD	= 2932,
2702	ARM_t2QADD16	= 2933,
2703	ARM_t2QADD8	= 2934,
2704	ARM_t2QASX	= 2935,
2705	ARM_t2QDADD	= 2936,
2706	ARM_t2QDSUB	= 2937,
2707	ARM_t2QSAX	= 2938,
2708	ARM_t2QSUB	= 2939,
2709	ARM_t2QSUB16	= 2940,
2710	ARM_t2QSUB8	= 2941,
2711	ARM_t2RBIT	= 2942,
2712	ARM_t2REV	= 2943,
2713	ARM_t2REV16	= 2944,
2714	ARM_t2REVSH	= 2945,
2715	ARM_t2RFEDB	= 2946,
2716	ARM_t2RFEDBW	= 2947,
2717	ARM_t2RFEIA	= 2948,
2718	ARM_t2RFEIAW	= 2949,
2719	ARM_t2RORri	= 2950,
2720	ARM_t2RORrr	= 2951,
2721	ARM_t2RRX	= 2952,
2722	ARM_t2RSBri	= 2953,
2723	ARM_t2RSBrr	= 2954,
2724	ARM_t2RSBrs	= 2955,
2725	ARM_t2SADD16	= 2956,
2726	ARM_t2SADD8	= 2957,
2727	ARM_t2SASX	= 2958,
2728	ARM_t2SBCri	= 2959,
2729	ARM_t2SBCrr	= 2960,
2730	ARM_t2SBCrs	= 2961,
2731	ARM_t2SBFX	= 2962,
2732	ARM_t2SDIV	= 2963,
2733	ARM_t2SEL	= 2964,
2734	ARM_t2SETPAN	= 2965,
2735	ARM_t2SG	= 2966,
2736	ARM_t2SHADD16	= 2967,
2737	ARM_t2SHADD8	= 2968,
2738	ARM_t2SHASX	= 2969,
2739	ARM_t2SHSAX	= 2970,
2740	ARM_t2SHSUB16	= 2971,
2741	ARM_t2SHSUB8	= 2972,
2742	ARM_t2SMC	= 2973,
2743	ARM_t2SMLABB	= 2974,
2744	ARM_t2SMLABT	= 2975,
2745	ARM_t2SMLAD	= 2976,
2746	ARM_t2SMLADX	= 2977,
2747	ARM_t2SMLAL	= 2978,
2748	ARM_t2SMLALBB	= 2979,
2749	ARM_t2SMLALBT	= 2980,
2750	ARM_t2SMLALD	= 2981,
2751	ARM_t2SMLALDX	= 2982,
2752	ARM_t2SMLALTB	= 2983,
2753	ARM_t2SMLALTT	= 2984,
2754	ARM_t2SMLATB	= 2985,
2755	ARM_t2SMLATT	= 2986,
2756	ARM_t2SMLAWB	= 2987,
2757	ARM_t2SMLAWT	= 2988,
2758	ARM_t2SMLSD	= 2989,
2759	ARM_t2SMLSDX	= 2990,
2760	ARM_t2SMLSLD	= 2991,
2761	ARM_t2SMLSLDX	= 2992,
2762	ARM_t2SMMLA	= 2993,
2763	ARM_t2SMMLAR	= 2994,
2764	ARM_t2SMMLS	= 2995,
2765	ARM_t2SMMLSR	= 2996,
2766	ARM_t2SMMUL	= 2997,
2767	ARM_t2SMMULR	= 2998,
2768	ARM_t2SMUAD	= 2999,
2769	ARM_t2SMUADX	= 3000,
2770	ARM_t2SMULBB	= 3001,
2771	ARM_t2SMULBT	= 3002,
2772	ARM_t2SMULL	= 3003,
2773	ARM_t2SMULTB	= 3004,
2774	ARM_t2SMULTT	= 3005,
2775	ARM_t2SMULWB	= 3006,
2776	ARM_t2SMULWT	= 3007,
2777	ARM_t2SMUSD	= 3008,
2778	ARM_t2SMUSDX	= 3009,
2779	ARM_t2SRSDB	= 3010,
2780	ARM_t2SRSDB_UPD	= 3011,
2781	ARM_t2SRSIA	= 3012,
2782	ARM_t2SRSIA_UPD	= 3013,
2783	ARM_t2SSAT	= 3014,
2784	ARM_t2SSAT16	= 3015,
2785	ARM_t2SSAX	= 3016,
2786	ARM_t2SSUB16	= 3017,
2787	ARM_t2SSUB8	= 3018,
2788	ARM_t2STC2L_OFFSET	= 3019,
2789	ARM_t2STC2L_OPTION	= 3020,
2790	ARM_t2STC2L_POST	= 3021,
2791	ARM_t2STC2L_PRE	= 3022,
2792	ARM_t2STC2_OFFSET	= 3023,
2793	ARM_t2STC2_OPTION	= 3024,
2794	ARM_t2STC2_POST	= 3025,
2795	ARM_t2STC2_PRE	= 3026,
2796	ARM_t2STCL_OFFSET	= 3027,
2797	ARM_t2STCL_OPTION	= 3028,
2798	ARM_t2STCL_POST	= 3029,
2799	ARM_t2STCL_PRE	= 3030,
2800	ARM_t2STC_OFFSET	= 3031,
2801	ARM_t2STC_OPTION	= 3032,
2802	ARM_t2STC_POST	= 3033,
2803	ARM_t2STC_PRE	= 3034,
2804	ARM_t2STL	= 3035,
2805	ARM_t2STLB	= 3036,
2806	ARM_t2STLEX	= 3037,
2807	ARM_t2STLEXB	= 3038,
2808	ARM_t2STLEXD	= 3039,
2809	ARM_t2STLEXH	= 3040,
2810	ARM_t2STLH	= 3041,
2811	ARM_t2STMDB	= 3042,
2812	ARM_t2STMDB_UPD	= 3043,
2813	ARM_t2STMIA	= 3044,
2814	ARM_t2STMIA_UPD	= 3045,
2815	ARM_t2STRBT	= 3046,
2816	ARM_t2STRB_POST	= 3047,
2817	ARM_t2STRB_PRE	= 3048,
2818	ARM_t2STRBi12	= 3049,
2819	ARM_t2STRBi8	= 3050,
2820	ARM_t2STRBs	= 3051,
2821	ARM_t2STRD_POST	= 3052,
2822	ARM_t2STRD_PRE	= 3053,
2823	ARM_t2STRDi8	= 3054,
2824	ARM_t2STREX	= 3055,
2825	ARM_t2STREXB	= 3056,
2826	ARM_t2STREXD	= 3057,
2827	ARM_t2STREXH	= 3058,
2828	ARM_t2STRHT	= 3059,
2829	ARM_t2STRH_POST	= 3060,
2830	ARM_t2STRH_PRE	= 3061,
2831	ARM_t2STRHi12	= 3062,
2832	ARM_t2STRHi8	= 3063,
2833	ARM_t2STRHs	= 3064,
2834	ARM_t2STRT	= 3065,
2835	ARM_t2STR_POST	= 3066,
2836	ARM_t2STR_PRE	= 3067,
2837	ARM_t2STRi12	= 3068,
2838	ARM_t2STRi8	= 3069,
2839	ARM_t2STRs	= 3070,
2840	ARM_t2SUBS_PC_LR	= 3071,
2841	ARM_t2SUBri	= 3072,
2842	ARM_t2SUBri12	= 3073,
2843	ARM_t2SUBrr	= 3074,
2844	ARM_t2SUBrs	= 3075,
2845	ARM_t2SXTAB	= 3076,
2846	ARM_t2SXTAB16	= 3077,
2847	ARM_t2SXTAH	= 3078,
2848	ARM_t2SXTB	= 3079,
2849	ARM_t2SXTB16	= 3080,
2850	ARM_t2SXTH	= 3081,
2851	ARM_t2TBB	= 3082,
2852	ARM_t2TBH	= 3083,
2853	ARM_t2TEQri	= 3084,
2854	ARM_t2TEQrr	= 3085,
2855	ARM_t2TEQrs	= 3086,
2856	ARM_t2TSB	= 3087,
2857	ARM_t2TSTri	= 3088,
2858	ARM_t2TSTrr	= 3089,
2859	ARM_t2TSTrs	= 3090,
2860	ARM_t2TT	= 3091,
2861	ARM_t2TTA	= 3092,
2862	ARM_t2TTAT	= 3093,
2863	ARM_t2TTT	= 3094,
2864	ARM_t2UADD16	= 3095,
2865	ARM_t2UADD8	= 3096,
2866	ARM_t2UASX	= 3097,
2867	ARM_t2UBFX	= 3098,
2868	ARM_t2UDF	= 3099,
2869	ARM_t2UDIV	= 3100,
2870	ARM_t2UHADD16	= 3101,
2871	ARM_t2UHADD8	= 3102,
2872	ARM_t2UHASX	= 3103,
2873	ARM_t2UHSAX	= 3104,
2874	ARM_t2UHSUB16	= 3105,
2875	ARM_t2UHSUB8	= 3106,
2876	ARM_t2UMAAL	= 3107,
2877	ARM_t2UMLAL	= 3108,
2878	ARM_t2UMULL	= 3109,
2879	ARM_t2UQADD16	= 3110,
2880	ARM_t2UQADD8	= 3111,
2881	ARM_t2UQASX	= 3112,
2882	ARM_t2UQSAX	= 3113,
2883	ARM_t2UQSUB16	= 3114,
2884	ARM_t2UQSUB8	= 3115,
2885	ARM_t2USAD8	= 3116,
2886	ARM_t2USADA8	= 3117,
2887	ARM_t2USAT	= 3118,
2888	ARM_t2USAT16	= 3119,
2889	ARM_t2USAX	= 3120,
2890	ARM_t2USUB16	= 3121,
2891	ARM_t2USUB8	= 3122,
2892	ARM_t2UXTAB	= 3123,
2893	ARM_t2UXTAB16	= 3124,
2894	ARM_t2UXTAH	= 3125,
2895	ARM_t2UXTB	= 3126,
2896	ARM_t2UXTB16	= 3127,
2897	ARM_t2UXTH	= 3128,
2898	ARM_tADC	= 3129,
2899	ARM_tADDhirr	= 3130,
2900	ARM_tADDi3	= 3131,
2901	ARM_tADDi8	= 3132,
2902	ARM_tADDrSP	= 3133,
2903	ARM_tADDrSPi	= 3134,
2904	ARM_tADDrr	= 3135,
2905	ARM_tADDspi	= 3136,
2906	ARM_tADDspr	= 3137,
2907	ARM_tADR	= 3138,
2908	ARM_tAND	= 3139,
2909	ARM_tASRri	= 3140,
2910	ARM_tASRrr	= 3141,
2911	ARM_tB	= 3142,
2912	ARM_tBIC	= 3143,
2913	ARM_tBKPT	= 3144,
2914	ARM_tBL	= 3145,
2915	ARM_tBLXNSr	= 3146,
2916	ARM_tBLXi	= 3147,
2917	ARM_tBLXr	= 3148,
2918	ARM_tBX	= 3149,
2919	ARM_tBXNS	= 3150,
2920	ARM_tBcc	= 3151,
2921	ARM_tCBNZ	= 3152,
2922	ARM_tCBZ	= 3153,
2923	ARM_tCMNz	= 3154,
2924	ARM_tCMPhir	= 3155,
2925	ARM_tCMPi8	= 3156,
2926	ARM_tCMPr	= 3157,
2927	ARM_tCPS	= 3158,
2928	ARM_tEOR	= 3159,
2929	ARM_tHINT	= 3160,
2930	ARM_tHLT	= 3161,
2931	ARM_tLDMIA	= 3165,
2932	ARM_tLDRBi	= 3166,
2933	ARM_tLDRBr	= 3167,
2934	ARM_tLDRHi	= 3168,
2935	ARM_tLDRHr	= 3169,
2936	ARM_tLDRSB	= 3170,
2937	ARM_tLDRSH	= 3171,
2938	ARM_tLDRi	= 3172,
2939	ARM_tLDRpci	= 3173,
2940	ARM_tLDRr	= 3174,
2941	ARM_tLDRspi	= 3175,
2942	ARM_tLSLri	= 3176,
2943	ARM_tLSLrr	= 3177,
2944	ARM_tLSRri	= 3178,
2945	ARM_tLSRrr	= 3179,
2946	ARM_tMOVSr	= 3180,
2947	ARM_tMOVi8	= 3181,
2948	ARM_tMOVr	= 3182,
2949	ARM_tMUL	= 3183,
2950	ARM_tMVN	= 3184,
2951	ARM_tORR	= 3185,
2952	ARM_tPICADD	= 3186,
2953	ARM_tPOP	= 3187,
2954	ARM_tPUSH	= 3188,
2955	ARM_tREV	= 3189,
2956	ARM_tREV16	= 3190,
2957	ARM_tREVSH	= 3191,
2958	ARM_tROR	= 3192,
2959	ARM_tRSB	= 3193,
2960	ARM_tSBC	= 3194,
2961	ARM_tSETEND	= 3195,
2962	ARM_tSTMIA_UPD	= 3196,
2963	ARM_tSTRBi	= 3197,
2964	ARM_tSTRBr	= 3198,
2965	ARM_tSTRHi	= 3199,
2966	ARM_tSTRHr	= 3200,
2967	ARM_tSTRi	= 3201,
2968	ARM_tSTRr	= 3202,
2969	ARM_tSTRspi	= 3203,
2970	ARM_tSUBi3	= 3204,
2971	ARM_tSUBi8	= 3205,
2972	ARM_tSUBrr	= 3206,
2973	ARM_tSUBspi	= 3207,
2974	ARM_tSVC	= 3208,
2975	ARM_tSXTB	= 3209,
2976	ARM_tSXTH	= 3210,
2977	ARM_tTRAP	= 3211,
2978	ARM_tTST	= 3212,
2979	ARM_tUDF	= 3213,
2980	ARM_tUXTB	= 3214,
2981	ARM_tUXTH	= 3215,
2982	ARM_t__brkdiv0	= 3216,
2983	ARM_INSTRUCTION_LIST_END = 3217
2984};
2985
2986#endif // GET_INSTRINFO_ENUM
2987
2988#ifdef GET_INSTRINFO_MC_DESC
2989#undef GET_INSTRINFO_MC_DESC
2990
2991#define nullptr 0
2992
2993static const MCOperandInfo OperandInfo2[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
2994static const MCOperandInfo OperandInfo3[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
2995static const MCOperandInfo OperandInfo4[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
2996static const MCOperandInfo OperandInfo5[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
2997static const MCOperandInfo OperandInfo6[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
2998static const MCOperandInfo OperandInfo7[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
2999static const MCOperandInfo OperandInfo8[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
3000static const MCOperandInfo OperandInfo9[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
3001static const MCOperandInfo OperandInfo10[] = { { 0, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, };
3002static const MCOperandInfo OperandInfo11[] = { { 0, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
3003static const MCOperandInfo OperandInfo12[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { 0, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
3004static const MCOperandInfo OperandInfo13[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, };
3005static const MCOperandInfo OperandInfo14[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, };
3006static const MCOperandInfo OperandInfo15[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
3007static const MCOperandInfo OperandInfo16[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
3008static const MCOperandInfo OperandInfo17[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, };
3009static const MCOperandInfo OperandInfo18[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
3010static const MCOperandInfo OperandInfo19[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, };
3011static const MCOperandInfo OperandInfo20[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, };
3012static const MCOperandInfo OperandInfo21[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, };
3013static const MCOperandInfo OperandInfo22[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, };
3014static const MCOperandInfo OperandInfo23[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, };
3015static const MCOperandInfo OperandInfo24[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, };
3016static const MCOperandInfo OperandInfo25[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, };
3017static const MCOperandInfo OperandInfo26[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, };
3018static const MCOperandInfo OperandInfo27[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
3019static const MCOperandInfo OperandInfo28[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_2, 0 }, };
3020static const MCOperandInfo OperandInfo29[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_2, 0 }, };
3021static const MCOperandInfo OperandInfo30[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_2, 0 }, };
3022static const MCOperandInfo OperandInfo31[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
3023static const MCOperandInfo OperandInfo32[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3024static const MCOperandInfo OperandInfo33[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3025static const MCOperandInfo OperandInfo34[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3026static const MCOperandInfo OperandInfo35[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3027static const MCOperandInfo OperandInfo36[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3028static const MCOperandInfo OperandInfo37[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
3029static const MCOperandInfo OperandInfo38[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
3030static const MCOperandInfo OperandInfo39[] = { { -1, 0, MCOI_OPERAND_PCREL, 0 }, };
3031static const MCOperandInfo OperandInfo40[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_PCREL, 0 }, };
3032static const MCOperandInfo OperandInfo41[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_PCREL, 0 }, };
3033static const MCOperandInfo OperandInfo42[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
3034static const MCOperandInfo OperandInfo43[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
3035static const MCOperandInfo OperandInfo44[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
3036static const MCOperandInfo OperandInfo45[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
3037static const MCOperandInfo OperandInfo46[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
3038static const MCOperandInfo OperandInfo47[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
3039static const MCOperandInfo OperandInfo48[] = { { ARM_GPRPairRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
3040static const MCOperandInfo OperandInfo49[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
3041static const MCOperandInfo OperandInfo50[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
3042static const MCOperandInfo OperandInfo51[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3043static const MCOperandInfo OperandInfo52[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3044static const MCOperandInfo OperandInfo53[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3045static const MCOperandInfo OperandInfo54[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
3046static const MCOperandInfo OperandInfo55[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
3047static const MCOperandInfo OperandInfo56[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3048static const MCOperandInfo OperandInfo57[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3049static const MCOperandInfo OperandInfo58[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3050static const MCOperandInfo OperandInfo59[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3051static const MCOperandInfo OperandInfo60[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3052static const MCOperandInfo OperandInfo61[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
3053static const MCOperandInfo OperandInfo62[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
3054static const MCOperandInfo OperandInfo63[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
3055static const MCOperandInfo OperandInfo64[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
3056static const MCOperandInfo OperandInfo65[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3057static const MCOperandInfo OperandInfo66[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
3058static const MCOperandInfo OperandInfo67[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
3059static const MCOperandInfo OperandInfo68[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
3060static const MCOperandInfo OperandInfo69[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
3061static const MCOperandInfo OperandInfo70[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3062static const MCOperandInfo OperandInfo71[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3063static const MCOperandInfo OperandInfo72[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3064static const MCOperandInfo OperandInfo73[] = { { ARM_tcGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
3065static const MCOperandInfo OperandInfo74[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3066static const MCOperandInfo OperandInfo75[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3067static const MCOperandInfo OperandInfo76[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3068static const MCOperandInfo OperandInfo77[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3069static const MCOperandInfo OperandInfo78[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
3070static const MCOperandInfo OperandInfo79[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3071static const MCOperandInfo OperandInfo80[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
3072static const MCOperandInfo OperandInfo81[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3073static const MCOperandInfo OperandInfo82[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
3074static const MCOperandInfo OperandInfo83[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3075static const MCOperandInfo OperandInfo84[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3076static const MCOperandInfo OperandInfo85[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3077static const MCOperandInfo OperandInfo86[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3078static const MCOperandInfo OperandInfo87[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
3079static const MCOperandInfo OperandInfo88[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3080static const MCOperandInfo OperandInfo89[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3081static const MCOperandInfo OperandInfo90[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3082static const MCOperandInfo OperandInfo91[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3083static const MCOperandInfo OperandInfo92[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3084static const MCOperandInfo OperandInfo93[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3085static const MCOperandInfo OperandInfo94[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3086static const MCOperandInfo OperandInfo95[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
3087static const MCOperandInfo OperandInfo96[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
3088static const MCOperandInfo OperandInfo97[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3089static const MCOperandInfo OperandInfo98[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3090static const MCOperandInfo OperandInfo99[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3091static const MCOperandInfo OperandInfo100[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
3092static const MCOperandInfo OperandInfo101[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
3093static const MCOperandInfo OperandInfo102[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
3094static const MCOperandInfo OperandInfo103[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3095static const MCOperandInfo OperandInfo104[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
3096static const MCOperandInfo OperandInfo105[] = { { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3097static const MCOperandInfo OperandInfo106[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3098static const MCOperandInfo OperandInfo107[] = { { -1, 0, MCOI_OPERAND_PCREL, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3099static const MCOperandInfo OperandInfo108[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3100static const MCOperandInfo OperandInfo109[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3101static const MCOperandInfo OperandInfo110[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3102static const MCOperandInfo OperandInfo111[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3103static const MCOperandInfo OperandInfo112[] = { { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
3104static const MCOperandInfo OperandInfo113[] = { { ARM_tGPRwithpcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
3105static const MCOperandInfo OperandInfo114[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
3106static const MCOperandInfo OperandInfo115[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
3107static const MCOperandInfo OperandInfo116[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
3108static const MCOperandInfo OperandInfo117[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
3109static const MCOperandInfo OperandInfo118[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
3110static const MCOperandInfo OperandInfo119[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
3111static const MCOperandInfo OperandInfo120[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3112static const MCOperandInfo OperandInfo121[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3113static const MCOperandInfo OperandInfo122[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
3114static const MCOperandInfo OperandInfo123[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3115static const MCOperandInfo OperandInfo124[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3116static const MCOperandInfo OperandInfo125[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3117static const MCOperandInfo OperandInfo126[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
3118static const MCOperandInfo OperandInfo127[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
3119static const MCOperandInfo OperandInfo128[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3120static const MCOperandInfo OperandInfo129[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3121static const MCOperandInfo OperandInfo130[] = { { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3122static const MCOperandInfo OperandInfo131[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3123static const MCOperandInfo OperandInfo132[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
3124static const MCOperandInfo OperandInfo133[] = { { ARM_GPRPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3125static const MCOperandInfo OperandInfo134[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, };
3126static const MCOperandInfo OperandInfo135[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
3127static const MCOperandInfo OperandInfo136[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3128static const MCOperandInfo OperandInfo137[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3129static const MCOperandInfo OperandInfo138[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3130static const MCOperandInfo OperandInfo139[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3131static const MCOperandInfo OperandInfo140[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3132static const MCOperandInfo OperandInfo141[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3133static const MCOperandInfo OperandInfo142[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3134static const MCOperandInfo OperandInfo143[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((2 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3135static const MCOperandInfo OperandInfo144[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3136static const MCOperandInfo OperandInfo145[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3137static const MCOperandInfo OperandInfo146[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3138static const MCOperandInfo OperandInfo147[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3139static const MCOperandInfo OperandInfo148[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3140static const MCOperandInfo OperandInfo149[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
3141static const MCOperandInfo OperandInfo150[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3142static const MCOperandInfo OperandInfo151[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
3143static const MCOperandInfo OperandInfo152[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
3144static const MCOperandInfo OperandInfo153[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3145static const MCOperandInfo OperandInfo154[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3146static const MCOperandInfo OperandInfo155[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
3147static const MCOperandInfo OperandInfo156[] = { { ARM_tcGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tcGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
3148static const MCOperandInfo OperandInfo157[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
3149static const MCOperandInfo OperandInfo158[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
3150static const MCOperandInfo OperandInfo159[] = { { ARM_GPRwithAPSRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3151static const MCOperandInfo OperandInfo160[] = { { ARM_GPRwithAPSRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
3152static const MCOperandInfo OperandInfo161[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3153static const MCOperandInfo OperandInfo162[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
3154static const MCOperandInfo OperandInfo163[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3155static const MCOperandInfo OperandInfo164[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3156static const MCOperandInfo OperandInfo165[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3157static const MCOperandInfo OperandInfo166[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3158static const MCOperandInfo OperandInfo167[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
3159static const MCOperandInfo OperandInfo168[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3160static const MCOperandInfo OperandInfo169[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, };
3161static const MCOperandInfo OperandInfo170[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, };
3162static const MCOperandInfo OperandInfo171[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3163static const MCOperandInfo OperandInfo172[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3164static const MCOperandInfo OperandInfo173[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
3165static const MCOperandInfo OperandInfo174[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3166static const MCOperandInfo OperandInfo175[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
3167static const MCOperandInfo OperandInfo176[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3168static const MCOperandInfo OperandInfo177[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
3169static const MCOperandInfo OperandInfo178[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3170static const MCOperandInfo OperandInfo179[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3171static const MCOperandInfo OperandInfo180[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3172static const MCOperandInfo OperandInfo181[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3173static const MCOperandInfo OperandInfo182[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3174static const MCOperandInfo OperandInfo183[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3175static const MCOperandInfo OperandInfo184[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3176static const MCOperandInfo OperandInfo185[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3177static const MCOperandInfo OperandInfo186[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3178static const MCOperandInfo OperandInfo187[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3179static const MCOperandInfo OperandInfo188[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3180static const MCOperandInfo OperandInfo189[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3181static const MCOperandInfo OperandInfo190[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3182static const MCOperandInfo OperandInfo191[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3183static const MCOperandInfo OperandInfo192[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3184static const MCOperandInfo OperandInfo193[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3185static const MCOperandInfo OperandInfo194[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3186static const MCOperandInfo OperandInfo195[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3187static const MCOperandInfo OperandInfo196[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3188static const MCOperandInfo OperandInfo197[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3189static const MCOperandInfo OperandInfo198[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3190static const MCOperandInfo OperandInfo199[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3191static const MCOperandInfo OperandInfo200[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3192static const MCOperandInfo OperandInfo201[] = { { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3193static const MCOperandInfo OperandInfo202[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3194static const MCOperandInfo OperandInfo203[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3195static const MCOperandInfo OperandInfo204[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3196static const MCOperandInfo OperandInfo205[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3197static const MCOperandInfo OperandInfo206[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3198static const MCOperandInfo OperandInfo207[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
3199static const MCOperandInfo OperandInfo208[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
3200static const MCOperandInfo OperandInfo209[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
3201static const MCOperandInfo OperandInfo210[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
3202static const MCOperandInfo OperandInfo211[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
3203static const MCOperandInfo OperandInfo212[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
3204static const MCOperandInfo OperandInfo213[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
3205static const MCOperandInfo OperandInfo214[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
3206static const MCOperandInfo OperandInfo215[] = { { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3207static const MCOperandInfo OperandInfo216[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3208static const MCOperandInfo OperandInfo217[] = { { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3209static const MCOperandInfo OperandInfo218[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3210static const MCOperandInfo OperandInfo219[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
3211static const MCOperandInfo OperandInfo220[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
3212static const MCOperandInfo OperandInfo221[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
3213static const MCOperandInfo OperandInfo222[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
3214static const MCOperandInfo OperandInfo223[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3215static const MCOperandInfo OperandInfo224[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3216static const MCOperandInfo OperandInfo225[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3217static const MCOperandInfo OperandInfo226[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3218static const MCOperandInfo OperandInfo227[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3219static const MCOperandInfo OperandInfo228[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3220static const MCOperandInfo OperandInfo229[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3221static const MCOperandInfo OperandInfo230[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3222static const MCOperandInfo OperandInfo231[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3223static const MCOperandInfo OperandInfo232[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3224static const MCOperandInfo OperandInfo233[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3225static const MCOperandInfo OperandInfo234[] = { { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3226static const MCOperandInfo OperandInfo235[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3227static const MCOperandInfo OperandInfo236[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3228static const MCOperandInfo OperandInfo237[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3229static const MCOperandInfo OperandInfo238[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3230static const MCOperandInfo OperandInfo239[] = { { ARM_DPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3231static const MCOperandInfo OperandInfo240[] = { { ARM_DPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3232static const MCOperandInfo OperandInfo241[] = { { ARM_DPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3233static const MCOperandInfo OperandInfo242[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3234static const MCOperandInfo OperandInfo243[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3235static const MCOperandInfo OperandInfo244[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3236static const MCOperandInfo OperandInfo245[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3237static const MCOperandInfo OperandInfo246[] = { { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3238static const MCOperandInfo OperandInfo247[] = { { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3239static const MCOperandInfo OperandInfo248[] = { { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3240static const MCOperandInfo OperandInfo249[] = { { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3241static const MCOperandInfo OperandInfo250[] = { { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3242static const MCOperandInfo OperandInfo251[] = { { ARM_DPairSpcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3243static const MCOperandInfo OperandInfo252[] = { { ARM_DPairSpcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3244static const MCOperandInfo OperandInfo253[] = { { ARM_DPairSpcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3245static const MCOperandInfo OperandInfo254[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3246static const MCOperandInfo OperandInfo255[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((2 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3247static const MCOperandInfo OperandInfo256[] = { { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3248static const MCOperandInfo OperandInfo257[] = { { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3249static const MCOperandInfo OperandInfo258[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3250static const MCOperandInfo OperandInfo259[] = { { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3251static const MCOperandInfo OperandInfo260[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((3 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3252static const MCOperandInfo OperandInfo261[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((2 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3253static const MCOperandInfo OperandInfo262[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((3 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((2 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3254static const MCOperandInfo OperandInfo263[] = { { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3255static const MCOperandInfo OperandInfo264[] = { { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3256static const MCOperandInfo OperandInfo265[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3257static const MCOperandInfo OperandInfo266[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((4 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3258static const MCOperandInfo OperandInfo267[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((2 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((3 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3259static const MCOperandInfo OperandInfo268[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((4 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((2 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((3 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3260static const MCOperandInfo OperandInfo269[] = { { ARM_DPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3261static const MCOperandInfo OperandInfo270[] = { { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3262static const MCOperandInfo OperandInfo271[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3263static const MCOperandInfo OperandInfo272[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
3264static const MCOperandInfo OperandInfo273[] = { { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
3265static const MCOperandInfo OperandInfo274[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
3266static const MCOperandInfo OperandInfo275[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
3267static const MCOperandInfo OperandInfo276[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3268static const MCOperandInfo OperandInfo277[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3269static const MCOperandInfo OperandInfo278[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3270static const MCOperandInfo OperandInfo279[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3271static const MCOperandInfo OperandInfo280[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3272static const MCOperandInfo OperandInfo281[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3273static const MCOperandInfo OperandInfo282[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3274static const MCOperandInfo OperandInfo283[] = { { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3275static const MCOperandInfo OperandInfo284[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3276static const MCOperandInfo OperandInfo285[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3277static const MCOperandInfo OperandInfo286[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3278static const MCOperandInfo OperandInfo287[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3279static const MCOperandInfo OperandInfo288[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3280static const MCOperandInfo OperandInfo289[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3281static const MCOperandInfo OperandInfo290[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3282static const MCOperandInfo OperandInfo291[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
3283static const MCOperandInfo OperandInfo292[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3284static const MCOperandInfo OperandInfo293[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3285static const MCOperandInfo OperandInfo294[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3286static const MCOperandInfo OperandInfo295[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3287static const MCOperandInfo OperandInfo296[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3288static const MCOperandInfo OperandInfo297[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3289static const MCOperandInfo OperandInfo298[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3290static const MCOperandInfo OperandInfo299[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3291static const MCOperandInfo OperandInfo300[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3292static const MCOperandInfo OperandInfo301[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3293static const MCOperandInfo OperandInfo302[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3294static const MCOperandInfo OperandInfo303[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3295static const MCOperandInfo OperandInfo304[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
3296static const MCOperandInfo OperandInfo305[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
3297static const MCOperandInfo OperandInfo306[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
3298static const MCOperandInfo OperandInfo307[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3299static const MCOperandInfo OperandInfo308[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3300static const MCOperandInfo OperandInfo309[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3301static const MCOperandInfo OperandInfo310[] = { { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3302static const MCOperandInfo OperandInfo311[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3303static const MCOperandInfo OperandInfo312[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3304static const MCOperandInfo OperandInfo313[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3305static const MCOperandInfo OperandInfo314[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3306static const MCOperandInfo OperandInfo315[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3307static const MCOperandInfo OperandInfo316[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3308static const MCOperandInfo OperandInfo317[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3309static const MCOperandInfo OperandInfo318[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3310static const MCOperandInfo OperandInfo319[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3311static const MCOperandInfo OperandInfo320[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3312static const MCOperandInfo OperandInfo321[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3313static const MCOperandInfo OperandInfo322[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3314static const MCOperandInfo OperandInfo323[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3315static const MCOperandInfo OperandInfo324[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3316static const MCOperandInfo OperandInfo325[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3317static const MCOperandInfo OperandInfo326[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3318static const MCOperandInfo OperandInfo327[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3319static const MCOperandInfo OperandInfo328[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3320static const MCOperandInfo OperandInfo329[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3321static const MCOperandInfo OperandInfo330[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3322static const MCOperandInfo OperandInfo331[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3323static const MCOperandInfo OperandInfo332[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3324static const MCOperandInfo OperandInfo333[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3325static const MCOperandInfo OperandInfo334[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3326static const MCOperandInfo OperandInfo335[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3327static const MCOperandInfo OperandInfo336[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3328static const MCOperandInfo OperandInfo337[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3329static const MCOperandInfo OperandInfo338[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3330static const MCOperandInfo OperandInfo339[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3331static const MCOperandInfo OperandInfo340[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3332static const MCOperandInfo OperandInfo341[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3333static const MCOperandInfo OperandInfo342[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3334static const MCOperandInfo OperandInfo343[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3335static const MCOperandInfo OperandInfo344[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3336static const MCOperandInfo OperandInfo345[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3337static const MCOperandInfo OperandInfo346[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3338static const MCOperandInfo OperandInfo347[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3339static const MCOperandInfo OperandInfo348[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3340static const MCOperandInfo OperandInfo349[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3341static const MCOperandInfo OperandInfo350[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
3342static const MCOperandInfo OperandInfo351[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
3343static const MCOperandInfo OperandInfo352[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
3344static const MCOperandInfo OperandInfo353[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
3345static const MCOperandInfo OperandInfo354[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3346static const MCOperandInfo OperandInfo355[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
3347static const MCOperandInfo OperandInfo356[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
3348static const MCOperandInfo OperandInfo357[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3349static const MCOperandInfo OperandInfo358[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3350static const MCOperandInfo OperandInfo359[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3351static const MCOperandInfo OperandInfo360[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3352static const MCOperandInfo OperandInfo361[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3353static const MCOperandInfo OperandInfo362[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
3354static const MCOperandInfo OperandInfo363[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
3355static const MCOperandInfo OperandInfo364[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3356static const MCOperandInfo OperandInfo365[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3357static const MCOperandInfo OperandInfo366[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3358static const MCOperandInfo OperandInfo367[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3359static const MCOperandInfo OperandInfo368[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((2 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3360static const MCOperandInfo OperandInfo369[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3361static const MCOperandInfo OperandInfo370[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3362static const MCOperandInfo OperandInfo371[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3363static const MCOperandInfo OperandInfo372[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3364static const MCOperandInfo OperandInfo373[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3365static const MCOperandInfo OperandInfo374[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
3366static const MCOperandInfo OperandInfo375[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
3367static const MCOperandInfo OperandInfo376[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3368static const MCOperandInfo OperandInfo377[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3369static const MCOperandInfo OperandInfo378[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3370static const MCOperandInfo OperandInfo379[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
3371static const MCOperandInfo OperandInfo380[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
3372static const MCOperandInfo OperandInfo381[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3373static const MCOperandInfo OperandInfo382[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3374static const MCOperandInfo OperandInfo383[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3375static const MCOperandInfo OperandInfo384[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3376static const MCOperandInfo OperandInfo385[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3377static const MCOperandInfo OperandInfo386[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3378static const MCOperandInfo OperandInfo387[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3379static const MCOperandInfo OperandInfo388[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3380static const MCOperandInfo OperandInfo389[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3381static const MCOperandInfo OperandInfo390[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3382static const MCOperandInfo OperandInfo391[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3383static const MCOperandInfo OperandInfo392[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3384static const MCOperandInfo OperandInfo393[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3385static const MCOperandInfo OperandInfo394[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3386static const MCOperandInfo OperandInfo395[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3387static const MCOperandInfo OperandInfo396[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3388static const MCOperandInfo OperandInfo397[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3389static const MCOperandInfo OperandInfo398[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3390static const MCOperandInfo OperandInfo399[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3391static const MCOperandInfo OperandInfo400[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRspRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3392static const MCOperandInfo OperandInfo401[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRspRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3393static const MCOperandInfo OperandInfo402[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3394static const MCOperandInfo OperandInfo403[] = { { ARM_GPRspRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRspRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3395static const MCOperandInfo OperandInfo404[] = { { ARM_GPRspRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRspRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3396static const MCOperandInfo OperandInfo405[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_PCREL, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3397static const MCOperandInfo OperandInfo406[] = { { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_PCREL, 0 }, };
3398static const MCOperandInfo OperandInfo407[] = { { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
3399static const MCOperandInfo OperandInfo408[] = { { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
3400static const MCOperandInfo OperandInfo409[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_PCREL, 0 }, };
3401static const MCOperandInfo OperandInfo410[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3402static const MCOperandInfo OperandInfo411[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
3403static const MCOperandInfo OperandInfo412[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3404static const MCOperandInfo OperandInfo413[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3405static const MCOperandInfo OperandInfo414[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3406static const MCOperandInfo OperandInfo415[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3407static const MCOperandInfo OperandInfo416[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3408static const MCOperandInfo OperandInfo417[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3409static const MCOperandInfo OperandInfo418[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
3410static const MCOperandInfo OperandInfo419[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
3411
3412static const MCInstrDesc ARMInsts[] = {
3413  { 1, OperandInfo2 },
3414  { 0, nullptr },
3415  { 1, OperandInfo3 },
3416  { 1, OperandInfo3 },
3417  { 1, OperandInfo3 },
3418  { 1, OperandInfo3 },
3419  { 0, nullptr },
3420  { 3, OperandInfo4 },
3421  { 4, OperandInfo5 },
3422  { 1, OperandInfo2 },
3423  { 4, OperandInfo6 },
3424  { 3, OperandInfo4 },
3425  { 0, nullptr },
3426  { 1, OperandInfo2 },
3427  { 2, OperandInfo7 },
3428  { 2, OperandInfo7 },
3429  { 0, nullptr },
3430  { 1, OperandInfo3 },
3431  { 1, OperandInfo3 },
3432  { 2, OperandInfo8 },
3433  { 1, OperandInfo2 },
3434  { 6, OperandInfo9 },
3435  { 1, OperandInfo10 },
3436  { 0, nullptr },
3437  { 2, OperandInfo11 },
3438  { 1, OperandInfo2 },
3439  { 1, OperandInfo2 },
3440  { 0, nullptr },
3441  { 0, nullptr },
3442  { 0, nullptr },
3443  { 0, nullptr },
3444  { 2, OperandInfo11 },
3445  { 3, OperandInfo12 },
3446  { 1, OperandInfo2 },
3447  { 3, OperandInfo13 },
3448  { 3, OperandInfo13 },
3449  { 3, OperandInfo13 },
3450  { 3, OperandInfo13 },
3451  { 3, OperandInfo13 },
3452  { 3, OperandInfo13 },
3453  { 3, OperandInfo13 },
3454  { 3, OperandInfo13 },
3455  { 3, OperandInfo13 },
3456  { 3, OperandInfo13 },
3457  { 1, OperandInfo14 },
3458  { 1, OperandInfo14 },
3459  { 2, OperandInfo15 },
3460  { 2, OperandInfo15 },
3461  { 3, OperandInfo16 },
3462  { 2, OperandInfo17 },
3463  { 4, OperandInfo18 },
3464  { 2, OperandInfo17 },
3465  { 2, OperandInfo17 },
3466  { 2, OperandInfo17 },
3467  { 2, OperandInfo17 },
3468  { 2, OperandInfo17 },
3469  { 2, OperandInfo17 },
3470  { 2, OperandInfo17 },
3471  { 2, OperandInfo17 },
3472  { 5, OperandInfo19 },
3473  { 4, OperandInfo20 },
3474  { 3, OperandInfo21 },
3475  { 3, OperandInfo21 },
3476  { 3, OperandInfo21 },
3477  { 3, OperandInfo21 },
3478  { 3, OperandInfo21 },
3479  { 3, OperandInfo21 },
3480  { 3, OperandInfo21 },
3481  { 3, OperandInfo21 },
3482  { 3, OperandInfo21 },
3483  { 3, OperandInfo21 },
3484  { 3, OperandInfo21 },
3485  { 2, OperandInfo15 },
3486  { 1, OperandInfo14 },
3487  { 1, OperandInfo2 },
3488  { 1, OperandInfo2 },
3489  { 2, OperandInfo17 },
3490  { 2, OperandInfo17 },
3491  { 2, OperandInfo15 },
3492  { 2, OperandInfo15 },
3493  { 1, OperandInfo14 },
3494  { 3, OperandInfo16 },
3495  { 2, OperandInfo17 },
3496  { 2, OperandInfo17 },
3497  { 3, OperandInfo13 },
3498  { 3, OperandInfo13 },
3499  { 3, OperandInfo13 },
3500  { 4, OperandInfo22 },
3501  { 4, OperandInfo22 },
3502  { 4, OperandInfo20 },
3503  { 5, OperandInfo23 },
3504  { 5, OperandInfo23 },
3505  { 4, OperandInfo20 },
3506  { 4, OperandInfo20 },
3507  { 4, OperandInfo20 },
3508  { 4, OperandInfo20 },
3509  { 3, OperandInfo13 },
3510  { 3, OperandInfo13 },
3511  { 3, OperandInfo13 },
3512  { 3, OperandInfo13 },
3513  { 3, OperandInfo13 },
3514  { 4, OperandInfo24 },
3515  { 3, OperandInfo13 },
3516  { 3, OperandInfo13 },
3517  { 3, OperandInfo13 },
3518  { 2, OperandInfo25 },
3519  { 2, OperandInfo25 },
3520  { 2, OperandInfo25 },
3521  { 2, OperandInfo25 },
3522  { 2, OperandInfo25 },
3523  { 2, OperandInfo17 },
3524  { 2, OperandInfo17 },
3525  { 2, OperandInfo17 },
3526  { 2, OperandInfo17 },
3527  { 2, OperandInfo17 },
3528  { 2, OperandInfo17 },
3529  { 2, OperandInfo25 },
3530  { 3, OperandInfo26 },
3531  { 3, OperandInfo27 },
3532  { 1, OperandInfo2 },
3533  { 4, OperandInfo28 },
3534  { 3, OperandInfo29 },
3535  { 4, OperandInfo30 },
3536  { 2, OperandInfo25 },
3537  { 2, OperandInfo17 },
3538  { 2, OperandInfo15 },
3539  { 2, OperandInfo31 },
3540  { 5, OperandInfo32 },
3541  { 5, OperandInfo33 },
3542  { 6, OperandInfo34 },
3543  { 7, OperandInfo35 },
3544  { 4, OperandInfo36 },
3545  { 4, OperandInfo36 },
3546  { 6, OperandInfo37 },
3547  { 6, OperandInfo38 },
3548  { 1, OperandInfo39 },
3549  { 4, OperandInfo40 },
3550  { 6, OperandInfo41 },
3551  { 1, OperandInfo39 },
3552  { 1, OperandInfo42 },
3553  { 3, OperandInfo43 },
3554  { 3, OperandInfo44 },
3555  { 4, OperandInfo45 },
3556  { 2, OperandInfo46 },
3557  { 1, OperandInfo42 },
3558  { 5, OperandInfo47 },
3559  { 5, OperandInfo47 },
3560  { 5, OperandInfo48 },
3561  { 5, OperandInfo47 },
3562  { 3, OperandInfo4 },
3563  { 4, OperandInfo49 },
3564  { 1, OperandInfo3 },
3565  { 2, OperandInfo7 },
3566  { 0, nullptr },
3567  { 2, OperandInfo31 },
3568  { 2, OperandInfo31 },
3569  { 2, OperandInfo31 },
3570  { 0, nullptr },
3571  { 3, OperandInfo4 },
3572  { 3, OperandInfo4 },
3573  { 3, OperandInfo4 },
3574  { 3, OperandInfo4 },
3575  { 5, OperandInfo50 },
3576  { 4, OperandInfo51 },
3577  { 4, OperandInfo52 },
3578  { 2, OperandInfo46 },
3579  { 2, OperandInfo46 },
3580  { 2, OperandInfo46 },
3581  { 4, OperandInfo51 },
3582  { 4, OperandInfo53 },
3583  { 4, OperandInfo53 },
3584  { 6, OperandInfo37 },
3585  { 6, OperandInfo38 },
3586  { 6, OperandInfo37 },
3587  { 6, OperandInfo38 },
3588  { 5, OperandInfo54 },
3589  { 7, OperandInfo55 },
3590  { 5, OperandInfo56 },
3591  { 5, OperandInfo56 },
3592  { 5, OperandInfo57 },
3593  { 5, OperandInfo58 },
3594  { 6, OperandInfo59 },
3595  { 7, OperandInfo60 },
3596  { 1, OperandInfo61 },
3597  { 4, OperandInfo62 },
3598  { 2, OperandInfo46 },
3599  { 2, OperandInfo46 },
3600  { 3, OperandInfo63 },
3601  { 2, OperandInfo46 },
3602  { 2, OperandInfo31 },
3603  { 2, OperandInfo31 },
3604  { 6, OperandInfo64 },
3605  { 5, OperandInfo56 },
3606  { 5, OperandInfo32 },
3607  { 5, OperandInfo65 },
3608  { 5, OperandInfo65 },
3609  { 5, OperandInfo65 },
3610  { 5, OperandInfo65 },
3611  { 5, OperandInfo65 },
3612  { 5, OperandInfo65 },
3613  { 5, OperandInfo65 },
3614  { 5, OperandInfo65 },
3615  { 6, OperandInfo37 },
3616  { 6, OperandInfo38 },
3617  { 2, OperandInfo31 },
3618  { 5, OperandInfo66 },
3619  { 5, OperandInfo32 },
3620  { 6, OperandInfo34 },
3621  { 7, OperandInfo35 },
3622  { 9, OperandInfo67 },
3623  { 7, OperandInfo68 },
3624  { 3, OperandInfo69 },
3625  { 4, OperandInfo51 },
3626  { 7, OperandInfo70 },
3627  { 7, OperandInfo70 },
3628  { 7, OperandInfo71 },
3629  { 4, OperandInfo51 },
3630  { 7, OperandInfo70 },
3631  { 7, OperandInfo70 },
3632  { 3, OperandInfo72 },
3633  { 5, OperandInfo32 },
3634  { 5, OperandInfo33 },
3635  { 6, OperandInfo34 },
3636  { 7, OperandInfo35 },
3637  { 1, OperandInfo39 },
3638  { 1, OperandInfo73 },
3639  { 1, OperandInfo61 },
3640  { 1, OperandInfo3 },
3641  { 1, OperandInfo73 },
3642  { 0, nullptr },
3643  { 9, OperandInfo67 },
3644  { 7, OperandInfo68 },
3645  { 6, OperandInfo74 },
3646  { 6, OperandInfo74 },
3647  { 6, OperandInfo74 },
3648  { 6, OperandInfo74 },
3649  { 6, OperandInfo74 },
3650  { 6, OperandInfo74 },
3651  { 7, OperandInfo75 },
3652  { 7, OperandInfo75 },
3653  { 7, OperandInfo75 },
3654  { 6, OperandInfo74 },
3655  { 6, OperandInfo74 },
3656  { 6, OperandInfo74 },
3657  { 6, OperandInfo74 },
3658  { 6, OperandInfo74 },
3659  { 6, OperandInfo74 },
3660  { 7, OperandInfo75 },
3661  { 7, OperandInfo75 },
3662  { 7, OperandInfo75 },
3663  { 6, OperandInfo74 },
3664  { 6, OperandInfo74 },
3665  { 6, OperandInfo74 },
3666  { 6, OperandInfo74 },
3667  { 7, OperandInfo75 },
3668  { 7, OperandInfo75 },
3669  { 5, OperandInfo76 },
3670  { 5, OperandInfo76 },
3671  { 5, OperandInfo76 },
3672  { 5, OperandInfo76 },
3673  { 5, OperandInfo76 },
3674  { 5, OperandInfo76 },
3675  { 6, OperandInfo77 },
3676  { 6, OperandInfo77 },
3677  { 6, OperandInfo77 },
3678  { 5, OperandInfo76 },
3679  { 5, OperandInfo76 },
3680  { 5, OperandInfo76 },
3681  { 5, OperandInfo76 },
3682  { 5, OperandInfo76 },
3683  { 5, OperandInfo76 },
3684  { 6, OperandInfo77 },
3685  { 6, OperandInfo77 },
3686  { 6, OperandInfo77 },
3687  { 6, OperandInfo74 },
3688  { 6, OperandInfo74 },
3689  { 6, OperandInfo74 },
3690  { 6, OperandInfo74 },
3691  { 6, OperandInfo74 },
3692  { 6, OperandInfo74 },
3693  { 7, OperandInfo75 },
3694  { 7, OperandInfo75 },
3695  { 7, OperandInfo75 },
3696  { 6, OperandInfo74 },
3697  { 6, OperandInfo74 },
3698  { 6, OperandInfo74 },
3699  { 6, OperandInfo74 },
3700  { 7, OperandInfo75 },
3701  { 7, OperandInfo75 },
3702  { 5, OperandInfo76 },
3703  { 5, OperandInfo76 },
3704  { 5, OperandInfo76 },
3705  { 5, OperandInfo76 },
3706  { 5, OperandInfo76 },
3707  { 5, OperandInfo76 },
3708  { 6, OperandInfo77 },
3709  { 6, OperandInfo77 },
3710  { 6, OperandInfo77 },
3711  { 5, OperandInfo76 },
3712  { 5, OperandInfo76 },
3713  { 5, OperandInfo76 },
3714  { 5, OperandInfo76 },
3715  { 5, OperandInfo76 },
3716  { 5, OperandInfo76 },
3717  { 6, OperandInfo77 },
3718  { 6, OperandInfo77 },
3719  { 6, OperandInfo77 },
3720  { 5, OperandInfo76 },
3721  { 5, OperandInfo76 },
3722  { 5, OperandInfo76 },
3723  { 5, OperandInfo76 },
3724  { 5, OperandInfo76 },
3725  { 5, OperandInfo76 },
3726  { 6, OperandInfo77 },
3727  { 6, OperandInfo77 },
3728  { 6, OperandInfo77 },
3729  { 5, OperandInfo76 },
3730  { 5, OperandInfo76 },
3731  { 5, OperandInfo76 },
3732  { 5, OperandInfo76 },
3733  { 5, OperandInfo76 },
3734  { 5, OperandInfo76 },
3735  { 6, OperandInfo77 },
3736  { 6, OperandInfo77 },
3737  { 6, OperandInfo77 },
3738  { 6, OperandInfo74 },
3739  { 6, OperandInfo74 },
3740  { 6, OperandInfo74 },
3741  { 6, OperandInfo74 },
3742  { 6, OperandInfo74 },
3743  { 6, OperandInfo74 },
3744  { 7, OperandInfo75 },
3745  { 7, OperandInfo75 },
3746  { 7, OperandInfo75 },
3747  { 6, OperandInfo74 },
3748  { 6, OperandInfo74 },
3749  { 6, OperandInfo74 },
3750  { 6, OperandInfo74 },
3751  { 7, OperandInfo75 },
3752  { 7, OperandInfo75 },
3753  { 5, OperandInfo76 },
3754  { 5, OperandInfo76 },
3755  { 5, OperandInfo76 },
3756  { 5, OperandInfo76 },
3757  { 5, OperandInfo76 },
3758  { 5, OperandInfo76 },
3759  { 6, OperandInfo77 },
3760  { 6, OperandInfo77 },
3761  { 6, OperandInfo77 },
3762  { 5, OperandInfo76 },
3763  { 5, OperandInfo76 },
3764  { 5, OperandInfo76 },
3765  { 5, OperandInfo76 },
3766  { 5, OperandInfo76 },
3767  { 5, OperandInfo76 },
3768  { 6, OperandInfo77 },
3769  { 6, OperandInfo77 },
3770  { 6, OperandInfo77 },
3771  { 1, OperandInfo78 },
3772  { 5, OperandInfo79 },
3773  { 1, OperandInfo80 },
3774  { 5, OperandInfo81 },
3775  { 6, OperandInfo74 },
3776  { 6, OperandInfo74 },
3777  { 6, OperandInfo74 },
3778  { 6, OperandInfo74 },
3779  { 6, OperandInfo74 },
3780  { 6, OperandInfo74 },
3781  { 7, OperandInfo75 },
3782  { 7, OperandInfo75 },
3783  { 7, OperandInfo75 },
3784  { 6, OperandInfo74 },
3785  { 6, OperandInfo74 },
3786  { 6, OperandInfo74 },
3787  { 6, OperandInfo74 },
3788  { 6, OperandInfo74 },
3789  { 6, OperandInfo74 },
3790  { 7, OperandInfo75 },
3791  { 7, OperandInfo75 },
3792  { 7, OperandInfo75 },
3793  { 6, OperandInfo74 },
3794  { 6, OperandInfo74 },
3795  { 6, OperandInfo74 },
3796  { 6, OperandInfo74 },
3797  { 7, OperandInfo75 },
3798  { 7, OperandInfo75 },
3799  { 6, OperandInfo74 },
3800  { 6, OperandInfo74 },
3801  { 6, OperandInfo74 },
3802  { 6, OperandInfo74 },
3803  { 6, OperandInfo74 },
3804  { 6, OperandInfo74 },
3805  { 7, OperandInfo75 },
3806  { 7, OperandInfo75 },
3807  { 7, OperandInfo75 },
3808  { 6, OperandInfo74 },
3809  { 6, OperandInfo74 },
3810  { 6, OperandInfo74 },
3811  { 6, OperandInfo74 },
3812  { 7, OperandInfo75 },
3813  { 7, OperandInfo75 },
3814  { 5, OperandInfo76 },
3815  { 5, OperandInfo76 },
3816  { 5, OperandInfo76 },
3817  { 5, OperandInfo76 },
3818  { 5, OperandInfo76 },
3819  { 5, OperandInfo76 },
3820  { 6, OperandInfo77 },
3821  { 6, OperandInfo77 },
3822  { 6, OperandInfo77 },
3823  { 5, OperandInfo76 },
3824  { 5, OperandInfo76 },
3825  { 5, OperandInfo76 },
3826  { 5, OperandInfo76 },
3827  { 5, OperandInfo76 },
3828  { 5, OperandInfo76 },
3829  { 6, OperandInfo77 },
3830  { 6, OperandInfo77 },
3831  { 6, OperandInfo77 },
3832  { 6, OperandInfo74 },
3833  { 6, OperandInfo74 },
3834  { 6, OperandInfo74 },
3835  { 6, OperandInfo74 },
3836  { 6, OperandInfo74 },
3837  { 6, OperandInfo74 },
3838  { 7, OperandInfo75 },
3839  { 7, OperandInfo75 },
3840  { 7, OperandInfo75 },
3841  { 6, OperandInfo74 },
3842  { 6, OperandInfo74 },
3843  { 6, OperandInfo74 },
3844  { 6, OperandInfo74 },
3845  { 7, OperandInfo75 },
3846  { 7, OperandInfo75 },
3847  { 5, OperandInfo76 },
3848  { 5, OperandInfo76 },
3849  { 5, OperandInfo76 },
3850  { 5, OperandInfo76 },
3851  { 5, OperandInfo76 },
3852  { 5, OperandInfo76 },
3853  { 6, OperandInfo77 },
3854  { 6, OperandInfo77 },
3855  { 6, OperandInfo77 },
3856  { 5, OperandInfo76 },
3857  { 5, OperandInfo76 },
3858  { 5, OperandInfo76 },
3859  { 5, OperandInfo76 },
3860  { 5, OperandInfo76 },
3861  { 5, OperandInfo76 },
3862  { 6, OperandInfo77 },
3863  { 6, OperandInfo77 },
3864  { 6, OperandInfo77 },
3865  { 0, nullptr },
3866  { 1, OperandInfo42 },
3867  { 2, OperandInfo82 },
3868  { 5, OperandInfo83 },
3869  { 5, OperandInfo84 },
3870  { 6, OperandInfo85 },
3871  { 3, OperandInfo43 },
3872  { 5, OperandInfo50 },
3873  { 4, OperandInfo86 },
3874  { 4, OperandInfo52 },
3875  { 4, OperandInfo86 },
3876  { 4, OperandInfo86 },
3877  { 4, OperandInfo86 },
3878  { 3, OperandInfo87 },
3879  { 4, OperandInfo52 },
3880  { 4, OperandInfo88 },
3881  { 4, OperandInfo88 },
3882  { 6, OperandInfo89 },
3883  { 5, OperandInfo90 },
3884  { 5, OperandInfo90 },
3885  { 5, OperandInfo91 },
3886  { 6, OperandInfo89 },
3887  { 6, OperandInfo89 },
3888  { 5, OperandInfo92 },
3889  { 6, OperandInfo89 },
3890  { 5, OperandInfo93 },
3891  { 6, OperandInfo94 },
3892  { 4, OperandInfo95 },
3893  { 2, OperandInfo96 },
3894  { 3, OperandInfo87 },
3895  { 2, OperandInfo96 },
3896  { 5, OperandInfo93 },
3897  { 6, OperandInfo94 },
3898  { 5, OperandInfo90 },
3899  { 5, OperandInfo97 },
3900  { 6, OperandInfo98 },
3901  { 6, OperandInfo99 },
3902  { 6, OperandInfo99 },
3903  { 6, OperandInfo99 },
3904  { 5, OperandInfo83 },
3905  { 5, OperandInfo84 },
3906  { 6, OperandInfo85 },
3907  { 4, OperandInfo49 },
3908  { 4, OperandInfo49 },
3909  { 3, OperandInfo100 },
3910  { 3, OperandInfo101 },
3911  { 3, OperandInfo101 },
3912  { 3, OperandInfo100 },
3913  { 3, OperandInfo102 },
3914  { 2, OperandInfo8 },
3915  { 2, OperandInfo8 },
3916  { 3, OperandInfo103 },
3917  { 2, OperandInfo104 },
3918  { 1, OperandInfo42 },
3919  { 2, OperandInfo105 },
3920  { 3, OperandInfo106 },
3921  { 3, OperandInfo107 },
3922  { 5, OperandInfo50 },
3923  { 4, OperandInfo108 },
3924  { 2, OperandInfo104 },
3925  { 2, OperandInfo104 },
3926  { 5, OperandInfo109 },
3927  { 3, OperandInfo63 },
3928  { 4, OperandInfo110 },
3929  { 4, OperandInfo110 },
3930  { 5, OperandInfo111 },
3931  { 3, OperandInfo112 },
3932  { 3, OperandInfo100 },
3933  { 3, OperandInfo101 },
3934  { 3, OperandInfo101 },
3935  { 3, OperandInfo100 },
3936  { 3, OperandInfo107 },
3937  { 3, OperandInfo107 },
3938  { 1, OperandInfo73 },
3939  { 4, OperandInfo113 },
3940  { 4, OperandInfo113 },
3941  { 0, nullptr },
3942  { 6, OperandInfo37 },
3943  { 6, OperandInfo114 },
3944  { 7, OperandInfo115 },
3945  { 8, OperandInfo116 },
3946  { 6, OperandInfo37 },
3947  { 6, OperandInfo114 },
3948  { 7, OperandInfo115 },
3949  { 8, OperandInfo117 },
3950  { 4, OperandInfo52 },
3951  { 3, OperandInfo118 },
3952  { 3, OperandInfo118 },
3953  { 2, OperandInfo119 },
3954  { 2, OperandInfo119 },
3955  { 6, OperandInfo37 },
3956  { 6, OperandInfo114 },
3957  { 7, OperandInfo115 },
3958  { 8, OperandInfo117 },
3959  { 5, OperandInfo56 },
3960  { 6, OperandInfo120 },
3961  { 6, OperandInfo37 },
3962  { 6, OperandInfo114 },
3963  { 7, OperandInfo115 },
3964  { 8, OperandInfo117 },
3965  { 1, OperandInfo2 },
3966  { 1, OperandInfo39 },
3967  { 1, OperandInfo61 },
3968  { 3, OperandInfo103 },
3969  { 1, OperandInfo39 },
3970  { 3, OperandInfo107 },
3971  { 1, OperandInfo61 },
3972  { 3, OperandInfo103 },
3973  { 2, OperandInfo105 },
3974  { 3, OperandInfo103 },
3975  { 3, OperandInfo107 },
3976  { 8, OperandInfo121 },
3977  { 6, OperandInfo122 },
3978  { 0, nullptr },
3979  { 4, OperandInfo123 },
3980  { 4, OperandInfo52 },
3981  { 4, OperandInfo123 },
3982  { 5, OperandInfo124 },
3983  { 6, OperandInfo125 },
3984  { 4, OperandInfo52 },
3985  { 4, OperandInfo123 },
3986  { 5, OperandInfo124 },
3987  { 6, OperandInfo125 },
3988  { 1, OperandInfo2 },
3989  { 2, OperandInfo7 },
3990  { 3, OperandInfo126 },
3991  { 3, OperandInfo127 },
3992  { 3, OperandInfo127 },
3993  { 3, OperandInfo127 },
3994  { 3, OperandInfo127 },
3995  { 3, OperandInfo127 },
3996  { 3, OperandInfo127 },
3997  { 3, OperandInfo128 },
3998  { 1, OperandInfo2 },
3999  { 1, OperandInfo2 },
4000  { 6, OperandInfo37 },
4001  { 6, OperandInfo114 },
4002  { 7, OperandInfo115 },
4003  { 8, OperandInfo117 },
4004  { 2, OperandInfo105 },
4005  { 4, OperandInfo129 },
4006  { 4, OperandInfo130 },
4007  { 4, OperandInfo131 },
4008  { 5, OperandInfo50 },
4009  { 4, OperandInfo132 },
4010  { 5, OperandInfo50 },
4011  { 2, OperandInfo105 },
4012  { 5, OperandInfo50 },
4013  { 4, OperandInfo132 },
4014  { 5, OperandInfo50 },
4015  { 3, OperandInfo128 },
4016  { 1, OperandInfo2 },
4017  { 1, OperandInfo2 },
4018  { 1, OperandInfo2 },
4019  { 4, OperandInfo51 },
4020  { 4, OperandInfo51 },
4021  { 4, OperandInfo51 },
4022  { 4, OperandInfo51 },
4023  { 4, OperandInfo133 },
4024  { 4, OperandInfo51 },
4025  { 4, OperandInfo51 },
4026  { 4, OperandInfo134 },
4027  { 4, OperandInfo135 },
4028  { 4, OperandInfo134 },
4029  { 4, OperandInfo134 },
4030  { 4, OperandInfo134 },
4031  { 4, OperandInfo135 },
4032  { 4, OperandInfo134 },
4033  { 4, OperandInfo134 },
4034  { 6, OperandInfo136 },
4035  { 6, OperandInfo137 },
4036  { 6, OperandInfo136 },
4037  { 6, OperandInfo136 },
4038  { 6, OperandInfo136 },
4039  { 6, OperandInfo137 },
4040  { 6, OperandInfo136 },
4041  { 6, OperandInfo136 },
4042  { 4, OperandInfo132 },
4043  { 5, OperandInfo50 },
4044  { 4, OperandInfo132 },
4045  { 5, OperandInfo50 },
4046  { 4, OperandInfo132 },
4047  { 5, OperandInfo50 },
4048  { 4, OperandInfo132 },
4049  { 5, OperandInfo50 },
4050  { 7, OperandInfo138 },
4051  { 7, OperandInfo138 },
4052  { 7, OperandInfo138 },
4053  { 7, OperandInfo138 },
4054  { 6, OperandInfo139 },
4055  { 7, OperandInfo138 },
4056  { 5, OperandInfo140 },
4057  { 6, OperandInfo141 },
4058  { 7, OperandInfo142 },
4059  { 8, OperandInfo143 },
4060  { 8, OperandInfo143 },
4061  { 4, OperandInfo51 },
4062  { 4, OperandInfo51 },
4063  { 4, OperandInfo133 },
4064  { 4, OperandInfo51 },
4065  { 6, OperandInfo144 },
4066  { 6, OperandInfo139 },
4067  { 7, OperandInfo145 },
4068  { 7, OperandInfo146 },
4069  { 7, OperandInfo146 },
4070  { 6, OperandInfo144 },
4071  { 6, OperandInfo139 },
4072  { 7, OperandInfo145 },
4073  { 7, OperandInfo146 },
4074  { 7, OperandInfo146 },
4075  { 6, OperandInfo144 },
4076  { 6, OperandInfo139 },
4077  { 7, OperandInfo145 },
4078  { 7, OperandInfo146 },
4079  { 7, OperandInfo146 },
4080  { 7, OperandInfo138 },
4081  { 7, OperandInfo138 },
4082  { 7, OperandInfo138 },
4083  { 7, OperandInfo138 },
4084  { 6, OperandInfo139 },
4085  { 7, OperandInfo138 },
4086  { 5, OperandInfo65 },
4087  { 5, OperandInfo65 },
4088  { 6, OperandInfo147 },
4089  { 8, OperandInfo148 },
4090  { 6, OperandInfo149 },
4091  { 7, OperandInfo150 },
4092  { 5, OperandInfo151 },
4093  { 7, OperandInfo152 },
4094  { 6, OperandInfo153 },
4095  { 2, OperandInfo105 },
4096  { 5, OperandInfo154 },
4097  { 5, OperandInfo155 },
4098  { 4, OperandInfo52 },
4099  { 5, OperandInfo66 },
4100  { 5, OperandInfo156 },
4101  { 6, OperandInfo157 },
4102  { 7, OperandInfo158 },
4103  { 8, OperandInfo159 },
4104  { 6, OperandInfo160 },
4105  { 7, OperandInfo161 },
4106  { 5, OperandInfo162 },
4107  { 3, OperandInfo163 },
4108  { 4, OperandInfo86 },
4109  { 3, OperandInfo163 },
4110  { 4, OperandInfo164 },
4111  { 4, OperandInfo165 },
4112  { 4, OperandInfo166 },
4113  { 6, OperandInfo38 },
4114  { 5, OperandInfo155 },
4115  { 5, OperandInfo66 },
4116  { 6, OperandInfo157 },
4117  { 7, OperandInfo167 },
4118  { 6, OperandInfo37 },
4119  { 6, OperandInfo114 },
4120  { 7, OperandInfo115 },
4121  { 8, OperandInfo117 },
4122  { 6, OperandInfo168 },
4123  { 6, OperandInfo168 },
4124  { 2, OperandInfo169 },
4125  { 3, OperandInfo170 },
4126  { 2, OperandInfo169 },
4127  { 3, OperandInfo170 },
4128  { 2, OperandInfo169 },
4129  { 3, OperandInfo170 },
4130  { 5, OperandInfo171 },
4131  { 5, OperandInfo171 },
4132  { 5, OperandInfo171 },
4133  { 5, OperandInfo171 },
4134  { 5, OperandInfo171 },
4135  { 5, OperandInfo171 },
4136  { 5, OperandInfo171 },
4137  { 5, OperandInfo171 },
4138  { 5, OperandInfo171 },
4139  { 5, OperandInfo171 },
4140  { 4, OperandInfo123 },
4141  { 4, OperandInfo123 },
4142  { 4, OperandInfo123 },
4143  { 4, OperandInfo123 },
4144  { 1, OperandInfo61 },
4145  { 1, OperandInfo61 },
4146  { 1, OperandInfo61 },
4147  { 1, OperandInfo61 },
4148  { 1, OperandInfo61 },
4149  { 1, OperandInfo61 },
4150  { 1, OperandInfo61 },
4151  { 1, OperandInfo61 },
4152  { 6, OperandInfo37 },
4153  { 6, OperandInfo114 },
4154  { 7, OperandInfo115 },
4155  { 8, OperandInfo117 },
4156  { 6, OperandInfo37 },
4157  { 6, OperandInfo114 },
4158  { 7, OperandInfo115 },
4159  { 8, OperandInfo117 },
4160  { 5, OperandInfo171 },
4161  { 5, OperandInfo171 },
4162  { 5, OperandInfo171 },
4163  { 6, OperandInfo37 },
4164  { 6, OperandInfo114 },
4165  { 7, OperandInfo115 },
4166  { 8, OperandInfo116 },
4167  { 6, OperandInfo172 },
4168  { 5, OperandInfo33 },
4169  { 5, OperandInfo33 },
4170  { 1, OperandInfo2 },
4171  { 1, OperandInfo2 },
4172  { 4, OperandInfo173 },
4173  { 2, OperandInfo119 },
4174  { 4, OperandInfo173 },
4175  { 4, OperandInfo173 },
4176  { 4, OperandInfo173 },
4177  { 3, OperandInfo118 },
4178  { 4, OperandInfo173 },
4179  { 4, OperandInfo173 },
4180  { 3, OperandInfo118 },
4181  { 4, OperandInfo173 },
4182  { 5, OperandInfo171 },
4183  { 5, OperandInfo171 },
4184  { 5, OperandInfo171 },
4185  { 5, OperandInfo171 },
4186  { 5, OperandInfo171 },
4187  { 5, OperandInfo171 },
4188  { 3, OperandInfo128 },
4189  { 6, OperandInfo174 },
4190  { 6, OperandInfo174 },
4191  { 6, OperandInfo174 },
4192  { 6, OperandInfo174 },
4193  { 9, OperandInfo175 },
4194  { 8, OperandInfo176 },
4195  { 8, OperandInfo176 },
4196  { 8, OperandInfo176 },
4197  { 8, OperandInfo176 },
4198  { 8, OperandInfo176 },
4199  { 8, OperandInfo176 },
4200  { 6, OperandInfo174 },
4201  { 6, OperandInfo174 },
4202  { 6, OperandInfo174 },
4203  { 6, OperandInfo174 },
4204  { 6, OperandInfo174 },
4205  { 6, OperandInfo174 },
4206  { 8, OperandInfo176 },
4207  { 8, OperandInfo176 },
4208  { 6, OperandInfo153 },
4209  { 6, OperandInfo153 },
4210  { 6, OperandInfo153 },
4211  { 6, OperandInfo153 },
4212  { 5, OperandInfo33 },
4213  { 5, OperandInfo33 },
4214  { 5, OperandInfo171 },
4215  { 5, OperandInfo171 },
4216  { 5, OperandInfo33 },
4217  { 5, OperandInfo33 },
4218  { 7, OperandInfo177 },
4219  { 5, OperandInfo33 },
4220  { 5, OperandInfo33 },
4221  { 5, OperandInfo33 },
4222  { 5, OperandInfo33 },
4223  { 5, OperandInfo171 },
4224  { 5, OperandInfo171 },
4225  { 1, OperandInfo2 },
4226  { 1, OperandInfo2 },
4227  { 1, OperandInfo2 },
4228  { 1, OperandInfo2 },
4229  { 1, OperandInfo2 },
4230  { 1, OperandInfo2 },
4231  { 1, OperandInfo2 },
4232  { 1, OperandInfo2 },
4233  { 6, OperandInfo178 },
4234  { 5, OperandInfo179 },
4235  { 5, OperandInfo171 },
4236  { 5, OperandInfo171 },
4237  { 5, OperandInfo171 },
4238  { 4, OperandInfo134 },
4239  { 4, OperandInfo135 },
4240  { 4, OperandInfo134 },
4241  { 4, OperandInfo134 },
4242  { 4, OperandInfo134 },
4243  { 4, OperandInfo135 },
4244  { 4, OperandInfo134 },
4245  { 4, OperandInfo134 },
4246  { 6, OperandInfo136 },
4247  { 6, OperandInfo137 },
4248  { 6, OperandInfo136 },
4249  { 6, OperandInfo136 },
4250  { 6, OperandInfo136 },
4251  { 6, OperandInfo137 },
4252  { 6, OperandInfo136 },
4253  { 6, OperandInfo136 },
4254  { 4, OperandInfo51 },
4255  { 4, OperandInfo51 },
4256  { 5, OperandInfo180 },
4257  { 5, OperandInfo180 },
4258  { 5, OperandInfo181 },
4259  { 5, OperandInfo180 },
4260  { 4, OperandInfo51 },
4261  { 4, OperandInfo132 },
4262  { 5, OperandInfo50 },
4263  { 4, OperandInfo132 },
4264  { 5, OperandInfo50 },
4265  { 4, OperandInfo132 },
4266  { 5, OperandInfo50 },
4267  { 4, OperandInfo132 },
4268  { 5, OperandInfo50 },
4269  { 7, OperandInfo182 },
4270  { 7, OperandInfo182 },
4271  { 7, OperandInfo183 },
4272  { 7, OperandInfo183 },
4273  { 6, OperandInfo184 },
4274  { 7, OperandInfo183 },
4275  { 5, OperandInfo140 },
4276  { 6, OperandInfo141 },
4277  { 7, OperandInfo142 },
4278  { 8, OperandInfo185 },
4279  { 8, OperandInfo185 },
4280  { 5, OperandInfo180 },
4281  { 5, OperandInfo180 },
4282  { 5, OperandInfo181 },
4283  { 5, OperandInfo180 },
4284  { 6, OperandInfo144 },
4285  { 6, OperandInfo186 },
4286  { 7, OperandInfo182 },
4287  { 7, OperandInfo187 },
4288  { 7, OperandInfo187 },
4289  { 7, OperandInfo182 },
4290  { 7, OperandInfo182 },
4291  { 7, OperandInfo183 },
4292  { 7, OperandInfo183 },
4293  { 6, OperandInfo184 },
4294  { 7, OperandInfo183 },
4295  { 5, OperandInfo65 },
4296  { 6, OperandInfo147 },
4297  { 6, OperandInfo37 },
4298  { 6, OperandInfo114 },
4299  { 7, OperandInfo115 },
4300  { 8, OperandInfo117 },
4301  { 3, OperandInfo128 },
4302  { 5, OperandInfo188 },
4303  { 5, OperandInfo188 },
4304  { 6, OperandInfo189 },
4305  { 6, OperandInfo189 },
4306  { 6, OperandInfo189 },
4307  { 5, OperandInfo190 },
4308  { 5, OperandInfo190 },
4309  { 5, OperandInfo190 },
4310  { 4, OperandInfo52 },
4311  { 4, OperandInfo123 },
4312  { 5, OperandInfo124 },
4313  { 6, OperandInfo125 },
4314  { 0, nullptr },
4315  { 0, nullptr },
4316  { 1, OperandInfo2 },
4317  { 4, OperandInfo52 },
4318  { 4, OperandInfo123 },
4319  { 5, OperandInfo124 },
4320  { 6, OperandInfo125 },
4321  { 5, OperandInfo171 },
4322  { 5, OperandInfo171 },
4323  { 5, OperandInfo171 },
4324  { 6, OperandInfo172 },
4325  { 1, OperandInfo2 },
4326  { 5, OperandInfo33 },
4327  { 5, OperandInfo171 },
4328  { 5, OperandInfo171 },
4329  { 5, OperandInfo171 },
4330  { 5, OperandInfo171 },
4331  { 5, OperandInfo171 },
4332  { 5, OperandInfo171 },
4333  { 8, OperandInfo191 },
4334  { 9, OperandInfo175 },
4335  { 7, OperandInfo177 },
4336  { 5, OperandInfo171 },
4337  { 5, OperandInfo171 },
4338  { 5, OperandInfo171 },
4339  { 5, OperandInfo171 },
4340  { 5, OperandInfo171 },
4341  { 5, OperandInfo171 },
4342  { 5, OperandInfo33 },
4343  { 6, OperandInfo153 },
4344  { 6, OperandInfo178 },
4345  { 5, OperandInfo179 },
4346  { 5, OperandInfo171 },
4347  { 5, OperandInfo171 },
4348  { 5, OperandInfo171 },
4349  { 6, OperandInfo189 },
4350  { 6, OperandInfo189 },
4351  { 6, OperandInfo189 },
4352  { 5, OperandInfo190 },
4353  { 5, OperandInfo190 },
4354  { 5, OperandInfo190 },
4355  { 6, OperandInfo192 },
4356  { 6, OperandInfo192 },
4357  { 6, OperandInfo192 },
4358  { 6, OperandInfo192 },
4359  { 6, OperandInfo192 },
4360  { 6, OperandInfo192 },
4361  { 6, OperandInfo193 },
4362  { 6, OperandInfo194 },
4363  { 6, OperandInfo194 },
4364  { 6, OperandInfo193 },
4365  { 6, OperandInfo193 },
4366  { 6, OperandInfo194 },
4367  { 6, OperandInfo193 },
4368  { 6, OperandInfo194 },
4369  { 6, OperandInfo194 },
4370  { 6, OperandInfo193 },
4371  { 6, OperandInfo193 },
4372  { 6, OperandInfo194 },
4373  { 5, OperandInfo195 },
4374  { 5, OperandInfo195 },
4375  { 5, OperandInfo195 },
4376  { 5, OperandInfo195 },
4377  { 5, OperandInfo195 },
4378  { 5, OperandInfo195 },
4379  { 5, OperandInfo196 },
4380  { 5, OperandInfo197 },
4381  { 5, OperandInfo196 },
4382  { 5, OperandInfo197 },
4383  { 5, OperandInfo197 },
4384  { 5, OperandInfo196 },
4385  { 5, OperandInfo196 },
4386  { 5, OperandInfo197 },
4387  { 5, OperandInfo197 },
4388  { 5, OperandInfo196 },
4389  { 5, OperandInfo197 },
4390  { 5, OperandInfo196 },
4391  { 5, OperandInfo196 },
4392  { 5, OperandInfo197 },
4393  { 5, OperandInfo197 },
4394  { 5, OperandInfo196 },
4395  { 4, OperandInfo198 },
4396  { 4, OperandInfo199 },
4397  { 4, OperandInfo199 },
4398  { 4, OperandInfo198 },
4399  { 4, OperandInfo200 },
4400  { 4, OperandInfo198 },
4401  { 4, OperandInfo200 },
4402  { 4, OperandInfo200 },
4403  { 4, OperandInfo198 },
4404  { 4, OperandInfo198 },
4405  { 4, OperandInfo200 },
4406  { 4, OperandInfo200 },
4407  { 4, OperandInfo198 },
4408  { 5, OperandInfo196 },
4409  { 5, OperandInfo197 },
4410  { 5, OperandInfo196 },
4411  { 5, OperandInfo197 },
4412  { 5, OperandInfo196 },
4413  { 5, OperandInfo197 },
4414  { 5, OperandInfo196 },
4415  { 5, OperandInfo197 },
4416  { 5, OperandInfo196 },
4417  { 5, OperandInfo201 },
4418  { 5, OperandInfo202 },
4419  { 5, OperandInfo202 },
4420  { 5, OperandInfo202 },
4421  { 5, OperandInfo195 },
4422  { 5, OperandInfo195 },
4423  { 5, OperandInfo195 },
4424  { 5, OperandInfo195 },
4425  { 5, OperandInfo195 },
4426  { 5, OperandInfo195 },
4427  { 5, OperandInfo203 },
4428  { 5, OperandInfo204 },
4429  { 5, OperandInfo204 },
4430  { 5, OperandInfo204 },
4431  { 5, OperandInfo204 },
4432  { 5, OperandInfo204 },
4433  { 5, OperandInfo204 },
4434  { 5, OperandInfo196 },
4435  { 5, OperandInfo197 },
4436  { 5, OperandInfo196 },
4437  { 5, OperandInfo197 },
4438  { 5, OperandInfo197 },
4439  { 5, OperandInfo196 },
4440  { 5, OperandInfo196 },
4441  { 5, OperandInfo197 },
4442  { 5, OperandInfo196 },
4443  { 5, OperandInfo197 },
4444  { 5, OperandInfo197 },
4445  { 5, OperandInfo196 },
4446  { 5, OperandInfo196 },
4447  { 5, OperandInfo197 },
4448  { 5, OperandInfo196 },
4449  { 5, OperandInfo205 },
4450  { 5, OperandInfo205 },
4451  { 5, OperandInfo206 },
4452  { 5, OperandInfo206 },
4453  { 5, OperandInfo197 },
4454  { 6, OperandInfo194 },
4455  { 6, OperandInfo193 },
4456  { 6, OperandInfo194 },
4457  { 6, OperandInfo193 },
4458  { 6, OperandInfo194 },
4459  { 6, OperandInfo193 },
4460  { 4, OperandInfo207 },
4461  { 4, OperandInfo207 },
4462  { 4, OperandInfo208 },
4463  { 4, OperandInfo208 },
4464  { 5, OperandInfo196 },
4465  { 5, OperandInfo197 },
4466  { 5, OperandInfo196 },
4467  { 5, OperandInfo197 },
4468  { 5, OperandInfo197 },
4469  { 5, OperandInfo196 },
4470  { 5, OperandInfo196 },
4471  { 5, OperandInfo197 },
4472  { 5, OperandInfo197 },
4473  { 5, OperandInfo196 },
4474  { 4, OperandInfo200 },
4475  { 4, OperandInfo198 },
4476  { 4, OperandInfo198 },
4477  { 4, OperandInfo198 },
4478  { 4, OperandInfo200 },
4479  { 4, OperandInfo198 },
4480  { 4, OperandInfo200 },
4481  { 4, OperandInfo200 },
4482  { 4, OperandInfo200 },
4483  { 4, OperandInfo198 },
4484  { 5, OperandInfo196 },
4485  { 5, OperandInfo197 },
4486  { 5, OperandInfo196 },
4487  { 5, OperandInfo197 },
4488  { 5, OperandInfo197 },
4489  { 5, OperandInfo196 },
4490  { 5, OperandInfo196 },
4491  { 5, OperandInfo197 },
4492  { 5, OperandInfo197 },
4493  { 5, OperandInfo196 },
4494  { 5, OperandInfo197 },
4495  { 5, OperandInfo196 },
4496  { 5, OperandInfo196 },
4497  { 5, OperandInfo197 },
4498  { 5, OperandInfo197 },
4499  { 5, OperandInfo196 },
4500  { 4, OperandInfo200 },
4501  { 4, OperandInfo198 },
4502  { 4, OperandInfo198 },
4503  { 4, OperandInfo198 },
4504  { 4, OperandInfo200 },
4505  { 4, OperandInfo198 },
4506  { 4, OperandInfo200 },
4507  { 4, OperandInfo200 },
4508  { 4, OperandInfo200 },
4509  { 4, OperandInfo198 },
4510  { 5, OperandInfo196 },
4511  { 5, OperandInfo197 },
4512  { 5, OperandInfo196 },
4513  { 5, OperandInfo197 },
4514  { 5, OperandInfo197 },
4515  { 5, OperandInfo196 },
4516  { 5, OperandInfo196 },
4517  { 5, OperandInfo197 },
4518  { 5, OperandInfo197 },
4519  { 5, OperandInfo196 },
4520  { 5, OperandInfo197 },
4521  { 5, OperandInfo196 },
4522  { 5, OperandInfo196 },
4523  { 5, OperandInfo197 },
4524  { 5, OperandInfo197 },
4525  { 5, OperandInfo196 },
4526  { 4, OperandInfo200 },
4527  { 4, OperandInfo198 },
4528  { 4, OperandInfo198 },
4529  { 4, OperandInfo198 },
4530  { 4, OperandInfo200 },
4531  { 4, OperandInfo198 },
4532  { 4, OperandInfo200 },
4533  { 4, OperandInfo200 },
4534  { 4, OperandInfo200 },
4535  { 4, OperandInfo198 },
4536  { 4, OperandInfo200 },
4537  { 4, OperandInfo198 },
4538  { 4, OperandInfo198 },
4539  { 4, OperandInfo198 },
4540  { 4, OperandInfo200 },
4541  { 4, OperandInfo198 },
4542  { 4, OperandInfo200 },
4543  { 4, OperandInfo200 },
4544  { 4, OperandInfo200 },
4545  { 4, OperandInfo198 },
4546  { 4, OperandInfo200 },
4547  { 4, OperandInfo198 },
4548  { 4, OperandInfo198 },
4549  { 4, OperandInfo200 },
4550  { 4, OperandInfo200 },
4551  { 4, OperandInfo198 },
4552  { 4, OperandInfo200 },
4553  { 4, OperandInfo198 },
4554  { 4, OperandInfo198 },
4555  { 4, OperandInfo198 },
4556  { 4, OperandInfo200 },
4557  { 4, OperandInfo198 },
4558  { 4, OperandInfo200 },
4559  { 4, OperandInfo200 },
4560  { 4, OperandInfo200 },
4561  { 4, OperandInfo198 },
4562  { 4, OperandInfo200 },
4563  { 4, OperandInfo198 },
4564  { 4, OperandInfo198 },
4565  { 4, OperandInfo200 },
4566  { 4, OperandInfo200 },
4567  { 4, OperandInfo198 },
4568  { 5, OperandInfo209 },
4569  { 6, OperandInfo210 },
4570  { 5, OperandInfo209 },
4571  { 6, OperandInfo211 },
4572  { 5, OperandInfo212 },
4573  { 6, OperandInfo213 },
4574  { 5, OperandInfo212 },
4575  { 6, OperandInfo214 },
4576  { 4, OperandInfo198 },
4577  { 4, OperandInfo198 },
4578  { 4, OperandInfo215 },
4579  { 4, OperandInfo199 },
4580  { 3, OperandInfo216 },
4581  { 3, OperandInfo217 },
4582  { 3, OperandInfo218 },
4583  { 4, OperandInfo215 },
4584  { 4, OperandInfo199 },
4585  { 3, OperandInfo216 },
4586  { 3, OperandInfo217 },
4587  { 3, OperandInfo218 },
4588  { 4, OperandInfo198 },
4589  { 4, OperandInfo200 },
4590  { 2, OperandInfo219 },
4591  { 2, OperandInfo219 },
4592  { 2, OperandInfo119 },
4593  { 2, OperandInfo119 },
4594  { 2, OperandInfo219 },
4595  { 2, OperandInfo219 },
4596  { 2, OperandInfo119 },
4597  { 2, OperandInfo119 },
4598  { 2, OperandInfo220 },
4599  { 2, OperandInfo221 },
4600  { 2, OperandInfo222 },
4601  { 2, OperandInfo220 },
4602  { 2, OperandInfo221 },
4603  { 2, OperandInfo222 },
4604  { 4, OperandInfo223 },
4605  { 4, OperandInfo224 },
4606  { 4, OperandInfo199 },
4607  { 4, OperandInfo199 },
4608  { 4, OperandInfo224 },
4609  { 2, OperandInfo219 },
4610  { 2, OperandInfo219 },
4611  { 2, OperandInfo119 },
4612  { 2, OperandInfo119 },
4613  { 2, OperandInfo219 },
4614  { 2, OperandInfo219 },
4615  { 2, OperandInfo119 },
4616  { 2, OperandInfo119 },
4617  { 2, OperandInfo220 },
4618  { 2, OperandInfo221 },
4619  { 2, OperandInfo222 },
4620  { 2, OperandInfo220 },
4621  { 2, OperandInfo221 },
4622  { 2, OperandInfo222 },
4623  { 2, OperandInfo219 },
4624  { 2, OperandInfo219 },
4625  { 2, OperandInfo119 },
4626  { 2, OperandInfo119 },
4627  { 2, OperandInfo219 },
4628  { 2, OperandInfo219 },
4629  { 2, OperandInfo119 },
4630  { 2, OperandInfo119 },
4631  { 2, OperandInfo220 },
4632  { 2, OperandInfo221 },
4633  { 2, OperandInfo222 },
4634  { 2, OperandInfo220 },
4635  { 2, OperandInfo221 },
4636  { 2, OperandInfo222 },
4637  { 2, OperandInfo219 },
4638  { 2, OperandInfo219 },
4639  { 2, OperandInfo119 },
4640  { 2, OperandInfo119 },
4641  { 2, OperandInfo219 },
4642  { 2, OperandInfo219 },
4643  { 2, OperandInfo119 },
4644  { 2, OperandInfo119 },
4645  { 2, OperandInfo220 },
4646  { 2, OperandInfo221 },
4647  { 2, OperandInfo222 },
4648  { 2, OperandInfo220 },
4649  { 2, OperandInfo221 },
4650  { 2, OperandInfo222 },
4651  { 4, OperandInfo223 },
4652  { 4, OperandInfo223 },
4653  { 4, OperandInfo224 },
4654  { 4, OperandInfo199 },
4655  { 4, OperandInfo199 },
4656  { 4, OperandInfo225 },
4657  { 4, OperandInfo198 },
4658  { 4, OperandInfo200 },
4659  { 4, OperandInfo198 },
4660  { 4, OperandInfo200 },
4661  { 5, OperandInfo226 },
4662  { 5, OperandInfo227 },
4663  { 5, OperandInfo226 },
4664  { 5, OperandInfo227 },
4665  { 4, OperandInfo228 },
4666  { 4, OperandInfo198 },
4667  { 4, OperandInfo200 },
4668  { 4, OperandInfo198 },
4669  { 4, OperandInfo200 },
4670  { 5, OperandInfo226 },
4671  { 5, OperandInfo227 },
4672  { 5, OperandInfo226 },
4673  { 5, OperandInfo227 },
4674  { 4, OperandInfo198 },
4675  { 4, OperandInfo200 },
4676  { 4, OperandInfo198 },
4677  { 4, OperandInfo200 },
4678  { 4, OperandInfo198 },
4679  { 4, OperandInfo200 },
4680  { 4, OperandInfo198 },
4681  { 4, OperandInfo200 },
4682  { 5, OperandInfo226 },
4683  { 5, OperandInfo227 },
4684  { 5, OperandInfo226 },
4685  { 5, OperandInfo227 },
4686  { 5, OperandInfo226 },
4687  { 5, OperandInfo227 },
4688  { 5, OperandInfo226 },
4689  { 5, OperandInfo227 },
4690  { 5, OperandInfo196 },
4691  { 5, OperandInfo201 },
4692  { 5, OperandInfo203 },
4693  { 4, OperandInfo229 },
4694  { 4, OperandInfo230 },
4695  { 4, OperandInfo229 },
4696  { 4, OperandInfo230 },
4697  { 4, OperandInfo229 },
4698  { 4, OperandInfo230 },
4699  { 5, OperandInfo226 },
4700  { 5, OperandInfo231 },
4701  { 5, OperandInfo226 },
4702  { 5, OperandInfo231 },
4703  { 5, OperandInfo226 },
4704  { 5, OperandInfo231 },
4705  { 5, OperandInfo196 },
4706  { 5, OperandInfo197 },
4707  { 6, OperandInfo232 },
4708  { 6, OperandInfo232 },
4709  { 6, OperandInfo232 },
4710  { 6, OperandInfo233 },
4711  { 6, OperandInfo233 },
4712  { 6, OperandInfo233 },
4713  { 6, OperandInfo233 },
4714  { 6, OperandInfo194 },
4715  { 6, OperandInfo234 },
4716  { 6, OperandInfo235 },
4717  { 6, OperandInfo194 },
4718  { 6, OperandInfo193 },
4719  { 6, OperandInfo194 },
4720  { 6, OperandInfo193 },
4721  { 6, OperandInfo194 },
4722  { 6, OperandInfo234 },
4723  { 6, OperandInfo235 },
4724  { 6, OperandInfo194 },
4725  { 6, OperandInfo193 },
4726  { 6, OperandInfo194 },
4727  { 6, OperandInfo193 },
4728  { 6, OperandInfo194 },
4729  { 6, OperandInfo234 },
4730  { 6, OperandInfo235 },
4731  { 6, OperandInfo194 },
4732  { 6, OperandInfo234 },
4733  { 6, OperandInfo235 },
4734  { 5, OperandInfo236 },
4735  { 5, OperandInfo236 },
4736  { 5, OperandInfo236 },
4737  { 5, OperandInfo236 },
4738  { 5, OperandInfo236 },
4739  { 5, OperandInfo197 },
4740  { 5, OperandInfo196 },
4741  { 5, OperandInfo196 },
4742  { 5, OperandInfo197 },
4743  { 5, OperandInfo197 },
4744  { 5, OperandInfo196 },
4745  { 5, OperandInfo197 },
4746  { 5, OperandInfo196 },
4747  { 5, OperandInfo196 },
4748  { 5, OperandInfo197 },
4749  { 5, OperandInfo197 },
4750  { 5, OperandInfo196 },
4751  { 5, OperandInfo197 },
4752  { 5, OperandInfo196 },
4753  { 5, OperandInfo196 },
4754  { 5, OperandInfo197 },
4755  { 5, OperandInfo197 },
4756  { 5, OperandInfo196 },
4757  { 5, OperandInfo197 },
4758  { 5, OperandInfo196 },
4759  { 5, OperandInfo196 },
4760  { 5, OperandInfo197 },
4761  { 5, OperandInfo197 },
4762  { 5, OperandInfo196 },
4763  { 2, OperandInfo222 },
4764  { 4, OperandInfo223 },
4765  { 5, OperandInfo76 },
4766  { 6, OperandInfo237 },
4767  { 7, OperandInfo238 },
4768  { 5, OperandInfo76 },
4769  { 6, OperandInfo237 },
4770  { 7, OperandInfo238 },
4771  { 5, OperandInfo76 },
4772  { 6, OperandInfo237 },
4773  { 7, OperandInfo238 },
4774  { 5, OperandInfo239 },
4775  { 6, OperandInfo240 },
4776  { 7, OperandInfo241 },
4777  { 5, OperandInfo239 },
4778  { 6, OperandInfo240 },
4779  { 7, OperandInfo241 },
4780  { 5, OperandInfo239 },
4781  { 6, OperandInfo240 },
4782  { 7, OperandInfo241 },
4783  { 7, OperandInfo242 },
4784  { 9, OperandInfo243 },
4785  { 7, OperandInfo242 },
4786  { 9, OperandInfo243 },
4787  { 7, OperandInfo242 },
4788  { 9, OperandInfo243 },
4789  { 7, OperandInfo244 },
4790  { 9, OperandInfo245 },
4791  { 7, OperandInfo244 },
4792  { 9, OperandInfo245 },
4793  { 7, OperandInfo244 },
4794  { 9, OperandInfo245 },
4795  { 5, OperandInfo76 },
4796  { 5, OperandInfo76 },
4797  { 5, OperandInfo246 },
4798  { 6, OperandInfo237 },
4799  { 7, OperandInfo238 },
4800  { 5, OperandInfo76 },
4801  { 5, OperandInfo246 },
4802  { 6, OperandInfo237 },
4803  { 7, OperandInfo238 },
4804  { 6, OperandInfo237 },
4805  { 7, OperandInfo238 },
4806  { 5, OperandInfo76 },
4807  { 5, OperandInfo76 },
4808  { 5, OperandInfo246 },
4809  { 6, OperandInfo237 },
4810  { 7, OperandInfo238 },
4811  { 5, OperandInfo76 },
4812  { 5, OperandInfo246 },
4813  { 6, OperandInfo237 },
4814  { 7, OperandInfo238 },
4815  { 6, OperandInfo237 },
4816  { 7, OperandInfo238 },
4817  { 5, OperandInfo76 },
4818  { 5, OperandInfo76 },
4819  { 5, OperandInfo246 },
4820  { 6, OperandInfo247 },
4821  { 7, OperandInfo248 },
4822  { 6, OperandInfo237 },
4823  { 7, OperandInfo238 },
4824  { 5, OperandInfo76 },
4825  { 5, OperandInfo246 },
4826  { 6, OperandInfo247 },
4827  { 7, OperandInfo248 },
4828  { 6, OperandInfo237 },
4829  { 7, OperandInfo238 },
4830  { 6, OperandInfo237 },
4831  { 7, OperandInfo238 },
4832  { 5, OperandInfo76 },
4833  { 5, OperandInfo76 },
4834  { 5, OperandInfo246 },
4835  { 6, OperandInfo237 },
4836  { 7, OperandInfo238 },
4837  { 5, OperandInfo76 },
4838  { 5, OperandInfo246 },
4839  { 6, OperandInfo237 },
4840  { 7, OperandInfo238 },
4841  { 6, OperandInfo237 },
4842  { 7, OperandInfo238 },
4843  { 5, OperandInfo239 },
4844  { 6, OperandInfo249 },
4845  { 6, OperandInfo249 },
4846  { 8, OperandInfo250 },
4847  { 8, OperandInfo250 },
4848  { 6, OperandInfo240 },
4849  { 7, OperandInfo241 },
4850  { 5, OperandInfo239 },
4851  { 6, OperandInfo249 },
4852  { 6, OperandInfo249 },
4853  { 8, OperandInfo250 },
4854  { 8, OperandInfo250 },
4855  { 6, OperandInfo240 },
4856  { 7, OperandInfo241 },
4857  { 5, OperandInfo239 },
4858  { 6, OperandInfo249 },
4859  { 6, OperandInfo249 },
4860  { 8, OperandInfo250 },
4861  { 8, OperandInfo250 },
4862  { 6, OperandInfo240 },
4863  { 7, OperandInfo241 },
4864  { 5, OperandInfo239 },
4865  { 6, OperandInfo249 },
4866  { 6, OperandInfo249 },
4867  { 8, OperandInfo250 },
4868  { 8, OperandInfo250 },
4869  { 6, OperandInfo240 },
4870  { 7, OperandInfo241 },
4871  { 5, OperandInfo239 },
4872  { 6, OperandInfo240 },
4873  { 7, OperandInfo241 },
4874  { 5, OperandInfo251 },
4875  { 6, OperandInfo252 },
4876  { 7, OperandInfo253 },
4877  { 5, OperandInfo239 },
4878  { 6, OperandInfo240 },
4879  { 7, OperandInfo241 },
4880  { 5, OperandInfo251 },
4881  { 6, OperandInfo252 },
4882  { 7, OperandInfo253 },
4883  { 5, OperandInfo239 },
4884  { 6, OperandInfo240 },
4885  { 7, OperandInfo241 },
4886  { 5, OperandInfo251 },
4887  { 6, OperandInfo252 },
4888  { 7, OperandInfo253 },
4889  { 5, OperandInfo246 },
4890  { 5, OperandInfo246 },
4891  { 5, OperandInfo246 },
4892  { 5, OperandInfo246 },
4893  { 5, OperandInfo246 },
4894  { 5, OperandInfo246 },
4895  { 9, OperandInfo254 },
4896  { 7, OperandInfo244 },
4897  { 9, OperandInfo245 },
4898  { 11, OperandInfo255 },
4899  { 9, OperandInfo254 },
4900  { 7, OperandInfo244 },
4901  { 9, OperandInfo245 },
4902  { 11, OperandInfo255 },
4903  { 9, OperandInfo254 },
4904  { 7, OperandInfo244 },
4905  { 9, OperandInfo245 },
4906  { 11, OperandInfo255 },
4907  { 9, OperandInfo254 },
4908  { 7, OperandInfo256 },
4909  { 9, OperandInfo257 },
4910  { 11, OperandInfo255 },
4911  { 9, OperandInfo254 },
4912  { 7, OperandInfo256 },
4913  { 9, OperandInfo257 },
4914  { 11, OperandInfo255 },
4915  { 5, OperandInfo239 },
4916  { 6, OperandInfo240 },
4917  { 7, OperandInfo241 },
4918  { 5, OperandInfo239 },
4919  { 6, OperandInfo240 },
4920  { 7, OperandInfo241 },
4921  { 5, OperandInfo239 },
4922  { 6, OperandInfo240 },
4923  { 7, OperandInfo241 },
4924  { 5, OperandInfo239 },
4925  { 6, OperandInfo240 },
4926  { 7, OperandInfo241 },
4927  { 5, OperandInfo239 },
4928  { 6, OperandInfo240 },
4929  { 7, OperandInfo241 },
4930  { 5, OperandInfo239 },
4931  { 6, OperandInfo240 },
4932  { 7, OperandInfo241 },
4933  { 5, OperandInfo76 },
4934  { 5, OperandInfo246 },
4935  { 6, OperandInfo247 },
4936  { 7, OperandInfo248 },
4937  { 6, OperandInfo237 },
4938  { 7, OperandInfo238 },
4939  { 5, OperandInfo76 },
4940  { 5, OperandInfo246 },
4941  { 6, OperandInfo247 },
4942  { 7, OperandInfo248 },
4943  { 6, OperandInfo237 },
4944  { 7, OperandInfo238 },
4945  { 5, OperandInfo76 },
4946  { 5, OperandInfo246 },
4947  { 6, OperandInfo247 },
4948  { 7, OperandInfo248 },
4949  { 6, OperandInfo237 },
4950  { 7, OperandInfo238 },
4951  { 7, OperandInfo258 },
4952  { 5, OperandInfo246 },
4953  { 7, OperandInfo259 },
4954  { 9, OperandInfo260 },
4955  { 7, OperandInfo258 },
4956  { 5, OperandInfo246 },
4957  { 7, OperandInfo259 },
4958  { 9, OperandInfo260 },
4959  { 7, OperandInfo258 },
4960  { 5, OperandInfo246 },
4961  { 7, OperandInfo259 },
4962  { 9, OperandInfo260 },
4963  { 7, OperandInfo258 },
4964  { 6, OperandInfo249 },
4965  { 6, OperandInfo249 },
4966  { 9, OperandInfo260 },
4967  { 7, OperandInfo258 },
4968  { 6, OperandInfo249 },
4969  { 6, OperandInfo249 },
4970  { 9, OperandInfo260 },
4971  { 7, OperandInfo258 },
4972  { 6, OperandInfo249 },
4973  { 6, OperandInfo249 },
4974  { 9, OperandInfo260 },
4975  { 11, OperandInfo261 },
4976  { 7, OperandInfo256 },
4977  { 9, OperandInfo257 },
4978  { 13, OperandInfo262 },
4979  { 11, OperandInfo261 },
4980  { 7, OperandInfo256 },
4981  { 9, OperandInfo257 },
4982  { 13, OperandInfo262 },
4983  { 11, OperandInfo261 },
4984  { 7, OperandInfo256 },
4985  { 9, OperandInfo257 },
4986  { 13, OperandInfo262 },
4987  { 11, OperandInfo261 },
4988  { 7, OperandInfo263 },
4989  { 9, OperandInfo264 },
4990  { 13, OperandInfo262 },
4991  { 11, OperandInfo261 },
4992  { 7, OperandInfo263 },
4993  { 9, OperandInfo264 },
4994  { 13, OperandInfo262 },
4995  { 7, OperandInfo258 },
4996  { 5, OperandInfo246 },
4997  { 7, OperandInfo259 },
4998  { 9, OperandInfo260 },
4999  { 7, OperandInfo258 },
5000  { 5, OperandInfo246 },
5001  { 7, OperandInfo259 },
5002  { 9, OperandInfo260 },
5003  { 7, OperandInfo258 },
5004  { 5, OperandInfo246 },
5005  { 7, OperandInfo259 },
5006  { 9, OperandInfo260 },
5007  { 7, OperandInfo258 },
5008  { 8, OperandInfo250 },
5009  { 9, OperandInfo260 },
5010  { 6, OperandInfo249 },
5011  { 8, OperandInfo250 },
5012  { 7, OperandInfo258 },
5013  { 8, OperandInfo250 },
5014  { 9, OperandInfo260 },
5015  { 6, OperandInfo249 },
5016  { 8, OperandInfo250 },
5017  { 7, OperandInfo258 },
5018  { 8, OperandInfo250 },
5019  { 9, OperandInfo260 },
5020  { 6, OperandInfo249 },
5021  { 8, OperandInfo250 },
5022  { 8, OperandInfo265 },
5023  { 5, OperandInfo246 },
5024  { 7, OperandInfo259 },
5025  { 10, OperandInfo266 },
5026  { 8, OperandInfo265 },
5027  { 5, OperandInfo246 },
5028  { 7, OperandInfo259 },
5029  { 10, OperandInfo266 },
5030  { 8, OperandInfo265 },
5031  { 5, OperandInfo246 },
5032  { 7, OperandInfo259 },
5033  { 10, OperandInfo266 },
5034  { 8, OperandInfo265 },
5035  { 6, OperandInfo249 },
5036  { 6, OperandInfo249 },
5037  { 10, OperandInfo266 },
5038  { 8, OperandInfo265 },
5039  { 6, OperandInfo249 },
5040  { 6, OperandInfo249 },
5041  { 10, OperandInfo266 },
5042  { 8, OperandInfo265 },
5043  { 6, OperandInfo249 },
5044  { 6, OperandInfo249 },
5045  { 10, OperandInfo266 },
5046  { 13, OperandInfo267 },
5047  { 7, OperandInfo256 },
5048  { 9, OperandInfo257 },
5049  { 15, OperandInfo268 },
5050  { 13, OperandInfo267 },
5051  { 7, OperandInfo256 },
5052  { 9, OperandInfo257 },
5053  { 15, OperandInfo268 },
5054  { 13, OperandInfo267 },
5055  { 7, OperandInfo256 },
5056  { 9, OperandInfo257 },
5057  { 15, OperandInfo268 },
5058  { 13, OperandInfo267 },
5059  { 7, OperandInfo263 },
5060  { 9, OperandInfo264 },
5061  { 15, OperandInfo268 },
5062  { 13, OperandInfo267 },
5063  { 7, OperandInfo263 },
5064  { 9, OperandInfo264 },
5065  { 15, OperandInfo268 },
5066  { 8, OperandInfo265 },
5067  { 5, OperandInfo246 },
5068  { 7, OperandInfo259 },
5069  { 10, OperandInfo266 },
5070  { 8, OperandInfo265 },
5071  { 5, OperandInfo246 },
5072  { 7, OperandInfo259 },
5073  { 10, OperandInfo266 },
5074  { 8, OperandInfo265 },
5075  { 5, OperandInfo246 },
5076  { 7, OperandInfo259 },
5077  { 10, OperandInfo266 },
5078  { 8, OperandInfo265 },
5079  { 8, OperandInfo250 },
5080  { 10, OperandInfo266 },
5081  { 6, OperandInfo249 },
5082  { 8, OperandInfo250 },
5083  { 8, OperandInfo265 },
5084  { 8, OperandInfo250 },
5085  { 10, OperandInfo266 },
5086  { 6, OperandInfo249 },
5087  { 8, OperandInfo250 },
5088  { 8, OperandInfo265 },
5089  { 8, OperandInfo250 },
5090  { 10, OperandInfo266 },
5091  { 6, OperandInfo249 },
5092  { 8, OperandInfo250 },
5093  { 5, OperandInfo50 },
5094  { 4, OperandInfo132 },
5095  { 5, OperandInfo50 },
5096  { 4, OperandInfo269 },
5097  { 5, OperandInfo50 },
5098  { 4, OperandInfo132 },
5099  { 5, OperandInfo50 },
5100  { 5, OperandInfo76 },
5101  { 5, OperandInfo270 },
5102  { 5, OperandInfo271 },
5103  { 3, OperandInfo163 },
5104  { 3, OperandInfo163 },
5105  { 3, OperandInfo272 },
5106  { 3, OperandInfo273 },
5107  { 3, OperandInfo272 },
5108  { 3, OperandInfo272 },
5109  { 3, OperandInfo274 },
5110  { 3, OperandInfo274 },
5111  { 3, OperandInfo275 },
5112  { 5, OperandInfo196 },
5113  { 5, OperandInfo197 },
5114  { 5, OperandInfo196 },
5115  { 5, OperandInfo197 },
5116  { 5, OperandInfo197 },
5117  { 5, OperandInfo196 },
5118  { 5, OperandInfo196 },
5119  { 5, OperandInfo197 },
5120  { 5, OperandInfo197 },
5121  { 5, OperandInfo196 },
5122  { 5, OperandInfo197 },
5123  { 5, OperandInfo196 },
5124  { 5, OperandInfo196 },
5125  { 5, OperandInfo197 },
5126  { 5, OperandInfo197 },
5127  { 5, OperandInfo196 },
5128  { 3, OperandInfo272 },
5129  { 3, OperandInfo273 },
5130  { 3, OperandInfo272 },
5131  { 3, OperandInfo272 },
5132  { 3, OperandInfo274 },
5133  { 3, OperandInfo274 },
5134  { 3, OperandInfo275 },
5135  { 5, OperandInfo196 },
5136  { 5, OperandInfo197 },
5137  { 5, OperandInfo196 },
5138  { 5, OperandInfo197 },
5139  { 5, OperandInfo197 },
5140  { 5, OperandInfo196 },
5141  { 5, OperandInfo196 },
5142  { 5, OperandInfo197 },
5143  { 5, OperandInfo197 },
5144  { 5, OperandInfo196 },
5145  { 5, OperandInfo197 },
5146  { 5, OperandInfo196 },
5147  { 5, OperandInfo196 },
5148  { 5, OperandInfo197 },
5149  { 5, OperandInfo197 },
5150  { 5, OperandInfo196 },
5151  { 6, OperandInfo194 },
5152  { 6, OperandInfo234 },
5153  { 7, OperandInfo276 },
5154  { 7, OperandInfo277 },
5155  { 7, OperandInfo276 },
5156  { 7, OperandInfo277 },
5157  { 6, OperandInfo192 },
5158  { 6, OperandInfo192 },
5159  { 6, OperandInfo192 },
5160  { 6, OperandInfo192 },
5161  { 6, OperandInfo192 },
5162  { 6, OperandInfo192 },
5163  { 6, OperandInfo235 },
5164  { 6, OperandInfo194 },
5165  { 6, OperandInfo193 },
5166  { 6, OperandInfo194 },
5167  { 6, OperandInfo193 },
5168  { 7, OperandInfo278 },
5169  { 7, OperandInfo279 },
5170  { 7, OperandInfo280 },
5171  { 7, OperandInfo281 },
5172  { 7, OperandInfo278 },
5173  { 7, OperandInfo280 },
5174  { 7, OperandInfo279 },
5175  { 7, OperandInfo281 },
5176  { 6, OperandInfo193 },
5177  { 6, OperandInfo194 },
5178  { 6, OperandInfo194 },
5179  { 6, OperandInfo193 },
5180  { 6, OperandInfo193 },
5181  { 6, OperandInfo194 },
5182  { 6, OperandInfo194 },
5183  { 6, OperandInfo234 },
5184  { 7, OperandInfo276 },
5185  { 7, OperandInfo277 },
5186  { 7, OperandInfo276 },
5187  { 7, OperandInfo277 },
5188  { 6, OperandInfo192 },
5189  { 6, OperandInfo192 },
5190  { 6, OperandInfo192 },
5191  { 6, OperandInfo192 },
5192  { 6, OperandInfo192 },
5193  { 6, OperandInfo192 },
5194  { 6, OperandInfo235 },
5195  { 6, OperandInfo194 },
5196  { 6, OperandInfo193 },
5197  { 6, OperandInfo194 },
5198  { 6, OperandInfo193 },
5199  { 7, OperandInfo278 },
5200  { 7, OperandInfo279 },
5201  { 7, OperandInfo280 },
5202  { 7, OperandInfo281 },
5203  { 7, OperandInfo278 },
5204  { 7, OperandInfo280 },
5205  { 7, OperandInfo279 },
5206  { 7, OperandInfo281 },
5207  { 6, OperandInfo193 },
5208  { 6, OperandInfo194 },
5209  { 6, OperandInfo194 },
5210  { 6, OperandInfo193 },
5211  { 6, OperandInfo193 },
5212  { 6, OperandInfo194 },
5213  { 4, OperandInfo198 },
5214  { 5, OperandInfo282 },
5215  { 2, OperandInfo222 },
5216  { 4, OperandInfo283 },
5217  { 4, OperandInfo228 },
5218  { 4, OperandInfo228 },
5219  { 4, OperandInfo228 },
5220  { 4, OperandInfo228 },
5221  { 4, OperandInfo228 },
5222  { 4, OperandInfo228 },
5223  { 4, OperandInfo225 },
5224  { 4, OperandInfo225 },
5225  { 4, OperandInfo225 },
5226  { 4, OperandInfo284 },
5227  { 5, OperandInfo285 },
5228  { 6, OperandInfo286 },
5229  { 4, OperandInfo287 },
5230  { 4, OperandInfo199 },
5231  { 4, OperandInfo288 },
5232  { 6, OperandInfo289 },
5233  { 4, OperandInfo290 },
5234  { 4, OperandInfo129 },
5235  { 4, OperandInfo129 },
5236  { 4, OperandInfo129 },
5237  { 4, OperandInfo290 },
5238  { 4, OperandInfo290 },
5239  { 4, OperandInfo129 },
5240  { 4, OperandInfo290 },
5241  { 4, OperandInfo290 },
5242  { 4, OperandInfo129 },
5243  { 3, OperandInfo163 },
5244  { 3, OperandInfo163 },
5245  { 3, OperandInfo163 },
5246  { 3, OperandInfo163 },
5247  { 3, OperandInfo163 },
5248  { 3, OperandInfo163 },
5249  { 3, OperandInfo163 },
5250  { 3, OperandInfo163 },
5251  { 3, OperandInfo163 },
5252  { 3, OperandInfo163 },
5253  { 3, OperandInfo163 },
5254  { 3, OperandInfo163 },
5255  { 3, OperandInfo163 },
5256  { 5, OperandInfo196 },
5257  { 5, OperandInfo201 },
5258  { 3, OperandInfo291 },
5259  { 5, OperandInfo195 },
5260  { 6, OperandInfo292 },
5261  { 6, OperandInfo293 },
5262  { 6, OperandInfo292 },
5263  { 6, OperandInfo293 },
5264  { 5, OperandInfo195 },
5265  { 5, OperandInfo195 },
5266  { 5, OperandInfo195 },
5267  { 5, OperandInfo195 },
5268  { 5, OperandInfo195 },
5269  { 5, OperandInfo195 },
5270  { 5, OperandInfo203 },
5271  { 5, OperandInfo196 },
5272  { 5, OperandInfo197 },
5273  { 5, OperandInfo196 },
5274  { 5, OperandInfo197 },
5275  { 5, OperandInfo196 },
5276  { 5, OperandInfo197 },
5277  { 6, OperandInfo294 },
5278  { 6, OperandInfo295 },
5279  { 6, OperandInfo296 },
5280  { 6, OperandInfo297 },
5281  { 6, OperandInfo294 },
5282  { 6, OperandInfo296 },
5283  { 6, OperandInfo295 },
5284  { 6, OperandInfo297 },
5285  { 5, OperandInfo197 },
5286  { 5, OperandInfo196 },
5287  { 5, OperandInfo196 },
5288  { 5, OperandInfo197 },
5289  { 5, OperandInfo197 },
5290  { 5, OperandInfo196 },
5291  { 4, OperandInfo198 },
5292  { 4, OperandInfo200 },
5293  { 4, OperandInfo129 },
5294  { 4, OperandInfo129 },
5295  { 4, OperandInfo290 },
5296  { 4, OperandInfo290 },
5297  { 4, OperandInfo198 },
5298  { 4, OperandInfo215 },
5299  { 4, OperandInfo199 },
5300  { 4, OperandInfo200 },
5301  { 4, OperandInfo198 },
5302  { 4, OperandInfo198 },
5303  { 4, OperandInfo200 },
5304  { 4, OperandInfo198 },
5305  { 4, OperandInfo200 },
5306  { 4, OperandInfo198 },
5307  { 4, OperandInfo200 },
5308  { 4, OperandInfo198 },
5309  { 4, OperandInfo200 },
5310  { 6, OperandInfo194 },
5311  { 6, OperandInfo234 },
5312  { 6, OperandInfo235 },
5313  { 6, OperandInfo194 },
5314  { 6, OperandInfo234 },
5315  { 6, OperandInfo235 },
5316  { 5, OperandInfo196 },
5317  { 5, OperandInfo201 },
5318  { 5, OperandInfo203 },
5319  { 5, OperandInfo196 },
5320  { 5, OperandInfo197 },
5321  { 5, OperandInfo196 },
5322  { 5, OperandInfo205 },
5323  { 5, OperandInfo205 },
5324  { 5, OperandInfo206 },
5325  { 5, OperandInfo206 },
5326  { 5, OperandInfo197 },
5327  { 5, OperandInfo298 },
5328  { 5, OperandInfo79 },
5329  { 5, OperandInfo79 },
5330  { 5, OperandInfo298 },
5331  { 5, OperandInfo298 },
5332  { 5, OperandInfo79 },
5333  { 5, OperandInfo298 },
5334  { 5, OperandInfo79 },
5335  { 5, OperandInfo79 },
5336  { 5, OperandInfo298 },
5337  { 5, OperandInfo298 },
5338  { 5, OperandInfo79 },
5339  { 4, OperandInfo200 },
5340  { 4, OperandInfo198 },
5341  { 4, OperandInfo198 },
5342  { 4, OperandInfo200 },
5343  { 4, OperandInfo200 },
5344  { 4, OperandInfo198 },
5345  { 4, OperandInfo200 },
5346  { 4, OperandInfo198 },
5347  { 4, OperandInfo198 },
5348  { 4, OperandInfo200 },
5349  { 4, OperandInfo200 },
5350  { 4, OperandInfo198 },
5351  { 5, OperandInfo196 },
5352  { 5, OperandInfo196 },
5353  { 5, OperandInfo196 },
5354  { 5, OperandInfo196 },
5355  { 5, OperandInfo196 },
5356  { 5, OperandInfo196 },
5357  { 5, OperandInfo196 },
5358  { 5, OperandInfo196 },
5359  { 5, OperandInfo196 },
5360  { 5, OperandInfo196 },
5361  { 5, OperandInfo196 },
5362  { 5, OperandInfo196 },
5363  { 5, OperandInfo196 },
5364  { 5, OperandInfo196 },
5365  { 5, OperandInfo196 },
5366  { 5, OperandInfo196 },
5367  { 5, OperandInfo196 },
5368  { 5, OperandInfo196 },
5369  { 5, OperandInfo196 },
5370  { 5, OperandInfo196 },
5371  { 5, OperandInfo196 },
5372  { 4, OperandInfo200 },
5373  { 4, OperandInfo198 },
5374  { 4, OperandInfo198 },
5375  { 4, OperandInfo200 },
5376  { 4, OperandInfo200 },
5377  { 4, OperandInfo198 },
5378  { 5, OperandInfo197 },
5379  { 5, OperandInfo196 },
5380  { 5, OperandInfo196 },
5381  { 5, OperandInfo197 },
5382  { 5, OperandInfo196 },
5383  { 5, OperandInfo197 },
5384  { 5, OperandInfo197 },
5385  { 5, OperandInfo196 },
5386  { 5, OperandInfo197 },
5387  { 5, OperandInfo196 },
5388  { 5, OperandInfo196 },
5389  { 5, OperandInfo197 },
5390  { 5, OperandInfo196 },
5391  { 5, OperandInfo197 },
5392  { 5, OperandInfo197 },
5393  { 5, OperandInfo196 },
5394  { 7, OperandInfo276 },
5395  { 7, OperandInfo277 },
5396  { 6, OperandInfo192 },
5397  { 6, OperandInfo192 },
5398  { 7, OperandInfo276 },
5399  { 7, OperandInfo277 },
5400  { 6, OperandInfo192 },
5401  { 6, OperandInfo192 },
5402  { 6, OperandInfo294 },
5403  { 6, OperandInfo296 },
5404  { 6, OperandInfo295 },
5405  { 6, OperandInfo297 },
5406  { 5, OperandInfo196 },
5407  { 5, OperandInfo196 },
5408  { 5, OperandInfo197 },
5409  { 5, OperandInfo197 },
5410  { 6, OperandInfo292 },
5411  { 6, OperandInfo293 },
5412  { 5, OperandInfo195 },
5413  { 5, OperandInfo195 },
5414  { 4, OperandInfo225 },
5415  { 4, OperandInfo225 },
5416  { 4, OperandInfo225 },
5417  { 4, OperandInfo225 },
5418  { 4, OperandInfo225 },
5419  { 4, OperandInfo225 },
5420  { 4, OperandInfo225 },
5421  { 4, OperandInfo225 },
5422  { 4, OperandInfo225 },
5423  { 4, OperandInfo200 },
5424  { 4, OperandInfo198 },
5425  { 4, OperandInfo198 },
5426  { 4, OperandInfo200 },
5427  { 4, OperandInfo200 },
5428  { 4, OperandInfo198 },
5429  { 7, OperandInfo278 },
5430  { 7, OperandInfo280 },
5431  { 7, OperandInfo279 },
5432  { 7, OperandInfo281 },
5433  { 6, OperandInfo194 },
5434  { 6, OperandInfo194 },
5435  { 6, OperandInfo193 },
5436  { 6, OperandInfo193 },
5437  { 7, OperandInfo278 },
5438  { 7, OperandInfo280 },
5439  { 7, OperandInfo279 },
5440  { 7, OperandInfo281 },
5441  { 6, OperandInfo194 },
5442  { 6, OperandInfo194 },
5443  { 6, OperandInfo193 },
5444  { 6, OperandInfo193 },
5445  { 6, OperandInfo294 },
5446  { 6, OperandInfo296 },
5447  { 6, OperandInfo295 },
5448  { 6, OperandInfo297 },
5449  { 5, OperandInfo196 },
5450  { 5, OperandInfo196 },
5451  { 5, OperandInfo197 },
5452  { 5, OperandInfo197 },
5453  { 5, OperandInfo197 },
5454  { 5, OperandInfo196 },
5455  { 5, OperandInfo196 },
5456  { 5, OperandInfo197 },
5457  { 5, OperandInfo196 },
5458  { 5, OperandInfo197 },
5459  { 5, OperandInfo197 },
5460  { 5, OperandInfo196 },
5461  { 5, OperandInfo197 },
5462  { 5, OperandInfo196 },
5463  { 5, OperandInfo196 },
5464  { 5, OperandInfo197 },
5465  { 5, OperandInfo196 },
5466  { 5, OperandInfo197 },
5467  { 5, OperandInfo197 },
5468  { 5, OperandInfo196 },
5469  { 5, OperandInfo299 },
5470  { 5, OperandInfo299 },
5471  { 5, OperandInfo299 },
5472  { 5, OperandInfo299 },
5473  { 5, OperandInfo299 },
5474  { 5, OperandInfo299 },
5475  { 5, OperandInfo299 },
5476  { 5, OperandInfo299 },
5477  { 5, OperandInfo299 },
5478  { 5, OperandInfo300 },
5479  { 5, OperandInfo301 },
5480  { 5, OperandInfo301 },
5481  { 5, OperandInfo300 },
5482  { 5, OperandInfo301 },
5483  { 5, OperandInfo300 },
5484  { 5, OperandInfo300 },
5485  { 5, OperandInfo301 },
5486  { 5, OperandInfo300 },
5487  { 5, OperandInfo301 },
5488  { 5, OperandInfo301 },
5489  { 5, OperandInfo300 },
5490  { 5, OperandInfo301 },
5491  { 5, OperandInfo300 },
5492  { 5, OperandInfo300 },
5493  { 5, OperandInfo301 },
5494  { 5, OperandInfo197 },
5495  { 5, OperandInfo196 },
5496  { 5, OperandInfo196 },
5497  { 5, OperandInfo197 },
5498  { 5, OperandInfo196 },
5499  { 5, OperandInfo197 },
5500  { 5, OperandInfo197 },
5501  { 5, OperandInfo196 },
5502  { 5, OperandInfo300 },
5503  { 5, OperandInfo301 },
5504  { 5, OperandInfo301 },
5505  { 5, OperandInfo300 },
5506  { 5, OperandInfo301 },
5507  { 5, OperandInfo300 },
5508  { 5, OperandInfo300 },
5509  { 5, OperandInfo301 },
5510  { 5, OperandInfo197 },
5511  { 5, OperandInfo196 },
5512  { 5, OperandInfo196 },
5513  { 5, OperandInfo197 },
5514  { 5, OperandInfo196 },
5515  { 5, OperandInfo197 },
5516  { 5, OperandInfo197 },
5517  { 5, OperandInfo196 },
5518  { 5, OperandInfo299 },
5519  { 5, OperandInfo299 },
5520  { 5, OperandInfo299 },
5521  { 5, OperandInfo299 },
5522  { 5, OperandInfo299 },
5523  { 5, OperandInfo299 },
5524  { 5, OperandInfo299 },
5525  { 5, OperandInfo299 },
5526  { 5, OperandInfo299 },
5527  { 5, OperandInfo197 },
5528  { 5, OperandInfo196 },
5529  { 5, OperandInfo196 },
5530  { 5, OperandInfo197 },
5531  { 5, OperandInfo196 },
5532  { 5, OperandInfo197 },
5533  { 5, OperandInfo197 },
5534  { 5, OperandInfo196 },
5535  { 5, OperandInfo197 },
5536  { 5, OperandInfo196 },
5537  { 5, OperandInfo196 },
5538  { 5, OperandInfo197 },
5539  { 5, OperandInfo196 },
5540  { 5, OperandInfo197 },
5541  { 5, OperandInfo197 },
5542  { 5, OperandInfo196 },
5543  { 5, OperandInfo202 },
5544  { 5, OperandInfo202 },
5545  { 5, OperandInfo202 },
5546  { 4, OperandInfo198 },
5547  { 4, OperandInfo198 },
5548  { 4, OperandInfo200 },
5549  { 4, OperandInfo198 },
5550  { 4, OperandInfo200 },
5551  { 4, OperandInfo200 },
5552  { 5, OperandInfo196 },
5553  { 5, OperandInfo197 },
5554  { 5, OperandInfo196 },
5555  { 5, OperandInfo197 },
5556  { 4, OperandInfo198 },
5557  { 4, OperandInfo200 },
5558  { 4, OperandInfo198 },
5559  { 4, OperandInfo198 },
5560  { 4, OperandInfo200 },
5561  { 4, OperandInfo200 },
5562  { 4, OperandInfo198 },
5563  { 4, OperandInfo198 },
5564  { 4, OperandInfo198 },
5565  { 4, OperandInfo200 },
5566  { 4, OperandInfo200 },
5567  { 4, OperandInfo200 },
5568  { 5, OperandInfo197 },
5569  { 5, OperandInfo196 },
5570  { 5, OperandInfo196 },
5571  { 5, OperandInfo197 },
5572  { 5, OperandInfo197 },
5573  { 5, OperandInfo196 },
5574  { 5, OperandInfo197 },
5575  { 5, OperandInfo196 },
5576  { 5, OperandInfo196 },
5577  { 5, OperandInfo197 },
5578  { 5, OperandInfo197 },
5579  { 5, OperandInfo196 },
5580  { 2, OperandInfo219 },
5581  { 2, OperandInfo222 },
5582  { 2, OperandInfo219 },
5583  { 2, OperandInfo219 },
5584  { 2, OperandInfo119 },
5585  { 2, OperandInfo119 },
5586  { 2, OperandInfo222 },
5587  { 2, OperandInfo219 },
5588  { 2, OperandInfo222 },
5589  { 2, OperandInfo219 },
5590  { 2, OperandInfo219 },
5591  { 2, OperandInfo119 },
5592  { 2, OperandInfo119 },
5593  { 2, OperandInfo222 },
5594  { 2, OperandInfo219 },
5595  { 2, OperandInfo222 },
5596  { 2, OperandInfo219 },
5597  { 2, OperandInfo219 },
5598  { 2, OperandInfo119 },
5599  { 2, OperandInfo119 },
5600  { 2, OperandInfo222 },
5601  { 2, OperandInfo219 },
5602  { 2, OperandInfo222 },
5603  { 2, OperandInfo219 },
5604  { 2, OperandInfo219 },
5605  { 2, OperandInfo119 },
5606  { 2, OperandInfo119 },
5607  { 2, OperandInfo222 },
5608  { 4, OperandInfo198 },
5609  { 4, OperandInfo199 },
5610  { 4, OperandInfo199 },
5611  { 4, OperandInfo198 },
5612  { 4, OperandInfo199 },
5613  { 2, OperandInfo219 },
5614  { 2, OperandInfo219 },
5615  { 2, OperandInfo119 },
5616  { 2, OperandInfo119 },
5617  { 4, OperandInfo199 },
5618  { 4, OperandInfo198 },
5619  { 4, OperandInfo199 },
5620  { 2, OperandInfo219 },
5621  { 2, OperandInfo219 },
5622  { 2, OperandInfo119 },
5623  { 2, OperandInfo119 },
5624  { 4, OperandInfo199 },
5625  { 5, OperandInfo197 },
5626  { 5, OperandInfo196 },
5627  { 5, OperandInfo196 },
5628  { 5, OperandInfo197 },
5629  { 5, OperandInfo196 },
5630  { 5, OperandInfo197 },
5631  { 5, OperandInfo197 },
5632  { 5, OperandInfo196 },
5633  { 5, OperandInfo197 },
5634  { 5, OperandInfo196 },
5635  { 5, OperandInfo196 },
5636  { 5, OperandInfo197 },
5637  { 5, OperandInfo196 },
5638  { 5, OperandInfo197 },
5639  { 5, OperandInfo197 },
5640  { 5, OperandInfo196 },
5641  { 5, OperandInfo299 },
5642  { 5, OperandInfo299 },
5643  { 5, OperandInfo299 },
5644  { 5, OperandInfo227 },
5645  { 5, OperandInfo226 },
5646  { 5, OperandInfo226 },
5647  { 5, OperandInfo227 },
5648  { 5, OperandInfo226 },
5649  { 5, OperandInfo227 },
5650  { 5, OperandInfo227 },
5651  { 5, OperandInfo226 },
5652  { 5, OperandInfo227 },
5653  { 5, OperandInfo226 },
5654  { 5, OperandInfo226 },
5655  { 5, OperandInfo227 },
5656  { 5, OperandInfo226 },
5657  { 5, OperandInfo227 },
5658  { 5, OperandInfo227 },
5659  { 5, OperandInfo226 },
5660  { 4, OperandInfo198 },
5661  { 4, OperandInfo198 },
5662  { 4, OperandInfo200 },
5663  { 4, OperandInfo198 },
5664  { 4, OperandInfo200 },
5665  { 4, OperandInfo200 },
5666  { 5, OperandInfo196 },
5667  { 5, OperandInfo197 },
5668  { 5, OperandInfo196 },
5669  { 5, OperandInfo197 },
5670  { 6, OperandInfo302 },
5671  { 6, OperandInfo303 },
5672  { 6, OperandInfo303 },
5673  { 6, OperandInfo302 },
5674  { 6, OperandInfo303 },
5675  { 6, OperandInfo302 },
5676  { 6, OperandInfo302 },
5677  { 6, OperandInfo303 },
5678  { 6, OperandInfo302 },
5679  { 6, OperandInfo303 },
5680  { 6, OperandInfo303 },
5681  { 6, OperandInfo302 },
5682  { 6, OperandInfo303 },
5683  { 6, OperandInfo302 },
5684  { 6, OperandInfo302 },
5685  { 6, OperandInfo303 },
5686  { 5, OperandInfo202 },
5687  { 5, OperandInfo202 },
5688  { 5, OperandInfo202 },
5689  { 4, OperandInfo304 },
5690  { 5, OperandInfo305 },
5691  { 4, OperandInfo173 },
5692  { 5, OperandInfo306 },
5693  { 3, OperandInfo272 },
5694  { 3, OperandInfo273 },
5695  { 3, OperandInfo275 },
5696  { 3, OperandInfo272 },
5697  { 3, OperandInfo273 },
5698  { 3, OperandInfo275 },
5699  { 3, OperandInfo272 },
5700  { 3, OperandInfo273 },
5701  { 3, OperandInfo275 },
5702  { 3, OperandInfo272 },
5703  { 3, OperandInfo273 },
5704  { 3, OperandInfo275 },
5705  { 6, OperandInfo307 },
5706  { 6, OperandInfo307 },
5707  { 6, OperandInfo307 },
5708  { 5, OperandInfo231 },
5709  { 5, OperandInfo231 },
5710  { 5, OperandInfo231 },
5711  { 5, OperandInfo231 },
5712  { 5, OperandInfo231 },
5713  { 5, OperandInfo231 },
5714  { 5, OperandInfo231 },
5715  { 5, OperandInfo231 },
5716  { 5, OperandInfo231 },
5717  { 5, OperandInfo300 },
5718  { 5, OperandInfo301 },
5719  { 5, OperandInfo301 },
5720  { 5, OperandInfo300 },
5721  { 5, OperandInfo301 },
5722  { 5, OperandInfo300 },
5723  { 5, OperandInfo300 },
5724  { 5, OperandInfo301 },
5725  { 5, OperandInfo197 },
5726  { 5, OperandInfo196 },
5727  { 5, OperandInfo196 },
5728  { 5, OperandInfo197 },
5729  { 5, OperandInfo196 },
5730  { 5, OperandInfo197 },
5731  { 5, OperandInfo197 },
5732  { 5, OperandInfo196 },
5733  { 5, OperandInfo197 },
5734  { 5, OperandInfo196 },
5735  { 5, OperandInfo196 },
5736  { 5, OperandInfo197 },
5737  { 5, OperandInfo196 },
5738  { 5, OperandInfo197 },
5739  { 5, OperandInfo197 },
5740  { 5, OperandInfo196 },
5741  { 5, OperandInfo299 },
5742  { 5, OperandInfo299 },
5743  { 5, OperandInfo299 },
5744  { 5, OperandInfo227 },
5745  { 5, OperandInfo226 },
5746  { 5, OperandInfo226 },
5747  { 5, OperandInfo227 },
5748  { 5, OperandInfo226 },
5749  { 5, OperandInfo227 },
5750  { 5, OperandInfo227 },
5751  { 5, OperandInfo226 },
5752  { 5, OperandInfo227 },
5753  { 5, OperandInfo226 },
5754  { 5, OperandInfo226 },
5755  { 5, OperandInfo227 },
5756  { 5, OperandInfo226 },
5757  { 5, OperandInfo227 },
5758  { 5, OperandInfo227 },
5759  { 5, OperandInfo226 },
5760  { 5, OperandInfo308 },
5761  { 5, OperandInfo309 },
5762  { 5, OperandInfo309 },
5763  { 4, OperandInfo224 },
5764  { 4, OperandInfo310 },
5765  { 4, OperandInfo199 },
5766  { 6, OperandInfo311 },
5767  { 6, OperandInfo312 },
5768  { 6, OperandInfo312 },
5769  { 6, OperandInfo311 },
5770  { 6, OperandInfo312 },
5771  { 6, OperandInfo311 },
5772  { 6, OperandInfo311 },
5773  { 6, OperandInfo312 },
5774  { 5, OperandInfo308 },
5775  { 5, OperandInfo309 },
5776  { 5, OperandInfo309 },
5777  { 4, OperandInfo198 },
5778  { 4, OperandInfo199 },
5779  { 4, OperandInfo199 },
5780  { 6, OperandInfo302 },
5781  { 6, OperandInfo303 },
5782  { 6, OperandInfo303 },
5783  { 6, OperandInfo302 },
5784  { 6, OperandInfo303 },
5785  { 6, OperandInfo302 },
5786  { 6, OperandInfo302 },
5787  { 6, OperandInfo303 },
5788  { 6, OperandInfo302 },
5789  { 6, OperandInfo303 },
5790  { 6, OperandInfo303 },
5791  { 6, OperandInfo302 },
5792  { 6, OperandInfo303 },
5793  { 6, OperandInfo302 },
5794  { 6, OperandInfo302 },
5795  { 6, OperandInfo303 },
5796  { 6, OperandInfo302 },
5797  { 6, OperandInfo303 },
5798  { 6, OperandInfo303 },
5799  { 6, OperandInfo302 },
5800  { 6, OperandInfo303 },
5801  { 6, OperandInfo302 },
5802  { 6, OperandInfo302 },
5803  { 6, OperandInfo303 },
5804  { 6, OperandInfo313 },
5805  { 8, OperandInfo314 },
5806  { 6, OperandInfo313 },
5807  { 8, OperandInfo314 },
5808  { 6, OperandInfo313 },
5809  { 8, OperandInfo314 },
5810  { 6, OperandInfo315 },
5811  { 8, OperandInfo316 },
5812  { 6, OperandInfo315 },
5813  { 8, OperandInfo316 },
5814  { 6, OperandInfo315 },
5815  { 8, OperandInfo316 },
5816  { 5, OperandInfo317 },
5817  { 5, OperandInfo317 },
5818  { 5, OperandInfo318 },
5819  { 6, OperandInfo319 },
5820  { 7, OperandInfo320 },
5821  { 5, OperandInfo317 },
5822  { 5, OperandInfo318 },
5823  { 6, OperandInfo319 },
5824  { 7, OperandInfo320 },
5825  { 6, OperandInfo319 },
5826  { 7, OperandInfo320 },
5827  { 5, OperandInfo317 },
5828  { 5, OperandInfo317 },
5829  { 5, OperandInfo318 },
5830  { 6, OperandInfo319 },
5831  { 7, OperandInfo320 },
5832  { 5, OperandInfo317 },
5833  { 5, OperandInfo318 },
5834  { 6, OperandInfo319 },
5835  { 7, OperandInfo320 },
5836  { 6, OperandInfo319 },
5837  { 7, OperandInfo320 },
5838  { 5, OperandInfo317 },
5839  { 5, OperandInfo317 },
5840  { 5, OperandInfo318 },
5841  { 6, OperandInfo321 },
5842  { 7, OperandInfo322 },
5843  { 6, OperandInfo319 },
5844  { 7, OperandInfo320 },
5845  { 5, OperandInfo317 },
5846  { 5, OperandInfo318 },
5847  { 6, OperandInfo321 },
5848  { 7, OperandInfo322 },
5849  { 6, OperandInfo319 },
5850  { 7, OperandInfo320 },
5851  { 6, OperandInfo319 },
5852  { 7, OperandInfo320 },
5853  { 5, OperandInfo317 },
5854  { 5, OperandInfo317 },
5855  { 5, OperandInfo318 },
5856  { 6, OperandInfo319 },
5857  { 7, OperandInfo320 },
5858  { 5, OperandInfo317 },
5859  { 5, OperandInfo318 },
5860  { 6, OperandInfo319 },
5861  { 7, OperandInfo320 },
5862  { 6, OperandInfo319 },
5863  { 7, OperandInfo320 },
5864  { 5, OperandInfo323 },
5865  { 5, OperandInfo324 },
5866  { 5, OperandInfo324 },
5867  { 7, OperandInfo325 },
5868  { 7, OperandInfo325 },
5869  { 6, OperandInfo326 },
5870  { 7, OperandInfo327 },
5871  { 5, OperandInfo323 },
5872  { 5, OperandInfo324 },
5873  { 5, OperandInfo324 },
5874  { 7, OperandInfo325 },
5875  { 7, OperandInfo325 },
5876  { 6, OperandInfo326 },
5877  { 7, OperandInfo327 },
5878  { 5, OperandInfo323 },
5879  { 5, OperandInfo324 },
5880  { 5, OperandInfo324 },
5881  { 7, OperandInfo325 },
5882  { 7, OperandInfo325 },
5883  { 6, OperandInfo326 },
5884  { 7, OperandInfo327 },
5885  { 5, OperandInfo323 },
5886  { 5, OperandInfo324 },
5887  { 5, OperandInfo324 },
5888  { 7, OperandInfo325 },
5889  { 7, OperandInfo325 },
5890  { 6, OperandInfo326 },
5891  { 7, OperandInfo327 },
5892  { 7, OperandInfo328 },
5893  { 6, OperandInfo315 },
5894  { 8, OperandInfo316 },
5895  { 9, OperandInfo329 },
5896  { 7, OperandInfo328 },
5897  { 6, OperandInfo315 },
5898  { 8, OperandInfo316 },
5899  { 9, OperandInfo329 },
5900  { 7, OperandInfo328 },
5901  { 6, OperandInfo315 },
5902  { 8, OperandInfo316 },
5903  { 9, OperandInfo329 },
5904  { 7, OperandInfo328 },
5905  { 6, OperandInfo330 },
5906  { 8, OperandInfo331 },
5907  { 9, OperandInfo329 },
5908  { 7, OperandInfo328 },
5909  { 6, OperandInfo330 },
5910  { 8, OperandInfo331 },
5911  { 9, OperandInfo329 },
5912  { 5, OperandInfo323 },
5913  { 6, OperandInfo326 },
5914  { 7, OperandInfo327 },
5915  { 5, OperandInfo323 },
5916  { 6, OperandInfo326 },
5917  { 7, OperandInfo327 },
5918  { 5, OperandInfo323 },
5919  { 6, OperandInfo326 },
5920  { 7, OperandInfo327 },
5921  { 5, OperandInfo323 },
5922  { 6, OperandInfo326 },
5923  { 7, OperandInfo327 },
5924  { 5, OperandInfo323 },
5925  { 6, OperandInfo326 },
5926  { 7, OperandInfo327 },
5927  { 5, OperandInfo323 },
5928  { 6, OperandInfo326 },
5929  { 7, OperandInfo327 },
5930  { 5, OperandInfo317 },
5931  { 5, OperandInfo318 },
5932  { 6, OperandInfo321 },
5933  { 7, OperandInfo332 },
5934  { 6, OperandInfo319 },
5935  { 7, OperandInfo320 },
5936  { 5, OperandInfo317 },
5937  { 5, OperandInfo318 },
5938  { 6, OperandInfo321 },
5939  { 7, OperandInfo332 },
5940  { 6, OperandInfo319 },
5941  { 7, OperandInfo320 },
5942  { 5, OperandInfo317 },
5943  { 5, OperandInfo318 },
5944  { 6, OperandInfo321 },
5945  { 7, OperandInfo332 },
5946  { 6, OperandInfo319 },
5947  { 7, OperandInfo320 },
5948  { 8, OperandInfo333 },
5949  { 6, OperandInfo330 },
5950  { 8, OperandInfo331 },
5951  { 10, OperandInfo334 },
5952  { 8, OperandInfo333 },
5953  { 6, OperandInfo330 },
5954  { 8, OperandInfo331 },
5955  { 10, OperandInfo334 },
5956  { 8, OperandInfo333 },
5957  { 6, OperandInfo330 },
5958  { 8, OperandInfo331 },
5959  { 10, OperandInfo334 },
5960  { 8, OperandInfo333 },
5961  { 6, OperandInfo335 },
5962  { 8, OperandInfo336 },
5963  { 10, OperandInfo334 },
5964  { 8, OperandInfo333 },
5965  { 6, OperandInfo335 },
5966  { 8, OperandInfo336 },
5967  { 10, OperandInfo334 },
5968  { 7, OperandInfo337 },
5969  { 5, OperandInfo318 },
5970  { 7, OperandInfo322 },
5971  { 9, OperandInfo338 },
5972  { 7, OperandInfo337 },
5973  { 5, OperandInfo318 },
5974  { 7, OperandInfo322 },
5975  { 9, OperandInfo338 },
5976  { 7, OperandInfo337 },
5977  { 5, OperandInfo318 },
5978  { 7, OperandInfo322 },
5979  { 9, OperandInfo338 },
5980  { 7, OperandInfo337 },
5981  { 7, OperandInfo325 },
5982  { 9, OperandInfo338 },
5983  { 5, OperandInfo324 },
5984  { 7, OperandInfo325 },
5985  { 7, OperandInfo337 },
5986  { 7, OperandInfo325 },
5987  { 9, OperandInfo338 },
5988  { 5, OperandInfo324 },
5989  { 7, OperandInfo325 },
5990  { 7, OperandInfo337 },
5991  { 7, OperandInfo325 },
5992  { 9, OperandInfo338 },
5993  { 5, OperandInfo324 },
5994  { 7, OperandInfo325 },
5995  { 9, OperandInfo339 },
5996  { 6, OperandInfo330 },
5997  { 8, OperandInfo331 },
5998  { 11, OperandInfo340 },
5999  { 9, OperandInfo339 },
6000  { 6, OperandInfo330 },
6001  { 8, OperandInfo331 },
6002  { 11, OperandInfo340 },
6003  { 9, OperandInfo339 },
6004  { 6, OperandInfo330 },
6005  { 8, OperandInfo331 },
6006  { 11, OperandInfo340 },
6007  { 9, OperandInfo339 },
6008  { 6, OperandInfo335 },
6009  { 8, OperandInfo336 },
6010  { 11, OperandInfo340 },
6011  { 9, OperandInfo339 },
6012  { 6, OperandInfo335 },
6013  { 8, OperandInfo336 },
6014  { 11, OperandInfo340 },
6015  { 8, OperandInfo341 },
6016  { 5, OperandInfo318 },
6017  { 7, OperandInfo322 },
6018  { 10, OperandInfo342 },
6019  { 8, OperandInfo341 },
6020  { 5, OperandInfo318 },
6021  { 7, OperandInfo322 },
6022  { 10, OperandInfo342 },
6023  { 8, OperandInfo341 },
6024  { 5, OperandInfo318 },
6025  { 7, OperandInfo322 },
6026  { 10, OperandInfo342 },
6027  { 8, OperandInfo341 },
6028  { 7, OperandInfo325 },
6029  { 10, OperandInfo342 },
6030  { 5, OperandInfo324 },
6031  { 7, OperandInfo325 },
6032  { 8, OperandInfo341 },
6033  { 7, OperandInfo325 },
6034  { 10, OperandInfo342 },
6035  { 5, OperandInfo324 },
6036  { 7, OperandInfo325 },
6037  { 8, OperandInfo341 },
6038  { 7, OperandInfo325 },
6039  { 10, OperandInfo342 },
6040  { 5, OperandInfo324 },
6041  { 7, OperandInfo325 },
6042  { 5, OperandInfo50 },
6043  { 4, OperandInfo132 },
6044  { 5, OperandInfo50 },
6045  { 4, OperandInfo269 },
6046  { 5, OperandInfo50 },
6047  { 4, OperandInfo132 },
6048  { 5, OperandInfo50 },
6049  { 5, OperandInfo76 },
6050  { 5, OperandInfo270 },
6051  { 5, OperandInfo271 },
6052  { 5, OperandInfo196 },
6053  { 5, OperandInfo201 },
6054  { 5, OperandInfo202 },
6055  { 5, OperandInfo202 },
6056  { 5, OperandInfo202 },
6057  { 5, OperandInfo195 },
6058  { 5, OperandInfo195 },
6059  { 5, OperandInfo195 },
6060  { 5, OperandInfo195 },
6061  { 5, OperandInfo195 },
6062  { 5, OperandInfo195 },
6063  { 5, OperandInfo203 },
6064  { 5, OperandInfo204 },
6065  { 5, OperandInfo204 },
6066  { 5, OperandInfo204 },
6067  { 5, OperandInfo204 },
6068  { 5, OperandInfo204 },
6069  { 5, OperandInfo204 },
6070  { 5, OperandInfo196 },
6071  { 5, OperandInfo197 },
6072  { 5, OperandInfo196 },
6073  { 5, OperandInfo197 },
6074  { 5, OperandInfo197 },
6075  { 5, OperandInfo196 },
6076  { 5, OperandInfo196 },
6077  { 5, OperandInfo197 },
6078  { 5, OperandInfo196 },
6079  { 5, OperandInfo197 },
6080  { 5, OperandInfo197 },
6081  { 5, OperandInfo196 },
6082  { 6, OperandInfo343 },
6083  { 6, OperandInfo344 },
6084  { 5, OperandInfo196 },
6085  { 5, OperandInfo345 },
6086  { 5, OperandInfo196 },
6087  { 5, OperandInfo346 },
6088  { 5, OperandInfo196 },
6089  { 5, OperandInfo346 },
6090  { 6, OperandInfo194 },
6091  { 6, OperandInfo347 },
6092  { 6, OperandInfo194 },
6093  { 6, OperandInfo348 },
6094  { 6, OperandInfo194 },
6095  { 6, OperandInfo348 },
6096  { 5, OperandInfo308 },
6097  { 5, OperandInfo309 },
6098  { 5, OperandInfo309 },
6099  { 4, OperandInfo223 },
6100  { 4, OperandInfo199 },
6101  { 4, OperandInfo199 },
6102  { 4, OperandInfo223 },
6103  { 4, OperandInfo349 },
6104  { 4, OperandInfo199 },
6105  { 5, OperandInfo308 },
6106  { 5, OperandInfo309 },
6107  { 5, OperandInfo309 },
6108  { 5, OperandInfo308 },
6109  { 5, OperandInfo309 },
6110  { 5, OperandInfo309 },
6111  { 4, OperandInfo223 },
6112  { 4, OperandInfo199 },
6113  { 4, OperandInfo199 },
6114  { 4, OperandInfo223 },
6115  { 4, OperandInfo349 },
6116  { 4, OperandInfo199 },
6117  { 5, OperandInfo308 },
6118  { 5, OperandInfo309 },
6119  { 5, OperandInfo309 },
6120  { 6, OperandInfo343 },
6121  { 6, OperandInfo343 },
6122  { 6, OperandInfo343 },
6123  { 6, OperandInfo344 },
6124  { 6, OperandInfo344 },
6125  { 6, OperandInfo344 },
6126  { 5, OperandInfo197 },
6127  { 5, OperandInfo196 },
6128  { 5, OperandInfo196 },
6129  { 5, OperandInfo197 },
6130  { 5, OperandInfo197 },
6131  { 5, OperandInfo196 },
6132  { 4, OperandInfo304 },
6133  { 5, OperandInfo305 },
6134  { 4, OperandInfo173 },
6135  { 5, OperandInfo306 },
6136  { 5, OperandInfo308 },
6137  { 5, OperandInfo309 },
6138  { 5, OperandInfo309 },
6139  { 4, OperandInfo224 },
6140  { 4, OperandInfo310 },
6141  { 4, OperandInfo199 },
6142  { 5, OperandInfo308 },
6143  { 5, OperandInfo309 },
6144  { 5, OperandInfo309 },
6145  { 6, OperandInfo343 },
6146  { 6, OperandInfo343 },
6147  { 6, OperandInfo344 },
6148  { 6, OperandInfo344 },
6149  { 6, OperandInfo344 },
6150  { 6, OperandInfo343 },
6151  { 6, OperandInfo343 },
6152  { 6, OperandInfo344 },
6153  { 6, OperandInfo344 },
6154  { 6, OperandInfo344 },
6155  { 4, OperandInfo132 },
6156  { 5, OperandInfo50 },
6157  { 4, OperandInfo132 },
6158  { 5, OperandInfo50 },
6159  { 4, OperandInfo132 },
6160  { 5, OperandInfo50 },
6161  { 4, OperandInfo132 },
6162  { 5, OperandInfo50 },
6163  { 4, OperandInfo132 },
6164  { 5, OperandInfo50 },
6165  { 4, OperandInfo132 },
6166  { 5, OperandInfo50 },
6167  { 4, OperandInfo132 },
6168  { 5, OperandInfo50 },
6169  { 4, OperandInfo132 },
6170  { 5, OperandInfo50 },
6171  { 6, OperandInfo350 },
6172  { 6, OperandInfo351 },
6173  { 7, OperandInfo352 },
6174  { 6, OperandInfo353 },
6175  { 5, OperandInfo354 },
6176  { 6, OperandInfo355 },
6177  { 7, OperandInfo356 },
6178  { 4, OperandInfo357 },
6179  { 6, OperandInfo350 },
6180  { 6, OperandInfo351 },
6181  { 7, OperandInfo352 },
6182  { 6, OperandInfo350 },
6183  { 6, OperandInfo351 },
6184  { 3, OperandInfo107 },
6185  { 5, OperandInfo90 },
6186  { 6, OperandInfo358 },
6187  { 6, OperandInfo350 },
6188  { 6, OperandInfo351 },
6189  { 7, OperandInfo352 },
6190  { 3, OperandInfo163 },
6191  { 3, OperandInfo107 },
6192  { 8, OperandInfo121 },
6193  { 8, OperandInfo121 },
6194  { 2, OperandInfo105 },
6195  { 4, OperandInfo359 },
6196  { 4, OperandInfo86 },
6197  { 4, OperandInfo360 },
6198  { 5, OperandInfo361 },
6199  { 4, OperandInfo86 },
6200  { 4, OperandInfo360 },
6201  { 5, OperandInfo361 },
6202  { 1, OperandInfo2 },
6203  { 2, OperandInfo7 },
6204  { 3, OperandInfo4 },
6205  { 3, OperandInfo362 },
6206  { 3, OperandInfo362 },
6207  { 3, OperandInfo362 },
6208  { 3, OperandInfo362 },
6209  { 3, OperandInfo362 },
6210  { 3, OperandInfo362 },
6211  { 3, OperandInfo128 },
6212  { 2, OperandInfo105 },
6213  { 2, OperandInfo105 },
6214  { 2, OperandInfo105 },
6215  { 3, OperandInfo128 },
6216  { 3, OperandInfo128 },
6217  { 6, OperandInfo350 },
6218  { 6, OperandInfo351 },
6219  { 7, OperandInfo352 },
6220  { 3, OperandInfo128 },
6221  { 1, OperandInfo2 },
6222  { 3, OperandInfo128 },
6223  { 2, OperandInfo7 },
6224  { 2, OperandInfo363 },
6225  { 2, OperandInfo363 },
6226  { 4, OperandInfo364 },
6227  { 4, OperandInfo364 },
6228  { 4, OperandInfo364 },
6229  { 4, OperandInfo364 },
6230  { 5, OperandInfo365 },
6231  { 4, OperandInfo364 },
6232  { 4, OperandInfo364 },
6233  { 6, OperandInfo136 },
6234  { 6, OperandInfo137 },
6235  { 6, OperandInfo136 },
6236  { 6, OperandInfo136 },
6237  { 6, OperandInfo136 },
6238  { 6, OperandInfo137 },
6239  { 6, OperandInfo136 },
6240  { 6, OperandInfo136 },
6241  { 6, OperandInfo136 },
6242  { 6, OperandInfo137 },
6243  { 6, OperandInfo136 },
6244  { 6, OperandInfo136 },
6245  { 6, OperandInfo136 },
6246  { 6, OperandInfo137 },
6247  { 6, OperandInfo136 },
6248  { 6, OperandInfo136 },
6249  { 4, OperandInfo132 },
6250  { 5, OperandInfo50 },
6251  { 4, OperandInfo132 },
6252  { 5, OperandInfo50 },
6253  { 5, OperandInfo366 },
6254  { 6, OperandInfo139 },
6255  { 6, OperandInfo139 },
6256  { 5, OperandInfo140 },
6257  { 5, OperandInfo140 },
6258  { 4, OperandInfo86 },
6259  { 6, OperandInfo367 },
6260  { 7, OperandInfo368 },
6261  { 7, OperandInfo368 },
6262  { 6, OperandInfo369 },
6263  { 5, OperandInfo370 },
6264  { 4, OperandInfo364 },
6265  { 5, OperandInfo365 },
6266  { 4, OperandInfo364 },
6267  { 5, OperandInfo366 },
6268  { 6, OperandInfo139 },
6269  { 6, OperandInfo139 },
6270  { 5, OperandInfo140 },
6271  { 5, OperandInfo140 },
6272  { 4, OperandInfo86 },
6273  { 6, OperandInfo367 },
6274  { 5, OperandInfo366 },
6275  { 6, OperandInfo139 },
6276  { 6, OperandInfo139 },
6277  { 5, OperandInfo140 },
6278  { 5, OperandInfo140 },
6279  { 4, OperandInfo86 },
6280  { 6, OperandInfo367 },
6281  { 5, OperandInfo366 },
6282  { 6, OperandInfo139 },
6283  { 6, OperandInfo139 },
6284  { 5, OperandInfo140 },
6285  { 5, OperandInfo140 },
6286  { 4, OperandInfo86 },
6287  { 6, OperandInfo367 },
6288  { 5, OperandInfo366 },
6289  { 6, OperandInfo139 },
6290  { 6, OperandInfo139 },
6291  { 5, OperandInfo65 },
6292  { 5, OperandInfo65 },
6293  { 4, OperandInfo52 },
6294  { 6, OperandInfo371 },
6295  { 6, OperandInfo350 },
6296  { 6, OperandInfo351 },
6297  { 6, OperandInfo350 },
6298  { 6, OperandInfo351 },
6299  { 8, OperandInfo148 },
6300  { 8, OperandInfo148 },
6301  { 7, OperandInfo372 },
6302  { 7, OperandInfo372 },
6303  { 6, OperandInfo373 },
6304  { 6, OperandInfo373 },
6305  { 5, OperandInfo90 },
6306  { 5, OperandInfo374 },
6307  { 4, OperandInfo357 },
6308  { 5, OperandInfo375 },
6309  { 4, OperandInfo359 },
6310  { 4, OperandInfo359 },
6311  { 8, OperandInfo159 },
6312  { 8, OperandInfo159 },
6313  { 7, OperandInfo376 },
6314  { 7, OperandInfo376 },
6315  { 3, OperandInfo103 },
6316  { 4, OperandInfo357 },
6317  { 4, OperandInfo357 },
6318  { 3, OperandInfo103 },
6319  { 4, OperandInfo377 },
6320  { 4, OperandInfo377 },
6321  { 4, OperandInfo377 },
6322  { 5, OperandInfo378 },
6323  { 5, OperandInfo374 },
6324  { 5, OperandInfo379 },
6325  { 6, OperandInfo380 },
6326  { 6, OperandInfo350 },
6327  { 6, OperandInfo351 },
6328  { 7, OperandInfo352 },
6329  { 6, OperandInfo350 },
6330  { 6, OperandInfo351 },
6331  { 7, OperandInfo352 },
6332  { 6, OperandInfo381 },
6333  { 6, OperandInfo381 },
6334  { 4, OperandInfo382 },
6335  { 4, OperandInfo382 },
6336  { 5, OperandInfo383 },
6337  { 4, OperandInfo382 },
6338  { 4, OperandInfo382 },
6339  { 3, OperandInfo128 },
6340  { 5, OperandInfo383 },
6341  { 4, OperandInfo382 },
6342  { 4, OperandInfo382 },
6343  { 3, OperandInfo128 },
6344  { 5, OperandInfo383 },
6345  { 5, OperandInfo378 },
6346  { 5, OperandInfo378 },
6347  { 5, OperandInfo378 },
6348  { 5, OperandInfo378 },
6349  { 5, OperandInfo378 },
6350  { 5, OperandInfo378 },
6351  { 5, OperandInfo378 },
6352  { 5, OperandInfo378 },
6353  { 5, OperandInfo378 },
6354  { 5, OperandInfo378 },
6355  { 4, OperandInfo359 },
6356  { 4, OperandInfo359 },
6357  { 4, OperandInfo359 },
6358  { 4, OperandInfo359 },
6359  { 3, OperandInfo103 },
6360  { 3, OperandInfo103 },
6361  { 3, OperandInfo103 },
6362  { 3, OperandInfo103 },
6363  { 6, OperandInfo350 },
6364  { 6, OperandInfo351 },
6365  { 5, OperandInfo379 },
6366  { 6, OperandInfo350 },
6367  { 6, OperandInfo351 },
6368  { 7, OperandInfo352 },
6369  { 5, OperandInfo378 },
6370  { 5, OperandInfo378 },
6371  { 5, OperandInfo378 },
6372  { 6, OperandInfo350 },
6373  { 6, OperandInfo351 },
6374  { 7, OperandInfo352 },
6375  { 6, OperandInfo384 },
6376  { 5, OperandInfo378 },
6377  { 5, OperandInfo33 },
6378  { 1, OperandInfo2 },
6379  { 2, OperandInfo105 },
6380  { 5, OperandInfo378 },
6381  { 5, OperandInfo378 },
6382  { 5, OperandInfo378 },
6383  { 5, OperandInfo378 },
6384  { 5, OperandInfo378 },
6385  { 5, OperandInfo378 },
6386  { 3, OperandInfo128 },
6387  { 6, OperandInfo373 },
6388  { 6, OperandInfo373 },
6389  { 6, OperandInfo373 },
6390  { 6, OperandInfo373 },
6391  { 8, OperandInfo385 },
6392  { 8, OperandInfo385 },
6393  { 8, OperandInfo385 },
6394  { 8, OperandInfo385 },
6395  { 8, OperandInfo385 },
6396  { 8, OperandInfo385 },
6397  { 8, OperandInfo385 },
6398  { 6, OperandInfo373 },
6399  { 6, OperandInfo373 },
6400  { 6, OperandInfo373 },
6401  { 6, OperandInfo373 },
6402  { 6, OperandInfo373 },
6403  { 6, OperandInfo373 },
6404  { 8, OperandInfo385 },
6405  { 8, OperandInfo385 },
6406  { 6, OperandInfo373 },
6407  { 6, OperandInfo373 },
6408  { 6, OperandInfo373 },
6409  { 6, OperandInfo373 },
6410  { 5, OperandInfo378 },
6411  { 5, OperandInfo378 },
6412  { 5, OperandInfo378 },
6413  { 5, OperandInfo378 },
6414  { 5, OperandInfo378 },
6415  { 5, OperandInfo378 },
6416  { 6, OperandInfo373 },
6417  { 5, OperandInfo378 },
6418  { 5, OperandInfo378 },
6419  { 5, OperandInfo378 },
6420  { 5, OperandInfo378 },
6421  { 5, OperandInfo378 },
6422  { 5, OperandInfo378 },
6423  { 3, OperandInfo128 },
6424  { 3, OperandInfo128 },
6425  { 3, OperandInfo128 },
6426  { 3, OperandInfo128 },
6427  { 6, OperandInfo386 },
6428  { 5, OperandInfo387 },
6429  { 5, OperandInfo378 },
6430  { 5, OperandInfo378 },
6431  { 5, OperandInfo378 },
6432  { 6, OperandInfo136 },
6433  { 6, OperandInfo137 },
6434  { 6, OperandInfo136 },
6435  { 6, OperandInfo136 },
6436  { 6, OperandInfo136 },
6437  { 6, OperandInfo137 },
6438  { 6, OperandInfo136 },
6439  { 6, OperandInfo136 },
6440  { 6, OperandInfo136 },
6441  { 6, OperandInfo137 },
6442  { 6, OperandInfo136 },
6443  { 6, OperandInfo136 },
6444  { 6, OperandInfo136 },
6445  { 6, OperandInfo137 },
6446  { 6, OperandInfo136 },
6447  { 6, OperandInfo136 },
6448  { 4, OperandInfo364 },
6449  { 4, OperandInfo364 },
6450  { 5, OperandInfo388 },
6451  { 5, OperandInfo388 },
6452  { 6, OperandInfo389 },
6453  { 5, OperandInfo388 },
6454  { 4, OperandInfo364 },
6455  { 4, OperandInfo132 },
6456  { 5, OperandInfo50 },
6457  { 4, OperandInfo132 },
6458  { 5, OperandInfo50 },
6459  { 5, OperandInfo366 },
6460  { 6, OperandInfo390 },
6461  { 6, OperandInfo390 },
6462  { 5, OperandInfo366 },
6463  { 5, OperandInfo366 },
6464  { 6, OperandInfo391 },
6465  { 7, OperandInfo392 },
6466  { 7, OperandInfo392 },
6467  { 6, OperandInfo369 },
6468  { 6, OperandInfo393 },
6469  { 5, OperandInfo388 },
6470  { 6, OperandInfo389 },
6471  { 5, OperandInfo388 },
6472  { 5, OperandInfo366 },
6473  { 6, OperandInfo390 },
6474  { 6, OperandInfo390 },
6475  { 5, OperandInfo366 },
6476  { 5, OperandInfo366 },
6477  { 6, OperandInfo391 },
6478  { 5, OperandInfo366 },
6479  { 6, OperandInfo394 },
6480  { 6, OperandInfo394 },
6481  { 5, OperandInfo65 },
6482  { 5, OperandInfo65 },
6483  { 6, OperandInfo371 },
6484  { 3, OperandInfo128 },
6485  { 6, OperandInfo353 },
6486  { 5, OperandInfo354 },
6487  { 6, OperandInfo355 },
6488  { 7, OperandInfo356 },
6489  { 6, OperandInfo381 },
6490  { 6, OperandInfo381 },
6491  { 6, OperandInfo381 },
6492  { 5, OperandInfo97 },
6493  { 5, OperandInfo97 },
6494  { 5, OperandInfo97 },
6495  { 4, OperandInfo395 },
6496  { 4, OperandInfo395 },
6497  { 4, OperandInfo86 },
6498  { 4, OperandInfo360 },
6499  { 5, OperandInfo361 },
6500  { 3, OperandInfo128 },
6501  { 4, OperandInfo86 },
6502  { 4, OperandInfo360 },
6503  { 5, OperandInfo361 },
6504  { 4, OperandInfo396 },
6505  { 4, OperandInfo396 },
6506  { 4, OperandInfo396 },
6507  { 4, OperandInfo396 },
6508  { 5, OperandInfo378 },
6509  { 5, OperandInfo378 },
6510  { 5, OperandInfo378 },
6511  { 6, OperandInfo384 },
6512  { 1, OperandInfo2 },
6513  { 5, OperandInfo378 },
6514  { 5, OperandInfo378 },
6515  { 5, OperandInfo378 },
6516  { 5, OperandInfo378 },
6517  { 5, OperandInfo378 },
6518  { 5, OperandInfo378 },
6519  { 5, OperandInfo378 },
6520  { 8, OperandInfo385 },
6521  { 8, OperandInfo385 },
6522  { 6, OperandInfo373 },
6523  { 5, OperandInfo378 },
6524  { 5, OperandInfo378 },
6525  { 5, OperandInfo378 },
6526  { 5, OperandInfo378 },
6527  { 5, OperandInfo378 },
6528  { 5, OperandInfo378 },
6529  { 5, OperandInfo378 },
6530  { 6, OperandInfo373 },
6531  { 6, OperandInfo386 },
6532  { 5, OperandInfo387 },
6533  { 5, OperandInfo378 },
6534  { 5, OperandInfo378 },
6535  { 5, OperandInfo378 },
6536  { 6, OperandInfo381 },
6537  { 6, OperandInfo381 },
6538  { 6, OperandInfo381 },
6539  { 5, OperandInfo97 },
6540  { 5, OperandInfo97 },
6541  { 5, OperandInfo97 },
6542  { 6, OperandInfo397 },
6543  { 5, OperandInfo58 },
6544  { 6, OperandInfo398 },
6545  { 6, OperandInfo399 },
6546  { 5, OperandInfo400 },
6547  { 5, OperandInfo401 },
6548  { 6, OperandInfo402 },
6549  { 5, OperandInfo403 },
6550  { 5, OperandInfo404 },
6551  { 4, OperandInfo405 },
6552  { 6, OperandInfo397 },
6553  { 6, OperandInfo398 },
6554  { 6, OperandInfo397 },
6555  { 3, OperandInfo107 },
6556  { 6, OperandInfo397 },
6557  { 1, OperandInfo2 },
6558  { 3, OperandInfo406 },
6559  { 3, OperandInfo407 },
6560  { 3, OperandInfo406 },
6561  { 3, OperandInfo408 },
6562  { 3, OperandInfo103 },
6563  { 3, OperandInfo103 },
6564  { 3, OperandInfo107 },
6565  { 2, OperandInfo409 },
6566  { 2, OperandInfo409 },
6567  { 4, OperandInfo410 },
6568  { 4, OperandInfo123 },
6569  { 4, OperandInfo108 },
6570  { 4, OperandInfo410 },
6571  { 2, OperandInfo7 },
6572  { 6, OperandInfo397 },
6573  { 3, OperandInfo128 },
6574  { 1, OperandInfo2 },
6575  { 2, OperandInfo31 },
6576  { 2, OperandInfo31 },
6577  { 2, OperandInfo363 },
6578  { 4, OperandInfo411 },
6579  { 5, OperandInfo412 },
6580  { 5, OperandInfo413 },
6581  { 5, OperandInfo412 },
6582  { 5, OperandInfo413 },
6583  { 5, OperandInfo413 },
6584  { 5, OperandInfo413 },
6585  { 5, OperandInfo412 },
6586  { 4, OperandInfo405 },
6587  { 5, OperandInfo413 },
6588  { 5, OperandInfo414 },
6589  { 6, OperandInfo398 },
6590  { 6, OperandInfo397 },
6591  { 6, OperandInfo398 },
6592  { 6, OperandInfo397 },
6593  { 2, OperandInfo363 },
6594  { 5, OperandInfo415 },
6595  { 4, OperandInfo123 },
6596  { 6, OperandInfo416 },
6597  { 5, OperandInfo417 },
6598  { 6, OperandInfo397 },
6599  { 3, OperandInfo418 },
6600  { 3, OperandInfo112 },
6601  { 3, OperandInfo112 },
6602  { 4, OperandInfo410 },
6603  { 4, OperandInfo410 },
6604  { 4, OperandInfo410 },
6605  { 6, OperandInfo397 },
6606  { 5, OperandInfo417 },
6607  { 6, OperandInfo397 },
6608  { 1, OperandInfo2 },
6609  { 5, OperandInfo419 },
6610  { 5, OperandInfo412 },
6611  { 5, OperandInfo413 },
6612  { 5, OperandInfo412 },
6613  { 5, OperandInfo413 },
6614  { 5, OperandInfo412 },
6615  { 5, OperandInfo413 },
6616  { 5, OperandInfo414 },
6617  { 6, OperandInfo398 },
6618  { 6, OperandInfo399 },
6619  { 6, OperandInfo402 },
6620  { 5, OperandInfo403 },
6621  { 3, OperandInfo128 },
6622  { 4, OperandInfo410 },
6623  { 4, OperandInfo410 },
6624  { 0, nullptr },
6625  { 4, OperandInfo410 },
6626  { 1, OperandInfo2 },
6627  { 4, OperandInfo410 },
6628  { 4, OperandInfo410 },
6629  { 0, nullptr },
6630};
6631
6632#endif // GET_INSTRINFO_MC_DESC
6633