1 2IF !(__page_zero_present) 3 4SECTION code_crt_init 5 ; Internal register definitions begin 6 ; at __IO_BASE_ADDRESS = 0x00C0 7 ld a,__IO_BASE_ADDRESS 8 out0 (ICR),a ; Move the internal register to 0x00C0 9 10 xor a ; Zero Accumulator 11 12 ; Clear Refresh Control Reg (RCR) 13 out0 (RCR),a ; DRAM Refresh Enable (0 Disabled) 14 15 ; Clear INT/TRAP Control Register (ITC) 16 out0 (ITC),a ; Disable all external interrupts. 17 18 ; Set Operation Mode Control Reg (OMCR) 19 ld a,OMCR_M1E ; Enable M1 for single step, disable 64180 I/O _RD Mode 20 out0 (OMCR),a ; X80 Mode (M1 Disabled, IOC Disabled) 21 22 ; DMA/Wait Control Reg Set I/O Wait States 23 ld a,DCNTL_MWI0|DCNTL_IWI1 24 out0 (DCNTL),a ; 1 Memory Wait & 3 I/O Wait 25 26 ; Set PHI = CCR x 2 = 36.864MHz 27 ; if using ZS8180 or Z80182 at High-Speed 28 ld a,CMR_X2 ; Set Hi-Speed flag 29 out0 (CMR),a ; CPU Clock Multiplier Reg (CMR) 30 31 ; Set CCR = crystal = 18.432MHz 32 ; if using ZS8180 or Z80182 at High-Speed 33 ld a,CCR_XTAL_X2 ; Set Hi-Speed flag 34 out0 (CCR),a ; CPU Control Reg (CCR) 35 36 ; Set Logical RAM Addresses - For Monitor 37 ; $F000-$FFFF RAM BIOS 38 ; $E000-$EFFF RAM HEAP CA1 -> $E. 39 ; $0000-$DFFF Flash BANK -> $.0 40 41 ; Later, set Logical RAM Addresses for Application 42 ; $F000-$FFFF RAM BIOS CA1 -> $F. 43 ; $0000-$EFFF RAM BANK -> $.0 44 45 ld a,$E0 ; Set New Common 1 / Bank Areas for RAM / Flash 46 out0 (CBAR),a 47 48 ld a,$F0 ; Set Common 1 Base Physical $FE000 -> $F0 49 out0 (CBR),a 50 51 ld a,$00 ; Set Bank Base Physical $00000 -> $00 52 out0 (BBR),a 53 54 ; we do 256 ticks per second 55 ld hl,__CPU_CLOCK/__CPU_TIMER_SCALE/__CLOCKS_PER_SECOND-1 56 out0 (RLDR0L),l 57 out0 (RLDR0H),h 58 ; enable down counting and interrupts for PRT0 59 ld a,TCR_TIE0|TCR_TDE0 60 out0 (TCR),a ; using the driver/z180/system_tick.asm 61 62 EXTERN asm_asci0_init 63 call asm_asci0_init ; initialise the asci0 64 65 EXTERN asm_asci1_init 66 call asm_asci1_init ; and the asci1 interfaces 67 68ENDIF 69