1 /* Definitions of target machine for GNU compiler. 2 Motorola 68HC11 and 68HC12. 3 Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004 4 Free Software Foundation, Inc. 5 Contributed by Stephane Carrez (stcarrez@nerim.fr) 6 7 This file is part of GCC. 8 9 GCC is free software; you can redistribute it and/or modify 10 it under the terms of the GNU General Public License as published by 11 the Free Software Foundation; either version 2, or (at your option) 12 any later version. 13 14 GCC is distributed in the hope that it will be useful, 15 but WITHOUT ANY WARRANTY; without even the implied warranty of 16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 GNU General Public License for more details. 18 19 You should have received a copy of the GNU General Public License 20 along with GCC; see the file COPYING. If not, write to 21 the Free Software Foundation, 59 Temple Place - Suite 330, 22 Boston, MA 02111-1307, USA. 23 24 Note: 25 A first 68HC11 port was made by Otto Lind (otto@coactive.com) 26 on gcc 2.6.3. I have used it as a starting point for this port. 27 However, this new port is a complete re-write. Its internal 28 design is completely different. The generated code is not 29 compatible with the gcc 2.6.3 port. 30 31 The gcc 2.6.3 port is available at: 32 33 ftp.unina.it/pub/electronics/motorola/68hc11/gcc/gcc-6811-fsf.tar.gz 34 35 */ 36 37 /***************************************************************************** 38 ** 39 ** Controlling the Compilation Driver, `gcc' 40 ** 41 *****************************************************************************/ 42 43 #undef ENDFILE_SPEC 44 45 /* Compile and assemble for a 68hc11 unless there is a -m68hc12 option. */ 46 #ifndef ASM_SPEC 47 #define ASM_SPEC \ 48 "%{m68hc12:-m68hc12}" \ 49 "%{m68hcs12:-m68hcs12}" \ 50 "%{!m68hc12:%{!m68hcs12:-m68hc11}} " \ 51 "%{mshort:-mshort}%{!mshort:-mlong} " \ 52 "%{fshort-double:-mshort-double}%{!fshort-double:-mlong-double}" 53 #endif 54 55 /* We need to tell the linker the target elf format. Just pass an 56 emulation option. This can be overridden by -Wl option of gcc. */ 57 #ifndef LINK_SPEC 58 #define LINK_SPEC \ 59 "%{m68hc12:-m m68hc12elf}" \ 60 "%{m68hcs12:-m m68hc12elf}" \ 61 "%{!m68hc12:%{!m68hcs12:-m m68hc11elf}} " \ 62 "%{!mnorelax:%{!m68hc12:%{!m68hcs12:-relax}}}" 63 #endif 64 65 #ifndef LIB_SPEC 66 #define LIB_SPEC "" 67 #endif 68 69 #ifndef CC1_SPEC 70 #define CC1_SPEC "" 71 #endif 72 73 #ifndef CPP_SPEC 74 #define CPP_SPEC \ 75 "%{mshort:-D__HAVE_SHORT_INT__ -D__INT__=16}\ 76 %{!mshort:-D__INT__=32}\ 77 %{m68hc12:-Dmc6812 -DMC6812 -Dmc68hc12}\ 78 %{m68hcs12:-Dmc6812 -DMC6812 -Dmc68hcs12}\ 79 %{!m68hc12:%{!m68hcs12:-Dmc6811 -DMC6811 -Dmc68hc11}}\ 80 %{fshort-double:-D__HAVE_SHORT_DOUBLE__}\ 81 %{mlong-calls:-D__USE_RTC__}" 82 #endif 83 84 #undef STARTFILE_SPEC 85 #define STARTFILE_SPEC "crt1%O%s" 86 87 /* Names to predefine in the preprocessor for this target machine. */ 88 #define TARGET_CPU_CPP_BUILTINS() \ 89 do \ 90 { \ 91 builtin_define_std ("mc68hc1x"); \ 92 } \ 93 while (0) 94 95 /* As an embedded target, we have no libc. */ 96 #ifndef inhibit_libc 97 # define inhibit_libc 98 #endif 99 100 /* Forward type declaration for prototypes definitions. 101 rtx_ptr is equivalent to rtx. Can't use the same name. */ 102 struct rtx_def; 103 typedef struct rtx_def *rtx_ptr; 104 105 union tree_node; 106 typedef union tree_node *tree_ptr; 107 108 /* We can't declare enum machine_mode forward nor include 'machmode.h' here. 109 Prototypes defined here will use an int instead. It's better than no 110 prototype at all. */ 111 typedef int enum_machine_mode; 112 113 /***************************************************************************** 114 ** 115 ** Run-time Target Specification 116 ** 117 *****************************************************************************/ 118 119 /* Run-time compilation parameters selecting different hardware subsets. */ 120 121 extern int target_flags; 122 123 extern short *reg_renumber; /* def in local_alloc.c */ 124 125 /* Macros used in the machine description to test the flags. */ 126 127 /* 6811 specific options 128 * 129 * For 68HC12, the auto inc/dec mode is disabled by default. The reason 130 * is that for most programs, the reload pass will fail because it needs 131 * more registers to save the value of the indexed register after the 132 * memory access. For simple programs, you can enable this 133 * with -mauto-incdec. 134 */ 135 136 #define MASK_SHORT 0002 /* Compile with 16-bit `int' */ 137 #define MASK_AUTO_INC_DEC 0004 138 #define MASK_M6811 0010 139 #define MASK_M6812 0020 140 #define MASK_M68S12 0040 141 #define MASK_NO_DIRECT_MODE 0100 142 #define MASK_MIN_MAX 0200 143 #define MASK_LONG_CALLS 0400 144 145 #define TARGET_OP_TIME (optimize && optimize_size == 0) 146 #define TARGET_SHORT (target_flags & MASK_SHORT) 147 #define TARGET_M6811 (target_flags & MASK_M6811) 148 #define TARGET_M6812 (target_flags & MASK_M6812) 149 #define TARGET_M68S12 (target_flags & MASK_M68S12) 150 #define TARGET_AUTO_INC_DEC (target_flags & MASK_AUTO_INC_DEC) 151 #define TARGET_MIN_MAX (target_flags & MASK_MIN_MAX) 152 #define TARGET_NO_DIRECT_MODE (target_flags & MASK_NO_DIRECT_MODE) 153 #define TARGET_RELAX (TARGET_NO_DIRECT_MODE) 154 #define TARGET_LONG_CALLS (target_flags & MASK_LONG_CALLS) 155 156 /* Default target_flags if no switches specified. */ 157 #ifndef TARGET_DEFAULT 158 # define TARGET_DEFAULT (MASK_M6811) 159 #endif 160 161 /* Define this macro as a C expression for the initializer of an 162 array of string to tell the driver program which options are 163 defaults for this target and thus do not need to be handled 164 specially when using `MULTILIB_OPTIONS'. */ 165 #ifndef MULTILIB_DEFAULTS 166 # if TARGET_DEFAULT & MASK_M6811 167 # define MULTILIB_DEFAULTS { "m68hc11" } 168 # else 169 # define MULTILIB_DEFAULTS { "m68hc12" } 170 # endif 171 #endif 172 173 /* Macro to define tables used to set the flags. This is a list in braces of 174 pairs in braces, each pair being { "NAME", VALUE } where VALUE is the bits 175 to set or minus the bits to clear. An empty string NAME is used to 176 identify the default VALUE. */ 177 178 #define TARGET_SWITCHES \ 179 { { "short", MASK_SHORT, \ 180 N_("Compile with 16-bit integer mode")}, \ 181 { "noshort", - MASK_SHORT, \ 182 N_("Compile with 32-bit integer mode")}, \ 183 { "auto-incdec", MASK_AUTO_INC_DEC, \ 184 N_("Auto pre/post decrement increment allowed")}, \ 185 { "noauto-incdec", - MASK_AUTO_INC_DEC, \ 186 N_("Auto pre/post decrement increment not allowed")}, \ 187 { "inmax", MASK_MIN_MAX, \ 188 N_("Min/max instructions allowed")}, \ 189 { "nominmax", - MASK_MIN_MAX, \ 190 N_("Min/max instructions not allowed")}, \ 191 { "long-calls", MASK_LONG_CALLS, \ 192 N_("Use call and rtc for function calls and returns")}, \ 193 { "nolong-calls", - MASK_LONG_CALLS, \ 194 N_("Use jsr and rts for function calls and returns")}, \ 195 { "relax", MASK_NO_DIRECT_MODE, \ 196 N_("Do not use direct addressing mode for soft registers")},\ 197 { "norelax", -MASK_NO_DIRECT_MODE, \ 198 N_("Use direct addressing mode for soft registers")}, \ 199 { "68hc11", MASK_M6811, \ 200 N_("Compile for a 68HC11")}, \ 201 { "68hc12", MASK_M6812, \ 202 N_("Compile for a 68HC12")}, \ 203 { "68hcs12", MASK_M6812 | MASK_M68S12, \ 204 N_("Compile for a 68HCS12")}, \ 205 { "6811", MASK_M6811, \ 206 N_("Compile for a 68HC11")}, \ 207 { "6812", MASK_M6812, \ 208 N_("Compile for a 68HC12")}, \ 209 { "68S12", MASK_M6812 | MASK_M68S12, \ 210 N_("Compile for a 68HCS12")}, \ 211 { "", TARGET_DEFAULT, 0 }} 212 213 /* This macro is similar to `TARGET_SWITCHES' but defines names of 214 command options that have values. Its definition is an 215 initializer with a subgrouping for each command option. 216 217 Each subgrouping contains a string constant, that defines the 218 fixed part of the option name, and the address of a variable. The 219 variable, type `char *', is set to the variable part of the given 220 option if the fixed part matches. The actual option name is made 221 by appending `-m' to the specified name. */ 222 #define TARGET_OPTIONS \ 223 { { "reg-alloc=", &m68hc11_reg_alloc_order, \ 224 N_("Specify the register allocation order"), 0}, \ 225 { "soft-reg-count=", &m68hc11_soft_reg_count, \ 226 N_("Indicate the number of soft registers available"), 0}, \ 227 SUBTARGET_OPTIONS \ 228 } 229 230 /* These are meant to be redefined in the host dependent files */ 231 #define SUBTARGET_SWITCHES 232 #define SUBTARGET_OPTIONS 233 234 extern const char *m68hc11_regparm_string; 235 extern const char *m68hc11_reg_alloc_order; 236 extern const char *m68hc11_soft_reg_count; 237 238 #ifndef TARGET_M68HC12 239 # define TARGET_M68HC11 1 240 #endif 241 242 /* Print subsidiary information on the compiler version in use. */ 243 #define TARGET_VERSION fprintf (stderr, " (MC68HC11/MC68HC12/MC68HCS12)") 244 245 /* Sometimes certain combinations of command options do not make 246 sense on a particular target machine. You can define a macro 247 `OVERRIDE_OPTIONS' to take account of this. This macro, if 248 defined, is executed once just after all the command options have 249 been parsed. 250 251 Don't use this macro to turn on various extra optimizations for 252 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */ 253 254 #define OVERRIDE_OPTIONS m68hc11_override_options (); 255 256 257 /* Define cost parameters for a given processor variant. */ 258 struct processor_costs { 259 const int add; /* cost of an add instruction */ 260 const int logical; /* cost of a logical instruction */ 261 const int shift_var; 262 const int shiftQI_const[8]; 263 const int shiftHI_const[16]; 264 const int multQI; 265 const int multHI; 266 const int multSI; 267 const int divQI; 268 const int divHI; 269 const int divSI; 270 }; 271 272 /* Costs for the current processor. */ 273 extern const struct processor_costs *m68hc11_cost; 274 275 276 /* target machine storage layout */ 277 278 /* Define this if most significant byte of a word is the lowest numbered. */ 279 #define BYTES_BIG_ENDIAN 1 280 281 /* Define this if most significant bit is lowest numbered 282 in instructions that operate on numbered bit-fields. */ 283 #define BITS_BIG_ENDIAN 0 284 285 /* Define this if most significant word of a multiword number is numbered. */ 286 #define WORDS_BIG_ENDIAN 1 287 288 /* Width of a word, in units (bytes). */ 289 #define UNITS_PER_WORD 2 290 291 /* Definition of size_t. This is really an unsigned short as the 292 68hc11 only handles a 64K address space. */ 293 #define SIZE_TYPE "short unsigned int" 294 295 /* A C expression for a string describing the name of the data type 296 to use for the result of subtracting two pointers. The typedef 297 name `ptrdiff_t' is defined using the contents of the string. 298 The 68hc11 only has a 64K address space. */ 299 #define PTRDIFF_TYPE "short int" 300 301 /* Allocation boundary (bits) for storing pointers in memory. */ 302 #define POINTER_BOUNDARY 8 303 304 /* Normal alignment required for function parameters on the stack, in bits. 305 This can't be less than BITS_PER_WORD */ 306 #define PARM_BOUNDARY (BITS_PER_WORD) 307 308 /* Boundary (bits) on which stack pointer should be aligned. */ 309 #define STACK_BOUNDARY 8 310 311 /* Allocation boundary (bits) for the code of a function. */ 312 #define FUNCTION_BOUNDARY 8 313 314 #define BIGGEST_ALIGNMENT 8 315 316 /* Alignment of field after `int : 0' in a structure. */ 317 #define EMPTY_FIELD_BOUNDARY 8 318 319 /* Every structure's size must be a multiple of this. */ 320 #define STRUCTURE_SIZE_BOUNDARY 8 321 322 /* Define this if instructions will fail to work if given data not 323 on the nominal alignment. If instructions will merely go slower 324 in that case, do not define this macro. */ 325 #define STRICT_ALIGNMENT 0 326 327 /* An integer expression for the size in bits of the largest integer 328 machine mode that should actually be used. All integer machine modes of 329 this size or smaller can be used for structures and unions with the 330 appropriate sizes. */ 331 #define MAX_FIXED_MODE_SIZE 64 332 333 /* target machine storage layout */ 334 335 /* Size (bits) of the type "int" on target machine 336 (If undefined, default is BITS_PER_WORD). */ 337 #define INT_TYPE_SIZE (TARGET_SHORT ? 16 : 32) 338 339 /* Size (bits) of the type "short" on target machine */ 340 #define SHORT_TYPE_SIZE 16 341 342 /* Size (bits) of the type "long" on target machine */ 343 #define LONG_TYPE_SIZE 32 344 345 /* Size (bits) of the type "long long" on target machine */ 346 #define LONG_LONG_TYPE_SIZE 64 347 348 /* A C expression for the size in bits of the type `float' on the 349 target machine. If you don't define this, the default is one word. 350 Don't use default: a word is only 16. */ 351 #define FLOAT_TYPE_SIZE 32 352 353 /* A C expression for the size in bits of the type double on the target 354 machine. If you don't define this, the default is two words. 355 Be IEEE compliant. */ 356 #define DOUBLE_TYPE_SIZE 64 357 358 #define LONG_DOUBLE_TYPE_SIZE 64 359 360 /* Define this as 1 if `char' should by default be signed; else as 0. */ 361 #define DEFAULT_SIGNED_CHAR 0 362 363 /* Define these to avoid dependence on meaning of `int'. 364 Note that WCHAR_TYPE_SIZE is used in cexp.y, 365 where TARGET_SHORT is not available. */ 366 #define WCHAR_TYPE "short int" 367 #define WCHAR_TYPE_SIZE 16 368 369 370 /* Standard register usage. */ 371 372 #define HARD_REG_SIZE (UNITS_PER_WORD) 373 374 /* Assign names to real MC68HC11 registers. 375 A and B registers are not really used (A+B = D) 376 X register is first so that GCC allocates X+D for 32-bit integers and 377 the lowpart of that integer will be D. Having the lower part in D is 378 better for 32<->16bit conversions and for many arithmetic operations. */ 379 #define HARD_X_REGNUM 0 380 #define HARD_D_REGNUM 1 381 #define HARD_Y_REGNUM 2 382 #define HARD_SP_REGNUM 3 383 #define HARD_PC_REGNUM 4 384 #define HARD_A_REGNUM 5 385 #define HARD_B_REGNUM 6 386 #define HARD_CCR_REGNUM 7 387 388 /* The Z register does not really exist in the 68HC11. This a fake register 389 for GCC. It is treated exactly as an index register (X or Y). It is only 390 in the A_REGS class, which is the BASE_REG_CLASS for GCC. Defining this 391 register helps the reload pass of GCC. Otherwise, the reload often aborts 392 with register spill failures. 393 394 The Z register is replaced by either X or Y during the machine specific 395 reorg (m68hc11_reorg). It is saved in the SOFT_Z_REGNUM soft-register 396 when this is necessary. 397 398 It's possible to tell GCC not to use this register with -ffixed-z. */ 399 #define HARD_Z_REGNUM 8 400 401 /* The frame pointer is a soft-register. It's treated as such by GCC: 402 it is not and must not be part of the BASE_REG_CLASS. */ 403 #define DEFAULT_HARD_FP_REGNUM (9) 404 #define HARD_FP_REGNUM (9) 405 #define HARD_AP_REGNUM (HARD_FP_REGNUM) 406 407 /* Temporary soft-register used in some cases when an operand came 408 up into a bad register class (D, X, Y, SP) and gcc failed to 409 recognize this. This register is never allocated by GCC. */ 410 #define SOFT_TMP_REGNUM 10 411 412 /* The soft-register which is used to save the Z register 413 (see Z register replacement notes in m68hc11.c). */ 414 #define SOFT_Z_REGNUM 11 415 416 /* The soft-register which is used to save either X or Y. */ 417 #define SOFT_SAVED_XY_REGNUM 12 418 419 /* A fake clobber register for 68HC12 patterns. */ 420 #define FAKE_CLOBBER_REGNUM (13) 421 422 /* Define 32 soft-registers of 16-bit each. By default, 423 only 12 of them are enabled and can be used by GCC. The 424 -msoft-reg-count=<n> option allows to control the number of valid 425 soft-registers. GCC can put 32-bit values in them 426 by allocating consecutive registers. The first 3 soft-registers 427 are never allocated by GCC. They are used in case the insn template needs 428 a temporary register, or for the Z register replacement. */ 429 430 #define MAX_SOFT_REG_COUNT (32) 431 #define SOFT_REG_FIXED 0, 0, 0, 0, 0, 0, 0, 0, \ 432 0, 0, 0, 0, 1, 1, 1, 1, \ 433 1, 1, 1, 1, 1, 1, 1, 1, \ 434 1, 1, 1, 1, 1, 1, 1, 1 435 #define SOFT_REG_USED 0, 0, 0, 0, 0, 0, 0, 0, \ 436 0, 0, 0, 0, 1, 1, 1, 1, \ 437 1, 1, 1, 1, 1, 1, 1, 1, \ 438 1, 1, 1, 1, 1, 1, 1, 1 439 #define SOFT_REG_ORDER \ 440 SOFT_REG_FIRST, SOFT_REG_FIRST+1,SOFT_REG_FIRST+2,SOFT_REG_FIRST+3,\ 441 SOFT_REG_FIRST+4, SOFT_REG_FIRST+5,SOFT_REG_FIRST+6,SOFT_REG_FIRST+7,\ 442 SOFT_REG_FIRST+8, SOFT_REG_FIRST+9,SOFT_REG_FIRST+10,SOFT_REG_FIRST+11,\ 443 SOFT_REG_FIRST+12, SOFT_REG_FIRST+13,SOFT_REG_FIRST+14,SOFT_REG_FIRST+15,\ 444 SOFT_REG_FIRST+16, SOFT_REG_FIRST+17,SOFT_REG_FIRST+18,SOFT_REG_FIRST+19,\ 445 SOFT_REG_FIRST+20, SOFT_REG_FIRST+21,SOFT_REG_FIRST+22,SOFT_REG_FIRST+23,\ 446 SOFT_REG_FIRST+24, SOFT_REG_FIRST+25,SOFT_REG_FIRST+26,SOFT_REG_FIRST+27,\ 447 SOFT_REG_FIRST+28, SOFT_REG_FIRST+29,SOFT_REG_FIRST+30,SOFT_REG_FIRST+31 448 449 #define SOFT_REG_NAMES \ 450 "*_.d1", "*_.d2", "*_.d3", "*_.d4", \ 451 "*_.d5", "*_.d6", "*_.d7", "*_.d8", \ 452 "*_.d9", "*_.d10", "*_.d11", "*_.d12", \ 453 "*_.d13", "*_.d14", "*_.d15", "*_.d16", \ 454 "*_.d17", "*_.d18", "*_.d19", "*_.d20", \ 455 "*_.d21", "*_.d22", "*_.d23", "*_.d24", \ 456 "*_.d25", "*_.d26", "*_.d27", "*_.d28", \ 457 "*_.d29", "*_.d30", "*_.d31", "*_.d32" 458 459 /* First available soft-register for GCC. */ 460 #define SOFT_REG_FIRST (SOFT_SAVED_XY_REGNUM+2) 461 462 /* Last available soft-register for GCC. */ 463 #define SOFT_REG_LAST (SOFT_REG_FIRST+MAX_SOFT_REG_COUNT) 464 #define SOFT_FP_REGNUM (SOFT_REG_LAST) 465 #define SOFT_AP_REGNUM (SOFT_FP_REGNUM+1) 466 467 /* Number of actual hardware registers. The hardware registers are assigned 468 numbers for the compiler from 0 to just below FIRST_PSEUDO_REGISTER. 469 All registers that the compiler knows about must be given numbers, even 470 those that are not normally considered general registers. */ 471 #define FIRST_PSEUDO_REGISTER (SOFT_REG_LAST+2) 472 473 /* 1 for registers that have pervasive standard uses and are not available 474 for the register allocator. */ 475 #define FIXED_REGISTERS \ 476 {0, 0, 0, 1, 1, 1, 1, 1, 0, 1, 1, 1,1, 1, SOFT_REG_FIXED, 1, 1} 477 /* X, D, Y, SP,PC,A, B, CCR, Z, FP,ZTMP,ZR,XYR, FK, D1 - D32, SOFT-FP, AP */ 478 479 /* 1 for registers not available across function calls. For our pseudo 480 registers, all are available. */ 481 #define CALL_USED_REGISTERS \ 482 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,1, 1, SOFT_REG_USED, 1, 1} 483 /* X, D, Y, SP,PC,A, B, CCR, Z, FP, ZTMP,ZR,XYR, D1 - 32, SOFT-FP, AP */ 484 485 486 /* Define this macro to change register usage conditional on target flags. 487 488 The soft-registers are disabled or enabled according to the 489 -msoft-reg-count=<n> option. */ 490 491 492 #define CONDITIONAL_REGISTER_USAGE (m68hc11_conditional_register_usage ()) 493 494 /* List the order in which to allocate registers. Each register must be 495 listed once, even those in FIXED_REGISTERS. */ 496 #define REG_ALLOC_ORDER \ 497 { HARD_D_REGNUM, HARD_X_REGNUM, HARD_Y_REGNUM, \ 498 SOFT_REG_ORDER, HARD_Z_REGNUM, HARD_PC_REGNUM, HARD_A_REGNUM, \ 499 HARD_B_REGNUM, HARD_CCR_REGNUM, HARD_FP_REGNUM, SOFT_FP_REGNUM, \ 500 HARD_SP_REGNUM, SOFT_TMP_REGNUM, SOFT_Z_REGNUM, SOFT_SAVED_XY_REGNUM, \ 501 SOFT_AP_REGNUM, FAKE_CLOBBER_REGNUM } 502 503 /* A C expression for the number of consecutive hard registers, 504 starting at register number REGNO, required to hold a value of 505 mode MODE. */ 506 #define HARD_REGNO_NREGS(REGNO, MODE) \ 507 ((Q_REGNO_P (REGNO)) ? (GET_MODE_SIZE (MODE)) : \ 508 ((GET_MODE_SIZE (MODE) + HARD_REG_SIZE - 1) / HARD_REG_SIZE)) 509 510 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. 511 - 8 bit values are stored anywhere (except the SP register). 512 - 16 bit values can be stored in any register whose mode is 16 513 - 32 bit values can be stored in D, X registers or in a soft register 514 (except the last one because we need 2 soft registers) 515 - Values whose size is > 32 bit are not stored in real hard 516 registers. They may be stored in soft registers if there are 517 enough of them. */ 518 #define HARD_REGNO_MODE_OK(REGNO, MODE) \ 519 hard_regno_mode_ok (REGNO,MODE) 520 521 /* Value is 1 if it is a good idea to tie two pseudo registers when one has 522 mode MODE1 and one has mode MODE2. If HARD_REGNO_MODE_OK could produce 523 different values for MODE1 and MODE2, for any hard reg, then this must be 524 0 for correct output. 525 526 All modes are tieable except QImode. */ 527 #define MODES_TIEABLE_P(MODE1, MODE2) \ 528 (((MODE1) == (MODE2)) \ 529 || ((MODE1) != QImode && (MODE2) != QImode)) 530 531 532 /* Define the classes of registers for register constraints in the 533 machine description. Also define ranges of constants. 534 535 One of the classes must always be named ALL_REGS and include all hard regs. 536 If there is more than one class, another class must be named NO_REGS 537 and contain no registers. 538 539 The name GENERAL_REGS must be the name of a class (or an alias for 540 another name such as ALL_REGS). This is the class of registers 541 that is allowed by "g" or "r" in a register constraint. 542 Also, registers outside this class are allocated only when 543 instructions express preferences for them. 544 545 The classes must be numbered in nondecreasing order; that is, 546 a larger-numbered class must never be contained completely 547 in a smaller-numbered class. 548 549 For any two classes, it is very desirable that there be another 550 class that represents their union. */ 551 552 /* The M68hc11 has so fiew registers that it's not possible for GCC to 553 do any register allocation without breaking. We extend the processor 554 registers by having soft registers. These registers are treated as 555 hard registers by GCC but they are located in memory and accessed by page0 556 accesses (IND mode). */ 557 enum reg_class 558 { 559 NO_REGS, 560 D_REGS, /* 16-bit data register */ 561 X_REGS, /* 16-bit X register */ 562 Y_REGS, /* 16-bit Y register */ 563 SP_REGS, /* 16 bit stack pointer */ 564 DA_REGS, /* 8-bit A reg. */ 565 DB_REGS, /* 8-bit B reg. */ 566 Z_REGS, /* 16-bit fake Z register */ 567 D8_REGS, /* 8-bit A or B reg. */ 568 Q_REGS, /* 8-bit (byte (QI)) data (A, B or D) */ 569 D_OR_X_REGS, /* D or X register */ 570 D_OR_Y_REGS, /* D or Y register */ 571 D_OR_SP_REGS, /* D or SP register */ 572 X_OR_Y_REGS, /* IX or Y register */ 573 A_REGS, /* 16-bit address register (X, Y, Z) */ 574 X_OR_SP_REGS, /* X or SP register */ 575 Y_OR_SP_REGS, /* Y or SP register */ 576 X_OR_Y_OR_D_REGS, /* X, Y or D */ 577 A_OR_D_REGS, /* X, Y, Z or D */ 578 A_OR_SP_REGS, /* X, Y, Z or SP */ 579 H_REGS, /* 16-bit hard register (D, X, Y, Z, SP) */ 580 S_REGS, /* 16-bit soft register */ 581 D_OR_S_REGS, /* 16-bit soft register or D register */ 582 X_OR_S_REGS, /* 16-bit soft register or X register */ 583 Y_OR_S_REGS, /* 16-bit soft register or Y register */ 584 Z_OR_S_REGS, /* 16-bit soft register or Z register */ 585 SP_OR_S_REGS, /* 16-bit soft register or SP register */ 586 D_OR_X_OR_S_REGS, /* 16-bit soft register or D or X register */ 587 D_OR_Y_OR_S_REGS, /* 16-bit soft register or D or Y register */ 588 D_OR_SP_OR_S_REGS, /* 16-bit soft register or D or SP register */ 589 A_OR_S_REGS, /* 16-bit soft register or X, Y registers */ 590 D_OR_A_OR_S_REGS, /* 16-bit soft register or D, X, Y registers */ 591 TMP_REGS, /* 16 bit fake scratch register */ 592 D_OR_A_OR_TMP_REGS, /* General scratch register */ 593 G_REGS, /* 16-bit general register 594 (H_REGS + soft registers) */ 595 ALL_REGS, 596 LIM_REG_CLASSES 597 }; 598 599 /* alias GENERAL_REGS to G_REGS. */ 600 #define GENERAL_REGS G_REGS 601 602 #define N_REG_CLASSES (int) LIM_REG_CLASSES 603 604 /* Give names of register classes as strings for dump file. */ 605 #define REG_CLASS_NAMES \ 606 { "NO_REGS", \ 607 "D_REGS", \ 608 "X_REGS", \ 609 "Y_REGS", \ 610 "SP_REGS", \ 611 "DA_REGS", \ 612 "DB_REGS", \ 613 "D8_REGS", \ 614 "Z_REGS", \ 615 "Q_REGS", \ 616 "D_OR_X_REGS", \ 617 "D_OR_Y_REGS", \ 618 "D_OR_SP_REGS", \ 619 "X_OR_Y_REGS", \ 620 "A_REGS", \ 621 "X_OR_SP_REGS", \ 622 "Y_OR_SP_REGS", \ 623 "X_OR_Y_OR_D_REGS", \ 624 "A_OR_D_REGS", \ 625 "A_OR_SP_REGS", \ 626 "H_REGS", \ 627 "S_REGS", \ 628 "D_OR_S_REGS", \ 629 "X_OR_S_REGS", \ 630 "Y_OR_S_REGS", \ 631 "Z_OR_S_REGS", \ 632 "SP_OR_S_REGS", \ 633 "D_OR_X_OR_S_REGS", \ 634 "D_OR_Y_OR_S_REGS", \ 635 "D_OR_SP_OR_S_REGS", \ 636 "A_OR_S_REGS", \ 637 "D_OR_A_OR_S_REGS", \ 638 "TMP_REGS", \ 639 "D_OR_A_OR_TMP_REGS", \ 640 "G_REGS", \ 641 "ALL_REGS" } 642 643 /* An initializer containing the contents of the register classes, 644 as integers which are bit masks. The Nth integer specifies the 645 contents of class N. The way the integer MASK is interpreted is 646 that register R is in the class if `MASK & (1 << R)' is 1. */ 647 648 /*-------------------------------------------------------------- 649 X 0x00000001 650 D 0x00000002 651 Y 0x00000004 652 SP 0x00000008 653 PC 0x00000010 654 A 0x00000020 655 B 0x00000040 656 CCR 0x00000080 657 Z 0x00000100 658 FRAME 0x00000200 659 ZTMP 0x00000400 660 ZREG 0x00000800 661 XYREG 0x00001000 662 FAKE 0x00002000 663 Di 0xFFFFc000, 0x03FFF 664 SFRAME 0x00000000, 0x04000 665 AP 0x00000000, 0x08000 666 667 D_OR_X_REGS represents D+X. It is used for 32-bits numbers. 668 A_REGS represents a valid base register for indexing. It represents 669 X,Y and the Z register. 670 S_REGS represents the soft-registers. This includes the hard frame 671 and soft frame registers. 672 --------------------------------------------------------------*/ 673 674 #define REG_CLASS_CONTENTS \ 675 /* NO_REGS */ {{ 0x00000000, 0x00000000 }, \ 676 /* D_REGS */ { 0x00000002, 0x00000000 }, /* D */ \ 677 /* X_REGS */ { 0x00000001, 0x00000000 }, /* X */ \ 678 /* Y_REGS */ { 0x00000004, 0x00000000 }, /* Y */ \ 679 /* SP_REGS */ { 0x00000008, 0x00000000 }, /* SP */ \ 680 /* DA_REGS */ { 0x00000020, 0x00000000 }, /* A */ \ 681 /* DB_REGS */ { 0x00000040, 0x00000000 }, /* B */ \ 682 /* Z_REGS */ { 0x00000100, 0x00000000 }, /* Z */ \ 683 /* D8_REGS */ { 0x00000060, 0x00000000 }, /* A B */ \ 684 /* Q_REGS */ { 0x00000062, 0x00000000 }, /* A B D */ \ 685 /* D_OR_X_REGS */ { 0x00000003, 0x00000000 }, /* D X */ \ 686 /* D_OR_Y_REGS */ { 0x00000006, 0x00000000 }, /* D Y */ \ 687 /* D_OR_SP_REGS */ { 0x0000000A, 0x00000000 }, /* D SP */ \ 688 /* X_OR_Y_REGS */ { 0x00000005, 0x00000000 }, /* X Y */ \ 689 /* A_REGS */ { 0x00000105, 0x00000000 }, /* X Y Z */ \ 690 /* X_OR_SP_REGS */ { 0x00000009, 0x00000000 }, /* X SP */ \ 691 /* Y_OR_SP_REGS */ { 0x0000000C, 0x00000000 }, /* Y SP */ \ 692 /* X_OR_Y_OR_D_REGS */ { 0x00000007, 0x00000000 }, /* D X Y */ \ 693 /* A_OR_D_REGS */ { 0x00000107, 0x00000000 }, /* D X Y Z */ \ 694 /* A_OR_SP_REGS */ { 0x0000010D, 0x00000000 }, /* X Y SP */ \ 695 /* H_REGS */ { 0x0000010F, 0x00000000 }, /* D X Y SP */ \ 696 /* S_REGS */ { 0xFFFFDE00, 0x00007FFF }, /* _.D,..,FP,Z* */ \ 697 /* D_OR_S_REGS */ { 0xFFFFDE02, 0x00007FFF }, /* D _.D */ \ 698 /* X_OR_S_REGS */ { 0xFFFFDE01, 0x00007FFF }, /* X _.D */ \ 699 /* Y_OR_S_REGS */ { 0xFFFFDE04, 0x00007FFF }, /* Y _.D */ \ 700 /* Z_OR_S_REGS */ { 0xFFFFDF00, 0x00007FFF }, /* Z _.D */ \ 701 /* SP_OR_S_REGS */ { 0xFFFFDE08, 0x00007FFF }, /* SP _.D */ \ 702 /* D_OR_X_OR_S_REGS */ { 0xFFFFDE03, 0x00007FFF }, /* D X _.D */ \ 703 /* D_OR_Y_OR_S_REGS */ { 0xFFFFDE06, 0x00007FFF }, /* D Y _.D */ \ 704 /* D_OR_SP_OR_S_REGS */ { 0xFFFFDE0A, 0x00007FFF }, /* D SP _.D */ \ 705 /* A_OR_S_REGS */ { 0xFFFFDF05, 0x00007FFF }, /* X Y _.D */ \ 706 /* D_OR_A_OR_S_REGS */ { 0xFFFFDF07, 0x00007FFF }, /* D X Y _.D */ \ 707 /* TMP_REGS */ { 0x00002000, 0x00000000 }, /* FAKE */ \ 708 /* D_OR_A_OR_TMP_REGS*/ { 0x00002107, 0x00000000 }, /* D X Y Z Fake */ \ 709 /* G_REGS */ { 0xFFFFFF1F, 0x00007FFF }, /* ? _.D D X Y */ \ 710 /* ALL_REGS*/ { 0xFFFFFFFF, 0x00007FFF }} 711 712 713 /* set up a C expression whose value is a register class containing hard 714 register REGNO */ 715 #define Q_REGNO_P(REGNO) ((REGNO) == HARD_A_REGNUM \ 716 || (REGNO) == HARD_B_REGNUM) 717 #define Q_REG_P(X) (REG_P (X) && Q_REGNO_P (REGNO (X))) 718 719 #define D_REGNO_P(REGNO) ((REGNO) == HARD_D_REGNUM) 720 #define D_REG_P(X) (REG_P (X) && D_REGNO_P (REGNO (X))) 721 722 #define DB_REGNO_P(REGNO) ((REGNO) == HARD_B_REGNUM) 723 #define DB_REG_P(X) (REG_P (X) && DB_REGNO_P (REGNO (X))) 724 #define DA_REGNO_P(REGNO) ((REGNO) == HARD_A_REGNUM) 725 #define DA_REG_P(X) (REG_P (X) && DA_REGNO_P (REGNO (X))) 726 727 #define X_REGNO_P(REGNO) ((REGNO) == HARD_X_REGNUM) 728 #define X_REG_P(X) (REG_P (X) && X_REGNO_P (REGNO (X))) 729 730 #define Y_REGNO_P(REGNO) ((REGNO) == HARD_Y_REGNUM) 731 #define Y_REG_P(X) (REG_P (X) && Y_REGNO_P (REGNO (X))) 732 733 #define Z_REGNO_P(REGNO) ((REGNO) == HARD_Z_REGNUM) 734 #define Z_REG_P(X) (REG_P (X) && Z_REGNO_P (REGNO (X))) 735 736 #define SP_REGNO_P(REGNO) ((REGNO) == HARD_SP_REGNUM) 737 #define SP_REG_P(X) (REG_P (X) && SP_REGNO_P (REGNO (X))) 738 739 /* Address register. */ 740 #define A_REGNO_P(REGNO) ((REGNO) == HARD_X_REGNUM \ 741 || (REGNO) == HARD_Y_REGNUM \ 742 || (REGNO) == HARD_Z_REGNUM) 743 #define A_REG_P(X) (REG_P (X) && A_REGNO_P (REGNO (X))) 744 745 /* M68hc11 hard registers. */ 746 #define H_REGNO_P(REGNO) (D_REGNO_P (REGNO) || A_REGNO_P (REGNO) \ 747 || SP_REGNO_P (REGNO) || Q_REGNO_P (REGNO)) 748 #define H_REG_P(X) (REG_P (X) && H_REGNO_P (REGNO (X))) 749 750 #define FAKE_REGNO_P(REGNO) ((REGNO) == FAKE_CLOBBER_REGNUM) 751 #define FAKE_REG_P(X) (REG_P (X) && FAKE_REGNO_P (REGNO (X))) 752 753 /* Soft registers (or register emulation for gcc). The temporary register 754 used by insn template must be part of the S_REGS class so that it 755 matches the 'u' constraint. */ 756 #define S_REGNO_P(REGNO) ((REGNO) >= SOFT_TMP_REGNUM \ 757 && (REGNO) <= SOFT_REG_LAST \ 758 && (REGNO) != FAKE_CLOBBER_REGNUM) 759 #define S_REG_P(X) (REG_P (X) && S_REGNO_P (REGNO (X))) 760 761 #define Z_REGNO_P(REGNO) ((REGNO) == HARD_Z_REGNUM) 762 #define Z_REG_P(X) (REG_P (X) && Z_REGNO_P (REGNO (X))) 763 764 /* General register. */ 765 #define G_REGNO_P(REGNO) (H_REGNO_P (REGNO) || S_REGNO_P (REGNO) \ 766 || ((REGNO) == HARD_PC_REGNUM) \ 767 || ((REGNO) == HARD_FP_REGNUM) \ 768 || ((REGNO) == SOFT_FP_REGNUM) \ 769 || ((REGNO) == FAKE_CLOBBER_REGNUM) \ 770 || ((REGNO) == SOFT_AP_REGNUM)) 771 772 #define G_REG_P(X) (REG_P (X) && G_REGNO_P (REGNO (X))) 773 774 #define REGNO_REG_CLASS(REGNO) \ 775 (D_REGNO_P (REGNO) ? D_REGS : \ 776 (X_REGNO_P (REGNO) ? X_REGS : \ 777 (Y_REGNO_P (REGNO) ? Y_REGS : \ 778 (SP_REGNO_P (REGNO) ? SP_REGS : \ 779 (Z_REGNO_P (REGNO) ? Z_REGS : \ 780 (H_REGNO_P (REGNO) ? H_REGS : \ 781 (FAKE_REGNO_P (REGNO) ? TMP_REGS : \ 782 (S_REGNO_P (REGNO) ? S_REGS : \ 783 (DA_REGNO_P (REGNO) ? DA_REGS: \ 784 (DB_REGNO_P (REGNO) ? DB_REGS: \ 785 (G_REGNO_P (REGNO) ? G_REGS : ALL_REGS))))))))))) 786 787 788 /* Get reg_class from a letter in the machine description. */ 789 790 extern enum reg_class m68hc11_tmp_regs_class; 791 #define REG_CLASS_FROM_LETTER(C) \ 792 ((C) == 'a' ? DA_REGS : \ 793 (C) == 'A' ? A_REGS : \ 794 (C) == 'b' ? DB_REGS : \ 795 (C) == 'B' ? X_OR_Y_REGS : \ 796 (C) == 'd' ? D_REGS : \ 797 (C) == 'D' ? D_OR_X_REGS : \ 798 (C) == 'q' ? Q_REGS : \ 799 (C) == 'h' ? H_REGS : \ 800 (C) == 't' ? TMP_REGS : \ 801 (C) == 'u' ? S_REGS : \ 802 (C) == 'v' ? m68hc11_tmp_regs_class : \ 803 (C) == 'w' ? SP_REGS : \ 804 (C) == 'x' ? X_REGS : \ 805 (C) == 'y' ? Y_REGS : \ 806 (C) == 'z' ? Z_REGS : NO_REGS) 807 808 #define PREFERRED_RELOAD_CLASS(X,CLASS) preferred_reload_class(X,CLASS) 809 810 #define SMALL_REGISTER_CLASSES 1 811 812 /* A C expression that is nonzero if hard register number REGNO2 can be 813 considered for use as a rename register for REGNO1 */ 814 815 #define HARD_REGNO_RENAME_OK(REGNO1,REGNO2) \ 816 m68hc11_hard_regno_rename_ok ((REGNO1), (REGNO2)) 817 818 /* A C expression whose value is nonzero if pseudos that have been 819 assigned to registers of class CLASS would likely be spilled 820 because registers of CLASS are needed for spill registers. 821 822 The default value of this macro returns 1 if CLASS has exactly one 823 register and zero otherwise. On most machines, this default 824 should be used. Only define this macro to some other expression 825 if pseudo allocated by `local-alloc.c' end up in memory because 826 their hard registers were needed for spill registers. If this 827 macro returns nonzero for those classes, those pseudos will only 828 be allocated by `global.c', which knows how to reallocate the 829 pseudo to another register. If there would not be another 830 register available for reallocation, you should not change the 831 definition of this macro since the only effect of such a 832 definition would be to slow down register allocation. */ 833 834 #define CLASS_LIKELY_SPILLED_P(CLASS) \ 835 (((CLASS) == D_REGS) \ 836 || ((CLASS) == X_REGS) \ 837 || ((CLASS) == Y_REGS) \ 838 || ((CLASS) == A_REGS) \ 839 || ((CLASS) == SP_REGS) \ 840 || ((CLASS) == D_OR_X_REGS) \ 841 || ((CLASS) == D_OR_Y_REGS) \ 842 || ((CLASS) == X_OR_SP_REGS) \ 843 || ((CLASS) == Y_OR_SP_REGS) \ 844 || ((CLASS) == D_OR_SP_REGS)) 845 846 /* Return the maximum number of consecutive registers needed to represent 847 mode MODE in a register of class CLASS. */ 848 #define CLASS_MAX_NREGS(CLASS, MODE) \ 849 (((CLASS) == DA_REGS || (CLASS) == DB_REGS \ 850 || (CLASS) == D8_REGS || (CLASS) == Q_REGS) ? GET_MODE_SIZE (MODE) \ 851 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) 852 853 /* The letters I, J, K, L and M in a register constraint string 854 can be used to stand for particular ranges of immediate operands. 855 This macro defines what the ranges are. 856 C is the letter, and VALUE is a constant value. 857 Return 1 if VALUE is in the range specified by C. 858 859 `K' is for 0. 860 `L' is for range -65536 to 65536 861 `M' is for values whose 16-bit low part is 0 862 'N' is for +1 or -1. 863 'O' is for 16 (for rotate using swap). 864 'P' is for range -8 to 2 (used by addhi_sp) 865 866 'I', 'J' are not used. */ 867 868 #define CONST_OK_FOR_LETTER_P(VALUE, C) \ 869 ((C) == 'K' ? (VALUE) == 0 : \ 870 (C) == 'L' ? ((VALUE) >= -65536 && (VALUE) <= 65535) : \ 871 (C) == 'M' ? ((VALUE) & 0x0ffffL) == 0 : \ 872 (C) == 'N' ? ((VALUE) == 1 || (VALUE) == -1) : \ 873 (C) == 'I' ? ((VALUE) >= -2 && (VALUE) <= 2) : \ 874 (C) == 'O' ? (VALUE) == 16 : \ 875 (C) == 'P' ? ((VALUE) <= 2 && (VALUE) >= -8) : 0) 876 877 /* Similar, but for floating constants, and defining letters G and H. 878 879 `G' is for 0.0. */ 880 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \ 881 ((C) == 'G' ? (GET_MODE_CLASS (GET_MODE (VALUE)) == MODE_FLOAT \ 882 && VALUE == CONST0_RTX (GET_MODE (VALUE))) : 0) 883 884 /* 'U' represents certain kind of memory indexed operand for 68HC12. 885 and any memory operand for 68HC11. 886 'R' represents indexed addressing mode or access to page0 for 68HC11. 887 For 68HC12, it represents any memory operand. */ 888 #define EXTRA_CONSTRAINT(OP, C) \ 889 ((C) == 'U' ? m68hc11_small_indexed_indirect_p (OP, GET_MODE (OP)) \ 890 : (C) == 'Q' ? m68hc11_symbolic_p (OP, GET_MODE (OP)) \ 891 : (C) == 'R' ? m68hc11_indirect_p (OP, GET_MODE (OP)) \ 892 : (C) == 'S' ? (memory_operand (OP, GET_MODE (OP)) \ 893 && non_push_operand (OP, GET_MODE (OP))) : 0) 894 895 896 /* Stack layout; function entry, exit and calling. */ 897 898 /* Define this if pushing a word on the stack 899 makes the stack pointer a smaller address. */ 900 #define STACK_GROWS_DOWNWARD 901 902 /* Define this if the nominal address of the stack frame 903 is at the high-address end of the local variables; 904 that is, each additional local variable allocated 905 goes at a more negative offset in the frame. 906 907 Don't define for 68HC11, the frame pointer is the bottom 908 of local variables. */ 909 /* #define FRAME_GROWS_DOWNWARD */ 910 911 /* Define this if successive arguments to a function occupy decreasing 912 addresses in the stack. */ 913 /* #define ARGS_GROW_DOWNWARD */ 914 915 /* Offset within stack frame to start allocating local variables at. 916 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the 917 first local allocated. Otherwise, it is the offset to the BEGINNING 918 of the first local allocated. */ 919 #define STARTING_FRAME_OFFSET 0 920 921 /* Offset of first parameter from the argument pointer register value. */ 922 923 #define FIRST_PARM_OFFSET(FNDECL) 2 924 925 /* After the prologue, RA is at 0(AP) in the current frame. */ 926 #define RETURN_ADDR_RTX(COUNT, FRAME) \ 927 ((COUNT) == 0 \ 928 ? gen_rtx_MEM (Pmode, arg_pointer_rtx) \ 929 : 0) 930 931 /* Before the prologue, the top of the frame is at 2(sp). */ 932 #define INCOMING_FRAME_SP_OFFSET 2 933 934 /* Define this if functions should assume that stack space has been 935 allocated for arguments even when their values are passed in 936 registers. 937 938 The value of this macro is the size, in bytes, of the area reserved for 939 arguments passed in registers. 940 941 This space can either be allocated by the caller or be a part of the 942 machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE' 943 says which. */ 944 /* #define REG_PARM_STACK_SPACE(FNDECL) 2 */ 945 946 /* Define this macro if REG_PARM_STACK_SPACE is defined but stack 947 parameters don't skip the area specified by REG_PARM_STACK_SPACE. 948 Normally, when a parameter is not passed in registers, it is placed on 949 the stack beyond the REG_PARM_STACK_SPACE area. Defining this macro 950 suppresses this behavior and causes the parameter to be passed on the 951 stack in its natural location. */ 952 /* #define STACK_PARMS_IN_REG_PARM_AREA */ 953 954 /* Register to use for pushing function arguments. */ 955 #define STACK_POINTER_REGNUM HARD_SP_REGNUM 956 957 /* Base register for access to local variables of the function. */ 958 #define FRAME_POINTER_REGNUM SOFT_FP_REGNUM 959 960 #define HARD_FRAME_POINTER_REGNUM HARD_FP_REGNUM 961 962 /* Base register for access to arguments of the function. */ 963 #define ARG_POINTER_REGNUM SOFT_AP_REGNUM 964 965 /* Register in which static-chain is passed to a function. */ 966 #define STATIC_CHAIN_REGNUM SOFT_Z_REGNUM 967 968 969 /* Definitions for register eliminations. 970 971 This is an array of structures. Each structure initializes one pair 972 of eliminable registers. The "from" register number is given first, 973 followed by "to". Eliminations of the same "from" register are listed 974 in order of preference. 975 976 We have two registers that are eliminated on the 6811. The pseudo arg 977 pointer and pseudo frame pointer registers can always be eliminated; 978 they are replaced with either the stack or the real frame pointer. */ 979 980 #define ELIMINABLE_REGS \ 981 {{ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 982 {ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ 983 {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 984 {FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} 985 986 /* Value should be nonzero if functions must have frame pointers. 987 Zero means the frame pointer need not be set up (and parms may be 988 accessed via the stack pointer) in functions that seem suitable. 989 This is computed in `reload', in reload1.c. */ 990 #define FRAME_POINTER_REQUIRED 0 991 992 /* Given FROM and TO register numbers, say whether this elimination is allowed. 993 Frame pointer elimination is automatically handled. 994 995 All other eliminations are valid. */ 996 997 #define CAN_ELIMINATE(FROM, TO) \ 998 ((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM \ 999 ? ! frame_pointer_needed \ 1000 : 1) 1001 1002 1003 /* Define the offset between two registers, one to be eliminated, and the other 1004 its replacement, at the start of a routine. */ 1005 1006 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 1007 { OFFSET = m68hc11_initial_elimination_offset (FROM, TO); } 1008 1009 1010 /* Passing Function Arguments on the Stack. */ 1011 1012 /* When a prototype says `char' or `short', really pass an `int'. */ 1013 /* #define PROMOTE_PROTOTYPES */ 1014 1015 /* If we generate an insn to push BYTES bytes, this says how many the 1016 stack pointer really advances by. No rounding or alignment needed 1017 for MC6811. */ 1018 #define PUSH_ROUNDING(BYTES) (BYTES) 1019 1020 /* Value is 1 if returning from a function call automatically pops the 1021 arguments described by the number-of-args field in the call. FUNTYPE is 1022 the data type of the function (as a tree), or for a library call it is 1023 an identifier node for the subroutine name. 1024 1025 The standard MC6811 call, with arg count word, includes popping the 1026 args as part of the call template. */ 1027 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0 1028 1029 /* Nonzero if type TYPE should be returned in memory. 1030 Blocks and data types largers than 4 bytes cannot be returned 1031 in the register (D + X = 4). */ 1032 #define RETURN_IN_MEMORY(TYPE) \ 1033 ((TYPE_MODE (TYPE) == BLKmode) \ 1034 ? (int_size_in_bytes (TYPE) > 4) \ 1035 : (GET_MODE_SIZE (TYPE_MODE (TYPE)) > 4)) 1036 1037 1038 /* Passing Arguments in Registers. */ 1039 1040 /* Define a data type for recording info about an argument list 1041 during the scan of that argument list. This data type should 1042 hold all necessary information about the function itself 1043 and about the args processed so far, enough to enable macros 1044 such as FUNCTION_ARG to determine where the next arg should go. */ 1045 1046 typedef struct m68hc11_args 1047 { 1048 int words; 1049 int nregs; 1050 } CUMULATIVE_ARGS; 1051 1052 /* A C expression that indicates when an argument must be passed by reference. 1053 If nonzero for an argument, a copy of that argument is made in memory and a 1054 pointer to the argument is passed instead of the argument itself. 1055 The pointer is passed in whatever way is appropriate for passing a pointer 1056 to that type. 1057 1058 64-bit numbers are passed by reference. */ 1059 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \ 1060 m68hc11_function_arg_pass_by_reference (& (CUM), (MODE), (TYPE), (NAMED)) 1061 1062 1063 /* If defined, a C expression which determines whether, and in which direction, 1064 to pad out an argument with extra space. The value should be of type 1065 `enum direction': either `upward' to pad above the argument, 1066 `downward' to pad below, or `none' to inhibit padding. 1067 1068 Structures are stored left shifted in their argument slot. */ 1069 #define FUNCTION_ARG_PADDING(MODE, TYPE) \ 1070 m68hc11_function_arg_padding ((MODE), (TYPE)) 1071 1072 #undef PAD_VARARGS_DOWN 1073 #define PAD_VARARGS_DOWN \ 1074 (m68hc11_function_arg_padding (TYPE_MODE (type), type) == downward) 1075 1076 /* A C expression that indicates when it is the called function's 1077 responsibility to make a copy of arguments passed by invisible 1078 reference. Normally, the caller makes a copy and passes the 1079 address of the copy to the routine being called. When 1080 FUNCTION_ARG_CALLEE_COPIES is defined and is nonzero, the caller 1081 does not make a copy. Instead, it passes a pointer to the "live" 1082 value. The called function must not modify this value. If it can 1083 be determined that the value won't be modified, it need not make a 1084 copy; otherwise a copy must be made. */ 1085 #define FUNCTION_ARG_CALLEE_COPIES(CUM, MODE, TYPE, NAMED) \ 1086 ((NAMED) && FUNCTION_ARG_PASS_BY_REFERENCE (CUM, MODE, TYPE, NAMED)) 1087 1088 /* Initialize a variable CUM of type CUMULATIVE_ARGS for a call to a 1089 function whose data type is FNTYPE. For a library call, FNTYPE is 0. */ 1090 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \ 1091 (m68hc11_init_cumulative_args (&CUM, FNTYPE, LIBNAME)) 1092 1093 /* Update the data in CUM to advance over an argument of mode MODE and data 1094 type TYPE. (TYPE is null for libcalls where that information may not be 1095 available.) */ 1096 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ 1097 (m68hc11_function_arg_advance (&CUM, MODE, TYPE, NAMED)) 1098 1099 /* Define where to put the arguments to a function. 1100 Value is zero to push the argument on the stack, 1101 or a hard register in which to store the argument. 1102 1103 MODE is the argument's machine mode. 1104 TYPE is the data type of the argument (as a tree). 1105 This is null for libcalls where that information may 1106 not be available. 1107 CUM is a variable of type CUMULATIVE_ARGS which gives info about 1108 the preceding args and about the function being called. 1109 NAMED is nonzero if this argument is a named parameter 1110 (otherwise it is an extra parameter matching an ellipsis). */ 1111 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ 1112 (m68hc11_function_arg (&CUM, MODE, TYPE, NAMED)) 1113 1114 /* Define the profitability of saving registers around calls. 1115 1116 Disable this because the saving instructions generated by 1117 caller-save need a reload and the way it is implemented, 1118 it forbids all spill registers at that point. Enabling 1119 caller saving results in spill failure. */ 1120 #define CALLER_SAVE_PROFITABLE(REFS,CALLS) 0 1121 1122 /* For an arg passed partly in registers and partly in memory, 1123 this is the number of registers used. 1124 For args passed entirely in registers or entirely in memory, zero. 1125 1126 Passing an arg partly in register and memory does not work at all. 1127 Don't do that. */ 1128 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) (0) 1129 1130 /* 1 if N is a possible register number for function argument passing. 1131 D is for 16-bit values, X is for 32-bit (X+D). */ 1132 #define FUNCTION_ARG_REGNO_P(N) \ 1133 (((N) == HARD_D_REGNUM) || ((N) == HARD_X_REGNUM)) 1134 1135 /* All return values are in the D or X+D registers: 1136 - 8 and 16-bit values are returned in D. 1137 BLKmode are passed in D as pointer. 1138 - 32-bit values are returned in X + D. 1139 The high part is passed in X and the low part in D. 1140 For GCC, the register number must be HARD_X_REGNUM. */ 1141 #define FUNCTION_VALUE(VALTYPE, FUNC) \ 1142 gen_rtx (REG, TYPE_MODE (VALTYPE), \ 1143 ((TYPE_MODE (VALTYPE) == BLKmode \ 1144 || GET_MODE_SIZE (TYPE_MODE (VALTYPE)) <= 2) \ 1145 ? HARD_D_REGNUM : HARD_X_REGNUM)) 1146 1147 #define LIBCALL_VALUE(MODE) \ 1148 gen_rtx (REG, MODE, \ 1149 (((MODE) == BLKmode || GET_MODE_SIZE (MODE) <= 2) \ 1150 ? HARD_D_REGNUM : HARD_X_REGNUM)) 1151 1152 /* 1 if N is a possible register number for a function value. */ 1153 #define FUNCTION_VALUE_REGNO_P(N) \ 1154 ((N) == HARD_D_REGNUM || (N) == HARD_X_REGNUM) 1155 1156 /* Register in which address to store a structure value is passed to a 1157 function. */ 1158 #define STRUCT_VALUE_REGNUM HARD_D_REGNUM 1159 1160 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, 1161 the stack pointer does not matter. The value is tested only in functions 1162 that have frame pointers. No definition is equivalent to always zero. */ 1163 #define EXIT_IGNORE_STACK 0 1164 1165 1166 /* Generating Code for Profiling. */ 1167 1168 /* Output assembler code to FILE to increment profiler label # LABELNO 1169 for profiling a function entry. */ 1170 #define FUNCTION_PROFILER(FILE, LABELNO) \ 1171 fprintf (FILE, "\tldy\t.LP%d\n\tjsr mcount\n", (LABELNO)) 1172 /* Length in units of the trampoline for entering a nested function. */ 1173 #define TRAMPOLINE_SIZE (TARGET_M6811 ? 11 : 9) 1174 1175 /* A C statement to initialize the variable parts of a trampoline. 1176 ADDR is an RTX for the address of the trampoline; FNADDR is an 1177 RTX for the address of the nested function; STATIC_CHAIN is an 1178 RTX for the static chain value that should be passed to the 1179 function when it is called. */ 1180 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \ 1181 m68hc11_initialize_trampoline ((TRAMP), (FNADDR), (CXT)) 1182 1183 1184 /* Addressing modes, and classification of registers for them. */ 1185 1186 /* The 68HC12 has all the post/pre increment/decrement modes. */ 1187 #define HAVE_POST_INCREMENT (TARGET_M6812 && TARGET_AUTO_INC_DEC) 1188 #define HAVE_PRE_INCREMENT (TARGET_M6812 && TARGET_AUTO_INC_DEC) 1189 #define HAVE_POST_DECREMENT (TARGET_M6812 && TARGET_AUTO_INC_DEC) 1190 #define HAVE_PRE_DECREMENT (TARGET_M6812 && TARGET_AUTO_INC_DEC) 1191 1192 /* The class value for base registers. This depends on the target: 1193 A_REGS for 68HC11 and A_OR_SP_REGS for 68HC12. The class value 1194 is stored at init time. */ 1195 extern enum reg_class m68hc11_base_reg_class; 1196 #define BASE_REG_CLASS m68hc11_base_reg_class 1197 1198 /* The class value for index registers. This is NO_REGS for 68HC11. */ 1199 1200 extern enum reg_class m68hc11_index_reg_class; 1201 #define INDEX_REG_CLASS m68hc11_index_reg_class 1202 1203 /* These assume that REGNO is a hard or pseudo reg number. They give nonzero 1204 only if REGNO is a hard reg of the suitable class or a pseudo reg currently 1205 allocated to a suitable hard reg. Since they use reg_renumber, they are 1206 safe only once reg_renumber has been allocated, which happens in 1207 local-alloc.c. */ 1208 1209 1210 /* Internal macro, return 1 if REGNO is a valid base register. */ 1211 #define REG_VALID_P(REGNO) (1) /* ? */ 1212 1213 extern unsigned char m68hc11_reg_valid_for_base[FIRST_PSEUDO_REGISTER]; 1214 #define REG_VALID_FOR_BASE_P(REGNO) \ 1215 (REG_VALID_P (REGNO) && (REGNO) < FIRST_PSEUDO_REGISTER \ 1216 && m68hc11_reg_valid_for_base[REGNO]) 1217 1218 /* Internal macro, return 1 if REGNO is a valid index register. */ 1219 extern unsigned char m68hc11_reg_valid_for_index[FIRST_PSEUDO_REGISTER]; 1220 #define REG_VALID_FOR_INDEX_P(REGNO) \ 1221 (REG_VALID_P (REGNO) >= 0 && (REGNO) < FIRST_PSEUDO_REGISTER \ 1222 && m68hc11_reg_valid_for_index[REGNO]) 1223 1224 /* Internal macro, the nonstrict definition for REGNO_OK_FOR_BASE_P. */ 1225 #define REGNO_OK_FOR_BASE_NONSTRICT_P(REGNO) \ 1226 ((REGNO) >= FIRST_PSEUDO_REGISTER \ 1227 || REG_VALID_FOR_BASE_P (REGNO) \ 1228 || (REGNO) == FRAME_POINTER_REGNUM \ 1229 || (REGNO) == HARD_FRAME_POINTER_REGNUM \ 1230 || (REGNO) == ARG_POINTER_REGNUM \ 1231 || (reg_renumber && REG_VALID_FOR_BASE_P (reg_renumber[REGNO]))) 1232 1233 /* Internal macro, the nonstrict definition for REGNO_OK_FOR_INDEX_P. */ 1234 #define REGNO_OK_FOR_INDEX_NONSTRICT_P(REGNO) \ 1235 (TARGET_M6812 \ 1236 && ((REGNO) >= FIRST_PSEUDO_REGISTER \ 1237 || REG_VALID_FOR_INDEX_P (REGNO) \ 1238 || (reg_renumber && REG_VALID_FOR_INDEX_P (reg_renumber[REGNO])))) 1239 1240 /* Internal macro, the strict definition for REGNO_OK_FOR_BASE_P. */ 1241 #define REGNO_OK_FOR_BASE_STRICT_P(REGNO) \ 1242 ((REGNO) < FIRST_PSEUDO_REGISTER ? REG_VALID_FOR_BASE_P (REGNO) \ 1243 : (reg_renumber && REG_VALID_FOR_BASE_P (reg_renumber[REGNO]))) 1244 1245 /* Internal macro, the strict definition for REGNO_OK_FOR_INDEX_P. */ 1246 #define REGNO_OK_FOR_INDEX_STRICT_P(REGNO) \ 1247 (TARGET_M6812 \ 1248 && ((REGNO) < FIRST_PSEUDO_REGISTER ? REG_VALID_FOR_INDEX_P (REGNO) \ 1249 : (reg_renumber && REG_VALID_FOR_INDEX_P (reg_renumber[REGNO])))) 1250 1251 #define REGNO_OK_FOR_BASE_P2(REGNO,STRICT) \ 1252 ((STRICT) ? (REGNO_OK_FOR_BASE_STRICT_P (REGNO)) \ 1253 : (REGNO_OK_FOR_BASE_NONSTRICT_P (REGNO))) 1254 1255 #define REGNO_OK_FOR_INDEX_P2(REGNO,STRICT) \ 1256 ((STRICT) ? (REGNO_OK_FOR_INDEX_STRICT_P (REGNO)) \ 1257 : (REGNO_OK_FOR_INDEX_NONSTRICT_P (REGNO))) 1258 1259 #define REGNO_OK_FOR_BASE_P(REGNO) REGNO_OK_FOR_BASE_STRICT_P (REGNO) 1260 #define REGNO_OK_FOR_INDEX_P(REGNO) REGNO_OK_FOR_INDEX_STRICT_P (REGNO) 1261 1262 #define REG_OK_FOR_BASE_STRICT_P(X) REGNO_OK_FOR_BASE_STRICT_P (REGNO (X)) 1263 #define REG_OK_FOR_BASE_NONSTRICT_P(X) REGNO_OK_FOR_BASE_NONSTRICT_P (REGNO (X)) 1264 #define REG_OK_FOR_INDEX_STRICT_P(X) REGNO_OK_FOR_INDEX_STRICT_P (REGNO (X)) 1265 #define REG_OK_FOR_INDEX_NONSTRICT_P(X) REGNO_OK_FOR_INDEX_NONSTRICT_P (REGNO (X)) 1266 1267 /* see PUSH_POP_ADDRESS_P() below for an explanation of this. */ 1268 #define IS_STACK_PUSH(operand) \ 1269 ((GET_CODE (operand) == MEM) \ 1270 && (GET_CODE (XEXP (operand, 0)) == PRE_DEC) \ 1271 && (SP_REG_P (XEXP (XEXP (operand, 0), 0)))) 1272 1273 #define IS_STACK_POP(operand) \ 1274 ((GET_CODE (operand) == MEM) \ 1275 && (GET_CODE (XEXP (operand, 0)) == POST_INC) \ 1276 && (SP_REG_P (XEXP (XEXP (operand, 0), 0)))) 1277 1278 /* 1 if X is an rtx for a constant that is a valid address. */ 1279 #define CONSTANT_ADDRESS_P(X) (CONSTANT_P (X)) 1280 1281 /* Maximum number of registers that can appear in a valid memory address */ 1282 #define MAX_REGS_PER_ADDRESS 2 1283 1284 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression that is a 1285 valid memory address for an instruction. The MODE argument is the 1286 machine mode for the MEM expression that wants to use this address. */ 1287 1288 /*-------------------------------------------------------------- 1289 Valid addresses are either direct or indirect (MEM) versions 1290 of the following forms: 1291 constant N 1292 register ,X 1293 indexed N,X 1294 --------------------------------------------------------------*/ 1295 1296 /* The range of index that is allowed by indirect addressing. */ 1297 1298 #define VALID_MIN_OFFSET m68hc11_min_offset 1299 #define VALID_MAX_OFFSET m68hc11_max_offset 1300 1301 /* The offset values which are allowed by the n,x and n,y addressing modes. 1302 Take into account the size of the mode because we may have to add 1303 a mode offset to access the lowest part of the data. 1304 (For example, for an SImode, the last valid offset is 252.) */ 1305 #define VALID_CONSTANT_OFFSET_P(X,MODE) \ 1306 (((GET_CODE (X) == CONST_INT) && \ 1307 ((INTVAL (X) >= VALID_MIN_OFFSET) \ 1308 && ((INTVAL (X) <= VALID_MAX_OFFSET \ 1309 - (HOST_WIDE_INT) (GET_MODE_SIZE (MODE) + 1))))) \ 1310 || (TARGET_M6812 \ 1311 && ((GET_CODE (X) == SYMBOL_REF) \ 1312 || GET_CODE (X) == LABEL_REF \ 1313 || GET_CODE (X) == CONST))) 1314 1315 /* This is included to allow stack push/pop operations. Special hacks in the 1316 md and m6811.c files exist to support this. */ 1317 #define PUSH_POP_ADDRESS_P(X) \ 1318 (((GET_CODE (X) == PRE_DEC) || (GET_CODE (X) == POST_INC)) \ 1319 && SP_REG_P (XEXP (X, 0))) 1320 1321 /* Go to ADDR if X is a valid address. */ 1322 #ifndef REG_OK_STRICT 1323 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ 1324 { \ 1325 if (m68hc11_go_if_legitimate_address ((X), (MODE), 0)) goto ADDR; \ 1326 } 1327 #else 1328 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ 1329 { \ 1330 if (m68hc11_go_if_legitimate_address ((X), (MODE), 1)) goto ADDR; \ 1331 } 1332 #endif 1333 1334 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx and check its 1335 validity for a certain class. We have two alternate definitions for each 1336 of them. The usual definition accepts all pseudo regs; the other rejects 1337 them unless they have been allocated suitable hard regs. The symbol 1338 REG_OK_STRICT causes the latter definition to be used. 1339 1340 Most source files want to accept pseudo regs in the hope that they will 1341 get allocated to the class that the insn wants them to be in. Source files 1342 for reload pass need to be strict. After reload, it makes no difference, 1343 since pseudo regs have been eliminated by then. */ 1344 1345 #ifndef REG_OK_STRICT 1346 /* Nonzero if X is a hard reg that can be used as a base reg. */ 1347 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_NONSTRICT_P(X) 1348 1349 /* Nonzero if X is a hard reg that can be used as an index. */ 1350 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_NONSTRICT_P(X) 1351 #else 1352 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_STRICT_P(X) 1353 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_STRICT_P(X) 1354 #endif 1355 1356 1357 /* Try machine-dependent ways of modifying an illegitimate address 1358 to be legitimate. If we find one, return the new, valid address. 1359 This macro is used in only one place: `memory_address' in explow.c. 1360 1361 OLDX is the address as it was before break_out_memory_refs was called. 1362 In some cases it is useful to look at this to decide what needs to be done. 1363 1364 MODE and WIN are passed so that this macro can use 1365 GO_IF_LEGITIMATE_ADDRESS. 1366 1367 It is always safe for this macro to do nothing. 1368 It exists to recognize opportunities to optimize the output. */ 1369 1370 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \ 1371 { rtx operand = (X); \ 1372 if (m68hc11_legitimize_address (&operand, (OLDX), (MODE))) \ 1373 { \ 1374 (X) = operand; \ 1375 GO_IF_LEGITIMATE_ADDRESS (MODE,X,WIN); \ 1376 } \ 1377 } 1378 1379 /* Go to LABEL if ADDR (a legitimate address expression) 1380 has an effect that depends on the machine mode it is used for. */ 1381 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \ 1382 { \ 1383 if (GET_CODE (ADDR) == PRE_DEC || GET_CODE (ADDR) == POST_DEC \ 1384 || GET_CODE (ADDR) == PRE_INC || GET_CODE (ADDR) == POST_INC) \ 1385 goto LABEL; \ 1386 } 1387 1388 /* Nonzero if the constant value X is a legitimate general operand. 1389 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */ 1390 1391 #define LEGITIMATE_CONSTANT_P(X) 1 1392 1393 1394 /* Tell final.c how to eliminate redundant test instructions. */ 1395 1396 #define NOTICE_UPDATE_CC(EXP, INSN) \ 1397 m68hc11_notice_update_cc ((EXP), (INSN)) 1398 1399 /* Move costs between classes of registers */ 1400 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \ 1401 (m68hc11_register_move_cost (MODE, CLASS1, CLASS2)) 1402 1403 /* Move cost between register and memory. 1404 - Move to a 16-bit register is reasonable, 1405 - Move to a soft register can be expensive. */ 1406 #define MEMORY_MOVE_COST(MODE,CLASS,IN) \ 1407 m68hc11_memory_move_cost ((MODE),(CLASS),(IN)) 1408 1409 /* A C expression for the cost of a branch instruction. A value of 1 1410 is the default; other values are interpreted relative to that. 1411 1412 Pretend branches are cheap because GCC generates sub-optimal code 1413 for the default value. */ 1414 #define BRANCH_COST 0 1415 1416 /* Nonzero if access to memory by bytes is slow and undesirable. */ 1417 #define SLOW_BYTE_ACCESS 0 1418 1419 /* It is as good to call a constant function address as to call an address 1420 kept in a register. */ 1421 #define NO_FUNCTION_CSE 1422 1423 /* Try a machine-dependent way of reloading an illegitimate address 1424 operand. If we find one, push the reload and jump to WIN. This 1425 macro is used in only one place: `find_reloads_address' in reload.c. 1426 1427 For M68HC11, we handle large displacements of a base register 1428 by splitting the addend across an addhi3 insn. 1429 1430 For M68HC12, the 64K offset range is available. 1431 */ 1432 1433 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \ 1434 do { \ 1435 /* We must recognize output that we have already generated ourselves. */ \ 1436 if (GET_CODE (X) == PLUS \ 1437 && GET_CODE (XEXP (X, 0)) == PLUS \ 1438 && GET_CODE (XEXP (XEXP (X, 0), 0)) == REG \ 1439 && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT \ 1440 && GET_CODE (XEXP (X, 1)) == CONST_INT) \ 1441 { \ 1442 push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL, \ 1443 BASE_REG_CLASS, GET_MODE (X), VOIDmode, 0, 0, \ 1444 OPNUM, TYPE); \ 1445 goto WIN; \ 1446 } \ 1447 if (GET_CODE (X) == PLUS \ 1448 && GET_CODE (XEXP (X, 0)) == REG \ 1449 && GET_CODE (XEXP (X, 1)) == CONST_INT \ 1450 && !VALID_CONSTANT_OFFSET_P (XEXP (X, 1), MODE)) \ 1451 { \ 1452 HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \ 1453 HOST_WIDE_INT low, high; \ 1454 high = val & (~0x0FF); \ 1455 low = val & 0x00FF; \ 1456 if (low >= 256-15) { high += 16; low -= 16; } \ 1457 /* Reload the high part into a base reg; leave the low part \ 1458 in the mem directly. */ \ 1459 \ 1460 X = gen_rtx_PLUS (Pmode, \ 1461 gen_rtx_PLUS (Pmode, XEXP (X, 0), \ 1462 GEN_INT (high)), \ 1463 GEN_INT (low)); \ 1464 \ 1465 push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL, \ 1466 BASE_REG_CLASS, GET_MODE (X), VOIDmode, 0, 0, \ 1467 OPNUM, TYPE); \ 1468 goto WIN; \ 1469 } \ 1470 } while (0) 1471 1472 1473 /* Defining the Output Assembler Language. */ 1474 1475 /* A default list of other sections which we might be "in" at any given 1476 time. For targets that use additional sections (e.g. .tdesc) you 1477 should override this definition in the target-specific file which 1478 includes this file. */ 1479 1480 /* Output before read-only data. */ 1481 #define TEXT_SECTION_ASM_OP ("\t.sect\t.text") 1482 1483 /* Output before writable data. */ 1484 #define DATA_SECTION_ASM_OP ("\t.sect\t.data") 1485 1486 /* Output before uninitialized data. */ 1487 #define BSS_SECTION_ASM_OP ("\t.sect\t.bss") 1488 1489 /* Define the pseudo-ops used to switch to the .ctors and .dtors sections. 1490 1491 Same as config/elfos.h but don't mark these section SHF_WRITE since 1492 there is no shared library problem. */ 1493 #undef CTORS_SECTION_ASM_OP 1494 #define CTORS_SECTION_ASM_OP "\t.section\t.ctors,\"a\"" 1495 1496 #undef DTORS_SECTION_ASM_OP 1497 #define DTORS_SECTION_ASM_OP "\t.section\t.dtors,\"a\"" 1498 1499 #define TARGET_ASM_CONSTRUCTOR m68hc11_asm_out_constructor 1500 #define TARGET_ASM_DESTRUCTOR m68hc11_asm_out_destructor 1501 1502 /* Comment character */ 1503 #define ASM_COMMENT_START ";" 1504 1505 /* Output to assembler file text saying following lines 1506 may contain character constants, extra white space, comments, etc. */ 1507 #define ASM_APP_ON "; Begin inline assembler code\n#APP\n" 1508 1509 /* Output to assembler file text saying following lines 1510 no longer contain unusual constructs. */ 1511 #define ASM_APP_OFF "; End of inline assembler code\n#NO_APP\n" 1512 1513 /* Write the extra assembler code needed to declare a function properly. 1514 Some svr4 assemblers need to also have something extra said about the 1515 function's return value. We allow for that here. 1516 1517 For 68HC12 we mark functions that return with 'rtc'. The linker 1518 will ensure that a 'call' is really made (instead of 'jsr'). 1519 The debugger needs this information to correctly compute the stack frame. 1520 1521 For 68HC11/68HC12 we also mark interrupt handlers for gdb to 1522 compute the correct stack frame. */ 1523 1524 #undef ASM_DECLARE_FUNCTION_NAME 1525 #define ASM_DECLARE_FUNCTION_NAME(FILE, NAME, DECL) \ 1526 do \ 1527 { \ 1528 fprintf (FILE, "%s", TYPE_ASM_OP); \ 1529 assemble_name (FILE, NAME); \ 1530 putc (',', FILE); \ 1531 fprintf (FILE, TYPE_OPERAND_FMT, "function"); \ 1532 putc ('\n', FILE); \ 1533 \ 1534 if (current_function_far) \ 1535 { \ 1536 fprintf (FILE, "\t.far\t"); \ 1537 assemble_name (FILE, NAME); \ 1538 putc ('\n', FILE); \ 1539 } \ 1540 else if (current_function_interrupt \ 1541 || current_function_trap) \ 1542 { \ 1543 fprintf (FILE, "\t.interrupt\t"); \ 1544 assemble_name (FILE, NAME); \ 1545 putc ('\n', FILE); \ 1546 } \ 1547 ASM_DECLARE_RESULT (FILE, DECL_RESULT (DECL)); \ 1548 ASM_OUTPUT_LABEL(FILE, NAME); \ 1549 } \ 1550 while (0) 1551 1552 /* Output #ident as a .ident. */ 1553 1554 /* output external reference */ 1555 #define ASM_OUTPUT_EXTERNAL(FILE,DECL,NAME) \ 1556 {fputs ("\t; extern\t", FILE); \ 1557 assemble_name (FILE, NAME); \ 1558 fputs ("\n", FILE);} 1559 1560 /* How to refer to registers in assembler output. This sequence is indexed 1561 by compiler's hard-register-number (see above). */ 1562 #define REGISTER_NAMES \ 1563 { "x", "d", "y", "sp", "pc", "a", "b", "ccr", "z", \ 1564 "*_.frame", "*_.tmp", "*_.z", "*_.xy", "*fake clobber", \ 1565 SOFT_REG_NAMES, "*sframe", "*ap"} 1566 1567 /* Print an instruction operand X on file FILE. CODE is the code from the 1568 %-spec for printing this operand. If `%z3' was used to print operand 1569 3, then CODE is 'z'. */ 1570 1571 #define PRINT_OPERAND(FILE, X, CODE) \ 1572 print_operand (FILE, X, CODE) 1573 1574 /* Print a memory operand whose address is X, on file FILE. */ 1575 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \ 1576 print_operand_address (FILE, ADDR) 1577 1578 /* This is how to output an insn to push/pop a register on the stack. 1579 It need not be very fast code. 1580 1581 Don't define because we don't know how to handle that with 1582 the STATIC_CHAIN_REGNUM (soft register). Saving the static 1583 chain must be made inside FUNCTION_PROFILER. */ 1584 1585 #undef ASM_OUTPUT_REG_PUSH 1586 #undef ASM_OUTPUT_REG_POP 1587 1588 /* This is how to output an element of a case-vector that is relative. */ 1589 1590 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ 1591 fprintf (FILE, "\t%s\tL%d-L%d\n", integer_asm_op (2, TRUE), VALUE, REL) 1592 1593 /* This is how to output an element of a case-vector that is absolute. */ 1594 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ 1595 fprintf (FILE, "\t%s\t.L%d\n", integer_asm_op (2, TRUE), VALUE) 1596 1597 /* This is how to output an assembler line that says to advance the 1598 location counter to a multiple of 2**LOG bytes. */ 1599 #define ASM_OUTPUT_ALIGN(FILE,LOG) \ 1600 do { \ 1601 if ((LOG) > 1) \ 1602 fprintf ((FILE), "%s\n", ALIGN_ASM_OP); \ 1603 } while (0) 1604 1605 1606 /* Assembler Commands for Exception Regions. */ 1607 1608 /* Default values provided by GCC should be ok. Assuming that DWARF-2 1609 frame unwind info is ok for this platform. */ 1610 1611 #undef PREFERRED_DEBUGGING_TYPE 1612 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG 1613 1614 /* For the support of memory banks we need addresses that indicate 1615 the page number. */ 1616 #define DWARF2_ADDR_SIZE 4 1617 1618 /* SCz 2003-07-08: Don't use as dwarf2 .file/.loc directives because 1619 the linker is doing relaxation and it does not adjust the debug_line 1620 sections when it shrinks the code. This results in invalid addresses 1621 when debugging. This does not bless too much the HC11/HC12 as most 1622 applications are embedded and small, hence a reasonable debug info. 1623 This problem is known for binutils 2.13, 2.14 and mainline. */ 1624 #undef HAVE_AS_DWARF2_DEBUG_LINE 1625 1626 /* The prefix for local labels. You should be able to define this as 1627 an empty string, or any arbitrary string (such as ".", ".L%", etc) 1628 without having to make any other changes to account for the specific 1629 definition. Note it is a string literal, not interpreted by printf 1630 and friends. */ 1631 #define LOCAL_LABEL_PREFIX "." 1632 1633 /* The prefix for immediate operands. */ 1634 #define IMMEDIATE_PREFIX "#" 1635 #define GLOBAL_ASM_OP "\t.globl\t" 1636 1637 1638 /* Miscellaneous Parameters. */ 1639 1640 /* Define the codes that are matched by predicates in m68hc11.c. */ 1641 #define PREDICATE_CODES \ 1642 {"stack_register_operand", {SUBREG, REG}}, \ 1643 {"d_register_operand", {SUBREG, REG}}, \ 1644 {"hard_addr_reg_operand", {SUBREG, REG}}, \ 1645 {"hard_reg_operand", {SUBREG, REG}}, \ 1646 {"m68hc11_logical_operator", {AND, IOR, XOR}}, \ 1647 {"m68hc11_arith_operator", {AND, IOR, XOR, PLUS, MINUS, \ 1648 ASHIFT, ASHIFTRT, LSHIFTRT, \ 1649 ROTATE, ROTATERT }}, \ 1650 {"m68hc11_non_shift_operator", {AND, IOR, XOR, PLUS, MINUS}}, \ 1651 {"m68hc11_unary_operator", {NEG, NOT, SIGN_EXTEND, ZERO_EXTEND}}, \ 1652 {"m68hc11_shift_operator", {ASHIFT, ASHIFTRT, LSHIFTRT, ROTATE, ROTATERT}},\ 1653 {"m68hc11_eq_compare_operator", {EQ, NE}}, \ 1654 {"non_push_operand", {SUBREG, REG, MEM}}, \ 1655 {"splitable_operand", {SUBREG, REG, MEM}}, \ 1656 {"reg_or_some_mem_operand", {SUBREG, REG, MEM}}, \ 1657 {"tst_operand", {SUBREG, REG, MEM}}, \ 1658 {"cmp_operand", {SUBREG, REG, MEM, SYMBOL_REF, LABEL_REF, \ 1659 CONST_INT, CONST_DOUBLE}}, 1660 1661 /* Specify the machine mode that this machine uses 1662 for the index in the tablejump instruction. */ 1663 #define CASE_VECTOR_MODE Pmode 1664 1665 /* This flag, if defined, says the same insns that convert to a signed fixnum 1666 also convert validly to an unsigned one. */ 1667 #define FIXUNS_TRUNC_LIKE_FIX_TRUNC 1668 1669 /* Max number of bytes we can move from memory to memory in one 1670 reasonably fast instruction. */ 1671 #define MOVE_MAX 2 1672 1673 /* MOVE_RATIO is the number of move instructions that is better than a 1674 block move. Make this small on 6811, since the code size grows very 1675 large with each move. */ 1676 #define MOVE_RATIO 3 1677 1678 /* Define if shifts truncate the shift count which implies one can omit 1679 a sign-extension or zero-extension of a shift count. */ 1680 #define SHIFT_COUNT_TRUNCATED 1 1681 1682 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits 1683 is done just by pretending it is already truncated. */ 1684 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 1685 1686 /* Specify the machine mode that pointers have. After generation of rtl, the 1687 compiler makes no further distinction between pointers and any other 1688 objects of this machine mode. */ 1689 #define Pmode HImode 1690 1691 /* A function address in a call instruction is a byte address (for indexing 1692 purposes) so give the MEM rtx a byte's mode. */ 1693 #define FUNCTION_MODE QImode 1694 1695 extern int debug_m6811; 1696 extern int z_replacement_completed; 1697 extern int current_function_interrupt; 1698 extern int current_function_trap; 1699 extern int current_function_far; 1700 1701 extern GTY(()) rtx m68hc11_compare_op0; 1702 extern GTY(()) rtx m68hc11_compare_op1; 1703 extern GTY(()) rtx m68hc11_soft_tmp_reg; 1704 extern GTY(()) rtx ix_reg; 1705 extern GTY(()) rtx iy_reg; 1706 extern GTY(()) rtx d_reg; 1707