1 /* Definitions of target machine for GNU compiler, for the pdp-11 2 Copyright (C) 1994, 1995, 1996, 1998, 1999, 2000, 2001, 2002 3 Free Software Foundation, Inc. 4 Contributed by Michael K. Gschwind (mike@vlsivie.tuwien.ac.at). 5 6 This file is part of GCC. 7 8 GCC is free software; you can redistribute it and/or modify 9 it under the terms of the GNU General Public License as published by 10 the Free Software Foundation; either version 2, or (at your option) 11 any later version. 12 13 GCC is distributed in the hope that it will be useful, 14 but WITHOUT ANY WARRANTY; without even the implied warranty of 15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 GNU General Public License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with GCC; see the file COPYING. If not, write to 20 the Free Software Foundation, 59 Temple Place - Suite 330, 21 Boston, MA 02111-1307, USA. */ 22 23 #define CONSTANT_POOL_BEFORE_FUNCTION 0 24 25 /* check whether load_fpu_reg or not */ 26 #define LOAD_FPU_REG_P(x) ((x)>=8 && (x)<=11) 27 #define NO_LOAD_FPU_REG_P(x) ((x)==12 || (x)==13) 28 #define FPU_REG_P(x) (LOAD_FPU_REG_P(x) || NO_LOAD_FPU_REG_P(x)) 29 #define CPU_REG_P(x) ((x)<8) 30 31 /* Names to predefine in the preprocessor for this target machine. */ 32 33 #define TARGET_CPU_CPP_BUILTINS() \ 34 do \ 35 { \ 36 builtin_define_std ("pdp11"); \ 37 } \ 38 while (0) 39 40 /* Print subsidiary information on the compiler version in use. */ 41 #define TARGET_VERSION fprintf (stderr, " (pdp11)"); 42 43 44 /* Generate DBX debugging information. */ 45 46 /* #define DBX_DEBUGGING_INFO */ 47 48 /* Run-time compilation parameters selecting different hardware subsets. 49 */ 50 51 extern int target_flags; 52 53 /* Macro to define tables used to set the flags. 54 This is a list in braces of triplets in braces, 55 each triplet being { "NAME", VALUE, DOC } 56 where VALUE is the bits to set or minus the bits to clear and DOC 57 is the documentation for --help (NULL if intentionally undocumented). 58 An empty string NAME is used to identify the default VALUE. */ 59 60 #define TARGET_SWITCHES \ 61 { { "fpu", 1, N_("Use hardware floating point") }, \ 62 { "soft-float", -1, N_("Do not use hardware floating point") }, \ 63 /* return float result in ac0 */ \ 64 { "ac0", 2, N_("Return floating point results in ac0") }, \ 65 { "no-ac0", -2, N_("Return floating point results in memory") }, \ 66 /* is 11/40 */ \ 67 { "40", 4, N_("Generate code for an 11/40") }, \ 68 { "no-40", -4, "" }, \ 69 /* is 11/45 */ \ 70 { "45", 8, N_("Generate code for an 11/45") }, \ 71 { "no-45", -8, "" }, \ 72 /* is 11/10 */ \ 73 { "10", -12, N_("Generate code for an 11/10") }, \ 74 /* use movstrhi for bcopy */ \ 75 { "bcopy", 16, NULL }, \ 76 { "bcopy-builtin", -16, NULL }, \ 77 /* use 32 bit for int */ \ 78 { "int32", 32, N_("Use 32 bit int") }, \ 79 { "no-int16", 32, N_("Use 32 bit int") }, \ 80 { "int16", -32, N_("Use 16 bit int") }, \ 81 { "no-int32", -32, N_("Use 16 bit int") }, \ 82 /* use 32 bit for float */ \ 83 { "float32", 64, N_("Use 32 bit float") }, \ 84 { "no-float64", 64, N_("Use 32 bit float") }, \ 85 { "float64", -64, N_("Use 64 bit float") }, \ 86 { "no-float32", -64, N_("Use 64 bit float") }, \ 87 /* allow abshi pattern? - can trigger "optimizations" which make code SLOW! */\ 88 { "abshi", 128, NULL }, \ 89 { "no-abshi", -128, NULL }, \ 90 /* is branching expensive - on a PDP, it's actually really cheap */ \ 91 /* this is just to play around and check what code gcc generates */ \ 92 { "branch-expensive", 256, NULL }, \ 93 { "branch-cheap", -256, NULL }, \ 94 /* split instruction and data memory? */ \ 95 { "split", 1024, N_("Target has split I&D") }, \ 96 { "no-split", -1024, N_("Target does not have split I&D") }, \ 97 /* UNIX assembler syntax? */ \ 98 { "unix-asm", 2048, N_("Use UNIX assembler syntax") }, \ 99 { "dec-asm", -2048, N_("Use DEC assembler syntax") }, \ 100 /* default */ \ 101 { "", TARGET_DEFAULT, NULL} \ 102 } 103 104 #define TARGET_DEFAULT (1 | 8 | 128 | TARGET_UNIX_ASM_DEFAULT) 105 106 #define TARGET_FPU (target_flags & 1) 107 #define TARGET_SOFT_FLOAT (!TARGET_FPU) 108 109 #define TARGET_AC0 ((target_flags & 2) && TARGET_FPU) 110 #define TARGET_NO_AC0 (! TARGET_AC0) 111 112 #define TARGET_45 (target_flags & 8) 113 #define TARGET_40_PLUS ((target_flags & 4) || (target_flags & 8)) 114 #define TARGET_10 (! TARGET_40_PLUS) 115 116 #define TARGET_BCOPY_BUILTIN (! (target_flags & 16)) 117 118 #define TARGET_INT16 (! TARGET_INT32) 119 #define TARGET_INT32 (target_flags & 32) 120 121 #define TARGET_FLOAT32 (target_flags & 64) 122 #define TARGET_FLOAT64 (! TARGET_FLOAT32) 123 124 #define TARGET_ABSHI_BUILTIN (target_flags & 128) 125 126 #define TARGET_BRANCH_EXPENSIVE (target_flags & 256) 127 #define TARGET_BRANCH_CHEAP (!TARGET_BRANCH_EXPENSIVE) 128 129 #define TARGET_SPLIT (target_flags & 1024) 130 #define TARGET_NOSPLIT (! TARGET_SPLIT) 131 132 #define TARGET_UNIX_ASM (target_flags & 2048) 133 #define TARGET_UNIX_ASM_DEFAULT 0 134 135 #define ASSEMBLER_DIALECT (TARGET_UNIX_ASM ? 1 : 0) 136 137 138 139 /* TYPE SIZES */ 140 #define SHORT_TYPE_SIZE 16 141 #define INT_TYPE_SIZE (TARGET_INT16 ? 16 : 32) 142 #define LONG_TYPE_SIZE 32 143 #define LONG_LONG_TYPE_SIZE 64 144 145 /* if we set FLOAT_TYPE_SIZE to 32, we could have the benefit 146 of saving core for huge arrays - the definitions are 147 already in md - but floats can never reside in 148 an FPU register - we keep the FPU in double float mode 149 all the time !! */ 150 #define FLOAT_TYPE_SIZE (TARGET_FLOAT32 ? 32 : 64) 151 #define DOUBLE_TYPE_SIZE 64 152 #define LONG_DOUBLE_TYPE_SIZE 64 153 154 /* machine types from ansi */ 155 #define SIZE_TYPE "unsigned int" /* definition of size_t */ 156 #define WCHAR_TYPE "int" /* or long int???? */ 157 #define WCHAR_TYPE_SIZE 16 158 159 #define PTRDIFF_TYPE "int" 160 161 /* target machine storage layout */ 162 163 /* Define this if most significant bit is lowest numbered 164 in instructions that operate on numbered bit-fields. */ 165 #define BITS_BIG_ENDIAN 0 166 167 /* Define this if most significant byte of a word is the lowest numbered. */ 168 #define BYTES_BIG_ENDIAN 0 169 170 /* Define this if most significant word of a multiword number is numbered. */ 171 #define WORDS_BIG_ENDIAN 1 172 173 /* Width of a word, in units (bytes). 174 175 UNITS OR BYTES - seems like units */ 176 #define UNITS_PER_WORD 2 177 178 /* Maximum sized of reasonable data type 179 DImode or Dfmode ...*/ 180 #define MAX_FIXED_MODE_SIZE 64 181 182 /* Allocation boundary (in *bits*) for storing pointers in memory. */ 183 #define POINTER_BOUNDARY 16 184 185 /* Allocation boundary (in *bits*) for storing arguments in argument list. */ 186 #define PARM_BOUNDARY 16 187 188 /* Boundary (in *bits*) on which stack pointer should be aligned. */ 189 #define STACK_BOUNDARY 16 190 191 /* Allocation boundary (in *bits*) for the code of a function. */ 192 #define FUNCTION_BOUNDARY 16 193 194 /* Alignment of field after `int : 0' in a structure. */ 195 #define EMPTY_FIELD_BOUNDARY 16 196 197 /* No data type wants to be aligned rounder than this. */ 198 #define BIGGEST_ALIGNMENT 16 199 200 /* Define this if move instructions will actually fail to work 201 when given unaligned data. */ 202 #define STRICT_ALIGNMENT 1 203 204 /* Standard register usage. */ 205 206 /* Number of actual hardware registers. 207 The hardware registers are assigned numbers for the compiler 208 from 0 to just below FIRST_PSEUDO_REGISTER. 209 All registers that the compiler knows about must be given numbers, 210 even those that are not normally considered general registers. 211 212 we have 8 integer registers, plus 6 float 213 (don't use scratch float !) */ 214 215 #define FIRST_PSEUDO_REGISTER 14 216 217 /* 1 for registers that have pervasive standard uses 218 and are not available for the register allocator. 219 220 On the pdp, these are: 221 Reg 7 = pc; 222 reg 6 = sp; 223 reg 5 = fp; not necessarily! 224 */ 225 226 /* don't let them touch fp regs for the time being !*/ 227 228 #define FIXED_REGISTERS \ 229 {0, 0, 0, 0, 0, 0, 1, 1, \ 230 0, 0, 0, 0, 0, 0 } 231 232 233 234 /* 1 for registers not available across function calls. 235 These must include the FIXED_REGISTERS and also any 236 registers that can be used without being saved. 237 The latter must include the registers where values are returned 238 and the register where structure-value addresses are passed. 239 Aside from that, you can include as many other registers as you like. */ 240 241 /* don't know about fp */ 242 #define CALL_USED_REGISTERS \ 243 {1, 1, 0, 0, 0, 0, 1, 1, \ 244 0, 0, 0, 0, 0, 0 } 245 246 247 /* Make sure everything's fine if we *don't* have an FPU. 248 This assumes that putting a register in fixed_regs will keep the 249 compiler's mitts completely off it. We don't bother to zero it out 250 of register classes. Also fix incompatible register naming with 251 the UNIX assembler. 252 */ 253 #define CONDITIONAL_REGISTER_USAGE \ 254 { \ 255 int i; \ 256 HARD_REG_SET x; \ 257 if (!TARGET_FPU) \ 258 { \ 259 COPY_HARD_REG_SET (x, reg_class_contents[(int)FPU_REGS]); \ 260 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++ ) \ 261 if (TEST_HARD_REG_BIT (x, i)) \ 262 fixed_regs[i] = call_used_regs[i] = 1; \ 263 } \ 264 \ 265 if (TARGET_AC0) \ 266 call_used_regs[8] = 1; \ 267 if (TARGET_UNIX_ASM) \ 268 { \ 269 /* Change names of FPU registers for the UNIX assembler. */ \ 270 reg_names[8] = "fr0"; \ 271 reg_names[9] = "fr1"; \ 272 reg_names[10] = "fr2"; \ 273 reg_names[11] = "fr3"; \ 274 reg_names[12] = "fr4"; \ 275 reg_names[13] = "fr5"; \ 276 } \ 277 } 278 279 /* Return number of consecutive hard regs needed starting at reg REGNO 280 to hold something of mode MODE. 281 This is ordinarily the length in words of a value of mode MODE 282 but can be less for certain modes in special long registers. 283 */ 284 285 #define HARD_REGNO_NREGS(REGNO, MODE) \ 286 ((REGNO < 8)? \ 287 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) \ 288 :1) 289 290 291 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. 292 On the pdp, the cpu registers can hold any mode - check alignment 293 294 FPU can only hold DF - simplifies life! 295 */ 296 #define HARD_REGNO_MODE_OK(REGNO, MODE) \ 297 (((REGNO) < 8)? \ 298 ((GET_MODE_BITSIZE(MODE) <= 16) \ 299 || (GET_MODE_BITSIZE(MODE) == 32 && !((REGNO) & 1))) \ 300 :(MODE) == DFmode) 301 302 303 /* Value is 1 if it is a good idea to tie two pseudo registers 304 when one has mode MODE1 and one has mode MODE2. 305 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, 306 for any hard reg, then this must be 0 for correct output. */ 307 #define MODES_TIEABLE_P(MODE1, MODE2) 0 308 309 /* Specify the registers used for certain standard purposes. 310 The values of these macros are register numbers. */ 311 312 /* the pdp11 pc overloaded on a register that the compiler knows about. */ 313 #define PC_REGNUM 7 314 315 /* Register to use for pushing function arguments. */ 316 #define STACK_POINTER_REGNUM 6 317 318 /* Base register for access to local variables of the function. */ 319 #define FRAME_POINTER_REGNUM 5 320 321 /* Value should be nonzero if functions must have frame pointers. 322 Zero means the frame pointer need not be set up (and parms 323 may be accessed via the stack pointer) in functions that seem suitable. 324 This is computed in `reload', in reload1.c. 325 */ 326 327 #define FRAME_POINTER_REQUIRED 0 328 329 /* Base register for access to arguments of the function. */ 330 #define ARG_POINTER_REGNUM 5 331 332 /* Register in which static-chain is passed to a function. */ 333 /* ??? - i don't want to give up a reg for this! */ 334 #define STATIC_CHAIN_REGNUM 4 335 336 /* Register in which address to store a structure value 337 is passed to a function. 338 let's make it an invisible first argument!!! */ 339 340 #define STRUCT_VALUE 0 341 342 343 /* Define the classes of registers for register constraints in the 344 machine description. Also define ranges of constants. 345 346 One of the classes must always be named ALL_REGS and include all hard regs. 347 If there is more than one class, another class must be named NO_REGS 348 and contain no registers. 349 350 The name GENERAL_REGS must be the name of a class (or an alias for 351 another name such as ALL_REGS). This is the class of registers 352 that is allowed by "g" or "r" in a register constraint. 353 Also, registers outside this class are allocated only when 354 instructions express preferences for them. 355 356 The classes must be numbered in nondecreasing order; that is, 357 a larger-numbered class must never be contained completely 358 in a smaller-numbered class. 359 360 For any two classes, it is very desirable that there be another 361 class that represents their union. */ 362 363 /* The pdp has a couple of classes: 364 365 MUL_REGS are used for odd numbered regs, to use in 16 bit multiplication 366 (even numbered do 32 bit multiply) 367 LMUL_REGS long multiply registers (even numbered regs ) 368 (don't need them, all 32 bit regs are even numbered!) 369 GENERAL_REGS is all cpu 370 LOAD_FPU_REGS is the first four cpu regs, they are easier to load 371 NO_LOAD_FPU_REGS is ac4 and ac5, currently - difficult to load them 372 FPU_REGS is all fpu regs 373 */ 374 375 enum reg_class { NO_REGS, MUL_REGS, GENERAL_REGS, LOAD_FPU_REGS, NO_LOAD_FPU_REGS, FPU_REGS, ALL_REGS, LIM_REG_CLASSES }; 376 377 #define N_REG_CLASSES (int) LIM_REG_CLASSES 378 379 /* have to allow this till cmpsi/tstsi are fixed in a better way !! */ 380 #define SMALL_REGISTER_CLASSES 1 381 382 /* Since GENERAL_REGS is the same class as ALL_REGS, 383 don't give it a different class number; just make it an alias. */ 384 385 /* #define GENERAL_REGS ALL_REGS */ 386 387 /* Give names of register classes as strings for dump file. */ 388 389 #define REG_CLASS_NAMES {"NO_REGS", "MUL_REGS", "GENERAL_REGS", "LOAD_FPU_REGS", "NO_LOAD_FPU_REGS", "FPU_REGS", "ALL_REGS" } 390 391 /* Define which registers fit in which classes. 392 This is an initializer for a vector of HARD_REG_SET 393 of length N_REG_CLASSES. */ 394 395 #define REG_CLASS_CONTENTS {{0}, {0x00aa}, {0x00ff}, {0x0f00}, {0x3000}, {0x3f00}, {0x3fff}} 396 397 /* The same information, inverted: 398 Return the class number of the smallest class containing 399 reg number REGNO. This could be a conditional expression 400 or could index an array. */ 401 402 #define REGNO_REG_CLASS(REGNO) \ 403 ((REGNO)>=8?((REGNO)<=11?LOAD_FPU_REGS:NO_LOAD_FPU_REGS):(((REGNO)&1)?MUL_REGS:GENERAL_REGS)) 404 405 406 /* The class value for index registers, and the one for base regs. */ 407 #define INDEX_REG_CLASS GENERAL_REGS 408 #define BASE_REG_CLASS GENERAL_REGS 409 410 /* Get reg_class from a letter such as appears in the machine description. */ 411 412 #define REG_CLASS_FROM_LETTER(C) \ 413 ((C) == 'f' ? FPU_REGS : \ 414 ((C) == 'd' ? MUL_REGS : \ 415 ((C) == 'a' ? LOAD_FPU_REGS : NO_REGS))) 416 417 418 /* The letters I, J, K, L and M in a register constraint string 419 can be used to stand for particular ranges of immediate operands. 420 This macro defines what the ranges are. 421 C is the letter, and VALUE is a constant value. 422 Return 1 if VALUE is in the range specified by C. 423 424 I bits 31-16 0000 425 J bits 15-00 0000 426 K completely random 32 bit 427 L,M,N -1,1,0 respectively 428 O where doing shifts in sequence is faster than 429 one big shift 430 */ 431 432 #define CONST_OK_FOR_LETTER_P(VALUE, C) \ 433 ((C) == 'I' ? ((VALUE) & 0xffff0000) == 0 \ 434 : (C) == 'J' ? ((VALUE) & 0x0000ffff) == 0 \ 435 : (C) == 'K' ? (((VALUE) & 0xffff0000) != 0 \ 436 && ((VALUE) & 0x0000ffff) != 0) \ 437 : (C) == 'L' ? ((VALUE) == 1) \ 438 : (C) == 'M' ? ((VALUE) == -1) \ 439 : (C) == 'N' ? ((VALUE) == 0) \ 440 : (C) == 'O' ? (abs(VALUE) >1 && abs(VALUE) <= 4) \ 441 : 0) 442 443 /* Similar, but for floating constants, and defining letters G and H. 444 Here VALUE is the CONST_DOUBLE rtx itself. */ 445 446 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \ 447 ((C) == 'G' && XINT (VALUE, 0) == 0 && XINT (VALUE, 1) == 0) 448 449 450 /* Letters in the range `Q' through `U' may be defined in a 451 machine-dependent fashion to stand for arbitrary operand types. 452 The machine description macro `EXTRA_CONSTRAINT' is passed the 453 operand as its first argument and the constraint letter as its 454 second operand. 455 456 `Q' is for memory references using take more than 1 instruction. 457 `R' is for memory references which take 1 word for the instruction. */ 458 459 #define EXTRA_CONSTRAINT(OP,CODE) \ 460 ((GET_CODE (OP) != MEM) ? 0 \ 461 : !legitimate_address_p (GET_MODE (OP), XEXP (OP, 0)) ? 0 \ 462 : ((CODE) == 'Q') ? !simple_memory_operand (OP, GET_MODE (OP)) \ 463 : ((CODE) == 'R') ? simple_memory_operand (OP, GET_MODE (OP)) \ 464 : 0) 465 466 /* Given an rtx X being reloaded into a reg required to be 467 in class CLASS, return the class of reg to actually use. 468 In general this is just CLASS; but on some machines 469 in some cases it is preferable to use a more restrictive class. 470 471 loading is easier into LOAD_FPU_REGS than FPU_REGS! */ 472 473 #define PREFERRED_RELOAD_CLASS(X,CLASS) \ 474 (((CLASS) != FPU_REGS)?(CLASS):LOAD_FPU_REGS) 475 476 #define SECONDARY_RELOAD_CLASS(CLASS,MODE,x) \ 477 (((CLASS) == NO_LOAD_FPU_REGS && !(REG_P(x) && LOAD_FPU_REG_P(REGNO(x))))?LOAD_FPU_REGS:NO_REGS) 478 479 /* Return the maximum number of consecutive registers 480 needed to represent mode MODE in a register of class CLASS. */ 481 #define CLASS_MAX_NREGS(CLASS, MODE) \ 482 ((CLASS == GENERAL_REGS || CLASS == MUL_REGS)? \ 483 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD): \ 484 1 \ 485 ) 486 487 488 /* Stack layout; function entry, exit and calling. */ 489 490 /* Define this if pushing a word on the stack 491 makes the stack pointer a smaller address. */ 492 #define STACK_GROWS_DOWNWARD 493 494 /* Define this if the nominal address of the stack frame 495 is at the high-address end of the local variables; 496 that is, each additional local variable allocated 497 goes at a more negative offset in the frame. 498 */ 499 #define FRAME_GROWS_DOWNWARD 500 501 /* Offset within stack frame to start allocating local variables at. 502 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the 503 first local allocated. Otherwise, it is the offset to the BEGINNING 504 of the first local allocated. */ 505 #define STARTING_FRAME_OFFSET 0 506 507 /* If we generate an insn to push BYTES bytes, 508 this says how many the stack pointer really advances by. 509 On the pdp11, the stack is on an even boundary */ 510 #define PUSH_ROUNDING(BYTES) ((BYTES + 1) & ~1) 511 512 /* current_first_parm_offset stores the # of registers pushed on the 513 stack */ 514 extern int current_first_parm_offset; 515 516 /* Offset of first parameter from the argument pointer register value. 517 For the pdp11, this is nonzero to account for the return address. 518 1 - return address 519 2 - frame pointer (always saved, even when not used!!!!) 520 -- chnage some day !!!:q! 521 522 */ 523 #define FIRST_PARM_OFFSET(FNDECL) 4 524 525 /* Value is 1 if returning from a function call automatically 526 pops the arguments described by the number-of-args field in the call. 527 FUNDECL is the declaration node of the function (as a tree), 528 FUNTYPE is the data type of the function (as a tree), 529 or for a library call it is an identifier node for the subroutine name. */ 530 531 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0 532 533 /* Define how to find the value returned by a function. 534 VALTYPE is the data type of the value (as a tree). 535 If the precise function being called is known, FUNC is its FUNCTION_DECL; 536 otherwise, FUNC is 0. */ 537 #define BASE_RETURN_VALUE_REG(MODE) \ 538 ((MODE) == DFmode ? 8 : 0) 539 540 /* On the pdp11 the value is found in R0 (or ac0??? 541 not without FPU!!!! ) */ 542 543 #define FUNCTION_VALUE(VALTYPE, FUNC) \ 544 gen_rtx_REG (TYPE_MODE (VALTYPE), BASE_RETURN_VALUE_REG(TYPE_MODE(VALTYPE))) 545 546 /* and the called function leaves it in the first register. 547 Difference only on machines with register windows. */ 548 549 #define FUNCTION_OUTGOING_VALUE(VALTYPE, FUNC) \ 550 gen_rtx_REG (TYPE_MODE (VALTYPE), BASE_RETURN_VALUE_REG(TYPE_MODE(VALTYPE))) 551 552 /* Define how to find the value returned by a library function 553 assuming the value has mode MODE. */ 554 555 #define LIBCALL_VALUE(MODE) gen_rtx_REG (MODE, BASE_RETURN_VALUE_REG(MODE)) 556 557 /* 1 if N is a possible register number for a function value 558 as seen by the caller. 559 On the pdp, the first "output" reg is the only register thus used. 560 561 maybe ac0 ? - as option someday! */ 562 563 #define FUNCTION_VALUE_REGNO_P(N) (((N) == 0) || (TARGET_AC0 && (N) == 8)) 564 565 /* should probably return DImode and DFmode in memory,lest 566 we fill up all regs! 567 568 have to, else we crash - exception: maybe return result in 569 ac0 if DFmode and FPU present - compatibility problem with 570 libraries for non-floating point ... 571 */ 572 573 #define RETURN_IN_MEMORY(TYPE) \ 574 (TYPE_MODE(TYPE) == DImode || (TYPE_MODE(TYPE) == DFmode && ! TARGET_AC0)) 575 576 577 /* 1 if N is a possible register number for function argument passing. 578 - not used on pdp */ 579 580 #define FUNCTION_ARG_REGNO_P(N) 0 581 582 /* Define a data type for recording info about an argument list 583 during the scan of that argument list. This data type should 584 hold all necessary information about the function itself 585 and about the args processed so far, enough to enable macros 586 such as FUNCTION_ARG to determine where the next arg should go. 587 588 */ 589 590 #define CUMULATIVE_ARGS int 591 592 /* Initialize a variable CUM of type CUMULATIVE_ARGS 593 for a call to a function whose data type is FNTYPE. 594 For a library call, FNTYPE is 0. 595 596 ...., the offset normally starts at 0, but starts at 1 word 597 when the function gets a structure-value-address as an 598 invisible first argument. */ 599 600 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \ 601 ((CUM) = 0) 602 603 /* Update the data in CUM to advance over an argument 604 of mode MODE and data type TYPE. 605 (TYPE is null for libcalls where that information may not be available.) 606 607 */ 608 609 610 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ 611 ((CUM) += ((MODE) != BLKmode \ 612 ? (GET_MODE_SIZE (MODE)) \ 613 : (int_size_in_bytes (TYPE)))) 614 615 /* Determine where to put an argument to a function. 616 Value is zero to push the argument on the stack, 617 or a hard register in which to store the argument. 618 619 MODE is the argument's machine mode. 620 TYPE is the data type of the argument (as a tree). 621 This is null for libcalls where that information may 622 not be available. 623 CUM is a variable of type CUMULATIVE_ARGS which gives info about 624 the preceding args and about the function being called. 625 NAMED is nonzero if this argument is a named parameter 626 (otherwise it is an extra parameter matching an ellipsis). */ 627 628 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) 0 629 630 /* Define where a function finds its arguments. 631 This would be different from FUNCTION_ARG if we had register windows. */ 632 /* 633 #define FUNCTION_INCOMING_ARG(CUM, MODE, TYPE, NAMED) \ 634 FUNCTION_ARG (CUM, MODE, TYPE, NAMED) 635 */ 636 637 /* For an arg passed partly in registers and partly in memory, 638 this is the number of registers used. 639 For args passed entirely in registers or entirely in memory, zero. */ 640 641 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) 0 642 643 /* Output assembler code to FILE to increment profiler label # LABELNO 644 for profiling a function entry. */ 645 646 #define FUNCTION_PROFILER(FILE, LABELNO) \ 647 abort (); 648 649 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, 650 the stack pointer does not matter. The value is tested only in 651 functions that have frame pointers. 652 No definition is equivalent to always zero. */ 653 654 extern int may_call_alloca; 655 656 #define EXIT_IGNORE_STACK 1 657 658 #define INITIAL_FRAME_POINTER_OFFSET(DEPTH_VAR) \ 659 { \ 660 int offset, regno; \ 661 offset = get_frame_size(); \ 662 for (regno = 0; regno < 8; regno++) \ 663 if (regs_ever_live[regno] && ! call_used_regs[regno]) \ 664 offset += 2; \ 665 for (regno = 8; regno < 14; regno++) \ 666 if (regs_ever_live[regno] && ! call_used_regs[regno]) \ 667 offset += 8; \ 668 /* offset -= 2; no fp on stack frame */ \ 669 (DEPTH_VAR) = offset; \ 670 } 671 672 673 /* Addressing modes, and classification of registers for them. */ 674 675 #define HAVE_POST_INCREMENT 1 676 677 #define HAVE_PRE_DECREMENT 1 678 679 /* Macros to check register numbers against specific register classes. */ 680 681 /* These assume that REGNO is a hard or pseudo reg number. 682 They give nonzero only if REGNO is a hard reg of the suitable class 683 or a pseudo reg currently allocated to a suitable hard reg. 684 Since they use reg_renumber, they are safe only once reg_renumber 685 has been allocated, which happens in local-alloc.c. */ 686 687 #define REGNO_OK_FOR_INDEX_P(REGNO) \ 688 ((REGNO) < 8 || (unsigned) reg_renumber[REGNO] < 8) 689 #define REGNO_OK_FOR_BASE_P(REGNO) \ 690 ((REGNO) < 8 || (unsigned) reg_renumber[REGNO] < 8) 691 692 /* Now macros that check whether X is a register and also, 693 strictly, whether it is in a specified class. 694 */ 695 696 697 698 /* Maximum number of registers that can appear in a valid memory address. */ 699 700 #define MAX_REGS_PER_ADDRESS 2 701 702 /* Recognize any constant value that is a valid address. */ 703 704 #define CONSTANT_ADDRESS_P(X) CONSTANT_P (X) 705 706 /* Nonzero if the constant value X is a legitimate general operand. 707 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */ 708 709 #define LEGITIMATE_CONSTANT_P(X) (TARGET_FPU? 1: !(GET_CODE(X) == CONST_DOUBLE)) 710 711 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx 712 and check its validity for a certain class. 713 We have two alternate definitions for each of them. 714 The usual definition accepts all pseudo regs; the other rejects 715 them unless they have been allocated suitable hard regs. 716 The symbol REG_OK_STRICT causes the latter definition to be used. 717 718 Most source files want to accept pseudo regs in the hope that 719 they will get allocated to the class that the insn wants them to be in. 720 Source files for reload pass need to be strict. 721 After reload, it makes no difference, since pseudo regs have 722 been eliminated by then. */ 723 724 #ifndef REG_OK_STRICT 725 726 /* Nonzero if X is a hard reg that can be used as an index 727 or if it is a pseudo reg. */ 728 #define REG_OK_FOR_INDEX_P(X) (1) 729 /* Nonzero if X is a hard reg that can be used as a base reg 730 or if it is a pseudo reg. */ 731 #define REG_OK_FOR_BASE_P(X) (1) 732 733 #else 734 735 /* Nonzero if X is a hard reg that can be used as an index. */ 736 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X)) 737 /* Nonzero if X is a hard reg that can be used as a base reg. */ 738 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X)) 739 740 #endif 741 742 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression 743 that is a valid memory address for an instruction. 744 The MODE argument is the machine mode for the MEM expression 745 that wants to use this address. 746 747 */ 748 749 #define GO_IF_LEGITIMATE_ADDRESS(mode, operand, ADDR) \ 750 { \ 751 rtx xfoob; \ 752 \ 753 /* accept (R0) */ \ 754 if (GET_CODE (operand) == REG \ 755 && REG_OK_FOR_BASE_P(operand)) \ 756 goto ADDR; \ 757 \ 758 /* accept @#address */ \ 759 if (CONSTANT_ADDRESS_P (operand)) \ 760 goto ADDR; \ 761 \ 762 /* accept X(R0) */ \ 763 if (GET_CODE (operand) == PLUS \ 764 && GET_CODE (XEXP (operand, 0)) == REG \ 765 && REG_OK_FOR_BASE_P (XEXP (operand, 0)) \ 766 && CONSTANT_ADDRESS_P (XEXP (operand, 1))) \ 767 goto ADDR; \ 768 \ 769 /* accept -(R0) */ \ 770 if (GET_CODE (operand) == PRE_DEC \ 771 && GET_CODE (XEXP (operand, 0)) == REG \ 772 && REG_OK_FOR_BASE_P (XEXP (operand, 0))) \ 773 goto ADDR; \ 774 \ 775 /* accept (R0)+ */ \ 776 if (GET_CODE (operand) == POST_INC \ 777 && GET_CODE (XEXP (operand, 0)) == REG \ 778 && REG_OK_FOR_BASE_P (XEXP (operand, 0))) \ 779 goto ADDR; \ 780 \ 781 /* accept -(SP) -- which uses PRE_MODIFY for byte mode */ \ 782 if (GET_CODE (operand) == PRE_MODIFY \ 783 && GET_CODE (XEXP (operand, 0)) == REG \ 784 && REGNO (XEXP (operand, 0)) == 6 \ 785 && GET_CODE ((xfoob = XEXP (operand, 1))) == PLUS \ 786 && GET_CODE (XEXP (xfoob, 0)) == REG \ 787 && REGNO (XEXP (xfoob, 0)) == 6 \ 788 && CONSTANT_P (XEXP (xfoob, 1)) \ 789 && INTVAL (XEXP (xfoob,1)) == -2) \ 790 goto ADDR; \ 791 \ 792 /* accept (SP)+ -- which uses POST_MODIFY for byte mode */ \ 793 if (GET_CODE (operand) == POST_MODIFY \ 794 && GET_CODE (XEXP (operand, 0)) == REG \ 795 && REGNO (XEXP (operand, 0)) == 6 \ 796 && GET_CODE ((xfoob = XEXP (operand, 1))) == PLUS \ 797 && GET_CODE (XEXP (xfoob, 0)) == REG \ 798 && REGNO (XEXP (xfoob, 0)) == 6 \ 799 && CONSTANT_P (XEXP (xfoob, 1)) \ 800 && INTVAL (XEXP (xfoob,1)) == 2) \ 801 goto ADDR; \ 802 \ 803 \ 804 /* handle another level of indirection ! */ \ 805 if (GET_CODE(operand) != MEM) \ 806 goto fail; \ 807 \ 808 xfoob = XEXP (operand, 0); \ 809 \ 810 /* (MEM:xx (MEM:xx ())) is not valid for SI, DI and currently */ \ 811 /* also forbidden for float, because we have to handle this */ \ 812 /* in output_move_double and/or output_move_quad() - we could */ \ 813 /* do it, but currently it's not worth it!!! */ \ 814 /* now that DFmode cannot go into CPU register file, */ \ 815 /* maybe I should allow float ... */ \ 816 /* but then I have to handle memory-to-memory moves in movdf ?? */ \ 817 \ 818 if (GET_MODE_BITSIZE(mode) > 16) \ 819 goto fail; \ 820 \ 821 /* accept @(R0) - which is @0(R0) */ \ 822 if (GET_CODE (xfoob) == REG \ 823 && REG_OK_FOR_BASE_P(xfoob)) \ 824 goto ADDR; \ 825 \ 826 /* accept @address */ \ 827 if (CONSTANT_ADDRESS_P (xfoob)) \ 828 goto ADDR; \ 829 \ 830 /* accept @X(R0) */ \ 831 if (GET_CODE (xfoob) == PLUS \ 832 && GET_CODE (XEXP (xfoob, 0)) == REG \ 833 && REG_OK_FOR_BASE_P (XEXP (xfoob, 0)) \ 834 && CONSTANT_ADDRESS_P (XEXP (xfoob, 1))) \ 835 goto ADDR; \ 836 \ 837 /* accept @-(R0) */ \ 838 if (GET_CODE (xfoob) == PRE_DEC \ 839 && GET_CODE (XEXP (xfoob, 0)) == REG \ 840 && REG_OK_FOR_BASE_P (XEXP (xfoob, 0))) \ 841 goto ADDR; \ 842 \ 843 /* accept @(R0)+ */ \ 844 if (GET_CODE (xfoob) == POST_INC \ 845 && GET_CODE (XEXP (xfoob, 0)) == REG \ 846 && REG_OK_FOR_BASE_P (XEXP (xfoob, 0))) \ 847 goto ADDR; \ 848 \ 849 /* anything else is invalid */ \ 850 fail: ; \ 851 } 852 853 854 /* Try machine-dependent ways of modifying an illegitimate address 855 to be legitimate. If we find one, return the new, valid address. 856 This macro is used in only one place: `memory_address' in explow.c. 857 858 OLDX is the address as it was before break_out_memory_refs was called. 859 In some cases it is useful to look at this to decide what needs to be done. 860 861 MODE and WIN are passed so that this macro can use 862 GO_IF_LEGITIMATE_ADDRESS. 863 864 It is always safe for this macro to do nothing. It exists to recognize 865 opportunities to optimize the output. */ 866 867 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) {} 868 869 870 /* Go to LABEL if ADDR (a legitimate address expression) 871 has an effect that depends on the machine mode it is used for. 872 On the pdp this is for predec/postinc */ 873 874 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \ 875 { if (GET_CODE (ADDR) == POST_INC || GET_CODE (ADDR) == PRE_DEC) \ 876 goto LABEL; \ 877 } 878 879 880 /* Specify the machine mode that this machine uses 881 for the index in the tablejump instruction. */ 882 #define CASE_VECTOR_MODE HImode 883 884 /* Define this if a raw index is all that is needed for a 885 `tablejump' insn. */ 886 #define CASE_TAKES_INDEX_RAW 887 888 /* Define as C expression which evaluates to nonzero if the tablejump 889 instruction expects the table to contain offsets from the address of the 890 table. 891 Do not define this if the table should contain absolute addresses. */ 892 /* #define CASE_VECTOR_PC_RELATIVE 1 */ 893 894 /* Define this as 1 if `char' should by default be signed; else as 0. */ 895 #define DEFAULT_SIGNED_CHAR 1 896 897 /* Max number of bytes we can move from memory to memory 898 in one reasonably fast instruction. 899 */ 900 901 #define MOVE_MAX 2 902 903 /* Nonzero if access to memory by byte is slow and undesirable. - 904 */ 905 #define SLOW_BYTE_ACCESS 0 906 907 /* Do not break .stabs pseudos into continuations. */ 908 #define DBX_CONTIN_LENGTH 0 909 910 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits 911 is done just by pretending it is already truncated. */ 912 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 913 914 /* Give a comparison code (EQ, NE etc) and the first operand of a COMPARE, 915 return the mode to be used for the comparison. For floating-point, CCFPmode 916 should be used. */ 917 918 #define SELECT_CC_MODE(OP,X,Y) \ 919 (GET_MODE_CLASS(GET_MODE(X)) == MODE_FLOAT? CCFPmode : CCmode) 920 921 /* Specify the machine mode that pointers have. 922 After generation of rtl, the compiler makes no further distinction 923 between pointers and any other objects of this machine mode. */ 924 #define Pmode HImode 925 926 /* A function address in a call instruction 927 is a word address (for indexing purposes) 928 so give the MEM rtx a word's mode. */ 929 #define FUNCTION_MODE HImode 930 931 /* Define this if addresses of constant functions 932 shouldn't be put through pseudo regs where they can be cse'd. 933 Desirable on machines where ordinary constants are expensive 934 but a CALL with constant address is cheap. */ 935 /* #define NO_FUNCTION_CSE */ 936 937 938 /* cost of moving one register class to another */ 939 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \ 940 register_move_cost (CLASS1, CLASS2) 941 942 /* Tell emit-rtl.c how to initialize special values on a per-function base. */ 943 extern int optimize; 944 extern struct rtx_def *cc0_reg_rtx; 945 946 #define CC_STATUS_MDEP rtx 947 948 #define CC_STATUS_MDEP_INIT (cc_status.mdep = 0) 949 950 /* Tell final.c how to eliminate redundant test instructions. */ 951 952 /* Here we define machine-dependent flags and fields in cc_status 953 (see `conditions.h'). */ 954 955 #define CC_IN_FPU 04000 956 957 /* Do UPDATE_CC if EXP is a set, used in 958 NOTICE_UPDATE_CC 959 960 floats only do compare correctly, else nullify ... 961 962 get cc0 out soon ... 963 */ 964 965 /* Store in cc_status the expressions 966 that the condition codes will describe 967 after execution of an instruction whose pattern is EXP. 968 Do not alter them if the instruction would not alter the cc's. */ 969 970 #define NOTICE_UPDATE_CC(EXP, INSN) \ 971 { if (GET_CODE (EXP) == SET) \ 972 { \ 973 notice_update_cc_on_set(EXP, INSN); \ 974 } \ 975 else if (GET_CODE (EXP) == PARALLEL \ 976 && GET_CODE (XVECEXP (EXP, 0, 0)) == SET) \ 977 { \ 978 notice_update_cc_on_set(XVECEXP (EXP, 0, 0), INSN); \ 979 } \ 980 else if (GET_CODE (EXP) == CALL) \ 981 { /* all bets are off */ CC_STATUS_INIT; } \ 982 if (cc_status.value1 && GET_CODE (cc_status.value1) == REG \ 983 && cc_status.value2 \ 984 && reg_overlap_mentioned_p (cc_status.value1, cc_status.value2)) \ 985 { \ 986 printf ("here!\n"); \ 987 cc_status.value2 = 0; \ 988 } \ 989 } 990 991 /* Control the assembler format that we output. */ 992 993 /* Output to assembler file text saying following lines 994 may contain character constants, extra white space, comments, etc. */ 995 996 #define ASM_APP_ON "" 997 998 /* Output to assembler file text saying following lines 999 no longer contain unusual constructs. */ 1000 1001 #define ASM_APP_OFF "" 1002 1003 /* Output before read-only data. */ 1004 1005 #define TEXT_SECTION_ASM_OP "\t.text\n" 1006 1007 /* Output before writable data. */ 1008 1009 #define DATA_SECTION_ASM_OP "\t.data\n" 1010 1011 /* How to refer to registers in assembler output. 1012 This sequence is indexed by compiler's hard-register-number (see above). */ 1013 1014 #define REGISTER_NAMES \ 1015 {"r0", "r1", "r2", "r3", "r4", "r5", "sp", "pc", \ 1016 "ac0", "ac1", "ac2", "ac3", "ac4", "ac5" } 1017 1018 /* Globalizing directive for a label. */ 1019 #define GLOBAL_ASM_OP "\t.globl " 1020 1021 /* The prefix to add to user-visible assembler symbols. */ 1022 1023 #define USER_LABEL_PREFIX "_" 1024 1025 /* This is how to store into the string LABEL 1026 the symbol_ref name of an internal numbered label where 1027 PREFIX is the class of label and NUM is the number within the class. 1028 This is suitable for output with `assemble_name'. */ 1029 1030 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \ 1031 sprintf (LABEL, "*%s_%lu", PREFIX, (unsigned long)(NUM)) 1032 1033 #define ASM_OUTPUT_ASCII(FILE, P, SIZE) \ 1034 output_ascii (FILE, P, SIZE) 1035 1036 /* This is how to output an element of a case-vector that is absolute. */ 1037 1038 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ 1039 fprintf (FILE, "\t%sL_%d\n", TARGET_UNIX_ASM ? "" : ".word ", VALUE) 1040 1041 /* This is how to output an element of a case-vector that is relative. 1042 Don't define this if it is not supported. */ 1043 1044 /* #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) */ 1045 1046 /* This is how to output an assembler line 1047 that says to advance the location counter 1048 to a multiple of 2**LOG bytes. 1049 1050 who needs this???? 1051 */ 1052 1053 #define ASM_OUTPUT_ALIGN(FILE,LOG) \ 1054 switch (LOG) \ 1055 { \ 1056 case 0: \ 1057 break; \ 1058 case 1: \ 1059 fprintf (FILE, "\t.even\n"); \ 1060 break; \ 1061 default: \ 1062 abort (); \ 1063 } 1064 1065 #define ASM_OUTPUT_SKIP(FILE,SIZE) \ 1066 fprintf (FILE, "\t.=.+ %#ho\n", (unsigned short)(SIZE)) 1067 1068 /* This says how to output an assembler line 1069 to define a global common symbol. */ 1070 1071 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \ 1072 ( fprintf ((FILE), ".globl "), \ 1073 assemble_name ((FILE), (NAME)), \ 1074 fprintf ((FILE), "\n"), \ 1075 assemble_name ((FILE), (NAME)), \ 1076 fprintf ((FILE), ": .=.+ %#ho\n", (unsigned short)(ROUNDED)) \ 1077 ) 1078 1079 /* This says how to output an assembler line 1080 to define a local common symbol. */ 1081 1082 #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \ 1083 ( assemble_name ((FILE), (NAME)), \ 1084 fprintf ((FILE), ":\t.=.+ %#ho\n", (unsigned short)(ROUNDED))) 1085 1086 /* Print operand X (an rtx) in assembler syntax to file FILE. 1087 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. 1088 For `%' followed by punctuation, CODE is the punctuation and X is null. 1089 1090 */ 1091 1092 1093 #define PRINT_OPERAND(FILE, X, CODE) \ 1094 { if (CODE == '#') fprintf (FILE, "#"); \ 1095 else if (GET_CODE (X) == REG) \ 1096 fprintf (FILE, "%s", reg_names[REGNO (X)]); \ 1097 else if (GET_CODE (X) == MEM) \ 1098 output_address (XEXP (X, 0)); \ 1099 else if (GET_CODE (X) == CONST_DOUBLE && GET_MODE (X) != SImode) \ 1100 { char buf[30]; \ 1101 real_to_decimal (buf, CONST_DOUBLE_REAL_VALUE (X), sizeof (buf), 0, 1); \ 1102 fprintf (FILE, "$0F%s", buf); } \ 1103 else { putc ('$', FILE); output_addr_const_pdp11 (FILE, X); }} 1104 1105 /* Print a memory address as an operand to reference that memory location. */ 1106 1107 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \ 1108 print_operand_address (FILE, ADDR) 1109 1110 #define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \ 1111 ( \ 1112 fprintf (FILE, "\tmov %s, -(sp)\n", reg_names[REGNO]) \ 1113 ) 1114 1115 #define ASM_OUTPUT_REG_POP(FILE,REGNO) \ 1116 ( \ 1117 fprintf (FILE, "\tmov (sp)+, %s\n", reg_names[REGNO]) \ 1118 ) 1119 1120 /* trampoline - how should i do it in separate i+d ? 1121 have some allocate_trampoline magic??? 1122 1123 the following should work for shared I/D: */ 1124 1125 /* lets see whether this works as trampoline: 1126 MV #STATIC, $4 0x940Y 0x0000 <- STATIC; Y = STATIC_CHAIN_REGNUM 1127 JMP FUNCTION 0x0058 0x0000 <- FUNCTION 1128 */ 1129 1130 #define TRAMPOLINE_TEMPLATE(FILE) \ 1131 { \ 1132 if (TARGET_SPLIT) \ 1133 abort(); \ 1134 \ 1135 assemble_aligned_integer (2, GEN_INT (0x9400+STATIC_CHAIN_REGNUM)); \ 1136 assemble_aligned_integer (2, const0_rtx); \ 1137 assemble_aligned_integer (2, GEN_INT(0x0058)); \ 1138 assemble_aligned_integer (2, const0_rtx); \ 1139 } 1140 1141 #define TRAMPOLINE_SIZE 8 1142 #define TRAMPOLINE_ALIGNMENT 16 1143 1144 /* Emit RTL insns to initialize the variable parts of a trampoline. 1145 FNADDR is an RTX for the address of the function's pure code. 1146 CXT is an RTX for the static chain value for the function. */ 1147 1148 #define INITIALIZE_TRAMPOLINE(TRAMP,FNADDR,CXT) \ 1149 { \ 1150 if (TARGET_SPLIT) \ 1151 abort(); \ 1152 \ 1153 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (TRAMP, 2)), CXT); \ 1154 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (TRAMP, 6)), FNADDR); \ 1155 } 1156 1157 1158 /* Some machines may desire to change what optimizations are 1159 performed for various optimization levels. This macro, if 1160 defined, is executed once just after the optimization level is 1161 determined and before the remainder of the command options have 1162 been parsed. Values set in this macro are used as the default 1163 values for the other command line options. 1164 1165 LEVEL is the optimization level specified; 2 if -O2 is 1166 specified, 1 if -O is specified, and 0 if neither is specified. */ 1167 1168 #define OPTIMIZATION_OPTIONS(LEVEL,SIZE) \ 1169 { \ 1170 if (LEVEL >= 3) \ 1171 { \ 1172 if (! SIZE) \ 1173 flag_inline_functions = 1; \ 1174 flag_omit_frame_pointer = 1; \ 1175 /* flag_unroll_loops = 1; */ \ 1176 } \ 1177 } 1178 1179 /* there is no point in avoiding branches on a pdp, 1180 since branches are really cheap - I just want to find out 1181 how much difference the BRANCH_COST macro makes in code */ 1182 #define BRANCH_COST (TARGET_BRANCH_CHEAP ? 0 : 1) 1183 1184 1185 #define COMPARE_FLAG_MODE HImode 1186