1/*
2 * regs.S -- standard MIPS register names.
3 *
4 * Copyright (c) 1995 Cygnus Support
5 *
6 * The authors hereby grant permission to use, copy, modify, distribute,
7 * and license this software and its documentation for any purpose, provided
8 * that existing copyright notices are retained in all copies and that this
9 * notice is included verbatim in any distributions. No written agreement,
10 * license, or royalty fee is required for any of the authorized uses.
11 * Modifications to this software may be copyrighted by their authors
12 * and need not follow the licensing terms described here, provided that
13 * the new terms are clearly indicated on the first page of each file where
14 * they apply.
15 */
16
17/* Standard MIPS register names: */
18#define zero	$0
19#define z0	$0
20#define v0	$2
21#define v1	$3
22#define a0	$4
23#define a1	$5
24#define a2	$6
25#define a3	$7
26#define t0	$8
27#define t1	$9
28#define t2	$10
29#define t3	$11
30#define t4	$12
31#define t5	$13
32#define t6	$14
33#define t7	$15
34#define s0	$16
35#define s1	$17
36#define s2	$18
37#define s3	$19
38#define s4	$20
39#define s5	$21
40#define s6	$22
41#define s7	$23
42#define t8	$24
43#define t9	$25
44#define k0	$26	/* kernel private register 0 */
45#define k1	$27	/* kernel private register 1 */
46#define gp	$28	/* global data pointer */
47#define sp 	$29	/* stack-pointer */
48#define fp	$30	/* frame-pointer */
49#define ra	$31	/* return address */
50#define pc	$pc	/* pc, used on mips16 */
51
52#define fp0	$f0
53#define fp1	$f1
54
55/* Useful memory constants: */
56#define K0BASE		0x80000000
57#ifndef __mips64
58#define K1BASE		0xA0000000
59#define K0BASE_ADDR	((char *)K0BASE)
60#define K1BASE_ADDR	((char *)K1BASE)
61#else
62#define K1BASE		0xFFFFFFFFA0000000LL
63#define K0BASE_ADDR	((char *)0xFFFFFFFF80000000LL)
64#define K1BASE_ADDR	((char *)K1BASE)
65#endif
66
67#define PHYS_TO_K1(a)   ((unsigned)(a) | K1BASE)
68
69/* Standard Co-Processor 0 register numbers:
70#define C0_COUNT	$9		/* Count Register */
71#define C0_SR		$12		/* Status Register */
72#define C0_CAUSE	$13		/* last exception description */
73#define C0_EPC		$14		/* Exception error address */
74#define C0_PRID		$15		/* Processor Revision ID */
75#define C0_CONFIG	$16		/* CPU configuration */
76
77/* Standard Processor Revision ID Register field offsets */
78#define PR_IMP	8
79
80/* Standard Config Register field offsets */
81#define CR_DB	4
82#define CR_IB	5
83#define CR_DC	6	/* NOTE v4121 semantics != 43,5xxx semantics */
84#define CR_IC	9	/* NOTE v4121 semantics != 43,5xxx semantics */
85#define CR_SC	17
86#define CR_SS	20
87#define CR_SB	22
88
89
90/* Standard Status Register bitmasks: */
91#define SR_CU1		0x20000000	/* Mark CP1 as usable */
92#define SR_FR		0x04000000	/* Enable MIPS III FP registers */
93#define SR_BEV		0x00400000	/* Controls location of exception vectors */
94#define SR_PE		0x00100000	/* Mark soft reset (clear parity error) */
95
96#define SR_KX		0x00000080	/* Kernel extended addressing enabled */
97#define SR_SX		0x00000040	/* Supervisor extended addressing enabled */
98#define SR_UX		0x00000020	/* User extended addressing enabled */
99
100/* Standard (R4000) cache operations. Taken from "MIPS R4000
101   Microprocessor User's Manual" 2nd edition: */
102
103#define CACHE_I		(0)	/* primary instruction */
104#define CACHE_D		(1)	/* primary data */
105#define CACHE_SI	(2)	/* secondary instruction */
106#define CACHE_SD	(3)	/* secondary data (or combined instruction/data) */
107
108#define INDEX_INVALIDATE		(0)	/* also encodes WRITEBACK if CACHE_D or CACHE_SD */
109#define INDEX_LOAD_TAG			(1)
110#define INDEX_STORE_TAG			(2)
111#define CREATE_DIRTY_EXCLUSIVE		(3)	/* CACHE_D and CACHE_SD only */
112#define HIT_INVALIDATE			(4)
113#define CACHE_FILL			(5)	/* CACHE_I only */
114#define HIT_WRITEBACK_INVALIDATE	(5)	/* CACHE_D and CACHE_SD only */
115#define HIT_WRITEBACK			(6)	/* CACHE_I, CACHE_D and CACHE_SD only */
116#define HIT_SET_VIRTUAL			(7)	/* CACHE_SI and CACHE_SD only */
117
118#define BUILD_CACHE_OP(o,c)		(((o) << 2) | (c))
119
120/* Individual cache operations: */
121#define INDEX_INVALIDATE_I		BUILD_CACHE_OP(INDEX_INVALIDATE,CACHE_I)
122#define INDEX_WRITEBACK_INVALIDATE_D	BUILD_CACHE_OP(INDEX_INVALIDATE,CACHE_D)
123#define INDEX_INVALIDATE_SI             BUILD_CACHE_OP(INDEX_INVALIDATE,CACHE_SI)
124#define INDEX_WRITEBACK_INVALIDATE_SD	BUILD_CACHE_OP(INDEX_INVALIDATE,CACHE_SD)
125
126#define INDEX_LOAD_TAG_I		BUILD_CACHE_OP(INDEX_LOAD_TAG,CACHE_I)
127#define INDEX_LOAD_TAG_D                BUILD_CACHE_OP(INDEX_LOAD_TAG,CACHE_D)
128#define INDEX_LOAD_TAG_SI               BUILD_CACHE_OP(INDEX_LOAD_TAG,CACHE_SI)
129#define INDEX_LOAD_TAG_SD               BUILD_CACHE_OP(INDEX_LOAD_TAG,CACHE_SD)
130
131#define INDEX_STORE_TAG_I              	BUILD_CACHE_OP(INDEX_STORE_TAG,CACHE_I)
132#define INDEX_STORE_TAG_D               BUILD_CACHE_OP(INDEX_STORE_TAG,CACHE_D)
133#define INDEX_STORE_TAG_SI              BUILD_CACHE_OP(INDEX_STORE_TAG,CACHE_SI)
134#define INDEX_STORE_TAG_SD              BUILD_CACHE_OP(INDEX_STORE_TAG,CACHE_SD)
135
136#define CREATE_DIRTY_EXCLUSIVE_D        BUILD_CACHE_OP(CREATE_DIRTY_EXCLUSIVE,CACHE_D)
137#define CREATE_DIRTY_EXCLUSIVE_SD       BUILD_CACHE_OP(CREATE_DIRTY_EXCLUSIVE,CACHE_SD)
138
139#define HIT_INVALIDATE_I                BUILD_CACHE_OP(HIT_INVALIDATE,CACHE_I)
140#define HIT_INVALIDATE_D                BUILD_CACHE_OP(HIT_INVALIDATE,CACHE_D)
141#define HIT_INVALIDATE_SI               BUILD_CACHE_OP(HIT_INVALIDATE,CACHE_SI)
142#define HIT_INVALIDATE_SD               BUILD_CACHE_OP(HIT_INVALIDATE,CACHE_SD)
143
144#define CACHE_FILL_I                    BUILD_CACHE_OP(CACHE_FILL,CACHE_I)
145#define HIT_WRITEBACK_INVALIDATE_D      BUILD_CACHE_OP(HIT_WRITEBACK_INVALIDATE,CACHE_D)
146#define HIT_WRITEBACK_INVALIDATE_SD     BUILD_CACHE_OP(HIT_WRITEBACK_INVALIDATE,CACHE_SD)
147
148#define HIT_WRITEBACK_I                 BUILD_CACHE_OP(HIT_WRITEBACK,CACHE_I)
149#define HIT_WRITEBACK_D                 BUILD_CACHE_OP(HIT_WRITEBACK,CACHE_D)
150#define HIT_WRITEBACK_SD                BUILD_CACHE_OP(HIT_WRITEBACK,CACHE_SD)
151
152#define HIT_SET_VIRTUAL_SI		BUILD_CACHE_OP(HIT_SET_VIRTUAL,CACHE_SI)
153#define HIT_SET_VIRTUAL_SD              BUILD_CACHE_OP(HIT_SET_VIRTUAL,CACHE_SD)
154
155/*> EOF regs.S <*/
156