1 /* CPU data header for fr30. 2 3 THIS FILE IS MACHINE GENERATED WITH CGEN. 4 5 Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc. 6 7 This file is part of the GNU Binutils and/or GDB, the GNU debugger. 8 9 This program is free software; you can redistribute it and/or modify 10 it under the terms of the GNU General Public License as published by 11 the Free Software Foundation; either version 2, or (at your option) 12 any later version. 13 14 This program is distributed in the hope that it will be useful, 15 but WITHOUT ANY WARRANTY; without even the implied warranty of 16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 GNU General Public License for more details. 18 19 You should have received a copy of the GNU General Public License along 20 with this program; if not, write to the Free Software Foundation, Inc., 21 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 22 23 */ 24 25 #ifndef FR30_CPU_H 26 #define FR30_CPU_H 27 28 #define CGEN_ARCH fr30 29 30 /* Given symbol S, return fr30_cgen_<S>. */ 31 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) 32 #define CGEN_SYM(s) fr30##_cgen_##s 33 #else 34 #define CGEN_SYM(s) fr30/**/_cgen_/**/s 35 #endif 36 37 38 /* Selected cpu families. */ 39 #define HAVE_CPU_FR30BF 40 41 #define CGEN_INSN_LSB0_P 0 42 43 /* Minimum size of any insn (in bytes). */ 44 #define CGEN_MIN_INSN_SIZE 2 45 46 /* Maximum size of any insn (in bytes). */ 47 #define CGEN_MAX_INSN_SIZE 6 48 49 #define CGEN_INT_INSN_P 0 50 51 /* Maximum number of syntax elements in an instruction. */ 52 #define CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS 15 53 54 /* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands. 55 e.g. In "b,a foo" the ",a" is an operand. If mnemonics have operands 56 we can't hash on everything up to the space. */ 57 #define CGEN_MNEMONIC_OPERANDS 58 59 /* Maximum number of fields in an instruction. */ 60 #define CGEN_ACTUAL_MAX_IFMT_OPERANDS 7 61 62 /* Enums. */ 63 64 /* Enum declaration for insn op1 enums. */ 65 typedef enum insn_op1 { 66 OP1_0, OP1_1, OP1_2, OP1_3 67 , OP1_4, OP1_5, OP1_6, OP1_7 68 , OP1_8, OP1_9, OP1_A, OP1_B 69 , OP1_C, OP1_D, OP1_E, OP1_F 70 } INSN_OP1; 71 72 /* Enum declaration for insn op2 enums. */ 73 typedef enum insn_op2 { 74 OP2_0, OP2_1, OP2_2, OP2_3 75 , OP2_4, OP2_5, OP2_6, OP2_7 76 , OP2_8, OP2_9, OP2_A, OP2_B 77 , OP2_C, OP2_D, OP2_E, OP2_F 78 } INSN_OP2; 79 80 /* Enum declaration for insn op3 enums. */ 81 typedef enum insn_op3 { 82 OP3_0, OP3_1, OP3_2, OP3_3 83 , OP3_4, OP3_5, OP3_6, OP3_7 84 , OP3_8, OP3_9, OP3_A, OP3_B 85 , OP3_C, OP3_D, OP3_E, OP3_F 86 } INSN_OP3; 87 88 /* Enum declaration for insn op4 enums. */ 89 typedef enum insn_op4 { 90 OP4_0 91 } INSN_OP4; 92 93 /* Enum declaration for insn op5 enums. */ 94 typedef enum insn_op5 { 95 OP5_0, OP5_1 96 } INSN_OP5; 97 98 /* Enum declaration for insn cc enums. */ 99 typedef enum insn_cc { 100 CC_RA, CC_NO, CC_EQ, CC_NE 101 , CC_C, CC_NC, CC_N, CC_P 102 , CC_V, CC_NV, CC_LT, CC_GE 103 , CC_LE, CC_GT, CC_LS, CC_HI 104 } INSN_CC; 105 106 /* Enum declaration for . */ 107 typedef enum gr_names { 108 H_GR_R0 = 0, H_GR_R1 = 1, H_GR_R2 = 2, H_GR_R3 = 3 109 , H_GR_R4 = 4, H_GR_R5 = 5, H_GR_R6 = 6, H_GR_R7 = 7 110 , H_GR_R8 = 8, H_GR_R9 = 9, H_GR_R10 = 10, H_GR_R11 = 11 111 , H_GR_R12 = 12, H_GR_R13 = 13, H_GR_R14 = 14, H_GR_R15 = 15 112 , H_GR_AC = 13, H_GR_FP = 14, H_GR_SP = 15 113 } GR_NAMES; 114 115 /* Enum declaration for . */ 116 typedef enum cr_names { 117 H_CR_CR0, H_CR_CR1, H_CR_CR2, H_CR_CR3 118 , H_CR_CR4, H_CR_CR5, H_CR_CR6, H_CR_CR7 119 , H_CR_CR8, H_CR_CR9, H_CR_CR10, H_CR_CR11 120 , H_CR_CR12, H_CR_CR13, H_CR_CR14, H_CR_CR15 121 } CR_NAMES; 122 123 /* Enum declaration for . */ 124 typedef enum dr_names { 125 H_DR_TBR, H_DR_RP, H_DR_SSP, H_DR_USP 126 , H_DR_MDH, H_DR_MDL 127 } DR_NAMES; 128 129 /* Attributes. */ 130 131 /* Enum declaration for machine type selection. */ 132 typedef enum mach_attr { 133 MACH_BASE, MACH_FR30, MACH_MAX 134 } MACH_ATTR; 135 136 /* Enum declaration for instruction set selection. */ 137 typedef enum isa_attr { 138 ISA_FR30, ISA_MAX 139 } ISA_ATTR; 140 141 /* Number of architecture variants. */ 142 #define MAX_ISAS 1 143 #define MAX_MACHS ((int) MACH_MAX) 144 145 /* Ifield support. */ 146 147 extern const struct cgen_ifld fr30_cgen_ifld_table[]; 148 149 /* Ifield attribute indices. */ 150 151 /* Enum declaration for cgen_ifld attrs. */ 152 typedef enum cgen_ifld_attr { 153 CGEN_IFLD_VIRTUAL, CGEN_IFLD_PCREL_ADDR, CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED 154 , CGEN_IFLD_SIGN_OPT, CGEN_IFLD_SIGNED, CGEN_IFLD_END_BOOLS, CGEN_IFLD_START_NBOOLS = 31 155 , CGEN_IFLD_MACH, CGEN_IFLD_END_NBOOLS 156 } CGEN_IFLD_ATTR; 157 158 /* Number of non-boolean elements in cgen_ifld_attr. */ 159 #define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1) 160 161 /* Enum declaration for fr30 ifield types. */ 162 typedef enum ifield_type { 163 FR30_F_NIL, FR30_F_ANYOF, FR30_F_OP1, FR30_F_OP2 164 , FR30_F_OP3, FR30_F_OP4, FR30_F_OP5, FR30_F_CC 165 , FR30_F_CCC, FR30_F_RJ, FR30_F_RI, FR30_F_RS1 166 , FR30_F_RS2, FR30_F_RJC, FR30_F_RIC, FR30_F_CRJ 167 , FR30_F_CRI, FR30_F_U4, FR30_F_U4C, FR30_F_I4 168 , FR30_F_M4, FR30_F_U8, FR30_F_I8, FR30_F_I20_4 169 , FR30_F_I20_16, FR30_F_I20, FR30_F_I32, FR30_F_UDISP6 170 , FR30_F_DISP8, FR30_F_DISP9, FR30_F_DISP10, FR30_F_S10 171 , FR30_F_U10, FR30_F_REL9, FR30_F_DIR8, FR30_F_DIR9 172 , FR30_F_DIR10, FR30_F_REL12, FR30_F_REGLIST_HI_ST, FR30_F_REGLIST_LOW_ST 173 , FR30_F_REGLIST_HI_LD, FR30_F_REGLIST_LOW_LD, FR30_F_MAX 174 } IFIELD_TYPE; 175 176 #define MAX_IFLD ((int) FR30_F_MAX) 177 178 /* Hardware attribute indices. */ 179 180 /* Enum declaration for cgen_hw attrs. */ 181 typedef enum cgen_hw_attr { 182 CGEN_HW_VIRTUAL, CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE 183 , CGEN_HW_END_BOOLS, CGEN_HW_START_NBOOLS = 31, CGEN_HW_MACH, CGEN_HW_END_NBOOLS 184 } CGEN_HW_ATTR; 185 186 /* Number of non-boolean elements in cgen_hw_attr. */ 187 #define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1) 188 189 /* Enum declaration for fr30 hardware types. */ 190 typedef enum cgen_hw_type { 191 HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR 192 , HW_H_IADDR, HW_H_PC, HW_H_GR, HW_H_CR 193 , HW_H_DR, HW_H_PS, HW_H_R13, HW_H_R14 194 , HW_H_R15, HW_H_NBIT, HW_H_ZBIT, HW_H_VBIT 195 , HW_H_CBIT, HW_H_IBIT, HW_H_SBIT, HW_H_TBIT 196 , HW_H_D0BIT, HW_H_D1BIT, HW_H_CCR, HW_H_SCR 197 , HW_H_ILM, HW_MAX 198 } CGEN_HW_TYPE; 199 200 #define MAX_HW ((int) HW_MAX) 201 202 /* Operand attribute indices. */ 203 204 /* Enum declaration for cgen_operand attrs. */ 205 typedef enum cgen_operand_attr { 206 CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT 207 , CGEN_OPERAND_SIGNED, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY 208 , CGEN_OPERAND_HASH_PREFIX, CGEN_OPERAND_END_BOOLS, CGEN_OPERAND_START_NBOOLS = 31, CGEN_OPERAND_MACH 209 , CGEN_OPERAND_END_NBOOLS 210 } CGEN_OPERAND_ATTR; 211 212 /* Number of non-boolean elements in cgen_operand_attr. */ 213 #define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1) 214 215 /* Enum declaration for fr30 operand types. */ 216 typedef enum cgen_operand_type { 217 FR30_OPERAND_PC, FR30_OPERAND_RI, FR30_OPERAND_RJ, FR30_OPERAND_RIC 218 , FR30_OPERAND_RJC, FR30_OPERAND_CRI, FR30_OPERAND_CRJ, FR30_OPERAND_RS1 219 , FR30_OPERAND_RS2, FR30_OPERAND_R13, FR30_OPERAND_R14, FR30_OPERAND_R15 220 , FR30_OPERAND_PS, FR30_OPERAND_U4, FR30_OPERAND_U4C, FR30_OPERAND_U8 221 , FR30_OPERAND_I8, FR30_OPERAND_UDISP6, FR30_OPERAND_DISP8, FR30_OPERAND_DISP9 222 , FR30_OPERAND_DISP10, FR30_OPERAND_S10, FR30_OPERAND_U10, FR30_OPERAND_I32 223 , FR30_OPERAND_M4, FR30_OPERAND_I20, FR30_OPERAND_DIR8, FR30_OPERAND_DIR9 224 , FR30_OPERAND_DIR10, FR30_OPERAND_LABEL9, FR30_OPERAND_LABEL12, FR30_OPERAND_REGLIST_LOW_LD 225 , FR30_OPERAND_REGLIST_HI_LD, FR30_OPERAND_REGLIST_LOW_ST, FR30_OPERAND_REGLIST_HI_ST, FR30_OPERAND_CC 226 , FR30_OPERAND_CCC, FR30_OPERAND_NBIT, FR30_OPERAND_VBIT, FR30_OPERAND_ZBIT 227 , FR30_OPERAND_CBIT, FR30_OPERAND_IBIT, FR30_OPERAND_SBIT, FR30_OPERAND_TBIT 228 , FR30_OPERAND_D0BIT, FR30_OPERAND_D1BIT, FR30_OPERAND_CCR, FR30_OPERAND_SCR 229 , FR30_OPERAND_ILM, FR30_OPERAND_MAX 230 } CGEN_OPERAND_TYPE; 231 232 /* Number of operands types. */ 233 #define MAX_OPERANDS 49 234 235 /* Maximum number of operands referenced by any insn. */ 236 #define MAX_OPERAND_INSTANCES 8 237 238 /* Insn attribute indices. */ 239 240 /* Enum declaration for cgen_insn attrs. */ 241 typedef enum cgen_insn_attr { 242 CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI 243 , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAXED 244 , CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_NOT_IN_DELAY_SLOT, CGEN_INSN_END_BOOLS 245 , CGEN_INSN_START_NBOOLS = 31, CGEN_INSN_MACH, CGEN_INSN_END_NBOOLS 246 } CGEN_INSN_ATTR; 247 248 /* Number of non-boolean elements in cgen_insn_attr. */ 249 #define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1) 250 251 /* cgen.h uses things we just defined. */ 252 #include "opcode/cgen.h" 253 254 /* Attributes. */ 255 extern const CGEN_ATTR_TABLE fr30_cgen_hardware_attr_table[]; 256 extern const CGEN_ATTR_TABLE fr30_cgen_ifield_attr_table[]; 257 extern const CGEN_ATTR_TABLE fr30_cgen_operand_attr_table[]; 258 extern const CGEN_ATTR_TABLE fr30_cgen_insn_attr_table[]; 259 260 /* Hardware decls. */ 261 262 extern CGEN_KEYWORD fr30_cgen_opval_gr_names; 263 extern CGEN_KEYWORD fr30_cgen_opval_cr_names; 264 extern CGEN_KEYWORD fr30_cgen_opval_dr_names; 265 extern CGEN_KEYWORD fr30_cgen_opval_h_ps; 266 extern CGEN_KEYWORD fr30_cgen_opval_h_r13; 267 extern CGEN_KEYWORD fr30_cgen_opval_h_r14; 268 extern CGEN_KEYWORD fr30_cgen_opval_h_r15; 269 270 271 272 273 #endif /* FR30_CPU_H */ 274