1 /* Definitions of Tensilica's Xtensa target machine for GNU compiler. 2 Copyright 2001,2002,2003,2004 Free Software Foundation, Inc. 3 Contributed by Bob Wilson (bwilson@tensilica.com) at Tensilica. 4 5 This file is part of GCC. 6 7 GCC is free software; you can redistribute it and/or modify it under 8 the terms of the GNU General Public License as published by the Free 9 Software Foundation; either version 2, or (at your option) any later 10 version. 11 12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY 13 WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 15 for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with GCC; see the file COPYING. If not, write to the Free 19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA 20 02111-1307, USA. */ 21 22 /* Get Xtensa configuration settings */ 23 #include "xtensa-config.h" 24 25 /* Standard GCC variables that we reference. */ 26 extern int current_function_calls_alloca; 27 extern int target_flags; 28 extern int optimize; 29 30 /* External variables defined in xtensa.c. */ 31 32 /* comparison type */ 33 enum cmp_type { 34 CMP_SI, /* four byte integers */ 35 CMP_DI, /* eight byte integers */ 36 CMP_SF, /* single precision floats */ 37 CMP_DF, /* double precision floats */ 38 CMP_MAX /* max comparison type */ 39 }; 40 41 extern struct rtx_def * branch_cmp[2]; /* operands for compare */ 42 extern enum cmp_type branch_type; /* what type of branch to use */ 43 extern unsigned xtensa_current_frame_size; 44 45 /* Masks for the -m switches */ 46 #define MASK_NO_FUSED_MADD 0x00000001 /* avoid f-p mul/add */ 47 #define MASK_CONST16 0x00000002 /* use CONST16 instruction */ 48 49 /* Macros used in the machine description to select various Xtensa 50 configuration options. */ 51 #define TARGET_BIG_ENDIAN XCHAL_HAVE_BE 52 #define TARGET_DENSITY XCHAL_HAVE_DENSITY 53 #define TARGET_MAC16 XCHAL_HAVE_MAC16 54 #define TARGET_MUL16 XCHAL_HAVE_MUL16 55 #define TARGET_MUL32 XCHAL_HAVE_MUL32 56 #define TARGET_DIV32 XCHAL_HAVE_DIV32 57 #define TARGET_NSA XCHAL_HAVE_NSA 58 #define TARGET_MINMAX XCHAL_HAVE_MINMAX 59 #define TARGET_SEXT XCHAL_HAVE_SEXT 60 #define TARGET_BOOLEANS XCHAL_HAVE_BOOLEANS 61 #define TARGET_HARD_FLOAT XCHAL_HAVE_FP 62 #define TARGET_HARD_FLOAT_DIV XCHAL_HAVE_FP_DIV 63 #define TARGET_HARD_FLOAT_RECIP XCHAL_HAVE_FP_RECIP 64 #define TARGET_HARD_FLOAT_SQRT XCHAL_HAVE_FP_SQRT 65 #define TARGET_HARD_FLOAT_RSQRT XCHAL_HAVE_FP_RSQRT 66 #define TARGET_ABS XCHAL_HAVE_ABS 67 #define TARGET_ADDX XCHAL_HAVE_ADDX 68 69 /* Macros controlled by command-line options. */ 70 #define TARGET_NO_FUSED_MADD (target_flags & MASK_NO_FUSED_MADD) 71 #define TARGET_CONST16 (target_flags & MASK_CONST16) 72 73 #define TARGET_DEFAULT ( \ 74 (XCHAL_HAVE_L32R ? 0 : MASK_CONST16)) 75 76 #define TARGET_SWITCHES \ 77 { \ 78 {"const16", MASK_CONST16, \ 79 N_("Use CONST16 instruction to load constants")}, \ 80 {"no-const16", -MASK_CONST16, \ 81 N_("Use PC-relative L32R instruction to load constants")}, \ 82 {"no-fused-madd", MASK_NO_FUSED_MADD, \ 83 N_("Disable fused multiply/add and multiply/subtract FP instructions")}, \ 84 {"fused-madd", -MASK_NO_FUSED_MADD, \ 85 N_("Enable fused multiply/add and multiply/subtract FP instructions")}, \ 86 {"text-section-literals", 0, \ 87 N_("Intersperse literal pools with code in the text section")}, \ 88 {"no-text-section-literals", 0, \ 89 N_("Put literal pools in a separate literal section")}, \ 90 {"target-align", 0, \ 91 N_("Automatically align branch targets to reduce branch penalties")}, \ 92 {"no-target-align", 0, \ 93 N_("Do not automatically align branch targets")}, \ 94 {"longcalls", 0, \ 95 N_("Use indirect CALLXn instructions for large programs")}, \ 96 {"no-longcalls", 0, \ 97 N_("Use direct CALLn instructions for fast calls")}, \ 98 {"", TARGET_DEFAULT, 0} \ 99 } 100 101 102 #define OVERRIDE_OPTIONS override_options () 103 104 /* Target CPU builtins. */ 105 #define TARGET_CPU_CPP_BUILTINS() \ 106 do { \ 107 builtin_assert ("cpu=xtensa"); \ 108 builtin_assert ("machine=xtensa"); \ 109 builtin_define ("__xtensa__"); \ 110 builtin_define ("__XTENSA__"); \ 111 builtin_define (TARGET_BIG_ENDIAN ? "__XTENSA_EB__" : "__XTENSA_EL__"); \ 112 if (!TARGET_HARD_FLOAT) \ 113 builtin_define ("__XTENSA_SOFT_FLOAT__"); \ 114 if (flag_pic) \ 115 { \ 116 builtin_define ("__PIC__"); \ 117 builtin_define ("__pic__"); \ 118 } \ 119 } while (0) 120 121 #define CPP_SPEC " %(subtarget_cpp_spec) " 122 123 #ifndef SUBTARGET_CPP_SPEC 124 #define SUBTARGET_CPP_SPEC "" 125 #endif 126 127 #define EXTRA_SPECS \ 128 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, 129 130 #ifdef __XTENSA_EB__ 131 #define LIBGCC2_WORDS_BIG_ENDIAN 1 132 #else 133 #define LIBGCC2_WORDS_BIG_ENDIAN 0 134 #endif 135 136 /* Show we can debug even without a frame pointer. */ 137 #define CAN_DEBUG_WITHOUT_FP 138 139 140 /* Target machine storage layout */ 141 142 /* Define this if most significant bit is lowest numbered 143 in instructions that operate on numbered bit-fields. */ 144 #define BITS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0) 145 146 /* Define this if most significant byte of a word is the lowest numbered. */ 147 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0) 148 149 /* Define this if most significant word of a multiword number is the lowest. */ 150 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0) 151 152 #define MAX_BITS_PER_WORD 32 153 154 /* Width of a word, in units (bytes). */ 155 #define UNITS_PER_WORD 4 156 #define MIN_UNITS_PER_WORD 4 157 158 /* Width of a floating point register. */ 159 #define UNITS_PER_FPREG 4 160 161 /* Size in bits of various types on the target machine. */ 162 #define INT_TYPE_SIZE 32 163 #define SHORT_TYPE_SIZE 16 164 #define LONG_TYPE_SIZE 32 165 #define MAX_LONG_TYPE_SIZE 32 166 #define LONG_LONG_TYPE_SIZE 64 167 #define FLOAT_TYPE_SIZE 32 168 #define DOUBLE_TYPE_SIZE 64 169 #define LONG_DOUBLE_TYPE_SIZE 64 170 171 /* Allocation boundary (in *bits*) for storing pointers in memory. */ 172 #define POINTER_BOUNDARY 32 173 174 /* Allocation boundary (in *bits*) for storing arguments in argument list. */ 175 #define PARM_BOUNDARY 32 176 177 /* Allocation boundary (in *bits*) for the code of a function. */ 178 #define FUNCTION_BOUNDARY 32 179 180 /* Alignment of field after 'int : 0' in a structure. */ 181 #define EMPTY_FIELD_BOUNDARY 32 182 183 /* Every structure's size must be a multiple of this. */ 184 #define STRUCTURE_SIZE_BOUNDARY 8 185 186 /* There is no point aligning anything to a rounder boundary than this. */ 187 #define BIGGEST_ALIGNMENT 128 188 189 /* Set this nonzero if move instructions will actually fail to work 190 when given unaligned data. */ 191 #define STRICT_ALIGNMENT 1 192 193 /* Promote integer modes smaller than a word to SImode. Set UNSIGNEDP 194 for QImode, because there is no 8-bit load from memory with sign 195 extension. Otherwise, leave UNSIGNEDP alone, since Xtensa has 16-bit 196 loads both with and without sign extension. */ 197 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ 198 do { \ 199 if (GET_MODE_CLASS (MODE) == MODE_INT \ 200 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \ 201 { \ 202 if ((MODE) == QImode) \ 203 (UNSIGNEDP) = 1; \ 204 (MODE) = SImode; \ 205 } \ 206 } while (0) 207 208 /* The promotion described by `PROMOTE_MODE' should also be done for 209 outgoing function arguments. */ 210 #define PROMOTE_FUNCTION_ARGS 211 212 /* The promotion described by `PROMOTE_MODE' should also be done for 213 the return value of functions. Note: `FUNCTION_VALUE' must perform 214 the same promotions done by `PROMOTE_MODE'. */ 215 #define PROMOTE_FUNCTION_RETURN 216 217 /* Imitate the way many other C compilers handle alignment of 218 bitfields and the structures that contain them. */ 219 #define PCC_BITFIELD_TYPE_MATTERS 1 220 221 /* Align string constants and constructors to at least a word boundary. 222 The typical use of this macro is to increase alignment for string 223 constants to be word aligned so that 'strcpy' calls that copy 224 constants can be done inline. */ 225 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \ 226 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \ 227 && (ALIGN) < BITS_PER_WORD \ 228 ? BITS_PER_WORD \ 229 : (ALIGN)) 230 231 /* Align arrays, unions and records to at least a word boundary. 232 One use of this macro is to increase alignment of medium-size 233 data to make it all fit in fewer cache lines. Another is to 234 cause character arrays to be word-aligned so that 'strcpy' calls 235 that copy constants to character arrays can be done inline. */ 236 #undef DATA_ALIGNMENT 237 #define DATA_ALIGNMENT(TYPE, ALIGN) \ 238 ((((ALIGN) < BITS_PER_WORD) \ 239 && (TREE_CODE (TYPE) == ARRAY_TYPE \ 240 || TREE_CODE (TYPE) == UNION_TYPE \ 241 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN)) 242 243 /* An argument declared as 'char' or 'short' in a prototype should 244 actually be passed as an 'int'. */ 245 #define PROMOTE_PROTOTYPES 1 246 247 /* Operations between registers always perform the operation 248 on the full register even if a narrower mode is specified. */ 249 #define WORD_REGISTER_OPERATIONS 250 251 /* Xtensa loads are zero-extended by default. */ 252 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND 253 254 /* Standard register usage. */ 255 256 /* Number of actual hardware registers. 257 The hardware registers are assigned numbers for the compiler 258 from 0 to just below FIRST_PSEUDO_REGISTER. 259 All registers that the compiler knows about must be given numbers, 260 even those that are not normally considered general registers. 261 262 The fake frame pointer and argument pointer will never appear in 263 the generated code, since they will always be eliminated and replaced 264 by either the stack pointer or the hard frame pointer. 265 266 0 - 15 AR[0] - AR[15] 267 16 FRAME_POINTER (fake = initial sp) 268 17 ARG_POINTER (fake = initial sp + framesize) 269 18 BR[0] for floating-point CC 270 19 - 34 FR[0] - FR[15] 271 35 MAC16 accumulator */ 272 273 #define FIRST_PSEUDO_REGISTER 36 274 275 /* Return the stabs register number to use for REGNO. */ 276 #define DBX_REGISTER_NUMBER(REGNO) xtensa_dbx_register_number (REGNO) 277 278 /* 1 for registers that have pervasive standard uses 279 and are not available for the register allocator. */ 280 #define FIXED_REGISTERS \ 281 { \ 282 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 283 1, 1, 0, \ 284 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 285 0, \ 286 } 287 288 /* 1 for registers not available across function calls. 289 These must include the FIXED_REGISTERS and also any 290 registers that can be used without being saved. 291 The latter must include the registers where values are returned 292 and the register where structure-value addresses are passed. 293 Aside from that, you can include as many other registers as you like. */ 294 #define CALL_USED_REGISTERS \ 295 { \ 296 1, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, \ 297 1, 1, 1, \ 298 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 299 1, \ 300 } 301 302 /* For non-leaf procedures on Xtensa processors, the allocation order 303 is as specified below by REG_ALLOC_ORDER. For leaf procedures, we 304 want to use the lowest numbered registers first to minimize 305 register window overflows. However, local-alloc is not smart 306 enough to consider conflicts with incoming arguments. If an 307 incoming argument in a2 is live throughout the function and 308 local-alloc decides to use a2, then the incoming argument must 309 either be spilled or copied to another register. To get around 310 this, we define ORDER_REGS_FOR_LOCAL_ALLOC to redefine 311 reg_alloc_order for leaf functions such that lowest numbered 312 registers are used first with the exception that the incoming 313 argument registers are not used until after other register choices 314 have been exhausted. */ 315 316 #define REG_ALLOC_ORDER \ 317 { 8, 9, 10, 11, 12, 13, 14, 15, 7, 6, 5, 4, 3, 2, \ 318 18, \ 319 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, \ 320 0, 1, 16, 17, \ 321 35, \ 322 } 323 324 #define ORDER_REGS_FOR_LOCAL_ALLOC order_regs_for_local_alloc () 325 326 /* For Xtensa, the only point of this is to prevent GCC from otherwise 327 giving preference to call-used registers. To minimize window 328 overflows for the AR registers, we want to give preference to the 329 lower-numbered AR registers. For other register files, which are 330 not windowed, we still prefer call-used registers, if there are any. */ 331 extern const char xtensa_leaf_regs[FIRST_PSEUDO_REGISTER]; 332 #define LEAF_REGISTERS xtensa_leaf_regs 333 334 /* For Xtensa, no remapping is necessary, but this macro must be 335 defined if LEAF_REGISTERS is defined. */ 336 #define LEAF_REG_REMAP(REGNO) (REGNO) 337 338 /* This must be declared if LEAF_REGISTERS is set. */ 339 extern int leaf_function; 340 341 /* Internal macros to classify a register number. */ 342 343 /* 16 address registers + fake registers */ 344 #define GP_REG_FIRST 0 345 #define GP_REG_LAST 17 346 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1) 347 348 /* Coprocessor registers */ 349 #define BR_REG_FIRST 18 350 #define BR_REG_LAST 18 351 #define BR_REG_NUM (BR_REG_LAST - BR_REG_FIRST + 1) 352 353 /* 16 floating-point registers */ 354 #define FP_REG_FIRST 19 355 #define FP_REG_LAST 34 356 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1) 357 358 /* MAC16 accumulator */ 359 #define ACC_REG_FIRST 35 360 #define ACC_REG_LAST 35 361 #define ACC_REG_NUM (ACC_REG_LAST - ACC_REG_FIRST + 1) 362 363 #define GP_REG_P(REGNO) ((unsigned) ((REGNO) - GP_REG_FIRST) < GP_REG_NUM) 364 #define BR_REG_P(REGNO) ((unsigned) ((REGNO) - BR_REG_FIRST) < BR_REG_NUM) 365 #define FP_REG_P(REGNO) ((unsigned) ((REGNO) - FP_REG_FIRST) < FP_REG_NUM) 366 #define ACC_REG_P(REGNO) ((unsigned) ((REGNO) - ACC_REG_FIRST) < ACC_REG_NUM) 367 368 /* Return number of consecutive hard regs needed starting at reg REGNO 369 to hold something of mode MODE. */ 370 #define HARD_REGNO_NREGS(REGNO, MODE) \ 371 (FP_REG_P (REGNO) ? \ 372 ((GET_MODE_SIZE (MODE) + UNITS_PER_FPREG - 1) / UNITS_PER_FPREG) : \ 373 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) 374 375 /* Value is 1 if hard register REGNO can hold a value of machine-mode 376 MODE. */ 377 extern char xtensa_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER]; 378 379 #define HARD_REGNO_MODE_OK(REGNO, MODE) \ 380 xtensa_hard_regno_mode_ok[(int) (MODE)][(REGNO)] 381 382 /* Value is 1 if it is a good idea to tie two pseudo registers 383 when one has mode MODE1 and one has mode MODE2. 384 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, 385 for any hard reg, then this must be 0 for correct output. */ 386 #define MODES_TIEABLE_P(MODE1, MODE2) \ 387 ((GET_MODE_CLASS (MODE1) == MODE_FLOAT || \ 388 GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \ 389 == (GET_MODE_CLASS (MODE2) == MODE_FLOAT || \ 390 GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT)) 391 392 /* Register to use for pushing function arguments. */ 393 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 1) 394 395 /* Base register for access to local variables of the function. */ 396 #define HARD_FRAME_POINTER_REGNUM (GP_REG_FIRST + 7) 397 398 /* The register number of the frame pointer register, which is used to 399 access automatic variables in the stack frame. For Xtensa, this 400 register never appears in the output. It is always eliminated to 401 either the stack pointer or the hard frame pointer. */ 402 #define FRAME_POINTER_REGNUM (GP_REG_FIRST + 16) 403 404 /* Value should be nonzero if functions must have frame pointers. 405 Zero means the frame pointer need not be set up (and parms 406 may be accessed via the stack pointer) in functions that seem suitable. 407 This is computed in 'reload', in reload1.c. */ 408 #define FRAME_POINTER_REQUIRED xtensa_frame_pointer_required () 409 410 /* Base register for access to arguments of the function. */ 411 #define ARG_POINTER_REGNUM (GP_REG_FIRST + 17) 412 413 /* If the static chain is passed in memory, these macros provide rtx 414 giving 'mem' expressions that denote where they are stored. 415 'STATIC_CHAIN' and 'STATIC_CHAIN_INCOMING' give the locations as 416 seen by the calling and called functions, respectively. */ 417 418 #define STATIC_CHAIN \ 419 gen_rtx_MEM (Pmode, plus_constant (stack_pointer_rtx, -5 * UNITS_PER_WORD)) 420 421 #define STATIC_CHAIN_INCOMING \ 422 gen_rtx_MEM (Pmode, plus_constant (arg_pointer_rtx, -5 * UNITS_PER_WORD)) 423 424 /* For now we don't try to use the full set of boolean registers. Without 425 software pipelining of FP operations, there's not much to gain and it's 426 a real pain to get them reloaded. */ 427 #define FPCC_REGNUM (BR_REG_FIRST + 0) 428 429 /* Pass structure value address as an "invisible" first argument. */ 430 #define STRUCT_VALUE 0 431 432 /* It is as good or better to call a constant function address than to 433 call an address kept in a register. */ 434 #define NO_FUNCTION_CSE 1 435 436 /* It is as good or better for a function to call itself with an 437 explicit address than to call an address kept in a register. */ 438 #define NO_RECURSIVE_FUNCTION_CSE 1 439 440 /* Xtensa processors have "register windows". GCC does not currently 441 take advantage of the possibility for variable-sized windows; instead, 442 we use a fixed window size of 8. */ 443 444 #define INCOMING_REGNO(OUT) \ 445 ((GP_REG_P (OUT) && \ 446 ((unsigned) ((OUT) - GP_REG_FIRST) >= WINDOW_SIZE)) ? \ 447 (OUT) - WINDOW_SIZE : (OUT)) 448 449 #define OUTGOING_REGNO(IN) \ 450 ((GP_REG_P (IN) && \ 451 ((unsigned) ((IN) - GP_REG_FIRST) < WINDOW_SIZE)) ? \ 452 (IN) + WINDOW_SIZE : (IN)) 453 454 455 /* Define the classes of registers for register constraints in the 456 machine description. */ 457 enum reg_class 458 { 459 NO_REGS, /* no registers in set */ 460 BR_REGS, /* coprocessor boolean registers */ 461 FP_REGS, /* floating point registers */ 462 ACC_REG, /* MAC16 accumulator */ 463 SP_REG, /* sp register (aka a1) */ 464 RL_REGS, /* preferred reload regs (not sp or fp) */ 465 GR_REGS, /* integer registers except sp */ 466 AR_REGS, /* all integer registers */ 467 ALL_REGS, /* all registers */ 468 LIM_REG_CLASSES /* max value + 1 */ 469 }; 470 471 #define N_REG_CLASSES (int) LIM_REG_CLASSES 472 473 #define GENERAL_REGS AR_REGS 474 475 /* An initializer containing the names of the register classes as C 476 string constants. These names are used in writing some of the 477 debugging dumps. */ 478 #define REG_CLASS_NAMES \ 479 { \ 480 "NO_REGS", \ 481 "BR_REGS", \ 482 "FP_REGS", \ 483 "ACC_REG", \ 484 "SP_REG", \ 485 "RL_REGS", \ 486 "GR_REGS", \ 487 "AR_REGS", \ 488 "ALL_REGS" \ 489 } 490 491 /* Contents of the register classes. The Nth integer specifies the 492 contents of class N. The way the integer MASK is interpreted is 493 that register R is in the class if 'MASK & (1 << R)' is 1. */ 494 #define REG_CLASS_CONTENTS \ 495 { \ 496 { 0x00000000, 0x00000000 }, /* no registers */ \ 497 { 0x00040000, 0x00000000 }, /* coprocessor boolean registers */ \ 498 { 0xfff80000, 0x00000007 }, /* floating-point registers */ \ 499 { 0x00000000, 0x00000008 }, /* MAC16 accumulator */ \ 500 { 0x00000002, 0x00000000 }, /* stack pointer register */ \ 501 { 0x0000ff7d, 0x00000000 }, /* preferred reload registers */ \ 502 { 0x0000fffd, 0x00000000 }, /* general-purpose registers */ \ 503 { 0x0003ffff, 0x00000000 }, /* integer registers */ \ 504 { 0xffffffff, 0x0000000f } /* all registers */ \ 505 } 506 507 /* A C expression whose value is a register class containing hard 508 register REGNO. In general there is more that one such class; 509 choose a class which is "minimal", meaning that no smaller class 510 also contains the register. */ 511 extern const enum reg_class xtensa_regno_to_class[FIRST_PSEUDO_REGISTER]; 512 513 #define REGNO_REG_CLASS(REGNO) xtensa_regno_to_class[ (REGNO) ] 514 515 /* Use the Xtensa AR register file for base registers. 516 No index registers. */ 517 #define BASE_REG_CLASS AR_REGS 518 #define INDEX_REG_CLASS NO_REGS 519 520 /* SMALL_REGISTER_CLASSES is required for Xtensa, because all of the 521 16 AR registers may be explicitly used in the RTL, as either 522 incoming or outgoing arguments. */ 523 #define SMALL_REGISTER_CLASSES 1 524 525 526 /* REGISTER AND CONSTANT CLASSES */ 527 528 /* Get reg_class from a letter such as appears in the machine 529 description. 530 531 Available letters: a-f,h,j-l,q,t-z,A-D,W,Y-Z 532 533 DEFINED REGISTER CLASSES: 534 535 'a' general-purpose registers except sp 536 'q' sp (aka a1) 537 'D' general-purpose registers (only if density option enabled) 538 'd' general-purpose registers, including sp (only if density enabled) 539 'A' MAC16 accumulator (only if MAC16 option enabled) 540 'B' general-purpose registers (only if sext instruction enabled) 541 'C' general-purpose registers (only if mul16 option enabled) 542 'W' general-purpose registers (only if const16 option enabled) 543 'b' coprocessor boolean registers 544 'f' floating-point registers 545 */ 546 547 extern enum reg_class xtensa_char_to_class[256]; 548 549 #define REG_CLASS_FROM_LETTER(C) xtensa_char_to_class[ (int) (C) ] 550 551 /* The letters I, J, K, L, M, N, O, and P in a register constraint 552 string can be used to stand for particular ranges of immediate 553 operands. This macro defines what the ranges are. C is the 554 letter, and VALUE is a constant value. Return 1 if VALUE is 555 in the range specified by C. 556 557 For Xtensa: 558 559 I = 12-bit signed immediate for movi 560 J = 8-bit signed immediate for addi 561 K = 4-bit value in (b4const U {0}) 562 L = 4-bit value in b4constu 563 M = 7-bit value in simm7 564 N = 8-bit unsigned immediate shifted left by 8 bits for addmi 565 O = 4-bit value in ai4const 566 P = valid immediate mask value for extui */ 567 568 #define CONST_OK_FOR_LETTER_P(VALUE, C) \ 569 ((C) == 'I' ? (xtensa_simm12b (VALUE)) \ 570 : (C) == 'J' ? (xtensa_simm8 (VALUE)) \ 571 : (C) == 'K' ? (((VALUE) == 0) || xtensa_b4const (VALUE)) \ 572 : (C) == 'L' ? (xtensa_b4constu (VALUE)) \ 573 : (C) == 'M' ? (xtensa_simm7 (VALUE)) \ 574 : (C) == 'N' ? (xtensa_simm8x256 (VALUE)) \ 575 : (C) == 'O' ? (xtensa_ai4const (VALUE)) \ 576 : (C) == 'P' ? (xtensa_mask_immediate (VALUE)) \ 577 : FALSE) 578 579 580 /* Similar, but for floating constants, and defining letters G and H. 581 Here VALUE is the CONST_DOUBLE rtx itself. */ 582 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) (0) 583 584 585 /* Other letters can be defined in a machine-dependent fashion to 586 stand for particular classes of registers or other arbitrary 587 operand types. 588 589 R = memory that can be accessed with a 4-bit unsigned offset 590 T = memory in a constant pool (addressable with a pc-relative load) 591 U = memory *NOT* in a constant pool 592 593 The offset range should not be checked here (except to distinguish 594 denser versions of the instructions for which more general versions 595 are available). Doing so leads to problems in reloading: an 596 argptr-relative address may become invalid when the phony argptr is 597 eliminated in favor of the stack pointer (the offset becomes too 598 large to fit in the instruction's immediate field); a reload is 599 generated to fix this but the RTL is not immediately updated; in 600 the meantime, the constraints are checked and none match. The 601 solution seems to be to simply skip the offset check here. The 602 address will be checked anyway because of the code in 603 GO_IF_LEGITIMATE_ADDRESS. */ 604 605 #define EXTRA_CONSTRAINT(OP, CODE) \ 606 ((GET_CODE (OP) != MEM) ? \ 607 ((CODE) >= 'R' && (CODE) <= 'U' \ 608 && reload_in_progress && GET_CODE (OP) == REG \ 609 && REGNO (OP) >= FIRST_PSEUDO_REGISTER) \ 610 : ((CODE) == 'R') ? smalloffset_mem_p (OP) \ 611 : ((CODE) == 'T') ? !TARGET_CONST16 && constantpool_mem_p (OP) \ 612 : ((CODE) == 'U') ? !constantpool_mem_p (OP) \ 613 : FALSE) 614 615 #define PREFERRED_RELOAD_CLASS(X, CLASS) \ 616 xtensa_preferred_reload_class (X, CLASS, 0) 617 618 #define PREFERRED_OUTPUT_RELOAD_CLASS(X, CLASS) \ 619 xtensa_preferred_reload_class (X, CLASS, 1) 620 621 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \ 622 xtensa_secondary_reload_class (CLASS, MODE, X, 0) 623 624 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \ 625 xtensa_secondary_reload_class (CLASS, MODE, X, 1) 626 627 /* Return the maximum number of consecutive registers 628 needed to represent mode MODE in a register of class CLASS. */ 629 #define CLASS_UNITS(mode, size) \ 630 ((GET_MODE_SIZE (mode) + (size) - 1) / (size)) 631 632 #define CLASS_MAX_NREGS(CLASS, MODE) \ 633 (CLASS_UNITS (MODE, UNITS_PER_WORD)) 634 635 636 /* Stack layout; function entry, exit and calling. */ 637 638 #define STACK_GROWS_DOWNWARD 639 640 /* Offset within stack frame to start allocating local variables at. */ 641 #define STARTING_FRAME_OFFSET \ 642 current_function_outgoing_args_size 643 644 /* The ARG_POINTER and FRAME_POINTER are not real Xtensa registers, so 645 they are eliminated to either the stack pointer or hard frame pointer. */ 646 #define ELIMINABLE_REGS \ 647 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 648 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ 649 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 650 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} 651 652 #define CAN_ELIMINATE(FROM, TO) 1 653 654 /* Specify the initial difference between the specified pair of registers. */ 655 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 656 do { \ 657 compute_frame_size (get_frame_size ()); \ 658 if ((FROM) == FRAME_POINTER_REGNUM) \ 659 (OFFSET) = 0; \ 660 else if ((FROM) == ARG_POINTER_REGNUM) \ 661 (OFFSET) = xtensa_current_frame_size; \ 662 else \ 663 abort (); \ 664 } while (0) 665 666 /* If defined, the maximum amount of space required for outgoing 667 arguments will be computed and placed into the variable 668 'current_function_outgoing_args_size'. No space will be pushed 669 onto the stack for each call; instead, the function prologue 670 should increase the stack frame size by this amount. */ 671 #define ACCUMULATE_OUTGOING_ARGS 1 672 673 /* Offset from the argument pointer register to the first argument's 674 address. On some machines it may depend on the data type of the 675 function. If 'ARGS_GROW_DOWNWARD', this is the offset to the 676 location above the first argument's address. */ 677 #define FIRST_PARM_OFFSET(FNDECL) 0 678 679 /* Align stack frames on 128 bits for Xtensa. This is necessary for 680 128-bit datatypes defined in TIE (e.g., for Vectra). */ 681 #define STACK_BOUNDARY 128 682 683 /* Functions do not pop arguments off the stack. */ 684 #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) 0 685 686 /* Use a fixed register window size of 8. */ 687 #define WINDOW_SIZE 8 688 689 /* Symbolic macros for the registers used to return integer, floating 690 point, and values of coprocessor and user-defined modes. */ 691 #define GP_RETURN (GP_REG_FIRST + 2 + WINDOW_SIZE) 692 #define GP_OUTGOING_RETURN (GP_REG_FIRST + 2) 693 694 /* Symbolic macros for the first/last argument registers. */ 695 #define GP_ARG_FIRST (GP_REG_FIRST + 2) 696 #define GP_ARG_LAST (GP_REG_FIRST + 7) 697 #define GP_OUTGOING_ARG_FIRST (GP_REG_FIRST + 2 + WINDOW_SIZE) 698 #define GP_OUTGOING_ARG_LAST (GP_REG_FIRST + 7 + WINDOW_SIZE) 699 700 #define MAX_ARGS_IN_REGISTERS 6 701 702 /* Don't worry about compatibility with PCC. */ 703 #define DEFAULT_PCC_STRUCT_RETURN 0 704 705 /* For Xtensa, up to 4 words can be returned in registers. (It would 706 have been nice to allow up to 6 words in registers but GCC cannot 707 support that. The return value must be given one of the standard 708 MODE_INT modes, and there is no 6 word mode. Instead, if we try to 709 return a 6 word structure, GCC selects the next biggest mode 710 (OImode, 8 words) and then the register allocator fails because 711 there is no 8-register group beginning with a10.) */ 712 #define RETURN_IN_MEMORY(TYPE) \ 713 ((unsigned HOST_WIDE_INT) int_size_in_bytes (TYPE) > 4 * UNITS_PER_WORD) 714 715 /* Define how to find the value returned by a library function 716 assuming the value has mode MODE. Because we have defined 717 PROMOTE_FUNCTION_RETURN, we have to perform the same promotions as 718 PROMOTE_MODE. */ 719 #define XTENSA_LIBCALL_VALUE(MODE, OUTGOINGP) \ 720 gen_rtx_REG ((GET_MODE_CLASS (MODE) == MODE_INT \ 721 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \ 722 ? SImode : (MODE), \ 723 OUTGOINGP ? GP_OUTGOING_RETURN : GP_RETURN) 724 725 #define LIBCALL_VALUE(MODE) \ 726 XTENSA_LIBCALL_VALUE ((MODE), 0) 727 728 #define LIBCALL_OUTGOING_VALUE(MODE) \ 729 XTENSA_LIBCALL_VALUE ((MODE), 1) 730 731 /* Define how to find the value returned by a function. 732 VALTYPE is the data type of the value (as a tree). 733 If the precise function being called is known, FUNC is its FUNCTION_DECL; 734 otherwise, FUNC is 0. */ 735 #define XTENSA_FUNCTION_VALUE(VALTYPE, FUNC, OUTGOINGP) \ 736 gen_rtx_REG ((INTEGRAL_TYPE_P (VALTYPE) \ 737 && TYPE_PRECISION (VALTYPE) < BITS_PER_WORD) \ 738 ? SImode: TYPE_MODE (VALTYPE), \ 739 OUTGOINGP ? GP_OUTGOING_RETURN : GP_RETURN) 740 741 #define FUNCTION_VALUE(VALTYPE, FUNC) \ 742 XTENSA_FUNCTION_VALUE (VALTYPE, FUNC, 0) 743 744 #define FUNCTION_OUTGOING_VALUE(VALTYPE, FUNC) \ 745 XTENSA_FUNCTION_VALUE (VALTYPE, FUNC, 1) 746 747 /* A C expression that is nonzero if REGNO is the number of a hard 748 register in which the values of called function may come back. A 749 register whose use for returning values is limited to serving as 750 the second of a pair (for a value of type 'double', say) need not 751 be recognized by this macro. If the machine has register windows, 752 so that the caller and the called function use different registers 753 for the return value, this macro should recognize only the caller's 754 register numbers. */ 755 #define FUNCTION_VALUE_REGNO_P(N) \ 756 ((N) == GP_RETURN) 757 758 /* A C expression that is nonzero if REGNO is the number of a hard 759 register in which function arguments are sometimes passed. This 760 does *not* include implicit arguments such as the static chain and 761 the structure-value address. On many machines, no registers can be 762 used for this purpose since all function arguments are pushed on 763 the stack. */ 764 #define FUNCTION_ARG_REGNO_P(N) \ 765 ((N) >= GP_OUTGOING_ARG_FIRST && (N) <= GP_OUTGOING_ARG_LAST) 766 767 /* Record the number of argument words seen so far, along with a flag to 768 indicate whether these are incoming arguments. (FUNCTION_INCOMING_ARG 769 is used for both incoming and outgoing args, so a separate flag is 770 needed. */ 771 typedef struct xtensa_args 772 { 773 int arg_words; 774 int incoming; 775 } CUMULATIVE_ARGS; 776 777 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \ 778 init_cumulative_args (&CUM, 0) 779 780 #define INIT_CUMULATIVE_INCOMING_ARGS(CUM, FNTYPE, LIBNAME) \ 781 init_cumulative_args (&CUM, 1) 782 783 /* Update the data in CUM to advance over an argument 784 of mode MODE and data type TYPE. 785 (TYPE is null for libcalls where that information may not be available.) */ 786 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ 787 function_arg_advance (&CUM, MODE, TYPE) 788 789 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ 790 function_arg (&CUM, MODE, TYPE, FALSE) 791 792 #define FUNCTION_INCOMING_ARG(CUM, MODE, TYPE, NAMED) \ 793 function_arg (&CUM, MODE, TYPE, TRUE) 794 795 /* Arguments are never passed partly in memory and partly in registers. */ 796 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) (0) 797 798 /* Specify function argument alignment. */ 799 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \ 800 ((TYPE) != 0 \ 801 ? (TYPE_ALIGN (TYPE) <= PARM_BOUNDARY \ 802 ? PARM_BOUNDARY \ 803 : TYPE_ALIGN (TYPE)) \ 804 : (GET_MODE_ALIGNMENT (MODE) <= PARM_BOUNDARY \ 805 ? PARM_BOUNDARY \ 806 : GET_MODE_ALIGNMENT (MODE))) 807 808 /* Nonzero if we do not know how to pass TYPE solely in registers. 809 We cannot do so in the following cases: 810 811 - if the type has variable size 812 - if the type is marked as addressable (it is required to be constructed 813 into the stack) 814 815 This differs from the default in that it does not check if the padding 816 and mode of the type are such that a copy into a register would put it 817 into the wrong part of the register. */ 818 819 #define MUST_PASS_IN_STACK(MODE, TYPE) \ 820 ((TYPE) != 0 \ 821 && (TREE_CODE (TYPE_SIZE (TYPE)) != INTEGER_CST \ 822 || TREE_ADDRESSABLE (TYPE))) 823 824 /* Profiling Xtensa code is typically done with the built-in profiling 825 feature of Tensilica's instruction set simulator, which does not 826 require any compiler support. Profiling code on a real (i.e., 827 non-simulated) Xtensa processor is currently only supported by 828 GNU/Linux with glibc. The glibc version of _mcount doesn't require 829 counter variables. The _mcount function needs the current PC and 830 the current return address to identify an arc in the call graph. 831 Pass the current return address as the first argument; the current 832 PC is available as a0 in _mcount's register window. Both of these 833 values contain window size information in the two most significant 834 bits; we assume that _mcount will mask off those bits. The call to 835 _mcount uses a window size of 8 to make sure that it doesn't clobber 836 any incoming argument values. */ 837 838 #define NO_PROFILE_COUNTERS 1 839 840 #define FUNCTION_PROFILER(FILE, LABELNO) \ 841 do { \ 842 fprintf (FILE, "\t%s\ta10, a0\n", TARGET_DENSITY ? "mov.n" : "mov"); \ 843 if (flag_pic) \ 844 { \ 845 fprintf (FILE, "\tmovi\ta8, _mcount@PLT\n"); \ 846 fprintf (FILE, "\tcallx8\ta8\n"); \ 847 } \ 848 else \ 849 fprintf (FILE, "\tcall8\t_mcount\n"); \ 850 } while (0) 851 852 /* Stack pointer value doesn't matter at exit. */ 853 #define EXIT_IGNORE_STACK 1 854 855 /* A C statement to output, on the stream FILE, assembler code for a 856 block of data that contains the constant parts of a trampoline. 857 This code should not include a label--the label is taken care of 858 automatically. 859 860 For Xtensa, the trampoline must perform an entry instruction with a 861 minimal stack frame in order to get some free registers. Once the 862 actual call target is known, the proper stack frame size is extracted 863 from the entry instruction at the target and the current frame is 864 adjusted to match. The trampoline then transfers control to the 865 instruction following the entry at the target. Note: this assumes 866 that the target begins with an entry instruction. */ 867 868 /* minimum frame = reg save area (4 words) plus static chain (1 word) 869 and the total number of words must be a multiple of 128 bits */ 870 #define MIN_FRAME_SIZE (8 * UNITS_PER_WORD) 871 872 #define TRAMPOLINE_TEMPLATE(STREAM) \ 873 do { \ 874 fprintf (STREAM, "\t.begin no-generics\n"); \ 875 fprintf (STREAM, "\tentry\tsp, %d\n", MIN_FRAME_SIZE); \ 876 \ 877 /* save the return address */ \ 878 fprintf (STREAM, "\tmov\ta10, a0\n"); \ 879 \ 880 /* Use a CALL0 instruction to skip past the constants and in the \ 881 process get the PC into A0. This allows PC-relative access to \ 882 the constants without relying on L32R, which may not always be \ 883 available. */ \ 884 \ 885 fprintf (STREAM, "\tcall0\t.Lskipconsts\n"); \ 886 fprintf (STREAM, "\t.align\t4\n"); \ 887 fprintf (STREAM, ".Lchainval:%s0\n", integer_asm_op (4, TRUE)); \ 888 fprintf (STREAM, ".Lfnaddr:%s0\n", integer_asm_op (4, TRUE)); \ 889 fprintf (STREAM, ".Lskipconsts:\n"); \ 890 \ 891 /* store the static chain */ \ 892 fprintf (STREAM, "\taddi\ta0, a0, 3\n"); \ 893 fprintf (STREAM, "\tl32i\ta8, a0, 0\n"); \ 894 fprintf (STREAM, "\ts32i\ta8, sp, %d\n", MIN_FRAME_SIZE - 20); \ 895 \ 896 /* set the proper stack pointer value */ \ 897 fprintf (STREAM, "\tl32i\ta8, a0, 4\n"); \ 898 fprintf (STREAM, "\tl32i\ta9, a8, 0\n"); \ 899 fprintf (STREAM, "\textui\ta9, a9, %d, 12\n", \ 900 TARGET_BIG_ENDIAN ? 8 : 12); \ 901 fprintf (STREAM, "\tslli\ta9, a9, 3\n"); \ 902 fprintf (STREAM, "\taddi\ta9, a9, %d\n", -MIN_FRAME_SIZE); \ 903 fprintf (STREAM, "\tsub\ta9, sp, a9\n"); \ 904 fprintf (STREAM, "\tmovsp\tsp, a9\n"); \ 905 \ 906 /* restore the return address */ \ 907 fprintf (STREAM, "\tmov\ta0, a10\n"); \ 908 \ 909 /* jump to the instruction following the entry */ \ 910 fprintf (STREAM, "\taddi\ta8, a8, 3\n"); \ 911 fprintf (STREAM, "\tjx\ta8\n"); \ 912 fprintf (STREAM, "\t.end no-generics\n"); \ 913 } while (0) 914 915 /* Size in bytes of the trampoline, as an integer. */ 916 #define TRAMPOLINE_SIZE 59 917 918 /* Alignment required for trampolines, in bits. */ 919 #define TRAMPOLINE_ALIGNMENT (32) 920 921 /* A C statement to initialize the variable parts of a trampoline. */ 922 #define INITIALIZE_TRAMPOLINE(ADDR, FUNC, CHAIN) \ 923 do { \ 924 rtx addr = ADDR; \ 925 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (addr, 12)), CHAIN); \ 926 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (addr, 16)), FUNC); \ 927 emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "__xtensa_sync_caches"), \ 928 0, VOIDmode, 1, addr, Pmode); \ 929 } while (0) 930 931 /* If defined, is a C expression that produces the machine-specific 932 code for a call to '__builtin_saveregs'. This code will be moved 933 to the very beginning of the function, before any parameter access 934 are made. The return value of this function should be an RTX that 935 contains the value to use as the return of '__builtin_saveregs'. */ 936 #define EXPAND_BUILTIN_SAVEREGS \ 937 xtensa_builtin_saveregs 938 939 /* Implement `va_start' for varargs and stdarg. */ 940 #define EXPAND_BUILTIN_VA_START(valist, nextarg) \ 941 xtensa_va_start (valist, nextarg) 942 943 /* Implement `va_arg'. */ 944 #define EXPAND_BUILTIN_VA_ARG(valist, type) \ 945 xtensa_va_arg (valist, type) 946 947 /* If defined, a C expression that produces the machine-specific code 948 to setup the stack so that arbitrary frames can be accessed. 949 950 On Xtensa, a stack back-trace must always begin from the stack pointer, 951 so that the register overflow save area can be located. However, the 952 stack-walking code in GCC always begins from the hard_frame_pointer 953 register, not the stack pointer. The frame pointer is usually equal 954 to the stack pointer, but the __builtin_return_address and 955 __builtin_frame_address functions will not work if count > 0 and 956 they are called from a routine that uses alloca. These functions 957 are not guaranteed to work at all if count > 0 so maybe that is OK. 958 959 A nicer solution would be to allow the architecture-specific files to 960 specify whether to start from the stack pointer or frame pointer. That 961 would also allow us to skip the machine->accesses_prev_frame stuff that 962 we currently need to ensure that there is a frame pointer when these 963 builtin functions are used. */ 964 965 #define SETUP_FRAME_ADDRESSES xtensa_setup_frame_addresses 966 967 /* A C expression whose value is RTL representing the address in a 968 stack frame where the pointer to the caller's frame is stored. 969 Assume that FRAMEADDR is an RTL expression for the address of the 970 stack frame itself. 971 972 For Xtensa, there is no easy way to get the frame pointer if it is 973 not equivalent to the stack pointer. Moreover, the result of this 974 macro is used for continuing to walk back up the stack, so it must 975 return the stack pointer address. Thus, there is some inconsistency 976 here in that __builtin_frame_address will return the frame pointer 977 when count == 0 and the stack pointer when count > 0. */ 978 979 #define DYNAMIC_CHAIN_ADDRESS(frame) \ 980 gen_rtx (PLUS, Pmode, frame, \ 981 gen_rtx_CONST_INT (VOIDmode, -3 * UNITS_PER_WORD)) 982 983 /* Define this if the return address of a particular stack frame is 984 accessed from the frame pointer of the previous stack frame. */ 985 #define RETURN_ADDR_IN_PREVIOUS_FRAME 986 987 /* A C expression whose value is RTL representing the value of the 988 return address for the frame COUNT steps up from the current 989 frame, after the prologue. */ 990 #define RETURN_ADDR_RTX xtensa_return_addr 991 992 /* Addressing modes, and classification of registers for them. */ 993 994 /* C expressions which are nonzero if register number NUM is suitable 995 for use as a base or index register in operand addresses. It may 996 be either a suitable hard register or a pseudo register that has 997 been allocated such a hard register. The difference between an 998 index register and a base register is that the index register may 999 be scaled. */ 1000 1001 #define REGNO_OK_FOR_BASE_P(NUM) \ 1002 (GP_REG_P (NUM) || GP_REG_P ((unsigned) reg_renumber[NUM])) 1003 1004 #define REGNO_OK_FOR_INDEX_P(NUM) 0 1005 1006 /* C expressions that are nonzero if X (assumed to be a `reg' RTX) is 1007 valid for use as a base or index register. For hard registers, it 1008 should always accept those which the hardware permits and reject 1009 the others. Whether the macro accepts or rejects pseudo registers 1010 must be controlled by `REG_OK_STRICT'. This usually requires two 1011 variant definitions, of which `REG_OK_STRICT' controls the one 1012 actually used. The difference between an index register and a base 1013 register is that the index register may be scaled. */ 1014 1015 #ifdef REG_OK_STRICT 1016 1017 #define REG_OK_FOR_INDEX_P(X) 0 1018 #define REG_OK_FOR_BASE_P(X) \ 1019 REGNO_OK_FOR_BASE_P (REGNO (X)) 1020 1021 #else /* !REG_OK_STRICT */ 1022 1023 #define REG_OK_FOR_INDEX_P(X) 0 1024 #define REG_OK_FOR_BASE_P(X) \ 1025 ((REGNO (X) >= FIRST_PSEUDO_REGISTER) || (GP_REG_P (REGNO (X)))) 1026 1027 #endif /* !REG_OK_STRICT */ 1028 1029 /* Maximum number of registers that can appear in a valid memory address. */ 1030 #define MAX_REGS_PER_ADDRESS 1 1031 1032 /* Identify valid Xtensa addresses. */ 1033 #define GO_IF_LEGITIMATE_ADDRESS(MODE, ADDR, LABEL) \ 1034 do { \ 1035 rtx xinsn = (ADDR); \ 1036 \ 1037 /* allow constant pool addresses */ \ 1038 if ((MODE) != BLKmode && GET_MODE_SIZE (MODE) >= UNITS_PER_WORD \ 1039 && !TARGET_CONST16 && constantpool_address_p (xinsn)) \ 1040 goto LABEL; \ 1041 \ 1042 while (GET_CODE (xinsn) == SUBREG) \ 1043 xinsn = SUBREG_REG (xinsn); \ 1044 \ 1045 /* allow base registers */ \ 1046 if (GET_CODE (xinsn) == REG && REG_OK_FOR_BASE_P (xinsn)) \ 1047 goto LABEL; \ 1048 \ 1049 /* check for "register + offset" addressing */ \ 1050 if (GET_CODE (xinsn) == PLUS) \ 1051 { \ 1052 rtx xplus0 = XEXP (xinsn, 0); \ 1053 rtx xplus1 = XEXP (xinsn, 1); \ 1054 enum rtx_code code0; \ 1055 enum rtx_code code1; \ 1056 \ 1057 while (GET_CODE (xplus0) == SUBREG) \ 1058 xplus0 = SUBREG_REG (xplus0); \ 1059 code0 = GET_CODE (xplus0); \ 1060 \ 1061 while (GET_CODE (xplus1) == SUBREG) \ 1062 xplus1 = SUBREG_REG (xplus1); \ 1063 code1 = GET_CODE (xplus1); \ 1064 \ 1065 /* swap operands if necessary so the register is first */ \ 1066 if (code0 != REG && code1 == REG) \ 1067 { \ 1068 xplus0 = XEXP (xinsn, 1); \ 1069 xplus1 = XEXP (xinsn, 0); \ 1070 code0 = GET_CODE (xplus0); \ 1071 code1 = GET_CODE (xplus1); \ 1072 } \ 1073 \ 1074 if (code0 == REG && REG_OK_FOR_BASE_P (xplus0) \ 1075 && code1 == CONST_INT \ 1076 && xtensa_mem_offset (INTVAL (xplus1), (MODE))) \ 1077 { \ 1078 goto LABEL; \ 1079 } \ 1080 } \ 1081 } while (0) 1082 1083 /* A C expression that is 1 if the RTX X is a constant which is a 1084 valid address. This is defined to be the same as 'CONSTANT_P (X)', 1085 but rejecting CONST_DOUBLE. */ 1086 #define CONSTANT_ADDRESS_P(X) \ 1087 ((GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \ 1088 || GET_CODE (X) == CONST_INT || GET_CODE (X) == HIGH \ 1089 || (GET_CODE (X) == CONST))) 1090 1091 /* Nonzero if the constant value X is a legitimate general operand. 1092 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */ 1093 #define LEGITIMATE_CONSTANT_P(X) 1 1094 1095 /* A C expression that is nonzero if X is a legitimate immediate 1096 operand on the target machine when generating position independent 1097 code. */ 1098 #define LEGITIMATE_PIC_OPERAND_P(X) \ 1099 ((GET_CODE (X) != SYMBOL_REF \ 1100 || (SYMBOL_REF_LOCAL_P (X) && !SYMBOL_REF_EXTERNAL_P (X))) \ 1101 && GET_CODE (X) != LABEL_REF \ 1102 && GET_CODE (X) != CONST) 1103 1104 /* Tell GCC how to use ADDMI to generate addresses. */ 1105 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \ 1106 do { \ 1107 rtx xinsn = (X); \ 1108 if (GET_CODE (xinsn) == PLUS) \ 1109 { \ 1110 rtx plus0 = XEXP (xinsn, 0); \ 1111 rtx plus1 = XEXP (xinsn, 1); \ 1112 \ 1113 if (GET_CODE (plus0) != REG && GET_CODE (plus1) == REG) \ 1114 { \ 1115 plus0 = XEXP (xinsn, 1); \ 1116 plus1 = XEXP (xinsn, 0); \ 1117 } \ 1118 \ 1119 if (GET_CODE (plus0) == REG \ 1120 && GET_CODE (plus1) == CONST_INT \ 1121 && !xtensa_mem_offset (INTVAL (plus1), MODE) \ 1122 && !xtensa_simm8 (INTVAL (plus1)) \ 1123 && xtensa_mem_offset (INTVAL (plus1) & 0xff, MODE) \ 1124 && xtensa_simm8x256 (INTVAL (plus1) & ~0xff)) \ 1125 { \ 1126 rtx temp = gen_reg_rtx (Pmode); \ 1127 emit_insn (gen_rtx (SET, Pmode, temp, \ 1128 gen_rtx (PLUS, Pmode, plus0, \ 1129 GEN_INT (INTVAL (plus1) & ~0xff)))); \ 1130 (X) = gen_rtx (PLUS, Pmode, temp, \ 1131 GEN_INT (INTVAL (plus1) & 0xff)); \ 1132 goto WIN; \ 1133 } \ 1134 } \ 1135 } while (0) 1136 1137 1138 /* Treat constant-pool references as "mode dependent" since they can 1139 only be accessed with SImode loads. This works around a bug in the 1140 combiner where a constant pool reference is temporarily converted 1141 to an HImode load, which is then assumed to zero-extend based on 1142 our definition of LOAD_EXTEND_OP. This is wrong because the high 1143 bits of a 16-bit value in the constant pool are now sign-extended 1144 by default. */ 1145 1146 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \ 1147 do { \ 1148 if (constantpool_address_p (ADDR)) \ 1149 goto LABEL; \ 1150 } while (0) 1151 1152 /* Specify the machine mode that this machine uses 1153 for the index in the tablejump instruction. */ 1154 #define CASE_VECTOR_MODE (SImode) 1155 1156 /* Define this if the tablejump instruction expects the table 1157 to contain offsets from the address of the table. 1158 Do not define this if the table should contain absolute addresses. */ 1159 /* #define CASE_VECTOR_PC_RELATIVE */ 1160 1161 /* Define this as 1 if 'char' should by default be signed; else as 0. */ 1162 #define DEFAULT_SIGNED_CHAR 0 1163 1164 /* Max number of bytes we can move from memory to memory 1165 in one reasonably fast instruction. */ 1166 #define MOVE_MAX 4 1167 #define MAX_MOVE_MAX 4 1168 1169 /* Prefer word-sized loads. */ 1170 #define SLOW_BYTE_ACCESS 1 1171 1172 /* Shift instructions ignore all but the low-order few bits. */ 1173 #define SHIFT_COUNT_TRUNCATED 1 1174 1175 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits 1176 is done just by pretending it is already truncated. */ 1177 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 1178 1179 /* Specify the machine mode that pointers have. 1180 After generation of rtl, the compiler makes no further distinction 1181 between pointers and any other objects of this machine mode. */ 1182 #define Pmode SImode 1183 1184 /* A function address in a call instruction is a word address (for 1185 indexing purposes) so give the MEM rtx a words's mode. */ 1186 #define FUNCTION_MODE SImode 1187 1188 /* A C expression for the cost of moving data from a register in 1189 class FROM to one in class TO. The classes are expressed using 1190 the enumeration values such as 'GENERAL_REGS'. A value of 2 is 1191 the default; other values are interpreted relative to that. */ 1192 #define REGISTER_MOVE_COST(MODE, FROM, TO) \ 1193 (((FROM) == (TO) && (FROM) != BR_REGS && (TO) != BR_REGS) \ 1194 ? 2 \ 1195 : (reg_class_subset_p ((FROM), AR_REGS) \ 1196 && reg_class_subset_p ((TO), AR_REGS) \ 1197 ? 2 \ 1198 : (reg_class_subset_p ((FROM), AR_REGS) \ 1199 && (TO) == ACC_REG \ 1200 ? 3 \ 1201 : ((FROM) == ACC_REG \ 1202 && reg_class_subset_p ((TO), AR_REGS) \ 1203 ? 3 \ 1204 : 10)))) 1205 1206 #define MEMORY_MOVE_COST(MODE, CLASS, IN) 4 1207 1208 #define BRANCH_COST 3 1209 1210 /* Optionally define this if you have added predicates to 1211 'MACHINE.c'. This macro is called within an initializer of an 1212 array of structures. The first field in the structure is the 1213 name of a predicate and the second field is an array of rtl 1214 codes. For each predicate, list all rtl codes that can be in 1215 expressions matched by the predicate. The list should have a 1216 trailing comma. */ 1217 1218 #define PREDICATE_CODES \ 1219 {"add_operand", { REG, CONST_INT, SUBREG }}, \ 1220 {"arith_operand", { REG, CONST_INT, SUBREG }}, \ 1221 {"nonimmed_operand", { REG, SUBREG, MEM }}, \ 1222 {"mem_operand", { MEM }}, \ 1223 {"mask_operand", { REG, CONST_INT, SUBREG }}, \ 1224 {"extui_fldsz_operand", { CONST_INT }}, \ 1225 {"sext_fldsz_operand", { CONST_INT }}, \ 1226 {"lsbitnum_operand", { CONST_INT }}, \ 1227 {"fpmem_offset_operand", { CONST_INT }}, \ 1228 {"sext_operand", { REG, SUBREG, MEM }}, \ 1229 {"branch_operand", { REG, CONST_INT, SUBREG }}, \ 1230 {"ubranch_operand", { REG, CONST_INT, SUBREG }}, \ 1231 {"call_insn_operand", { CONST_INT, CONST, SYMBOL_REF, REG }}, \ 1232 {"move_operand", { REG, SUBREG, MEM, CONST_INT, CONST_DOUBLE, \ 1233 CONST, SYMBOL_REF, LABEL_REF }}, \ 1234 {"const_float_1_operand", { CONST_DOUBLE }}, \ 1235 {"branch_operator", { EQ, NE, LT, GE }}, \ 1236 {"ubranch_operator", { LTU, GEU }}, \ 1237 {"boolean_operator", { EQ, NE }}, 1238 1239 /* Control the assembler format that we output. */ 1240 1241 /* How to refer to registers in assembler output. 1242 This sequence is indexed by compiler's hard-register-number (see above). */ 1243 #define REGISTER_NAMES \ 1244 { \ 1245 "a0", "sp", "a2", "a3", "a4", "a5", "a6", "a7", \ 1246 "a8", "a9", "a10", "a11", "a12", "a13", "a14", "a15", \ 1247 "fp", "argp", "b0", \ 1248 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", \ 1249 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", \ 1250 "acc" \ 1251 } 1252 1253 /* If defined, a C initializer for an array of structures containing a 1254 name and a register number. This macro defines additional names 1255 for hard registers, thus allowing the 'asm' option in declarations 1256 to refer to registers using alternate names. */ 1257 #define ADDITIONAL_REGISTER_NAMES \ 1258 { \ 1259 { "a1", 1 + GP_REG_FIRST } \ 1260 } 1261 1262 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE) 1263 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR) 1264 1265 /* Recognize machine-specific patterns that may appear within 1266 constants. Used for PIC-specific UNSPECs. */ 1267 #define OUTPUT_ADDR_CONST_EXTRA(STREAM, X, FAIL) \ 1268 do { \ 1269 if (flag_pic && GET_CODE (X) == UNSPEC && XVECLEN ((X), 0) == 1) \ 1270 { \ 1271 switch (XINT ((X), 1)) \ 1272 { \ 1273 case UNSPEC_PLT: \ 1274 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \ 1275 fputs ("@PLT", (STREAM)); \ 1276 break; \ 1277 default: \ 1278 goto FAIL; \ 1279 } \ 1280 break; \ 1281 } \ 1282 else \ 1283 goto FAIL; \ 1284 } while (0) 1285 1286 /* Globalizing directive for a label. */ 1287 #define GLOBAL_ASM_OP "\t.global\t" 1288 1289 /* Declare an uninitialized external linkage data object. */ 1290 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \ 1291 asm_output_aligned_bss (FILE, DECL, NAME, SIZE, ALIGN) 1292 1293 /* This is how to output an element of a case-vector that is absolute. */ 1294 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \ 1295 fprintf (STREAM, "%s%sL%u\n", integer_asm_op (4, TRUE), \ 1296 LOCAL_LABEL_PREFIX, VALUE) 1297 1298 /* This is how to output an element of a case-vector that is relative. 1299 This is used for pc-relative code. */ 1300 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \ 1301 do { \ 1302 fprintf (STREAM, "%s%sL%u-%sL%u\n", integer_asm_op (4, TRUE), \ 1303 LOCAL_LABEL_PREFIX, (VALUE), \ 1304 LOCAL_LABEL_PREFIX, (REL)); \ 1305 } while (0) 1306 1307 /* This is how to output an assembler line that says to advance the 1308 location counter to a multiple of 2**LOG bytes. */ 1309 #define ASM_OUTPUT_ALIGN(STREAM, LOG) \ 1310 do { \ 1311 if ((LOG) != 0) \ 1312 fprintf (STREAM, "\t.align\t%d\n", 1 << (LOG)); \ 1313 } while (0) 1314 1315 /* Indicate that jump tables go in the text section. This is 1316 necessary when compiling PIC code. */ 1317 #define JUMP_TABLES_IN_TEXT_SECTION (flag_pic) 1318 1319 1320 /* Define the strings to put out for each section in the object file. */ 1321 #define TEXT_SECTION_ASM_OP "\t.text" 1322 #define DATA_SECTION_ASM_OP "\t.data" 1323 #define BSS_SECTION_ASM_OP "\t.section\t.bss" 1324 1325 1326 /* Define output to appear before the constant pool. If the function 1327 has been assigned to a specific ELF section, or if it goes into a 1328 unique section, set the name of that section to be the literal 1329 prefix. */ 1330 #define ASM_OUTPUT_POOL_PROLOGUE(FILE, FUNNAME, FUNDECL, SIZE) \ 1331 do { \ 1332 tree fnsection; \ 1333 resolve_unique_section ((FUNDECL), 0, flag_function_sections); \ 1334 fnsection = DECL_SECTION_NAME (FUNDECL); \ 1335 if (fnsection != NULL_TREE) \ 1336 { \ 1337 const char *fnsectname = TREE_STRING_POINTER (fnsection); \ 1338 fprintf (FILE, "\t.begin\tliteral_prefix %s\n", \ 1339 strcmp (fnsectname, ".text") ? fnsectname : ""); \ 1340 } \ 1341 if ((SIZE) > 0) \ 1342 { \ 1343 function_section (FUNDECL); \ 1344 fprintf (FILE, "\t.literal_position\n"); \ 1345 } \ 1346 } while (0) 1347 1348 1349 /* Define code to write out the ".end literal_prefix" directive for a 1350 function in a special section. This is appended to the standard ELF 1351 code for ASM_DECLARE_FUNCTION_SIZE. */ 1352 #define XTENSA_DECLARE_FUNCTION_SIZE(FILE, FNAME, DECL) \ 1353 if (DECL_SECTION_NAME (DECL) != NULL_TREE) \ 1354 fprintf (FILE, "\t.end\tliteral_prefix\n") 1355 1356 /* A C statement (with or without semicolon) to output a constant in 1357 the constant pool, if it needs special treatment. */ 1358 #define ASM_OUTPUT_SPECIAL_POOL_ENTRY(FILE, X, MODE, ALIGN, LABELNO, JUMPTO) \ 1359 do { \ 1360 xtensa_output_literal (FILE, X, MODE, LABELNO); \ 1361 goto JUMPTO; \ 1362 } while (0) 1363 1364 /* How to start an assembler comment. */ 1365 #define ASM_COMMENT_START "#" 1366 1367 /* Exception handling TODO!! */ 1368 #define DWARF_UNWIND_INFO 0 1369 1370 /* Xtensa constant pool breaks the devices in crtstuff.c to control 1371 section in where code resides. We have to write it as asm code. Use 1372 a MOVI and let the assembler relax it -- for the .init and .fini 1373 sections, the assembler knows to put the literal in the right 1374 place. */ 1375 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \ 1376 asm (SECTION_OP "\n\ 1377 movi\ta8, " USER_LABEL_PREFIX #FUNC "\n\ 1378 callx8\ta8\n" \ 1379 TEXT_SECTION_ASM_OP); 1380