1// -*- C -*-
2
3// Simulator definition for the MIPS MIPS-3D ASE.
4// Copyright (C) 2002 Free Software Foundation, Inc.
5// Contributed by Ed Satterthwaite and Chris Demetriou, of Broadcom
6// Corporation (SiByte).
7//
8// This file is part of GDB, the GNU debugger.
9//
10// This program is free software; you can redistribute it and/or modify
11// it under the terms of the GNU General Public License as published by
12// the Free Software Foundation; either version 2, or (at your option)
13// any later version.
14//
15// This program is distributed in the hope that it will be useful,
16// but WITHOUT ANY WARRANTY; without even the implied warranty of
17// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
18// GNU General Public License for more details.
19//
20// You should have received a copy of the GNU General Public License along
21// with this program; if not, write to the Free Software Foundation, Inc.,
22// 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
23
24//  Reference: MIPS64 Architecture for Programmers Volume IV-c:
25//             The MIPS-3D Application-Specific Extension to the
26//             MIPS64 Architecture.  (MIPS Document MD00099)
27
28
29010001,10,110,5.FT,5.FS,5.FD,011000:COP1:64,f::ADDR.PS
30"addr.ps f<FD>, f<FS>, f<FT>"
31*mips3d:
32{
33  /* fd.PL = ft.PU + ft.PL;  fd.PU = fs.PU + fs.PL;  */
34  check_fpu (SD_);
35  check_u64 (SD_, instruction_0);
36  StoreFPR (FD, fmt_ps, AddR (ValueFPR (FS, fmt_ps),
37			      ValueFPR (FT, fmt_ps), fmt_ps));
38}
39
40
41010001,01001,3.CC,0,1.TF,16.OFFSET:COP1:64,f::BC1ANY2tf
42"bc1any2%s<TF> <CC>, %#lx<OFFSET>"
43*mips3d:
44{
45  address_word offset;
46  int cc = CC;
47  check_fpu (SD_);
48  check_u64 (SD_, instruction_0);
49  if ((cc & 0x1) != 0)
50    Unpredictable ();
51  if ((GETFCC (cc) == TF) || (GETFCC (cc + 1) == TF))
52    {
53      offset = (EXTEND16 (OFFSET) << 2);
54      DELAY_SLOT (NIA + offset);
55    }
56}
57
58
59010001,01010,3.CC,0,1.TF,16.OFFSET:COP1:64,f::BC1ANY4tf
60"bc1any4%s<TF> <CC>, %#lx<OFFSET>"
61*mips3d:
62{
63  address_word offset;
64  int cc = CC;
65  check_fpu (SD_);
66  check_u64 (SD_, instruction_0);
67  if ((cc & 0x3) != 0)
68    Unpredictable ();
69  if ((GETFCC (cc) == TF)
70      || (GETFCC (cc + 1) == TF)
71      || (GETFCC (cc + 2) == TF)
72      || (GETFCC (cc + 3) == TF))
73    {
74      offset = (EXTEND16 (OFFSET) << 2);
75      DELAY_SLOT (NIA + offset);
76    }
77}
78
79
80010001,10,3.FMT,5.FT,5.FS,3.CC,01,11,4.COND:COP1:64,f::CABS.cond.fmt
81"cabs.%s<COND>.%s<FMT> <CC>, f<FS>, f<FT>"
82*mips3d:
83{
84  int fmt = FMT;
85  check_fpu (SD_);
86  check_u64 (SD_, instruction_0);
87  check_fmt_p (SD_, fmt, instruction_0);
88  CompareAbs (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt, COND, CC);
89  TRACE_ALU_RESULT (ValueFCR (31));
90}
91
92
93010001,10,110,00000,5.FS,5.FD,100100:COP1:64,f::CVT.PW.PS
94"cvt.pw.ps f<FD>, f<FS>"
95*mips3d:
96{
97  /* fd.pu = cvt_rnd (fs.pu); fd.pl = cvt_rnd (fs.pl);  */
98  /* fmt_pw is fmt_long for 64 bit transfers, but cvt encoding is fmt_word.  */
99  check_fpu (SD_);
100  check_u64 (SD_, instruction_0);
101  StoreFPR (FD, fmt_pw, ConvertPS (GETRM (), ValueFPR (FS, fmt_ps),
102				   fmt_ps, fmt_word));
103}
104
105
106010001,10,100,00000,5.FS,5.FD,100110:COP1:64,f::CVT.PS.PW
107"cvt.ps.pw f<FD>, f<FS>"
108*mips3d:
109{
110  /* fd.pl = cvt_rnd (fs.pl); fd.pu = cvt_rnd (fs.pu);  */
111  /* fmt_pw is fmt_long for 64 bit transfers, but cvt encoding is fmt_word.  */
112  check_fpu (SD_);
113  check_u64 (SD_, instruction_0);
114  StoreFPR (FD, fmt_ps, ConvertPS (GETRM (), ValueFPR (FS, fmt_pw),
115				   fmt_word, fmt_ps));
116}
117
118
119010001,10,110,5.FT,5.FS,5.FD,011010:COP1:64,f::MULR.PS
120"mulr.ps f<FD>, f<FS>, f<FT>"
121*mips3d:
122{
123  /* fd.PL = ft.PU * ft.PL;  fd.PU = fs.PU * fs.PL;  */
124  check_fpu (SD_);
125  check_u64 (SD_, instruction_0);
126  StoreFPR (FD, fmt_ps, MultiplyR (ValueFPR (FS, fmt_ps),
127				   ValueFPR (FT, fmt_ps), fmt_ps));
128}
129
130
131010001,10,3.FMT,00000,5.FS,5.FD,011101:COP1:64,f::RECIP1.fmt
132"recip1.%s<FMT> f<FD>, f<FS>"
133*mips3d:
134{
135  int fmt = FMT;
136  check_fpu (SD_);
137  check_u64 (SD_, instruction_0);
138  check_fmt_p (SD_, fmt, instruction_0);
139  StoreFPR (FD, fmt, Recip1 (ValueFPR (FS, fmt), fmt));
140}
141
142
143010001,10,3.FMT,5.FT,5.FS,5.FD,011100:COP1:64,f::RECIP2.fmt
144"recip2.%s<FMT> f<FD>, f<FS>, f<FT>"
145*mips3d:
146{
147  int fmt = FMT;
148  check_fpu (SD_);
149  check_u64 (SD_, instruction_0);
150  check_fmt_p (SD_, fmt, instruction_0);
151  StoreFPR (FD, fmt, Recip2 (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt));
152}
153
154
155010001,10,3.FMT,00000,5.FS,5.FD,011110:COP1:64,f::RSQRT1.fmt
156"rsqrt1.%s<FMT> f<FD>, f<FS>"
157*mips3d:
158{
159  int fmt = FMT;
160  check_fpu (SD_);
161  check_u64 (SD_, instruction_0);
162  check_fmt_p (SD_, fmt, instruction_0);
163  StoreFPR (FD, fmt, RSquareRoot1 (ValueFPR (FS, fmt), fmt));
164}
165
166
167010001,10,3.FMT,5.FT,5.FS,5.FD,011111:COP1:64,f::RSQRT2.fmt
168"rsqrt2.%s<FMT> f<FD>, f<FS>, f<FT>"
169*mips3d:
170{
171  int fmt = FMT;
172  check_fpu (SD_);
173  check_u64 (SD_, instruction_0);
174  check_fmt_p (SD_, fmt, instruction_0);
175  StoreFPR (FD, fmt, RSquareRoot2 (ValueFPR (FS, fmt),
176				   ValueFPR (FT, fmt), fmt));
177}
178