1{ 2 System register definitions and utility code for Cortex-M0 3 Created by Jeppe Johansen 2012 - jeppe@j-software.dk 4 Modified for M0 by Michael Ring 2013 - mail@michael-ring.org 5} 6unit cortexm0; 7 8interface 9 10{$PACKRECORDS 2} 11const 12 SCS_BASE = $E000E000; 13 SysTick_BASE = SCS_BASE+$0010; 14 NVIC_BASE = SCS_BASE+$0100; 15 SCB_BASE = SCS_BASE+$0D00; 16 17 DWT_BASE = $E0001000; 18 FP_BASE = $E0002000; 19 ITM_BASE = $E0000000; 20 TPIU_BASE = $E0040000; 21 ETM_BASE = $E0041000; 22 23type 24 25 TNVICRegisters = record 26 ISER : dword; 27 RESERVED0 : array[0..30] of dword; 28 ICER : dword; 29 RSERVED1 : array[0..30] of dword; 30 ISPR : dword; 31 RESERVED2 : array[0..30] of dword; 32 ICPR : dword; 33 RESERVED3 : array[0..30] of dword; 34 RESERVED4 : array[0..63] of dword; 35 IPR : array[0..7] of dword; 36 end; 37 38 TSCBRegisters = record 39 CPUID, {!< CPU ID Base Register } 40 ICSR, {!< Interrupt Control State Register } 41 RESERVED0, 42 AIRCR, {!< Application Interrupt / Reset Control Register } 43 SCR, {!< System Control Register } 44 CCR: dword; {!< Configuration Control Register } 45 RESERVED1 : dword; 46 SHP: array[0..1] of dword; {!< System Handlers Priority Registers (4-7, 8-11, 12-15) } 47 end; 48 49 TSysTickRegisters = record 50 Ctrl, 51 Load, 52 Val, 53 Calib: dword; 54 end; 55 56 TCoreDebugRegisters = record 57 DHCSR, 58 DCRSR, 59 DCRDR, 60 DEMCR: longword; 61 end; 62 63 64var 65 // System Control 66 InterruptControlType: longword absolute (SCS_BASE+$0004); 67 SCB: TSCBRegisters absolute (SCS_BASE+$0D00); 68 SysTick: TSysTickRegisters absolute (SCS_BASE+$0010); 69 NVIC: TNVICRegisters absolute (SCS_BASE+$0100); 70 SoftwareTriggerInterrupt: longword absolute (SCS_BASE+$0000); 71 72 // Core Debug 73 CoreDebug: TCoreDebugRegisters absolute (SCS_BASE+$0DF0); 74 75 76implementation 77 78end. 79