1unit ATtiny461; 2 3{$goto on} 4 5interface 6 7var 8 // PORTA 9 PORTA : byte absolute $00+$3B; // Port A Data Register 10 DDRA : byte absolute $00+$3A; // Port A Data Direction Register 11 PINA : byte absolute $00+$39; // Port A Input Pins 12 // PORTB 13 PORTB : byte absolute $00+$38; // Port B Data Register 14 DDRB : byte absolute $00+$37; // Port B Data Direction Register 15 PINB : byte absolute $00+$36; // Port B Input Pins 16 // AD_CONVERTER 17 ADMUX : byte absolute $00+$27; // The ADC multiplexer Selection Register 18 ADCSRA : byte absolute $00+$26; // The ADC Control and Status register 19 ADC : word absolute $00+$24; // ADC Data Register Bytes 20 ADCL : byte absolute $00+$24; // ADC Data Register Bytes 21 ADCH : byte absolute $00+$24+1; // ADC Data Register Bytes 22 ADCSRB : byte absolute $00+$23; // ADC Control and Status Register B 23 DIDR1 : byte absolute $00+$22; // Digital Input Disable Register 1 24 DIDR0 : byte absolute $00+$21; // Digital Input Disable Register 0 25 // ANALOG_COMPARATOR 26 ACSRB : byte absolute $00+$29; // Analog Comparator Control And Status Register B 27 ACSRA : byte absolute $00+$28; // Analog Comparator Control And Status Register A 28 // USI 29 USIPP : byte absolute $00+$31; // USI Pin Position 30 USIBR : byte absolute $00+$30; // USI Buffer Register 31 USIDR : byte absolute $00+$2F; // USI Data Register 32 USISR : byte absolute $00+$2E; // USI Status Register 33 USICR : byte absolute $00+$2D; // USI Control Register 34 // EEPROM 35 EEAR : word absolute $00+$3E; // EEPROM Address Register Bytes 36 EEARL : byte absolute $00+$3E; // EEPROM Address Register Bytes 37 EEARH : byte absolute $00+$3E+1; // EEPROM Address Register Bytes 38 EEDR : byte absolute $00+$3D; // EEPROM Data Register 39 EECR : byte absolute $00+$3C; // EEPROM Control Register 40 // WATCHDOG 41 WDTCR : byte absolute $00+$41; // Watchdog Timer Control Register 42 // TIMER_COUNTER_0 43 TIMSK : byte absolute $00+$59; // Timer/Counter Interrupt Mask Register 44 TIFR : byte absolute $00+$58; // Timer/Counter0 Interrupt Flag register 45 TCCR0A : byte absolute $00+$35; // Timer/Counter Control Register A 46 TCCR0B : byte absolute $00+$53; // Timer/Counter Control Register B 47 TCNT0H : byte absolute $00+$34; // Timer/Counter0 High 48 TCNT0L : byte absolute $00+$52; // Timer/Counter0 Low 49 OCR0A : byte absolute $00+$33; // Timer/Counter0 Output Compare Register 50 OCR0B : byte absolute $00+$32; // Timer/Counter0 Output Compare Register 51 // TIMER_COUNTER_1 52 TCCR1A : byte absolute $00+$50; // Timer/Counter Control Register A 53 TCCR1B : byte absolute $00+$4F; // Timer/Counter Control Register B 54 TCCR1C : byte absolute $00+$47; // Timer/Counter Control Register C 55 TCCR1D : byte absolute $00+$46; // Timer/Counter Control Register D 56 TCCR1E : byte absolute $00+$20; // Timer/Counter1 Control Register E 57 TCNT1 : byte absolute $00+$4E; // Timer/Counter Register 58 TC1H : byte absolute $00+$45; // Timer/Counter 1 Register High 59 OCR1A : byte absolute $00+$4D; // Output Compare Register 60 OCR1B : byte absolute $00+$4C; // Output Compare Register 61 OCR1C : byte absolute $00+$4B; // Output compare register 62 OCR1D : byte absolute $00+$4A; // Output compare register 63 DT1 : byte absolute $00+$44; // Timer/Counter 1 Dead Time Value 64 // BOOT_LOAD 65 SPMCSR : byte absolute $00+$57; // Store Program Memory Control Register 66 // CPU 67 SREG : byte absolute $00+$5F; // Status Register 68 PRR : byte absolute $00+$56; // Power Reduction Register 69 SP : word absolute $00+$5D; // Stack Pointer Bytes 70 SPL : byte absolute $00+$5D; // Stack Pointer Bytes 71 SPH : byte absolute $00+$5D+1; // Stack Pointer Bytes 72 MCUCR : byte absolute $00+$55; // MCU Control Register 73 MCUSR : byte absolute $00+$54; // MCU Status register 74 OSCCAL : byte absolute $00+$51; // Oscillator Calibration Register 75 CLKPR : byte absolute $00+$48; // Clock Prescale Register 76 PLLCSR : byte absolute $00+$49; // PLL Control and status register 77 DWDR : byte absolute $00+$40; // debugWire data register 78 GPIOR2 : byte absolute $00+$2C; // General Purpose IO register 2 79 GPIOR1 : byte absolute $00+$2B; // General Purpose register 1 80 GPIOR0 : byte absolute $00+$2A; // General purpose register 0 81 // EXTERNAL_INTERRUPT 82 GIMSK : byte absolute $00+$5B; // General Interrupt Mask Register 83 GIFR : byte absolute $00+$5A; // General Interrupt Flag register 84 PCMSK1 : byte absolute $00+$42; // Pin Change Enable Mask 1 85 PCMSK0 : byte absolute $00+$43; // Pin Change Enable Mask 0 86 87const 88 // ADMUX 89 REFS = 6; // Reference Selection Bits 90 ADLAR = 5; // Left Adjust Result 91 MUX = 0; // Analog Channel and Gain Selection Bits 92 // ADCSRA 93 ADEN = 7; // ADC Enable 94 ADSC = 6; // ADC Start Conversion 95 ADATE = 5; // ADC Auto Trigger Enable 96 ADIF = 4; // ADC Interrupt Flag 97 ADIE = 3; // ADC Interrupt Enable 98 ADPS = 0; // ADC Prescaler Select Bits 99 // ADCSRB 100 BIN = 7; // Bipolar Input Mode 101 GSEL = 6; // Gain Select 102 IPR = 5; // Input Polarity Mode 103 REFS2 = 4; // 104 MUX5 = 3; // 105 ADTS = 0; // ADC Auto Trigger Sources 106 // DIDR1 107 ADC10D = 7; // ADC10 Digital input Disable 108 ADC9D = 6; // ADC9 Digital input Disable 109 ADC8D = 5; // ADC8 Digital input Disable 110 ADC7D = 4; // ADC7 Digital input Disable 111 // DIDR0 112 ADC6D = 7; // ADC6 Digital input Disable 113 ADC5D = 6; // ADC5 Digital input Disable 114 ADC4D = 5; // ADC4 Digital input Disable 115 ADC3D = 4; // ADC3 Digital input Disable 116 AREFD = 3; // AREF Digital Input Disable 117 ADC2D = 2; // ADC2 Digital input Disable 118 ADC1D = 1; // ADC1 Digital input Disable 119 ADC0D = 0; // ADC0 Digital input Disable 120 // ACSRB 121 HSEL = 7; // Hysteresis Select 122 HLEV = 6; // Hysteresis Level 123 ACM = 0; // Analog Comparator Multiplexer 124 // ACSRA 125 ACD = 7; // Analog Comparator Disable 126 ACBG = 6; // Analog Comparator Bandgap Select 127 ACO = 5; // Analog Compare Output 128 ACI = 4; // Analog Comparator Interrupt Flag 129 ACIE = 3; // Analog Comparator Interrupt Enable 130 ACME = 2; // Analog Comparator Multiplexer Enable 131 ACIS = 0; // Analog Comparator Interrupt Mode Select bits 132 // USISR 133 USISIF = 7; // Start Condition Interrupt Flag 134 USIOIF = 6; // Counter Overflow Interrupt Flag 135 USIPF = 5; // Stop Condition Flag 136 USIDC = 4; // Data Output Collision 137 USICNT = 0; // USI Counter Value Bits 138 // USICR 139 USISIE = 7; // Start Condition Interrupt Enable 140 USIOIE = 6; // Counter Overflow Interrupt Enable 141 USIWM = 4; // USI Wire Mode Bits 142 USICS = 2; // USI Clock Source Select Bits 143 USICLK = 1; // Clock Strobe 144 USITC = 0; // Toggle Clock Port Pin 145 // EECR 146 EEPM = 4; // EEPROM Programming Mode Bits 147 EERIE = 3; // EEPROM Ready Interrupt Enable 148 EEMPE = 2; // EEPROM Master Write Enable 149 EEPE = 1; // EEPROM Write Enable 150 EERE = 0; // EEPROM Read Enable 151 // WDTCR 152 WDIF = 7; // Watchdog Timeout Interrupt Flag 153 WDIE = 6; // Watchdog Timeout Interrupt Enable 154 WDP = 0; // Watchdog Timer Prescaler Bits 155 WDCE = 4; // Watchdog Change Enable 156 WDE = 3; // Watch Dog Enable 157 // TIMSK 158 OCIE0A = 4; // Timer/Counter0 Output Compare Match A Interrupt Enable 159 OCIE0B = 3; // Timer/Counter0 Output Compare Match B Interrupt Enable 160 TOIE0 = 1; // Timer/Counter0 Overflow Interrupt Enable 161 TICIE0 = 0; // Timer/Counter0 Input Capture Interrupt Enable 162 // TIFR 163 OCF0A = 4; // Timer/Counter0 Output Compare Flag 0A 164 OCF0B = 3; // Timer/Counter0 Output Compare Flag 0B 165 TOV0 = 1; // Timer/Counter0 Overflow Flag 166 ICF0 = 0; // Timer/Counter0 Input Capture Flag 167 // TCCR0A 168 TCW0 = 7; // Timer/Counter 0 Width 169 ICEN0 = 6; // Input Capture Mode Enable 170 ICNC0 = 5; // Input Capture Noice Canceler 171 ICES0 = 4; // Input Capture Edge Select 172 ACIC0 = 3; // Analog Comparator Input Capture Enable 173 WGM00 = 0; // Waveform Generation Mode 174 // TCCR0B 175 TSM = 4; // Timer/Counter Synchronization Mode 176 PSR0 = 3; // Timer/Counter 0 Prescaler Reset 177 CS0 = 0; // Clock Select 178 // TCCR1A 179 COM1A = 6; // Compare Output Mode, Bits 180 COM1B = 4; // Compare Output Mode, Bits 181 FOC1A = 3; // Force Output Compare Match 1A 182 FOC1B = 2; // Force Output Compare Match 1B 183 PWM1A = 1; // Pulse Width Modulator Enable 184 PWM1B = 0; // Pulse Width Modulator Enable 185 // TCCR1B 186 PSR1 = 6; // Timer/Counter 1 Prescaler reset 187 DTPS1 = 4; // Dead Time Prescaler 188 CS1 = 0; // Clock Select Bits 189 // TCCR1C 190 COM1A1S = 7; // COM1A1 Shadow Bit 191 COM1A0S = 6; // COM1A0 Shadow Bit 192 COM1B1S = 5; // COM1B1 Shadow Bit 193 COM1B0S = 4; // COM1B0 Shadow Bit 194 COM1D = 2; // Comparator D output mode 195 FOC1D = 1; // Force Output Compare Match 1D 196 PWM1D = 0; // Pulse Width Modulator D Enable 197 // TCCR1D 198 FPIE1 = 7; // Fault Protection Interrupt Enable 199 FPEN1 = 6; // Fault Protection Mode Enable 200 FPNC1 = 5; // Fault Protection Noise Canceler 201 FPES1 = 4; // Fault Protection Edge Select 202 FPAC1 = 3; // Fault Protection Analog Comparator Enable 203 FPF1 = 2; // Fault Protection Interrupt Flag 204 WGM1 = 0; // Waveform Generation Mode Bit 205 // TCCR1E 206 OC1OE = 0; // Ouput Compare Override Enable Bits 207 // TIMSK 208 OCIE1D = 7; // OCIE1D: Timer/Counter1 Output Compare Interrupt Enable 209 OCIE1A = 6; // OCIE1A: Timer/Counter1 Output Compare Interrupt Enable 210 OCIE1B = 5; // OCIE1A: Timer/Counter1 Output Compare B Interrupt Enable 211 TOIE1 = 2; // Timer/Counter1 Overflow Interrupt Enable 212 // TIFR 213 OCF1D = 7; // Timer/Counter1 Output Compare Flag 1D 214 OCF1A = 6; // Timer/Counter1 Output Compare Flag 1A 215 OCF1B = 5; // Timer/Counter1 Output Compare Flag 1B 216 TOV1 = 2; // Timer/Counter1 Overflow Flag 217 // DT1 218 DT1H = 4; // 219 DT1L = 0; // 220 // SPMCSR 221 CTPB = 4; // Clear temporary page buffer 222 RFLB = 3; // Read fuse and lock bits 223 PGWRT = 2; // Page Write 224 PGERS = 1; // Page Erase 225 SPMEN = 0; // Store Program Memory Enable 226 // SREG 227 I = 7; // Global Interrupt Enable 228 T = 6; // Bit Copy Storage 229 H = 5; // Half Carry Flag 230 S = 4; // Sign Bit 231 V = 3; // Two's Complement Overflow Flag 232 N = 2; // Negative Flag 233 Z = 1; // Zero Flag 234 C = 0; // Carry Flag 235 // PRR 236 PRTIM1 = 3; // Power Reduction Timer/Counter1 237 PRTIM0 = 2; // Power Reduction Timer/Counter0 238 PRUSI = 1; // Power Reduction USI 239 PRADC = 0; // Power Reduction ADC 240 // MCUCR 241 PUD = 6; // Pull-up Disable 242 SE = 5; // Sleep Enable 243 SM = 3; // Sleep Mode Select Bits 244 ISC0 = 0; // Interrupt Sense Control 0 bits 245 // MCUSR 246 WDRF = 3; // Watchdog Reset Flag 247 BORF = 2; // Brown-out Reset Flag 248 EXTRF = 1; // External Reset Flag 249 PORF = 0; // Power-On Reset Flag 250 // CLKPR 251 CLKPCE = 7; // Clock Prescaler Change Enable 252 CLKPS = 0; // Clock Prescaler Select Bits 253 // PLLCSR 254 LSM = 7; // Low speed mode 255 PCKE = 2; // PCK Enable 256 PLLE = 1; // PLL Enable 257 PLOCK = 0; // PLL Lock detector 258 // MCUCR 259 ISC01 = 1; // Interrupt Sense Control 0 Bit 1 260 ISC00 = 0; // Interrupt Sense Control 0 Bit 0 261 // GIMSK 262 INT = 6; // External Interrupt Request 1 Enable 263 PCIE = 4; // Pin Change Interrupt Enables 264 // GIFR 265 INTF = 6; // External Interrupt Flags 266 PCIF = 5; // Pin Change Interrupt Flag 267 268implementation 269 270{$define RELBRANCHES} 271 272{$i avrcommon.inc} 273 274procedure INT0_ISR; external name 'INT0_ISR'; // Interrupt 1 External Interrupt 0 275procedure PCINT_ISR; external name 'PCINT_ISR'; // Interrupt 2 Pin Change Interrupt 276procedure TIMER1_COMPA_ISR; external name 'TIMER1_COMPA_ISR'; // Interrupt 3 Timer/Counter1 Compare Match 1A 277procedure TIMER1_COMPB_ISR; external name 'TIMER1_COMPB_ISR'; // Interrupt 4 Timer/Counter1 Compare Match 1B 278procedure TIMER1_OVF_ISR; external name 'TIMER1_OVF_ISR'; // Interrupt 5 Timer/Counter1 Overflow 279procedure TIMER0_OVF_ISR; external name 'TIMER0_OVF_ISR'; // Interrupt 6 Timer/Counter0 Overflow 280procedure USI_START_ISR; external name 'USI_START_ISR'; // Interrupt 7 USI Start 281procedure USI_OVF_ISR; external name 'USI_OVF_ISR'; // Interrupt 8 USI Overflow 282procedure EE_RDY_ISR; external name 'EE_RDY_ISR'; // Interrupt 9 EEPROM Ready 283procedure ANA_COMP_ISR; external name 'ANA_COMP_ISR'; // Interrupt 10 Analog Comparator 284procedure ADC_ISR; external name 'ADC_ISR'; // Interrupt 11 ADC Conversion Complete 285procedure WDT_ISR; external name 'WDT_ISR'; // Interrupt 12 Watchdog Time-Out 286procedure INT1_ISR; external name 'INT1_ISR'; // Interrupt 13 External Interrupt 1 287procedure TIMER0_COMPA_ISR; external name 'TIMER0_COMPA_ISR'; // Interrupt 14 Timer/Counter0 Compare Match A 288procedure TIMER0_COMPB_ISR; external name 'TIMER0_COMPB_ISR'; // Interrupt 15 Timer/Counter0 Compare Match B 289procedure TIMER0_CAPT_ISR; external name 'TIMER0_CAPT_ISR'; // Interrupt 16 ADC Conversion Complete 290procedure TIMER1_COMPD_ISR; external name 'TIMER1_COMPD_ISR'; // Interrupt 17 Timer/Counter1 Compare Match D 291procedure FAULT_PROTECTION_ISR; external name 'FAULT_PROTECTION_ISR'; // Interrupt 18 Timer/Counter1 Fault Protection 292 293procedure _FPC_start; assembler; nostackframe; 294label 295 _start; 296 asm 297 .init 298 .globl _start 299 300 rjmp _start 301 rjmp INT0_ISR 302 rjmp PCINT_ISR 303 rjmp TIMER1_COMPA_ISR 304 rjmp TIMER1_COMPB_ISR 305 rjmp TIMER1_OVF_ISR 306 rjmp TIMER0_OVF_ISR 307 rjmp USI_START_ISR 308 rjmp USI_OVF_ISR 309 rjmp EE_RDY_ISR 310 rjmp ANA_COMP_ISR 311 rjmp ADC_ISR 312 rjmp WDT_ISR 313 rjmp INT1_ISR 314 rjmp TIMER0_COMPA_ISR 315 rjmp TIMER0_COMPB_ISR 316 rjmp TIMER0_CAPT_ISR 317 rjmp TIMER1_COMPD_ISR 318 rjmp FAULT_PROTECTION_ISR 319 320 {$i start.inc} 321 322 .weak INT0_ISR 323 .weak PCINT_ISR 324 .weak TIMER1_COMPA_ISR 325 .weak TIMER1_COMPB_ISR 326 .weak TIMER1_OVF_ISR 327 .weak TIMER0_OVF_ISR 328 .weak USI_START_ISR 329 .weak USI_OVF_ISR 330 .weak EE_RDY_ISR 331 .weak ANA_COMP_ISR 332 .weak ADC_ISR 333 .weak WDT_ISR 334 .weak INT1_ISR 335 .weak TIMER0_COMPA_ISR 336 .weak TIMER0_COMPB_ISR 337 .weak TIMER0_CAPT_ISR 338 .weak TIMER1_COMPD_ISR 339 .weak FAULT_PROTECTION_ISR 340 341 .set INT0_ISR, Default_IRQ_handler 342 .set PCINT_ISR, Default_IRQ_handler 343 .set TIMER1_COMPA_ISR, Default_IRQ_handler 344 .set TIMER1_COMPB_ISR, Default_IRQ_handler 345 .set TIMER1_OVF_ISR, Default_IRQ_handler 346 .set TIMER0_OVF_ISR, Default_IRQ_handler 347 .set USI_START_ISR, Default_IRQ_handler 348 .set USI_OVF_ISR, Default_IRQ_handler 349 .set EE_RDY_ISR, Default_IRQ_handler 350 .set ANA_COMP_ISR, Default_IRQ_handler 351 .set ADC_ISR, Default_IRQ_handler 352 .set WDT_ISR, Default_IRQ_handler 353 .set INT1_ISR, Default_IRQ_handler 354 .set TIMER0_COMPA_ISR, Default_IRQ_handler 355 .set TIMER0_COMPB_ISR, Default_IRQ_handler 356 .set TIMER0_CAPT_ISR, Default_IRQ_handler 357 .set TIMER1_COMPD_ISR, Default_IRQ_handler 358 .set FAULT_PROTECTION_ISR, Default_IRQ_handler 359 end; 360 361end. 362