1 unit PIC12F1572; 2 3 // Define hardware 4 {$SET PIC_MODEL = 'PIC12F1572'} 5 {$SET PIC_MAXFREQ = 32000000} 6 {$SET PIC_NPINS = 8} 7 {$SET PIC_NUMBANKS = 32} 8 {$SET PIC_NUMPAGES = 1} 9 {$SET PIC_MAXFLASH = 2048} 10 11 interface 12 var 13 INDF0 : byte absolute $0000; 14 INDF1 : byte absolute $0001; 15 PCL : byte absolute $0002; 16 STATUS : byte absolute $0003; 17 STATUS_nTO : bit absolute STATUS.4; 18 STATUS_nPD : bit absolute STATUS.3; 19 STATUS_Z : bit absolute STATUS.2; 20 STATUS_DC : bit absolute STATUS.1; 21 STATUS_C : bit absolute STATUS.0; 22 FSR0L : byte absolute $0004; 23 FSR0H : byte absolute $0005; 24 FSR1L : byte absolute $0006; 25 FSR1H : byte absolute $0007; 26 BSR : byte absolute $0008; 27 BSR_BSR4 : bit absolute BSR.4; 28 BSR_BSR3 : bit absolute BSR.3; 29 BSR_BSR2 : bit absolute BSR.2; 30 BSR_BSR1 : bit absolute BSR.1; 31 BSR_BSR0 : bit absolute BSR.0; 32 WREG : byte absolute $0009; 33 PCLATH : byte absolute $000A; 34 PCLATH_PCLATH6 : bit absolute PCLATH.6; 35 PCLATH_PCLATH5 : bit absolute PCLATH.5; 36 PCLATH_PCLATH4 : bit absolute PCLATH.4; 37 PCLATH_PCLATH3 : bit absolute PCLATH.3; 38 PCLATH_PCLATH2 : bit absolute PCLATH.2; 39 PCLATH_PCLATH1 : bit absolute PCLATH.1; 40 PCLATH_PCLATH0 : bit absolute PCLATH.0; 41 INTCON : byte absolute $000B; 42 INTCON_GIE : bit absolute INTCON.7; 43 INTCON_PEIE : bit absolute INTCON.6; 44 INTCON_TMR0IE : bit absolute INTCON.5; 45 INTCON_INTE : bit absolute INTCON.4; 46 INTCON_IOCIE : bit absolute INTCON.3; 47 INTCON_TMR0IF : bit absolute INTCON.2; 48 INTCON_INTF : bit absolute INTCON.1; 49 INTCON_IOCIF : bit absolute INTCON.0; 50 PORTA : byte absolute $000C; 51 PORTA_RA5 : bit absolute PORTA.5; 52 PORTA_RA4 : bit absolute PORTA.4; 53 PORTA_RA3 : bit absolute PORTA.3; 54 PORTA_RA2 : bit absolute PORTA.2; 55 PORTA_RA1 : bit absolute PORTA.1; 56 PORTA_RA0 : bit absolute PORTA.0; 57 PIR1 : byte absolute $0011; 58 PIR1_TMR1GIF : bit absolute PIR1.7; 59 PIR1_ADIF : bit absolute PIR1.6; 60 PIR1_RCIF : bit absolute PIR1.5; 61 PIR1_TXIF : bit absolute PIR1.4; 62 PIR1_TMR2IF : bit absolute PIR1.1; 63 PIR1_TMR1IF : bit absolute PIR1.0; 64 PIR2 : byte absolute $0012; 65 PIR2_C1IF : bit absolute PIR2.5; 66 PIR3 : byte absolute $0013; 67 PIR3_PWM3IF : bit absolute PIR3.6; 68 PIR3_PWM2IF : bit absolute PIR3.5; 69 PIR3_PWM1IF : bit absolute PIR3.4; 70 TMR0 : byte absolute $0015; 71 TMR1L : byte absolute $0016; 72 TMR1H : byte absolute $0017; 73 T1CON : byte absolute $0018; 74 T1CON_TMR1CS1 : bit absolute T1CON.7; 75 T1CON_TMR1CS0 : bit absolute T1CON.6; 76 T1CON_T1CKPS1 : bit absolute T1CON.5; 77 T1CON_T1CKPS0 : bit absolute T1CON.4; 78 T1CON_nT1SYNC : bit absolute T1CON.2; 79 T1CON_TMR1ON : bit absolute T1CON.0; 80 T1GCON : byte absolute $0019; 81 T1GCON_TMR1GE : bit absolute T1GCON.7; 82 T1GCON_T1GPOL : bit absolute T1GCON.6; 83 T1GCON_T1GTM : bit absolute T1GCON.5; 84 T1GCON_T1GSPM : bit absolute T1GCON.4; 85 T1GCON_T1GGO_nDONE : bit absolute T1GCON.3; 86 T1GCON_T1GVAL : bit absolute T1GCON.2; 87 T1GCON_T1GSS1 : bit absolute T1GCON.1; 88 T1GCON_T1GSS0 : bit absolute T1GCON.0; 89 TMR2 : byte absolute $001A; 90 PR2 : byte absolute $001B; 91 T2CON : byte absolute $001C; 92 T2CON_T2OUTPS3 : bit absolute T2CON.6; 93 T2CON_T2OUTPS2 : bit absolute T2CON.5; 94 T2CON_T2OUTPS1 : bit absolute T2CON.4; 95 T2CON_T2OUTPS0 : bit absolute T2CON.3; 96 T2CON_T2CKPS1 : bit absolute T2CON.1; 97 T2CON_T2CKPS0 : bit absolute T2CON.0; 98 TRISA : byte absolute $008C; 99 TRISA_TRISA5 : bit absolute TRISA.5; 100 TRISA_TRISA4 : bit absolute TRISA.4; 101 TRISA_TRISA3 : bit absolute TRISA.3; 102 TRISA_TRISA2 : bit absolute TRISA.2; 103 TRISA_TRISA1 : bit absolute TRISA.1; 104 TRISA_TRISA0 : bit absolute TRISA.0; 105 PIE1 : byte absolute $0091; 106 PIE1_TMR1GIE : bit absolute PIE1.7; 107 PIE1_ADIE : bit absolute PIE1.6; 108 PIE1_RCIE : bit absolute PIE1.5; 109 PIE1_TXIE : bit absolute PIE1.4; 110 PIE1_TMR2IE : bit absolute PIE1.1; 111 PIE1_TMR1IE : bit absolute PIE1.0; 112 PIE2 : byte absolute $0092; 113 PIE2_C1IE : bit absolute PIE2.5; 114 PIE3 : byte absolute $0093; 115 PIE3_PWM3IE : bit absolute PIE3.6; 116 PIE3_PWM2IE : bit absolute PIE3.5; 117 PIE3_PWM1IE : bit absolute PIE3.4; 118 OPTION_REG : byte absolute $0095; 119 OPTION_REG_nWPUEN : bit absolute OPTION_REG.7; 120 OPTION_REG_INTEDG : bit absolute OPTION_REG.6; 121 OPTION_REG_TMR0CS : bit absolute OPTION_REG.5; 122 OPTION_REG_TMR0SE : bit absolute OPTION_REG.4; 123 OPTION_REG_PSA : bit absolute OPTION_REG.3; 124 OPTION_REG_PS2 : bit absolute OPTION_REG.2; 125 OPTION_REG_PS1 : bit absolute OPTION_REG.1; 126 OPTION_REG_PS0 : bit absolute OPTION_REG.0; 127 PCON : byte absolute $0096; 128 PCON_STKOVF : bit absolute PCON.7; 129 PCON_STKUNF : bit absolute PCON.6; 130 PCON_nRWDT : bit absolute PCON.4; 131 PCON_nRMCLR : bit absolute PCON.3; 132 PCON_nRI : bit absolute PCON.2; 133 PCON_nPOR : bit absolute PCON.1; 134 PCON_nBOR : bit absolute PCON.0; 135 WDTCON : byte absolute $0097; 136 WDTCON_WDTPS4 : bit absolute WDTCON.5; 137 WDTCON_WDTPS3 : bit absolute WDTCON.4; 138 WDTCON_WDTPS2 : bit absolute WDTCON.3; 139 WDTCON_WDTPS1 : bit absolute WDTCON.2; 140 WDTCON_WDTPS0 : bit absolute WDTCON.1; 141 WDTCON_SWDTEN : bit absolute WDTCON.0; 142 OSCTUNE : byte absolute $0098; 143 OSCTUNE_TUN5 : bit absolute OSCTUNE.5; 144 OSCTUNE_TUN4 : bit absolute OSCTUNE.4; 145 OSCTUNE_TUN3 : bit absolute OSCTUNE.3; 146 OSCTUNE_TUN2 : bit absolute OSCTUNE.2; 147 OSCTUNE_TUN1 : bit absolute OSCTUNE.1; 148 OSCTUNE_TUN0 : bit absolute OSCTUNE.0; 149 OSCCON : byte absolute $0099; 150 OSCCON_SPLLEN : bit absolute OSCCON.7; 151 OSCCON_IRCF3 : bit absolute OSCCON.6; 152 OSCCON_IRCF2 : bit absolute OSCCON.5; 153 OSCCON_IRCF1 : bit absolute OSCCON.4; 154 OSCCON_IRCF0 : bit absolute OSCCON.3; 155 OSCCON_SCS1 : bit absolute OSCCON.1; 156 OSCCON_SCS0 : bit absolute OSCCON.0; 157 OSCSTAT : byte absolute $009A; 158 OSCSTAT_PLLR : bit absolute OSCSTAT.6; 159 OSCSTAT_OSTS : bit absolute OSCSTAT.5; 160 OSCSTAT_HFIOFR : bit absolute OSCSTAT.4; 161 OSCSTAT_HFIOFL : bit absolute OSCSTAT.3; 162 OSCSTAT_MFIOFR : bit absolute OSCSTAT.2; 163 OSCSTAT_LFIOFR : bit absolute OSCSTAT.1; 164 OSCSTAT_HFIOFS : bit absolute OSCSTAT.0; 165 ADRESL : byte absolute $009B; 166 ADRESH : byte absolute $009C; 167 ADCON0 : byte absolute $009D; 168 ADCON0_CHS4 : bit absolute ADCON0.6; 169 ADCON0_CHS3 : bit absolute ADCON0.5; 170 ADCON0_CHS2 : bit absolute ADCON0.4; 171 ADCON0_CHS1 : bit absolute ADCON0.3; 172 ADCON0_CHS0 : bit absolute ADCON0.2; 173 ADCON0_GO_nDONE : bit absolute ADCON0.1; 174 ADCON0_ADON : bit absolute ADCON0.0; 175 ADCON1 : byte absolute $009E; 176 ADCON1_ADFM : bit absolute ADCON1.7; 177 ADCON1_ADCS2 : bit absolute ADCON1.6; 178 ADCON1_ADCS1 : bit absolute ADCON1.5; 179 ADCON1_ADCS0 : bit absolute ADCON1.4; 180 ADCON1_ADPREF1 : bit absolute ADCON1.1; 181 ADCON1_ADPREF0 : bit absolute ADCON1.0; 182 ADCON2 : byte absolute $009F; 183 ADCON2_TRIGSEL3 : bit absolute ADCON2.7; 184 ADCON2_TRIGSEL2 : bit absolute ADCON2.6; 185 ADCON2_TRIGSEL1 : bit absolute ADCON2.5; 186 ADCON2_TRIGSEL0 : bit absolute ADCON2.4; 187 LATA : byte absolute $010C; 188 LATA_LATA5 : bit absolute LATA.5; 189 LATA_LATA4 : bit absolute LATA.4; 190 LATA_LATA2 : bit absolute LATA.2; 191 LATA_LATA1 : bit absolute LATA.1; 192 LATA_LATA0 : bit absolute LATA.0; 193 CM1CON0 : byte absolute $0111; 194 CM1CON0_C1ON : bit absolute CM1CON0.7; 195 CM1CON0_C1OUT : bit absolute CM1CON0.6; 196 CM1CON0_C1OE : bit absolute CM1CON0.5; 197 CM1CON0_C1POL : bit absolute CM1CON0.4; 198 CM1CON0_C1SP : bit absolute CM1CON0.2; 199 CM1CON0_C1HYS : bit absolute CM1CON0.1; 200 CM1CON0_C1SYNC : bit absolute CM1CON0.0; 201 CM1CON1 : byte absolute $0112; 202 CM1CON1_C1INTP : bit absolute CM1CON1.7; 203 CM1CON1_C1INTN : bit absolute CM1CON1.6; 204 CM1CON1_C1PCH1 : bit absolute CM1CON1.5; 205 CM1CON1_C1PCH0 : bit absolute CM1CON1.4; 206 CM1CON1_C1NCH2 : bit absolute CM1CON1.2; 207 CM1CON1_C1NCH1 : bit absolute CM1CON1.1; 208 CM1CON1_C1NCH0 : bit absolute CM1CON1.0; 209 CMOUT : byte absolute $0115; 210 CMOUT_MC1OUT : bit absolute CMOUT.0; 211 BORCON : byte absolute $0116; 212 BORCON_SBOREN : bit absolute BORCON.7; 213 BORCON_BORFS : bit absolute BORCON.6; 214 BORCON_BORRDY : bit absolute BORCON.0; 215 FVRCON : byte absolute $0117; 216 FVRCON_FVREN : bit absolute FVRCON.7; 217 FVRCON_FVRRDY : bit absolute FVRCON.6; 218 FVRCON_TSEN : bit absolute FVRCON.5; 219 FVRCON_TSRNG : bit absolute FVRCON.4; 220 FVRCON_CDAFVR1 : bit absolute FVRCON.3; 221 FVRCON_CDAFVR0 : bit absolute FVRCON.2; 222 FVRCON_ADFVR1 : bit absolute FVRCON.1; 223 FVRCON_ADFVR0 : bit absolute FVRCON.0; 224 DACCON0 : byte absolute $0118; 225 DACCON0_DACEN : bit absolute DACCON0.7; 226 DACCON0_DACLPS : bit absolute DACCON0.6; 227 DACCON0_DACOE : bit absolute DACCON0.5; 228 DACCON0_DACPSS1 : bit absolute DACCON0.3; 229 DACCON0_DACPSS0 : bit absolute DACCON0.2; 230 DACCON1 : byte absolute $0119; 231 DACCON1_DACR4 : bit absolute DACCON1.4; 232 DACCON1_DACR3 : bit absolute DACCON1.3; 233 DACCON1_DACR2 : bit absolute DACCON1.2; 234 DACCON1_DACR1 : bit absolute DACCON1.1; 235 DACCON1_DACR0 : bit absolute DACCON1.0; 236 APFCON : byte absolute $011D; 237 APFCON_RXDTSEL : bit absolute APFCON.7; 238 APFCON_CWGASEL : bit absolute APFCON.6; 239 APFCON_CWGBSEL : bit absolute APFCON.5; 240 APFCON_T1GSEL : bit absolute APFCON.3; 241 APFCON_TXCKSEL : bit absolute APFCON.2; 242 APFCON_P2SEL : bit absolute APFCON.1; 243 APFCON_P1SEL : bit absolute APFCON.0; 244 ANSELA : byte absolute $018C; 245 ANSELA_ANSA4 : bit absolute ANSELA.4; 246 ANSELA_ANSA2 : bit absolute ANSELA.2; 247 ANSELA_ANSA1 : bit absolute ANSELA.1; 248 ANSELA_ANSA0 : bit absolute ANSELA.0; 249 PMADRL : byte absolute $0191; 250 PMADRH : byte absolute $0192; 251 PMADRH_PMADRH6 : bit absolute PMADRH.6; 252 PMADRH_PMADRH5 : bit absolute PMADRH.5; 253 PMADRH_PMADRH4 : bit absolute PMADRH.4; 254 PMADRH_PMADRH3 : bit absolute PMADRH.3; 255 PMADRH_PMADRH2 : bit absolute PMADRH.2; 256 PMADRH_PMADRH1 : bit absolute PMADRH.1; 257 PMADRH_PMADRH0 : bit absolute PMADRH.0; 258 PMDATL : byte absolute $0193; 259 PMDATH : byte absolute $0194; 260 PMDATH_PMDATH5 : bit absolute PMDATH.5; 261 PMDATH_PMDATH4 : bit absolute PMDATH.4; 262 PMDATH_PMDATH3 : bit absolute PMDATH.3; 263 PMDATH_PMDATH2 : bit absolute PMDATH.2; 264 PMDATH_PMDATH1 : bit absolute PMDATH.1; 265 PMDATH_PMDATH0 : bit absolute PMDATH.0; 266 PMCON1 : byte absolute $0195; 267 PMCON1_CFGS : bit absolute PMCON1.6; 268 PMCON1_LWLO : bit absolute PMCON1.5; 269 PMCON1_FREE : bit absolute PMCON1.4; 270 PMCON1_WRERR : bit absolute PMCON1.3; 271 PMCON1_WREN : bit absolute PMCON1.2; 272 PMCON1_WR : bit absolute PMCON1.1; 273 PMCON1_RD : bit absolute PMCON1.0; 274 PMCON2 : byte absolute $0196; 275 VREGCON : byte absolute $0197; 276 VREGCON_VREGPM : bit absolute VREGCON.1; 277 RCREG : byte absolute $0199; 278 TXREG : byte absolute $019A; 279 SPBRGL : byte absolute $019B; 280 SPBRGH : byte absolute $019C; 281 RCSTA : byte absolute $019D; 282 RCSTA_SPEN : bit absolute RCSTA.7; 283 RCSTA_RX9 : bit absolute RCSTA.6; 284 RCSTA_SREN : bit absolute RCSTA.5; 285 RCSTA_CREN : bit absolute RCSTA.4; 286 RCSTA_ADDEN : bit absolute RCSTA.3; 287 RCSTA_FERR : bit absolute RCSTA.2; 288 RCSTA_OERR : bit absolute RCSTA.1; 289 RCSTA_RX9D : bit absolute RCSTA.0; 290 TXSTA : byte absolute $019E; 291 TXSTA_CSRC : bit absolute TXSTA.7; 292 TXSTA_TX9 : bit absolute TXSTA.6; 293 TXSTA_TXEN : bit absolute TXSTA.5; 294 TXSTA_SYNC : bit absolute TXSTA.4; 295 TXSTA_SENDB : bit absolute TXSTA.3; 296 TXSTA_BRGH : bit absolute TXSTA.2; 297 TXSTA_TRMT : bit absolute TXSTA.1; 298 TXSTA_TX9D : bit absolute TXSTA.0; 299 BAUDCON : byte absolute $019F; 300 BAUDCON_ABDOVF : bit absolute BAUDCON.7; 301 BAUDCON_RCIDL : bit absolute BAUDCON.6; 302 BAUDCON_SCKP : bit absolute BAUDCON.4; 303 BAUDCON_BRG16 : bit absolute BAUDCON.3; 304 BAUDCON_WUE : bit absolute BAUDCON.1; 305 BAUDCON_ABDEN : bit absolute BAUDCON.0; 306 WPUA : byte absolute $020C; 307 WPUA_WPUA5 : bit absolute WPUA.5; 308 WPUA_WPUA4 : bit absolute WPUA.4; 309 WPUA_WPUA3 : bit absolute WPUA.3; 310 WPUA_WPUA2 : bit absolute WPUA.2; 311 WPUA_WPUA1 : bit absolute WPUA.1; 312 WPUA_WPUA0 : bit absolute WPUA.0; 313 ODCONA : byte absolute $028C; 314 ODCONA_ODA5 : bit absolute ODCONA.5; 315 ODCONA_ODA4 : bit absolute ODCONA.4; 316 ODCONA_ODA2 : bit absolute ODCONA.2; 317 ODCONA_ODA1 : bit absolute ODCONA.1; 318 ODCONA_ODA0 : bit absolute ODCONA.0; 319 SLRCONA : byte absolute $030C; 320 SLRCONA_SLRA5 : bit absolute SLRCONA.5; 321 SLRCONA_SLRA4 : bit absolute SLRCONA.4; 322 SLRCONA_SLRA2 : bit absolute SLRCONA.2; 323 SLRCONA_SLRA1 : bit absolute SLRCONA.1; 324 SLRCONA_SLRA0 : bit absolute SLRCONA.0; 325 INLVLA : byte absolute $038C; 326 INLVLA_INLVLA5 : bit absolute INLVLA.5; 327 INLVLA_INLVLA4 : bit absolute INLVLA.4; 328 INLVLA_INLVLA3 : bit absolute INLVLA.3; 329 INLVLA_INLVLA2 : bit absolute INLVLA.2; 330 INLVLA_INLVLA1 : bit absolute INLVLA.1; 331 INLVLA_INLVLA0 : bit absolute INLVLA.0; 332 IOCAP : byte absolute $0391; 333 IOCAP_IOCAP5 : bit absolute IOCAP.5; 334 IOCAP_IOCAP4 : bit absolute IOCAP.4; 335 IOCAP_IOCAP3 : bit absolute IOCAP.3; 336 IOCAP_IOCAP2 : bit absolute IOCAP.2; 337 IOCAP_IOCAP1 : bit absolute IOCAP.1; 338 IOCAP_IOCAP0 : bit absolute IOCAP.0; 339 IOCAN : byte absolute $0392; 340 IOCAN_IOCAN5 : bit absolute IOCAN.5; 341 IOCAN_IOCAN4 : bit absolute IOCAN.4; 342 IOCAN_IOCAN3 : bit absolute IOCAN.3; 343 IOCAN_IOCAN2 : bit absolute IOCAN.2; 344 IOCAN_IOCAN1 : bit absolute IOCAN.1; 345 IOCAN_IOCAN0 : bit absolute IOCAN.0; 346 IOCAF : byte absolute $0393; 347 IOCAF_IOCAF5 : bit absolute IOCAF.5; 348 IOCAF_IOCAF4 : bit absolute IOCAF.4; 349 IOCAF_IOCAF3 : bit absolute IOCAF.3; 350 IOCAF_IOCAF2 : bit absolute IOCAF.2; 351 IOCAF_IOCAF1 : bit absolute IOCAF.1; 352 IOCAF_IOCAF0 : bit absolute IOCAF.0; 353 CWG1DBR : byte absolute $0691; 354 CWG1DBR_CWG1DBR5 : bit absolute CWG1DBR.5; 355 CWG1DBR_CWG1DBR4 : bit absolute CWG1DBR.4; 356 CWG1DBR_CWG1DBR3 : bit absolute CWG1DBR.3; 357 CWG1DBR_CWG1DBR2 : bit absolute CWG1DBR.2; 358 CWG1DBR_CWG1DBR1 : bit absolute CWG1DBR.1; 359 CWG1DBR_CWG1DBR0 : bit absolute CWG1DBR.0; 360 CWG1DBF : byte absolute $0692; 361 CWG1DBF_CWG1DBF5 : bit absolute CWG1DBF.5; 362 CWG1DBF_CWG1DBF4 : bit absolute CWG1DBF.4; 363 CWG1DBF_CWG1DBF3 : bit absolute CWG1DBF.3; 364 CWG1DBF_CWG1DBF2 : bit absolute CWG1DBF.2; 365 CWG1DBF_CWG1DBF1 : bit absolute CWG1DBF.1; 366 CWG1DBF_CWG1DBF0 : bit absolute CWG1DBF.0; 367 CWG1CON0 : byte absolute $0693; 368 CWG1CON0_G1EN : bit absolute CWG1CON0.7; 369 CWG1CON0_G1OEB : bit absolute CWG1CON0.6; 370 CWG1CON0_G1OEA : bit absolute CWG1CON0.5; 371 CWG1CON0_G1POLB : bit absolute CWG1CON0.4; 372 CWG1CON0_G1POLA : bit absolute CWG1CON0.3; 373 CWG1CON0_G1CS0 : bit absolute CWG1CON0.0; 374 CWG1CON1 : byte absolute $0694; 375 CWG1CON1_G1ASDLB1 : bit absolute CWG1CON1.7; 376 CWG1CON1_G1ASDLB0 : bit absolute CWG1CON1.6; 377 CWG1CON1_G1ASDLA1 : bit absolute CWG1CON1.5; 378 CWG1CON1_G1ASDLA0 : bit absolute CWG1CON1.4; 379 CWG1CON1_G1IS2 : bit absolute CWG1CON1.2; 380 CWG1CON1_G1IS1 : bit absolute CWG1CON1.1; 381 CWG1CON1_G1IS0 : bit absolute CWG1CON1.0; 382 CWG1CON2 : byte absolute $0695; 383 CWG1CON2_G1ASE : bit absolute CWG1CON2.7; 384 CWG1CON2_G1ARSEN : bit absolute CWG1CON2.6; 385 CWG1CON2_G1ASDSC1 : bit absolute CWG1CON2.2; 386 CWG1CON2_G1ASDSFLT : bit absolute CWG1CON2.1; 387 PWMEN : byte absolute $0D8E; 388 PWMEN_PWM3EN_A : bit absolute PWMEN.2; 389 PWMEN_PWM2EN_A : bit absolute PWMEN.1; 390 PWMEN_PWM1EN_A : bit absolute PWMEN.0; 391 PWMLD : byte absolute $0D8F; 392 PWMLD_PWM3LDA_A : bit absolute PWMLD.2; 393 PWMLD_PWM2LDA_A : bit absolute PWMLD.1; 394 PWMLD_PWM1LDA_A : bit absolute PWMLD.0; 395 PWMOUT : byte absolute $0D90; 396 PWMOUT_PWM3OUT_A : bit absolute PWMOUT.2; 397 PWMOUT_PWM2OUT_A : bit absolute PWMOUT.1; 398 PWMOUT_PWM1OUT_A : bit absolute PWMOUT.0; 399 PWM1PHL : byte absolute $0D91; 400 PWM1PHH : byte absolute $0D92; 401 PWM1DCL : byte absolute $0D93; 402 PWM1DCH : byte absolute $0D94; 403 PWM1PRL : byte absolute $0D95; 404 PWM1PRH : byte absolute $0D96; 405 PWM1OFL : byte absolute $0D97; 406 PWM1OFH : byte absolute $0D98; 407 PWM1TMRL : byte absolute $0D99; 408 PWM1TMRH : byte absolute $0D9A; 409 PWM1CON : byte absolute $0D9B; 410 PWM1CON_EN : bit absolute PWM1CON.7; 411 PWM1CON_OE : bit absolute PWM1CON.6; 412 PWM1CON_OUT : bit absolute PWM1CON.5; 413 PWM1CON_POL : bit absolute PWM1CON.4; 414 PWM1CON_MODE1 : bit absolute PWM1CON.3; 415 PWM1CON_MODE0 : bit absolute PWM1CON.2; 416 PWM1INTE : byte absolute $0D9C; 417 PWM1INTE_OFIE : bit absolute PWM1INTE.3; 418 PWM1INTE_PHIE : bit absolute PWM1INTE.2; 419 PWM1INTE_DCIE : bit absolute PWM1INTE.1; 420 PWM1INTE_PRIE : bit absolute PWM1INTE.0; 421 PWM1INTF : byte absolute $0D9D; 422 PWM1INTF_OFIF : bit absolute PWM1INTF.3; 423 PWM1INTF_PHIF : bit absolute PWM1INTF.2; 424 PWM1INTF_DCIF : bit absolute PWM1INTF.1; 425 PWM1INTF_PRIF : bit absolute PWM1INTF.0; 426 PWM1CLKCON : byte absolute $0D9E; 427 PWM1CLKCON_CS1 : bit absolute PWM1CLKCON.1; 428 PWM1CLKCON_CS0 : bit absolute PWM1CLKCON.0; 429 PWM1LDCON : byte absolute $0D9F; 430 PWM1LDCON_LDA : bit absolute PWM1LDCON.7; 431 PWM1LDCON_LDT : bit absolute PWM1LDCON.6; 432 PWM1LDCON_LDS1 : bit absolute PWM1LDCON.1; 433 PWM1LDCON_LDS0 : bit absolute PWM1LDCON.0; 434 PWM1OFCON : byte absolute $0DA0; 435 PWM1OFCON_OFM1 : bit absolute PWM1OFCON.6; 436 PWM1OFCON_OFM0 : bit absolute PWM1OFCON.5; 437 PWM1OFCON_OFO : bit absolute PWM1OFCON.4; 438 PWM1OFCON_OFS1 : bit absolute PWM1OFCON.1; 439 PWM1OFCON_OFS0 : bit absolute PWM1OFCON.0; 440 PWM2PHL : byte absolute $0DA1; 441 PWM2PHH : byte absolute $0DA2; 442 PWM2DCL : byte absolute $0DA3; 443 PWM2DCH : byte absolute $0DA4; 444 PWM2PRL : byte absolute $0DA5; 445 PWM2PRH : byte absolute $0DA6; 446 PWM2OFL : byte absolute $0DA7; 447 PWM2OFH : byte absolute $0DA8; 448 PWM2TMRL : byte absolute $0DA9; 449 PWM2TMRH : byte absolute $0DAA; 450 PWM2CON : byte absolute $0DAB; 451 PWM2INTE : byte absolute $0DAC; 452 PWM2INTF : byte absolute $0DAD; 453 PWM2CLKCON : byte absolute $0DAE; 454 PWM2LDCON : byte absolute $0DAF; 455 PWM2OFCON : byte absolute $0DB0; 456 PWM3PHL : byte absolute $0DB1; 457 PWM3PHH : byte absolute $0DB2; 458 PWM3DCL : byte absolute $0DB3; 459 PWM3DCH : byte absolute $0DB4; 460 PWM3PRL : byte absolute $0DB5; 461 PWM3PRH : byte absolute $0DB6; 462 PWM3OFL : byte absolute $0DB7; 463 PWM3OFH : byte absolute $0DB8; 464 PWM3TMRL : byte absolute $0DB9; 465 PWM3TMRH : byte absolute $0DBA; 466 PWM3CON : byte absolute $0DBB; 467 PWM3INTE : byte absolute $0DBC; 468 PWM3INTF : byte absolute $0DBD; 469 PWM3CLKCON : byte absolute $0DBE; 470 PWM3LDCON : byte absolute $0DBF; 471 PWM3OFCON : byte absolute $0DC0; 472 STATUS_SHAD : byte absolute $0FE4; 473 STATUS_SHAD_Z_SHAD : bit absolute STATUS_SHAD.2; 474 STATUS_SHAD_DC_SHAD : bit absolute STATUS_SHAD.1; 475 STATUS_SHAD_C_SHAD : bit absolute STATUS_SHAD.0; 476 WREG_SHAD : byte absolute $0FE5; 477 BSR_SHAD : byte absolute $0FE6; 478 BSR_SHAD_BSR_SHAD4 : bit absolute BSR_SHAD.4; 479 BSR_SHAD_BSR_SHAD3 : bit absolute BSR_SHAD.3; 480 BSR_SHAD_BSR_SHAD2 : bit absolute BSR_SHAD.2; 481 BSR_SHAD_BSR_SHAD1 : bit absolute BSR_SHAD.1; 482 BSR_SHAD_BSR_SHAD0 : bit absolute BSR_SHAD.0; 483 PCLATH_SHAD : byte absolute $0FE7; 484 PCLATH_SHAD_PCLATH_SHAD6 : bit absolute PCLATH_SHAD.6; 485 PCLATH_SHAD_PCLATH_SHAD5 : bit absolute PCLATH_SHAD.5; 486 PCLATH_SHAD_PCLATH_SHAD4 : bit absolute PCLATH_SHAD.4; 487 PCLATH_SHAD_PCLATH_SHAD3 : bit absolute PCLATH_SHAD.3; 488 PCLATH_SHAD_PCLATH_SHAD2 : bit absolute PCLATH_SHAD.2; 489 PCLATH_SHAD_PCLATH_SHAD1 : bit absolute PCLATH_SHAD.1; 490 PCLATH_SHAD_PCLATH_SHAD0 : bit absolute PCLATH_SHAD.0; 491 FSR0L_SHAD : byte absolute $0FE8; 492 FSR0H_SHAD : byte absolute $0FE9; 493 FSR1L_SHAD : byte absolute $0FEA; 494 FSR1H_SHAD : byte absolute $0FEB; 495 STKPTR : byte absolute $0FED; 496 STKPTR_STKPTR4 : bit absolute STKPTR.4; 497 STKPTR_STKPTR3 : bit absolute STKPTR.3; 498 STKPTR_STKPTR2 : bit absolute STKPTR.2; 499 STKPTR_STKPTR1 : bit absolute STKPTR.1; 500 STKPTR_STKPTR0 : bit absolute STKPTR.0; 501 TOSL : byte absolute $0FEE; 502 TOSH : byte absolute $0FEF; 503 TOSH_TOSH6 : bit absolute TOSH.6; 504 TOSH_TOSH5 : bit absolute TOSH.5; 505 TOSH_TOSH4 : bit absolute TOSH.4; 506 TOSH_TOSH3 : bit absolute TOSH.3; 507 TOSH_TOSH2 : bit absolute TOSH.2; 508 TOSH_TOSH1 : bit absolute TOSH.1; 509 TOSH_TOSH0 : bit absolute TOSH.0; 510 511 512 // -- Define RAM state values -- 513 514 {$CLEAR_STATE_RAM} 515 516 {$SET_STATE_RAM '000-00B:SFR:ALLMAPPED'} // Banks 0-31 : INDF0, INDF1, PCL, STATUS, FSR0L, FSR0H, FSR1L, FSR1H, BSR, WREG, PCLATH, INTCON 517 {$SET_STATE_RAM '00C-00C:SFR'} // Bank 0 : PORTA 518 {$SET_STATE_RAM '011-013:SFR'} // Bank 0 : PIR1, PIR2, PIR3 519 {$SET_STATE_RAM '015-01C:SFR'} // Bank 0 : TMR0, TMR1L, TMR1H, T1CON, T1GCON, TMR2, PR2, T2CON 520 {$SET_STATE_RAM '020-06F:GPR'} 521 {$SET_STATE_RAM '070-07F:GPR:ALLMAPPED'} 522 {$SET_STATE_RAM '08C-08C:SFR'} // Bank 1 : TRISA 523 {$SET_STATE_RAM '091-093:SFR'} // Bank 1 : PIE1, PIE2, PIE3 524 {$SET_STATE_RAM '095-09F:SFR'} // Bank 1 : OPTION_REG, PCON, WDTCON, OSCTUNE, OSCCON, OSCSTAT, ADRESL, ADRESH, ADCON0, ADCON1, ADCON2 525 {$SET_STATE_RAM '0A0-0EF:GPR'} 526 {$SET_STATE_RAM '10C-10C:SFR'} // Bank 2 : LATA 527 {$SET_STATE_RAM '111-112:SFR'} // Bank 2 : CM1CON0, CM1CON1 528 {$SET_STATE_RAM '115-119:SFR'} // Bank 2 : CMOUT, BORCON, FVRCON, DACCON0, DACCON1 529 {$SET_STATE_RAM '11D-11D:SFR'} // Bank 2 : APFCON 530 {$SET_STATE_RAM '120-16F:GPR'} 531 {$SET_STATE_RAM '18C-18C:SFR'} // Bank 3 : ANSELA 532 {$SET_STATE_RAM '191-197:SFR'} // Bank 3 : PMADRL, PMADRH, PMDATL, PMDATH, PMCON1, PMCON2, VREGCON 533 {$SET_STATE_RAM '199-19F:SFR'} // Bank 3 : RCREG, TXREG, SPBRGL, SPBRGH, RCSTA, TXSTA, BAUDCON 534 {$SET_STATE_RAM '20C-20C:SFR'} // Bank 4 : WPUA 535 {$SET_STATE_RAM '28C-28C:SFR'} // Bank 5 : ODCONA 536 {$SET_STATE_RAM '30C-30C:SFR'} // Bank 6 : SLRCONA 537 {$SET_STATE_RAM '38C-38C:SFR'} // Bank 7 : INLVLA 538 {$SET_STATE_RAM '391-393:SFR'} // Bank 7 : IOCAP, IOCAN, IOCAF 539 {$SET_STATE_RAM '691-695:SFR'} // Bank 13 : CWG1DBR, CWG1DBF, CWG1CON0, CWG1CON1, CWG1CON2 540 {$SET_STATE_RAM 'D8E-DC0:SFR'} // Bank 27 : PWMEN, PWMLD, PWMOUT, PWM1PHL, PWM1PHH, PWM1DCL, PWM1DCH, PWM1PRL, PWM1PRH, PWM1OFL, PWM1OFH, PWM1TMRL, PWM1TMRH, PWM1CON, PWM1INTE, PWM1INTF, PWM1CLKCON, PWM1LDCON, PWM1OFCON, PWM2PHL, PWM2PHH, PWM2DCL, PWM2DCH, PWM2PRL, PWM2PRH, PWM2OFL, PWM2OFH, PWM2TMRL, PWM2TMRH, PWM2CON, PWM2INTE, PWM2INTF, PWM2CLKCON, PWM2LDCON, PWM2OFCON, PWM3PHL, PWM3PHH, PWM3DCL, PWM3DCH, PWM3PRL, PWM3PRH, PWM3OFL, PWM3OFH, PWM3TMRL, PWM3TMRH, PWM3CON, PWM3INTE, PWM3INTF, PWM3CLKCON, PWM3LDCON, PWM3OFCON 541 {$SET_STATE_RAM 'FE4-FEB:SFR'} // Bank 31 : STATUS_SHAD, WREG_SHAD, BSR_SHAD, PCLATH_SHAD, FSR0L_SHAD, FSR0H_SHAD, FSR1L_SHAD, FSR1H_SHAD 542 {$SET_STATE_RAM 'FED-FEF:SFR'} // Bank 31 : STKPTR, TOSL, TOSH 543 544 545 // -- Define mapped RAM -- 546 547 548 549 550 // -- Un-implemented fields -- 551 552 {$SET_UNIMP_BITS '003:1F'} // STATUS bits 7,6,5 un-implemented (read as 0) 553 {$SET_UNIMP_BITS '008:1F'} // BSR bits 7,6,5 un-implemented (read as 0) 554 {$SET_UNIMP_BITS '00A:7F'} // PCLATH bit 7 un-implemented (read as 0) 555 {$SET_UNIMP_BITS '00C:3F'} // PORTA bits 7,6 un-implemented (read as 0) 556 {$SET_UNIMP_BITS '011:F3'} // PIR1 bits 3,2 un-implemented (read as 0) 557 {$SET_UNIMP_BITS '012:20'} // PIR2 bits 7,6,4,3,2,1,0 un-implemented (read as 0) 558 {$SET_UNIMP_BITS '013:70'} // PIR3 bits 7,3,2,1,0 un-implemented (read as 0) 559 {$SET_UNIMP_BITS '018:F5'} // T1CON bits 3,1 un-implemented (read as 0) 560 {$SET_UNIMP_BITS '01C:7F'} // T2CON bit 7 un-implemented (read as 0) 561 {$SET_UNIMP_BITS '08C:3F'} // TRISA bits 7,6 un-implemented (read as 0) 562 {$SET_UNIMP_BITS '091:F3'} // PIE1 bits 3,2 un-implemented (read as 0) 563 {$SET_UNIMP_BITS '092:20'} // PIE2 bits 7,6,4,3,2,1,0 un-implemented (read as 0) 564 {$SET_UNIMP_BITS '093:70'} // PIE3 bits 7,3,2,1,0 un-implemented (read as 0) 565 {$SET_UNIMP_BITS '096:DF'} // PCON bit 5 un-implemented (read as 0) 566 {$SET_UNIMP_BITS '097:3F'} // WDTCON bits 7,6 un-implemented (read as 0) 567 {$SET_UNIMP_BITS '098:3F'} // OSCTUNE bits 7,6 un-implemented (read as 0) 568 {$SET_UNIMP_BITS '099:FB'} // OSCCON bit 2 un-implemented (read as 0) 569 {$SET_UNIMP_BITS '09A:7F'} // OSCSTAT bit 7 un-implemented (read as 0) 570 {$SET_UNIMP_BITS '09D:7F'} // ADCON0 bit 7 un-implemented (read as 0) 571 {$SET_UNIMP_BITS '09E:F3'} // ADCON1 bits 3,2 un-implemented (read as 0) 572 {$SET_UNIMP_BITS '09F:F0'} // ADCON2 bits 3,2,1,0 un-implemented (read as 0) 573 {$SET_UNIMP_BITS '10C:37'} // LATA bits 7,6,3 un-implemented (read as 0) 574 {$SET_UNIMP_BITS '111:F7'} // CM1CON0 bit 3 un-implemented (read as 0) 575 {$SET_UNIMP_BITS '112:F7'} // CM1CON1 bit 3 un-implemented (read as 0) 576 {$SET_UNIMP_BITS '115:01'} // CMOUT bits 7,6,5,4,3,2,1 un-implemented (read as 0) 577 {$SET_UNIMP_BITS '116:C1'} // BORCON bits 5,4,3,2,1 un-implemented (read as 0) 578 {$SET_UNIMP_BITS '118:EC'} // DACCON0 bits 4,1,0 un-implemented (read as 0) 579 {$SET_UNIMP_BITS '119:1F'} // DACCON1 bits 7,6,5 un-implemented (read as 0) 580 {$SET_UNIMP_BITS '11D:EF'} // APFCON bit 4 un-implemented (read as 0) 581 {$SET_UNIMP_BITS '18C:17'} // ANSELA bits 7,6,5,3 un-implemented (read as 0) 582 {$SET_UNIMP_BITS '192:7F'} // PMADRH bit 7 un-implemented (read as 0) 583 {$SET_UNIMP_BITS '194:3F'} // PMDATH bits 7,6 un-implemented (read as 0) 584 {$SET_UNIMP_BITS '195:7F'} // PMCON1 bit 7 un-implemented (read as 0) 585 {$SET_UNIMP_BITS '197:02'} // VREGCON bits 7,6,5,4,3,2,0 un-implemented (read as 0) 586 {$SET_UNIMP_BITS '19F:DB'} // BAUDCON bits 5,2 un-implemented (read as 0) 587 {$SET_UNIMP_BITS '20C:3F'} // WPUA bits 7,6 un-implemented (read as 0) 588 {$SET_UNIMP_BITS '28C:37'} // ODCONA bits 7,6,3 un-implemented (read as 0) 589 {$SET_UNIMP_BITS '30C:37'} // SLRCONA bits 7,6,3 un-implemented (read as 0) 590 {$SET_UNIMP_BITS '38C:3F'} // INLVLA bits 7,6 un-implemented (read as 0) 591 {$SET_UNIMP_BITS '391:3F'} // IOCAP bits 7,6 un-implemented (read as 0) 592 {$SET_UNIMP_BITS '392:3F'} // IOCAN bits 7,6 un-implemented (read as 0) 593 {$SET_UNIMP_BITS '393:3F'} // IOCAF bits 7,6 un-implemented (read as 0) 594 {$SET_UNIMP_BITS '691:3F'} // CWG1DBR bits 7,6 un-implemented (read as 0) 595 {$SET_UNIMP_BITS '692:3F'} // CWG1DBF bits 7,6 un-implemented (read as 0) 596 {$SET_UNIMP_BITS '693:F9'} // CWG1CON0 bits 2,1 un-implemented (read as 0) 597 {$SET_UNIMP_BITS '694:F7'} // CWG1CON1 bit 3 un-implemented (read as 0) 598 {$SET_UNIMP_BITS '695:C6'} // CWG1CON2 bits 5,4,3,0 un-implemented (read as 0) 599 {$SET_UNIMP_BITS 'D8E:07'} // PWMEN bits 7,6,5,4,3 un-implemented (read as 0) 600 {$SET_UNIMP_BITS 'D8F:07'} // PWMLD bits 7,6,5,4,3 un-implemented (read as 0) 601 {$SET_UNIMP_BITS 'D90:07'} // PWMOUT bits 7,6,5,4,3 un-implemented (read as 0) 602 {$SET_UNIMP_BITS 'D9B:FC'} // PWM1CON bits 1,0 un-implemented (read as 0) 603 {$SET_UNIMP_BITS 'D9C:0F'} // PWM1INTE bits 7,6,5,4 un-implemented (read as 0) 604 {$SET_UNIMP_BITS 'D9D:0F'} // PWM1INTF bits 7,6,5,4 un-implemented (read as 0) 605 {$SET_UNIMP_BITS 'D9E:73'} // PWM1CLKCON bits 7,3,2 un-implemented (read as 0) 606 {$SET_UNIMP_BITS 'D9F:C3'} // PWM1LDCON bits 5,4,3,2 un-implemented (read as 0) 607 {$SET_UNIMP_BITS 'DA0:73'} // PWM1OFCON bits 7,3,2 un-implemented (read as 0) 608 {$SET_UNIMP_BITS 'DAB:FC'} // PWM2CON bits 1,0 un-implemented (read as 0) 609 {$SET_UNIMP_BITS 'DAC:0F'} // PWM2INTE bits 7,6,5,4 un-implemented (read as 0) 610 {$SET_UNIMP_BITS 'DAD:0F'} // PWM2INTF bits 7,6,5,4 un-implemented (read as 0) 611 {$SET_UNIMP_BITS 'DAE:73'} // PWM2CLKCON bits 7,3,2 un-implemented (read as 0) 612 {$SET_UNIMP_BITS 'DAF:C3'} // PWM2LDCON bits 5,4,3,2 un-implemented (read as 0) 613 {$SET_UNIMP_BITS 'DB0:73'} // PWM2OFCON bits 7,3,2 un-implemented (read as 0) 614 {$SET_UNIMP_BITS 'DBB:FC'} // PWM3CON bits 1,0 un-implemented (read as 0) 615 {$SET_UNIMP_BITS 'DBC:0F'} // PWM3INTE bits 7,6,5,4 un-implemented (read as 0) 616 {$SET_UNIMP_BITS 'DBD:0F'} // PWM3INTF bits 7,6,5,4 un-implemented (read as 0) 617 {$SET_UNIMP_BITS 'DBE:73'} // PWM3CLKCON bits 7,3,2 un-implemented (read as 0) 618 {$SET_UNIMP_BITS 'DBF:C3'} // PWM3LDCON bits 5,4,3,2 un-implemented (read as 0) 619 {$SET_UNIMP_BITS 'DC0:73'} // PWM3OFCON bits 7,3,2 un-implemented (read as 0) 620 {$SET_UNIMP_BITS 'FE4:07'} // STATUS_SHAD bits 7,6,5,4,3 un-implemented (read as 0) 621 {$SET_UNIMP_BITS 'FE6:1F'} // BSR_SHAD bits 7,6,5 un-implemented (read as 0) 622 {$SET_UNIMP_BITS 'FE7:7F'} // PCLATH_SHAD bit 7 un-implemented (read as 0) 623 {$SET_UNIMP_BITS 'FED:1F'} // STKPTR bits 7,6,5 un-implemented (read as 0) 624 {$SET_UNIMP_BITS 'FEF:7F'} // TOSH bit 7 un-implemented (read as 0) 625 626 627 // -- PIN mapping -- 628 629 // Pin 1 : Vdd 630 // Pin 2 : RA5/T1CKI/CWG1A/PWM1/RX/DT/CLKIN 631 // Pin 3 : T1G/RA4/AN3/C1IN1-/PWM2/TX/CK/CWG1B/CLKOUT 632 // Pin 4 : RA3/T1G/MCLR/Vpp 633 // Pin 5 : RA2/AN2/T0CKI/PWM3/C1OUT/CWG1FLT/CWG1A/INT 634 // Pin 6 : RA1/AN1/VREF+/C1IN0-/PWM1/RX/DT/ICSPCLK/ICDCLK 635 // Pin 7 : RA0/AN0/C1IN+/PWM2/TX/CK/DAC1OUT/CWG1B/ICSPDAT/ICDDAT 636 // Pin 8 : Vss 637 638 639 // -- RAM to PIN mapping -- 640 641 {$MAP_RAM_TO_PIN '00C:0-7,1-6,2-5,3-4,4-3,5-2'} // PORTA 642 643 644 // -- Bits Configuration -- 645 646 // FOSC : 647 {$define _FOSC_ECH = $3FFF} // ECH, External Clock, High Power Mode (4-32 MHz); device clock supplied to CLKIN pin 648 {$define _FOSC_ECM = $3FFE} // ECM, External Clock, Medium Power Mode (0.5-4 MHz); device clock supplied to CLKIN pin 649 {$define _FOSC_ECL = $3FFD} // ECL, External Clock, Low Power Mode (0-0.5 MHz); device clock supplied to CLKIN pin 650 {$define _FOSC_INTOSC = $3FFC} // INTOSC oscillator; I/O function on CLKIN pin 651 652 // WDTE : Watchdog Timer Enable 653 {$define _WDTE_ON = $3FFF} // WDT enabled 654 {$define _WDTE_NSLEEP = $3FF7} // WDT enabled while running and disabled in Sleep 655 {$define _WDTE_SWDTEN = $3FEF} // WDT controlled by the SWDTEN bit in the WDTCON register 656 {$define _WDTE_OFF = $3FE7} // WDT disabled 657 658 // PWRTE : Power-up Timer Enable 659 {$define _PWRTE_OFF = $3FFF} // PWRT disabled 660 {$define _PWRTE_ON = $3FDF} // PWRT enabled 661 662 // MCLRE : MCLR Pin Function Select 663 {$define _MCLRE_ON = $3FFF} // MCLR/VPP pin function is MCLR 664 {$define _MCLRE_OFF = $3FBF} // MCLR/VPP pin function is digital input 665 666 // CP : Flash Program Memory Code Protection 667 {$define _CP_OFF = $3FFF} // Program memory code protection is disabled 668 {$define _CP_ON = $3F7F} // Program memory code protection is enabled 669 670 // BOREN : Brown-out Reset Enable 671 {$define _BOREN_ON = $3FFF} // Brown-out Reset enabled 672 {$define _BOREN_NSLEEP = $3DFF} // Brown-out Reset enabled while running and disabled in Sleep 673 {$define _BOREN_SBODEN = $3BFF} // Brown-out Reset controlled by the SBOREN bit in the BORCON register 674 {$define _BOREN_OFF = $39FF} // Brown-out Reset disabled 675 676 // CLKOUTEN : Clock Out Enable 677 {$define _CLKOUTEN_OFF = $3FFF} // CLKOUT function is disabled. I/O or oscillator function on the CLKOUT pin 678 {$define _CLKOUTEN_ON = $37FF} // CLKOUT function is enabled on the CLKOUT pin 679 680 // WRT : Flash Memory Self-Write Protection 681 {$define _WRT_OFF = $3FFF} // Write protection off 682 {$define _WRT_BOOT = $3FFE} // 000h to 1FFh write protected, 200h to 7FFh may be modified by EECON control 683 {$define _WRT_HALF = $3FFD} // 000h to 3FFh write protected, 400h to 7FFh may be modified by EECON control 684 {$define _WRT_ALL = $3FFC} // 000h to 7FFh write protected, no addresses may be modified by EECON control 685 686 // PLLEN : PLL Enable 687 {$define _PLLEN_ON = $3FFF} // 4x PLL enabled 688 {$define _PLLEN_OFF = $3EFF} // 4x PLL disabled 689 690 // STVREN : Stack Overflow/Underflow Reset Enable 691 {$define _STVREN_ON = $3FFF} // Stack Overflow or Underflow will cause a Reset 692 {$define _STVREN_OFF = $3DFF} // Stack Overflow or Underflow will not cause a Reset 693 694 // BORV : Brown-out Reset Voltage Selection 695 {$define _BORV_LO = $3FFF} // Brown-out Reset Voltage (Vbor), low trip point selected. 696 {$define _BORV_HI = $3BFF} // Brown-out Reset Voltage (Vbor), high trip point selected. 697 698 // LPBOREN : Low Power Brown-out Reset enable bit 699 {$define _LPBOREN_OFF = $3FFF} // LPBOR is disabled 700 {$define _LPBOREN_ON = $37FF} // LPBOR is enabled 701 702 // LVP : Low-Voltage Programming Enable 703 {$define _LVP_ON = $3FFF} // Low-voltage programming enabled 704 {$define _LVP_OFF = $1FFF} // High-voltage on MCLR/VPP must be used for programming 705 706 implementation 707 end. 708