1 // Copyright 2017 Citra Emulator Project
2 // Licensed under GPLv2 or any later version
3 // Refer to the license.txt file included.
4 
5 #pragma once
6 
7 #include <array>
8 #include <cstddef>
9 #include <string>
10 
11 #include "common/common_funcs.h"
12 #include "common/common_types.h"
13 #include "video_core/regs_framebuffer.h"
14 #include "video_core/regs_lighting.h"
15 #include "video_core/regs_pipeline.h"
16 #include "video_core/regs_rasterizer.h"
17 #include "video_core/regs_shader.h"
18 #include "video_core/regs_texturing.h"
19 
20 namespace Pica {
21 
22 #define PICA_REG_INDEX(field_name) (offsetof(Pica::Regs, field_name) / sizeof(u32))
23 
24 struct Regs {
25     static constexpr std::size_t NUM_REGS = 0x300;
26 
27     union {
28         struct {
29             INSERT_PADDING_WORDS(0x10);
30             u32 trigger_irq;
31             INSERT_PADDING_WORDS(0x2f);
32             RasterizerRegs rasterizer;
33             TexturingRegs texturing;
34             FramebufferRegs framebuffer;
35             LightingRegs lighting;
36             PipelineRegs pipeline;
37             ShaderRegs gs;
38             ShaderRegs vs;
39             INSERT_PADDING_WORDS(0x20);
40         };
41         std::array<u32, NUM_REGS> reg_array;
42     };
43 
44     /// Map register indices to names readable by humans
45     static const char* GetRegisterName(u16 index);
46 };
47 
48 static_assert(sizeof(Regs) == Regs::NUM_REGS * sizeof(u32), "Regs struct has wrong size");
49 
50 #define ASSERT_REG_POSITION(field_name, position)                                                  \
51     static_assert(offsetof(Regs, field_name) == position * 4,                                      \
52                   "Field " #field_name " has invalid position")
53 
54 ASSERT_REG_POSITION(trigger_irq, 0x10);
55 
56 ASSERT_REG_POSITION(rasterizer, 0x40);
57 ASSERT_REG_POSITION(rasterizer.cull_mode, 0x40);
58 ASSERT_REG_POSITION(rasterizer.viewport_size_x, 0x41);
59 ASSERT_REG_POSITION(rasterizer.viewport_size_y, 0x43);
60 ASSERT_REG_POSITION(rasterizer.viewport_depth_range, 0x4d);
61 ASSERT_REG_POSITION(rasterizer.viewport_depth_near_plane, 0x4e);
62 ASSERT_REG_POSITION(rasterizer.vs_output_attributes[0], 0x50);
63 ASSERT_REG_POSITION(rasterizer.vs_output_attributes[1], 0x51);
64 ASSERT_REG_POSITION(rasterizer.scissor_test, 0x65);
65 ASSERT_REG_POSITION(rasterizer.viewport_corner, 0x68);
66 ASSERT_REG_POSITION(rasterizer.depthmap_enable, 0x6D);
67 
68 ASSERT_REG_POSITION(texturing, 0x80);
69 ASSERT_REG_POSITION(texturing.main_config, 0x80);
70 ASSERT_REG_POSITION(texturing.texture0, 0x81);
71 ASSERT_REG_POSITION(texturing.texture0_format, 0x8e);
72 ASSERT_REG_POSITION(texturing.fragment_lighting_enable, 0x8f);
73 ASSERT_REG_POSITION(texturing.texture1, 0x91);
74 ASSERT_REG_POSITION(texturing.texture1_format, 0x96);
75 ASSERT_REG_POSITION(texturing.texture2, 0x99);
76 ASSERT_REG_POSITION(texturing.texture2_format, 0x9e);
77 ASSERT_REG_POSITION(texturing.proctex, 0xa8);
78 ASSERT_REG_POSITION(texturing.proctex_noise_u, 0xa9);
79 ASSERT_REG_POSITION(texturing.proctex_noise_v, 0xaa);
80 ASSERT_REG_POSITION(texturing.proctex_noise_frequency, 0xab);
81 ASSERT_REG_POSITION(texturing.proctex_lut, 0xac);
82 ASSERT_REG_POSITION(texturing.proctex_lut_offset, 0xad);
83 ASSERT_REG_POSITION(texturing.proctex_lut_config, 0xaf);
84 ASSERT_REG_POSITION(texturing.tev_stage0, 0xc0);
85 ASSERT_REG_POSITION(texturing.tev_stage1, 0xc8);
86 ASSERT_REG_POSITION(texturing.tev_stage2, 0xd0);
87 ASSERT_REG_POSITION(texturing.tev_stage3, 0xd8);
88 ASSERT_REG_POSITION(texturing.tev_combiner_buffer_input, 0xe0);
89 ASSERT_REG_POSITION(texturing.fog_mode, 0xe0);
90 ASSERT_REG_POSITION(texturing.fog_color, 0xe1);
91 ASSERT_REG_POSITION(texturing.fog_lut_offset, 0xe6);
92 ASSERT_REG_POSITION(texturing.fog_lut_data, 0xe8);
93 ASSERT_REG_POSITION(texturing.tev_stage4, 0xf0);
94 ASSERT_REG_POSITION(texturing.tev_stage5, 0xf8);
95 ASSERT_REG_POSITION(texturing.tev_combiner_buffer_color, 0xfd);
96 
97 ASSERT_REG_POSITION(framebuffer, 0x100);
98 ASSERT_REG_POSITION(framebuffer.output_merger, 0x100);
99 ASSERT_REG_POSITION(framebuffer.framebuffer, 0x110);
100 
101 ASSERT_REG_POSITION(lighting, 0x140);
102 
103 ASSERT_REG_POSITION(pipeline, 0x200);
104 ASSERT_REG_POSITION(pipeline.vertex_attributes, 0x200);
105 ASSERT_REG_POSITION(pipeline.index_array, 0x227);
106 ASSERT_REG_POSITION(pipeline.num_vertices, 0x228);
107 ASSERT_REG_POSITION(pipeline.vertex_offset, 0x22a);
108 ASSERT_REG_POSITION(pipeline.trigger_draw, 0x22e);
109 ASSERT_REG_POSITION(pipeline.trigger_draw_indexed, 0x22f);
110 ASSERT_REG_POSITION(pipeline.vs_default_attributes_setup, 0x232);
111 ASSERT_REG_POSITION(pipeline.command_buffer, 0x238);
112 ASSERT_REG_POSITION(pipeline.gpu_mode, 0x245);
113 ASSERT_REG_POSITION(pipeline.triangle_topology, 0x25e);
114 ASSERT_REG_POSITION(pipeline.restart_primitive, 0x25f);
115 
116 ASSERT_REG_POSITION(gs, 0x280);
117 ASSERT_REG_POSITION(vs, 0x2b0);
118 
119 #undef ASSERT_REG_POSITION
120 } // namespace Pica
121