1 /*
2 armvfp.c - ARM VFPv3 emulation unit
3 Copyright (C) 2003 Skyeye Develop Group
4 for help please send mail to <skyeye-developer@lists.gro.clinux.org>
5
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2 of the License, or
9 (at your option) any later version.
10
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21 /* Note: this file handles interface with arm core and vfp registers */
22
23 #include "common/common_funcs.h"
24 #include "common/common_types.h"
25 #include "common/logging/log.h"
26 #include "core/arm/skyeye_common/armstate.h"
27 #include "core/arm/skyeye_common/vfp/asm_vfp.h"
28 #include "core/arm/skyeye_common/vfp/vfp.h"
29
VFPInit(ARMul_State * state)30 void VFPInit(ARMul_State* state) {
31 state->VFP[VFP_FPSID] = VFP_FPSID_IMPLMEN << 24 | VFP_FPSID_SW << 23 | VFP_FPSID_SUBARCH << 16 |
32 VFP_FPSID_PARTNUM << 8 | VFP_FPSID_VARIANT << 4 | VFP_FPSID_REVISION;
33 state->VFP[VFP_FPEXC] = 0;
34 state->VFP[VFP_FPSCR] = 0;
35
36 // ARM11 MPCore instruction register reset values.
37 state->VFP[VFP_FPINST] = 0xEE000A00;
38 state->VFP[VFP_FPINST2] = 0;
39
40 // ARM11 MPCore feature register values.
41 state->VFP[VFP_MVFR0] = 0x11111111;
42 state->VFP[VFP_MVFR1] = 0;
43 }
44
VMOVBRS(ARMul_State * state,u32 to_arm,u32 t,u32 n,u32 * value)45 void VMOVBRS(ARMul_State* state, u32 to_arm, u32 t, u32 n, u32* value) {
46 if (to_arm) {
47 *value = state->ExtReg[n];
48 } else {
49 state->ExtReg[n] = *value;
50 }
51 }
52
VMOVBRRD(ARMul_State * state,u32 to_arm,u32 t,u32 t2,u32 n,u32 * value1,u32 * value2)53 void VMOVBRRD(ARMul_State* state, u32 to_arm, u32 t, u32 t2, u32 n, u32* value1, u32* value2) {
54 if (to_arm) {
55 *value2 = state->ExtReg[n * 2 + 1];
56 *value1 = state->ExtReg[n * 2];
57 } else {
58 state->ExtReg[n * 2 + 1] = *value2;
59 state->ExtReg[n * 2] = *value1;
60 }
61 }
VMOVBRRSS(ARMul_State * state,u32 to_arm,u32 t,u32 t2,u32 n,u32 * value1,u32 * value2)62 void VMOVBRRSS(ARMul_State* state, u32 to_arm, u32 t, u32 t2, u32 n, u32* value1, u32* value2) {
63 if (to_arm) {
64 *value1 = state->ExtReg[n + 0];
65 *value2 = state->ExtReg[n + 1];
66 } else {
67 state->ExtReg[n + 0] = *value1;
68 state->ExtReg[n + 1] = *value2;
69 }
70 }
71
VMOVI(ARMul_State * state,u32 single,u32 d,u32 imm)72 void VMOVI(ARMul_State* state, u32 single, u32 d, u32 imm) {
73 if (single) {
74 state->ExtReg[d] = imm;
75 } else {
76 /* Check endian please */
77 state->ExtReg[d * 2 + 1] = imm;
78 state->ExtReg[d * 2] = 0;
79 }
80 }
VMOVR(ARMul_State * state,u32 single,u32 d,u32 m)81 void VMOVR(ARMul_State* state, u32 single, u32 d, u32 m) {
82 if (single) {
83 state->ExtReg[d] = state->ExtReg[m];
84 } else {
85 /* Check endian please */
86 state->ExtReg[d * 2 + 1] = state->ExtReg[m * 2 + 1];
87 state->ExtReg[d * 2] = state->ExtReg[m * 2];
88 }
89 }
90
91 /* Miscellaneous functions */
vfp_get_float(ARMul_State * state,unsigned int reg)92 s32 vfp_get_float(ARMul_State* state, unsigned int reg) {
93 LOG_TRACE(Core_ARM11, "VFP get float: s{}=[{:08x}]", reg, state->ExtReg[reg]);
94 return state->ExtReg[reg];
95 }
96
vfp_put_float(ARMul_State * state,s32 val,unsigned int reg)97 void vfp_put_float(ARMul_State* state, s32 val, unsigned int reg) {
98 LOG_TRACE(Core_ARM11, "VFP put float: s{} <= [{:08x}]", reg, val);
99 state->ExtReg[reg] = val;
100 }
101
vfp_get_double(ARMul_State * state,unsigned int reg)102 u64 vfp_get_double(ARMul_State* state, unsigned int reg) {
103 u64 result = ((u64)state->ExtReg[reg * 2 + 1]) << 32 | state->ExtReg[reg * 2];
104 LOG_TRACE(Core_ARM11, "VFP get double: s[{}-{}]=[{:016llx}]", reg * 2 + 1, reg * 2, result);
105 return result;
106 }
107
vfp_put_double(ARMul_State * state,u64 val,unsigned int reg)108 void vfp_put_double(ARMul_State* state, u64 val, unsigned int reg) {
109 LOG_TRACE(Core_ARM11, "VFP put double: s[{}-{}] <= [{:08x}-{:08x}]", reg * 2 + 1, reg * 2,
110 (u32)(val >> 32), (u32)(val & 0xffffffff));
111 state->ExtReg[reg * 2] = (u32)(val & 0xffffffff);
112 state->ExtReg[reg * 2 + 1] = (u32)(val >> 32);
113 }
114
115 /*
116 * Process bitmask of exception conditions. (from vfpmodule.c)
117 */
vfp_raise_exceptions(ARMul_State * state,u32 exceptions,u32 inst,u32 fpscr)118 void vfp_raise_exceptions(ARMul_State* state, u32 exceptions, u32 inst, u32 fpscr) {
119 LOG_TRACE(Core_ARM11, "VFP: raising exceptions {:08x}", exceptions);
120
121 if (exceptions == VFP_EXCEPTION_ERROR) {
122 LOG_CRITICAL(Core_ARM11, "unhandled bounce {:x}", inst);
123 Crash();
124 }
125
126 /*
127 * If any of the status flags are set, update the FPSCR.
128 * Comparison instructions always return at least one of
129 * these flags set.
130 */
131 if (exceptions & (FPSCR_NFLAG | FPSCR_ZFLAG | FPSCR_CFLAG | FPSCR_VFLAG))
132 fpscr &= ~(FPSCR_NFLAG | FPSCR_ZFLAG | FPSCR_CFLAG | FPSCR_VFLAG);
133
134 fpscr |= exceptions;
135
136 state->VFP[VFP_FPSCR] = fpscr;
137 }
138