1 /*
2 * Copyright (C) 2002-2010 The DOSBox Team
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
17 */
18
19 #ifndef DOSBOX_REGS_H
20 #define DOSBOX_REGS_H
21
22 #ifndef DOSBOX_MEM_H
23 #include "mem.h"
24 #endif
25
26 #define FLAG_CF 0x00000001
27 #define FLAG_PF 0x00000004
28 #define FLAG_AF 0x00000010
29 #define FLAG_ZF 0x00000040
30 #define FLAG_SF 0x00000080
31 #define FLAG_OF 0x00000800
32
33 #define FLAG_TF 0x00000100
34 #define FLAG_IF 0x00000200
35 #define FLAG_DF 0x00000400
36
37 #define FLAG_IOPL 0x00003000
38 #define FLAG_NT 0x00004000
39 #define FLAG_VM 0x00020000
40 #define FLAG_AC 0x00040000
41 #define FLAG_ID 0x00200000
42
43 #define FMASK_TEST (FLAG_CF | FLAG_PF | FLAG_AF | FLAG_ZF | FLAG_SF | FLAG_OF)
44 #define FMASK_NORMAL (FMASK_TEST | FLAG_DF | FLAG_TF | FLAG_IF | FLAG_AC )
45 #define FMASK_ALL (FMASK_NORMAL | FLAG_IOPL | FLAG_NT)
46
47 #define SETFLAGBIT(TYPE,TEST) if (TEST) reg_flags|=FLAG_ ## TYPE; else reg_flags&=~FLAG_ ## TYPE
48
49 #define GETFLAG(TYPE) (reg_flags & FLAG_ ## TYPE)
50 #define GETFLAGBOOL(TYPE) ((reg_flags & FLAG_ ## TYPE) ? true : false )
51
52 #define GETFLAG_IOPL ((reg_flags & FLAG_IOPL) >> 12)
53
54 struct Segment {
55 Bit16u val;
56 PhysPt phys; /* The phyiscal address start in emulated machine */
57 };
58
59 enum SegNames { es=0,cs,ss,ds,fs,gs};
60
61 struct Segments {
62 Bitu val[8];
63 PhysPt phys[8];
64 };
65
66 union GenReg32 {
67 Bit32u dword[1];
68 Bit16u word[2];
69 Bit8u byte[4];
70 };
71
72 #ifdef WORDS_BIGENDIAN
73
74 #define DW_INDEX 0
75 #define W_INDEX 1
76 #define BH_INDEX 2
77 #define BL_INDEX 3
78
79 #else
80
81 #define DW_INDEX 0
82 #define W_INDEX 0
83 #define BH_INDEX 1
84 #define BL_INDEX 0
85
86 #endif
87
88 struct CPU_Regs {
89 GenReg32 regs[8],ip;
90 Bitu flags;
91 };
92
93 extern Segments Segs;
94 extern CPU_Regs cpu_regs;
95
SegPhys(SegNames index)96 static INLINE PhysPt SegPhys(SegNames index) {
97 return Segs.phys[index];
98 }
99
SegValue(SegNames index)100 static INLINE Bit16u SegValue(SegNames index) {
101 return (Bit16u)Segs.val[index];
102 }
103
RealMakeSeg(SegNames index,Bit16u off)104 static INLINE RealPt RealMakeSeg(SegNames index,Bit16u off) {
105 return RealMake(SegValue(index),off);
106 }
107
108
SegSet16(Bitu index,Bit16u val)109 static INLINE void SegSet16(Bitu index,Bit16u val) {
110 Segs.val[index]=val;
111 Segs.phys[index]=val << 4;
112 }
113
114 enum {
115 REGI_AX, REGI_CX, REGI_DX, REGI_BX,
116 REGI_SP, REGI_BP, REGI_SI, REGI_DI
117 };
118
119 enum {
120 REGI_AL, REGI_CL, REGI_DL, REGI_BL,
121 REGI_AH, REGI_CH, REGI_DH, REGI_BH
122 };
123
124
125 //macros to convert a 3-bit register index to the correct register
126 #define reg_8l(reg) (cpu_regs.regs[(reg)].byte[BL_INDEX])
127 #define reg_8h(reg) (cpu_regs.regs[(reg)].byte[BH_INDEX])
128 #define reg_8(reg) ((reg) & 4 ? reg_8h((reg) & 3) : reg_8l((reg) & 3))
129 #define reg_16(reg) (cpu_regs.regs[(reg)].word[W_INDEX])
130 #define reg_32(reg) (cpu_regs.regs[(reg)].dword[DW_INDEX])
131
132 #define reg_al cpu_regs.regs[REGI_AX].byte[BL_INDEX]
133 #define reg_ah cpu_regs.regs[REGI_AX].byte[BH_INDEX]
134 #define reg_ax cpu_regs.regs[REGI_AX].word[W_INDEX]
135 #define reg_eax cpu_regs.regs[REGI_AX].dword[DW_INDEX]
136
137 #define reg_bl cpu_regs.regs[REGI_BX].byte[BL_INDEX]
138 #define reg_bh cpu_regs.regs[REGI_BX].byte[BH_INDEX]
139 #define reg_bx cpu_regs.regs[REGI_BX].word[W_INDEX]
140 #define reg_ebx cpu_regs.regs[REGI_BX].dword[DW_INDEX]
141
142 #define reg_cl cpu_regs.regs[REGI_CX].byte[BL_INDEX]
143 #define reg_ch cpu_regs.regs[REGI_CX].byte[BH_INDEX]
144 #define reg_cx cpu_regs.regs[REGI_CX].word[W_INDEX]
145 #define reg_ecx cpu_regs.regs[REGI_CX].dword[DW_INDEX]
146
147 #define reg_dl cpu_regs.regs[REGI_DX].byte[BL_INDEX]
148 #define reg_dh cpu_regs.regs[REGI_DX].byte[BH_INDEX]
149 #define reg_dx cpu_regs.regs[REGI_DX].word[W_INDEX]
150 #define reg_edx cpu_regs.regs[REGI_DX].dword[DW_INDEX]
151
152 #define reg_si cpu_regs.regs[REGI_SI].word[W_INDEX]
153 #define reg_esi cpu_regs.regs[REGI_SI].dword[DW_INDEX]
154
155 #define reg_di cpu_regs.regs[REGI_DI].word[W_INDEX]
156 #define reg_edi cpu_regs.regs[REGI_DI].dword[DW_INDEX]
157
158 #define reg_sp cpu_regs.regs[REGI_SP].word[W_INDEX]
159 #define reg_esp cpu_regs.regs[REGI_SP].dword[DW_INDEX]
160
161 #define reg_bp cpu_regs.regs[REGI_BP].word[W_INDEX]
162 #define reg_ebp cpu_regs.regs[REGI_BP].dword[DW_INDEX]
163
164 #define reg_ip cpu_regs.ip.word[W_INDEX]
165 #define reg_eip cpu_regs.ip.dword[DW_INDEX]
166
167 #define reg_flags cpu_regs.flags
168
169 #endif
170