1 /*
2 * QEMU LSI53C895A SCSI Host Bus Adapter emulation
3 *
4 * Copyright (c) 2006 CodeSourcery.
5 * Written by Paul Brook
6 *
7 * This code is licensed under the LGPL.
8 */
9
10 /* Note:
11 * LSI53C810 emulation is incorrect, in the sense that it supports
12 * features added in later evolutions. This should not be a problem,
13 * as well-behaved operating systems will not try to use them.
14 */
15
16 /* Hacked to support LSI53C710 for UAE by Toni Wilen */
17
18 #include <assert.h>
19
20 #include "qemuuaeglue.h"
21 #include "queue.h"
22
23 //#include "hw/hw.h"
24 //#include "hw/pci/pci.h"
25 #include "scsi/scsi.h"
26 //#include "sysemu/dma.h"
27
28 //#define DEBUG_LSI
29 //#define DEBUG_LSI_REG
30
31 #ifdef DEBUG_LSI
32 #define DPRINTF(fmt, ...) \
33 do { write_log("lsi_scsi: " fmt , ## __VA_ARGS__); } while (0)
34 #define BADF(fmt, ...) \
35 do { write_log("lsi_scsi: error: " fmt , ## __VA_ARGS__); } while (0)
36 #else
37 #define DPRINTF(fmt, ...) do {} while(0)
38 #define BADF(fmt, ...) \
39 do { write_log("lsi_scsi: error: " fmt , ## __VA_ARGS__); assert(false);} while (0)
40 #endif
41
42 #define LSI_MAX_DEVS 7
43
44 #define LSI_SCNTL0_TRG 0x01
45 #define LSI_SCNTL0_AAP 0x02
46 #define LSI_SCNTL0_EPG 0x08
47 #define LSI_SCNTL0_EPC 0x08
48 #define LSI_SCNTL0_WATN 0x10,
49 #define LSI_SCNTL0_START 0x20
50
51 #define LSI_SCNTL1_RCV 0x01
52 #define LSI_SCNTL1_SND 0x02
53 #define LSI_SCNTL1_AESP 0x04
54 #define LSI_SCNTL1_RST 0x08
55 #define LSI_SCNTL1_CON 0x10
56 #define LSI_SCNTL1_ESR 0x20
57 #define LSI_SCNTL1_ADB 0x40
58 #define LSI_SCNTL1_EXC 0x80
59
60 #define LSI_SCNTL2_WSR 0x01
61 #define LSI_SCNTL2_VUE0 0x02
62 #define LSI_SCNTL2_VUE1 0x04
63 #define LSI_SCNTL2_WSS 0x08
64 #define LSI_SCNTL2_SLPHBEN 0x10
65 #define LSI_SCNTL2_SLPMD 0x20
66 #define LSI_SCNTL2_CHM 0x40
67 #define LSI_SCNTL2_SDU 0x80
68
69 #define LSI_ISTAT_DIP 0x01
70 #define LSI_ISTAT_SIP 0x02
71 //#define LSI_ISTAT0_INTF 0x04
72 #define LSI_ISTAT_CON 0x08
73 //#define LSI_ISTAT0_SEM 0x10
74 #define LSI_ISTAT_SIGP 0x20
75 #define LSI_ISTAT_RST 0x40
76 #define LSI_ISTAT_ABRT 0x80
77
78 #define LSI_SSTAT1_WOA 0x04
79
80 #define LSI_SSTAT0_PAR 0x01
81 #define LSI_SSTAT0_RST 0x02
82 #define LSI_SSTAT0_UDC 0x04
83 #define LSI_SSTAT0_SGE 0x08
84 #define LSI_SSTAT0_SEL 0x10
85 #define LSI_SSTAT0_STO 0x20
86 #define LSI_SSTAT0_FCMP 0x40
87 #define LSI_SSTAT0_MA 0x80
88
89 //#define LSI_SIST0_PAR 0x01
90 //#define LSI_SIST0_RST 0x02
91 //#define LSI_SIST0_UDC 0x04
92 //#define LSI_SIST0_SGE 0x08
93 //#define LSI_SIST0_RSL 0x10
94 //#define LSI_SIST0_SEL 0x20
95 //#define LSI_SIST0_CMP 0x40
96 //#define LSI_SIST0_MA 0x80
97
98 //#define LSI_SIST1_HTH 0x01
99 //#define LSI_SIST1_GEN 0x02
100 //#define LSI_SIST1_STO 0x04
101 //#define LSI_SIST1_SBMC 0x10
102
103 #define LSI_SOCL_IO 0x01
104 #define LSI_SOCL_CD 0x02
105 #define LSI_SOCL_MSG 0x04
106 #define LSI_SOCL_ATN 0x08
107 #define LSI_SOCL_SEL 0x10
108 #define LSI_SOCL_BSY 0x20
109 #define LSI_SOCL_ACK 0x40
110 #define LSI_SOCL_REQ 0x80
111
112 #define LSI_DSTAT_IID 0x01
113 #define LSI_DSTAT_SIR 0x04
114 #define LSI_DSTAT_SSI 0x08
115 #define LSI_DSTAT_ABRT 0x10
116 #define LSI_DSTAT_BF 0x20
117 #define LSI_DSTAT_MDPE 0x40
118 #define LSI_DSTAT_DFE 0x80
119
120 #define LSI_DCNTL_COM 0x01
121 #define LSI_DCNTL_IRQD 0x02
122 #define LSI_DCNTL_STD 0x04
123 #define LSI_DCNTL_IRQM 0x08
124 #define LSI_DCNTL_SSM 0x10
125 #define LSI_DCNTL_PFEN 0x20
126 #define LSI_DCNTL_PFF 0x40
127 #define LSI_DCNTL_CLSE 0x80
128
129 #define LSI_DMODE_MAN 0x01
130 #define LSI_DMODE_UO 0x02
131 #define LSI_DMODE_FAM 0x04
132 #define LSI_DMODE_PD 0x08
133
134 #define LSI_CTEST2_DACK 0x01
135 #define LSI_CTEST2_DREQ 0x02
136 #define LSI_CTEST2_TEOP 0x04
137 #define LSI_CTEST2_PCICIE 0x08
138 #define LSI_CTEST2_CM 0x10
139 #define LSI_CTEST2_CIO 0x20
140 #define LSI_CTEST2_SIGP 0x40
141 #define LSI_CTEST2_DDIR 0x80
142
143 #define LSI_CTEST5_BL2 0x04
144 #define LSI_CTEST5_DDIR 0x08
145 #define LSI_CTEST5_MASR 0x10
146 #define LSI_CTEST5_DFSN 0x20
147 #define LSI_CTEST5_BBCK 0x40
148 #define LSI_CTEST5_ADCK 0x80
149
150 #define LSI_CCNTL0_DILS 0x01
151 #define LSI_CCNTL0_DISFC 0x10
152 #define LSI_CCNTL0_ENNDJ 0x20
153 #define LSI_CCNTL0_PMJCTL 0x40
154 #define LSI_CCNTL0_ENPMJ 0x80
155
156 #define LSI_CCNTL1_EN64DBMV 0x01
157 #define LSI_CCNTL1_EN64TIBMV 0x02
158 #define LSI_CCNTL1_64TIMOD 0x04
159 #define LSI_CCNTL1_DDAC 0x08
160 #define LSI_CCNTL1_ZMOD 0x80
161
162 #define LSI_SBCL_IO 0x01
163 #define LSI_SBCL_CD 0x02
164 #define LSI_SBCL_MSG 0x04
165 #define LSI_SBCL_ATN 0x08
166 #define LSI_SBCL_SEL 0x10
167 #define LSI_SBCL_BSY 0x20
168 #define LSI_SBCL_ACK 0x40
169 #define LSI_SBCL_REQ 0x80
170
171 /* Enable Response to Reselection */
172 #define LSI_SCID_RRE 0x60
173
174 #define PHASE_DO 0
175 #define PHASE_DI 1
176 #define PHASE_CMD 2
177 #define PHASE_ST 3
178 #define PHASE_MO 6
179 #define PHASE_MI 7
180 #define PHASE_MASK 7
181
182 /* Maximum length of MSG IN data. */
183 #define LSI_MAX_MSGIN_LEN 8
184
185 /* Flag set if this is a tagged command. */
186 #define LSI_TAG_VALID (1 << 16)
187
188 typedef struct lsi_request {
189 SCSIRequest *req;
190 uint32_t tag;
191 uint32_t dma_len;
192 uint8_t *dma_buf;
193 uint32_t pending;
194 int out;
195 QTAILQ_ENTRY(lsi_request) next;
196 } lsi_request;
197
198 typedef struct {
199 /*< private >*/
200 //PCIDevice parent_obj;
201 /*< public >*/
202
203 //MemoryRegion mmio_io;
204 //MemoryRegion ram_io;
205 //MemoryRegion io_io;
206
207 int carry; /* ??? Should this be an a visible register somewhere? */
208 int status;
209 /* Action to take at the end of a MSG IN phase.
210 0 = COMMAND, 1 = disconnect, 2 = DATA OUT, 3 = DATA IN. */
211 int msg_action;
212 int msg_len;
213 uint8_t msg[LSI_MAX_MSGIN_LEN];
214 /* 0 if SCRIPTS are running or stopped.
215 * 1 if a Wait Reselect instruction has been issued.
216 * 2 if processing DMA from lsi_execute_script.
217 * 3 if a DMA operation is in progress. */
218 int waiting;
219 SCSIBus bus;
220 int current_lun;
221 /* The tag is a combination of the device ID and the SCSI tag. */
222 uint32_t select_tag;
223 int command_complete;
224 QTAILQ_HEAD(, lsi_request) queue;
225 lsi_request *current;
226
227 uint32_t dsa;
228 uint32_t temp;
229 uint32_t dnad;
230 uint32_t dbc;
231 uint8_t istat;
232 uint8_t dcmd;
233 uint8_t dstat;
234 uint8_t dien;
235 // uint8_t sist0;
236 // uint8_t sist1;
237 uint8_t sien0;
238 uint8_t ctest2;
239 uint8_t ctest3;
240 uint8_t ctest4;
241 uint8_t ctest5;
242 uint32_t dsp;
243 uint32_t dsps;
244 uint8_t dmode;
245 uint8_t dcntl;
246 uint8_t scntl0;
247 uint8_t scntl1;
248 uint8_t sstat0;
249 uint8_t sstat1;
250 uint8_t scid;
251 uint8_t sxfer;
252 uint8_t socl;
253 uint8_t sdid;
254 uint8_t sfbr;
255 uint8_t sidl;
256 uint32_t sbc;
257 uint32_t scratch;
258 uint8_t sbr;
259
260 uint8_t ctest0;
261 uint8_t ctest1;
262 uint8_t ctest6;
263 uint8_t ctest7;
264 uint8_t ctest8;
265 uint8_t lcrc;
266 uint8_t sstat2;
267 uint8_t dwt;
268 uint8_t sbcl;
269 uint8_t script_active;
270 } LSIState710;
271
272 //#define TYPE_LSI53C810 "lsi53c810"
273 //#define TYPE_LSI53C895A "lsi53c895a"
274
275 #define LSI53C895A(obj) (LSIState710*)obj->lsistate
276 //((LSIState710*)(OBJECT_CHECK(LSIState710, (obj), TYPE_LSI53C895A)))
277
lsi_irq_on_rsl(LSIState710 * s)278 static inline int lsi_irq_on_rsl(LSIState710 *s)
279 {
280 return 0; //return (s->sien0 & LSI_SIST0_RSL) && (s->scid & LSI_SCID_RRE);
281 }
282
lsi_soft_reset(LSIState710 * s)283 static void lsi_soft_reset(LSIState710 *s)
284 {
285 DPRINTF("Reset\n");
286 s->carry = 0;
287 s->msg_action = 0;
288 s->msg_len = 0;
289 s->waiting = 0;
290 s->dsa = 0;
291 s->dnad = 0;
292 s->dbc = 0;
293 s->temp = 0;
294 s->scratch = 0;
295 // reset bit does not reset
296 s->istat &= 0x40;
297 s->dcmd = 0x40;
298 s->dstat = LSI_DSTAT_DFE;
299 s->dien = 0;
300 s->sien0 = 0;
301 s->ctest2 = LSI_CTEST2_DACK;
302 s->ctest3 = 0;
303 s->ctest4 = 0;
304 s->ctest5 = 0;
305 s->dsp = 0;
306 s->dsps = 0;
307 s->dmode = 0;
308 s->dcntl = 0;
309 s->scntl0 = 0xc0;
310 s->scntl1 = 0;
311 s->sstat0 = 0;
312 s->sstat1 = 0;
313 s->sstat2 = 0;
314 s->scid = 0x80;
315 s->sxfer = 0;
316 s->socl = 0;
317 s->sdid = 0;
318 s->sidl = 0;
319 s->sbc = 0;
320 s->sbr = 0;
321 assert(QTAILQ_EMPTY(&s->queue));
322 assert(!s->current);
323 }
324
325 #if 0
326 static int lsi_dma_40bit(LSIState710 *s)
327 {
328 if ((s->ccntl1 & LSI_CCNTL1_40BIT) == LSI_CCNTL1_40BIT)
329 return 1;
330 return 0;
331 }
332
333 static int lsi_dma_ti64bit(LSIState710 *s)
334 {
335 if ((s->ccntl1 & LSI_CCNTL1_EN64TIBMV) == LSI_CCNTL1_EN64TIBMV)
336 return 1;
337 return 0;
338 }
339
340 static int lsi_dma_64bit(LSIState710 *s)
341 {
342 if ((s->ccntl1 & LSI_CCNTL1_EN64DBMV) == LSI_CCNTL1_EN64DBMV)
343 return 1;
344 return 0;
345 }
346 #endif
347
348 static uint8_t lsi_reg_readb(LSIState710 *s, int offset);
349 static void lsi_reg_writeb(LSIState710 *s, int offset, uint8_t val);
350 static void lsi_execute_script(LSIState710 *s);
351 static void lsi_reselect(LSIState710 *s, lsi_request *p);
352
read_dword(LSIState710 * s,uint32_t addr)353 static inline uint32_t read_dword(LSIState710 *s, uint32_t addr)
354 {
355 uint32_t buf;
356
357 pci710_dma_read(PCI_DEVICE(s), addr, &buf, 4);
358 return cpu_to_le32(buf);
359 }
360
lsi_stop_script(LSIState710 * s)361 static void lsi_stop_script(LSIState710 *s)
362 {
363 s->script_active = 0;
364 }
365
lsi_update_irq(LSIState710 * s)366 static void lsi_update_irq(LSIState710 *s)
367 {
368 PCIDevice *d = PCI_DEVICE(s);
369 int level;
370 static int last_level;
371 lsi_request *p;
372
373 /* It's unclear whether the DIP/SIP bits should be cleared when the
374 Interrupt Status Registers are cleared or when istat0 is read.
375 We currently do the formwer, which seems to work. */
376 level = 0;
377 if (s->dstat) {
378 if (s->dstat & s->dien)
379 level = 1;
380 s->istat |= LSI_ISTAT_DIP;
381 } else {
382 s->istat &= ~LSI_ISTAT_DIP;
383 }
384
385 if (s->sstat0) {
386 if ((s->sstat0 & s->sien0))
387 level = 1;
388 s->istat |= LSI_ISTAT_SIP;
389 } else {
390 s->istat &= ~LSI_ISTAT_SIP;
391 }
392
393 if (level != last_level) {
394 DPRINTF("Update IRQ level %d dstat %02x sist %02x%02x\n",
395 level, s->dstat, s->sstat0, s->sstat1);
396 last_level = level;
397 }
398 pci710_set_irq(d, level);
399
400 if (!level && lsi_irq_on_rsl(s) && !(s->scntl1 & LSI_SCNTL1_CON)) {
401 DPRINTF("Handled IRQs & disconnected, looking for pending "
402 "processes\n");
403 QTAILQ_FOREACH(p, &s->queue, next) {
404 if (p->pending) {
405 lsi_reselect(s, p);
406 break;
407 }
408 }
409 }
410 }
411
412 /* Stop SCRIPTS execution and raise a SCSI interrupt. */
lsi_script_scsi_interrupt(LSIState710 * s,int stat0)413 static void lsi_script_scsi_interrupt(LSIState710 *s, int stat0)
414 {
415 uint32_t mask0;
416 //uint32_t mask1;
417
418 DPRINTF("SCSI Interrupt 0x%02x%02x prev 0x%02x%02x\n",
419 stat0, s->sstat0);
420 s->sstat0 |= stat0;
421 //s->sist1 |= stat1;
422 /* Stop processor on fatal or unmasked interrupt. As a special hack
423 we don't stop processing when raising STO. Instead continue
424 execution and stop at the next insn that accesses the SCSI bus. */
425 mask0 = s->sien0 | ~(LSI_SSTAT0_FCMP | LSI_SSTAT0_SEL); // | LSI_SIST1_RSL);
426 //mask1 = s->sien1 | ~(LSI_SIST1_GEN | LSI_SIST1_HTH);
427 //mask1 &= ~LSI_SIST1_STO;
428 if (s->sstat0 & mask0) { // || s->sist1 & mask1) {
429 lsi_stop_script(s);
430 }
431 lsi_update_irq(s);
432 }
433
434 /* Stop SCRIPTS execution and raise a DMA interrupt. */
lsi_script_dma_interrupt(LSIState710 * s,int stat)435 static void lsi_script_dma_interrupt(LSIState710 *s, int stat)
436 {
437 DPRINTF("DMA Interrupt 0x%x prev 0x%x\n", stat, s->dstat);
438 s->dstat |= stat;
439 lsi_update_irq(s);
440 lsi_stop_script(s);
441 }
442
lsi_set_phase(LSIState710 * s,int phase)443 static inline void lsi_set_phase(LSIState710 *s, int phase)
444 {
445 s->sstat2 = (s->sstat2 & ~PHASE_MASK) | phase;
446 s->ctest0 &= ~1;
447 if (phase == PHASE_DI)
448 s->ctest0 |= 1;
449 s->sbcl &= ~LSI_SBCL_REQ;
450 }
451
lsi_bad_phase(LSIState710 * s,int out,int new_phase)452 static void lsi_bad_phase(LSIState710 *s, int out, int new_phase)
453 {
454 /* Trigger a phase mismatch. */
455 DPRINTF("Phase mismatch interrupt\n");
456 lsi_script_scsi_interrupt(s, LSI_SSTAT0_MA);
457 lsi_stop_script(s);
458 lsi_set_phase(s, new_phase);
459 s->sbcl |= LSI_SBCL_REQ;
460 }
461
462
463 /* Resume SCRIPTS execution after a DMA operation. */
lsi_resume_script(LSIState710 * s)464 static void lsi_resume_script(LSIState710 *s)
465 {
466 if (s->waiting != 2) {
467 s->waiting = 0;
468 lsi_execute_script(s);
469 } else {
470 s->waiting = 0;
471 }
472 }
473
lsi_disconnect(LSIState710 * s)474 static void lsi_disconnect(LSIState710 *s)
475 {
476 s->scntl1 &= ~LSI_SCNTL1_CON;
477 s->sstat2 &= ~PHASE_MASK;
478 }
479
lsi_bad_selection(LSIState710 * s,uint32_t id)480 static void lsi_bad_selection(LSIState710 *s, uint32_t id)
481 {
482 DPRINTF("Selected absent target %d\n", id);
483 lsi_script_scsi_interrupt(s, LSI_SSTAT0_STO);
484 lsi_disconnect(s);
485 }
486
487 /* Initiate a SCSI layer data transfer. */
lsi_do_dma(LSIState710 * s,int out)488 static void lsi_do_dma(LSIState710 *s, int out)
489 {
490 PCIDevice *pci_dev;
491 uint32_t count;
492 dma_addr_t addr;
493 SCSIDevice *dev;
494
495 assert(s->current);
496 if (!s->current->dma_len) {
497 /* Wait until data is available. */
498 DPRINTF("DMA no data available\n");
499 return;
500 }
501
502 pci_dev = PCI_DEVICE(s);
503 dev = s->current->req->dev;
504 assert(dev);
505
506 count = s->dbc;
507 if (count > s->current->dma_len)
508 count = s->current->dma_len;
509
510 addr = s->dnad;
511 #if 0
512 /* both 40 and Table Indirect 64-bit DMAs store upper bits in dnad64 */
513 if (lsi_dma_40bit(s) || lsi_dma_ti64bit(s))
514 addr |= ((uint64_t)s->dnad64 << 32);
515 else if (s->dbms)
516 addr |= ((uint64_t)s->dbms << 32);
517 else if (s->sbms)
518 addr |= ((uint64_t)s->sbms << 32);
519 #endif
520
521 DPRINTF("DMA addr=0x" DMA_ADDR_FMT " len=%d\n", addr, count);
522 s->dnad += count;
523 s->dbc -= count;
524 if (s->current->dma_buf == NULL) {
525 s->current->dma_buf = scsi710_req_get_buf(s->current->req);
526 }
527 /* ??? Set SFBR to first data byte. */
528 if (out) {
529 pci710_dma_read(pci_dev, addr, s->current->dma_buf, count);
530 } else {
531 pci710_dma_write(pci_dev, addr, s->current->dma_buf, count);
532 }
533 s->current->dma_len -= count;
534 if (s->current->dma_len == 0) {
535 s->current->dma_buf = NULL;
536 scsi710_req_continue(s->current->req);
537 } else {
538 s->current->dma_buf += count;
539 lsi_resume_script(s);
540 }
541 }
542
543
544 /* Add a command to the queue. */
lsi_queue_command(LSIState710 * s)545 static void lsi_queue_command(LSIState710 *s)
546 {
547 lsi_request *p = s->current;
548
549 DPRINTF("Queueing tag=0x%x\n", p->tag);
550 assert(s->current != NULL);
551 assert(s->current->dma_len == 0);
552 QTAILQ_INSERT_TAIL(&s->queue, s->current, next);
553 s->current = NULL;
554
555 p->pending = 0;
556 p->out = (s->sstat2 & PHASE_MASK) == PHASE_DO;
557 }
558
559 /* Queue a byte for a MSG IN phase. */
lsi_add_msg_byte(LSIState710 * s,uint8_t data)560 static void lsi_add_msg_byte(LSIState710 *s, uint8_t data)
561 {
562 if (s->msg_len >= LSI_MAX_MSGIN_LEN) {
563 BADF("MSG IN data too long\n");
564 } else {
565 DPRINTF("MSG IN 0x%02x\n", data);
566 s->msg[s->msg_len++] = data;
567 }
568 }
569
570 /* Perform reselection to continue a command. */
lsi_reselect(LSIState710 * s,lsi_request * p)571 static void lsi_reselect(LSIState710 *s, lsi_request *p)
572 {
573 int id;
574
575 assert(s->current == NULL);
576 QTAILQ_REMOVE(&s->queue, p, next);
577 s->current = p;
578
579 id = (p->tag >> 8) & 0xf;
580 /* LSI53C700 Family Compatibility, see LSI53C895A 4-73 */
581 if (!(s->dcntl & LSI_DCNTL_COM)) {
582 s->sfbr = 1 << (id & 0x7);
583 }
584 s->lcrc = 0;
585 DPRINTF("Reselected target %d\n", id);
586 s->scntl1 |= LSI_SCNTL1_CON;
587 lsi_set_phase(s, PHASE_MI);
588 s->msg_action = p->out ? 2 : 3;
589 s->current->dma_len = p->pending;
590 lsi_add_msg_byte(s, 0x80);
591 if (s->current->tag & LSI_TAG_VALID) {
592 lsi_add_msg_byte(s, 0x20);
593 lsi_add_msg_byte(s, p->tag & 0xff);
594 }
595
596 if (lsi_irq_on_rsl(s)) {
597 lsi_script_scsi_interrupt(s, LSI_SSTAT0_SEL);
598 }
599 }
600
lsi_find_by_tag(LSIState710 * s,uint32_t tag)601 static lsi_request *lsi_find_by_tag(LSIState710 *s, uint32_t tag)
602 {
603 lsi_request *p;
604
605 QTAILQ_FOREACH(p, &s->queue, next) {
606 if (p->tag == tag) {
607 return p;
608 }
609 }
610
611 return NULL;
612 }
613
lsi_request_free(LSIState710 * s,lsi_request * p)614 static void lsi_request_free(LSIState710 *s, lsi_request *p)
615 {
616 if (p == s->current) {
617 s->current = NULL;
618 } else {
619 QTAILQ_REMOVE(&s->queue, p, next);
620 }
621 g_free(p);
622 }
623
lsi710_request_cancelled(SCSIRequest * req)624 void lsi710_request_cancelled(SCSIRequest *req)
625 {
626 LSIState710 *s = LSI53C895A(req->bus->qbus.parent);
627 lsi_request *p = (lsi_request*)req->hba_private;
628
629 req->hba_private = NULL;
630 lsi_request_free(s, p);
631 scsi710_req_unref(req);
632 }
633
634 /* Record that data is available for a queued command. Returns zero if
635 the device was reselected, nonzero if the IO is deferred. */
lsi_queue_req(LSIState710 * s,SCSIRequest * req,uint32_t len)636 static int lsi_queue_req(LSIState710 *s, SCSIRequest *req, uint32_t len)
637 {
638 lsi_request *p = (lsi_request*)req->hba_private;
639
640 if (p->pending) {
641 BADF("Multiple IO pending for request %p\n", p);
642 }
643 p->pending = len;
644 /* Reselect if waiting for it, or if reselection triggers an IRQ
645 and the bus is free.
646 Since no interrupt stacking is implemented in the emulation, it
647 is also required that there are no pending interrupts waiting
648 for service from the device driver. */
649 if (s->waiting == 1 ||
650 (lsi_irq_on_rsl(s) && !(s->scntl1 & LSI_SCNTL1_CON) &&
651 !(s->istat & (LSI_ISTAT_SIP | LSI_ISTAT_DIP)))) {
652 /* Reselect device. */
653 lsi_reselect(s, p);
654 return 0;
655 } else {
656 DPRINTF("Queueing IO tag=0x%x\n", p->tag);
657 p->pending = len;
658 return 1;
659 }
660 }
661
662 /* Callback to indicate that the SCSI layer has completed a command. */
lsi710_command_complete(SCSIRequest * req,uint32_t status,size_t resid)663 void lsi710_command_complete(SCSIRequest *req, uint32_t status, size_t resid)
664 {
665 LSIState710 *s = LSI53C895A(req->bus->qbus.parent);
666 int out;
667
668 out = (s->sstat2 & PHASE_MASK) == PHASE_DO;
669 DPRINTF("Command complete status=%d\n", (int)status);
670 s->lcrc = 0;
671 s->status = status;
672 s->command_complete = 2;
673 if (s->waiting && s->dbc != 0) {
674 /* Raise phase mismatch for short transfers. */
675 lsi_bad_phase(s, out, PHASE_ST);
676 } else {
677 lsi_set_phase(s, PHASE_ST);
678 }
679
680 if (req->hba_private == s->current) {
681 req->hba_private = NULL;
682 lsi_request_free(s, s->current);
683 scsi710_req_unref(req);
684 }
685 lsi_resume_script(s);
686 }
687
688 /* Callback to indicate that the SCSI layer has completed a transfer. */
lsi710_transfer_data(SCSIRequest * req,uint32_t len)689 void lsi710_transfer_data(SCSIRequest *req, uint32_t len)
690 {
691 LSIState710 *s = LSI53C895A(req->bus->qbus.parent);
692 int out;
693
694 assert(req->hba_private);
695 if (s->waiting == 1 || req->hba_private != s->current ||
696 (lsi_irq_on_rsl(s) && !(s->scntl1 & LSI_SCNTL1_CON))) {
697 if (lsi_queue_req(s, req, len)) {
698 return;
699 }
700 }
701
702 out = (s->sstat2 & PHASE_MASK) == PHASE_DO;
703
704 /* host adapter (re)connected */
705 DPRINTF("Data ready tag=0x%x len=%d\n", req->tag, len);
706 s->current->dma_len = len;
707 s->command_complete = 1;
708 if (s->waiting) {
709 if (s->waiting == 1 || s->dbc == 0) {
710 lsi_resume_script(s);
711 } else {
712 lsi_do_dma(s, out);
713 }
714 }
715 }
716
idbitstonum(int id)717 static int idbitstonum(int id)
718 {
719 int num = 0;
720 while (id > 1) {
721 num++;
722 id >>= 1;
723 }
724 if (num > 7)
725 num = -1;
726 return num;
727 }
728
lsi_do_command(LSIState710 * s)729 static void lsi_do_command(LSIState710 *s)
730 {
731 SCSIDevice *dev;
732 uint8_t buf[16];
733 uint32_t id;
734 int n;
735
736 DPRINTF("Send command len=%d\n", s->dbc);
737 if (s->dbc > 16)
738 s->dbc = 16;
739 pci710_dma_read(PCI_DEVICE(s), s->dnad, buf, s->dbc);
740 DPRINTF("Send command len=%d %02x.%02x.%02x.%02x.%02x.%02x\n", s->dbc, buf[0], buf[1], buf[2], buf[3], buf[4], buf[5]);
741 s->sfbr = buf[0];
742 s->command_complete = 0;
743
744 id = (s->select_tag >> 8) & 0xff;
745 s->lcrc = id; //1 << (id & 0x7);
746 dev = scsi710_device_find(&s->bus, 0, idbitstonum(id), s->current_lun);
747 if (!dev) {
748 lsi_bad_selection(s, id);
749 return;
750 }
751
752 assert(s->current == NULL);
753 s->current = (lsi_request*)calloc(sizeof(lsi_request), 1);
754 s->current->tag = s->select_tag;
755 s->current->req = scsi710_req_new(dev, s->current->tag, s->current_lun, buf, s->dbc, s->current);
756
757 n = scsi710_req_enqueue(s->current->req);
758 if (n) {
759 if (n > 0) {
760 lsi_set_phase(s, PHASE_DI);
761 } else if (n < 0) {
762 lsi_set_phase(s, PHASE_DO);
763 }
764 scsi710_req_continue(s->current->req);
765 }
766 if (!s->command_complete) {
767 if (n) {
768 /* Command did not complete immediately so disconnect. */
769 lsi_add_msg_byte(s, 2); /* SAVE DATA POINTER */
770 lsi_add_msg_byte(s, 4); /* DISCONNECT */
771 /* wait data */
772 lsi_set_phase(s, PHASE_MI);
773 s->msg_action = 1;
774 lsi_queue_command(s);
775 } else {
776 /* wait command complete */
777 lsi_set_phase(s, PHASE_DI);
778 }
779 }
780 }
781
lsi_do_status(LSIState710 * s)782 static void lsi_do_status(LSIState710 *s)
783 {
784 uint8_t status;
785 DPRINTF("Get status len=%d status=%d\n", s->dbc, s->status);
786 if (s->dbc != 1)
787 BADF("Bad Status move\n");
788 s->dbc = 1;
789 status = s->status;
790 s->sfbr = status;
791 pci710_dma_write(PCI_DEVICE(s), s->dnad, &status, 1);
792 lsi_set_phase(s, PHASE_MI);
793 s->msg_action = 1;
794 lsi_add_msg_byte(s, 0); /* COMMAND COMPLETE */
795 }
796
lsi_do_msgin(LSIState710 * s)797 static void lsi_do_msgin(LSIState710 *s)
798 {
799 int len;
800 DPRINTF("Message in len=%d/%d\n", s->dbc, s->msg_len);
801 s->sfbr = s->msg[0];
802 len = s->msg_len;
803 if (len > s->dbc)
804 len = s->dbc;
805 pci710_dma_write(PCI_DEVICE(s), s->dnad, s->msg, len);
806 /* Linux drivers rely on the last byte being in the SIDL. */
807 s->sidl = s->msg[len - 1];
808 s->msg_len -= len;
809 if (s->msg_len) {
810 memmove(s->msg, s->msg + len, s->msg_len);
811 } else {
812 /* ??? Check if ATN (not yet implemented) is asserted and maybe
813 switch to PHASE_MO. */
814 switch (s->msg_action) {
815 case 0:
816 lsi_set_phase(s, PHASE_CMD);
817 break;
818 case 1:
819 lsi_disconnect(s);
820 break;
821 case 2:
822 lsi_set_phase(s, PHASE_DO);
823 break;
824 case 3:
825 lsi_set_phase(s, PHASE_DI);
826 break;
827 default:
828 abort();
829 }
830 }
831 }
832
833 /* Read the next byte during a MSGOUT phase. */
lsi_get_msgbyte(LSIState710 * s)834 static uint8_t lsi_get_msgbyte(LSIState710 *s)
835 {
836 uint8_t data;
837 pci710_dma_read(PCI_DEVICE(s), s->dnad, &data, 1);
838 s->dnad++;
839 s->dbc--;
840 return data;
841 }
842
843 /* Skip the next n bytes during a MSGOUT phase. */
lsi_skip_msgbytes(LSIState710 * s,unsigned int n)844 static void lsi_skip_msgbytes(LSIState710 *s, unsigned int n)
845 {
846 s->dnad += n;
847 s->dbc -= n;
848 }
849
lsi_do_msgout(LSIState710 * s)850 static void lsi_do_msgout(LSIState710 *s)
851 {
852 uint8_t msg;
853 int len;
854 uint32_t current_tag;
855 lsi_request *current_req, *p, *p_next;
856
857 if (s->current) {
858 current_tag = s->current->tag;
859 current_req = s->current;
860 } else {
861 current_tag = s->select_tag;
862 current_req = lsi_find_by_tag(s, current_tag);
863 }
864
865 DPRINTF("MSG out len=%d\n", s->dbc);
866 while (s->dbc) {
867 msg = lsi_get_msgbyte(s);
868 s->sfbr = msg;
869
870 switch (msg) {
871 case 0x04:
872 DPRINTF("MSG: Disconnect\n");
873 lsi_disconnect(s);
874 break;
875 case 0x08:
876 DPRINTF("MSG: No Operation\n");
877 lsi_set_phase(s, PHASE_CMD);
878 break;
879 case 0x01:
880 len = lsi_get_msgbyte(s);
881 msg = lsi_get_msgbyte(s);
882 (void)len; /* avoid a warning about unused variable*/
883 DPRINTF("Extended message 0x%x (len %d)\n", msg, len);
884 switch (msg) {
885 case 1:
886 DPRINTF("SDTR (ignored)\n");
887 lsi_skip_msgbytes(s, 2);
888 break;
889 case 3:
890 DPRINTF("WDTR (ignored)\n");
891 lsi_skip_msgbytes(s, 1);
892 break;
893 default:
894 goto bad;
895 }
896 break;
897 case 0x20: /* SIMPLE queue */
898 s->select_tag |= lsi_get_msgbyte(s) | LSI_TAG_VALID;
899 DPRINTF("SIMPLE queue tag=0x%x\n", s->select_tag & 0xff);
900 break;
901 case 0x21: /* HEAD of queue */
902 BADF("HEAD queue not implemented\n");
903 s->select_tag |= lsi_get_msgbyte(s) | LSI_TAG_VALID;
904 break;
905 case 0x22: /* ORDERED queue */
906 BADF("ORDERED queue not implemented\n");
907 s->select_tag |= lsi_get_msgbyte(s) | LSI_TAG_VALID;
908 break;
909 case 0x0d:
910 /* The ABORT TAG message clears the current I/O process only. */
911 DPRINTF("MSG: ABORT TAG tag=0x%x\n", current_tag);
912 if (current_req) {
913 scsi710_req_cancel(current_req->req);
914 }
915 lsi_disconnect(s);
916 break;
917 case 0x06:
918 case 0x0e:
919 case 0x0c:
920 /* The ABORT message clears all I/O processes for the selecting
921 initiator on the specified logical unit of the target. */
922 if (msg == 0x06) {
923 DPRINTF("MSG: ABORT tag=0x%x\n", current_tag);
924 }
925 /* The CLEAR QUEUE message clears all I/O processes for all
926 initiators on the specified logical unit of the target. */
927 if (msg == 0x0e) {
928 DPRINTF("MSG: CLEAR QUEUE tag=0x%x\n", current_tag);
929 }
930 /* The BUS DEVICE RESET message clears all I/O processes for all
931 initiators on all logical units of the target. */
932 if (msg == 0x0c) {
933 DPRINTF("MSG: BUS DEVICE RESET tag=0x%x\n", current_tag);
934 }
935
936 /* clear the current I/O process */
937 if (s->current) {
938 scsi710_req_cancel(s->current->req);
939 }
940
941 /* As the current implemented devices scsi_disk and scsi_generic
942 only support one LUN, we don't need to keep track of LUNs.
943 Clearing I/O processes for other initiators could be possible
944 for scsi_generic by sending a SG_SCSI_RESET to the /dev/sgX
945 device, but this is currently not implemented (and seems not
946 to be really necessary). So let's simply clear all queued
947 commands for the current device: */
948 QTAILQ_FOREACH_SAFE(p, &s->queue, next, p_next) {
949 if ((p->tag & 0x0000ff00) == (current_tag & 0x0000ff00)) {
950 scsi710_req_cancel(p->req);
951 }
952 }
953
954 lsi_disconnect(s);
955 break;
956 default:
957 if ((msg & 0x80) == 0) {
958 goto bad;
959 }
960 s->current_lun = msg & 7;
961 DPRINTF("Select LUN %d\n", s->current_lun);
962 lsi_set_phase(s, PHASE_CMD);
963 break;
964 }
965 }
966 return;
967 bad:
968 BADF("Unimplemented message 0x%02x\n", msg);
969 lsi_set_phase(s, PHASE_MI);
970 lsi_add_msg_byte(s, 7); /* MESSAGE REJECT */
971 s->msg_action = 0;
972 }
973
974 #define LSI_BUF_SIZE 4096
lsi_memcpy(LSIState710 * s,uint32_t dest,uint32_t src,int count)975 static void lsi_memcpy(LSIState710 *s, uint32_t dest, uint32_t src, int count)
976 {
977 PCIDevice *d = PCI_DEVICE(s);
978 int n;
979 uint8_t buf[LSI_BUF_SIZE];
980
981 DPRINTF("memcpy dest 0x%08x src 0x%08x count %d\n", dest, src, count);
982 while (count) {
983 n = (count > LSI_BUF_SIZE) ? LSI_BUF_SIZE : count;
984 pci710_dma_read(d, src, buf, n);
985 pci710_dma_write(d, dest, buf, n);
986 src += n;
987 dest += n;
988 count -= n;
989 }
990 }
991
lsi_wait_reselect(LSIState710 * s)992 static void lsi_wait_reselect(LSIState710 *s)
993 {
994 lsi_request *p;
995
996 DPRINTF("Wait Reselect\n");
997
998 QTAILQ_FOREACH(p, &s->queue, next) {
999 if (p->pending) {
1000 lsi_reselect(s, p);
1001 break;
1002 }
1003 }
1004 if (s->current == NULL) {
1005 s->waiting = 1;
1006 }
1007 }
1008
lsi_execute_script(LSIState710 * s)1009 static void lsi_execute_script(LSIState710 *s)
1010 {
1011 PCIDevice *pci_dev = PCI_DEVICE(s);
1012 uint32_t insn;
1013 uint32_t addr;
1014 int opcode;
1015 int insn_processed = 0;
1016
1017 s->script_active = 1;
1018 again:
1019 insn_processed++;
1020 insn = read_dword(s, s->dsp);
1021 if (!insn) {
1022 /* If we receive an empty opcode increment the DSP by 4 bytes
1023 instead of 8 and execute the next opcode at that location */
1024 s->dsp += 4;
1025 goto again;
1026 }
1027 addr = read_dword(s, s->dsp + 4);
1028 DPRINTF("SCRIPTS dsp=%08x opcode %08x arg %08x\n", s->dsp, insn, addr);
1029 s->dsps = addr;
1030 s->dcmd = insn >> 24;
1031 s->dsp += 8;
1032 switch (insn >> 30) {
1033 case 0: /* Block move. */
1034 if (s->sstat0 & LSI_SSTAT0_STO) {
1035 DPRINTF("Delayed select timeout\n");
1036 lsi_stop_script(s);
1037 break;
1038 }
1039 s->dbc = insn & 0xffffff;
1040 if (insn & (1 << 29)) {
1041 /* Indirect addressing. */
1042 addr = read_dword(s, addr);
1043 } else if (insn & (1 << 28)) {
1044 uint32_t buf[2];
1045 int32_t offset;
1046 /* Table indirect addressing. */
1047
1048 /* 32-bit Table indirect */
1049 offset = sextract32(addr, 0, 24);
1050 pci710_dma_read(pci_dev, s->dsa + offset, buf, 8);
1051 /* byte count is stored in bits 0:23 only */
1052 s->dbc = cpu_to_le32(buf[0]) & 0xffffff;
1053 addr = cpu_to_le32(buf[1]);
1054
1055 #if 0
1056 /* 40-bit DMA, upper addr bits [39:32] stored in first DWORD of
1057 * table, bits [31:24] */
1058 if (lsi_dma_40bit(s))
1059 addr_high = cpu_to_le32(buf[0]) >> 24;
1060 else if (lsi_dma_ti64bit(s)) {
1061 int selector = (cpu_to_le32(buf[0]) >> 24) & 0x1f;
1062 switch (selector) {
1063 case 0x00:
1064 case 0x01:
1065 case 0x02:
1066 case 0x03:
1067 case 0x04:
1068 case 0x05:
1069 case 0x06:
1070 case 0x07:
1071 case 0x08:
1072 case 0x09:
1073 case 0x0a:
1074 case 0x0b:
1075 case 0x0c:
1076 case 0x0d:
1077 case 0x0e:
1078 case 0x0f:
1079 /* offset index into scratch registers since
1080 * TI64 mode can use registers C to R */
1081 addr_high = s->scratch[2 + selector];
1082 break;
1083 case 0x10:
1084 addr_high = s->mmrs;
1085 break;
1086 case 0x11:
1087 addr_high = s->mmws;
1088 break;
1089 case 0x12:
1090 addr_high = s->sfs;
1091 break;
1092 case 0x13:
1093 addr_high = s->drs;
1094 break;
1095 case 0x14:
1096 addr_high = s->sbms;
1097 break;
1098 case 0x15:
1099 addr_high = s->dbms;
1100 break;
1101 default:
1102 BADF("Illegal selector specified (0x%x > 0x15)"
1103 " for 64-bit DMA block move", selector);
1104 break;
1105 }
1106 }
1107 } else if (lsi_dma_64bit(s)) {
1108 /* fetch a 3rd dword if 64-bit direct move is enabled and
1109 only if we're not doing table indirect or indirect addressing */
1110 s->dbms = read_dword(s, s->dsp);
1111 s->dsp += 4;
1112 s->ia = s->dsp - 12;
1113 #endif
1114 }
1115 if ((s->sstat2 & PHASE_MASK) != ((insn >> 24) & 7)) {
1116 DPRINTF("Wrong phase got %d expected %d\n",
1117 s->sstat2 & PHASE_MASK, (insn >> 24) & 7);
1118 lsi_script_scsi_interrupt(s, LSI_SSTAT0_MA);
1119 s->sbcl |= LSI_SBCL_REQ;
1120 break;
1121 }
1122 s->dnad = addr;
1123 switch (s->sstat2 & 0x7) {
1124 case PHASE_DO:
1125 s->waiting = 2;
1126 lsi_do_dma(s, 1);
1127 if (s->waiting)
1128 s->waiting = 3;
1129 break;
1130 case PHASE_DI:
1131 s->waiting = 2;
1132 lsi_do_dma(s, 0);
1133 if (s->waiting)
1134 s->waiting = 3;
1135 break;
1136 case PHASE_CMD:
1137 lsi_do_command(s);
1138 break;
1139 case PHASE_ST:
1140 lsi_do_status(s);
1141 break;
1142 case PHASE_MO:
1143 lsi_do_msgout(s);
1144 break;
1145 case PHASE_MI:
1146 lsi_do_msgin(s);
1147 break;
1148 default:
1149 BADF("Unimplemented phase %d\n", s->sstat2 & PHASE_MASK);
1150 }
1151 s->ctest5 = (s->ctest5 & 0xfc) | ((s->dbc >> 8) & 3);
1152 s->sbc = s->dbc;
1153 break;
1154
1155 case 1: /* IO or Read/Write instruction. */
1156 opcode = (insn >> 27) & 7;
1157 if (opcode < 5) {
1158 uint32_t id;
1159
1160 if (insn & (1 << 25)) {
1161 id = read_dword(s, s->dsa + sextract32(insn, 0, 24));
1162 } else {
1163 id = insn;
1164 }
1165 id = (id >> 16) & 0xff;
1166 if (insn & (1 << 26)) {
1167 addr = s->dsp + sextract32(addr, 0, 24);
1168 }
1169 s->dnad = addr;
1170 switch (opcode) {
1171 case 0: /* Select */
1172 s->sdid = id;
1173 if (s->scntl1 & LSI_SCNTL1_CON) {
1174 DPRINTF("Already reselected, jumping to alternative address\n");
1175 s->dsp = s->dnad;
1176 break;
1177 }
1178 s->sstat1 |= LSI_SSTAT1_WOA;
1179 // s->scntl1 &= ~LSI_SCNTL1_IARB;
1180 if (!scsi710_device_find(&s->bus, 0, idbitstonum(id), 0)) {
1181 lsi_bad_selection(s, id);
1182 break;
1183 }
1184 DPRINTF("Selected target %d%s\n",
1185 id, insn & (1 << 24) ? " ATN" : "");
1186 /* ??? Linux drivers compain when this is set. Maybe
1187 it only applies in low-level mode (unimplemented).
1188 lsi_script_scsi_interrupt(s, LSI_SIST0_CMP, 0); */
1189 s->select_tag = id << 8;
1190 s->scntl1 |= LSI_SCNTL1_CON;
1191 if (insn & (1 << 24)) {
1192 s->socl |= LSI_SOCL_ATN;
1193 }
1194 lsi_set_phase(s, PHASE_MO);
1195 break;
1196 case 1: /* Disconnect */
1197 DPRINTF("Wait Disconnect\n");
1198 s->scntl1 &= ~LSI_SCNTL1_CON;
1199 break;
1200 case 2: /* Wait Reselect */
1201 if (!lsi_irq_on_rsl(s)) {
1202 lsi_wait_reselect(s);
1203 }
1204 break;
1205 case 3: /* Set */
1206 DPRINTF("Set%s%s%s%s\n",
1207 insn & (1 << 3) ? " ATN" : "",
1208 insn & (1 << 6) ? " ACK" : "",
1209 insn & (1 << 9) ? " TM" : "",
1210 insn & (1 << 10) ? " CC" : "");
1211 if (insn & (1 << 3)) {
1212 s->socl |= LSI_SOCL_ATN;
1213 lsi_set_phase(s, PHASE_MO);
1214 }
1215 if (insn & (1 << 9)) {
1216 BADF("Target mode not implemented\n");
1217 }
1218 if (insn & (1 << 10))
1219 s->carry = 1;
1220 break;
1221 case 4: /* Clear */
1222 DPRINTF("Clear%s%s%s%s\n",
1223 insn & (1 << 3) ? " ATN" : "",
1224 insn & (1 << 6) ? " ACK" : "",
1225 insn & (1 << 9) ? " TM" : "",
1226 insn & (1 << 10) ? " CC" : "");
1227 if (insn & (1 << 3)) {
1228 s->socl &= ~LSI_SOCL_ATN;
1229 }
1230 if (insn & (1 << 10))
1231 s->carry = 0;
1232 break;
1233 }
1234 } else {
1235 uint8_t op0;
1236 uint8_t op1;
1237 uint8_t data8;
1238 int reg;
1239 int xoperator;
1240 #ifdef DEBUG_LSI
1241 static const char *opcode_names[3] =
1242 {"Write", "Read", "Read-Modify-Write"};
1243 static const char *operator_names[8] =
1244 {"MOV", "SHL", "OR", "XOR", "AND", "SHR", "ADD", "ADC"};
1245 #endif
1246
1247 reg = ((insn >> 16) & 0x7f) | (insn & 0x80);
1248 data8 = (insn >> 8) & 0xff;
1249 opcode = (insn >> 27) & 7;
1250 xoperator = (insn >> 24) & 7;
1251 DPRINTF("%s reg 0x%x %s data8=0x%02x sfbr=0x%02x%s\n",
1252 opcode_names[opcode - 5], reg,
1253 operator_names[xoperator], data8, s->sfbr,
1254 (insn & (1 << 23)) ? " SFBR" : "");
1255 op0 = op1 = 0;
1256 switch (opcode) {
1257 case 5: /* From SFBR */
1258 op0 = s->sfbr;
1259 op1 = data8;
1260 break;
1261 case 6: /* To SFBR */
1262 if (xoperator)
1263 op0 = lsi_reg_readb(s, reg);
1264 op1 = data8;
1265 break;
1266 case 7: /* Read-modify-write */
1267 if (xoperator)
1268 op0 = lsi_reg_readb(s, reg);
1269 if (insn & (1 << 23)) {
1270 op1 = s->sfbr;
1271 } else {
1272 op1 = data8;
1273 }
1274 break;
1275 }
1276
1277 switch (xoperator) {
1278 case 0: /* move */
1279 op0 = op1;
1280 break;
1281 case 1: /* Shift left */
1282 op1 = op0 >> 7;
1283 op0 = (op0 << 1) | s->carry;
1284 s->carry = op1;
1285 break;
1286 case 2: /* OR */
1287 op0 |= op1;
1288 break;
1289 case 3: /* XOR */
1290 op0 ^= op1;
1291 break;
1292 case 4: /* AND */
1293 op0 &= op1;
1294 break;
1295 case 5: /* SHR */
1296 op1 = op0 & 1;
1297 op0 = (op0 >> 1) | (s->carry << 7);
1298 s->carry = op1;
1299 break;
1300 case 6: /* ADD */
1301 op0 += op1;
1302 s->carry = op0 < op1;
1303 break;
1304 case 7: /* ADC */
1305 op0 += op1 + s->carry;
1306 if (s->carry)
1307 s->carry = op0 <= op1;
1308 else
1309 s->carry = op0 < op1;
1310 break;
1311 }
1312
1313 switch (opcode) {
1314 case 5: /* From SFBR */
1315 case 7: /* Read-modify-write */
1316 lsi_reg_writeb(s, reg, op0);
1317 break;
1318 case 6: /* To SFBR */
1319 s->sfbr = op0;
1320 break;
1321 }
1322 }
1323 break;
1324
1325 case 2: /* Transfer Control. */
1326 {
1327 int cond;
1328 int jmp;
1329
1330 if ((insn & 0x002e0000) == 0) {
1331 DPRINTF("NOP\n");
1332 break;
1333 }
1334 if (s->sstat0 & LSI_SSTAT0_STO) {
1335 DPRINTF("Delayed select timeout\n");
1336 lsi_stop_script(s);
1337 break;
1338 }
1339 cond = jmp = (insn & (1 << 19)) != 0;
1340 if (cond == jmp && (insn & (1 << 21))) {
1341 DPRINTF("Compare carry %d\n", s->carry == jmp);
1342 cond = s->carry != 0;
1343 }
1344 if (cond == jmp && (insn & (1 << 17))) {
1345 DPRINTF("Compare phase %d %c= %d\n",
1346 (s->sstat2 & PHASE_MASK),
1347 jmp ? '=' : '!',
1348 ((insn >> 24) & 7));
1349 cond = (s->sstat2 & PHASE_MASK) == ((insn >> 24) & 7);
1350 }
1351 if (cond == jmp && (insn & (1 << 18))) {
1352 uint8_t mask;
1353
1354 mask = (~insn >> 8) & 0xff;
1355 DPRINTF("Compare data 0x%x & 0x%x %c= 0x%x\n",
1356 s->sfbr, mask, jmp ? '=' : '!', insn & mask);
1357 cond = (s->sfbr & mask) == (insn & mask);
1358 }
1359 if (cond == jmp) {
1360 if (insn & (1 << 23)) {
1361 /* Relative address. */
1362 addr = s->dsp + sextract32(addr, 0, 24);
1363 }
1364 switch ((insn >> 27) & 7) {
1365 case 0: /* Jump */
1366 DPRINTF("Jump to 0x%08x\n", addr);
1367 s->dsp = addr;
1368 break;
1369 case 1: /* Call */
1370 DPRINTF("Call 0x%08x\n", addr);
1371 s->temp = s->dsp;
1372 s->dsp = addr;
1373 break;
1374 case 2: /* Return */
1375 DPRINTF("Return to 0x%08x\n", s->temp);
1376 s->dsp = s->temp;
1377 break;
1378 case 3: /* Interrupt */
1379 DPRINTF("Interrupt 0x%08x\n", s->dsps);
1380 if ((insn & (1 << 20)) != 0) {
1381 lsi_update_irq(s);
1382 } else {
1383 lsi_script_dma_interrupt(s, LSI_DSTAT_SIR);
1384 }
1385 break;
1386 default:
1387 DPRINTF("Illegal transfer control\n");
1388 lsi_script_dma_interrupt(s, LSI_DSTAT_IID);
1389 break;
1390 }
1391 } else {
1392 DPRINTF("Control condition failed\n");
1393 }
1394 }
1395 break;
1396
1397 case 3:
1398 if ((insn & (1 << 29)) == 0) {
1399 /* Memory move. */
1400 uint32_t dest;
1401 /* ??? The docs imply the destination address is loaded into
1402 the TEMP register. However the Linux drivers rely on
1403 the value being presrved. */
1404 dest = read_dword(s, s->dsp);
1405 s->dsp += 4;
1406 lsi_memcpy(s, dest, addr, insn & 0xffffff);
1407 } else {
1408 uint8_t data[7];
1409 int reg;
1410 int n;
1411 int i;
1412
1413 if (insn & (1 << 28)) {
1414 addr = s->dsa + sextract32(addr, 0, 24);
1415 }
1416 n = (insn & 7);
1417 reg = (insn >> 16) & 0xff;
1418 if (insn & (1 << 24)) {
1419 pci710_dma_read(pci_dev, addr, data, n);
1420 DPRINTF("Load reg 0x%x size %d addr 0x%08x = %08x\n", reg, n,
1421 addr, *(int *)data);
1422 for (i = 0; i < n; i++) {
1423 lsi_reg_writeb(s, reg + i, data[i]);
1424 }
1425 } else {
1426 DPRINTF("Store reg 0x%x size %d addr 0x%08x\n", reg, n, addr);
1427 for (i = 0; i < n; i++) {
1428 data[i] = lsi_reg_readb(s, reg + i);
1429 }
1430 pci710_dma_write(pci_dev, addr, data, n);
1431 }
1432 }
1433 }
1434 if (insn_processed > 10000 && !s->waiting) {
1435 /* Some windows drivers make the device spin waiting for a memory
1436 location to change. If we have been executed a lot of code then
1437 assume this is the case and force an unexpected device disconnect.
1438 This is apparently sufficient to beat the drivers into submission.
1439 */
1440 if (!(s->sien0 & LSI_SSTAT0_UDC))
1441 fprintf(stderr, "inf. loop with UDC masked\n");
1442 lsi_script_scsi_interrupt(s, LSI_SSTAT0_UDC);
1443 lsi_disconnect(s);
1444 } else if (s->script_active && !s->waiting) {
1445 if (s->dcntl & LSI_DCNTL_SSM) {
1446 lsi_script_dma_interrupt(s, LSI_DSTAT_SSI);
1447 } else {
1448 goto again;
1449 }
1450 }
1451 DPRINTF("SCRIPTS execution stopped\n");
1452 }
1453
1454 #if 0
1455 static uint8_t lsi_reg_readb(LSIState710 *s, int offset)
1456 {
1457 uint8_t tmp;
1458 #define CASE_GET_REG24(name, addr) \
1459 case addr: return s->name & 0xff; \
1460 case addr + 1: return (s->name >> 8) & 0xff; \
1461 case addr + 2: return (s->name >> 16) & 0xff;
1462
1463 #define CASE_GET_REG32(name, addr) \
1464 case addr: return s->name & 0xff; \
1465 case addr + 1: return (s->name >> 8) & 0xff; \
1466 case addr + 2: return (s->name >> 16) & 0xff; \
1467 case addr + 3: return (s->name >> 24) & 0xff;
1468
1469 #ifdef DEBUG_LSI_REG
1470 DPRINTF("Read reg %x\n", offset);
1471 #endif
1472 switch (offset) {
1473 case 0x00: /* SCNTL0 */
1474 return s->scntl0;
1475 case 0x01: /* SCNTL1 */
1476 return s->scntl1;
1477 case 0x02: /* SCNTL2 */
1478 return s->scntl2;
1479 case 0x03: /* SCNTL3 */
1480 return s->scntl3;
1481 case 0x04: /* SCID */
1482 return s->scid;
1483 case 0x05: /* SXFER */
1484 return s->sxfer;
1485 case 0x06: /* SDID */
1486 return s->sdid;
1487 case 0x07: /* GPREG0 */
1488 return 0x7f;
1489 case 0x08: /* Revision ID */
1490 return 0x00;
1491 case 0xa: /* SSID */
1492 return s->ssid;
1493 case 0xb: /* SBCL */
1494 /* ??? This is not correct. However it's (hopefully) only
1495 used for diagnostics, so should be ok. */
1496 return 0;
1497 case 0xc: /* DSTAT */
1498 tmp = s->dstat | LSI_DSTAT_DFE;
1499 if ((s->istat0 & LSI_ISTAT0_INTF) == 0)
1500 s->dstat = 0;
1501 lsi_update_irq(s);
1502 return tmp;
1503 case 0x0d: /* SSTAT0 */
1504 return s->sstat0;
1505 case 0x0e: /* SSTAT1 */
1506 return s->sstat1;
1507 case 0x0f: /* SSTAT2 */
1508 return s->scntl1 & LSI_SCNTL1_CON ? 0 : 2;
1509 CASE_GET_REG32(dsa, 0x10)
1510 case 0x14: /* ISTAT0 */
1511 return s->istat0;
1512 case 0x15: /* ISTAT1 */
1513 return s->istat1;
1514 case 0x16: /* MBOX0 */
1515 return s->mbox0;
1516 case 0x17: /* MBOX1 */
1517 return s->mbox1;
1518 case 0x18: /* CTEST0 */
1519 return 0xff;
1520 case 0x19: /* CTEST1 */
1521 return 0;
1522 case 0x1a: /* CTEST2 */
1523 tmp = s->ctest2 | LSI_CTEST2_DACK | LSI_CTEST2_CM;
1524 if (s->istat0 & LSI_ISTAT0_SIGP) {
1525 s->istat0 &= ~LSI_ISTAT0_SIGP;
1526 tmp |= LSI_CTEST2_SIGP;
1527 }
1528 return tmp;
1529 case 0x1b: /* CTEST3 */
1530 return s->ctest3;
1531 CASE_GET_REG32(temp, 0x1c)
1532 case 0x20: /* DFIFO */
1533 return 0;
1534 case 0x21: /* CTEST4 */
1535 return s->ctest4;
1536 case 0x22: /* CTEST5 */
1537 return s->ctest5;
1538 case 0x23: /* CTEST6 */
1539 return 0;
1540 CASE_GET_REG24(dbc, 0x24)
1541 case 0x27: /* DCMD */
1542 return s->dcmd;
1543 CASE_GET_REG32(dnad, 0x28)
1544 CASE_GET_REG32(dsp, 0x2c)
1545 CASE_GET_REG32(dsps, 0x30)
1546 CASE_GET_REG32(scratch[0], 0x34)
1547 case 0x38: /* DMODE */
1548 return s->dmode;
1549 case 0x39: /* DIEN */
1550 return s->dien;
1551 case 0x3a: /* SBR */
1552 return s->sbr;
1553 case 0x3b: /* DCNTL */
1554 return s->dcntl;
1555 case 0x40: /* SIEN0 */
1556 return s->sien0;
1557 case 0x41: /* SIEN1 */
1558 return s->sien1;
1559 case 0x42: /* SIST0 */
1560 tmp = s->sist0;
1561 s->sist0 = 0;
1562 lsi_update_irq(s);
1563 return tmp;
1564 case 0x43: /* SIST1 */
1565 tmp = s->sist1;
1566 s->sist1 = 0;
1567 lsi_update_irq(s);
1568 return tmp;
1569 case 0x46: /* MACNTL */
1570 return 0x0f;
1571 case 0x47: /* GPCNTL0 */
1572 return 0x0f;
1573 case 0x48: /* STIME0 */
1574 return s->stime0;
1575 case 0x4a: /* RESPID0 */
1576 return s->respid0;
1577 case 0x4b: /* RESPID1 */
1578 return s->respid1;
1579 case 0x4d: /* STEST1 */
1580 return s->stest1;
1581 case 0x4e: /* STEST2 */
1582 return s->stest2;
1583 case 0x4f: /* STEST3 */
1584 return s->stest3;
1585 case 0x50: /* SIDL */
1586 /* This is needed by the linux drivers. We currently only update it
1587 during the MSG IN phase. */
1588 return s->sidl;
1589 case 0x52: /* STEST4 */
1590 return 0xe0;
1591 case 0x56: /* CCNTL0 */
1592 return s->ccntl0;
1593 case 0x57: /* CCNTL1 */
1594 return s->ccntl1;
1595 case 0x58: /* SBDL */
1596 /* Some drivers peek at the data bus during the MSG IN phase. */
1597 if ((s->sstat1 & PHASE_MASK) == PHASE_MI)
1598 return s->msg[0];
1599 return 0;
1600 case 0x59: /* SBDL high */
1601 return 0;
1602 CASE_GET_REG32(mmrs, 0xa0)
1603 CASE_GET_REG32(mmws, 0xa4)
1604 CASE_GET_REG32(sfs, 0xa8)
1605 CASE_GET_REG32(drs, 0xac)
1606 CASE_GET_REG32(sbms, 0xb0)
1607 CASE_GET_REG32(dbms, 0xb4)
1608 CASE_GET_REG32(dnad64, 0xb8)
1609 CASE_GET_REG32(pmjad1, 0xc0)
1610 CASE_GET_REG32(pmjad2, 0xc4)
1611 CASE_GET_REG32(rbc, 0xc8)
1612 CASE_GET_REG32(ua, 0xcc)
1613 CASE_GET_REG32(ia, 0xd4)
1614 CASE_GET_REG32(sbc, 0xd8)
1615 CASE_GET_REG32(csbc, 0xdc)
1616 }
1617 if (offset >= 0x5c && offset < 0xa0) {
1618 int n;
1619 int shift;
1620 n = (offset - 0x58) >> 2;
1621 shift = (offset & 3) * 8;
1622 return (s->scratch[n] >> shift) & 0xff;
1623 }
1624 BADF("readb 0x%x\n", offset);
1625 #undef CASE_GET_REG24
1626 #undef CASE_GET_REG32
1627 }
1628 #endif
1629
lsi_reg_readb2(LSIState710 * s,int offset)1630 static uint8_t lsi_reg_readb2(LSIState710 *s, int offset)
1631 {
1632 uint8_t tmp;
1633 #define CASE_GET_REG24(name, addr) \
1634 case addr: return s->name & 0xff; \
1635 case addr + 1: return (s->name >> 8) & 0xff; \
1636 case addr + 2: return (s->name >> 16) & 0xff;
1637
1638 #define CASE_GET_REG32(name, addr) \
1639 case addr: return s->name & 0xff; \
1640 case addr + 1: return (s->name >> 8) & 0xff; \
1641 case addr + 2: return (s->name >> 16) & 0xff; \
1642 case addr + 3: return (s->name >> 24) & 0xff;
1643
1644 switch (offset)
1645 {
1646 case 0x00: /* SCNTL0 */
1647 return s->scntl0;
1648 case 0x01: /* SCNTL1 */
1649 return s->scntl1;
1650 case 0x02: /* SDID */
1651 return s->sdid;
1652 case 0x03: /* SIEN */
1653 return s->sien0;
1654 case 0x04: /* SCID */
1655 return s->scid;
1656 case 0x05: /* SXFER */
1657 return s->sxfer;
1658 case 0x09: /* SIDL */
1659 /* This is needed by the linux drivers. We currently only update it
1660 during the MSG IN phase. */
1661 return s->sidl;
1662 case 0xb: /* SBCL */
1663 tmp = 0;
1664 if (s->scntl1 & LSI_SCNTL1_CON) {
1665 /* NetBSD 1.x checks for REQ */
1666 tmp = s->sstat2 & PHASE_MASK;
1667 /* if phase mismatch, REQ is also active */
1668 tmp |= s->sbcl;
1669 if (s->socl & LSI_SOCL_ATN)
1670 tmp |= LSI_SBCL_ATN;
1671 }
1672 return tmp;
1673 case 0xc: /* DSTAT */
1674 tmp = s->dstat | LSI_DSTAT_DFE;
1675 s->dstat = 0;
1676 // if ((s->istat0 & LSI_ISTAT0_INTF) == 0)
1677 // s->dstat = 0;
1678 lsi_update_irq(s);
1679 return tmp;
1680 case 0x0d: /* SSTAT0 */
1681 tmp = s->sstat0;
1682 s->sstat0 = 0;
1683 lsi_update_irq(s);
1684 return tmp;
1685 case 0x0e: /* SSTAT1 */
1686 return s->sstat1;
1687 case 0x0f: /* SSTAT2 */
1688 return s->sstat2;
1689 CASE_GET_REG32(dsa, 0x10)
1690 case 0x14: /* CTEST0 */
1691 return s->ctest0;
1692 case 0x15: /* CTEST1 */
1693 return 0xf0; // FMT and FFL are always empty
1694 case 0x16: /* CTEST2 */
1695 tmp = s->ctest2 | LSI_CTEST2_DACK;
1696 if (s->istat & LSI_ISTAT_SIGP) {
1697 s->istat &= ~LSI_ISTAT_SIGP;
1698 tmp |= LSI_CTEST2_SIGP;
1699 }
1700 return tmp;
1701 case 0x17: /* CTEST3 */
1702 return s->ctest3;
1703 case 0x18: /* CTEST4 */
1704 return s->ctest4;
1705 case 0x19: /* CTEST5 */
1706 return s->ctest5;
1707 case 0x1a: /* CTEST6 */
1708 return s->ctest6;
1709 case 0x1b: /* CTEST7 */
1710 return s->ctest7;
1711 CASE_GET_REG32(temp, 0x1c)
1712 case 0x20: /* DFIFO */
1713 return 0;
1714 case 0x21: /* ISTAT */
1715 return s->istat;
1716 case 0x22: /* CTEST8 */
1717 return (s->ctest8 | (2 << 4)) & ~0x08; // clear CLF
1718 case 0x23: /* LCRC */
1719 return s->lcrc;
1720 CASE_GET_REG24(dbc, 0x24)
1721 case 0x27: /* DCMD */
1722 return s->dcmd;
1723 CASE_GET_REG32(dnad, 0x28)
1724 CASE_GET_REG32(dsp, 0x2c)
1725 CASE_GET_REG32(dsps, 0x30)
1726 CASE_GET_REG32(scratch, 0x34)
1727 case 0x38: /* DMODE */
1728 return s->dmode;
1729 case 0x3a: /* DWT */
1730 return s->dwt;
1731 case 0x3b: /* DCNTL */
1732 return s->dcntl;
1733 }
1734 #undef CASE_GET_REG24
1735 #undef CASE_GET_REG32
1736 write_log ("read unknown register %02X\n", offset);
1737 return 0;
1738 }
lsi_reg_readb(LSIState710 * s,int offset)1739 static uint8_t lsi_reg_readb(LSIState710 *s, int offset)
1740 {
1741 uint8_t v = lsi_reg_readb2(s, offset);
1742 #ifdef DEBUG_LSI_REG
1743 DPRINTF("Read reg %x: %02X\n", offset, v);
1744 #endif
1745 return v;
1746 }
1747
lsi_reg_writeb(LSIState710 * s,int offset,uint8_t val)1748 static void lsi_reg_writeb(LSIState710 *s, int offset, uint8_t val)
1749 {
1750 #define CASE_SET_REG24(name, addr) \
1751 case addr : s->name &= 0xffffff00; s->name |= val; break; \
1752 case addr + 1: s->name &= 0xffff00ff; s->name |= val << 8; break; \
1753 case addr + 2: s->name &= 0xff00ffff; s->name |= val << 16; break;
1754
1755 #define CASE_SET_REG32(name, addr) \
1756 case addr : s->name &= 0xffffff00; s->name |= val; break; \
1757 case addr + 1: s->name &= 0xffff00ff; s->name |= val << 8; break; \
1758 case addr + 2: s->name &= 0xff00ffff; s->name |= val << 16; break; \
1759 case addr + 3: s->name &= 0x00ffffff; s->name |= val << 24; break;
1760
1761 #ifdef DEBUG_LSI_REG
1762 DPRINTF("Write reg %x = %02x\n", offset, val);
1763 #endif
1764 switch (offset) {
1765 case 0x00: /* SCNTL0 */
1766 s->scntl0 = val;
1767 if (val & LSI_SCNTL0_START) {
1768 BADF("Start sequence not implemented\n");
1769 }
1770 break;
1771 case 0x01: /* SCNTL1 */
1772 s->scntl1 = val;
1773 if (val & LSI_SCNTL1_ADB) {
1774 BADF("Immediate Arbritration not implemented\n");
1775 }
1776 if (val & LSI_SCNTL1_RST) {
1777 if (!(s->sstat0 & LSI_SSTAT0_RST)) {
1778 // qbus_reset_all(&s->bus.qbus);
1779 s->sstat0 |= LSI_SSTAT0_RST;
1780 lsi_script_scsi_interrupt(s, LSI_SSTAT0_RST);
1781 }
1782 } else {
1783 s->sstat0 &= ~LSI_SSTAT0_RST;
1784 }
1785 break;
1786 case 0x03: /* SIEN */
1787 s->sien0 = val;
1788 lsi_update_irq(s);
1789 break;
1790 case 0x04: /* SCID */
1791 s->scid = val;
1792 break;
1793 case 0x05: /* SXFER */
1794 s->sxfer = val;
1795 break;
1796 case 0x0b: /* SBCL */
1797 lsi_set_phase (s, val & PHASE_MASK);
1798 break;
1799 case 0x0c: case 0x0d: case 0x0e: case 0x0f:
1800 /* Linux writes to these readonly registers on startup. */
1801 return;
1802 CASE_SET_REG32(dsa, 0x10)
1803 case 0x14: /* CTEST0 */
1804 s->ctest0 = (val & 0xfe) | (s->ctest0 & 1);
1805 break;
1806 case 0x15: /* CTEST1, read-only */
1807 break;
1808 case 0x16: /* CTEST2, read-only */
1809 break;
1810 case 0x17: /* CTEST3 */
1811 s->ctest3 = val;
1812 break;
1813 case 0x18: /* CTEST4 */
1814 s->ctest4 = val;
1815 break;
1816 case 0x19: /* CTEST5 */
1817 s->ctest5 = val;
1818 break;
1819 case 0x1a: /* CTEST6 */
1820 s->ctest6 = val;
1821 break;
1822 case 0x1b: /* CTEST7 */
1823 s->ctest7 = val;
1824 break;
1825 CASE_SET_REG32(temp, 0x1c)
1826
1827 case 0x21: /* ISTAT */
1828 s->istat = (s->istat & 0x0f) | (val & 0xf0);
1829 if (val & LSI_ISTAT_ABRT) {
1830 lsi_script_dma_interrupt(s, LSI_DSTAT_ABRT);
1831 }
1832 if (s->waiting == 1 && (val & LSI_ISTAT_SIGP)) {
1833 DPRINTF("Woken by SIGP\n");
1834 s->waiting = 0;
1835 s->dsp = s->dnad;
1836 lsi_execute_script(s);
1837 }
1838 if (val & LSI_ISTAT_RST) {
1839 lsi_soft_reset(s);
1840 }
1841 break;
1842 case 0x22: /* CTEST8 */
1843 s->ctest8 = val;
1844 break;
1845 case 0x23: /* LCRC */
1846 s->lcrc = 0;
1847 break;
1848
1849 CASE_SET_REG24(dbc, 0x24)
1850 CASE_SET_REG32(dnad, 0x28)
1851 case 0x2c: /* DSP[0:7] */
1852 s->dsp &= 0xffffff00;
1853 s->dsp |= val;
1854 break;
1855 case 0x2d: /* DSP[8:15] */
1856 s->dsp &= 0xffff00ff;
1857 s->dsp |= val << 8;
1858 break;
1859 case 0x2e: /* DSP[16:23] */
1860 s->dsp &= 0xff00ffff;
1861 s->dsp |= val << 16;
1862 break;
1863 case 0x2f: /* DSP[24:31] */
1864 s->dsp &= 0x00ffffff;
1865 s->dsp |= val << 24;
1866 if ((s->dmode & LSI_DMODE_MAN) == 0) {
1867 s->waiting = 0;
1868 lsi_execute_script(s);
1869 }
1870 break;
1871 CASE_SET_REG32(scratch, 0x34)
1872 case 0x38: /* DMODE */
1873 #if 0
1874 if (val & (LSI_DMODE_SIOM | LSI_DMODE_DIOM)) {
1875 BADF("IO mappings not implemented\n");
1876 }
1877 #endif
1878 s->dmode = val;
1879 break;
1880 case 0x39: /* DIEN */
1881 s->dien = val;
1882 lsi_update_irq(s);
1883 break;
1884 case 0x3a: /* DWT */
1885 s->dwt = val;
1886 break;
1887 case 0x3b: /* DCNTL */
1888 s->dcntl = val & ~(LSI_DCNTL_PFF | LSI_DCNTL_STD);
1889 if ((val & LSI_DCNTL_STD) && (s->dmode & LSI_DMODE_MAN) != 0)
1890 lsi_execute_script(s);
1891 break;
1892 default:
1893 write_log ("write unknown register %02X\n", offset);
1894 break;
1895 }
1896 #undef CASE_SET_REG24
1897 #undef CASE_SET_REG32
1898 }
1899
1900 #if 0
1901 static void lsi_reg_writeb(LSIState710 *s, int offset, uint8_t val)
1902 {
1903 #define CASE_SET_REG24(name, addr) \
1904 case addr : s->name &= 0xffffff00; s->name |= val; break; \
1905 case addr + 1: s->name &= 0xffff00ff; s->name |= val << 8; break; \
1906 case addr + 2: s->name &= 0xff00ffff; s->name |= val << 16; break;
1907
1908 #define CASE_SET_REG32(name, addr) \
1909 case addr : s->name &= 0xffffff00; s->name |= val; break; \
1910 case addr + 1: s->name &= 0xffff00ff; s->name |= val << 8; break; \
1911 case addr + 2: s->name &= 0xff00ffff; s->name |= val << 16; break; \
1912 case addr + 3: s->name &= 0x00ffffff; s->name |= val << 24; break;
1913
1914 #ifdef DEBUG_LSI_REG
1915 DPRINTF("Write reg %x = %02x\n", offset, val);
1916 #endif
1917 switch (offset) {
1918 case 0x00: /* SCNTL0 */
1919 s->scntl0 = val;
1920 if (val & LSI_SCNTL0_START) {
1921 BADF("Start sequence not implemented\n");
1922 }
1923 break;
1924 case 0x01: /* SCNTL1 */
1925 s->scntl1 = val & ~LSI_SCNTL1_SST;
1926 if (val & LSI_SCNTL1_IARB) {
1927 BADF("Immediate Arbritration not implemented\n");
1928 }
1929 if (val & LSI_SCNTL1_RST) {
1930 if (!(s->sstat0 & LSI_SSTAT0_RST)) {
1931 // qbus_reset_all(&s->bus.qbus);
1932 s->sstat0 |= LSI_SSTAT0_RST;
1933 lsi_script_scsi_interrupt(s, LSI_SIST0_RST, 0);
1934 }
1935 } else {
1936 s->sstat0 &= ~LSI_SSTAT0_RST;
1937 }
1938 break;
1939 case 0x02: /* SCNTL2 */
1940 val &= ~(LSI_SCNTL2_WSR | LSI_SCNTL2_WSS);
1941 s->scntl2 = val;
1942 break;
1943 case 0x03: /* SCNTL3 */
1944 s->scntl3 = val;
1945 break;
1946 case 0x04: /* SCID */
1947 s->scid = val;
1948 break;
1949 case 0x05: /* SXFER */
1950 s->sxfer = val;
1951 break;
1952 case 0x06: /* SDID */
1953 if ((s->ssid & 0x80) && (val & 0xf) != (s->ssid & 0xf)) {
1954 BADF("Destination ID does not match SSID\n");
1955 }
1956 s->sdid = val & 0xf;
1957 break;
1958 case 0x07: /* GPREG0 */
1959 break;
1960 case 0x08: /* SFBR */
1961 /* The CPU is not allowed to write to this register. However the
1962 SCRIPTS register move instructions are. */
1963 s->sfbr = val;
1964 break;
1965 case 0x0a: case 0x0b:
1966 /* Openserver writes to these readonly registers on startup */
1967 return;
1968 case 0x0c: case 0x0d: case 0x0e: case 0x0f:
1969 /* Linux writes to these readonly registers on startup. */
1970 return;
1971 CASE_SET_REG32(dsa, 0x10)
1972 case 0x14: /* ISTAT0 */
1973 s->istat0 = (s->istat0 & 0x0f) | (val & 0xf0);
1974 if (val & LSI_ISTAT0_ABRT) {
1975 lsi_script_dma_interrupt(s, LSI_DSTAT_ABRT);
1976 }
1977 if (val & LSI_ISTAT0_INTF) {
1978 s->istat0 &= ~LSI_ISTAT0_INTF;
1979 lsi_update_irq(s);
1980 }
1981 if (s->waiting == 1 && val & LSI_ISTAT0_SIGP) {
1982 DPRINTF("Woken by SIGP\n");
1983 s->waiting = 0;
1984 s->dsp = s->dnad;
1985 lsi_execute_script(s);
1986 }
1987 // if (val & LSI_ISTAT0_SRST) {
1988 // qdev_reset_all(DEVICE(s));
1989 // }
1990 break;
1991 case 0x16: /* MBOX0 */
1992 s->mbox0 = val;
1993 break;
1994 case 0x17: /* MBOX1 */
1995 s->mbox1 = val;
1996 break;
1997 case 0x18: /* CTEST0 */
1998 /* nothing to do */
1999 break;
2000 case 0x1a: /* CTEST2 */
2001 s->ctest2 = val & LSI_CTEST2_PCICIE;
2002 break;
2003 case 0x1b: /* CTEST3 */
2004 s->ctest3 = val & 0x0f;
2005 break;
2006 CASE_SET_REG32(temp, 0x1c)
2007 case 0x21: /* CTEST4 */
2008 if (val & 7) {
2009 BADF("Unimplemented CTEST4-FBL 0x%x\n", val);
2010 }
2011 s->ctest4 = val;
2012 break;
2013 case 0x22: /* CTEST5 */
2014 if (val & (LSI_CTEST5_ADCK | LSI_CTEST5_BBCK)) {
2015 BADF("CTEST5 DMA increment not implemented\n");
2016 val &= ~(LSI_CTEST5_ADCK | LSI_CTEST5_BBCK);
2017 }
2018 s->ctest5 = val;
2019 break;
2020 CASE_SET_REG24(dbc, 0x24)
2021 CASE_SET_REG32(dnad, 0x28)
2022 case 0x2c: /* DSP[0:7] */
2023 s->dsp &= 0xffffff00;
2024 s->dsp |= val;
2025 break;
2026 case 0x2d: /* DSP[8:15] */
2027 s->dsp &= 0xffff00ff;
2028 s->dsp |= val << 8;
2029 break;
2030 case 0x2e: /* DSP[16:23] */
2031 s->dsp &= 0xff00ffff;
2032 s->dsp |= val << 16;
2033 break;
2034 case 0x2f: /* DSP[24:31] */
2035 s->dsp &= 0x00ffffff;
2036 s->dsp |= val << 24;
2037 if ((s->dmode & LSI_DMODE_MAN) == 0
2038 && (s->istat1 & LSI_ISTAT1_SRUN) == 0)
2039 lsi_execute_script(s);
2040 break;
2041 CASE_SET_REG32(dsps, 0x30)
2042 CASE_SET_REG32(scratch[0], 0x34)
2043 case 0x38: /* DMODE */
2044 if (val & (LSI_DMODE_SIOM | LSI_DMODE_DIOM)) {
2045 BADF("IO mappings not implemented\n");
2046 }
2047 s->dmode = val;
2048 break;
2049 case 0x39: /* DIEN */
2050 s->dien = val;
2051 lsi_update_irq(s);
2052 break;
2053 case 0x3a: /* SBR */
2054 s->sbr = val;
2055 break;
2056 case 0x3b: /* DCNTL */
2057 s->dcntl = val & ~(LSI_DCNTL_PFF | LSI_DCNTL_STD);
2058 if ((val & LSI_DCNTL_STD) && (s->istat1 & LSI_ISTAT1_SRUN) == 0)
2059 lsi_execute_script(s);
2060 break;
2061 case 0x40: /* SIEN0 */
2062 s->sien0 = val;
2063 lsi_update_irq(s);
2064 break;
2065 case 0x41: /* SIEN1 */
2066 s->sien1 = val;
2067 lsi_update_irq(s);
2068 break;
2069 case 0x47: /* GPCNTL0 */
2070 break;
2071 case 0x48: /* STIME0 */
2072 s->stime0 = val;
2073 break;
2074 case 0x49: /* STIME1 */
2075 if (val & 0xf) {
2076 DPRINTF("General purpose timer not implemented\n");
2077 /* ??? Raising the interrupt immediately seems to be sufficient
2078 to keep the FreeBSD driver happy. */
2079 lsi_script_scsi_interrupt(s, 0, LSI_SIST1_GEN);
2080 }
2081 break;
2082 case 0x4a: /* RESPID0 */
2083 s->respid0 = val;
2084 break;
2085 case 0x4b: /* RESPID1 */
2086 s->respid1 = val;
2087 break;
2088 case 0x4d: /* STEST1 */
2089 s->stest1 = val;
2090 break;
2091 case 0x4e: /* STEST2 */
2092 if (val & 1) {
2093 BADF("Low level mode not implemented\n");
2094 }
2095 s->stest2 = val;
2096 break;
2097 case 0x4f: /* STEST3 */
2098 if (val & 0x41) {
2099 BADF("SCSI FIFO test mode not implemented\n");
2100 }
2101 s->stest3 = val;
2102 break;
2103 case 0x56: /* CCNTL0 */
2104 s->ccntl0 = val;
2105 break;
2106 case 0x57: /* CCNTL1 */
2107 s->ccntl1 = val;
2108 break;
2109 CASE_SET_REG32(mmrs, 0xa0)
2110 CASE_SET_REG32(mmws, 0xa4)
2111 CASE_SET_REG32(sfs, 0xa8)
2112 CASE_SET_REG32(drs, 0xac)
2113 CASE_SET_REG32(sbms, 0xb0)
2114 CASE_SET_REG32(dbms, 0xb4)
2115 CASE_SET_REG32(dnad64, 0xb8)
2116 CASE_SET_REG32(pmjad1, 0xc0)
2117 CASE_SET_REG32(pmjad2, 0xc4)
2118 CASE_SET_REG32(rbc, 0xc8)
2119 CASE_SET_REG32(ua, 0xcc)
2120 CASE_SET_REG32(ia, 0xd4)
2121 CASE_SET_REG32(sbc, 0xd8)
2122 CASE_SET_REG32(csbc, 0xdc)
2123 default:
2124 if (offset >= 0x5c && offset < 0xa0) {
2125 int n;
2126 int shift;
2127 n = (offset - 0x58) >> 2;
2128 shift = (offset & 3) * 8;
2129 s->scratch[n] = deposit32(s->scratch[n], shift, 8, val);
2130 } else {
2131 BADF("Unhandled writeb 0x%x = 0x%x\n", offset, val);
2132 }
2133 }
2134 #undef CASE_SET_REG24
2135 #undef CASE_SET_REG32
2136 }
2137 #endif
2138
lsi710_mmio_write(void * opaque,hwaddr addr,uint64_t val,unsigned size)2139 void lsi710_mmio_write(void *opaque, hwaddr addr,
2140 uint64_t val, unsigned size)
2141 {
2142 LSIState710 *s = (LSIState710*)opaque;
2143
2144 lsi_reg_writeb(s, addr & 0xff, val);
2145 }
2146
lsi710_mmio_read(void * opaque,hwaddr addr,unsigned size)2147 uint64_t lsi710_mmio_read(void *opaque, hwaddr addr,
2148 unsigned size)
2149 {
2150 LSIState710 *s = (LSIState710*)opaque;
2151
2152 return lsi_reg_readb(s, addr & 0xff);
2153 }
2154
2155 #if 0
2156 static const MemoryRegionOps lsi_mmio_ops = {
2157 lsi_mmio_read,
2158 lsi_mmio_write,
2159 DEVICE_NATIVE_ENDIAN,
2160 {
2161 1,
2162 1,
2163 },
2164 };
2165
2166 static void lsi_ram_write(void *opaque, hwaddr addr,
2167 uint64_t val, unsigned size)
2168 {
2169 LSIState710 *s = (LSIState710*)opaque;
2170 uint32_t newval;
2171 uint32_t mask;
2172 int shift;
2173
2174 newval = s->script_ram[addr >> 2];
2175 shift = (addr & 3) * 8;
2176 mask = ((uint64_t)1 << (size * 8)) - 1;
2177 newval &= ~(mask << shift);
2178 newval |= val << shift;
2179 s->script_ram[addr >> 2] = newval;
2180 }
2181
2182 static uint64_t lsi_ram_read(void *opaque, hwaddr addr,
2183 unsigned size)
2184 {
2185 LSIState710 *s = (LSIState710*)opaque;
2186 uint32_t val;
2187 uint32_t mask;
2188
2189 val = s->script_ram[addr >> 2];
2190 mask = ((uint64_t)1 << (size * 8)) - 1;
2191 val >>= (addr & 3) * 8;
2192 return val & mask;
2193 }
2194
2195 static const MemoryRegionOps lsi_ram_ops = {
2196 lsi_ram_read,
2197 lsi_ram_write,
2198 DEVICE_NATIVE_ENDIAN,
2199 };
2200
2201 static uint64_t lsi_io_read(void *opaque, hwaddr addr,
2202 unsigned size)
2203 {
2204 LSIState710 *s = (LSIState710*)opaque;
2205 return lsi_reg_readb(s, addr & 0xff);
2206 }
2207
2208 static void lsi_io_write(void *opaque, hwaddr addr,
2209 uint64_t val, unsigned size)
2210 {
2211 LSIState710 *s = (LSIState710*)opaque;
2212 lsi_reg_writeb(s, addr & 0xff, val);
2213 }
2214
2215 static const MemoryRegionOps lsi_io_ops = {
2216 lsi_io_read,
2217 lsi_io_write,
2218 DEVICE_NATIVE_ENDIAN,
2219 {
2220 1,
2221 1,
2222 },
2223 };
2224 #endif
2225
lsi710_scsi_reset(DeviceState * dev,void * privdata)2226 void lsi710_scsi_reset(DeviceState *dev, void *privdata)
2227 {
2228 LSIState710 *s = LSI53C895A(dev);
2229
2230 memset (s, 0, sizeof(LSIState710));
2231 lsi_soft_reset(s);
2232 s->bus.privdata = privdata;
2233 }
2234
lsi710_scsi_init(DeviceState * dev)2235 void lsi710_scsi_init(DeviceState *dev)
2236 {
2237 dev->lsistate = calloc (sizeof(LSIState710), 1);
2238 }
2239
2240 #if 0
2241 static void lsi_pre_save(void *opaque)
2242 {
2243 LSIState710 *s = opaque;
2244
2245 if (s->current) {
2246 assert(s->current->dma_buf == NULL);
2247 assert(s->current->dma_len == 0);
2248 }
2249 assert(QTAILQ_EMPTY(&s->queue));
2250 }
2251
2252 static const VMStateDescription vmstate_lsi_scsi = {
2253 .name = "lsiscsi",
2254 .version_id = 0,
2255 .minimum_version_id = 0,
2256 .minimum_version_id_old = 0,
2257 .pre_save = lsi_pre_save,
2258 .fields = (VMStateField []) {
2259 VMSTATE_PCI_DEVICE(parent_obj, LSIState710),
2260
2261 VMSTATE_INT32(carry, LSIState710),
2262 VMSTATE_INT32(status, LSIState710),
2263 VMSTATE_INT32(msg_action, LSIState710),
2264 VMSTATE_INT32(msg_len, LSIState710),
2265 VMSTATE_BUFFER(msg, LSIState710),
2266 VMSTATE_INT32(waiting, LSIState710),
2267
2268 VMSTATE_UINT32(dsa, LSIState710),
2269 VMSTATE_UINT32(temp, LSIState710),
2270 VMSTATE_UINT32(dnad, LSIState710),
2271 VMSTATE_UINT32(dbc, LSIState710),
2272 VMSTATE_UINT8(istat0, LSIState710),
2273 VMSTATE_UINT8(istat1, LSIState710),
2274 VMSTATE_UINT8(dcmd, LSIState710),
2275 VMSTATE_UINT8(dstat, LSIState710),
2276 VMSTATE_UINT8(dien, LSIState710),
2277 VMSTATE_UINT8(sist0, LSIState710),
2278 VMSTATE_UINT8(sist1, LSIState710),
2279 VMSTATE_UINT8(sien0, LSIState710),
2280 VMSTATE_UINT8(sien1, LSIState710),
2281 VMSTATE_UINT8(mbox0, LSIState710),
2282 VMSTATE_UINT8(mbox1, LSIState710),
2283 VMSTATE_UINT8(dfifo, LSIState710),
2284 VMSTATE_UINT8(ctest2, LSIState710),
2285 VMSTATE_UINT8(ctest3, LSIState710),
2286 VMSTATE_UINT8(ctest4, LSIState710),
2287 VMSTATE_UINT8(ctest5, LSIState710),
2288 VMSTATE_UINT8(ccntl0, LSIState710),
2289 VMSTATE_UINT8(ccntl1, LSIState710),
2290 VMSTATE_UINT32(dsp, LSIState710),
2291 VMSTATE_UINT32(dsps, LSIState710),
2292 VMSTATE_UINT8(dmode, LSIState710),
2293 VMSTATE_UINT8(dcntl, LSIState710),
2294 VMSTATE_UINT8(scntl0, LSIState710),
2295 VMSTATE_UINT8(scntl1, LSIState710),
2296 VMSTATE_UINT8(scntl2, LSIState710),
2297 VMSTATE_UINT8(scntl3, LSIState710),
2298 VMSTATE_UINT8(sstat0, LSIState710),
2299 VMSTATE_UINT8(sstat1, LSIState710),
2300 VMSTATE_UINT8(scid, LSIState710),
2301 VMSTATE_UINT8(sxfer, LSIState710),
2302 VMSTATE_UINT8(socl, LSIState710),
2303 VMSTATE_UINT8(sdid, LSIState710),
2304 VMSTATE_UINT8(ssid, LSIState710),
2305 VMSTATE_UINT8(sfbr, LSIState710),
2306 VMSTATE_UINT8(stest1, LSIState710),
2307 VMSTATE_UINT8(stest2, LSIState710),
2308 VMSTATE_UINT8(stest3, LSIState710),
2309 VMSTATE_UINT8(sidl, LSIState710),
2310 VMSTATE_UINT8(stime0, LSIState710),
2311 VMSTATE_UINT8(respid0, LSIState710),
2312 VMSTATE_UINT8(respid1, LSIState710),
2313 VMSTATE_UINT32(mmrs, LSIState710),
2314 VMSTATE_UINT32(mmws, LSIState710),
2315 VMSTATE_UINT32(sfs, LSIState710),
2316 VMSTATE_UINT32(drs, LSIState710),
2317 VMSTATE_UINT32(sbms, LSIState710),
2318 VMSTATE_UINT32(dbms, LSIState710),
2319 VMSTATE_UINT32(dnad64, LSIState710),
2320 VMSTATE_UINT32(pmjad1, LSIState710),
2321 VMSTATE_UINT32(pmjad2, LSIState710),
2322 VMSTATE_UINT32(rbc, LSIState710),
2323 VMSTATE_UINT32(ua, LSIState710),
2324 VMSTATE_UINT32(ia, LSIState710),
2325 VMSTATE_UINT32(sbc, LSIState710),
2326 VMSTATE_UINT32(csbc, LSIState710),
2327 VMSTATE_BUFFER_UNSAFE(scratch, LSIState710, 0, 18 * sizeof(uint32_t)),
2328 VMSTATE_UINT8(sbr, LSIState710),
2329
2330 VMSTATE_BUFFER_UNSAFE(script_ram, LSIState710, 0, 2048 * sizeof(uint32_t)),
2331 VMSTATE_END_OF_LIST()
2332 }
2333 };
2334
2335 static void lsi_scsi_uninit(PCIDevice *d)
2336 {
2337 LSIState710 *s = LSI53C895A(d);
2338
2339 memory_region_destroy(&s->mmio_io);
2340 memory_region_destroy(&s->ram_io);
2341 memory_region_destroy(&s->io_io);
2342 }
2343
2344 static const struct SCSIBusInfo lsi_scsi_info = {
2345 .tcq = true,
2346 .max_target = LSI_MAX_DEVS,
2347 .max_lun = 0, /* LUN support is buggy */
2348
2349 .transfer_data = lsi710_transfer_data,
2350 .complete = lsi710_command_complete,
2351 .cancel = lsi710_request_cancelled
2352 };
2353
2354 static int lsi_scsi_init(PCIDevice *dev)
2355 {
2356 LSIState710 *s = LSI53C895A(dev);
2357 DeviceState *d = DEVICE(dev);
2358 uint8_t *pci_conf;
2359 Error *err = NULL;
2360
2361 pci_conf = dev->config;
2362
2363 /* PCI latency timer = 255 */
2364 pci_conf[PCI_LATENCY_TIMER] = 0xff;
2365 /* Interrupt pin A */
2366 pci_conf[PCI_INTERRUPT_PIN] = 0x01;
2367
2368 memory_region_init_io(&s->mmio_io, OBJECT(s), &lsi_mmio_ops, s,
2369 "lsi-mmio", 0x400);
2370 memory_region_init_io(&s->ram_io, OBJECT(s), &lsi_ram_ops, s,
2371 "lsi-ram", 0x2000);
2372 memory_region_init_io(&s->io_io, OBJECT(s), &lsi_io_ops, s,
2373 "lsi-io", 256);
2374
2375 pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->io_io);
2376 pci_register_bar(dev, 1, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->mmio_io);
2377 pci_register_bar(dev, 2, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->ram_io);
2378 QTAILQ_INIT(&s->queue);
2379
2380 scsi_bus_new(&s->bus, sizeof(s->bus), d, &lsi_scsi_info, NULL);
2381 if (!d->hotplugged) {
2382 scsi_bus_legacy_handle_cmdline(&s->bus, &err);
2383 if (err != NULL) {
2384 error_free(err);
2385 return -1;
2386 }
2387 }
2388 return 0;
2389 }
2390
2391 static void lsi_class_init(ObjectClass *klass, void *data)
2392 {
2393 DeviceClass *dc = DEVICE_CLASS(klass);
2394 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
2395
2396 k->init = lsi_scsi_init;
2397 k->exit = lsi_scsi_uninit;
2398 k->vendor_id = PCI_VENDOR_ID_LSI_LOGIC;
2399 k->device_id = PCI_DEVICE_ID_LSI_53C895A;
2400 k->class_id = PCI_CLASS_STORAGE_SCSI;
2401 k->subsystem_id = 0x1000;
2402 dc->reset = lsi_scsi_reset;
2403 dc->vmsd = &vmstate_lsi_scsi;
2404 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
2405 }
2406
2407 static const TypeInfo lsi_info = {
2408 .name = TYPE_LSI53C895A,
2409 .parent = TYPE_PCI_DEVICE,
2410 .instance_size = sizeof(LSIState710),
2411 .class_init = lsi_class_init,
2412 };
2413
2414 static void lsi53c810_class_init(ObjectClass *klass, void *data)
2415 {
2416 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
2417
2418 k->device_id = PCI_DEVICE_ID_LSI_53C810;
2419 }
2420
2421 static TypeInfo lsi53c810_info = {
2422 .name = TYPE_LSI53C810,
2423 .parent = TYPE_LSI53C895A,
2424 .class_init = lsi53c810_class_init,
2425 };
2426
2427 static void lsi53c895a_register_types(void)
2428 {
2429 type_register_static(&lsi_info);
2430 type_register_static(&lsi53c810_info);
2431 }
2432
2433 type_init(lsi53c895a_register_types)
2434 #endif
2435